include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90 };
  91
  92 enum {
  93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  94         MLX5_OBJ_TYPE_MKEY = 0xff01,
  95         MLX5_OBJ_TYPE_QP = 0xff02,
  96         MLX5_OBJ_TYPE_PSV = 0xff03,
  97         MLX5_OBJ_TYPE_RMP = 0xff04,
  98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  99         MLX5_OBJ_TYPE_RQ = 0xff06,
 100         MLX5_OBJ_TYPE_SQ = 0xff07,
 101         MLX5_OBJ_TYPE_TIR = 0xff08,
 102         MLX5_OBJ_TYPE_TIS = 0xff09,
 103         MLX5_OBJ_TYPE_DCT = 0xff0a,
 104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 105         MLX5_OBJ_TYPE_RQT = 0xff0e,
 106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 107         MLX5_OBJ_TYPE_CQ = 0xff10,
 108 };
 109
 110 enum {
 111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 175         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 176         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 177         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 178         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 179         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 180         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 181         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 182         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 183         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 184         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 185         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 186         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 188         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 189         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 190         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 191         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 192         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 193         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 194         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 195         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 196         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 197         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 198         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 199         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 200         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 201         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 202         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 203         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 204         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 205         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 206         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 207         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 208         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 209         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 210         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 211         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 212         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 213         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 214         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 215         MLX5_CMD_OP_NOP                           = 0x80d,
 216         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 217         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 218         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 219         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 220         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 221         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 222         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 223         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 224         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 225         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 226         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 227         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 228         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 229         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 230         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 231         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 232         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 233         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 234         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 235         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 236         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 237         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 238         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 239         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 240         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 241         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 242         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 243         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 244         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 245         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 246         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 247         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 248         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 249         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 250         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 251         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 252         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 253         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 254         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 255         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 256         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 257         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 258         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 259         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 260         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 261         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 262         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 263         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 264         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 265         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 266         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 267         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 268         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 269         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 270         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 271         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 272         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 273         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 274         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 275         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 276         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 277         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 278         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 279         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 280         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 281         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 282         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 283         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 284         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 285         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 286         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 287         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 288         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 289         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 290         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 291         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 292         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 293         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 294         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 295         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 296         MLX5_CMD_OP_MAX
 297 };
 298
 299 /* Valid range for general commands that don't work over an object */
 300 enum {
 301         MLX5_CMD_OP_GENERAL_START = 0xb00,
 302         MLX5_CMD_OP_GENERAL_END = 0xd00,
 303 };
 304
 305 struct mlx5_ifc_flow_table_fields_supported_bits {
 306         u8         outer_dmac[0x1];
 307         u8         outer_smac[0x1];
 308         u8         outer_ether_type[0x1];
 309         u8         outer_ip_version[0x1];
 310         u8         outer_first_prio[0x1];
 311         u8         outer_first_cfi[0x1];
 312         u8         outer_first_vid[0x1];
 313         u8         outer_ipv4_ttl[0x1];
 314         u8         outer_second_prio[0x1];
 315         u8         outer_second_cfi[0x1];
 316         u8         outer_second_vid[0x1];
 317         u8         reserved_at_b[0x1];
 318         u8         outer_sip[0x1];
 319         u8         outer_dip[0x1];
 320         u8         outer_frag[0x1];
 321         u8         outer_ip_protocol[0x1];
 322         u8         outer_ip_ecn[0x1];
 323         u8         outer_ip_dscp[0x1];
 324         u8         outer_udp_sport[0x1];
 325         u8         outer_udp_dport[0x1];
 326         u8         outer_tcp_sport[0x1];
 327         u8         outer_tcp_dport[0x1];
 328         u8         outer_tcp_flags[0x1];
 329         u8         outer_gre_protocol[0x1];
 330         u8         outer_gre_key[0x1];
 331         u8         outer_vxlan_vni[0x1];
 332         u8         outer_geneve_vni[0x1];
 333         u8         outer_geneve_oam[0x1];
 334         u8         outer_geneve_protocol_type[0x1];
 335         u8         outer_geneve_opt_len[0x1];
 336         u8         reserved_at_1e[0x1];
 337         u8         source_eswitch_port[0x1];
 338
 339         u8         inner_dmac[0x1];
 340         u8         inner_smac[0x1];
 341         u8         inner_ether_type[0x1];
 342         u8         inner_ip_version[0x1];
 343         u8         inner_first_prio[0x1];
 344         u8         inner_first_cfi[0x1];
 345         u8         inner_first_vid[0x1];
 346         u8         reserved_at_27[0x1];
 347         u8         inner_second_prio[0x1];
 348         u8         inner_second_cfi[0x1];
 349         u8         inner_second_vid[0x1];
 350         u8         reserved_at_2b[0x1];
 351         u8         inner_sip[0x1];
 352         u8         inner_dip[0x1];
 353         u8         inner_frag[0x1];
 354         u8         inner_ip_protocol[0x1];
 355         u8         inner_ip_ecn[0x1];
 356         u8         inner_ip_dscp[0x1];
 357         u8         inner_udp_sport[0x1];
 358         u8         inner_udp_dport[0x1];
 359         u8         inner_tcp_sport[0x1];
 360         u8         inner_tcp_dport[0x1];
 361         u8         inner_tcp_flags[0x1];
 362         u8         reserved_at_37[0x9];
 363
 364         u8         geneve_tlv_option_0_data[0x1];
 365         u8         reserved_at_41[0x4];
 366         u8         outer_first_mpls_over_udp[0x4];
 367         u8         outer_first_mpls_over_gre[0x4];
 368         u8         inner_first_mpls[0x4];
 369         u8         outer_first_mpls[0x4];
 370         u8         reserved_at_55[0x2];
 371         u8         outer_esp_spi[0x1];
 372         u8         reserved_at_58[0x2];
 373         u8         bth_dst_qp[0x1];
 374
 375         u8         reserved_at_5b[0x25];
 376 };
 377
 378 struct mlx5_ifc_flow_table_prop_layout_bits {
 379         u8         ft_support[0x1];
 380         u8         reserved_at_1[0x1];
 381         u8         flow_counter[0x1];
 382         u8         flow_modify_en[0x1];
 383         u8         modify_root[0x1];
 384         u8         identified_miss_table_mode[0x1];
 385         u8         flow_table_modify[0x1];
 386         u8         reformat[0x1];
 387         u8         decap[0x1];
 388         u8         reserved_at_9[0x1];
 389         u8         pop_vlan[0x1];
 390         u8         push_vlan[0x1];
 391         u8         reserved_at_c[0x1];
 392         u8         pop_vlan_2[0x1];
 393         u8         push_vlan_2[0x1];
 394         u8         reformat_and_vlan_action[0x1];
 395         u8         reserved_at_10[0x1];
 396         u8         sw_owner[0x1];
 397         u8         reformat_l3_tunnel_to_l2[0x1];
 398         u8         reformat_l2_to_l3_tunnel[0x1];
 399         u8         reformat_and_modify_action[0x1];
 400         u8         reserved_at_15[0x2];
 401         u8         table_miss_action_domain[0x1];
 402         u8         termination_table[0x1];
 403         u8         reserved_at_19[0x7];
 404         u8         reserved_at_20[0x2];
 405         u8         log_max_ft_size[0x6];
 406         u8         log_max_modify_header_context[0x8];
 407         u8         max_modify_header_actions[0x8];
 408         u8         max_ft_level[0x8];
 409
 410         u8         reserved_at_40[0x20];
 411
 412         u8         reserved_at_60[0x18];
 413         u8         log_max_ft_num[0x8];
 414
 415         u8         reserved_at_80[0x18];
 416         u8         log_max_destination[0x8];
 417
 418         u8         log_max_flow_counter[0x8];
 419         u8         reserved_at_a8[0x10];
 420         u8         log_max_flow[0x8];
 421
 422         u8         reserved_at_c0[0x40];
 423
 424         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 425
 426         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 427 };
 428
 429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 430         u8         send[0x1];
 431         u8         receive[0x1];
 432         u8         write[0x1];
 433         u8         read[0x1];
 434         u8         atomic[0x1];
 435         u8         srq_receive[0x1];
 436         u8         reserved_at_6[0x1a];
 437 };
 438
 439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 440         u8         smac_47_16[0x20];
 441
 442         u8         smac_15_0[0x10];
 443         u8         ethertype[0x10];
 444
 445         u8         dmac_47_16[0x20];
 446
 447         u8         dmac_15_0[0x10];
 448         u8         first_prio[0x3];
 449         u8         first_cfi[0x1];
 450         u8         first_vid[0xc];
 451
 452         u8         ip_protocol[0x8];
 453         u8         ip_dscp[0x6];
 454         u8         ip_ecn[0x2];
 455         u8         cvlan_tag[0x1];
 456         u8         svlan_tag[0x1];
 457         u8         frag[0x1];
 458         u8         ip_version[0x4];
 459         u8         tcp_flags[0x9];
 460
 461         u8         tcp_sport[0x10];
 462         u8         tcp_dport[0x10];
 463
 464         u8         reserved_at_c0[0x18];
 465         u8         ttl_hoplimit[0x8];
 466
 467         u8         udp_sport[0x10];
 468         u8         udp_dport[0x10];
 469
 470         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 471
 472         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 473 };
 474
 475 struct mlx5_ifc_nvgre_key_bits {
 476         u8 hi[0x18];
 477         u8 lo[0x8];
 478 };
 479
 480 union mlx5_ifc_gre_key_bits {
 481         struct mlx5_ifc_nvgre_key_bits nvgre;
 482         u8 key[0x20];
 483 };
 484
 485 struct mlx5_ifc_fte_match_set_misc_bits {
 486         u8         reserved_at_0[0x8];
 487         u8         source_sqn[0x18];
 488
 489         u8         source_eswitch_owner_vhca_id[0x10];
 490         u8         source_port[0x10];
 491
 492         u8         outer_second_prio[0x3];
 493         u8         outer_second_cfi[0x1];
 494         u8         outer_second_vid[0xc];
 495         u8         inner_second_prio[0x3];
 496         u8         inner_second_cfi[0x1];
 497         u8         inner_second_vid[0xc];
 498
 499         u8         outer_second_cvlan_tag[0x1];
 500         u8         inner_second_cvlan_tag[0x1];
 501         u8         outer_second_svlan_tag[0x1];
 502         u8         inner_second_svlan_tag[0x1];
 503         u8         reserved_at_64[0xc];
 504         u8         gre_protocol[0x10];
 505
 506         union mlx5_ifc_gre_key_bits gre_key;
 507
 508         u8         vxlan_vni[0x18];
 509         u8         reserved_at_b8[0x8];
 510
 511         u8         geneve_vni[0x18];
 512         u8         reserved_at_d8[0x7];
 513         u8         geneve_oam[0x1];
 514
 515         u8         reserved_at_e0[0xc];
 516         u8         outer_ipv6_flow_label[0x14];
 517
 518         u8         reserved_at_100[0xc];
 519         u8         inner_ipv6_flow_label[0x14];
 520
 521         u8         reserved_at_120[0xa];
 522         u8         geneve_opt_len[0x6];
 523         u8         geneve_protocol_type[0x10];
 524
 525         u8         reserved_at_140[0x8];
 526         u8         bth_dst_qp[0x18];
 527         u8         reserved_at_160[0x20];
 528         u8         outer_esp_spi[0x20];
 529         u8         reserved_at_1a0[0x60];
 530 };
 531
 532 struct mlx5_ifc_fte_match_mpls_bits {
 533         u8         mpls_label[0x14];
 534         u8         mpls_exp[0x3];
 535         u8         mpls_s_bos[0x1];
 536         u8         mpls_ttl[0x8];
 537 };
 538
 539 struct mlx5_ifc_fte_match_set_misc2_bits {
 540         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 541
 542         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 543
 544         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 545
 546         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 547
 548         u8         metadata_reg_c_7[0x20];
 549
 550         u8         metadata_reg_c_6[0x20];
 551
 552         u8         metadata_reg_c_5[0x20];
 553
 554         u8         metadata_reg_c_4[0x20];
 555
 556         u8         metadata_reg_c_3[0x20];
 557
 558         u8         metadata_reg_c_2[0x20];
 559
 560         u8         metadata_reg_c_1[0x20];
 561
 562         u8         metadata_reg_c_0[0x20];
 563
 564         u8         metadata_reg_a[0x20];
 565
 566         u8         reserved_at_1a0[0x60];
 567 };
 568
 569 struct mlx5_ifc_fte_match_set_misc3_bits {
 570         u8         reserved_at_0[0x120];
 571         u8         geneve_tlv_option_0_data[0x20];
 572         u8         reserved_at_140[0xc0];
 573 };
 574
 575 struct mlx5_ifc_cmd_pas_bits {
 576         u8         pa_h[0x20];
 577
 578         u8         pa_l[0x14];
 579         u8         reserved_at_34[0xc];
 580 };
 581
 582 struct mlx5_ifc_uint64_bits {
 583         u8         hi[0x20];
 584
 585         u8         lo[0x20];
 586 };
 587
 588 enum {
 589         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 590         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 591         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 592         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 593         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 594         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 595         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 596         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 597         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 598         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 599 };
 600
 601 struct mlx5_ifc_ads_bits {
 602         u8         fl[0x1];
 603         u8         free_ar[0x1];
 604         u8         reserved_at_2[0xe];
 605         u8         pkey_index[0x10];
 606
 607         u8         reserved_at_20[0x8];
 608         u8         grh[0x1];
 609         u8         mlid[0x7];
 610         u8         rlid[0x10];
 611
 612         u8         ack_timeout[0x5];
 613         u8         reserved_at_45[0x3];
 614         u8         src_addr_index[0x8];
 615         u8         reserved_at_50[0x4];
 616         u8         stat_rate[0x4];
 617         u8         hop_limit[0x8];
 618
 619         u8         reserved_at_60[0x4];
 620         u8         tclass[0x8];
 621         u8         flow_label[0x14];
 622
 623         u8         rgid_rip[16][0x8];
 624
 625         u8         reserved_at_100[0x4];
 626         u8         f_dscp[0x1];
 627         u8         f_ecn[0x1];
 628         u8         reserved_at_106[0x1];
 629         u8         f_eth_prio[0x1];
 630         u8         ecn[0x2];
 631         u8         dscp[0x6];
 632         u8         udp_sport[0x10];
 633
 634         u8         dei_cfi[0x1];
 635         u8         eth_prio[0x3];
 636         u8         sl[0x4];
 637         u8         vhca_port_num[0x8];
 638         u8         rmac_47_32[0x10];
 639
 640         u8         rmac_31_0[0x20];
 641 };
 642
 643 struct mlx5_ifc_flow_table_nic_cap_bits {
 644         u8         nic_rx_multi_path_tirs[0x1];
 645         u8         nic_rx_multi_path_tirs_fts[0x1];
 646         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 647         u8         reserved_at_3[0x1d];
 648         u8         encap_general_header[0x1];
 649         u8         reserved_at_21[0xa];
 650         u8         log_max_packet_reformat_context[0x5];
 651         u8         reserved_at_30[0x6];
 652         u8         max_encap_header_size[0xa];
 653         u8         reserved_at_40[0x1c0];
 654
 655         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 656
 657         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 658
 659         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 660
 661         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 662
 663         u8         reserved_at_a00[0x200];
 664
 665         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 666
 667         u8         reserved_at_e00[0x7200];
 668 };
 669
 670 enum {
 671         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 672         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 673         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 674         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 675         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 676         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 677         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 678         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 679 };
 680
 681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 682         u8      fdb_to_vport_reg_c_id[0x8];
 683         u8      reserved_at_8[0xf];
 684         u8      flow_source[0x1];
 685         u8      reserved_at_18[0x2];
 686         u8      multi_fdb_encap[0x1];
 687         u8      reserved_at_1b[0x1];
 688         u8      fdb_multi_path_to_table[0x1];
 689         u8      reserved_at_1d[0x3];
 690
 691         u8      reserved_at_20[0x1e0];
 692
 693         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 694
 695         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 696
 697         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 698
 699         u8      reserved_at_800[0x7800];
 700 };
 701
 702 enum {
 703         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 704         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 705 };
 706
 707 struct mlx5_ifc_e_switch_cap_bits {
 708         u8         vport_svlan_strip[0x1];
 709         u8         vport_cvlan_strip[0x1];
 710         u8         vport_svlan_insert[0x1];
 711         u8         vport_cvlan_insert_if_not_exist[0x1];
 712         u8         vport_cvlan_insert_overwrite[0x1];
 713         u8         reserved_at_5[0x3];
 714         u8         esw_uplink_ingress_acl[0x1];
 715         u8         reserved_at_9[0x10];
 716         u8         esw_functions_changed[0x1];
 717         u8         reserved_at_1a[0x1];
 718         u8         ecpf_vport_exists[0x1];
 719         u8         counter_eswitch_affinity[0x1];
 720         u8         merged_eswitch[0x1];
 721         u8         nic_vport_node_guid_modify[0x1];
 722         u8         nic_vport_port_guid_modify[0x1];
 723
 724         u8         vxlan_encap_decap[0x1];
 725         u8         nvgre_encap_decap[0x1];
 726         u8         reserved_at_22[0x1];
 727         u8         log_max_fdb_encap_uplink[0x5];
 728         u8         reserved_at_21[0x3];
 729         u8         log_max_packet_reformat_context[0x5];
 730         u8         reserved_2b[0x6];
 731         u8         max_encap_header_size[0xa];
 732
 733         u8         reserved_at_40[0xb];
 734         u8         log_max_esw_sf[0x5];
 735         u8         esw_sf_base_id[0x10];
 736
 737         u8         reserved_at_60[0x7a0];
 738
 739 };
 740
 741 struct mlx5_ifc_qos_cap_bits {
 742         u8         packet_pacing[0x1];
 743         u8         esw_scheduling[0x1];
 744         u8         esw_bw_share[0x1];
 745         u8         esw_rate_limit[0x1];
 746         u8         reserved_at_4[0x1];
 747         u8         packet_pacing_burst_bound[0x1];
 748         u8         packet_pacing_typical_size[0x1];
 749         u8         reserved_at_7[0x19];
 750
 751         u8         reserved_at_20[0x20];
 752
 753         u8         packet_pacing_max_rate[0x20];
 754
 755         u8         packet_pacing_min_rate[0x20];
 756
 757         u8         reserved_at_80[0x10];
 758         u8         packet_pacing_rate_table_size[0x10];
 759
 760         u8         esw_element_type[0x10];
 761         u8         esw_tsar_type[0x10];
 762
 763         u8         reserved_at_c0[0x10];
 764         u8         max_qos_para_vport[0x10];
 765
 766         u8         max_tsar_bw_share[0x20];
 767
 768         u8         reserved_at_100[0x700];
 769 };
 770
 771 struct mlx5_ifc_debug_cap_bits {
 772         u8         core_dump_general[0x1];
 773         u8         core_dump_qp[0x1];
 774         u8         reserved_at_2[0x1e];
 775
 776         u8         reserved_at_20[0x2];
 777         u8         stall_detect[0x1];
 778         u8         reserved_at_23[0x1d];
 779
 780         u8         reserved_at_40[0x7c0];
 781 };
 782
 783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 784         u8         csum_cap[0x1];
 785         u8         vlan_cap[0x1];
 786         u8         lro_cap[0x1];
 787         u8         lro_psh_flag[0x1];
 788         u8         lro_time_stamp[0x1];
 789         u8         reserved_at_5[0x2];
 790         u8         wqe_vlan_insert[0x1];
 791         u8         self_lb_en_modifiable[0x1];
 792         u8         reserved_at_9[0x2];
 793         u8         max_lso_cap[0x5];
 794         u8         multi_pkt_send_wqe[0x2];
 795         u8         wqe_inline_mode[0x2];
 796         u8         rss_ind_tbl_cap[0x4];
 797         u8         reg_umr_sq[0x1];
 798         u8         scatter_fcs[0x1];
 799         u8         enhanced_multi_pkt_send_wqe[0x1];
 800         u8         tunnel_lso_const_out_ip_id[0x1];
 801         u8         reserved_at_1c[0x2];
 802         u8         tunnel_stateless_gre[0x1];
 803         u8         tunnel_stateless_vxlan[0x1];
 804
 805         u8         swp[0x1];
 806         u8         swp_csum[0x1];
 807         u8         swp_lso[0x1];
 808         u8         reserved_at_23[0xd];
 809         u8         max_vxlan_udp_ports[0x8];
 810         u8         reserved_at_38[0x6];
 811         u8         max_geneve_opt_len[0x1];
 812         u8         tunnel_stateless_geneve_rx[0x1];
 813
 814         u8         reserved_at_40[0x10];
 815         u8         lro_min_mss_size[0x10];
 816
 817         u8         reserved_at_60[0x120];
 818
 819         u8         lro_timer_supported_periods[4][0x20];
 820
 821         u8         reserved_at_200[0x600];
 822 };
 823
 824 struct mlx5_ifc_roce_cap_bits {
 825         u8         roce_apm[0x1];
 826         u8         reserved_at_1[0x1f];
 827
 828         u8         reserved_at_20[0x60];
 829
 830         u8         reserved_at_80[0xc];
 831         u8         l3_type[0x4];
 832         u8         reserved_at_90[0x8];
 833         u8         roce_version[0x8];
 834
 835         u8         reserved_at_a0[0x10];
 836         u8         r_roce_dest_udp_port[0x10];
 837
 838         u8         r_roce_max_src_udp_port[0x10];
 839         u8         r_roce_min_src_udp_port[0x10];
 840
 841         u8         reserved_at_e0[0x10];
 842         u8         roce_address_table_size[0x10];
 843
 844         u8         reserved_at_100[0x700];
 845 };
 846
 847 struct mlx5_ifc_device_mem_cap_bits {
 848         u8         memic[0x1];
 849         u8         reserved_at_1[0x1f];
 850
 851         u8         reserved_at_20[0xb];
 852         u8         log_min_memic_alloc_size[0x5];
 853         u8         reserved_at_30[0x8];
 854         u8         log_max_memic_addr_alignment[0x8];
 855
 856         u8         memic_bar_start_addr[0x40];
 857
 858         u8         memic_bar_size[0x20];
 859
 860         u8         max_memic_size[0x20];
 861
 862         u8         steering_sw_icm_start_address[0x40];
 863
 864         u8         reserved_at_100[0x8];
 865         u8         log_header_modify_sw_icm_size[0x8];
 866         u8         reserved_at_110[0x2];
 867         u8         log_sw_icm_alloc_granularity[0x6];
 868         u8         log_steering_sw_icm_size[0x8];
 869
 870         u8         reserved_at_120[0x20];
 871
 872         u8         header_modify_sw_icm_start_address[0x40];
 873
 874         u8         reserved_at_180[0x680];
 875 };
 876
 877 struct mlx5_ifc_device_event_cap_bits {
 878         u8         user_affiliated_events[4][0x40];
 879
 880         u8         user_unaffiliated_events[4][0x40];
 881 };
 882
 883 enum {
 884         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 885         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 886         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 887         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 888         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 889         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 890         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 891         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 892         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 893 };
 894
 895 enum {
 896         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 897         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 898         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 899         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 900         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 901         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 902         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 903         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 904         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 905 };
 906
 907 struct mlx5_ifc_atomic_caps_bits {
 908         u8         reserved_at_0[0x40];
 909
 910         u8         atomic_req_8B_endianness_mode[0x2];
 911         u8         reserved_at_42[0x4];
 912         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 913
 914         u8         reserved_at_47[0x19];
 915
 916         u8         reserved_at_60[0x20];
 917
 918         u8         reserved_at_80[0x10];
 919         u8         atomic_operations[0x10];
 920
 921         u8         reserved_at_a0[0x10];
 922         u8         atomic_size_qp[0x10];
 923
 924         u8         reserved_at_c0[0x10];
 925         u8         atomic_size_dc[0x10];
 926
 927         u8         reserved_at_e0[0x720];
 928 };
 929
 930 struct mlx5_ifc_odp_cap_bits {
 931         u8         reserved_at_0[0x40];
 932
 933         u8         sig[0x1];
 934         u8         reserved_at_41[0x1f];
 935
 936         u8         reserved_at_60[0x20];
 937
 938         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 939
 940         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 941
 942         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 943
 944         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 945
 946         u8         reserved_at_100[0x700];
 947 };
 948
 949 struct mlx5_ifc_calc_op {
 950         u8        reserved_at_0[0x10];
 951         u8        reserved_at_10[0x9];
 952         u8        op_swap_endianness[0x1];
 953         u8        op_min[0x1];
 954         u8        op_xor[0x1];
 955         u8        op_or[0x1];
 956         u8        op_and[0x1];
 957         u8        op_max[0x1];
 958         u8        op_add[0x1];
 959 };
 960
 961 struct mlx5_ifc_vector_calc_cap_bits {
 962         u8         calc_matrix[0x1];
 963         u8         reserved_at_1[0x1f];
 964         u8         reserved_at_20[0x8];
 965         u8         max_vec_count[0x8];
 966         u8         reserved_at_30[0xd];
 967         u8         max_chunk_size[0x3];
 968         struct mlx5_ifc_calc_op calc0;
 969         struct mlx5_ifc_calc_op calc1;
 970         struct mlx5_ifc_calc_op calc2;
 971         struct mlx5_ifc_calc_op calc3;
 972
 973         u8         reserved_at_c0[0x720];
 974 };
 975
 976 struct mlx5_ifc_tls_cap_bits {
 977         u8         tls_1_2_aes_gcm_128[0x1];
 978         u8         tls_1_3_aes_gcm_128[0x1];
 979         u8         tls_1_2_aes_gcm_256[0x1];
 980         u8         tls_1_3_aes_gcm_256[0x1];
 981         u8         reserved_at_4[0x1c];
 982
 983         u8         reserved_at_20[0x7e0];
 984 };
 985
 986 enum {
 987         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 988         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 989         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 990         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 991 };
 992
 993 enum {
 994         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 995         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 996 };
 997
 998 enum {
 999         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1000         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1001         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1002         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1003         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1004 };
1005
1006 enum {
1007         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1008         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1009         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1010         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1011         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1012         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1013 };
1014
1015 enum {
1016         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1017         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1018 };
1019
1020 enum {
1021         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1022         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1023         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1024 };
1025
1026 enum {
1027         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1028         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1029 };
1030
1031 enum {
1032         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1033         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1034         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1035 };
1036
1037 enum {
1038         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1039         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1040 };
1041
1042 struct mlx5_ifc_cmd_hca_cap_bits {
1043         u8         reserved_at_0[0x30];
1044         u8         vhca_id[0x10];
1045
1046         u8         reserved_at_40[0x40];
1047
1048         u8         log_max_srq_sz[0x8];
1049         u8         log_max_qp_sz[0x8];
1050         u8         event_cap[0x1];
1051         u8         reserved_at_91[0x7];
1052         u8         prio_tag_required[0x1];
1053         u8         reserved_at_99[0x2];
1054         u8         log_max_qp[0x5];
1055
1056         u8         reserved_at_a0[0xb];
1057         u8         log_max_srq[0x5];
1058         u8         reserved_at_b0[0x10];
1059
1060         u8         reserved_at_c0[0x8];
1061         u8         log_max_cq_sz[0x8];
1062         u8         reserved_at_d0[0xb];
1063         u8         log_max_cq[0x5];
1064
1065         u8         log_max_eq_sz[0x8];
1066         u8         reserved_at_e8[0x2];
1067         u8         log_max_mkey[0x6];
1068         u8         reserved_at_f0[0x8];
1069         u8         dump_fill_mkey[0x1];
1070         u8         reserved_at_f9[0x2];
1071         u8         fast_teardown[0x1];
1072         u8         log_max_eq[0x4];
1073
1074         u8         max_indirection[0x8];
1075         u8         fixed_buffer_size[0x1];
1076         u8         log_max_mrw_sz[0x7];
1077         u8         force_teardown[0x1];
1078         u8         reserved_at_111[0x1];
1079         u8         log_max_bsf_list_size[0x6];
1080         u8         umr_extended_translation_offset[0x1];
1081         u8         null_mkey[0x1];
1082         u8         log_max_klm_list_size[0x6];
1083
1084         u8         reserved_at_120[0xa];
1085         u8         log_max_ra_req_dc[0x6];
1086         u8         reserved_at_130[0xa];
1087         u8         log_max_ra_res_dc[0x6];
1088
1089         u8         reserved_at_140[0xa];
1090         u8         log_max_ra_req_qp[0x6];
1091         u8         reserved_at_150[0xa];
1092         u8         log_max_ra_res_qp[0x6];
1093
1094         u8         end_pad[0x1];
1095         u8         cc_query_allowed[0x1];
1096         u8         cc_modify_allowed[0x1];
1097         u8         start_pad[0x1];
1098         u8         cache_line_128byte[0x1];
1099         u8         reserved_at_165[0x4];
1100         u8         rts2rts_qp_counters_set_id[0x1];
1101         u8         reserved_at_16a[0x5];
1102         u8         qcam_reg[0x1];
1103         u8         gid_table_size[0x10];
1104
1105         u8         out_of_seq_cnt[0x1];
1106         u8         vport_counters[0x1];
1107         u8         retransmission_q_counters[0x1];
1108         u8         debug[0x1];
1109         u8         modify_rq_counter_set_id[0x1];
1110         u8         rq_delay_drop[0x1];
1111         u8         max_qp_cnt[0xa];
1112         u8         pkey_table_size[0x10];
1113
1114         u8         vport_group_manager[0x1];
1115         u8         vhca_group_manager[0x1];
1116         u8         ib_virt[0x1];
1117         u8         eth_virt[0x1];
1118         u8         vnic_env_queue_counters[0x1];
1119         u8         ets[0x1];
1120         u8         nic_flow_table[0x1];
1121         u8         eswitch_manager[0x1];
1122         u8         device_memory[0x1];
1123         u8         mcam_reg[0x1];
1124         u8         pcam_reg[0x1];
1125         u8         local_ca_ack_delay[0x5];
1126         u8         port_module_event[0x1];
1127         u8         enhanced_error_q_counters[0x1];
1128         u8         ports_check[0x1];
1129         u8         reserved_at_1b3[0x1];
1130         u8         disable_link_up[0x1];
1131         u8         beacon_led[0x1];
1132         u8         port_type[0x2];
1133         u8         num_ports[0x8];
1134
1135         u8         reserved_at_1c0[0x1];
1136         u8         pps[0x1];
1137         u8         pps_modify[0x1];
1138         u8         log_max_msg[0x5];
1139         u8         reserved_at_1c8[0x4];
1140         u8         max_tc[0x4];
1141         u8         temp_warn_event[0x1];
1142         u8         dcbx[0x1];
1143         u8         general_notification_event[0x1];
1144         u8         reserved_at_1d3[0x2];
1145         u8         fpga[0x1];
1146         u8         rol_s[0x1];
1147         u8         rol_g[0x1];
1148         u8         reserved_at_1d8[0x1];
1149         u8         wol_s[0x1];
1150         u8         wol_g[0x1];
1151         u8         wol_a[0x1];
1152         u8         wol_b[0x1];
1153         u8         wol_m[0x1];
1154         u8         wol_u[0x1];
1155         u8         wol_p[0x1];
1156
1157         u8         stat_rate_support[0x10];
1158         u8         reserved_at_1f0[0xc];
1159         u8         cqe_version[0x4];
1160
1161         u8         compact_address_vector[0x1];
1162         u8         striding_rq[0x1];
1163         u8         reserved_at_202[0x1];
1164         u8         ipoib_enhanced_offloads[0x1];
1165         u8         ipoib_basic_offloads[0x1];
1166         u8         reserved_at_205[0x1];
1167         u8         repeated_block_disabled[0x1];
1168         u8         umr_modify_entity_size_disabled[0x1];
1169         u8         umr_modify_atomic_disabled[0x1];
1170         u8         umr_indirect_mkey_disabled[0x1];
1171         u8         umr_fence[0x2];
1172         u8         dc_req_scat_data_cqe[0x1];
1173         u8         reserved_at_20d[0x2];
1174         u8         drain_sigerr[0x1];
1175         u8         cmdif_checksum[0x2];
1176         u8         sigerr_cqe[0x1];
1177         u8         reserved_at_213[0x1];
1178         u8         wq_signature[0x1];
1179         u8         sctr_data_cqe[0x1];
1180         u8         reserved_at_216[0x1];
1181         u8         sho[0x1];
1182         u8         tph[0x1];
1183         u8         rf[0x1];
1184         u8         dct[0x1];
1185         u8         qos[0x1];
1186         u8         eth_net_offloads[0x1];
1187         u8         roce[0x1];
1188         u8         atomic[0x1];
1189         u8         reserved_at_21f[0x1];
1190
1191         u8         cq_oi[0x1];
1192         u8         cq_resize[0x1];
1193         u8         cq_moderation[0x1];
1194         u8         reserved_at_223[0x3];
1195         u8         cq_eq_remap[0x1];
1196         u8         pg[0x1];
1197         u8         block_lb_mc[0x1];
1198         u8         reserved_at_229[0x1];
1199         u8         scqe_break_moderation[0x1];
1200         u8         cq_period_start_from_cqe[0x1];
1201         u8         cd[0x1];
1202         u8         reserved_at_22d[0x1];
1203         u8         apm[0x1];
1204         u8         vector_calc[0x1];
1205         u8         umr_ptr_rlky[0x1];
1206         u8         imaicl[0x1];
1207         u8         qp_packet_based[0x1];
1208         u8         reserved_at_233[0x3];
1209         u8         qkv[0x1];
1210         u8         pkv[0x1];
1211         u8         set_deth_sqpn[0x1];
1212         u8         reserved_at_239[0x3];
1213         u8         xrc[0x1];
1214         u8         ud[0x1];
1215         u8         uc[0x1];
1216         u8         rc[0x1];
1217
1218         u8         uar_4k[0x1];
1219         u8         reserved_at_241[0x9];
1220         u8         uar_sz[0x6];
1221         u8         reserved_at_250[0x8];
1222         u8         log_pg_sz[0x8];
1223
1224         u8         bf[0x1];
1225         u8         driver_version[0x1];
1226         u8         pad_tx_eth_packet[0x1];
1227         u8         reserved_at_263[0x8];
1228         u8         log_bf_reg_size[0x5];
1229
1230         u8         reserved_at_270[0xb];
1231         u8         lag_master[0x1];
1232         u8         num_lag_ports[0x4];
1233
1234         u8         reserved_at_280[0x10];
1235         u8         max_wqe_sz_sq[0x10];
1236
1237         u8         reserved_at_2a0[0x10];
1238         u8         max_wqe_sz_rq[0x10];
1239
1240         u8         max_flow_counter_31_16[0x10];
1241         u8         max_wqe_sz_sq_dc[0x10];
1242
1243         u8         reserved_at_2e0[0x7];
1244         u8         max_qp_mcg[0x19];
1245
1246         u8         reserved_at_300[0x18];
1247         u8         log_max_mcg[0x8];
1248
1249         u8         reserved_at_320[0x3];
1250         u8         log_max_transport_domain[0x5];
1251         u8         reserved_at_328[0x3];
1252         u8         log_max_pd[0x5];
1253         u8         reserved_at_330[0xb];
1254         u8         log_max_xrcd[0x5];
1255
1256         u8         nic_receive_steering_discard[0x1];
1257         u8         receive_discard_vport_down[0x1];
1258         u8         transmit_discard_vport_down[0x1];
1259         u8         reserved_at_343[0x5];
1260         u8         log_max_flow_counter_bulk[0x8];
1261         u8         max_flow_counter_15_0[0x10];
1262
1263
1264         u8         reserved_at_360[0x3];
1265         u8         log_max_rq[0x5];
1266         u8         reserved_at_368[0x3];
1267         u8         log_max_sq[0x5];
1268         u8         reserved_at_370[0x3];
1269         u8         log_max_tir[0x5];
1270         u8         reserved_at_378[0x3];
1271         u8         log_max_tis[0x5];
1272
1273         u8         basic_cyclic_rcv_wqe[0x1];
1274         u8         reserved_at_381[0x2];
1275         u8         log_max_rmp[0x5];
1276         u8         reserved_at_388[0x3];
1277         u8         log_max_rqt[0x5];
1278         u8         reserved_at_390[0x3];
1279         u8         log_max_rqt_size[0x5];
1280         u8         reserved_at_398[0x3];
1281         u8         log_max_tis_per_sq[0x5];
1282
1283         u8         ext_stride_num_range[0x1];
1284         u8         reserved_at_3a1[0x2];
1285         u8         log_max_stride_sz_rq[0x5];
1286         u8         reserved_at_3a8[0x3];
1287         u8         log_min_stride_sz_rq[0x5];
1288         u8         reserved_at_3b0[0x3];
1289         u8         log_max_stride_sz_sq[0x5];
1290         u8         reserved_at_3b8[0x3];
1291         u8         log_min_stride_sz_sq[0x5];
1292
1293         u8         hairpin[0x1];
1294         u8         reserved_at_3c1[0x2];
1295         u8         log_max_hairpin_queues[0x5];
1296         u8         reserved_at_3c8[0x3];
1297         u8         log_max_hairpin_wq_data_sz[0x5];
1298         u8         reserved_at_3d0[0x3];
1299         u8         log_max_hairpin_num_packets[0x5];
1300         u8         reserved_at_3d8[0x3];
1301         u8         log_max_wq_sz[0x5];
1302
1303         u8         nic_vport_change_event[0x1];
1304         u8         disable_local_lb_uc[0x1];
1305         u8         disable_local_lb_mc[0x1];
1306         u8         log_min_hairpin_wq_data_sz[0x5];
1307         u8         reserved_at_3e8[0x3];
1308         u8         log_max_vlan_list[0x5];
1309         u8         reserved_at_3f0[0x3];
1310         u8         log_max_current_mc_list[0x5];
1311         u8         reserved_at_3f8[0x3];
1312         u8         log_max_current_uc_list[0x5];
1313
1314         u8         general_obj_types[0x40];
1315
1316         u8         reserved_at_440[0x20];
1317
1318         u8         tls[0x1];
1319         u8         reserved_at_461[0x2];
1320         u8         log_max_uctx[0x5];
1321         u8         reserved_at_468[0x3];
1322         u8         log_max_umem[0x5];
1323         u8         max_num_eqs[0x10];
1324
1325         u8         reserved_at_480[0x3];
1326         u8         log_max_l2_table[0x5];
1327         u8         reserved_at_488[0x8];
1328         u8         log_uar_page_sz[0x10];
1329
1330         u8         reserved_at_4a0[0x20];
1331         u8         device_frequency_mhz[0x20];
1332         u8         device_frequency_khz[0x20];
1333
1334         u8         reserved_at_500[0x20];
1335         u8         num_of_uars_per_page[0x20];
1336
1337         u8         flex_parser_protocols[0x20];
1338
1339         u8         max_geneve_tlv_options[0x8];
1340         u8         reserved_at_568[0x3];
1341         u8         max_geneve_tlv_option_data_len[0x5];
1342         u8         reserved_at_570[0x10];
1343
1344         u8         reserved_at_580[0x33];
1345         u8         log_max_dek[0x5];
1346         u8         reserved_at_5b8[0x4];
1347         u8         mini_cqe_resp_stride_index[0x1];
1348         u8         cqe_128_always[0x1];
1349         u8         cqe_compression_128[0x1];
1350         u8         cqe_compression[0x1];
1351
1352         u8         cqe_compression_timeout[0x10];
1353         u8         cqe_compression_max_num[0x10];
1354
1355         u8         reserved_at_5e0[0x10];
1356         u8         tag_matching[0x1];
1357         u8         rndv_offload_rc[0x1];
1358         u8         rndv_offload_dc[0x1];
1359         u8         log_tag_matching_list_sz[0x5];
1360         u8         reserved_at_5f8[0x3];
1361         u8         log_max_xrq[0x5];
1362
1363         u8         affiliate_nic_vport_criteria[0x8];
1364         u8         native_port_num[0x8];
1365         u8         num_vhca_ports[0x8];
1366         u8         reserved_at_618[0x6];
1367         u8         sw_owner_id[0x1];
1368         u8         reserved_at_61f[0x1];
1369
1370         u8         max_num_of_monitor_counters[0x10];
1371         u8         num_ppcnt_monitor_counters[0x10];
1372
1373         u8         reserved_at_640[0x10];
1374         u8         num_q_monitor_counters[0x10];
1375
1376         u8         reserved_at_660[0x20];
1377
1378         u8         sf[0x1];
1379         u8         sf_set_partition[0x1];
1380         u8         reserved_at_682[0x1];
1381         u8         log_max_sf[0x5];
1382         u8         reserved_at_688[0x8];
1383         u8         log_min_sf_size[0x8];
1384         u8         max_num_sf_partitions[0x8];
1385
1386         u8         uctx_cap[0x20];
1387
1388         u8         reserved_at_6c0[0x4];
1389         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1390         u8         reserved_at_6c8[0x28];
1391         u8         sf_base_id[0x10];
1392
1393         u8         reserved_at_700[0x100];
1394 };
1395
1396 enum mlx5_flow_destination_type {
1397         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1398         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1399         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1400
1401         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1402         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1403         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1404 };
1405
1406 enum mlx5_flow_table_miss_action {
1407         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1408         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1409         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1410 };
1411
1412 struct mlx5_ifc_dest_format_struct_bits {
1413         u8         destination_type[0x8];
1414         u8         destination_id[0x18];
1415
1416         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1417         u8         packet_reformat[0x1];
1418         u8         reserved_at_22[0xe];
1419         u8         destination_eswitch_owner_vhca_id[0x10];
1420 };
1421
1422 struct mlx5_ifc_flow_counter_list_bits {
1423         u8         flow_counter_id[0x20];
1424
1425         u8         reserved_at_20[0x20];
1426 };
1427
1428 struct mlx5_ifc_extended_dest_format_bits {
1429         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1430
1431         u8         packet_reformat_id[0x20];
1432
1433         u8         reserved_at_60[0x20];
1434 };
1435
1436 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1437         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1438         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1439         u8         reserved_at_0[0x40];
1440 };
1441
1442 struct mlx5_ifc_fte_match_param_bits {
1443         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1444
1445         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1446
1447         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1448
1449         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1450
1451         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1452
1453         u8         reserved_at_a00[0x600];
1454 };
1455
1456 enum {
1457         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1458         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1459         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1460         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1461         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1462 };
1463
1464 struct mlx5_ifc_rx_hash_field_select_bits {
1465         u8         l3_prot_type[0x1];
1466         u8         l4_prot_type[0x1];
1467         u8         selected_fields[0x1e];
1468 };
1469
1470 enum {
1471         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1472         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1473 };
1474
1475 enum {
1476         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1477         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1478 };
1479
1480 struct mlx5_ifc_wq_bits {
1481         u8         wq_type[0x4];
1482         u8         wq_signature[0x1];
1483         u8         end_padding_mode[0x2];
1484         u8         cd_slave[0x1];
1485         u8         reserved_at_8[0x18];
1486
1487         u8         hds_skip_first_sge[0x1];
1488         u8         log2_hds_buf_size[0x3];
1489         u8         reserved_at_24[0x7];
1490         u8         page_offset[0x5];
1491         u8         lwm[0x10];
1492
1493         u8         reserved_at_40[0x8];
1494         u8         pd[0x18];
1495
1496         u8         reserved_at_60[0x8];
1497         u8         uar_page[0x18];
1498
1499         u8         dbr_addr[0x40];
1500
1501         u8         hw_counter[0x20];
1502
1503         u8         sw_counter[0x20];
1504
1505         u8         reserved_at_100[0xc];
1506         u8         log_wq_stride[0x4];
1507         u8         reserved_at_110[0x3];
1508         u8         log_wq_pg_sz[0x5];
1509         u8         reserved_at_118[0x3];
1510         u8         log_wq_sz[0x5];
1511
1512         u8         dbr_umem_valid[0x1];
1513         u8         wq_umem_valid[0x1];
1514         u8         reserved_at_122[0x1];
1515         u8         log_hairpin_num_packets[0x5];
1516         u8         reserved_at_128[0x3];
1517         u8         log_hairpin_data_sz[0x5];
1518
1519         u8         reserved_at_130[0x4];
1520         u8         log_wqe_num_of_strides[0x4];
1521         u8         two_byte_shift_en[0x1];
1522         u8         reserved_at_139[0x4];
1523         u8         log_wqe_stride_size[0x3];
1524
1525         u8         reserved_at_140[0x4c0];
1526
1527         struct mlx5_ifc_cmd_pas_bits pas[0];
1528 };
1529
1530 struct mlx5_ifc_rq_num_bits {
1531         u8         reserved_at_0[0x8];
1532         u8         rq_num[0x18];
1533 };
1534
1535 struct mlx5_ifc_mac_address_layout_bits {
1536         u8         reserved_at_0[0x10];
1537         u8         mac_addr_47_32[0x10];
1538
1539         u8         mac_addr_31_0[0x20];
1540 };
1541
1542 struct mlx5_ifc_vlan_layout_bits {
1543         u8         reserved_at_0[0x14];
1544         u8         vlan[0x0c];
1545
1546         u8         reserved_at_20[0x20];
1547 };
1548
1549 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1550         u8         reserved_at_0[0xa0];
1551
1552         u8         min_time_between_cnps[0x20];
1553
1554         u8         reserved_at_c0[0x12];
1555         u8         cnp_dscp[0x6];
1556         u8         reserved_at_d8[0x4];
1557         u8         cnp_prio_mode[0x1];
1558         u8         cnp_802p_prio[0x3];
1559
1560         u8         reserved_at_e0[0x720];
1561 };
1562
1563 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1564         u8         reserved_at_0[0x60];
1565
1566         u8         reserved_at_60[0x4];
1567         u8         clamp_tgt_rate[0x1];
1568         u8         reserved_at_65[0x3];
1569         u8         clamp_tgt_rate_after_time_inc[0x1];
1570         u8         reserved_at_69[0x17];
1571
1572         u8         reserved_at_80[0x20];
1573
1574         u8         rpg_time_reset[0x20];
1575
1576         u8         rpg_byte_reset[0x20];
1577
1578         u8         rpg_threshold[0x20];
1579
1580         u8         rpg_max_rate[0x20];
1581
1582         u8         rpg_ai_rate[0x20];
1583
1584         u8         rpg_hai_rate[0x20];
1585
1586         u8         rpg_gd[0x20];
1587
1588         u8         rpg_min_dec_fac[0x20];
1589
1590         u8         rpg_min_rate[0x20];
1591
1592         u8         reserved_at_1c0[0xe0];
1593
1594         u8         rate_to_set_on_first_cnp[0x20];
1595
1596         u8         dce_tcp_g[0x20];
1597
1598         u8         dce_tcp_rtt[0x20];
1599
1600         u8         rate_reduce_monitor_period[0x20];
1601
1602         u8         reserved_at_320[0x20];
1603
1604         u8         initial_alpha_value[0x20];
1605
1606         u8         reserved_at_360[0x4a0];
1607 };
1608
1609 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1610         u8         reserved_at_0[0x80];
1611
1612         u8         rppp_max_rps[0x20];
1613
1614         u8         rpg_time_reset[0x20];
1615
1616         u8         rpg_byte_reset[0x20];
1617
1618         u8         rpg_threshold[0x20];
1619
1620         u8         rpg_max_rate[0x20];
1621
1622         u8         rpg_ai_rate[0x20];
1623
1624         u8         rpg_hai_rate[0x20];
1625
1626         u8         rpg_gd[0x20];
1627
1628         u8         rpg_min_dec_fac[0x20];
1629
1630         u8         rpg_min_rate[0x20];
1631
1632         u8         reserved_at_1c0[0x640];
1633 };
1634
1635 enum {
1636         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1637         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1638         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1639 };
1640
1641 struct mlx5_ifc_resize_field_select_bits {
1642         u8         resize_field_select[0x20];
1643 };
1644
1645 enum {
1646         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1647         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1648         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1649         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1650 };
1651
1652 struct mlx5_ifc_modify_field_select_bits {
1653         u8         modify_field_select[0x20];
1654 };
1655
1656 struct mlx5_ifc_field_select_r_roce_np_bits {
1657         u8         field_select_r_roce_np[0x20];
1658 };
1659
1660 struct mlx5_ifc_field_select_r_roce_rp_bits {
1661         u8         field_select_r_roce_rp[0x20];
1662 };
1663
1664 enum {
1665         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1666         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1667         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1668         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1669         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1670         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1671         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1672         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1673         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1674         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1675 };
1676
1677 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1678         u8         field_select_8021qaurp[0x20];
1679 };
1680
1681 struct mlx5_ifc_phys_layer_cntrs_bits {
1682         u8         time_since_last_clear_high[0x20];
1683
1684         u8         time_since_last_clear_low[0x20];
1685
1686         u8         symbol_errors_high[0x20];
1687
1688         u8         symbol_errors_low[0x20];
1689
1690         u8         sync_headers_errors_high[0x20];
1691
1692         u8         sync_headers_errors_low[0x20];
1693
1694         u8         edpl_bip_errors_lane0_high[0x20];
1695
1696         u8         edpl_bip_errors_lane0_low[0x20];
1697
1698         u8         edpl_bip_errors_lane1_high[0x20];
1699
1700         u8         edpl_bip_errors_lane1_low[0x20];
1701
1702         u8         edpl_bip_errors_lane2_high[0x20];
1703
1704         u8         edpl_bip_errors_lane2_low[0x20];
1705
1706         u8         edpl_bip_errors_lane3_high[0x20];
1707
1708         u8         edpl_bip_errors_lane3_low[0x20];
1709
1710         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1711
1712         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1713
1714         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1715
1716         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1717
1718         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1719
1720         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1721
1722         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1723
1724         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1725
1726         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1727
1728         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1729
1730         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1731
1732         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1733
1734         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1735
1736         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1737
1738         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1739
1740         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1741
1742         u8         rs_fec_corrected_blocks_high[0x20];
1743
1744         u8         rs_fec_corrected_blocks_low[0x20];
1745
1746         u8         rs_fec_uncorrectable_blocks_high[0x20];
1747
1748         u8         rs_fec_uncorrectable_blocks_low[0x20];
1749
1750         u8         rs_fec_no_errors_blocks_high[0x20];
1751
1752         u8         rs_fec_no_errors_blocks_low[0x20];
1753
1754         u8         rs_fec_single_error_blocks_high[0x20];
1755
1756         u8         rs_fec_single_error_blocks_low[0x20];
1757
1758         u8         rs_fec_corrected_symbols_total_high[0x20];
1759
1760         u8         rs_fec_corrected_symbols_total_low[0x20];
1761
1762         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1763
1764         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1765
1766         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1767
1768         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1769
1770         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1771
1772         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1773
1774         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1775
1776         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1777
1778         u8         link_down_events[0x20];
1779
1780         u8         successful_recovery_events[0x20];
1781
1782         u8         reserved_at_640[0x180];
1783 };
1784
1785 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1786         u8         time_since_last_clear_high[0x20];
1787
1788         u8         time_since_last_clear_low[0x20];
1789
1790         u8         phy_received_bits_high[0x20];
1791
1792         u8         phy_received_bits_low[0x20];
1793
1794         u8         phy_symbol_errors_high[0x20];
1795
1796         u8         phy_symbol_errors_low[0x20];
1797
1798         u8         phy_corrected_bits_high[0x20];
1799
1800         u8         phy_corrected_bits_low[0x20];
1801
1802         u8         phy_corrected_bits_lane0_high[0x20];
1803
1804         u8         phy_corrected_bits_lane0_low[0x20];
1805
1806         u8         phy_corrected_bits_lane1_high[0x20];
1807
1808         u8         phy_corrected_bits_lane1_low[0x20];
1809
1810         u8         phy_corrected_bits_lane2_high[0x20];
1811
1812         u8         phy_corrected_bits_lane2_low[0x20];
1813
1814         u8         phy_corrected_bits_lane3_high[0x20];
1815
1816         u8         phy_corrected_bits_lane3_low[0x20];
1817
1818         u8         reserved_at_200[0x5c0];
1819 };
1820
1821 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1822         u8         symbol_error_counter[0x10];
1823
1824         u8         link_error_recovery_counter[0x8];
1825
1826         u8         link_downed_counter[0x8];
1827
1828         u8         port_rcv_errors[0x10];
1829
1830         u8         port_rcv_remote_physical_errors[0x10];
1831
1832         u8         port_rcv_switch_relay_errors[0x10];
1833
1834         u8         port_xmit_discards[0x10];
1835
1836         u8         port_xmit_constraint_errors[0x8];
1837
1838         u8         port_rcv_constraint_errors[0x8];
1839
1840         u8         reserved_at_70[0x8];
1841
1842         u8         link_overrun_errors[0x8];
1843
1844         u8         reserved_at_80[0x10];
1845
1846         u8         vl_15_dropped[0x10];
1847
1848         u8         reserved_at_a0[0x80];
1849
1850         u8         port_xmit_wait[0x20];
1851 };
1852
1853 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1854         u8         transmit_queue_high[0x20];
1855
1856         u8         transmit_queue_low[0x20];
1857
1858         u8         reserved_at_40[0x780];
1859 };
1860
1861 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1862         u8         rx_octets_high[0x20];
1863
1864         u8         rx_octets_low[0x20];
1865
1866         u8         reserved_at_40[0xc0];
1867
1868         u8         rx_frames_high[0x20];
1869
1870         u8         rx_frames_low[0x20];
1871
1872         u8         tx_octets_high[0x20];
1873
1874         u8         tx_octets_low[0x20];
1875
1876         u8         reserved_at_180[0xc0];
1877
1878         u8         tx_frames_high[0x20];
1879
1880         u8         tx_frames_low[0x20];
1881
1882         u8         rx_pause_high[0x20];
1883
1884         u8         rx_pause_low[0x20];
1885
1886         u8         rx_pause_duration_high[0x20];
1887
1888         u8         rx_pause_duration_low[0x20];
1889
1890         u8         tx_pause_high[0x20];
1891
1892         u8         tx_pause_low[0x20];
1893
1894         u8         tx_pause_duration_high[0x20];
1895
1896         u8         tx_pause_duration_low[0x20];
1897
1898         u8         rx_pause_transition_high[0x20];
1899
1900         u8         rx_pause_transition_low[0x20];
1901
1902         u8         reserved_at_3c0[0x40];
1903
1904         u8         device_stall_minor_watermark_cnt_high[0x20];
1905
1906         u8         device_stall_minor_watermark_cnt_low[0x20];
1907
1908         u8         device_stall_critical_watermark_cnt_high[0x20];
1909
1910         u8         device_stall_critical_watermark_cnt_low[0x20];
1911
1912         u8         reserved_at_480[0x340];
1913 };
1914
1915 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1916         u8         port_transmit_wait_high[0x20];
1917
1918         u8         port_transmit_wait_low[0x20];
1919
1920         u8         reserved_at_40[0x100];
1921
1922         u8         rx_buffer_almost_full_high[0x20];
1923
1924         u8         rx_buffer_almost_full_low[0x20];
1925
1926         u8         rx_buffer_full_high[0x20];
1927
1928         u8         rx_buffer_full_low[0x20];
1929
1930         u8         rx_icrc_encapsulated_high[0x20];
1931
1932         u8         rx_icrc_encapsulated_low[0x20];
1933
1934         u8         reserved_at_200[0x5c0];
1935 };
1936
1937 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1938         u8         dot3stats_alignment_errors_high[0x20];
1939
1940         u8         dot3stats_alignment_errors_low[0x20];
1941
1942         u8         dot3stats_fcs_errors_high[0x20];
1943
1944         u8         dot3stats_fcs_errors_low[0x20];
1945
1946         u8         dot3stats_single_collision_frames_high[0x20];
1947
1948         u8         dot3stats_single_collision_frames_low[0x20];
1949
1950         u8         dot3stats_multiple_collision_frames_high[0x20];
1951
1952         u8         dot3stats_multiple_collision_frames_low[0x20];
1953
1954         u8         dot3stats_sqe_test_errors_high[0x20];
1955
1956         u8         dot3stats_sqe_test_errors_low[0x20];
1957
1958         u8         dot3stats_deferred_transmissions_high[0x20];
1959
1960         u8         dot3stats_deferred_transmissions_low[0x20];
1961
1962         u8         dot3stats_late_collisions_high[0x20];
1963
1964         u8         dot3stats_late_collisions_low[0x20];
1965
1966         u8         dot3stats_excessive_collisions_high[0x20];
1967
1968         u8         dot3stats_excessive_collisions_low[0x20];
1969
1970         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1971
1972         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1973
1974         u8         dot3stats_carrier_sense_errors_high[0x20];
1975
1976         u8         dot3stats_carrier_sense_errors_low[0x20];
1977
1978         u8         dot3stats_frame_too_longs_high[0x20];
1979
1980         u8         dot3stats_frame_too_longs_low[0x20];
1981
1982         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1983
1984         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1985
1986         u8         dot3stats_symbol_errors_high[0x20];
1987
1988         u8         dot3stats_symbol_errors_low[0x20];
1989
1990         u8         dot3control_in_unknown_opcodes_high[0x20];
1991
1992         u8         dot3control_in_unknown_opcodes_low[0x20];
1993
1994         u8         dot3in_pause_frames_high[0x20];
1995
1996         u8         dot3in_pause_frames_low[0x20];
1997
1998         u8         dot3out_pause_frames_high[0x20];
1999
2000         u8         dot3out_pause_frames_low[0x20];
2001
2002         u8         reserved_at_400[0x3c0];
2003 };
2004
2005 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2006         u8         ether_stats_drop_events_high[0x20];
2007
2008         u8         ether_stats_drop_events_low[0x20];
2009
2010         u8         ether_stats_octets_high[0x20];
2011
2012         u8         ether_stats_octets_low[0x20];
2013
2014         u8         ether_stats_pkts_high[0x20];
2015
2016         u8         ether_stats_pkts_low[0x20];
2017
2018         u8         ether_stats_broadcast_pkts_high[0x20];
2019
2020         u8         ether_stats_broadcast_pkts_low[0x20];
2021
2022         u8         ether_stats_multicast_pkts_high[0x20];
2023
2024         u8         ether_stats_multicast_pkts_low[0x20];
2025
2026         u8         ether_stats_crc_align_errors_high[0x20];
2027
2028         u8         ether_stats_crc_align_errors_low[0x20];
2029
2030         u8         ether_stats_undersize_pkts_high[0x20];
2031
2032         u8         ether_stats_undersize_pkts_low[0x20];
2033
2034         u8         ether_stats_oversize_pkts_high[0x20];
2035
2036         u8         ether_stats_oversize_pkts_low[0x20];
2037
2038         u8         ether_stats_fragments_high[0x20];
2039
2040         u8         ether_stats_fragments_low[0x20];
2041
2042         u8         ether_stats_jabbers_high[0x20];
2043
2044         u8         ether_stats_jabbers_low[0x20];
2045
2046         u8         ether_stats_collisions_high[0x20];
2047
2048         u8         ether_stats_collisions_low[0x20];
2049
2050         u8         ether_stats_pkts64octets_high[0x20];
2051
2052         u8         ether_stats_pkts64octets_low[0x20];
2053
2054         u8         ether_stats_pkts65to127octets_high[0x20];
2055
2056         u8         ether_stats_pkts65to127octets_low[0x20];
2057
2058         u8         ether_stats_pkts128to255octets_high[0x20];
2059
2060         u8         ether_stats_pkts128to255octets_low[0x20];
2061
2062         u8         ether_stats_pkts256to511octets_high[0x20];
2063
2064         u8         ether_stats_pkts256to511octets_low[0x20];
2065
2066         u8         ether_stats_pkts512to1023octets_high[0x20];
2067
2068         u8         ether_stats_pkts512to1023octets_low[0x20];
2069
2070         u8         ether_stats_pkts1024to1518octets_high[0x20];
2071
2072         u8         ether_stats_pkts1024to1518octets_low[0x20];
2073
2074         u8         ether_stats_pkts1519to2047octets_high[0x20];
2075
2076         u8         ether_stats_pkts1519to2047octets_low[0x20];
2077
2078         u8         ether_stats_pkts2048to4095octets_high[0x20];
2079
2080         u8         ether_stats_pkts2048to4095octets_low[0x20];
2081
2082         u8         ether_stats_pkts4096to8191octets_high[0x20];
2083
2084         u8         ether_stats_pkts4096to8191octets_low[0x20];
2085
2086         u8         ether_stats_pkts8192to10239octets_high[0x20];
2087
2088         u8         ether_stats_pkts8192to10239octets_low[0x20];
2089
2090         u8         reserved_at_540[0x280];
2091 };
2092
2093 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2094         u8         if_in_octets_high[0x20];
2095
2096         u8         if_in_octets_low[0x20];
2097
2098         u8         if_in_ucast_pkts_high[0x20];
2099
2100         u8         if_in_ucast_pkts_low[0x20];
2101
2102         u8         if_in_discards_high[0x20];
2103
2104         u8         if_in_discards_low[0x20];
2105
2106         u8         if_in_errors_high[0x20];
2107
2108         u8         if_in_errors_low[0x20];
2109
2110         u8         if_in_unknown_protos_high[0x20];
2111
2112         u8         if_in_unknown_protos_low[0x20];
2113
2114         u8         if_out_octets_high[0x20];
2115
2116         u8         if_out_octets_low[0x20];
2117
2118         u8         if_out_ucast_pkts_high[0x20];
2119
2120         u8         if_out_ucast_pkts_low[0x20];
2121
2122         u8         if_out_discards_high[0x20];
2123
2124         u8         if_out_discards_low[0x20];
2125
2126         u8         if_out_errors_high[0x20];
2127
2128         u8         if_out_errors_low[0x20];
2129
2130         u8         if_in_multicast_pkts_high[0x20];
2131
2132         u8         if_in_multicast_pkts_low[0x20];
2133
2134         u8         if_in_broadcast_pkts_high[0x20];
2135
2136         u8         if_in_broadcast_pkts_low[0x20];
2137
2138         u8         if_out_multicast_pkts_high[0x20];
2139
2140         u8         if_out_multicast_pkts_low[0x20];
2141
2142         u8         if_out_broadcast_pkts_high[0x20];
2143
2144         u8         if_out_broadcast_pkts_low[0x20];
2145
2146         u8         reserved_at_340[0x480];
2147 };
2148
2149 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2150         u8         a_frames_transmitted_ok_high[0x20];
2151
2152         u8         a_frames_transmitted_ok_low[0x20];
2153
2154         u8         a_frames_received_ok_high[0x20];
2155
2156         u8         a_frames_received_ok_low[0x20];
2157
2158         u8         a_frame_check_sequence_errors_high[0x20];
2159
2160         u8         a_frame_check_sequence_errors_low[0x20];
2161
2162         u8         a_alignment_errors_high[0x20];
2163
2164         u8         a_alignment_errors_low[0x20];
2165
2166         u8         a_octets_transmitted_ok_high[0x20];
2167
2168         u8         a_octets_transmitted_ok_low[0x20];
2169
2170         u8         a_octets_received_ok_high[0x20];
2171
2172         u8         a_octets_received_ok_low[0x20];
2173
2174         u8         a_multicast_frames_xmitted_ok_high[0x20];
2175
2176         u8         a_multicast_frames_xmitted_ok_low[0x20];
2177
2178         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2179
2180         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2181
2182         u8         a_multicast_frames_received_ok_high[0x20];
2183
2184         u8         a_multicast_frames_received_ok_low[0x20];
2185
2186         u8         a_broadcast_frames_received_ok_high[0x20];
2187
2188         u8         a_broadcast_frames_received_ok_low[0x20];
2189
2190         u8         a_in_range_length_errors_high[0x20];
2191
2192         u8         a_in_range_length_errors_low[0x20];
2193
2194         u8         a_out_of_range_length_field_high[0x20];
2195
2196         u8         a_out_of_range_length_field_low[0x20];
2197
2198         u8         a_frame_too_long_errors_high[0x20];
2199
2200         u8         a_frame_too_long_errors_low[0x20];
2201
2202         u8         a_symbol_error_during_carrier_high[0x20];
2203
2204         u8         a_symbol_error_during_carrier_low[0x20];
2205
2206         u8         a_mac_control_frames_transmitted_high[0x20];
2207
2208         u8         a_mac_control_frames_transmitted_low[0x20];
2209
2210         u8         a_mac_control_frames_received_high[0x20];
2211
2212         u8         a_mac_control_frames_received_low[0x20];
2213
2214         u8         a_unsupported_opcodes_received_high[0x20];
2215
2216         u8         a_unsupported_opcodes_received_low[0x20];
2217
2218         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2219
2220         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2221
2222         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2223
2224         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2225
2226         u8         reserved_at_4c0[0x300];
2227 };
2228
2229 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2230         u8         life_time_counter_high[0x20];
2231
2232         u8         life_time_counter_low[0x20];
2233
2234         u8         rx_errors[0x20];
2235
2236         u8         tx_errors[0x20];
2237
2238         u8         l0_to_recovery_eieos[0x20];
2239
2240         u8         l0_to_recovery_ts[0x20];
2241
2242         u8         l0_to_recovery_framing[0x20];
2243
2244         u8         l0_to_recovery_retrain[0x20];
2245
2246         u8         crc_error_dllp[0x20];
2247
2248         u8         crc_error_tlp[0x20];
2249
2250         u8         tx_overflow_buffer_pkt_high[0x20];
2251
2252         u8         tx_overflow_buffer_pkt_low[0x20];
2253
2254         u8         outbound_stalled_reads[0x20];
2255
2256         u8         outbound_stalled_writes[0x20];
2257
2258         u8         outbound_stalled_reads_events[0x20];
2259
2260         u8         outbound_stalled_writes_events[0x20];
2261
2262         u8         reserved_at_200[0x5c0];
2263 };
2264
2265 struct mlx5_ifc_cmd_inter_comp_event_bits {
2266         u8         command_completion_vector[0x20];
2267
2268         u8         reserved_at_20[0xc0];
2269 };
2270
2271 struct mlx5_ifc_stall_vl_event_bits {
2272         u8         reserved_at_0[0x18];
2273         u8         port_num[0x1];
2274         u8         reserved_at_19[0x3];
2275         u8         vl[0x4];
2276
2277         u8         reserved_at_20[0xa0];
2278 };
2279
2280 struct mlx5_ifc_db_bf_congestion_event_bits {
2281         u8         event_subtype[0x8];
2282         u8         reserved_at_8[0x8];
2283         u8         congestion_level[0x8];
2284         u8         reserved_at_18[0x8];
2285
2286         u8         reserved_at_20[0xa0];
2287 };
2288
2289 struct mlx5_ifc_gpio_event_bits {
2290         u8         reserved_at_0[0x60];
2291
2292         u8         gpio_event_hi[0x20];
2293
2294         u8         gpio_event_lo[0x20];
2295
2296         u8         reserved_at_a0[0x40];
2297 };
2298
2299 struct mlx5_ifc_port_state_change_event_bits {
2300         u8         reserved_at_0[0x40];
2301
2302         u8         port_num[0x4];
2303         u8         reserved_at_44[0x1c];
2304
2305         u8         reserved_at_60[0x80];
2306 };
2307
2308 struct mlx5_ifc_dropped_packet_logged_bits {
2309         u8         reserved_at_0[0xe0];
2310 };
2311
2312 enum {
2313         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2314         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2315 };
2316
2317 struct mlx5_ifc_cq_error_bits {
2318         u8         reserved_at_0[0x8];
2319         u8         cqn[0x18];
2320
2321         u8         reserved_at_20[0x20];
2322
2323         u8         reserved_at_40[0x18];
2324         u8         syndrome[0x8];
2325
2326         u8         reserved_at_60[0x80];
2327 };
2328
2329 struct mlx5_ifc_rdma_page_fault_event_bits {
2330         u8         bytes_committed[0x20];
2331
2332         u8         r_key[0x20];
2333
2334         u8         reserved_at_40[0x10];
2335         u8         packet_len[0x10];
2336
2337         u8         rdma_op_len[0x20];
2338
2339         u8         rdma_va[0x40];
2340
2341         u8         reserved_at_c0[0x5];
2342         u8         rdma[0x1];
2343         u8         write[0x1];
2344         u8         requestor[0x1];
2345         u8         qp_number[0x18];
2346 };
2347
2348 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2349         u8         bytes_committed[0x20];
2350
2351         u8         reserved_at_20[0x10];
2352         u8         wqe_index[0x10];
2353
2354         u8         reserved_at_40[0x10];
2355         u8         len[0x10];
2356
2357         u8         reserved_at_60[0x60];
2358
2359         u8         reserved_at_c0[0x5];
2360         u8         rdma[0x1];
2361         u8         write_read[0x1];
2362         u8         requestor[0x1];
2363         u8         qpn[0x18];
2364 };
2365
2366 struct mlx5_ifc_qp_events_bits {
2367         u8         reserved_at_0[0xa0];
2368
2369         u8         type[0x8];
2370         u8         reserved_at_a8[0x18];
2371
2372         u8         reserved_at_c0[0x8];
2373         u8         qpn_rqn_sqn[0x18];
2374 };
2375
2376 struct mlx5_ifc_dct_events_bits {
2377         u8         reserved_at_0[0xc0];
2378
2379         u8         reserved_at_c0[0x8];
2380         u8         dct_number[0x18];
2381 };
2382
2383 struct mlx5_ifc_comp_event_bits {
2384         u8         reserved_at_0[0xc0];
2385
2386         u8         reserved_at_c0[0x8];
2387         u8         cq_number[0x18];
2388 };
2389
2390 enum {
2391         MLX5_QPC_STATE_RST        = 0x0,
2392         MLX5_QPC_STATE_INIT       = 0x1,
2393         MLX5_QPC_STATE_RTR        = 0x2,
2394         MLX5_QPC_STATE_RTS        = 0x3,
2395         MLX5_QPC_STATE_SQER       = 0x4,
2396         MLX5_QPC_STATE_ERR        = 0x6,
2397         MLX5_QPC_STATE_SQD        = 0x7,
2398         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2399 };
2400
2401 enum {
2402         MLX5_QPC_ST_RC            = 0x0,
2403         MLX5_QPC_ST_UC            = 0x1,
2404         MLX5_QPC_ST_UD            = 0x2,
2405         MLX5_QPC_ST_XRC           = 0x3,
2406         MLX5_QPC_ST_DCI           = 0x5,
2407         MLX5_QPC_ST_QP0           = 0x7,
2408         MLX5_QPC_ST_QP1           = 0x8,
2409         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2410         MLX5_QPC_ST_REG_UMR       = 0xc,
2411 };
2412
2413 enum {
2414         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2415         MLX5_QPC_PM_STATE_REARM     = 0x1,
2416         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2417         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2418 };
2419
2420 enum {
2421         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2422 };
2423
2424 enum {
2425         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2426         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2427 };
2428
2429 enum {
2430         MLX5_QPC_MTU_256_BYTES        = 0x1,
2431         MLX5_QPC_MTU_512_BYTES        = 0x2,
2432         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2433         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2434         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2435         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2436 };
2437
2438 enum {
2439         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2440         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2441         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2442         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2443         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2444         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2445         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2446         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2447 };
2448
2449 enum {
2450         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2451         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2452         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2453 };
2454
2455 enum {
2456         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2457         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2458         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2459 };
2460
2461 struct mlx5_ifc_qpc_bits {
2462         u8         state[0x4];
2463         u8         lag_tx_port_affinity[0x4];
2464         u8         st[0x8];
2465         u8         reserved_at_10[0x3];
2466         u8         pm_state[0x2];
2467         u8         reserved_at_15[0x1];
2468         u8         req_e2e_credit_mode[0x2];
2469         u8         offload_type[0x4];
2470         u8         end_padding_mode[0x2];
2471         u8         reserved_at_1e[0x2];
2472
2473         u8         wq_signature[0x1];
2474         u8         block_lb_mc[0x1];
2475         u8         atomic_like_write_en[0x1];
2476         u8         latency_sensitive[0x1];
2477         u8         reserved_at_24[0x1];
2478         u8         drain_sigerr[0x1];
2479         u8         reserved_at_26[0x2];
2480         u8         pd[0x18];
2481
2482         u8         mtu[0x3];
2483         u8         log_msg_max[0x5];
2484         u8         reserved_at_48[0x1];
2485         u8         log_rq_size[0x4];
2486         u8         log_rq_stride[0x3];
2487         u8         no_sq[0x1];
2488         u8         log_sq_size[0x4];
2489         u8         reserved_at_55[0x6];
2490         u8         rlky[0x1];
2491         u8         ulp_stateless_offload_mode[0x4];
2492
2493         u8         counter_set_id[0x8];
2494         u8         uar_page[0x18];
2495
2496         u8         reserved_at_80[0x8];
2497         u8         user_index[0x18];
2498
2499         u8         reserved_at_a0[0x3];
2500         u8         log_page_size[0x5];
2501         u8         remote_qpn[0x18];
2502
2503         struct mlx5_ifc_ads_bits primary_address_path;
2504
2505         struct mlx5_ifc_ads_bits secondary_address_path;
2506
2507         u8         log_ack_req_freq[0x4];
2508         u8         reserved_at_384[0x4];
2509         u8         log_sra_max[0x3];
2510         u8         reserved_at_38b[0x2];
2511         u8         retry_count[0x3];
2512         u8         rnr_retry[0x3];
2513         u8         reserved_at_393[0x1];
2514         u8         fre[0x1];
2515         u8         cur_rnr_retry[0x3];
2516         u8         cur_retry_count[0x3];
2517         u8         reserved_at_39b[0x5];
2518
2519         u8         reserved_at_3a0[0x20];
2520
2521         u8         reserved_at_3c0[0x8];
2522         u8         next_send_psn[0x18];
2523
2524         u8         reserved_at_3e0[0x8];
2525         u8         cqn_snd[0x18];
2526
2527         u8         reserved_at_400[0x8];
2528         u8         deth_sqpn[0x18];
2529
2530         u8         reserved_at_420[0x20];
2531
2532         u8         reserved_at_440[0x8];
2533         u8         last_acked_psn[0x18];
2534
2535         u8         reserved_at_460[0x8];
2536         u8         ssn[0x18];
2537
2538         u8         reserved_at_480[0x8];
2539         u8         log_rra_max[0x3];
2540         u8         reserved_at_48b[0x1];
2541         u8         atomic_mode[0x4];
2542         u8         rre[0x1];
2543         u8         rwe[0x1];
2544         u8         rae[0x1];
2545         u8         reserved_at_493[0x1];
2546         u8         page_offset[0x6];
2547         u8         reserved_at_49a[0x3];
2548         u8         cd_slave_receive[0x1];
2549         u8         cd_slave_send[0x1];
2550         u8         cd_master[0x1];
2551
2552         u8         reserved_at_4a0[0x3];
2553         u8         min_rnr_nak[0x5];
2554         u8         next_rcv_psn[0x18];
2555
2556         u8         reserved_at_4c0[0x8];
2557         u8         xrcd[0x18];
2558
2559         u8         reserved_at_4e0[0x8];
2560         u8         cqn_rcv[0x18];
2561
2562         u8         dbr_addr[0x40];
2563
2564         u8         q_key[0x20];
2565
2566         u8         reserved_at_560[0x5];
2567         u8         rq_type[0x3];
2568         u8         srqn_rmpn_xrqn[0x18];
2569
2570         u8         reserved_at_580[0x8];
2571         u8         rmsn[0x18];
2572
2573         u8         hw_sq_wqebb_counter[0x10];
2574         u8         sw_sq_wqebb_counter[0x10];
2575
2576         u8         hw_rq_counter[0x20];
2577
2578         u8         sw_rq_counter[0x20];
2579
2580         u8         reserved_at_600[0x20];
2581
2582         u8         reserved_at_620[0xf];
2583         u8         cgs[0x1];
2584         u8         cs_req[0x8];
2585         u8         cs_res[0x8];
2586
2587         u8         dc_access_key[0x40];
2588
2589         u8         reserved_at_680[0x3];
2590         u8         dbr_umem_valid[0x1];
2591
2592         u8         reserved_at_684[0xbc];
2593 };
2594
2595 struct mlx5_ifc_roce_addr_layout_bits {
2596         u8         source_l3_address[16][0x8];
2597
2598         u8         reserved_at_80[0x3];
2599         u8         vlan_valid[0x1];
2600         u8         vlan_id[0xc];
2601         u8         source_mac_47_32[0x10];
2602
2603         u8         source_mac_31_0[0x20];
2604
2605         u8         reserved_at_c0[0x14];
2606         u8         roce_l3_type[0x4];
2607         u8         roce_version[0x8];
2608
2609         u8         reserved_at_e0[0x20];
2610 };
2611
2612 union mlx5_ifc_hca_cap_union_bits {
2613         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2614         struct mlx5_ifc_odp_cap_bits odp_cap;
2615         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2616         struct mlx5_ifc_roce_cap_bits roce_cap;
2617         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2618         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2619         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2620         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2621         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2622         struct mlx5_ifc_qos_cap_bits qos_cap;
2623         struct mlx5_ifc_debug_cap_bits debug_cap;
2624         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2625         struct mlx5_ifc_tls_cap_bits tls_cap;
2626         u8         reserved_at_0[0x8000];
2627 };
2628
2629 enum {
2630         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2631         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2632         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2633         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2634         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2635         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2636         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2637         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2638         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2639         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2640         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2641 };
2642
2643 enum {
2644         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2645         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2646         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2647 };
2648
2649 struct mlx5_ifc_vlan_bits {
2650         u8         ethtype[0x10];
2651         u8         prio[0x3];
2652         u8         cfi[0x1];
2653         u8         vid[0xc];
2654 };
2655
2656 struct mlx5_ifc_flow_context_bits {
2657         struct mlx5_ifc_vlan_bits push_vlan;
2658
2659         u8         group_id[0x20];
2660
2661         u8         reserved_at_40[0x8];
2662         u8         flow_tag[0x18];
2663
2664         u8         reserved_at_60[0x10];
2665         u8         action[0x10];
2666
2667         u8         extended_destination[0x1];
2668         u8         reserved_at_81[0x1];
2669         u8         flow_source[0x2];
2670         u8         reserved_at_84[0x4];
2671         u8         destination_list_size[0x18];
2672
2673         u8         reserved_at_a0[0x8];
2674         u8         flow_counter_list_size[0x18];
2675
2676         u8         packet_reformat_id[0x20];
2677
2678         u8         modify_header_id[0x20];
2679
2680         struct mlx5_ifc_vlan_bits push_vlan_2;
2681
2682         u8         reserved_at_120[0xe0];
2683
2684         struct mlx5_ifc_fte_match_param_bits match_value;
2685
2686         u8         reserved_at_1200[0x600];
2687
2688         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2689 };
2690
2691 enum {
2692         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2693         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2694 };
2695
2696 struct mlx5_ifc_xrc_srqc_bits {
2697         u8         state[0x4];
2698         u8         log_xrc_srq_size[0x4];
2699         u8         reserved_at_8[0x18];
2700
2701         u8         wq_signature[0x1];
2702         u8         cont_srq[0x1];
2703         u8         reserved_at_22[0x1];
2704         u8         rlky[0x1];
2705         u8         basic_cyclic_rcv_wqe[0x1];
2706         u8         log_rq_stride[0x3];
2707         u8         xrcd[0x18];
2708
2709         u8         page_offset[0x6];
2710         u8         reserved_at_46[0x1];
2711         u8         dbr_umem_valid[0x1];
2712         u8         cqn[0x18];
2713
2714         u8         reserved_at_60[0x20];
2715
2716         u8         user_index_equal_xrc_srqn[0x1];
2717         u8         reserved_at_81[0x1];
2718         u8         log_page_size[0x6];
2719         u8         user_index[0x18];
2720
2721         u8         reserved_at_a0[0x20];
2722
2723         u8         reserved_at_c0[0x8];
2724         u8         pd[0x18];
2725
2726         u8         lwm[0x10];
2727         u8         wqe_cnt[0x10];
2728
2729         u8         reserved_at_100[0x40];
2730
2731         u8         db_record_addr_h[0x20];
2732
2733         u8         db_record_addr_l[0x1e];
2734         u8         reserved_at_17e[0x2];
2735
2736         u8         reserved_at_180[0x80];
2737 };
2738
2739 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2740         u8         counter_error_queues[0x20];
2741
2742         u8         total_error_queues[0x20];
2743
2744         u8         send_queue_priority_update_flow[0x20];
2745
2746         u8         reserved_at_60[0x20];
2747
2748         u8         nic_receive_steering_discard[0x40];
2749
2750         u8         receive_discard_vport_down[0x40];
2751
2752         u8         transmit_discard_vport_down[0x40];
2753
2754         u8         reserved_at_140[0xec0];
2755 };
2756
2757 struct mlx5_ifc_traffic_counter_bits {
2758         u8         packets[0x40];
2759
2760         u8         octets[0x40];
2761 };
2762
2763 struct mlx5_ifc_tisc_bits {
2764         u8         strict_lag_tx_port_affinity[0x1];
2765         u8         tls_en[0x1];
2766         u8         reserved_at_1[0x2];
2767         u8         lag_tx_port_affinity[0x04];
2768
2769         u8         reserved_at_8[0x4];
2770         u8         prio[0x4];
2771         u8         reserved_at_10[0x10];
2772
2773         u8         reserved_at_20[0x100];
2774
2775         u8         reserved_at_120[0x8];
2776         u8         transport_domain[0x18];
2777
2778         u8         reserved_at_140[0x8];
2779         u8         underlay_qpn[0x18];
2780
2781         u8         reserved_at_160[0x8];
2782         u8         pd[0x18];
2783
2784         u8         reserved_at_180[0x380];
2785 };
2786
2787 enum {
2788         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2789         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2790 };
2791
2792 enum {
2793         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2794         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2795 };
2796
2797 enum {
2798         MLX5_RX_HASH_FN_NONE           = 0x0,
2799         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2800         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2801 };
2802
2803 enum {
2804         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2805         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2806 };
2807
2808 struct mlx5_ifc_tirc_bits {
2809         u8         reserved_at_0[0x20];
2810
2811         u8         disp_type[0x4];
2812         u8         reserved_at_24[0x1c];
2813
2814         u8         reserved_at_40[0x40];
2815
2816         u8         reserved_at_80[0x4];
2817         u8         lro_timeout_period_usecs[0x10];
2818         u8         lro_enable_mask[0x4];
2819         u8         lro_max_ip_payload_size[0x8];
2820
2821         u8         reserved_at_a0[0x40];
2822
2823         u8         reserved_at_e0[0x8];
2824         u8         inline_rqn[0x18];
2825
2826         u8         rx_hash_symmetric[0x1];
2827         u8         reserved_at_101[0x1];
2828         u8         tunneled_offload_en[0x1];
2829         u8         reserved_at_103[0x5];
2830         u8         indirect_table[0x18];
2831
2832         u8         rx_hash_fn[0x4];
2833         u8         reserved_at_124[0x2];
2834         u8         self_lb_block[0x2];
2835         u8         transport_domain[0x18];
2836
2837         u8         rx_hash_toeplitz_key[10][0x20];
2838
2839         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2840
2841         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2842
2843         u8         reserved_at_2c0[0x4c0];
2844 };
2845
2846 enum {
2847         MLX5_SRQC_STATE_GOOD   = 0x0,
2848         MLX5_SRQC_STATE_ERROR  = 0x1,
2849 };
2850
2851 struct mlx5_ifc_srqc_bits {
2852         u8         state[0x4];
2853         u8         log_srq_size[0x4];
2854         u8         reserved_at_8[0x18];
2855
2856         u8         wq_signature[0x1];
2857         u8         cont_srq[0x1];
2858         u8         reserved_at_22[0x1];
2859         u8         rlky[0x1];
2860         u8         reserved_at_24[0x1];
2861         u8         log_rq_stride[0x3];
2862         u8         xrcd[0x18];
2863
2864         u8         page_offset[0x6];
2865         u8         reserved_at_46[0x2];
2866         u8         cqn[0x18];
2867
2868         u8         reserved_at_60[0x20];
2869
2870         u8         reserved_at_80[0x2];
2871         u8         log_page_size[0x6];
2872         u8         reserved_at_88[0x18];
2873
2874         u8         reserved_at_a0[0x20];
2875
2876         u8         reserved_at_c0[0x8];
2877         u8         pd[0x18];
2878
2879         u8         lwm[0x10];
2880         u8         wqe_cnt[0x10];
2881
2882         u8         reserved_at_100[0x40];
2883
2884         u8         dbr_addr[0x40];
2885
2886         u8         reserved_at_180[0x80];
2887 };
2888
2889 enum {
2890         MLX5_SQC_STATE_RST  = 0x0,
2891         MLX5_SQC_STATE_RDY  = 0x1,
2892         MLX5_SQC_STATE_ERR  = 0x3,
2893 };
2894
2895 struct mlx5_ifc_sqc_bits {
2896         u8         rlky[0x1];
2897         u8         cd_master[0x1];
2898         u8         fre[0x1];
2899         u8         flush_in_error_en[0x1];
2900         u8         allow_multi_pkt_send_wqe[0x1];
2901         u8         min_wqe_inline_mode[0x3];
2902         u8         state[0x4];
2903         u8         reg_umr[0x1];
2904         u8         allow_swp[0x1];
2905         u8         hairpin[0x1];
2906         u8         reserved_at_f[0x11];
2907
2908         u8         reserved_at_20[0x8];
2909         u8         user_index[0x18];
2910
2911         u8         reserved_at_40[0x8];
2912         u8         cqn[0x18];
2913
2914         u8         reserved_at_60[0x8];
2915         u8         hairpin_peer_rq[0x18];
2916
2917         u8         reserved_at_80[0x10];
2918         u8         hairpin_peer_vhca[0x10];
2919
2920         u8         reserved_at_a0[0x50];
2921
2922         u8         packet_pacing_rate_limit_index[0x10];
2923         u8         tis_lst_sz[0x10];
2924         u8         reserved_at_110[0x10];
2925
2926         u8         reserved_at_120[0x40];
2927
2928         u8         reserved_at_160[0x8];
2929         u8         tis_num_0[0x18];
2930
2931         struct mlx5_ifc_wq_bits wq;
2932 };
2933
2934 enum {
2935         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2936         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2937         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2938         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2939 };
2940
2941 struct mlx5_ifc_scheduling_context_bits {
2942         u8         element_type[0x8];
2943         u8         reserved_at_8[0x18];
2944
2945         u8         element_attributes[0x20];
2946
2947         u8         parent_element_id[0x20];
2948
2949         u8         reserved_at_60[0x40];
2950
2951         u8         bw_share[0x20];
2952
2953         u8         max_average_bw[0x20];
2954
2955         u8         reserved_at_e0[0x120];
2956 };
2957
2958 struct mlx5_ifc_rqtc_bits {
2959         u8         reserved_at_0[0xa0];
2960
2961         u8         reserved_at_a0[0x10];
2962         u8         rqt_max_size[0x10];
2963
2964         u8         reserved_at_c0[0x10];
2965         u8         rqt_actual_size[0x10];
2966
2967         u8         reserved_at_e0[0x6a0];
2968
2969         struct mlx5_ifc_rq_num_bits rq_num[0];
2970 };
2971
2972 enum {
2973         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2974         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2975 };
2976
2977 enum {
2978         MLX5_RQC_STATE_RST  = 0x0,
2979         MLX5_RQC_STATE_RDY  = 0x1,
2980         MLX5_RQC_STATE_ERR  = 0x3,
2981 };
2982
2983 struct mlx5_ifc_rqc_bits {
2984         u8         rlky[0x1];
2985         u8         delay_drop_en[0x1];
2986         u8         scatter_fcs[0x1];
2987         u8         vsd[0x1];
2988         u8         mem_rq_type[0x4];
2989         u8         state[0x4];
2990         u8         reserved_at_c[0x1];
2991         u8         flush_in_error_en[0x1];
2992         u8         hairpin[0x1];
2993         u8         reserved_at_f[0x11];
2994
2995         u8         reserved_at_20[0x8];
2996         u8         user_index[0x18];
2997
2998         u8         reserved_at_40[0x8];
2999         u8         cqn[0x18];
3000
3001         u8         counter_set_id[0x8];
3002         u8         reserved_at_68[0x18];
3003
3004         u8         reserved_at_80[0x8];
3005         u8         rmpn[0x18];
3006
3007         u8         reserved_at_a0[0x8];
3008         u8         hairpin_peer_sq[0x18];
3009
3010         u8         reserved_at_c0[0x10];
3011         u8         hairpin_peer_vhca[0x10];
3012
3013         u8         reserved_at_e0[0xa0];
3014
3015         struct mlx5_ifc_wq_bits wq;
3016 };
3017
3018 enum {
3019         MLX5_RMPC_STATE_RDY  = 0x1,
3020         MLX5_RMPC_STATE_ERR  = 0x3,
3021 };
3022
3023 struct mlx5_ifc_rmpc_bits {
3024         u8         reserved_at_0[0x8];
3025         u8         state[0x4];
3026         u8         reserved_at_c[0x14];
3027
3028         u8         basic_cyclic_rcv_wqe[0x1];
3029         u8         reserved_at_21[0x1f];
3030
3031         u8         reserved_at_40[0x140];
3032
3033         struct mlx5_ifc_wq_bits wq;
3034 };
3035
3036 struct mlx5_ifc_nic_vport_context_bits {
3037         u8         reserved_at_0[0x5];
3038         u8         min_wqe_inline_mode[0x3];
3039         u8         reserved_at_8[0x15];
3040         u8         disable_mc_local_lb[0x1];
3041         u8         disable_uc_local_lb[0x1];
3042         u8         roce_en[0x1];
3043
3044         u8         arm_change_event[0x1];
3045         u8         reserved_at_21[0x1a];
3046         u8         event_on_mtu[0x1];
3047         u8         event_on_promisc_change[0x1];
3048         u8         event_on_vlan_change[0x1];
3049         u8         event_on_mc_address_change[0x1];
3050         u8         event_on_uc_address_change[0x1];
3051
3052         u8         reserved_at_40[0xc];
3053
3054         u8         affiliation_criteria[0x4];
3055         u8         affiliated_vhca_id[0x10];
3056
3057         u8         reserved_at_60[0xd0];
3058
3059         u8         mtu[0x10];
3060
3061         u8         system_image_guid[0x40];
3062         u8         port_guid[0x40];
3063         u8         node_guid[0x40];
3064
3065         u8         reserved_at_200[0x140];
3066         u8         qkey_violation_counter[0x10];
3067         u8         reserved_at_350[0x430];
3068
3069         u8         promisc_uc[0x1];
3070         u8         promisc_mc[0x1];
3071         u8         promisc_all[0x1];
3072         u8         reserved_at_783[0x2];
3073         u8         allowed_list_type[0x3];
3074         u8         reserved_at_788[0xc];
3075         u8         allowed_list_size[0xc];
3076
3077         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3078
3079         u8         reserved_at_7e0[0x20];
3080
3081         u8         current_uc_mac_address[0][0x40];
3082 };
3083
3084 enum {
3085         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3086         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3087         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3088         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3089         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3090         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3091 };
3092
3093 struct mlx5_ifc_mkc_bits {
3094         u8         reserved_at_0[0x1];
3095         u8         free[0x1];
3096         u8         reserved_at_2[0x1];
3097         u8         access_mode_4_2[0x3];
3098         u8         reserved_at_6[0x7];
3099         u8         relaxed_ordering_write[0x1];
3100         u8         reserved_at_e[0x1];
3101         u8         small_fence_on_rdma_read_response[0x1];
3102         u8         umr_en[0x1];
3103         u8         a[0x1];
3104         u8         rw[0x1];
3105         u8         rr[0x1];
3106         u8         lw[0x1];
3107         u8         lr[0x1];
3108         u8         access_mode_1_0[0x2];
3109         u8         reserved_at_18[0x8];
3110
3111         u8         qpn[0x18];
3112         u8         mkey_7_0[0x8];
3113
3114         u8         reserved_at_40[0x20];
3115
3116         u8         length64[0x1];
3117         u8         bsf_en[0x1];
3118         u8         sync_umr[0x1];
3119         u8         reserved_at_63[0x2];
3120         u8         expected_sigerr_count[0x1];
3121         u8         reserved_at_66[0x1];
3122         u8         en_rinval[0x1];
3123         u8         pd[0x18];
3124
3125         u8         start_addr[0x40];
3126
3127         u8         len[0x40];
3128
3129         u8         bsf_octword_size[0x20];
3130
3131         u8         reserved_at_120[0x80];
3132
3133         u8         translations_octword_size[0x20];
3134
3135         u8         reserved_at_1c0[0x1b];
3136         u8         log_page_size[0x5];
3137
3138         u8         reserved_at_1e0[0x20];
3139 };
3140
3141 struct mlx5_ifc_pkey_bits {
3142         u8         reserved_at_0[0x10];
3143         u8         pkey[0x10];
3144 };
3145
3146 struct mlx5_ifc_array128_auto_bits {
3147         u8         array128_auto[16][0x8];
3148 };
3149
3150 struct mlx5_ifc_hca_vport_context_bits {
3151         u8         field_select[0x20];
3152
3153         u8         reserved_at_20[0xe0];
3154
3155         u8         sm_virt_aware[0x1];
3156         u8         has_smi[0x1];
3157         u8         has_raw[0x1];
3158         u8         grh_required[0x1];
3159         u8         reserved_at_104[0xc];
3160         u8         port_physical_state[0x4];
3161         u8         vport_state_policy[0x4];
3162         u8         port_state[0x4];
3163         u8         vport_state[0x4];
3164
3165         u8         reserved_at_120[0x20];
3166
3167         u8         system_image_guid[0x40];
3168
3169         u8         port_guid[0x40];
3170
3171         u8         node_guid[0x40];
3172
3173         u8         cap_mask1[0x20];
3174
3175         u8         cap_mask1_field_select[0x20];
3176
3177         u8         cap_mask2[0x20];
3178
3179         u8         cap_mask2_field_select[0x20];
3180
3181         u8         reserved_at_280[0x80];
3182
3183         u8         lid[0x10];
3184         u8         reserved_at_310[0x4];
3185         u8         init_type_reply[0x4];
3186         u8         lmc[0x3];
3187         u8         subnet_timeout[0x5];
3188
3189         u8         sm_lid[0x10];
3190         u8         sm_sl[0x4];
3191         u8         reserved_at_334[0xc];
3192
3193         u8         qkey_violation_counter[0x10];
3194         u8         pkey_violation_counter[0x10];
3195
3196         u8         reserved_at_360[0xca0];
3197 };
3198
3199 struct mlx5_ifc_esw_vport_context_bits {
3200         u8         fdb_to_vport_reg_c[0x1];
3201         u8         reserved_at_1[0x2];
3202         u8         vport_svlan_strip[0x1];
3203         u8         vport_cvlan_strip[0x1];
3204         u8         vport_svlan_insert[0x1];
3205         u8         vport_cvlan_insert[0x2];
3206         u8         fdb_to_vport_reg_c_id[0x8];
3207         u8         reserved_at_10[0x10];
3208
3209         u8         reserved_at_20[0x20];
3210
3211         u8         svlan_cfi[0x1];
3212         u8         svlan_pcp[0x3];
3213         u8         svlan_id[0xc];
3214         u8         cvlan_cfi[0x1];
3215         u8         cvlan_pcp[0x3];
3216         u8         cvlan_id[0xc];
3217
3218         u8         reserved_at_60[0x7a0];
3219 };
3220
3221 enum {
3222         MLX5_EQC_STATUS_OK                = 0x0,
3223         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3224 };
3225
3226 enum {
3227         MLX5_EQC_ST_ARMED  = 0x9,
3228         MLX5_EQC_ST_FIRED  = 0xa,
3229 };
3230
3231 struct mlx5_ifc_eqc_bits {
3232         u8         status[0x4];
3233         u8         reserved_at_4[0x9];
3234         u8         ec[0x1];
3235         u8         oi[0x1];
3236         u8         reserved_at_f[0x5];
3237         u8         st[0x4];
3238         u8         reserved_at_18[0x8];
3239
3240         u8         reserved_at_20[0x20];
3241
3242         u8         reserved_at_40[0x14];
3243         u8         page_offset[0x6];
3244         u8         reserved_at_5a[0x6];
3245
3246         u8         reserved_at_60[0x3];
3247         u8         log_eq_size[0x5];
3248         u8         uar_page[0x18];
3249
3250         u8         reserved_at_80[0x20];
3251
3252         u8         reserved_at_a0[0x18];
3253         u8         intr[0x8];
3254
3255         u8         reserved_at_c0[0x3];
3256         u8         log_page_size[0x5];
3257         u8         reserved_at_c8[0x18];
3258
3259         u8         reserved_at_e0[0x60];
3260
3261         u8         reserved_at_140[0x8];
3262         u8         consumer_counter[0x18];
3263
3264         u8         reserved_at_160[0x8];
3265         u8         producer_counter[0x18];
3266
3267         u8         reserved_at_180[0x80];
3268 };
3269
3270 enum {
3271         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3272         MLX5_DCTC_STATE_DRAINING  = 0x1,
3273         MLX5_DCTC_STATE_DRAINED   = 0x2,
3274 };
3275
3276 enum {
3277         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3278         MLX5_DCTC_CS_RES_NA         = 0x1,
3279         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3280 };
3281
3282 enum {
3283         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3284         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3285         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3286         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3287         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3288 };
3289
3290 struct mlx5_ifc_dctc_bits {
3291         u8         reserved_at_0[0x4];
3292         u8         state[0x4];
3293         u8         reserved_at_8[0x18];
3294
3295         u8         reserved_at_20[0x8];
3296         u8         user_index[0x18];
3297
3298         u8         reserved_at_40[0x8];
3299         u8         cqn[0x18];
3300
3301         u8         counter_set_id[0x8];
3302         u8         atomic_mode[0x4];
3303         u8         rre[0x1];
3304         u8         rwe[0x1];
3305         u8         rae[0x1];
3306         u8         atomic_like_write_en[0x1];
3307         u8         latency_sensitive[0x1];
3308         u8         rlky[0x1];
3309         u8         free_ar[0x1];
3310         u8         reserved_at_73[0xd];
3311
3312         u8         reserved_at_80[0x8];
3313         u8         cs_res[0x8];
3314         u8         reserved_at_90[0x3];
3315         u8         min_rnr_nak[0x5];
3316         u8         reserved_at_98[0x8];
3317
3318         u8         reserved_at_a0[0x8];
3319         u8         srqn_xrqn[0x18];
3320
3321         u8         reserved_at_c0[0x8];
3322         u8         pd[0x18];
3323
3324         u8         tclass[0x8];
3325         u8         reserved_at_e8[0x4];
3326         u8         flow_label[0x14];
3327
3328         u8         dc_access_key[0x40];
3329
3330         u8         reserved_at_140[0x5];
3331         u8         mtu[0x3];
3332         u8         port[0x8];
3333         u8         pkey_index[0x10];
3334
3335         u8         reserved_at_160[0x8];
3336         u8         my_addr_index[0x8];
3337         u8         reserved_at_170[0x8];
3338         u8         hop_limit[0x8];
3339
3340         u8         dc_access_key_violation_count[0x20];
3341
3342         u8         reserved_at_1a0[0x14];
3343         u8         dei_cfi[0x1];
3344         u8         eth_prio[0x3];
3345         u8         ecn[0x2];
3346         u8         dscp[0x6];
3347
3348         u8         reserved_at_1c0[0x40];
3349 };
3350
3351 enum {
3352         MLX5_CQC_STATUS_OK             = 0x0,
3353         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3354         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3355 };
3356
3357 enum {
3358         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3359         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3360 };
3361
3362 enum {
3363         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3364         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3365         MLX5_CQC_ST_FIRED                                 = 0xa,
3366 };
3367
3368 enum {
3369         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3370         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3371         MLX5_CQ_PERIOD_NUM_MODES
3372 };
3373
3374 struct mlx5_ifc_cqc_bits {
3375         u8         status[0x4];
3376         u8         reserved_at_4[0x2];
3377         u8         dbr_umem_valid[0x1];
3378         u8         reserved_at_7[0x1];
3379         u8         cqe_sz[0x3];
3380         u8         cc[0x1];
3381         u8         reserved_at_c[0x1];
3382         u8         scqe_break_moderation_en[0x1];
3383         u8         oi[0x1];
3384         u8         cq_period_mode[0x2];
3385         u8         cqe_comp_en[0x1];
3386         u8         mini_cqe_res_format[0x2];
3387         u8         st[0x4];
3388         u8         reserved_at_18[0x8];
3389
3390         u8         reserved_at_20[0x20];
3391
3392         u8         reserved_at_40[0x14];
3393         u8         page_offset[0x6];
3394         u8         reserved_at_5a[0x6];
3395
3396         u8         reserved_at_60[0x3];
3397         u8         log_cq_size[0x5];
3398         u8         uar_page[0x18];
3399
3400         u8         reserved_at_80[0x4];
3401         u8         cq_period[0xc];
3402         u8         cq_max_count[0x10];
3403
3404         u8         reserved_at_a0[0x18];
3405         u8         c_eqn[0x8];
3406
3407         u8         reserved_at_c0[0x3];
3408         u8         log_page_size[0x5];
3409         u8         reserved_at_c8[0x18];
3410
3411         u8         reserved_at_e0[0x20];
3412
3413         u8         reserved_at_100[0x8];
3414         u8         last_notified_index[0x18];
3415
3416         u8         reserved_at_120[0x8];
3417         u8         last_solicit_index[0x18];
3418
3419         u8         reserved_at_140[0x8];
3420         u8         consumer_counter[0x18];
3421
3422         u8         reserved_at_160[0x8];
3423         u8         producer_counter[0x18];
3424
3425         u8         reserved_at_180[0x40];
3426
3427         u8         dbr_addr[0x40];
3428 };
3429
3430 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3431         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3432         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3433         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3434         u8         reserved_at_0[0x800];
3435 };
3436
3437 struct mlx5_ifc_query_adapter_param_block_bits {
3438         u8         reserved_at_0[0xc0];
3439
3440         u8         reserved_at_c0[0x8];
3441         u8         ieee_vendor_id[0x18];
3442
3443         u8         reserved_at_e0[0x10];
3444         u8         vsd_vendor_id[0x10];
3445
3446         u8         vsd[208][0x8];
3447
3448         u8         vsd_contd_psid[16][0x8];
3449 };
3450
3451 enum {
3452         MLX5_XRQC_STATE_GOOD   = 0x0,
3453         MLX5_XRQC_STATE_ERROR  = 0x1,
3454 };
3455
3456 enum {
3457         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3458         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3459 };
3460
3461 enum {
3462         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3463 };
3464
3465 struct mlx5_ifc_tag_matching_topology_context_bits {
3466         u8         log_matching_list_sz[0x4];
3467         u8         reserved_at_4[0xc];
3468         u8         append_next_index[0x10];
3469
3470         u8         sw_phase_cnt[0x10];
3471         u8         hw_phase_cnt[0x10];
3472
3473         u8         reserved_at_40[0x40];
3474 };
3475
3476 struct mlx5_ifc_xrqc_bits {
3477         u8         state[0x4];
3478         u8         rlkey[0x1];
3479         u8         reserved_at_5[0xf];
3480         u8         topology[0x4];
3481         u8         reserved_at_18[0x4];
3482         u8         offload[0x4];
3483
3484         u8         reserved_at_20[0x8];
3485         u8         user_index[0x18];
3486
3487         u8         reserved_at_40[0x8];
3488         u8         cqn[0x18];
3489
3490         u8         reserved_at_60[0xa0];
3491
3492         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3493
3494         u8         reserved_at_180[0x280];
3495
3496         struct mlx5_ifc_wq_bits wq;
3497 };
3498
3499 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3500         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3501         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3502         u8         reserved_at_0[0x20];
3503 };
3504
3505 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3506         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3507         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3508         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3509         u8         reserved_at_0[0x20];
3510 };
3511
3512 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3513         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3514         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3515         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3516         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3517         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3518         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3519         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3520         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3521         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3522         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3523         u8         reserved_at_0[0x7c0];
3524 };
3525
3526 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3527         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3528         u8         reserved_at_0[0x7c0];
3529 };
3530
3531 union mlx5_ifc_event_auto_bits {
3532         struct mlx5_ifc_comp_event_bits comp_event;
3533         struct mlx5_ifc_dct_events_bits dct_events;
3534         struct mlx5_ifc_qp_events_bits qp_events;
3535         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3536         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3537         struct mlx5_ifc_cq_error_bits cq_error;
3538         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3539         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3540         struct mlx5_ifc_gpio_event_bits gpio_event;
3541         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3542         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3543         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3544         u8         reserved_at_0[0xe0];
3545 };
3546
3547 struct mlx5_ifc_health_buffer_bits {
3548         u8         reserved_at_0[0x100];
3549
3550         u8         assert_existptr[0x20];
3551
3552         u8         assert_callra[0x20];
3553
3554         u8         reserved_at_140[0x40];
3555
3556         u8         fw_version[0x20];
3557
3558         u8         hw_id[0x20];
3559
3560         u8         reserved_at_1c0[0x20];
3561
3562         u8         irisc_index[0x8];
3563         u8         synd[0x8];
3564         u8         ext_synd[0x10];
3565 };
3566
3567 struct mlx5_ifc_register_loopback_control_bits {
3568         u8         no_lb[0x1];
3569         u8         reserved_at_1[0x7];
3570         u8         port[0x8];
3571         u8         reserved_at_10[0x10];
3572
3573         u8         reserved_at_20[0x60];
3574 };
3575
3576 struct mlx5_ifc_vport_tc_element_bits {
3577         u8         traffic_class[0x4];
3578         u8         reserved_at_4[0xc];
3579         u8         vport_number[0x10];
3580 };
3581
3582 struct mlx5_ifc_vport_element_bits {
3583         u8         reserved_at_0[0x10];
3584         u8         vport_number[0x10];
3585 };
3586
3587 enum {
3588         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3589         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3590         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3591 };
3592
3593 struct mlx5_ifc_tsar_element_bits {
3594         u8         reserved_at_0[0x8];
3595         u8         tsar_type[0x8];
3596         u8         reserved_at_10[0x10];
3597 };
3598
3599 enum {
3600         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3601         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3602 };
3603
3604 struct mlx5_ifc_teardown_hca_out_bits {
3605         u8         status[0x8];
3606         u8         reserved_at_8[0x18];
3607
3608         u8         syndrome[0x20];
3609
3610         u8         reserved_at_40[0x3f];
3611
3612         u8         state[0x1];
3613 };
3614
3615 enum {
3616         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3617         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3618         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3619 };
3620
3621 struct mlx5_ifc_teardown_hca_in_bits {
3622         u8         opcode[0x10];
3623         u8         reserved_at_10[0x10];
3624
3625         u8         reserved_at_20[0x10];
3626         u8         op_mod[0x10];
3627
3628         u8         reserved_at_40[0x10];
3629         u8         profile[0x10];
3630
3631         u8         reserved_at_60[0x20];
3632 };
3633
3634 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3635         u8         status[0x8];
3636         u8         reserved_at_8[0x18];
3637
3638         u8         syndrome[0x20];
3639
3640         u8         reserved_at_40[0x40];
3641 };
3642
3643 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3644         u8         opcode[0x10];
3645         u8         uid[0x10];
3646
3647         u8         reserved_at_20[0x10];
3648         u8         op_mod[0x10];
3649
3650         u8         reserved_at_40[0x8];
3651         u8         qpn[0x18];
3652
3653         u8         reserved_at_60[0x20];
3654
3655         u8         opt_param_mask[0x20];
3656
3657         u8         reserved_at_a0[0x20];
3658
3659         struct mlx5_ifc_qpc_bits qpc;
3660
3661         u8         reserved_at_800[0x80];
3662 };
3663
3664 struct mlx5_ifc_sqd2rts_qp_out_bits {
3665         u8         status[0x8];
3666         u8         reserved_at_8[0x18];
3667
3668         u8         syndrome[0x20];
3669
3670         u8         reserved_at_40[0x40];
3671 };
3672
3673 struct mlx5_ifc_sqd2rts_qp_in_bits {
3674         u8         opcode[0x10];
3675         u8         uid[0x10];
3676
3677         u8         reserved_at_20[0x10];
3678         u8         op_mod[0x10];
3679
3680         u8         reserved_at_40[0x8];
3681         u8         qpn[0x18];
3682
3683         u8         reserved_at_60[0x20];
3684
3685         u8         opt_param_mask[0x20];
3686
3687         u8         reserved_at_a0[0x20];
3688
3689         struct mlx5_ifc_qpc_bits qpc;
3690
3691         u8         reserved_at_800[0x80];
3692 };
3693
3694 struct mlx5_ifc_set_roce_address_out_bits {
3695         u8         status[0x8];
3696         u8         reserved_at_8[0x18];
3697
3698         u8         syndrome[0x20];
3699
3700         u8         reserved_at_40[0x40];
3701 };
3702
3703 struct mlx5_ifc_set_roce_address_in_bits {
3704         u8         opcode[0x10];
3705         u8         reserved_at_10[0x10];
3706
3707         u8         reserved_at_20[0x10];
3708         u8         op_mod[0x10];
3709
3710         u8         roce_address_index[0x10];
3711         u8         reserved_at_50[0xc];
3712         u8         vhca_port_num[0x4];
3713
3714         u8         reserved_at_60[0x20];
3715
3716         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3717 };
3718
3719 struct mlx5_ifc_set_mad_demux_out_bits {
3720         u8         status[0x8];
3721         u8         reserved_at_8[0x18];
3722
3723         u8         syndrome[0x20];
3724
3725         u8         reserved_at_40[0x40];
3726 };
3727
3728 enum {
3729         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3730         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3731 };
3732
3733 struct mlx5_ifc_set_mad_demux_in_bits {
3734         u8         opcode[0x10];
3735         u8         reserved_at_10[0x10];
3736
3737         u8         reserved_at_20[0x10];
3738         u8         op_mod[0x10];
3739
3740         u8         reserved_at_40[0x20];
3741
3742         u8         reserved_at_60[0x6];
3743         u8         demux_mode[0x2];
3744         u8         reserved_at_68[0x18];
3745 };
3746
3747 struct mlx5_ifc_set_l2_table_entry_out_bits {
3748         u8         status[0x8];
3749         u8         reserved_at_8[0x18];
3750
3751         u8         syndrome[0x20];
3752
3753         u8         reserved_at_40[0x40];
3754 };
3755
3756 struct mlx5_ifc_set_l2_table_entry_in_bits {
3757         u8         opcode[0x10];
3758         u8         reserved_at_10[0x10];
3759
3760         u8         reserved_at_20[0x10];
3761         u8         op_mod[0x10];
3762
3763         u8         reserved_at_40[0x60];
3764
3765         u8         reserved_at_a0[0x8];
3766         u8         table_index[0x18];
3767
3768         u8         reserved_at_c0[0x20];
3769
3770         u8         reserved_at_e0[0x13];
3771         u8         vlan_valid[0x1];
3772         u8         vlan[0xc];
3773
3774         struct mlx5_ifc_mac_address_layout_bits mac_address;
3775
3776         u8         reserved_at_140[0xc0];
3777 };
3778
3779 struct mlx5_ifc_set_issi_out_bits {
3780         u8         status[0x8];
3781         u8         reserved_at_8[0x18];
3782
3783         u8         syndrome[0x20];
3784
3785         u8         reserved_at_40[0x40];
3786 };
3787
3788 struct mlx5_ifc_set_issi_in_bits {
3789         u8         opcode[0x10];
3790         u8         reserved_at_10[0x10];
3791
3792         u8         reserved_at_20[0x10];
3793         u8         op_mod[0x10];
3794
3795         u8         reserved_at_40[0x10];
3796         u8         current_issi[0x10];
3797
3798         u8         reserved_at_60[0x20];
3799 };
3800
3801 struct mlx5_ifc_set_hca_cap_out_bits {
3802         u8         status[0x8];
3803         u8         reserved_at_8[0x18];
3804
3805         u8         syndrome[0x20];
3806
3807         u8         reserved_at_40[0x40];
3808 };
3809
3810 struct mlx5_ifc_set_hca_cap_in_bits {
3811         u8         opcode[0x10];
3812         u8         reserved_at_10[0x10];
3813
3814         u8         reserved_at_20[0x10];
3815         u8         op_mod[0x10];
3816
3817         u8         reserved_at_40[0x40];
3818
3819         union mlx5_ifc_hca_cap_union_bits capability;
3820 };
3821
3822 enum {
3823         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3824         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3825         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3826         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3827 };
3828
3829 struct mlx5_ifc_set_fte_out_bits {
3830         u8         status[0x8];
3831         u8         reserved_at_8[0x18];
3832
3833         u8         syndrome[0x20];
3834
3835         u8         reserved_at_40[0x40];
3836 };
3837
3838 struct mlx5_ifc_set_fte_in_bits {
3839         u8         opcode[0x10];
3840         u8         reserved_at_10[0x10];
3841
3842         u8         reserved_at_20[0x10];
3843         u8         op_mod[0x10];
3844
3845         u8         other_vport[0x1];
3846         u8         reserved_at_41[0xf];
3847         u8         vport_number[0x10];
3848
3849         u8         reserved_at_60[0x20];
3850
3851         u8         table_type[0x8];
3852         u8         reserved_at_88[0x18];
3853
3854         u8         reserved_at_a0[0x8];
3855         u8         table_id[0x18];
3856
3857         u8         reserved_at_c0[0x18];
3858         u8         modify_enable_mask[0x8];
3859
3860         u8         reserved_at_e0[0x20];
3861
3862         u8         flow_index[0x20];
3863
3864         u8         reserved_at_120[0xe0];
3865
3866         struct mlx5_ifc_flow_context_bits flow_context;
3867 };
3868
3869 struct mlx5_ifc_rts2rts_qp_out_bits {
3870         u8         status[0x8];
3871         u8         reserved_at_8[0x18];
3872
3873         u8         syndrome[0x20];
3874
3875         u8         reserved_at_40[0x40];
3876 };
3877
3878 struct mlx5_ifc_rts2rts_qp_in_bits {
3879         u8         opcode[0x10];
3880         u8         uid[0x10];
3881
3882         u8         reserved_at_20[0x10];
3883         u8         op_mod[0x10];
3884
3885         u8         reserved_at_40[0x8];
3886         u8         qpn[0x18];
3887
3888         u8         reserved_at_60[0x20];
3889
3890         u8         opt_param_mask[0x20];
3891
3892         u8         reserved_at_a0[0x20];
3893
3894         struct mlx5_ifc_qpc_bits qpc;
3895
3896         u8         reserved_at_800[0x80];
3897 };
3898
3899 struct mlx5_ifc_rtr2rts_qp_out_bits {
3900         u8         status[0x8];
3901         u8         reserved_at_8[0x18];
3902
3903         u8         syndrome[0x20];
3904
3905         u8         reserved_at_40[0x40];
3906 };
3907
3908 struct mlx5_ifc_rtr2rts_qp_in_bits {
3909         u8         opcode[0x10];
3910         u8         uid[0x10];
3911
3912         u8         reserved_at_20[0x10];
3913         u8         op_mod[0x10];
3914
3915         u8         reserved_at_40[0x8];
3916         u8         qpn[0x18];
3917
3918         u8         reserved_at_60[0x20];
3919
3920         u8         opt_param_mask[0x20];
3921
3922         u8         reserved_at_a0[0x20];
3923
3924         struct mlx5_ifc_qpc_bits qpc;
3925
3926         u8         reserved_at_800[0x80];
3927 };
3928
3929 struct mlx5_ifc_rst2init_qp_out_bits {
3930         u8         status[0x8];
3931         u8         reserved_at_8[0x18];
3932
3933         u8         syndrome[0x20];
3934
3935         u8         reserved_at_40[0x40];
3936 };
3937
3938 struct mlx5_ifc_rst2init_qp_in_bits {
3939         u8         opcode[0x10];
3940         u8         uid[0x10];
3941
3942         u8         reserved_at_20[0x10];
3943         u8         op_mod[0x10];
3944
3945         u8         reserved_at_40[0x8];
3946         u8         qpn[0x18];
3947
3948         u8         reserved_at_60[0x20];
3949
3950         u8         opt_param_mask[0x20];
3951
3952         u8         reserved_at_a0[0x20];
3953
3954         struct mlx5_ifc_qpc_bits qpc;
3955
3956         u8         reserved_at_800[0x80];
3957 };
3958
3959 struct mlx5_ifc_query_xrq_out_bits {
3960         u8         status[0x8];
3961         u8         reserved_at_8[0x18];
3962
3963         u8         syndrome[0x20];
3964
3965         u8         reserved_at_40[0x40];
3966
3967         struct mlx5_ifc_xrqc_bits xrq_context;
3968 };
3969
3970 struct mlx5_ifc_query_xrq_in_bits {
3971         u8         opcode[0x10];
3972         u8         reserved_at_10[0x10];
3973
3974         u8         reserved_at_20[0x10];
3975         u8         op_mod[0x10];
3976
3977         u8         reserved_at_40[0x8];
3978         u8         xrqn[0x18];
3979
3980         u8         reserved_at_60[0x20];
3981 };
3982
3983 struct mlx5_ifc_query_xrc_srq_out_bits {
3984         u8         status[0x8];
3985         u8         reserved_at_8[0x18];
3986
3987         u8         syndrome[0x20];
3988
3989         u8         reserved_at_40[0x40];
3990
3991         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3992
3993         u8         reserved_at_280[0x600];
3994
3995         u8         pas[0][0x40];
3996 };
3997
3998 struct mlx5_ifc_query_xrc_srq_in_bits {
3999         u8         opcode[0x10];
4000         u8         reserved_at_10[0x10];
4001
4002         u8         reserved_at_20[0x10];
4003         u8         op_mod[0x10];
4004
4005         u8         reserved_at_40[0x8];
4006         u8         xrc_srqn[0x18];
4007
4008         u8         reserved_at_60[0x20];
4009 };
4010
4011 enum {
4012         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4013         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4014 };
4015
4016 struct mlx5_ifc_query_vport_state_out_bits {
4017         u8         status[0x8];
4018         u8         reserved_at_8[0x18];
4019
4020         u8         syndrome[0x20];
4021
4022         u8         reserved_at_40[0x20];
4023
4024         u8         reserved_at_60[0x18];
4025         u8         admin_state[0x4];
4026         u8         state[0x4];
4027 };
4028
4029 enum {
4030         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4031         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4032 };
4033
4034 struct mlx5_ifc_arm_monitor_counter_in_bits {
4035         u8         opcode[0x10];
4036         u8         uid[0x10];
4037
4038         u8         reserved_at_20[0x10];
4039         u8         op_mod[0x10];
4040
4041         u8         reserved_at_40[0x20];
4042
4043         u8         reserved_at_60[0x20];
4044 };
4045
4046 struct mlx5_ifc_arm_monitor_counter_out_bits {
4047         u8         status[0x8];
4048         u8         reserved_at_8[0x18];
4049
4050         u8         syndrome[0x20];
4051
4052         u8         reserved_at_40[0x40];
4053 };
4054
4055 enum {
4056         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4057         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4058 };
4059
4060 enum mlx5_monitor_counter_ppcnt {
4061         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4062         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4063         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4064         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4065         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4066         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4067 };
4068
4069 enum {
4070         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4071 };
4072
4073 struct mlx5_ifc_monitor_counter_output_bits {
4074         u8         reserved_at_0[0x4];
4075         u8         type[0x4];
4076         u8         reserved_at_8[0x8];
4077         u8         counter[0x10];
4078
4079         u8         counter_group_id[0x20];
4080 };
4081
4082 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4083 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4084 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4085                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4086
4087 struct mlx5_ifc_set_monitor_counter_in_bits {
4088         u8         opcode[0x10];
4089         u8         uid[0x10];
4090
4091         u8         reserved_at_20[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         reserved_at_40[0x10];
4095         u8         num_of_counters[0x10];
4096
4097         u8         reserved_at_60[0x20];
4098
4099         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4100 };
4101
4102 struct mlx5_ifc_set_monitor_counter_out_bits {
4103         u8         status[0x8];
4104         u8         reserved_at_8[0x18];
4105
4106         u8         syndrome[0x20];
4107
4108         u8         reserved_at_40[0x40];
4109 };
4110
4111 struct mlx5_ifc_query_vport_state_in_bits {
4112         u8         opcode[0x10];
4113         u8         reserved_at_10[0x10];
4114
4115         u8         reserved_at_20[0x10];
4116         u8         op_mod[0x10];
4117
4118         u8         other_vport[0x1];
4119         u8         reserved_at_41[0xf];
4120         u8         vport_number[0x10];
4121
4122         u8         reserved_at_60[0x20];
4123 };
4124
4125 struct mlx5_ifc_query_vnic_env_out_bits {
4126         u8         status[0x8];
4127         u8         reserved_at_8[0x18];
4128
4129         u8         syndrome[0x20];
4130
4131         u8         reserved_at_40[0x40];
4132
4133         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4134 };
4135
4136 enum {
4137         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4138 };
4139
4140 struct mlx5_ifc_query_vnic_env_in_bits {
4141         u8         opcode[0x10];
4142         u8         reserved_at_10[0x10];
4143
4144         u8         reserved_at_20[0x10];
4145         u8         op_mod[0x10];
4146
4147         u8         other_vport[0x1];
4148         u8         reserved_at_41[0xf];
4149         u8         vport_number[0x10];
4150
4151         u8         reserved_at_60[0x20];
4152 };
4153
4154 struct mlx5_ifc_query_vport_counter_out_bits {
4155         u8         status[0x8];
4156         u8         reserved_at_8[0x18];
4157
4158         u8         syndrome[0x20];
4159
4160         u8         reserved_at_40[0x40];
4161
4162         struct mlx5_ifc_traffic_counter_bits received_errors;
4163
4164         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4165
4166         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4167
4168         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4169
4170         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4171
4172         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4173
4174         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4175
4176         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4177
4178         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4179
4180         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4181
4182         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4183
4184         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4185
4186         u8         reserved_at_680[0xa00];
4187 };
4188
4189 enum {
4190         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4191 };
4192
4193 struct mlx5_ifc_query_vport_counter_in_bits {
4194         u8         opcode[0x10];
4195         u8         reserved_at_10[0x10];
4196
4197         u8         reserved_at_20[0x10];
4198         u8         op_mod[0x10];
4199
4200         u8         other_vport[0x1];
4201         u8         reserved_at_41[0xb];
4202         u8         port_num[0x4];
4203         u8         vport_number[0x10];
4204
4205         u8         reserved_at_60[0x60];
4206
4207         u8         clear[0x1];
4208         u8         reserved_at_c1[0x1f];
4209
4210         u8         reserved_at_e0[0x20];
4211 };
4212
4213 struct mlx5_ifc_query_tis_out_bits {
4214         u8         status[0x8];
4215         u8         reserved_at_8[0x18];
4216
4217         u8         syndrome[0x20];
4218
4219         u8         reserved_at_40[0x40];
4220
4221         struct mlx5_ifc_tisc_bits tis_context;
4222 };
4223
4224 struct mlx5_ifc_query_tis_in_bits {
4225         u8         opcode[0x10];
4226         u8         reserved_at_10[0x10];
4227
4228         u8         reserved_at_20[0x10];
4229         u8         op_mod[0x10];
4230
4231         u8         reserved_at_40[0x8];
4232         u8         tisn[0x18];
4233
4234         u8         reserved_at_60[0x20];
4235 };
4236
4237 struct mlx5_ifc_query_tir_out_bits {
4238         u8         status[0x8];
4239         u8         reserved_at_8[0x18];
4240
4241         u8         syndrome[0x20];
4242
4243         u8         reserved_at_40[0xc0];
4244
4245         struct mlx5_ifc_tirc_bits tir_context;
4246 };
4247
4248 struct mlx5_ifc_query_tir_in_bits {
4249         u8         opcode[0x10];
4250         u8         reserved_at_10[0x10];
4251
4252         u8         reserved_at_20[0x10];
4253         u8         op_mod[0x10];
4254
4255         u8         reserved_at_40[0x8];
4256         u8         tirn[0x18];
4257
4258         u8         reserved_at_60[0x20];
4259 };
4260
4261 struct mlx5_ifc_query_srq_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_at_8[0x18];
4264
4265         u8         syndrome[0x20];
4266
4267         u8         reserved_at_40[0x40];
4268
4269         struct mlx5_ifc_srqc_bits srq_context_entry;
4270
4271         u8         reserved_at_280[0x600];
4272
4273         u8         pas[0][0x40];
4274 };
4275
4276 struct mlx5_ifc_query_srq_in_bits {
4277         u8         opcode[0x10];
4278         u8         reserved_at_10[0x10];
4279
4280         u8         reserved_at_20[0x10];
4281         u8         op_mod[0x10];
4282
4283         u8         reserved_at_40[0x8];
4284         u8         srqn[0x18];
4285
4286         u8         reserved_at_60[0x20];
4287 };
4288
4289 struct mlx5_ifc_query_sq_out_bits {
4290         u8         status[0x8];
4291         u8         reserved_at_8[0x18];
4292
4293         u8         syndrome[0x20];
4294
4295         u8         reserved_at_40[0xc0];
4296
4297         struct mlx5_ifc_sqc_bits sq_context;
4298 };
4299
4300 struct mlx5_ifc_query_sq_in_bits {
4301         u8         opcode[0x10];
4302         u8         reserved_at_10[0x10];
4303
4304         u8         reserved_at_20[0x10];
4305         u8         op_mod[0x10];
4306
4307         u8         reserved_at_40[0x8];
4308         u8         sqn[0x18];
4309
4310         u8         reserved_at_60[0x20];
4311 };
4312
4313 struct mlx5_ifc_query_special_contexts_out_bits {
4314         u8         status[0x8];
4315         u8         reserved_at_8[0x18];
4316
4317         u8         syndrome[0x20];
4318
4319         u8         dump_fill_mkey[0x20];
4320
4321         u8         resd_lkey[0x20];
4322
4323         u8         null_mkey[0x20];
4324
4325         u8         reserved_at_a0[0x60];
4326 };
4327
4328 struct mlx5_ifc_query_special_contexts_in_bits {
4329         u8         opcode[0x10];
4330         u8         reserved_at_10[0x10];
4331
4332         u8         reserved_at_20[0x10];
4333         u8         op_mod[0x10];
4334
4335         u8         reserved_at_40[0x40];
4336 };
4337
4338 struct mlx5_ifc_query_scheduling_element_out_bits {
4339         u8         opcode[0x10];
4340         u8         reserved_at_10[0x10];
4341
4342         u8         reserved_at_20[0x10];
4343         u8         op_mod[0x10];
4344
4345         u8         reserved_at_40[0xc0];
4346
4347         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4348
4349         u8         reserved_at_300[0x100];
4350 };
4351
4352 enum {
4353         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4354 };
4355
4356 struct mlx5_ifc_query_scheduling_element_in_bits {
4357         u8         opcode[0x10];
4358         u8         reserved_at_10[0x10];
4359
4360         u8         reserved_at_20[0x10];
4361         u8         op_mod[0x10];
4362
4363         u8         scheduling_hierarchy[0x8];
4364         u8         reserved_at_48[0x18];
4365
4366         u8         scheduling_element_id[0x20];
4367
4368         u8         reserved_at_80[0x180];
4369 };
4370
4371 struct mlx5_ifc_query_rqt_out_bits {
4372         u8         status[0x8];
4373         u8         reserved_at_8[0x18];
4374
4375         u8         syndrome[0x20];
4376
4377         u8         reserved_at_40[0xc0];
4378
4379         struct mlx5_ifc_rqtc_bits rqt_context;
4380 };
4381
4382 struct mlx5_ifc_query_rqt_in_bits {
4383         u8         opcode[0x10];
4384         u8         reserved_at_10[0x10];
4385
4386         u8         reserved_at_20[0x10];
4387         u8         op_mod[0x10];
4388
4389         u8         reserved_at_40[0x8];
4390         u8         rqtn[0x18];
4391
4392         u8         reserved_at_60[0x20];
4393 };
4394
4395 struct mlx5_ifc_query_rq_out_bits {
4396         u8         status[0x8];
4397         u8         reserved_at_8[0x18];
4398
4399         u8         syndrome[0x20];
4400
4401         u8         reserved_at_40[0xc0];
4402
4403         struct mlx5_ifc_rqc_bits rq_context;
4404 };
4405
4406 struct mlx5_ifc_query_rq_in_bits {
4407         u8         opcode[0x10];
4408         u8         reserved_at_10[0x10];
4409
4410         u8         reserved_at_20[0x10];
4411         u8         op_mod[0x10];
4412
4413         u8         reserved_at_40[0x8];
4414         u8         rqn[0x18];
4415
4416         u8         reserved_at_60[0x20];
4417 };
4418
4419 struct mlx5_ifc_query_roce_address_out_bits {
4420         u8         status[0x8];
4421         u8         reserved_at_8[0x18];
4422
4423         u8         syndrome[0x20];
4424
4425         u8         reserved_at_40[0x40];
4426
4427         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4428 };
4429
4430 struct mlx5_ifc_query_roce_address_in_bits {
4431         u8         opcode[0x10];
4432         u8         reserved_at_10[0x10];
4433
4434         u8         reserved_at_20[0x10];
4435         u8         op_mod[0x10];
4436
4437         u8         roce_address_index[0x10];
4438         u8         reserved_at_50[0xc];
4439         u8         vhca_port_num[0x4];
4440
4441         u8         reserved_at_60[0x20];
4442 };
4443
4444 struct mlx5_ifc_query_rmp_out_bits {
4445         u8         status[0x8];
4446         u8         reserved_at_8[0x18];
4447
4448         u8         syndrome[0x20];
4449
4450         u8         reserved_at_40[0xc0];
4451
4452         struct mlx5_ifc_rmpc_bits rmp_context;
4453 };
4454
4455 struct mlx5_ifc_query_rmp_in_bits {
4456         u8         opcode[0x10];
4457         u8         reserved_at_10[0x10];
4458
4459         u8         reserved_at_20[0x10];
4460         u8         op_mod[0x10];
4461
4462         u8         reserved_at_40[0x8];
4463         u8         rmpn[0x18];
4464
4465         u8         reserved_at_60[0x20];
4466 };
4467
4468 struct mlx5_ifc_query_qp_out_bits {
4469         u8         status[0x8];
4470         u8         reserved_at_8[0x18];
4471
4472         u8         syndrome[0x20];
4473
4474         u8         reserved_at_40[0x40];
4475
4476         u8         opt_param_mask[0x20];
4477
4478         u8         reserved_at_a0[0x20];
4479
4480         struct mlx5_ifc_qpc_bits qpc;
4481
4482         u8         reserved_at_800[0x80];
4483
4484         u8         pas[0][0x40];
4485 };
4486
4487 struct mlx5_ifc_query_qp_in_bits {
4488         u8         opcode[0x10];
4489         u8         reserved_at_10[0x10];
4490
4491         u8         reserved_at_20[0x10];
4492         u8         op_mod[0x10];
4493
4494         u8         reserved_at_40[0x8];
4495         u8         qpn[0x18];
4496
4497         u8         reserved_at_60[0x20];
4498 };
4499
4500 struct mlx5_ifc_query_q_counter_out_bits {
4501         u8         status[0x8];
4502         u8         reserved_at_8[0x18];
4503
4504         u8         syndrome[0x20];
4505
4506         u8         reserved_at_40[0x40];
4507
4508         u8         rx_write_requests[0x20];
4509
4510         u8         reserved_at_a0[0x20];
4511
4512         u8         rx_read_requests[0x20];
4513
4514         u8         reserved_at_e0[0x20];
4515
4516         u8         rx_atomic_requests[0x20];
4517
4518         u8         reserved_at_120[0x20];
4519
4520         u8         rx_dct_connect[0x20];
4521
4522         u8         reserved_at_160[0x20];
4523
4524         u8         out_of_buffer[0x20];
4525
4526         u8         reserved_at_1a0[0x20];
4527
4528         u8         out_of_sequence[0x20];
4529
4530         u8         reserved_at_1e0[0x20];
4531
4532         u8         duplicate_request[0x20];
4533
4534         u8         reserved_at_220[0x20];
4535
4536         u8         rnr_nak_retry_err[0x20];
4537
4538         u8         reserved_at_260[0x20];
4539
4540         u8         packet_seq_err[0x20];
4541
4542         u8         reserved_at_2a0[0x20];
4543
4544         u8         implied_nak_seq_err[0x20];
4545
4546         u8         reserved_at_2e0[0x20];
4547
4548         u8         local_ack_timeout_err[0x20];
4549
4550         u8         reserved_at_320[0xa0];
4551
4552         u8         resp_local_length_error[0x20];
4553
4554         u8         req_local_length_error[0x20];
4555
4556         u8         resp_local_qp_error[0x20];
4557
4558         u8         local_operation_error[0x20];
4559
4560         u8         resp_local_protection[0x20];
4561
4562         u8         req_local_protection[0x20];
4563
4564         u8         resp_cqe_error[0x20];
4565
4566         u8         req_cqe_error[0x20];
4567
4568         u8         req_mw_binding[0x20];
4569
4570         u8         req_bad_response[0x20];
4571
4572         u8         req_remote_invalid_request[0x20];
4573
4574         u8         resp_remote_invalid_request[0x20];
4575
4576         u8         req_remote_access_errors[0x20];
4577
4578         u8         resp_remote_access_errors[0x20];
4579
4580         u8         req_remote_operation_errors[0x20];
4581
4582         u8         req_transport_retries_exceeded[0x20];
4583
4584         u8         cq_overflow[0x20];
4585
4586         u8         resp_cqe_flush_error[0x20];
4587
4588         u8         req_cqe_flush_error[0x20];
4589
4590         u8         reserved_at_620[0x1e0];
4591 };
4592
4593 struct mlx5_ifc_query_q_counter_in_bits {
4594         u8         opcode[0x10];
4595         u8         reserved_at_10[0x10];
4596
4597         u8         reserved_at_20[0x10];
4598         u8         op_mod[0x10];
4599
4600         u8         reserved_at_40[0x80];
4601
4602         u8         clear[0x1];
4603         u8         reserved_at_c1[0x1f];
4604
4605         u8         reserved_at_e0[0x18];
4606         u8         counter_set_id[0x8];
4607 };
4608
4609 struct mlx5_ifc_query_pages_out_bits {
4610         u8         status[0x8];
4611         u8         reserved_at_8[0x18];
4612
4613         u8         syndrome[0x20];
4614
4615         u8         embedded_cpu_function[0x1];
4616         u8         reserved_at_41[0xf];
4617         u8         function_id[0x10];
4618
4619         u8         num_pages[0x20];
4620 };
4621
4622 enum {
4623         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4624         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4625         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4626 };
4627
4628 struct mlx5_ifc_query_pages_in_bits {
4629         u8         opcode[0x10];
4630         u8         reserved_at_10[0x10];
4631
4632         u8         reserved_at_20[0x10];
4633         u8         op_mod[0x10];
4634
4635         u8         embedded_cpu_function[0x1];
4636         u8         reserved_at_41[0xf];
4637         u8         function_id[0x10];
4638
4639         u8         reserved_at_60[0x20];
4640 };
4641
4642 struct mlx5_ifc_query_nic_vport_context_out_bits {
4643         u8         status[0x8];
4644         u8         reserved_at_8[0x18];
4645
4646         u8         syndrome[0x20];
4647
4648         u8         reserved_at_40[0x40];
4649
4650         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4651 };
4652
4653 struct mlx5_ifc_query_nic_vport_context_in_bits {
4654         u8         opcode[0x10];
4655         u8         reserved_at_10[0x10];
4656
4657         u8         reserved_at_20[0x10];
4658         u8         op_mod[0x10];
4659
4660         u8         other_vport[0x1];
4661         u8         reserved_at_41[0xf];
4662         u8         vport_number[0x10];
4663
4664         u8         reserved_at_60[0x5];
4665         u8         allowed_list_type[0x3];
4666         u8         reserved_at_68[0x18];
4667 };
4668
4669 struct mlx5_ifc_query_mkey_out_bits {
4670         u8         status[0x8];
4671         u8         reserved_at_8[0x18];
4672
4673         u8         syndrome[0x20];
4674
4675         u8         reserved_at_40[0x40];
4676
4677         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4678
4679         u8         reserved_at_280[0x600];
4680
4681         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4682
4683         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4684 };
4685
4686 struct mlx5_ifc_query_mkey_in_bits {
4687         u8         opcode[0x10];
4688         u8         reserved_at_10[0x10];
4689
4690         u8         reserved_at_20[0x10];
4691         u8         op_mod[0x10];
4692
4693         u8         reserved_at_40[0x8];
4694         u8         mkey_index[0x18];
4695
4696         u8         pg_access[0x1];
4697         u8         reserved_at_61[0x1f];
4698 };
4699
4700 struct mlx5_ifc_query_mad_demux_out_bits {
4701         u8         status[0x8];
4702         u8         reserved_at_8[0x18];
4703
4704         u8         syndrome[0x20];
4705
4706         u8         reserved_at_40[0x40];
4707
4708         u8         mad_dumux_parameters_block[0x20];
4709 };
4710
4711 struct mlx5_ifc_query_mad_demux_in_bits {
4712         u8         opcode[0x10];
4713         u8         reserved_at_10[0x10];
4714
4715         u8         reserved_at_20[0x10];
4716         u8         op_mod[0x10];
4717
4718         u8         reserved_at_40[0x40];
4719 };
4720
4721 struct mlx5_ifc_query_l2_table_entry_out_bits {
4722         u8         status[0x8];
4723         u8         reserved_at_8[0x18];
4724
4725         u8         syndrome[0x20];
4726
4727         u8         reserved_at_40[0xa0];
4728
4729         u8         reserved_at_e0[0x13];
4730         u8         vlan_valid[0x1];
4731         u8         vlan[0xc];
4732
4733         struct mlx5_ifc_mac_address_layout_bits mac_address;
4734
4735         u8         reserved_at_140[0xc0];
4736 };
4737
4738 struct mlx5_ifc_query_l2_table_entry_in_bits {
4739         u8         opcode[0x10];
4740         u8         reserved_at_10[0x10];
4741
4742         u8         reserved_at_20[0x10];
4743         u8         op_mod[0x10];
4744
4745         u8         reserved_at_40[0x60];
4746
4747         u8         reserved_at_a0[0x8];
4748         u8         table_index[0x18];
4749
4750         u8         reserved_at_c0[0x140];
4751 };
4752
4753 struct mlx5_ifc_query_issi_out_bits {
4754         u8         status[0x8];
4755         u8         reserved_at_8[0x18];
4756
4757         u8         syndrome[0x20];
4758
4759         u8         reserved_at_40[0x10];
4760         u8         current_issi[0x10];
4761
4762         u8         reserved_at_60[0xa0];
4763
4764         u8         reserved_at_100[76][0x8];
4765         u8         supported_issi_dw0[0x20];
4766 };
4767
4768 struct mlx5_ifc_query_issi_in_bits {
4769         u8         opcode[0x10];
4770         u8         reserved_at_10[0x10];
4771
4772         u8         reserved_at_20[0x10];
4773         u8         op_mod[0x10];
4774
4775         u8         reserved_at_40[0x40];
4776 };
4777
4778 struct mlx5_ifc_set_driver_version_out_bits {
4779         u8         status[0x8];
4780         u8         reserved_0[0x18];
4781
4782         u8         syndrome[0x20];
4783         u8         reserved_1[0x40];
4784 };
4785
4786 struct mlx5_ifc_set_driver_version_in_bits {
4787         u8         opcode[0x10];
4788         u8         reserved_0[0x10];
4789
4790         u8         reserved_1[0x10];
4791         u8         op_mod[0x10];
4792
4793         u8         reserved_2[0x40];
4794         u8         driver_version[64][0x8];
4795 };
4796
4797 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4798         u8         status[0x8];
4799         u8         reserved_at_8[0x18];
4800
4801         u8         syndrome[0x20];
4802
4803         u8         reserved_at_40[0x40];
4804
4805         struct mlx5_ifc_pkey_bits pkey[0];
4806 };
4807
4808 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4809         u8         opcode[0x10];
4810         u8         reserved_at_10[0x10];
4811
4812         u8         reserved_at_20[0x10];
4813         u8         op_mod[0x10];
4814
4815         u8         other_vport[0x1];
4816         u8         reserved_at_41[0xb];
4817         u8         port_num[0x4];
4818         u8         vport_number[0x10];
4819
4820         u8         reserved_at_60[0x10];
4821         u8         pkey_index[0x10];
4822 };
4823
4824 enum {
4825         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4826         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4827         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4828 };
4829
4830 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4831         u8         status[0x8];
4832         u8         reserved_at_8[0x18];
4833
4834         u8         syndrome[0x20];
4835
4836         u8         reserved_at_40[0x20];
4837
4838         u8         gids_num[0x10];
4839         u8         reserved_at_70[0x10];
4840
4841         struct mlx5_ifc_array128_auto_bits gid[0];
4842 };
4843
4844 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4845         u8         opcode[0x10];
4846         u8         reserved_at_10[0x10];
4847
4848         u8         reserved_at_20[0x10];
4849         u8         op_mod[0x10];
4850
4851         u8         other_vport[0x1];
4852         u8         reserved_at_41[0xb];
4853         u8         port_num[0x4];
4854         u8         vport_number[0x10];
4855
4856         u8         reserved_at_60[0x10];
4857         u8         gid_index[0x10];
4858 };
4859
4860 struct mlx5_ifc_query_hca_vport_context_out_bits {
4861         u8         status[0x8];
4862         u8         reserved_at_8[0x18];
4863
4864         u8         syndrome[0x20];
4865
4866         u8         reserved_at_40[0x40];
4867
4868         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4869 };
4870
4871 struct mlx5_ifc_query_hca_vport_context_in_bits {
4872         u8         opcode[0x10];
4873         u8         reserved_at_10[0x10];
4874
4875         u8         reserved_at_20[0x10];
4876         u8         op_mod[0x10];
4877
4878         u8         other_vport[0x1];
4879         u8         reserved_at_41[0xb];
4880         u8         port_num[0x4];
4881         u8         vport_number[0x10];
4882
4883         u8         reserved_at_60[0x20];
4884 };
4885
4886 struct mlx5_ifc_query_hca_cap_out_bits {
4887         u8         status[0x8];
4888         u8         reserved_at_8[0x18];
4889
4890         u8         syndrome[0x20];
4891
4892         u8         reserved_at_40[0x40];
4893
4894         union mlx5_ifc_hca_cap_union_bits capability;
4895 };
4896
4897 struct mlx5_ifc_query_hca_cap_in_bits {
4898         u8         opcode[0x10];
4899         u8         reserved_at_10[0x10];
4900
4901         u8         reserved_at_20[0x10];
4902         u8         op_mod[0x10];
4903
4904         u8         reserved_at_40[0x40];
4905 };
4906
4907 struct mlx5_ifc_query_flow_table_out_bits {
4908         u8         status[0x8];
4909         u8         reserved_at_8[0x18];
4910
4911         u8         syndrome[0x20];
4912
4913         u8         reserved_at_40[0x80];
4914
4915         u8         reserved_at_c0[0x8];
4916         u8         level[0x8];
4917         u8         reserved_at_d0[0x8];
4918         u8         log_size[0x8];
4919
4920         u8         reserved_at_e0[0x120];
4921 };
4922
4923 struct mlx5_ifc_query_flow_table_in_bits {
4924         u8         opcode[0x10];
4925         u8         reserved_at_10[0x10];
4926
4927         u8         reserved_at_20[0x10];
4928         u8         op_mod[0x10];
4929
4930         u8         reserved_at_40[0x40];
4931
4932         u8         table_type[0x8];
4933         u8         reserved_at_88[0x18];
4934
4935         u8         reserved_at_a0[0x8];
4936         u8         table_id[0x18];
4937
4938         u8         reserved_at_c0[0x140];
4939 };
4940
4941 struct mlx5_ifc_query_fte_out_bits {
4942         u8         status[0x8];
4943         u8         reserved_at_8[0x18];
4944
4945         u8         syndrome[0x20];
4946
4947         u8         reserved_at_40[0x1c0];
4948
4949         struct mlx5_ifc_flow_context_bits flow_context;
4950 };
4951
4952 struct mlx5_ifc_query_fte_in_bits {
4953         u8         opcode[0x10];
4954         u8         reserved_at_10[0x10];
4955
4956         u8         reserved_at_20[0x10];
4957         u8         op_mod[0x10];
4958
4959         u8         reserved_at_40[0x40];
4960
4961         u8         table_type[0x8];
4962         u8         reserved_at_88[0x18];
4963
4964         u8         reserved_at_a0[0x8];
4965         u8         table_id[0x18];
4966
4967         u8         reserved_at_c0[0x40];
4968
4969         u8         flow_index[0x20];
4970
4971         u8         reserved_at_120[0xe0];
4972 };
4973
4974 enum {
4975         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4976         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4977         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4978         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4979         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
4980 };
4981
4982 struct mlx5_ifc_query_flow_group_out_bits {
4983         u8         status[0x8];
4984         u8         reserved_at_8[0x18];
4985
4986         u8         syndrome[0x20];
4987
4988         u8         reserved_at_40[0xa0];
4989
4990         u8         start_flow_index[0x20];
4991
4992         u8         reserved_at_100[0x20];
4993
4994         u8         end_flow_index[0x20];
4995
4996         u8         reserved_at_140[0xa0];
4997
4998         u8         reserved_at_1e0[0x18];
4999         u8         match_criteria_enable[0x8];
5000
5001         struct mlx5_ifc_fte_match_param_bits match_criteria;
5002
5003         u8         reserved_at_1200[0xe00];
5004 };
5005
5006 struct mlx5_ifc_query_flow_group_in_bits {
5007         u8         opcode[0x10];
5008         u8         reserved_at_10[0x10];
5009
5010         u8         reserved_at_20[0x10];
5011         u8         op_mod[0x10];
5012
5013         u8         reserved_at_40[0x40];
5014
5015         u8         table_type[0x8];
5016         u8         reserved_at_88[0x18];
5017
5018         u8         reserved_at_a0[0x8];
5019         u8         table_id[0x18];
5020
5021         u8         group_id[0x20];
5022
5023         u8         reserved_at_e0[0x120];
5024 };
5025
5026 struct mlx5_ifc_query_flow_counter_out_bits {
5027         u8         status[0x8];
5028         u8         reserved_at_8[0x18];
5029
5030         u8         syndrome[0x20];
5031
5032         u8         reserved_at_40[0x40];
5033
5034         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5035 };
5036
5037 struct mlx5_ifc_query_flow_counter_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_at_10[0x10];
5040
5041         u8         reserved_at_20[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         reserved_at_40[0x80];
5045
5046         u8         clear[0x1];
5047         u8         reserved_at_c1[0xf];
5048         u8         num_of_counters[0x10];
5049
5050         u8         flow_counter_id[0x20];
5051 };
5052
5053 struct mlx5_ifc_query_esw_vport_context_out_bits {
5054         u8         status[0x8];
5055         u8         reserved_at_8[0x18];
5056
5057         u8         syndrome[0x20];
5058
5059         u8         reserved_at_40[0x40];
5060
5061         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5062 };
5063
5064 struct mlx5_ifc_query_esw_vport_context_in_bits {
5065         u8         opcode[0x10];
5066         u8         reserved_at_10[0x10];
5067
5068         u8         reserved_at_20[0x10];
5069         u8         op_mod[0x10];
5070
5071         u8         other_vport[0x1];
5072         u8         reserved_at_41[0xf];
5073         u8         vport_number[0x10];
5074
5075         u8         reserved_at_60[0x20];
5076 };
5077
5078 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5079         u8         status[0x8];
5080         u8         reserved_at_8[0x18];
5081
5082         u8         syndrome[0x20];
5083
5084         u8         reserved_at_40[0x40];
5085 };
5086
5087 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5088         u8         reserved_at_0[0x1b];
5089         u8         fdb_to_vport_reg_c_id[0x1];
5090         u8         vport_cvlan_insert[0x1];
5091         u8         vport_svlan_insert[0x1];
5092         u8         vport_cvlan_strip[0x1];
5093         u8         vport_svlan_strip[0x1];
5094 };
5095
5096 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5097         u8         opcode[0x10];
5098         u8         reserved_at_10[0x10];
5099
5100         u8         reserved_at_20[0x10];
5101         u8         op_mod[0x10];
5102
5103         u8         other_vport[0x1];
5104         u8         reserved_at_41[0xf];
5105         u8         vport_number[0x10];
5106
5107         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5108
5109         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5110 };
5111
5112 struct mlx5_ifc_query_eq_out_bits {
5113         u8         status[0x8];
5114         u8         reserved_at_8[0x18];
5115
5116         u8         syndrome[0x20];
5117
5118         u8         reserved_at_40[0x40];
5119
5120         struct mlx5_ifc_eqc_bits eq_context_entry;
5121
5122         u8         reserved_at_280[0x40];
5123
5124         u8         event_bitmask[0x40];
5125
5126         u8         reserved_at_300[0x580];
5127
5128         u8         pas[0][0x40];
5129 };
5130
5131 struct mlx5_ifc_query_eq_in_bits {
5132         u8         opcode[0x10];
5133         u8         reserved_at_10[0x10];
5134
5135         u8         reserved_at_20[0x10];
5136         u8         op_mod[0x10];
5137
5138         u8         reserved_at_40[0x18];
5139         u8         eq_number[0x8];
5140
5141         u8         reserved_at_60[0x20];
5142 };
5143
5144 struct mlx5_ifc_packet_reformat_context_in_bits {
5145         u8         reserved_at_0[0x5];
5146         u8         reformat_type[0x3];
5147         u8         reserved_at_8[0xe];
5148         u8         reformat_data_size[0xa];
5149
5150         u8         reserved_at_20[0x10];
5151         u8         reformat_data[2][0x8];
5152
5153         u8         more_reformat_data[0][0x8];
5154 };
5155
5156 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5157         u8         status[0x8];
5158         u8         reserved_at_8[0x18];
5159
5160         u8         syndrome[0x20];
5161
5162         u8         reserved_at_40[0xa0];
5163
5164         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5165 };
5166
5167 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5168         u8         opcode[0x10];
5169         u8         reserved_at_10[0x10];
5170
5171         u8         reserved_at_20[0x10];
5172         u8         op_mod[0x10];
5173
5174         u8         packet_reformat_id[0x20];
5175
5176         u8         reserved_at_60[0xa0];
5177 };
5178
5179 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5180         u8         status[0x8];
5181         u8         reserved_at_8[0x18];
5182
5183         u8         syndrome[0x20];
5184
5185         u8         packet_reformat_id[0x20];
5186
5187         u8         reserved_at_60[0x20];
5188 };
5189
5190 enum {
5191         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5192         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5193         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5194         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5195         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5196 };
5197
5198 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5199         u8         opcode[0x10];
5200         u8         reserved_at_10[0x10];
5201
5202         u8         reserved_at_20[0x10];
5203         u8         op_mod[0x10];
5204
5205         u8         reserved_at_40[0xa0];
5206
5207         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5208 };
5209
5210 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5211         u8         status[0x8];
5212         u8         reserved_at_8[0x18];
5213
5214         u8         syndrome[0x20];
5215
5216         u8         reserved_at_40[0x40];
5217 };
5218
5219 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5220         u8         opcode[0x10];
5221         u8         reserved_at_10[0x10];
5222
5223         u8         reserved_20[0x10];
5224         u8         op_mod[0x10];
5225
5226         u8         packet_reformat_id[0x20];
5227
5228         u8         reserved_60[0x20];
5229 };
5230
5231 struct mlx5_ifc_set_action_in_bits {
5232         u8         action_type[0x4];
5233         u8         field[0xc];
5234         u8         reserved_at_10[0x3];
5235         u8         offset[0x5];
5236         u8         reserved_at_18[0x3];
5237         u8         length[0x5];
5238
5239         u8         data[0x20];
5240 };
5241
5242 struct mlx5_ifc_add_action_in_bits {
5243         u8         action_type[0x4];
5244         u8         field[0xc];
5245         u8         reserved_at_10[0x10];
5246
5247         u8         data[0x20];
5248 };
5249
5250 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5251         struct mlx5_ifc_set_action_in_bits set_action_in;
5252         struct mlx5_ifc_add_action_in_bits add_action_in;
5253         u8         reserved_at_0[0x40];
5254 };
5255
5256 enum {
5257         MLX5_ACTION_TYPE_SET   = 0x1,
5258         MLX5_ACTION_TYPE_ADD   = 0x2,
5259 };
5260
5261 enum {
5262         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5263         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5264         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5265         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5266         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5267         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5268         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5269         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5270         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5271         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5272         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5273         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5274         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5275         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5276         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5277         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5278         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5279         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5280         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5281         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5282         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5283         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5284         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5285         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5286         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5287 };
5288
5289 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5290         u8         status[0x8];
5291         u8         reserved_at_8[0x18];
5292
5293         u8         syndrome[0x20];
5294
5295         u8         modify_header_id[0x20];
5296
5297         u8         reserved_at_60[0x20];
5298 };
5299
5300 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5301         u8         opcode[0x10];
5302         u8         reserved_at_10[0x10];
5303
5304         u8         reserved_at_20[0x10];
5305         u8         op_mod[0x10];
5306
5307         u8         reserved_at_40[0x20];
5308
5309         u8         table_type[0x8];
5310         u8         reserved_at_68[0x10];
5311         u8         num_of_actions[0x8];
5312
5313         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5314 };
5315
5316 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5317         u8         status[0x8];
5318         u8         reserved_at_8[0x18];
5319
5320         u8         syndrome[0x20];
5321
5322         u8         reserved_at_40[0x40];
5323 };
5324
5325 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5326         u8         opcode[0x10];
5327         u8         reserved_at_10[0x10];
5328
5329         u8         reserved_at_20[0x10];
5330         u8         op_mod[0x10];
5331
5332         u8         modify_header_id[0x20];
5333
5334         u8         reserved_at_60[0x20];
5335 };
5336
5337 struct mlx5_ifc_query_dct_out_bits {
5338         u8         status[0x8];
5339         u8         reserved_at_8[0x18];
5340
5341         u8         syndrome[0x20];
5342
5343         u8         reserved_at_40[0x40];
5344
5345         struct mlx5_ifc_dctc_bits dct_context_entry;
5346
5347         u8         reserved_at_280[0x180];
5348 };
5349
5350 struct mlx5_ifc_query_dct_in_bits {
5351         u8         opcode[0x10];
5352         u8         reserved_at_10[0x10];
5353
5354         u8         reserved_at_20[0x10];
5355         u8         op_mod[0x10];
5356
5357         u8         reserved_at_40[0x8];
5358         u8         dctn[0x18];
5359
5360         u8         reserved_at_60[0x20];
5361 };
5362
5363 struct mlx5_ifc_query_cq_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_at_8[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         reserved_at_40[0x40];
5370
5371         struct mlx5_ifc_cqc_bits cq_context;
5372
5373         u8         reserved_at_280[0x600];
5374
5375         u8         pas[0][0x40];
5376 };
5377
5378 struct mlx5_ifc_query_cq_in_bits {
5379         u8         opcode[0x10];
5380         u8         reserved_at_10[0x10];
5381
5382         u8         reserved_at_20[0x10];
5383         u8         op_mod[0x10];
5384
5385         u8         reserved_at_40[0x8];
5386         u8         cqn[0x18];
5387
5388         u8         reserved_at_60[0x20];
5389 };
5390
5391 struct mlx5_ifc_query_cong_status_out_bits {
5392         u8         status[0x8];
5393         u8         reserved_at_8[0x18];
5394
5395         u8         syndrome[0x20];
5396
5397         u8         reserved_at_40[0x20];
5398
5399         u8         enable[0x1];
5400         u8         tag_enable[0x1];
5401         u8         reserved_at_62[0x1e];
5402 };
5403
5404 struct mlx5_ifc_query_cong_status_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_at_10[0x10];
5407
5408         u8         reserved_at_20[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_at_40[0x18];
5412         u8         priority[0x4];
5413         u8         cong_protocol[0x4];
5414
5415         u8         reserved_at_60[0x20];
5416 };
5417
5418 struct mlx5_ifc_query_cong_statistics_out_bits {
5419         u8         status[0x8];
5420         u8         reserved_at_8[0x18];
5421
5422         u8         syndrome[0x20];
5423
5424         u8         reserved_at_40[0x40];
5425
5426         u8         rp_cur_flows[0x20];
5427
5428         u8         sum_flows[0x20];
5429
5430         u8         rp_cnp_ignored_high[0x20];
5431
5432         u8         rp_cnp_ignored_low[0x20];
5433
5434         u8         rp_cnp_handled_high[0x20];
5435
5436         u8         rp_cnp_handled_low[0x20];
5437
5438         u8         reserved_at_140[0x100];
5439
5440         u8         time_stamp_high[0x20];
5441
5442         u8         time_stamp_low[0x20];
5443
5444         u8         accumulators_period[0x20];
5445
5446         u8         np_ecn_marked_roce_packets_high[0x20];
5447
5448         u8         np_ecn_marked_roce_packets_low[0x20];
5449
5450         u8         np_cnp_sent_high[0x20];
5451
5452         u8         np_cnp_sent_low[0x20];
5453
5454         u8         reserved_at_320[0x560];
5455 };
5456
5457 struct mlx5_ifc_query_cong_statistics_in_bits {
5458         u8         opcode[0x10];
5459         u8         reserved_at_10[0x10];
5460
5461         u8         reserved_at_20[0x10];
5462         u8         op_mod[0x10];
5463
5464         u8         clear[0x1];
5465         u8         reserved_at_41[0x1f];
5466
5467         u8         reserved_at_60[0x20];
5468 };
5469
5470 struct mlx5_ifc_query_cong_params_out_bits {
5471         u8         status[0x8];
5472         u8         reserved_at_8[0x18];
5473
5474         u8         syndrome[0x20];
5475
5476         u8         reserved_at_40[0x40];
5477
5478         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5479 };
5480
5481 struct mlx5_ifc_query_cong_params_in_bits {
5482         u8         opcode[0x10];
5483         u8         reserved_at_10[0x10];
5484
5485         u8         reserved_at_20[0x10];
5486         u8         op_mod[0x10];
5487
5488         u8         reserved_at_40[0x1c];
5489         u8         cong_protocol[0x4];
5490
5491         u8         reserved_at_60[0x20];
5492 };
5493
5494 struct mlx5_ifc_query_adapter_out_bits {
5495         u8         status[0x8];
5496         u8         reserved_at_8[0x18];
5497
5498         u8         syndrome[0x20];
5499
5500         u8         reserved_at_40[0x40];
5501
5502         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5503 };
5504
5505 struct mlx5_ifc_query_adapter_in_bits {
5506         u8         opcode[0x10];
5507         u8         reserved_at_10[0x10];
5508
5509         u8         reserved_at_20[0x10];
5510         u8         op_mod[0x10];
5511
5512         u8         reserved_at_40[0x40];
5513 };
5514
5515 struct mlx5_ifc_qp_2rst_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_at_8[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_at_40[0x40];
5522 };
5523
5524 struct mlx5_ifc_qp_2rst_in_bits {
5525         u8         opcode[0x10];
5526         u8         uid[0x10];
5527
5528         u8         reserved_at_20[0x10];
5529         u8         op_mod[0x10];
5530
5531         u8         reserved_at_40[0x8];
5532         u8         qpn[0x18];
5533
5534         u8         reserved_at_60[0x20];
5535 };
5536
5537 struct mlx5_ifc_qp_2err_out_bits {
5538         u8         status[0x8];
5539         u8         reserved_at_8[0x18];
5540
5541         u8         syndrome[0x20];
5542
5543         u8         reserved_at_40[0x40];
5544 };
5545
5546 struct mlx5_ifc_qp_2err_in_bits {
5547         u8         opcode[0x10];
5548         u8         uid[0x10];
5549
5550         u8         reserved_at_20[0x10];
5551         u8         op_mod[0x10];
5552
5553         u8         reserved_at_40[0x8];
5554         u8         qpn[0x18];
5555
5556         u8         reserved_at_60[0x20];
5557 };
5558
5559 struct mlx5_ifc_page_fault_resume_out_bits {
5560         u8         status[0x8];
5561         u8         reserved_at_8[0x18];
5562
5563         u8         syndrome[0x20];
5564
5565         u8         reserved_at_40[0x40];
5566 };
5567
5568 struct mlx5_ifc_page_fault_resume_in_bits {
5569         u8         opcode[0x10];
5570         u8         reserved_at_10[0x10];
5571
5572         u8         reserved_at_20[0x10];
5573         u8         op_mod[0x10];
5574
5575         u8         error[0x1];
5576         u8         reserved_at_41[0x4];
5577         u8         page_fault_type[0x3];
5578         u8         wq_number[0x18];
5579
5580         u8         reserved_at_60[0x8];
5581         u8         token[0x18];
5582 };
5583
5584 struct mlx5_ifc_nop_out_bits {
5585         u8         status[0x8];
5586         u8         reserved_at_8[0x18];
5587
5588         u8         syndrome[0x20];
5589
5590         u8         reserved_at_40[0x40];
5591 };
5592
5593 struct mlx5_ifc_nop_in_bits {
5594         u8         opcode[0x10];
5595         u8         reserved_at_10[0x10];
5596
5597         u8         reserved_at_20[0x10];
5598         u8         op_mod[0x10];
5599
5600         u8         reserved_at_40[0x40];
5601 };
5602
5603 struct mlx5_ifc_modify_vport_state_out_bits {
5604         u8         status[0x8];
5605         u8         reserved_at_8[0x18];
5606
5607         u8         syndrome[0x20];
5608
5609         u8         reserved_at_40[0x40];
5610 };
5611
5612 struct mlx5_ifc_modify_vport_state_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_at_10[0x10];
5615
5616         u8         reserved_at_20[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         other_vport[0x1];
5620         u8         reserved_at_41[0xf];
5621         u8         vport_number[0x10];
5622
5623         u8         reserved_at_60[0x18];
5624         u8         admin_state[0x4];
5625         u8         reserved_at_7c[0x4];
5626 };
5627
5628 struct mlx5_ifc_modify_tis_out_bits {
5629         u8         status[0x8];
5630         u8         reserved_at_8[0x18];
5631
5632         u8         syndrome[0x20];
5633
5634         u8         reserved_at_40[0x40];
5635 };
5636
5637 struct mlx5_ifc_modify_tis_bitmask_bits {
5638         u8         reserved_at_0[0x20];
5639
5640         u8         reserved_at_20[0x1d];
5641         u8         lag_tx_port_affinity[0x1];
5642         u8         strict_lag_tx_port_affinity[0x1];
5643         u8         prio[0x1];
5644 };
5645
5646 struct mlx5_ifc_modify_tis_in_bits {
5647         u8         opcode[0x10];
5648         u8         uid[0x10];
5649
5650         u8         reserved_at_20[0x10];
5651         u8         op_mod[0x10];
5652
5653         u8         reserved_at_40[0x8];
5654         u8         tisn[0x18];
5655
5656         u8         reserved_at_60[0x20];
5657
5658         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5659
5660         u8         reserved_at_c0[0x40];
5661
5662         struct mlx5_ifc_tisc_bits ctx;
5663 };
5664
5665 struct mlx5_ifc_modify_tir_bitmask_bits {
5666         u8         reserved_at_0[0x20];
5667
5668         u8         reserved_at_20[0x1b];
5669         u8         self_lb_en[0x1];
5670         u8         reserved_at_3c[0x1];
5671         u8         hash[0x1];
5672         u8         reserved_at_3e[0x1];
5673         u8         lro[0x1];
5674 };
5675
5676 struct mlx5_ifc_modify_tir_out_bits {
5677         u8         status[0x8];
5678         u8         reserved_at_8[0x18];
5679
5680         u8         syndrome[0x20];
5681
5682         u8         reserved_at_40[0x40];
5683 };
5684
5685 struct mlx5_ifc_modify_tir_in_bits {
5686         u8         opcode[0x10];
5687         u8         uid[0x10];
5688
5689         u8         reserved_at_20[0x10];
5690         u8         op_mod[0x10];
5691
5692         u8         reserved_at_40[0x8];
5693         u8         tirn[0x18];
5694
5695         u8         reserved_at_60[0x20];
5696
5697         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5698
5699         u8         reserved_at_c0[0x40];
5700
5701         struct mlx5_ifc_tirc_bits ctx;
5702 };
5703
5704 struct mlx5_ifc_modify_sq_out_bits {
5705         u8         status[0x8];
5706         u8         reserved_at_8[0x18];
5707
5708         u8         syndrome[0x20];
5709
5710         u8         reserved_at_40[0x40];
5711 };
5712
5713 struct mlx5_ifc_modify_sq_in_bits {
5714         u8         opcode[0x10];
5715         u8         uid[0x10];
5716
5717         u8         reserved_at_20[0x10];
5718         u8         op_mod[0x10];
5719
5720         u8         sq_state[0x4];
5721         u8         reserved_at_44[0x4];
5722         u8         sqn[0x18];
5723
5724         u8         reserved_at_60[0x20];
5725
5726         u8         modify_bitmask[0x40];
5727
5728         u8         reserved_at_c0[0x40];
5729
5730         struct mlx5_ifc_sqc_bits ctx;
5731 };
5732
5733 struct mlx5_ifc_modify_scheduling_element_out_bits {
5734         u8         status[0x8];
5735         u8         reserved_at_8[0x18];
5736
5737         u8         syndrome[0x20];
5738
5739         u8         reserved_at_40[0x1c0];
5740 };
5741
5742 enum {
5743         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5744         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5745 };
5746
5747 struct mlx5_ifc_modify_scheduling_element_in_bits {
5748         u8         opcode[0x10];
5749         u8         reserved_at_10[0x10];
5750
5751         u8         reserved_at_20[0x10];
5752         u8         op_mod[0x10];
5753
5754         u8         scheduling_hierarchy[0x8];
5755         u8         reserved_at_48[0x18];
5756
5757         u8         scheduling_element_id[0x20];
5758
5759         u8         reserved_at_80[0x20];
5760
5761         u8         modify_bitmask[0x20];
5762
5763         u8         reserved_at_c0[0x40];
5764
5765         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5766
5767         u8         reserved_at_300[0x100];
5768 };
5769
5770 struct mlx5_ifc_modify_rqt_out_bits {
5771         u8         status[0x8];
5772         u8         reserved_at_8[0x18];
5773
5774         u8         syndrome[0x20];
5775
5776         u8         reserved_at_40[0x40];
5777 };
5778
5779 struct mlx5_ifc_rqt_bitmask_bits {
5780         u8         reserved_at_0[0x20];
5781
5782         u8         reserved_at_20[0x1f];
5783         u8         rqn_list[0x1];
5784 };
5785
5786 struct mlx5_ifc_modify_rqt_in_bits {
5787         u8         opcode[0x10];
5788         u8         uid[0x10];
5789
5790         u8         reserved_at_20[0x10];
5791         u8         op_mod[0x10];
5792
5793         u8         reserved_at_40[0x8];
5794         u8         rqtn[0x18];
5795
5796         u8         reserved_at_60[0x20];
5797
5798         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5799
5800         u8         reserved_at_c0[0x40];
5801
5802         struct mlx5_ifc_rqtc_bits ctx;
5803 };
5804
5805 struct mlx5_ifc_modify_rq_out_bits {
5806         u8         status[0x8];
5807         u8         reserved_at_8[0x18];
5808
5809         u8         syndrome[0x20];
5810
5811         u8         reserved_at_40[0x40];
5812 };
5813
5814 enum {
5815         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5816         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5817         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5818 };
5819
5820 struct mlx5_ifc_modify_rq_in_bits {
5821         u8         opcode[0x10];
5822         u8         uid[0x10];
5823
5824         u8         reserved_at_20[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         rq_state[0x4];
5828         u8         reserved_at_44[0x4];
5829         u8         rqn[0x18];
5830
5831         u8         reserved_at_60[0x20];
5832
5833         u8         modify_bitmask[0x40];
5834
5835         u8         reserved_at_c0[0x40];
5836
5837         struct mlx5_ifc_rqc_bits ctx;
5838 };
5839
5840 struct mlx5_ifc_modify_rmp_out_bits {
5841         u8         status[0x8];
5842         u8         reserved_at_8[0x18];
5843
5844         u8         syndrome[0x20];
5845
5846         u8         reserved_at_40[0x40];
5847 };
5848
5849 struct mlx5_ifc_rmp_bitmask_bits {
5850         u8         reserved_at_0[0x20];
5851
5852         u8         reserved_at_20[0x1f];
5853         u8         lwm[0x1];
5854 };
5855
5856 struct mlx5_ifc_modify_rmp_in_bits {
5857         u8         opcode[0x10];
5858         u8         uid[0x10];
5859
5860         u8         reserved_at_20[0x10];
5861         u8         op_mod[0x10];
5862
5863         u8         rmp_state[0x4];
5864         u8         reserved_at_44[0x4];
5865         u8         rmpn[0x18];
5866
5867         u8         reserved_at_60[0x20];
5868
5869         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5870
5871         u8         reserved_at_c0[0x40];
5872
5873         struct mlx5_ifc_rmpc_bits ctx;
5874 };
5875
5876 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x40];
5883 };
5884
5885 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5886         u8         reserved_at_0[0x12];
5887         u8         affiliation[0x1];
5888         u8         reserved_at_13[0x1];
5889         u8         disable_uc_local_lb[0x1];
5890         u8         disable_mc_local_lb[0x1];
5891         u8         node_guid[0x1];
5892         u8         port_guid[0x1];
5893         u8         min_inline[0x1];
5894         u8         mtu[0x1];
5895         u8         change_event[0x1];
5896         u8         promisc[0x1];
5897         u8         permanent_address[0x1];
5898         u8         addresses_list[0x1];
5899         u8         roce_en[0x1];
5900         u8         reserved_at_1f[0x1];
5901 };
5902
5903 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5904         u8         opcode[0x10];
5905         u8         reserved_at_10[0x10];
5906
5907         u8         reserved_at_20[0x10];
5908         u8         op_mod[0x10];
5909
5910         u8         other_vport[0x1];
5911         u8         reserved_at_41[0xf];
5912         u8         vport_number[0x10];
5913
5914         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5915
5916         u8         reserved_at_80[0x780];
5917
5918         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5919 };
5920
5921 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5922         u8         status[0x8];
5923         u8         reserved_at_8[0x18];
5924
5925         u8         syndrome[0x20];
5926
5927         u8         reserved_at_40[0x40];
5928 };
5929
5930 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5931         u8         opcode[0x10];
5932         u8         reserved_at_10[0x10];
5933
5934         u8         reserved_at_20[0x10];
5935         u8         op_mod[0x10];
5936
5937         u8         other_vport[0x1];
5938         u8         reserved_at_41[0xb];
5939         u8         port_num[0x4];
5940         u8         vport_number[0x10];
5941
5942         u8         reserved_at_60[0x20];
5943
5944         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5945 };
5946
5947 struct mlx5_ifc_modify_cq_out_bits {
5948         u8         status[0x8];
5949         u8         reserved_at_8[0x18];
5950
5951         u8         syndrome[0x20];
5952
5953         u8         reserved_at_40[0x40];
5954 };
5955
5956 enum {
5957         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5958         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5959 };
5960
5961 struct mlx5_ifc_modify_cq_in_bits {
5962         u8         opcode[0x10];
5963         u8         uid[0x10];
5964
5965         u8         reserved_at_20[0x10];
5966         u8         op_mod[0x10];
5967
5968         u8         reserved_at_40[0x8];
5969         u8         cqn[0x18];
5970
5971         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5972
5973         struct mlx5_ifc_cqc_bits cq_context;
5974
5975         u8         reserved_at_280[0x40];
5976
5977         u8         cq_umem_valid[0x1];
5978         u8         reserved_at_2c1[0x5bf];
5979
5980         u8         pas[0][0x40];
5981 };
5982
5983 struct mlx5_ifc_modify_cong_status_out_bits {
5984         u8         status[0x8];
5985         u8         reserved_at_8[0x18];
5986
5987         u8         syndrome[0x20];
5988
5989         u8         reserved_at_40[0x40];
5990 };
5991
5992 struct mlx5_ifc_modify_cong_status_in_bits {
5993         u8         opcode[0x10];
5994         u8         reserved_at_10[0x10];
5995
5996         u8         reserved_at_20[0x10];
5997         u8         op_mod[0x10];
5998
5999         u8         reserved_at_40[0x18];
6000         u8         priority[0x4];
6001         u8         cong_protocol[0x4];
6002
6003         u8         enable[0x1];
6004         u8         tag_enable[0x1];
6005         u8         reserved_at_62[0x1e];
6006 };
6007
6008 struct mlx5_ifc_modify_cong_params_out_bits {
6009         u8         status[0x8];
6010         u8         reserved_at_8[0x18];
6011
6012         u8         syndrome[0x20];
6013
6014         u8         reserved_at_40[0x40];
6015 };
6016
6017 struct mlx5_ifc_modify_cong_params_in_bits {
6018         u8         opcode[0x10];
6019         u8         reserved_at_10[0x10];
6020
6021         u8         reserved_at_20[0x10];
6022         u8         op_mod[0x10];
6023
6024         u8         reserved_at_40[0x1c];
6025         u8         cong_protocol[0x4];
6026
6027         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6028
6029         u8         reserved_at_80[0x80];
6030
6031         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6032 };
6033
6034 struct mlx5_ifc_manage_pages_out_bits {
6035         u8         status[0x8];
6036         u8         reserved_at_8[0x18];
6037
6038         u8         syndrome[0x20];
6039
6040         u8         output_num_entries[0x20];
6041
6042         u8         reserved_at_60[0x20];
6043
6044         u8         pas[0][0x40];
6045 };
6046
6047 enum {
6048         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6049         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6050         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6051 };
6052
6053 struct mlx5_ifc_manage_pages_in_bits {
6054         u8         opcode[0x10];
6055         u8         reserved_at_10[0x10];
6056
6057         u8         reserved_at_20[0x10];
6058         u8         op_mod[0x10];
6059
6060         u8         embedded_cpu_function[0x1];
6061         u8         reserved_at_41[0xf];
6062         u8         function_id[0x10];
6063
6064         u8         input_num_entries[0x20];
6065
6066         u8         pas[0][0x40];
6067 };
6068
6069 struct mlx5_ifc_mad_ifc_out_bits {
6070         u8         status[0x8];
6071         u8         reserved_at_8[0x18];
6072
6073         u8         syndrome[0x20];
6074
6075         u8         reserved_at_40[0x40];
6076
6077         u8         response_mad_packet[256][0x8];
6078 };
6079
6080 struct mlx5_ifc_mad_ifc_in_bits {
6081         u8         opcode[0x10];
6082         u8         reserved_at_10[0x10];
6083
6084         u8         reserved_at_20[0x10];
6085         u8         op_mod[0x10];
6086
6087         u8         remote_lid[0x10];
6088         u8         reserved_at_50[0x8];
6089         u8         port[0x8];
6090
6091         u8         reserved_at_60[0x20];
6092
6093         u8         mad[256][0x8];
6094 };
6095
6096 struct mlx5_ifc_init_hca_out_bits {
6097         u8         status[0x8];
6098         u8         reserved_at_8[0x18];
6099
6100         u8         syndrome[0x20];
6101
6102         u8         reserved_at_40[0x40];
6103 };
6104
6105 struct mlx5_ifc_init_hca_in_bits {
6106         u8         opcode[0x10];
6107         u8         reserved_at_10[0x10];
6108
6109         u8         reserved_at_20[0x10];
6110         u8         op_mod[0x10];
6111
6112         u8         reserved_at_40[0x40];
6113         u8         sw_owner_id[4][0x20];
6114 };
6115
6116 struct mlx5_ifc_init2rtr_qp_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x40];
6123 };
6124
6125 struct mlx5_ifc_init2rtr_qp_in_bits {
6126         u8         opcode[0x10];
6127         u8         uid[0x10];
6128
6129         u8         reserved_at_20[0x10];
6130         u8         op_mod[0x10];
6131
6132         u8         reserved_at_40[0x8];
6133         u8         qpn[0x18];
6134
6135         u8         reserved_at_60[0x20];
6136
6137         u8         opt_param_mask[0x20];
6138
6139         u8         reserved_at_a0[0x20];
6140
6141         struct mlx5_ifc_qpc_bits qpc;
6142
6143         u8         reserved_at_800[0x80];
6144 };
6145
6146 struct mlx5_ifc_init2init_qp_out_bits {
6147         u8         status[0x8];
6148         u8         reserved_at_8[0x18];
6149
6150         u8         syndrome[0x20];
6151
6152         u8         reserved_at_40[0x40];
6153 };
6154
6155 struct mlx5_ifc_init2init_qp_in_bits {
6156         u8         opcode[0x10];
6157         u8         uid[0x10];
6158
6159         u8         reserved_at_20[0x10];
6160         u8         op_mod[0x10];
6161
6162         u8         reserved_at_40[0x8];
6163         u8         qpn[0x18];
6164
6165         u8         reserved_at_60[0x20];
6166
6167         u8         opt_param_mask[0x20];
6168
6169         u8         reserved_at_a0[0x20];
6170
6171         struct mlx5_ifc_qpc_bits qpc;
6172
6173         u8         reserved_at_800[0x80];
6174 };
6175
6176 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6177         u8         status[0x8];
6178         u8         reserved_at_8[0x18];
6179
6180         u8         syndrome[0x20];
6181
6182         u8         reserved_at_40[0x40];
6183
6184         u8         packet_headers_log[128][0x8];
6185
6186         u8         packet_syndrome[64][0x8];
6187 };
6188
6189 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6190         u8         opcode[0x10];
6191         u8         reserved_at_10[0x10];
6192
6193         u8         reserved_at_20[0x10];
6194         u8         op_mod[0x10];
6195
6196         u8         reserved_at_40[0x40];
6197 };
6198
6199 struct mlx5_ifc_gen_eqe_in_bits {
6200         u8         opcode[0x10];
6201         u8         reserved_at_10[0x10];
6202
6203         u8         reserved_at_20[0x10];
6204         u8         op_mod[0x10];
6205
6206         u8         reserved_at_40[0x18];
6207         u8         eq_number[0x8];
6208
6209         u8         reserved_at_60[0x20];
6210
6211         u8         eqe[64][0x8];
6212 };
6213
6214 struct mlx5_ifc_gen_eq_out_bits {
6215         u8         status[0x8];
6216         u8         reserved_at_8[0x18];
6217
6218         u8         syndrome[0x20];
6219
6220         u8         reserved_at_40[0x40];
6221 };
6222
6223 struct mlx5_ifc_enable_hca_out_bits {
6224         u8         status[0x8];
6225         u8         reserved_at_8[0x18];
6226
6227         u8         syndrome[0x20];
6228
6229         u8         reserved_at_40[0x20];
6230 };
6231
6232 struct mlx5_ifc_enable_hca_in_bits {
6233         u8         opcode[0x10];
6234         u8         reserved_at_10[0x10];
6235
6236         u8         reserved_at_20[0x10];
6237         u8         op_mod[0x10];
6238
6239         u8         embedded_cpu_function[0x1];
6240         u8         reserved_at_41[0xf];
6241         u8         function_id[0x10];
6242
6243         u8         reserved_at_60[0x20];
6244 };
6245
6246 struct mlx5_ifc_drain_dct_out_bits {
6247         u8         status[0x8];
6248         u8         reserved_at_8[0x18];
6249
6250         u8         syndrome[0x20];
6251
6252         u8         reserved_at_40[0x40];
6253 };
6254
6255 struct mlx5_ifc_drain_dct_in_bits {
6256         u8         opcode[0x10];
6257         u8         uid[0x10];
6258
6259         u8         reserved_at_20[0x10];
6260         u8         op_mod[0x10];
6261
6262         u8         reserved_at_40[0x8];
6263         u8         dctn[0x18];
6264
6265         u8         reserved_at_60[0x20];
6266 };
6267
6268 struct mlx5_ifc_disable_hca_out_bits {
6269         u8         status[0x8];
6270         u8         reserved_at_8[0x18];
6271
6272         u8         syndrome[0x20];
6273
6274         u8         reserved_at_40[0x20];
6275 };
6276
6277 struct mlx5_ifc_disable_hca_in_bits {
6278         u8         opcode[0x10];
6279         u8         reserved_at_10[0x10];
6280
6281         u8         reserved_at_20[0x10];
6282         u8         op_mod[0x10];
6283
6284         u8         embedded_cpu_function[0x1];
6285         u8         reserved_at_41[0xf];
6286         u8         function_id[0x10];
6287
6288         u8         reserved_at_60[0x20];
6289 };
6290
6291 struct mlx5_ifc_detach_from_mcg_out_bits {
6292         u8         status[0x8];
6293         u8         reserved_at_8[0x18];
6294
6295         u8         syndrome[0x20];
6296
6297         u8         reserved_at_40[0x40];
6298 };
6299
6300 struct mlx5_ifc_detach_from_mcg_in_bits {
6301         u8         opcode[0x10];
6302         u8         uid[0x10];
6303
6304         u8         reserved_at_20[0x10];
6305         u8         op_mod[0x10];
6306
6307         u8         reserved_at_40[0x8];
6308         u8         qpn[0x18];
6309
6310         u8         reserved_at_60[0x20];
6311
6312         u8         multicast_gid[16][0x8];
6313 };
6314
6315 struct mlx5_ifc_destroy_xrq_out_bits {
6316         u8         status[0x8];
6317         u8         reserved_at_8[0x18];
6318
6319         u8         syndrome[0x20];
6320
6321         u8         reserved_at_40[0x40];
6322 };
6323
6324 struct mlx5_ifc_destroy_xrq_in_bits {
6325         u8         opcode[0x10];
6326         u8         uid[0x10];
6327
6328         u8         reserved_at_20[0x10];
6329         u8         op_mod[0x10];
6330
6331         u8         reserved_at_40[0x8];
6332         u8         xrqn[0x18];
6333
6334         u8         reserved_at_60[0x20];
6335 };
6336
6337 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6338         u8         status[0x8];
6339         u8         reserved_at_8[0x18];
6340
6341         u8         syndrome[0x20];
6342
6343         u8         reserved_at_40[0x40];
6344 };
6345
6346 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6347         u8         opcode[0x10];
6348         u8         uid[0x10];
6349
6350         u8         reserved_at_20[0x10];
6351         u8         op_mod[0x10];
6352
6353         u8         reserved_at_40[0x8];
6354         u8         xrc_srqn[0x18];
6355
6356         u8         reserved_at_60[0x20];
6357 };
6358
6359 struct mlx5_ifc_destroy_tis_out_bits {
6360         u8         status[0x8];
6361         u8         reserved_at_8[0x18];
6362
6363         u8         syndrome[0x20];
6364
6365         u8         reserved_at_40[0x40];
6366 };
6367
6368 struct mlx5_ifc_destroy_tis_in_bits {
6369         u8         opcode[0x10];
6370         u8         uid[0x10];
6371
6372         u8         reserved_at_20[0x10];
6373         u8         op_mod[0x10];
6374
6375         u8         reserved_at_40[0x8];
6376         u8         tisn[0x18];
6377
6378         u8         reserved_at_60[0x20];
6379 };
6380
6381 struct mlx5_ifc_destroy_tir_out_bits {
6382         u8         status[0x8];
6383         u8         reserved_at_8[0x18];
6384
6385         u8         syndrome[0x20];
6386
6387         u8         reserved_at_40[0x40];
6388 };
6389
6390 struct mlx5_ifc_destroy_tir_in_bits {
6391         u8         opcode[0x10];
6392         u8         uid[0x10];
6393
6394         u8         reserved_at_20[0x10];
6395         u8         op_mod[0x10];
6396
6397         u8         reserved_at_40[0x8];
6398         u8         tirn[0x18];
6399
6400         u8         reserved_at_60[0x20];
6401 };
6402
6403 struct mlx5_ifc_destroy_srq_out_bits {
6404         u8         status[0x8];
6405         u8         reserved_at_8[0x18];
6406
6407         u8         syndrome[0x20];
6408
6409         u8         reserved_at_40[0x40];
6410 };
6411
6412 struct mlx5_ifc_destroy_srq_in_bits {
6413         u8         opcode[0x10];
6414         u8         uid[0x10];
6415
6416         u8         reserved_at_20[0x10];
6417         u8         op_mod[0x10];
6418
6419         u8         reserved_at_40[0x8];
6420         u8         srqn[0x18];
6421
6422         u8         reserved_at_60[0x20];
6423 };
6424
6425 struct mlx5_ifc_destroy_sq_out_bits {
6426         u8         status[0x8];
6427         u8         reserved_at_8[0x18];
6428
6429         u8         syndrome[0x20];
6430
6431         u8         reserved_at_40[0x40];
6432 };
6433
6434 struct mlx5_ifc_destroy_sq_in_bits {
6435         u8         opcode[0x10];
6436         u8         uid[0x10];
6437
6438         u8         reserved_at_20[0x10];
6439         u8         op_mod[0x10];
6440
6441         u8         reserved_at_40[0x8];
6442         u8         sqn[0x18];
6443
6444         u8         reserved_at_60[0x20];
6445 };
6446
6447 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6448         u8         status[0x8];
6449         u8         reserved_at_8[0x18];
6450
6451         u8         syndrome[0x20];
6452
6453         u8         reserved_at_40[0x1c0];
6454 };
6455
6456 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6457         u8         opcode[0x10];
6458         u8         reserved_at_10[0x10];
6459
6460         u8         reserved_at_20[0x10];
6461         u8         op_mod[0x10];
6462
6463         u8         scheduling_hierarchy[0x8];
6464         u8         reserved_at_48[0x18];
6465
6466         u8         scheduling_element_id[0x20];
6467
6468         u8         reserved_at_80[0x180];
6469 };
6470
6471 struct mlx5_ifc_destroy_rqt_out_bits {
6472         u8         status[0x8];
6473         u8         reserved_at_8[0x18];
6474
6475         u8         syndrome[0x20];
6476
6477         u8         reserved_at_40[0x40];
6478 };
6479
6480 struct mlx5_ifc_destroy_rqt_in_bits {
6481         u8         opcode[0x10];
6482         u8         uid[0x10];
6483
6484         u8         reserved_at_20[0x10];
6485         u8         op_mod[0x10];
6486
6487         u8         reserved_at_40[0x8];
6488         u8         rqtn[0x18];
6489
6490         u8         reserved_at_60[0x20];
6491 };
6492
6493 struct mlx5_ifc_destroy_rq_out_bits {
6494         u8         status[0x8];
6495         u8         reserved_at_8[0x18];
6496
6497         u8         syndrome[0x20];
6498
6499         u8         reserved_at_40[0x40];
6500 };
6501
6502 struct mlx5_ifc_destroy_rq_in_bits {
6503         u8         opcode[0x10];
6504         u8         uid[0x10];
6505
6506         u8         reserved_at_20[0x10];
6507         u8         op_mod[0x10];
6508
6509         u8         reserved_at_40[0x8];
6510         u8         rqn[0x18];
6511
6512         u8         reserved_at_60[0x20];
6513 };
6514
6515 struct mlx5_ifc_set_delay_drop_params_in_bits {
6516         u8         opcode[0x10];
6517         u8         reserved_at_10[0x10];
6518
6519         u8         reserved_at_20[0x10];
6520         u8         op_mod[0x10];
6521
6522         u8         reserved_at_40[0x20];
6523
6524         u8         reserved_at_60[0x10];
6525         u8         delay_drop_timeout[0x10];
6526 };
6527
6528 struct mlx5_ifc_set_delay_drop_params_out_bits {
6529         u8         status[0x8];
6530         u8         reserved_at_8[0x18];
6531
6532         u8         syndrome[0x20];
6533
6534         u8         reserved_at_40[0x40];
6535 };
6536
6537 struct mlx5_ifc_destroy_rmp_out_bits {
6538         u8         status[0x8];
6539         u8         reserved_at_8[0x18];
6540
6541         u8         syndrome[0x20];
6542
6543         u8         reserved_at_40[0x40];
6544 };
6545
6546 struct mlx5_ifc_destroy_rmp_in_bits {
6547         u8         opcode[0x10];
6548         u8         uid[0x10];
6549
6550         u8         reserved_at_20[0x10];
6551         u8         op_mod[0x10];
6552
6553         u8         reserved_at_40[0x8];
6554         u8         rmpn[0x18];
6555
6556         u8         reserved_at_60[0x20];
6557 };
6558
6559 struct mlx5_ifc_destroy_qp_out_bits {
6560         u8         status[0x8];
6561         u8         reserved_at_8[0x18];
6562
6563         u8         syndrome[0x20];
6564
6565         u8         reserved_at_40[0x40];
6566 };
6567
6568 struct mlx5_ifc_destroy_qp_in_bits {
6569         u8         opcode[0x10];
6570         u8         uid[0x10];
6571
6572         u8         reserved_at_20[0x10];
6573         u8         op_mod[0x10];
6574
6575         u8         reserved_at_40[0x8];
6576         u8         qpn[0x18];
6577
6578         u8         reserved_at_60[0x20];
6579 };
6580
6581 struct mlx5_ifc_destroy_psv_out_bits {
6582         u8         status[0x8];
6583         u8         reserved_at_8[0x18];
6584
6585         u8         syndrome[0x20];
6586
6587         u8         reserved_at_40[0x40];
6588 };
6589
6590 struct mlx5_ifc_destroy_psv_in_bits {
6591         u8         opcode[0x10];
6592         u8         reserved_at_10[0x10];
6593
6594         u8         reserved_at_20[0x10];
6595         u8         op_mod[0x10];
6596
6597         u8         reserved_at_40[0x8];
6598         u8         psvn[0x18];
6599
6600         u8         reserved_at_60[0x20];
6601 };
6602
6603 struct mlx5_ifc_destroy_mkey_out_bits {
6604         u8         status[0x8];
6605         u8         reserved_at_8[0x18];
6606
6607         u8         syndrome[0x20];
6608
6609         u8         reserved_at_40[0x40];
6610 };
6611
6612 struct mlx5_ifc_destroy_mkey_in_bits {
6613         u8         opcode[0x10];
6614         u8         reserved_at_10[0x10];
6615
6616         u8         reserved_at_20[0x10];
6617         u8         op_mod[0x10];
6618
6619         u8         reserved_at_40[0x8];
6620         u8         mkey_index[0x18];
6621
6622         u8         reserved_at_60[0x20];
6623 };
6624
6625 struct mlx5_ifc_destroy_flow_table_out_bits {
6626         u8         status[0x8];
6627         u8         reserved_at_8[0x18];
6628
6629         u8         syndrome[0x20];
6630
6631         u8         reserved_at_40[0x40];
6632 };
6633
6634 struct mlx5_ifc_destroy_flow_table_in_bits {
6635         u8         opcode[0x10];
6636         u8         reserved_at_10[0x10];
6637
6638         u8         reserved_at_20[0x10];
6639         u8         op_mod[0x10];
6640
6641         u8         other_vport[0x1];
6642         u8         reserved_at_41[0xf];
6643         u8         vport_number[0x10];
6644
6645         u8         reserved_at_60[0x20];
6646
6647         u8         table_type[0x8];
6648         u8         reserved_at_88[0x18];
6649
6650         u8         reserved_at_a0[0x8];
6651         u8         table_id[0x18];
6652
6653         u8         reserved_at_c0[0x140];
6654 };
6655
6656 struct mlx5_ifc_destroy_flow_group_out_bits {
6657         u8         status[0x8];
6658         u8         reserved_at_8[0x18];
6659
6660         u8         syndrome[0x20];
6661
6662         u8         reserved_at_40[0x40];
6663 };
6664
6665 struct mlx5_ifc_destroy_flow_group_in_bits {
6666         u8         opcode[0x10];
6667         u8         reserved_at_10[0x10];
6668
6669         u8         reserved_at_20[0x10];
6670         u8         op_mod[0x10];
6671
6672         u8         other_vport[0x1];
6673         u8         reserved_at_41[0xf];
6674         u8         vport_number[0x10];
6675
6676         u8         reserved_at_60[0x20];
6677
6678         u8         table_type[0x8];
6679         u8         reserved_at_88[0x18];
6680
6681         u8         reserved_at_a0[0x8];
6682         u8         table_id[0x18];
6683
6684         u8         group_id[0x20];
6685
6686         u8         reserved_at_e0[0x120];
6687 };
6688
6689 struct mlx5_ifc_destroy_eq_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_at_8[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         reserved_at_40[0x40];
6696 };
6697
6698 struct mlx5_ifc_destroy_eq_in_bits {
6699         u8         opcode[0x10];
6700         u8         reserved_at_10[0x10];
6701
6702         u8         reserved_at_20[0x10];
6703         u8         op_mod[0x10];
6704
6705         u8         reserved_at_40[0x18];
6706         u8         eq_number[0x8];
6707
6708         u8         reserved_at_60[0x20];
6709 };
6710
6711 struct mlx5_ifc_destroy_dct_out_bits {
6712         u8         status[0x8];
6713         u8         reserved_at_8[0x18];
6714
6715         u8         syndrome[0x20];
6716
6717         u8         reserved_at_40[0x40];
6718 };
6719
6720 struct mlx5_ifc_destroy_dct_in_bits {
6721         u8         opcode[0x10];
6722         u8         uid[0x10];
6723
6724         u8         reserved_at_20[0x10];
6725         u8         op_mod[0x10];
6726
6727         u8         reserved_at_40[0x8];
6728         u8         dctn[0x18];
6729
6730         u8         reserved_at_60[0x20];
6731 };
6732
6733 struct mlx5_ifc_destroy_cq_out_bits {
6734         u8         status[0x8];
6735         u8         reserved_at_8[0x18];
6736
6737         u8         syndrome[0x20];
6738
6739         u8         reserved_at_40[0x40];
6740 };
6741
6742 struct mlx5_ifc_destroy_cq_in_bits {
6743         u8         opcode[0x10];
6744         u8         uid[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         reserved_at_40[0x8];
6750         u8         cqn[0x18];
6751
6752         u8         reserved_at_60[0x20];
6753 };
6754
6755 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6756         u8         status[0x8];
6757         u8         reserved_at_8[0x18];
6758
6759         u8         syndrome[0x20];
6760
6761         u8         reserved_at_40[0x40];
6762 };
6763
6764 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6765         u8         opcode[0x10];
6766         u8         reserved_at_10[0x10];
6767
6768         u8         reserved_at_20[0x10];
6769         u8         op_mod[0x10];
6770
6771         u8         reserved_at_40[0x20];
6772
6773         u8         reserved_at_60[0x10];
6774         u8         vxlan_udp_port[0x10];
6775 };
6776
6777 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6778         u8         status[0x8];
6779         u8         reserved_at_8[0x18];
6780
6781         u8         syndrome[0x20];
6782
6783         u8         reserved_at_40[0x40];
6784 };
6785
6786 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6787         u8         opcode[0x10];
6788         u8         reserved_at_10[0x10];
6789
6790         u8         reserved_at_20[0x10];
6791         u8         op_mod[0x10];
6792
6793         u8         reserved_at_40[0x60];
6794
6795         u8         reserved_at_a0[0x8];
6796         u8         table_index[0x18];
6797
6798         u8         reserved_at_c0[0x140];
6799 };
6800
6801 struct mlx5_ifc_delete_fte_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_at_40[0x40];
6808 };
6809
6810 struct mlx5_ifc_delete_fte_in_bits {
6811         u8         opcode[0x10];
6812         u8         reserved_at_10[0x10];
6813
6814         u8         reserved_at_20[0x10];
6815         u8         op_mod[0x10];
6816
6817         u8         other_vport[0x1];
6818         u8         reserved_at_41[0xf];
6819         u8         vport_number[0x10];
6820
6821         u8         reserved_at_60[0x20];
6822
6823         u8         table_type[0x8];
6824         u8         reserved_at_88[0x18];
6825
6826         u8         reserved_at_a0[0x8];
6827         u8         table_id[0x18];
6828
6829         u8         reserved_at_c0[0x40];
6830
6831         u8         flow_index[0x20];
6832
6833         u8         reserved_at_120[0xe0];
6834 };
6835
6836 struct mlx5_ifc_dealloc_xrcd_out_bits {
6837         u8         status[0x8];
6838         u8         reserved_at_8[0x18];
6839
6840         u8         syndrome[0x20];
6841
6842         u8         reserved_at_40[0x40];
6843 };
6844
6845 struct mlx5_ifc_dealloc_xrcd_in_bits {
6846         u8         opcode[0x10];
6847         u8         uid[0x10];
6848
6849         u8         reserved_at_20[0x10];
6850         u8         op_mod[0x10];
6851
6852         u8         reserved_at_40[0x8];
6853         u8         xrcd[0x18];
6854
6855         u8         reserved_at_60[0x20];
6856 };
6857
6858 struct mlx5_ifc_dealloc_uar_out_bits {
6859         u8         status[0x8];
6860         u8         reserved_at_8[0x18];
6861
6862         u8         syndrome[0x20];
6863
6864         u8         reserved_at_40[0x40];
6865 };
6866
6867 struct mlx5_ifc_dealloc_uar_in_bits {
6868         u8         opcode[0x10];
6869         u8         reserved_at_10[0x10];
6870
6871         u8         reserved_at_20[0x10];
6872         u8         op_mod[0x10];
6873
6874         u8         reserved_at_40[0x8];
6875         u8         uar[0x18];
6876
6877         u8         reserved_at_60[0x20];
6878 };
6879
6880 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6881         u8         status[0x8];
6882         u8         reserved_at_8[0x18];
6883
6884         u8         syndrome[0x20];
6885
6886         u8         reserved_at_40[0x40];
6887 };
6888
6889 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6890         u8         opcode[0x10];
6891         u8         uid[0x10];
6892
6893         u8         reserved_at_20[0x10];
6894         u8         op_mod[0x10];
6895
6896         u8         reserved_at_40[0x8];
6897         u8         transport_domain[0x18];
6898
6899         u8         reserved_at_60[0x20];
6900 };
6901
6902 struct mlx5_ifc_dealloc_q_counter_out_bits {
6903         u8         status[0x8];
6904         u8         reserved_at_8[0x18];
6905
6906         u8         syndrome[0x20];
6907
6908         u8         reserved_at_40[0x40];
6909 };
6910
6911 struct mlx5_ifc_dealloc_q_counter_in_bits {
6912         u8         opcode[0x10];
6913         u8         reserved_at_10[0x10];
6914
6915         u8         reserved_at_20[0x10];
6916         u8         op_mod[0x10];
6917
6918         u8         reserved_at_40[0x18];
6919         u8         counter_set_id[0x8];
6920
6921         u8         reserved_at_60[0x20];
6922 };
6923
6924 struct mlx5_ifc_dealloc_pd_out_bits {
6925         u8         status[0x8];
6926         u8         reserved_at_8[0x18];
6927
6928         u8         syndrome[0x20];
6929
6930         u8         reserved_at_40[0x40];
6931 };
6932
6933 struct mlx5_ifc_dealloc_pd_in_bits {
6934         u8         opcode[0x10];
6935         u8         uid[0x10];
6936
6937         u8         reserved_at_20[0x10];
6938         u8         op_mod[0x10];
6939
6940         u8         reserved_at_40[0x8];
6941         u8         pd[0x18];
6942
6943         u8         reserved_at_60[0x20];
6944 };
6945
6946 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6947         u8         status[0x8];
6948         u8         reserved_at_8[0x18];
6949
6950         u8         syndrome[0x20];
6951
6952         u8         reserved_at_40[0x40];
6953 };
6954
6955 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6956         u8         opcode[0x10];
6957         u8         reserved_at_10[0x10];
6958
6959         u8         reserved_at_20[0x10];
6960         u8         op_mod[0x10];
6961
6962         u8         flow_counter_id[0x20];
6963
6964         u8         reserved_at_60[0x20];
6965 };
6966
6967 struct mlx5_ifc_create_xrq_out_bits {
6968         u8         status[0x8];
6969         u8         reserved_at_8[0x18];
6970
6971         u8         syndrome[0x20];
6972
6973         u8         reserved_at_40[0x8];
6974         u8         xrqn[0x18];
6975
6976         u8         reserved_at_60[0x20];
6977 };
6978
6979 struct mlx5_ifc_create_xrq_in_bits {
6980         u8         opcode[0x10];
6981         u8         uid[0x10];
6982
6983         u8         reserved_at_20[0x10];
6984         u8         op_mod[0x10];
6985
6986         u8         reserved_at_40[0x40];
6987
6988         struct mlx5_ifc_xrqc_bits xrq_context;
6989 };
6990
6991 struct mlx5_ifc_create_xrc_srq_out_bits {
6992         u8         status[0x8];
6993         u8         reserved_at_8[0x18];
6994
6995         u8         syndrome[0x20];
6996
6997         u8         reserved_at_40[0x8];
6998         u8         xrc_srqn[0x18];
6999
7000         u8         reserved_at_60[0x20];
7001 };
7002
7003 struct mlx5_ifc_create_xrc_srq_in_bits {
7004         u8         opcode[0x10];
7005         u8         uid[0x10];
7006
7007         u8         reserved_at_20[0x10];
7008         u8         op_mod[0x10];
7009
7010         u8         reserved_at_40[0x40];
7011
7012         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7013
7014         u8         reserved_at_280[0x60];
7015
7016         u8         xrc_srq_umem_valid[0x1];
7017         u8         reserved_at_2e1[0x1f];
7018
7019         u8         reserved_at_300[0x580];
7020
7021         u8         pas[0][0x40];
7022 };
7023
7024 struct mlx5_ifc_create_tis_out_bits {
7025         u8         status[0x8];
7026         u8         reserved_at_8[0x18];
7027
7028         u8         syndrome[0x20];
7029
7030         u8         reserved_at_40[0x8];
7031         u8         tisn[0x18];
7032
7033         u8         reserved_at_60[0x20];
7034 };
7035
7036 struct mlx5_ifc_create_tis_in_bits {
7037         u8         opcode[0x10];
7038         u8         uid[0x10];
7039
7040         u8         reserved_at_20[0x10];
7041         u8         op_mod[0x10];
7042
7043         u8         reserved_at_40[0xc0];
7044
7045         struct mlx5_ifc_tisc_bits ctx;
7046 };
7047
7048 struct mlx5_ifc_create_tir_out_bits {
7049         u8         status[0x8];
7050         u8         icm_address_63_40[0x18];
7051
7052         u8         syndrome[0x20];
7053
7054         u8         icm_address_39_32[0x8];
7055         u8         tirn[0x18];
7056
7057         u8         icm_address_31_0[0x20];
7058 };
7059
7060 struct mlx5_ifc_create_tir_in_bits {
7061         u8         opcode[0x10];
7062         u8         uid[0x10];
7063
7064         u8         reserved_at_20[0x10];
7065         u8         op_mod[0x10];
7066
7067         u8         reserved_at_40[0xc0];
7068
7069         struct mlx5_ifc_tirc_bits ctx;
7070 };
7071
7072 struct mlx5_ifc_create_srq_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         srqn[0x18];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 struct mlx5_ifc_create_srq_in_bits {
7085         u8         opcode[0x10];
7086         u8         uid[0x10];
7087
7088         u8         reserved_at_20[0x10];
7089         u8         op_mod[0x10];
7090
7091         u8         reserved_at_40[0x40];
7092
7093         struct mlx5_ifc_srqc_bits srq_context_entry;
7094
7095         u8         reserved_at_280[0x600];
7096
7097         u8         pas[0][0x40];
7098 };
7099
7100 struct mlx5_ifc_create_sq_out_bits {
7101         u8         status[0x8];
7102         u8         reserved_at_8[0x18];
7103
7104         u8         syndrome[0x20];
7105
7106         u8         reserved_at_40[0x8];
7107         u8         sqn[0x18];
7108
7109         u8         reserved_at_60[0x20];
7110 };
7111
7112 struct mlx5_ifc_create_sq_in_bits {
7113         u8         opcode[0x10];
7114         u8         uid[0x10];
7115
7116         u8         reserved_at_20[0x10];
7117         u8         op_mod[0x10];
7118
7119         u8         reserved_at_40[0xc0];
7120
7121         struct mlx5_ifc_sqc_bits ctx;
7122 };
7123
7124 struct mlx5_ifc_create_scheduling_element_out_bits {
7125         u8         status[0x8];
7126         u8         reserved_at_8[0x18];
7127
7128         u8         syndrome[0x20];
7129
7130         u8         reserved_at_40[0x40];
7131
7132         u8         scheduling_element_id[0x20];
7133
7134         u8         reserved_at_a0[0x160];
7135 };
7136
7137 struct mlx5_ifc_create_scheduling_element_in_bits {
7138         u8         opcode[0x10];
7139         u8         reserved_at_10[0x10];
7140
7141         u8         reserved_at_20[0x10];
7142         u8         op_mod[0x10];
7143
7144         u8         scheduling_hierarchy[0x8];
7145         u8         reserved_at_48[0x18];
7146
7147         u8         reserved_at_60[0xa0];
7148
7149         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7150
7151         u8         reserved_at_300[0x100];
7152 };
7153
7154 struct mlx5_ifc_create_rqt_out_bits {
7155         u8         status[0x8];
7156         u8         reserved_at_8[0x18];
7157
7158         u8         syndrome[0x20];
7159
7160         u8         reserved_at_40[0x8];
7161         u8         rqtn[0x18];
7162
7163         u8         reserved_at_60[0x20];
7164 };
7165
7166 struct mlx5_ifc_create_rqt_in_bits {
7167         u8         opcode[0x10];
7168         u8         uid[0x10];
7169
7170         u8         reserved_at_20[0x10];
7171         u8         op_mod[0x10];
7172
7173         u8         reserved_at_40[0xc0];
7174
7175         struct mlx5_ifc_rqtc_bits rqt_context;
7176 };
7177
7178 struct mlx5_ifc_create_rq_out_bits {
7179         u8         status[0x8];
7180         u8         reserved_at_8[0x18];
7181
7182         u8         syndrome[0x20];
7183
7184         u8         reserved_at_40[0x8];
7185         u8         rqn[0x18];
7186
7187         u8         reserved_at_60[0x20];
7188 };
7189
7190 struct mlx5_ifc_create_rq_in_bits {
7191         u8         opcode[0x10];
7192         u8         uid[0x10];
7193
7194         u8         reserved_at_20[0x10];
7195         u8         op_mod[0x10];
7196
7197         u8         reserved_at_40[0xc0];
7198
7199         struct mlx5_ifc_rqc_bits ctx;
7200 };
7201
7202 struct mlx5_ifc_create_rmp_out_bits {
7203         u8         status[0x8];
7204         u8         reserved_at_8[0x18];
7205
7206         u8         syndrome[0x20];
7207
7208         u8         reserved_at_40[0x8];
7209         u8         rmpn[0x18];
7210
7211         u8         reserved_at_60[0x20];
7212 };
7213
7214 struct mlx5_ifc_create_rmp_in_bits {
7215         u8         opcode[0x10];
7216         u8         uid[0x10];
7217
7218         u8         reserved_at_20[0x10];
7219         u8         op_mod[0x10];
7220
7221         u8         reserved_at_40[0xc0];
7222
7223         struct mlx5_ifc_rmpc_bits ctx;
7224 };
7225
7226 struct mlx5_ifc_create_qp_out_bits {
7227         u8         status[0x8];
7228         u8         reserved_at_8[0x18];
7229
7230         u8         syndrome[0x20];
7231
7232         u8         reserved_at_40[0x8];
7233         u8         qpn[0x18];
7234
7235         u8         reserved_at_60[0x20];
7236 };
7237
7238 struct mlx5_ifc_create_qp_in_bits {
7239         u8         opcode[0x10];
7240         u8         uid[0x10];
7241
7242         u8         reserved_at_20[0x10];
7243         u8         op_mod[0x10];
7244
7245         u8         reserved_at_40[0x40];
7246
7247         u8         opt_param_mask[0x20];
7248
7249         u8         reserved_at_a0[0x20];
7250
7251         struct mlx5_ifc_qpc_bits qpc;
7252
7253         u8         reserved_at_800[0x60];
7254
7255         u8         wq_umem_valid[0x1];
7256         u8         reserved_at_861[0x1f];
7257
7258         u8         pas[0][0x40];
7259 };
7260
7261 struct mlx5_ifc_create_psv_out_bits {
7262         u8         status[0x8];
7263         u8         reserved_at_8[0x18];
7264
7265         u8         syndrome[0x20];
7266
7267         u8         reserved_at_40[0x40];
7268
7269         u8         reserved_at_80[0x8];
7270         u8         psv0_index[0x18];
7271
7272         u8         reserved_at_a0[0x8];
7273         u8         psv1_index[0x18];
7274
7275         u8         reserved_at_c0[0x8];
7276         u8         psv2_index[0x18];
7277
7278         u8         reserved_at_e0[0x8];
7279         u8         psv3_index[0x18];
7280 };
7281
7282 struct mlx5_ifc_create_psv_in_bits {
7283         u8         opcode[0x10];
7284         u8         reserved_at_10[0x10];
7285
7286         u8         reserved_at_20[0x10];
7287         u8         op_mod[0x10];
7288
7289         u8         num_psv[0x4];
7290         u8         reserved_at_44[0x4];
7291         u8         pd[0x18];
7292
7293         u8         reserved_at_60[0x20];
7294 };
7295
7296 struct mlx5_ifc_create_mkey_out_bits {
7297         u8         status[0x8];
7298         u8         reserved_at_8[0x18];
7299
7300         u8         syndrome[0x20];
7301
7302         u8         reserved_at_40[0x8];
7303         u8         mkey_index[0x18];
7304
7305         u8         reserved_at_60[0x20];
7306 };
7307
7308 struct mlx5_ifc_create_mkey_in_bits {
7309         u8         opcode[0x10];
7310         u8         reserved_at_10[0x10];
7311
7312         u8         reserved_at_20[0x10];
7313         u8         op_mod[0x10];
7314
7315         u8         reserved_at_40[0x20];
7316
7317         u8         pg_access[0x1];
7318         u8         mkey_umem_valid[0x1];
7319         u8         reserved_at_62[0x1e];
7320
7321         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7322
7323         u8         reserved_at_280[0x80];
7324
7325         u8         translations_octword_actual_size[0x20];
7326
7327         u8         reserved_at_320[0x560];
7328
7329         u8         klm_pas_mtt[0][0x20];
7330 };
7331
7332 struct mlx5_ifc_create_flow_table_out_bits {
7333         u8         status[0x8];
7334         u8         reserved_at_8[0x18];
7335
7336         u8         syndrome[0x20];
7337
7338         u8         reserved_at_40[0x8];
7339         u8         table_id[0x18];
7340
7341         u8         reserved_at_60[0x20];
7342 };
7343
7344 struct mlx5_ifc_flow_table_context_bits {
7345         u8         reformat_en[0x1];
7346         u8         decap_en[0x1];
7347         u8         reserved_at_2[0x1];
7348         u8         termination_table[0x1];
7349         u8         table_miss_action[0x4];
7350         u8         level[0x8];
7351         u8         reserved_at_10[0x8];
7352         u8         log_size[0x8];
7353
7354         u8         reserved_at_20[0x8];
7355         u8         table_miss_id[0x18];
7356
7357         u8         reserved_at_40[0x8];
7358         u8         lag_master_next_table_id[0x18];
7359
7360         u8         reserved_at_60[0xe0];
7361 };
7362
7363 struct mlx5_ifc_create_flow_table_in_bits {
7364         u8         opcode[0x10];
7365         u8         reserved_at_10[0x10];
7366
7367         u8         reserved_at_20[0x10];
7368         u8         op_mod[0x10];
7369
7370         u8         other_vport[0x1];
7371         u8         reserved_at_41[0xf];
7372         u8         vport_number[0x10];
7373
7374         u8         reserved_at_60[0x20];
7375
7376         u8         table_type[0x8];
7377         u8         reserved_at_88[0x18];
7378
7379         u8         reserved_at_a0[0x20];
7380
7381         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7382 };
7383
7384 struct mlx5_ifc_create_flow_group_out_bits {
7385         u8         status[0x8];
7386         u8         reserved_at_8[0x18];
7387
7388         u8         syndrome[0x20];
7389
7390         u8         reserved_at_40[0x8];
7391         u8         group_id[0x18];
7392
7393         u8         reserved_at_60[0x20];
7394 };
7395
7396 enum {
7397         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7398         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7399         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7400         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7401 };
7402
7403 struct mlx5_ifc_create_flow_group_in_bits {
7404         u8         opcode[0x10];
7405         u8         reserved_at_10[0x10];
7406
7407         u8         reserved_at_20[0x10];
7408         u8         op_mod[0x10];
7409
7410         u8         other_vport[0x1];
7411         u8         reserved_at_41[0xf];
7412         u8         vport_number[0x10];
7413
7414         u8         reserved_at_60[0x20];
7415
7416         u8         table_type[0x8];
7417         u8         reserved_at_88[0x18];
7418
7419         u8         reserved_at_a0[0x8];
7420         u8         table_id[0x18];
7421
7422         u8         source_eswitch_owner_vhca_id_valid[0x1];
7423
7424         u8         reserved_at_c1[0x1f];
7425
7426         u8         start_flow_index[0x20];
7427
7428         u8         reserved_at_100[0x20];
7429
7430         u8         end_flow_index[0x20];
7431
7432         u8         reserved_at_140[0xa0];
7433
7434         u8         reserved_at_1e0[0x18];
7435         u8         match_criteria_enable[0x8];
7436
7437         struct mlx5_ifc_fte_match_param_bits match_criteria;
7438
7439         u8         reserved_at_1200[0xe00];
7440 };
7441
7442 struct mlx5_ifc_create_eq_out_bits {
7443         u8         status[0x8];
7444         u8         reserved_at_8[0x18];
7445
7446         u8         syndrome[0x20];
7447
7448         u8         reserved_at_40[0x18];
7449         u8         eq_number[0x8];
7450
7451         u8         reserved_at_60[0x20];
7452 };
7453
7454 struct mlx5_ifc_create_eq_in_bits {
7455         u8         opcode[0x10];
7456         u8         uid[0x10];
7457
7458         u8         reserved_at_20[0x10];
7459         u8         op_mod[0x10];
7460
7461         u8         reserved_at_40[0x40];
7462
7463         struct mlx5_ifc_eqc_bits eq_context_entry;
7464
7465         u8         reserved_at_280[0x40];
7466
7467         u8         event_bitmask[4][0x40];
7468
7469         u8         reserved_at_3c0[0x4c0];
7470
7471         u8         pas[0][0x40];
7472 };
7473
7474 struct mlx5_ifc_create_dct_out_bits {
7475         u8         status[0x8];
7476         u8         reserved_at_8[0x18];
7477
7478         u8         syndrome[0x20];
7479
7480         u8         reserved_at_40[0x8];
7481         u8         dctn[0x18];
7482
7483         u8         reserved_at_60[0x20];
7484 };
7485
7486 struct mlx5_ifc_create_dct_in_bits {
7487         u8         opcode[0x10];
7488         u8         uid[0x10];
7489
7490         u8         reserved_at_20[0x10];
7491         u8         op_mod[0x10];
7492
7493         u8         reserved_at_40[0x40];
7494
7495         struct mlx5_ifc_dctc_bits dct_context_entry;
7496
7497         u8         reserved_at_280[0x180];
7498 };
7499
7500 struct mlx5_ifc_create_cq_out_bits {
7501         u8         status[0x8];
7502         u8         reserved_at_8[0x18];
7503
7504         u8         syndrome[0x20];
7505
7506         u8         reserved_at_40[0x8];
7507         u8         cqn[0x18];
7508
7509         u8         reserved_at_60[0x20];
7510 };
7511
7512 struct mlx5_ifc_create_cq_in_bits {
7513         u8         opcode[0x10];
7514         u8         uid[0x10];
7515
7516         u8         reserved_at_20[0x10];
7517         u8         op_mod[0x10];
7518
7519         u8         reserved_at_40[0x40];
7520
7521         struct mlx5_ifc_cqc_bits cq_context;
7522
7523         u8         reserved_at_280[0x60];
7524
7525         u8         cq_umem_valid[0x1];
7526         u8         reserved_at_2e1[0x59f];
7527
7528         u8         pas[0][0x40];
7529 };
7530
7531 struct mlx5_ifc_config_int_moderation_out_bits {
7532         u8         status[0x8];
7533         u8         reserved_at_8[0x18];
7534
7535         u8         syndrome[0x20];
7536
7537         u8         reserved_at_40[0x4];
7538         u8         min_delay[0xc];
7539         u8         int_vector[0x10];
7540
7541         u8         reserved_at_60[0x20];
7542 };
7543
7544 enum {
7545         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7546         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7547 };
7548
7549 struct mlx5_ifc_config_int_moderation_in_bits {
7550         u8         opcode[0x10];
7551         u8         reserved_at_10[0x10];
7552
7553         u8         reserved_at_20[0x10];
7554         u8         op_mod[0x10];
7555
7556         u8         reserved_at_40[0x4];
7557         u8         min_delay[0xc];
7558         u8         int_vector[0x10];
7559
7560         u8         reserved_at_60[0x20];
7561 };
7562
7563 struct mlx5_ifc_attach_to_mcg_out_bits {
7564         u8         status[0x8];
7565         u8         reserved_at_8[0x18];
7566
7567         u8         syndrome[0x20];
7568
7569         u8         reserved_at_40[0x40];
7570 };
7571
7572 struct mlx5_ifc_attach_to_mcg_in_bits {
7573         u8         opcode[0x10];
7574         u8         uid[0x10];
7575
7576         u8         reserved_at_20[0x10];
7577         u8         op_mod[0x10];
7578
7579         u8         reserved_at_40[0x8];
7580         u8         qpn[0x18];
7581
7582         u8         reserved_at_60[0x20];
7583
7584         u8         multicast_gid[16][0x8];
7585 };
7586
7587 struct mlx5_ifc_arm_xrq_out_bits {
7588         u8         status[0x8];
7589         u8         reserved_at_8[0x18];
7590
7591         u8         syndrome[0x20];
7592
7593         u8         reserved_at_40[0x40];
7594 };
7595
7596 struct mlx5_ifc_arm_xrq_in_bits {
7597         u8         opcode[0x10];
7598         u8         reserved_at_10[0x10];
7599
7600         u8         reserved_at_20[0x10];
7601         u8         op_mod[0x10];
7602
7603         u8         reserved_at_40[0x8];
7604         u8         xrqn[0x18];
7605
7606         u8         reserved_at_60[0x10];
7607         u8         lwm[0x10];
7608 };
7609
7610 struct mlx5_ifc_arm_xrc_srq_out_bits {
7611         u8         status[0x8];
7612         u8         reserved_at_8[0x18];
7613
7614         u8         syndrome[0x20];
7615
7616         u8         reserved_at_40[0x40];
7617 };
7618
7619 enum {
7620         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7621 };
7622
7623 struct mlx5_ifc_arm_xrc_srq_in_bits {
7624         u8         opcode[0x10];
7625         u8         uid[0x10];
7626
7627         u8         reserved_at_20[0x10];
7628         u8         op_mod[0x10];
7629
7630         u8         reserved_at_40[0x8];
7631         u8         xrc_srqn[0x18];
7632
7633         u8         reserved_at_60[0x10];
7634         u8         lwm[0x10];
7635 };
7636
7637 struct mlx5_ifc_arm_rq_out_bits {
7638         u8         status[0x8];
7639         u8         reserved_at_8[0x18];
7640
7641         u8         syndrome[0x20];
7642
7643         u8         reserved_at_40[0x40];
7644 };
7645
7646 enum {
7647         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7648         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7649 };
7650
7651 struct mlx5_ifc_arm_rq_in_bits {
7652         u8         opcode[0x10];
7653         u8         uid[0x10];
7654
7655         u8         reserved_at_20[0x10];
7656         u8         op_mod[0x10];
7657
7658         u8         reserved_at_40[0x8];
7659         u8         srq_number[0x18];
7660
7661         u8         reserved_at_60[0x10];
7662         u8         lwm[0x10];
7663 };
7664
7665 struct mlx5_ifc_arm_dct_out_bits {
7666         u8         status[0x8];
7667         u8         reserved_at_8[0x18];
7668
7669         u8         syndrome[0x20];
7670
7671         u8         reserved_at_40[0x40];
7672 };
7673
7674 struct mlx5_ifc_arm_dct_in_bits {
7675         u8         opcode[0x10];
7676         u8         reserved_at_10[0x10];
7677
7678         u8         reserved_at_20[0x10];
7679         u8         op_mod[0x10];
7680
7681         u8         reserved_at_40[0x8];
7682         u8         dct_number[0x18];
7683
7684         u8         reserved_at_60[0x20];
7685 };
7686
7687 struct mlx5_ifc_alloc_xrcd_out_bits {
7688         u8         status[0x8];
7689         u8         reserved_at_8[0x18];
7690
7691         u8         syndrome[0x20];
7692
7693         u8         reserved_at_40[0x8];
7694         u8         xrcd[0x18];
7695
7696         u8         reserved_at_60[0x20];
7697 };
7698
7699 struct mlx5_ifc_alloc_xrcd_in_bits {
7700         u8         opcode[0x10];
7701         u8         uid[0x10];
7702
7703         u8         reserved_at_20[0x10];
7704         u8         op_mod[0x10];
7705
7706         u8         reserved_at_40[0x40];
7707 };
7708
7709 struct mlx5_ifc_alloc_uar_out_bits {
7710         u8         status[0x8];
7711         u8         reserved_at_8[0x18];
7712
7713         u8         syndrome[0x20];
7714
7715         u8         reserved_at_40[0x8];
7716         u8         uar[0x18];
7717
7718         u8         reserved_at_60[0x20];
7719 };
7720
7721 struct mlx5_ifc_alloc_uar_in_bits {
7722         u8         opcode[0x10];
7723         u8         reserved_at_10[0x10];
7724
7725         u8         reserved_at_20[0x10];
7726         u8         op_mod[0x10];
7727
7728         u8         reserved_at_40[0x40];
7729 };
7730
7731 struct mlx5_ifc_alloc_transport_domain_out_bits {
7732         u8         status[0x8];
7733         u8         reserved_at_8[0x18];
7734
7735         u8         syndrome[0x20];
7736
7737         u8         reserved_at_40[0x8];
7738         u8         transport_domain[0x18];
7739
7740         u8         reserved_at_60[0x20];
7741 };
7742
7743 struct mlx5_ifc_alloc_transport_domain_in_bits {
7744         u8         opcode[0x10];
7745         u8         uid[0x10];
7746
7747         u8         reserved_at_20[0x10];
7748         u8         op_mod[0x10];
7749
7750         u8         reserved_at_40[0x40];
7751 };
7752
7753 struct mlx5_ifc_alloc_q_counter_out_bits {
7754         u8         status[0x8];
7755         u8         reserved_at_8[0x18];
7756
7757         u8         syndrome[0x20];
7758
7759         u8         reserved_at_40[0x18];
7760         u8         counter_set_id[0x8];
7761
7762         u8         reserved_at_60[0x20];
7763 };
7764
7765 struct mlx5_ifc_alloc_q_counter_in_bits {
7766         u8         opcode[0x10];
7767         u8         uid[0x10];
7768
7769         u8         reserved_at_20[0x10];
7770         u8         op_mod[0x10];
7771
7772         u8         reserved_at_40[0x40];
7773 };
7774
7775 struct mlx5_ifc_alloc_pd_out_bits {
7776         u8         status[0x8];
7777         u8         reserved_at_8[0x18];
7778
7779         u8         syndrome[0x20];
7780
7781         u8         reserved_at_40[0x8];
7782         u8         pd[0x18];
7783
7784         u8         reserved_at_60[0x20];
7785 };
7786
7787 struct mlx5_ifc_alloc_pd_in_bits {
7788         u8         opcode[0x10];
7789         u8         uid[0x10];
7790
7791         u8         reserved_at_20[0x10];
7792         u8         op_mod[0x10];
7793
7794         u8         reserved_at_40[0x40];
7795 };
7796
7797 struct mlx5_ifc_alloc_flow_counter_out_bits {
7798         u8         status[0x8];
7799         u8         reserved_at_8[0x18];
7800
7801         u8         syndrome[0x20];
7802
7803         u8         flow_counter_id[0x20];
7804
7805         u8         reserved_at_60[0x20];
7806 };
7807
7808 struct mlx5_ifc_alloc_flow_counter_in_bits {
7809         u8         opcode[0x10];
7810         u8         reserved_at_10[0x10];
7811
7812         u8         reserved_at_20[0x10];
7813         u8         op_mod[0x10];
7814
7815         u8         reserved_at_40[0x40];
7816 };
7817
7818 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7819         u8         status[0x8];
7820         u8         reserved_at_8[0x18];
7821
7822         u8         syndrome[0x20];
7823
7824         u8         reserved_at_40[0x40];
7825 };
7826
7827 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7828         u8         opcode[0x10];
7829         u8         reserved_at_10[0x10];
7830
7831         u8         reserved_at_20[0x10];
7832         u8         op_mod[0x10];
7833
7834         u8         reserved_at_40[0x20];
7835
7836         u8         reserved_at_60[0x10];
7837         u8         vxlan_udp_port[0x10];
7838 };
7839
7840 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7841         u8         status[0x8];
7842         u8         reserved_at_8[0x18];
7843
7844         u8         syndrome[0x20];
7845
7846         u8         reserved_at_40[0x40];
7847 };
7848
7849 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7850         u8         opcode[0x10];
7851         u8         reserved_at_10[0x10];
7852
7853         u8         reserved_at_20[0x10];
7854         u8         op_mod[0x10];
7855
7856         u8         reserved_at_40[0x10];
7857         u8         rate_limit_index[0x10];
7858
7859         u8         reserved_at_60[0x20];
7860
7861         u8         rate_limit[0x20];
7862
7863         u8         burst_upper_bound[0x20];
7864
7865         u8         reserved_at_c0[0x10];
7866         u8         typical_packet_size[0x10];
7867
7868         u8         reserved_at_e0[0x120];
7869 };
7870
7871 struct mlx5_ifc_access_register_out_bits {
7872         u8         status[0x8];
7873         u8         reserved_at_8[0x18];
7874
7875         u8         syndrome[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878
7879         u8         register_data[0][0x20];
7880 };
7881
7882 enum {
7883         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7884         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7885 };
7886
7887 struct mlx5_ifc_access_register_in_bits {
7888         u8         opcode[0x10];
7889         u8         reserved_at_10[0x10];
7890
7891         u8         reserved_at_20[0x10];
7892         u8         op_mod[0x10];
7893
7894         u8         reserved_at_40[0x10];
7895         u8         register_id[0x10];
7896
7897         u8         argument[0x20];
7898
7899         u8         register_data[0][0x20];
7900 };
7901
7902 struct mlx5_ifc_sltp_reg_bits {
7903         u8         status[0x4];
7904         u8         version[0x4];
7905         u8         local_port[0x8];
7906         u8         pnat[0x2];
7907         u8         reserved_at_12[0x2];
7908         u8         lane[0x4];
7909         u8         reserved_at_18[0x8];
7910
7911         u8         reserved_at_20[0x20];
7912
7913         u8         reserved_at_40[0x7];
7914         u8         polarity[0x1];
7915         u8         ob_tap0[0x8];
7916         u8         ob_tap1[0x8];
7917         u8         ob_tap2[0x8];
7918
7919         u8         reserved_at_60[0xc];
7920         u8         ob_preemp_mode[0x4];
7921         u8         ob_reg[0x8];
7922         u8         ob_bias[0x8];
7923
7924         u8         reserved_at_80[0x20];
7925 };
7926
7927 struct mlx5_ifc_slrg_reg_bits {
7928         u8         status[0x4];
7929         u8         version[0x4];
7930         u8         local_port[0x8];
7931         u8         pnat[0x2];
7932         u8         reserved_at_12[0x2];
7933         u8         lane[0x4];
7934         u8         reserved_at_18[0x8];
7935
7936         u8         time_to_link_up[0x10];
7937         u8         reserved_at_30[0xc];
7938         u8         grade_lane_speed[0x4];
7939
7940         u8         grade_version[0x8];
7941         u8         grade[0x18];
7942
7943         u8         reserved_at_60[0x4];
7944         u8         height_grade_type[0x4];
7945         u8         height_grade[0x18];
7946
7947         u8         height_dz[0x10];
7948         u8         height_dv[0x10];
7949
7950         u8         reserved_at_a0[0x10];
7951         u8         height_sigma[0x10];
7952
7953         u8         reserved_at_c0[0x20];
7954
7955         u8         reserved_at_e0[0x4];
7956         u8         phase_grade_type[0x4];
7957         u8         phase_grade[0x18];
7958
7959         u8         reserved_at_100[0x8];
7960         u8         phase_eo_pos[0x8];
7961         u8         reserved_at_110[0x8];
7962         u8         phase_eo_neg[0x8];
7963
7964         u8         ffe_set_tested[0x10];
7965         u8         test_errors_per_lane[0x10];
7966 };
7967
7968 struct mlx5_ifc_pvlc_reg_bits {
7969         u8         reserved_at_0[0x8];
7970         u8         local_port[0x8];
7971         u8         reserved_at_10[0x10];
7972
7973         u8         reserved_at_20[0x1c];
7974         u8         vl_hw_cap[0x4];
7975
7976         u8         reserved_at_40[0x1c];
7977         u8         vl_admin[0x4];
7978
7979         u8         reserved_at_60[0x1c];
7980         u8         vl_operational[0x4];
7981 };
7982
7983 struct mlx5_ifc_pude_reg_bits {
7984         u8         swid[0x8];
7985         u8         local_port[0x8];
7986         u8         reserved_at_10[0x4];
7987         u8         admin_status[0x4];
7988         u8         reserved_at_18[0x4];
7989         u8         oper_status[0x4];
7990
7991         u8         reserved_at_20[0x60];
7992 };
7993
7994 struct mlx5_ifc_ptys_reg_bits {
7995         u8         reserved_at_0[0x1];
7996         u8         an_disable_admin[0x1];
7997         u8         an_disable_cap[0x1];
7998         u8         reserved_at_3[0x5];
7999         u8         local_port[0x8];
8000         u8         reserved_at_10[0xd];
8001         u8         proto_mask[0x3];
8002
8003         u8         an_status[0x4];
8004         u8         reserved_at_24[0x1c];
8005
8006         u8         ext_eth_proto_capability[0x20];
8007
8008         u8         eth_proto_capability[0x20];
8009
8010         u8         ib_link_width_capability[0x10];
8011         u8         ib_proto_capability[0x10];
8012
8013         u8         ext_eth_proto_admin[0x20];
8014
8015         u8         eth_proto_admin[0x20];
8016
8017         u8         ib_link_width_admin[0x10];
8018         u8         ib_proto_admin[0x10];
8019
8020         u8         ext_eth_proto_oper[0x20];
8021
8022         u8         eth_proto_oper[0x20];
8023
8024         u8         ib_link_width_oper[0x10];
8025         u8         ib_proto_oper[0x10];
8026
8027         u8         reserved_at_160[0x1c];
8028         u8         connector_type[0x4];
8029
8030         u8         eth_proto_lp_advertise[0x20];
8031
8032         u8         reserved_at_1a0[0x60];
8033 };
8034
8035 struct mlx5_ifc_mlcr_reg_bits {
8036         u8         reserved_at_0[0x8];
8037         u8         local_port[0x8];
8038         u8         reserved_at_10[0x20];
8039
8040         u8         beacon_duration[0x10];
8041         u8         reserved_at_40[0x10];
8042
8043         u8         beacon_remain[0x10];
8044 };
8045
8046 struct mlx5_ifc_ptas_reg_bits {
8047         u8         reserved_at_0[0x20];
8048
8049         u8         algorithm_options[0x10];
8050         u8         reserved_at_30[0x4];
8051         u8         repetitions_mode[0x4];
8052         u8         num_of_repetitions[0x8];
8053
8054         u8         grade_version[0x8];
8055         u8         height_grade_type[0x4];
8056         u8         phase_grade_type[0x4];
8057         u8         height_grade_weight[0x8];
8058         u8         phase_grade_weight[0x8];
8059
8060         u8         gisim_measure_bits[0x10];
8061         u8         adaptive_tap_measure_bits[0x10];
8062
8063         u8         ber_bath_high_error_threshold[0x10];
8064         u8         ber_bath_mid_error_threshold[0x10];
8065
8066         u8         ber_bath_low_error_threshold[0x10];
8067         u8         one_ratio_high_threshold[0x10];
8068
8069         u8         one_ratio_high_mid_threshold[0x10];
8070         u8         one_ratio_low_mid_threshold[0x10];
8071
8072         u8         one_ratio_low_threshold[0x10];
8073         u8         ndeo_error_threshold[0x10];
8074
8075         u8         mixer_offset_step_size[0x10];
8076         u8         reserved_at_110[0x8];
8077         u8         mix90_phase_for_voltage_bath[0x8];
8078
8079         u8         mixer_offset_start[0x10];
8080         u8         mixer_offset_end[0x10];
8081
8082         u8         reserved_at_140[0x15];
8083         u8         ber_test_time[0xb];
8084 };
8085
8086 struct mlx5_ifc_pspa_reg_bits {
8087         u8         swid[0x8];
8088         u8         local_port[0x8];
8089         u8         sub_port[0x8];
8090         u8         reserved_at_18[0x8];
8091
8092         u8         reserved_at_20[0x20];
8093 };
8094
8095 struct mlx5_ifc_pqdr_reg_bits {
8096         u8         reserved_at_0[0x8];
8097         u8         local_port[0x8];
8098         u8         reserved_at_10[0x5];
8099         u8         prio[0x3];
8100         u8         reserved_at_18[0x6];
8101         u8         mode[0x2];
8102
8103         u8         reserved_at_20[0x20];
8104
8105         u8         reserved_at_40[0x10];
8106         u8         min_threshold[0x10];
8107
8108         u8         reserved_at_60[0x10];
8109         u8         max_threshold[0x10];
8110
8111         u8         reserved_at_80[0x10];
8112         u8         mark_probability_denominator[0x10];
8113
8114         u8         reserved_at_a0[0x60];
8115 };
8116
8117 struct mlx5_ifc_ppsc_reg_bits {
8118         u8         reserved_at_0[0x8];
8119         u8         local_port[0x8];
8120         u8         reserved_at_10[0x10];
8121
8122         u8         reserved_at_20[0x60];
8123
8124         u8         reserved_at_80[0x1c];
8125         u8         wrps_admin[0x4];
8126
8127         u8         reserved_at_a0[0x1c];
8128         u8         wrps_status[0x4];
8129
8130         u8         reserved_at_c0[0x8];
8131         u8         up_threshold[0x8];
8132         u8         reserved_at_d0[0x8];
8133         u8         down_threshold[0x8];
8134
8135         u8         reserved_at_e0[0x20];
8136
8137         u8         reserved_at_100[0x1c];
8138         u8         srps_admin[0x4];
8139
8140         u8         reserved_at_120[0x1c];
8141         u8         srps_status[0x4];
8142
8143         u8         reserved_at_140[0x40];
8144 };
8145
8146 struct mlx5_ifc_pplr_reg_bits {
8147         u8         reserved_at_0[0x8];
8148         u8         local_port[0x8];
8149         u8         reserved_at_10[0x10];
8150
8151         u8         reserved_at_20[0x8];
8152         u8         lb_cap[0x8];
8153         u8         reserved_at_30[0x8];
8154         u8         lb_en[0x8];
8155 };
8156
8157 struct mlx5_ifc_pplm_reg_bits {
8158         u8         reserved_at_0[0x8];
8159         u8         local_port[0x8];
8160         u8         reserved_at_10[0x10];
8161
8162         u8         reserved_at_20[0x20];
8163
8164         u8         port_profile_mode[0x8];
8165         u8         static_port_profile[0x8];
8166         u8         active_port_profile[0x8];
8167         u8         reserved_at_58[0x8];
8168
8169         u8         retransmission_active[0x8];
8170         u8         fec_mode_active[0x18];
8171
8172         u8         rs_fec_correction_bypass_cap[0x4];
8173         u8         reserved_at_84[0x8];
8174         u8         fec_override_cap_56g[0x4];
8175         u8         fec_override_cap_100g[0x4];
8176         u8         fec_override_cap_50g[0x4];
8177         u8         fec_override_cap_25g[0x4];
8178         u8         fec_override_cap_10g_40g[0x4];
8179
8180         u8         rs_fec_correction_bypass_admin[0x4];
8181         u8         reserved_at_a4[0x8];
8182         u8         fec_override_admin_56g[0x4];
8183         u8         fec_override_admin_100g[0x4];
8184         u8         fec_override_admin_50g[0x4];
8185         u8         fec_override_admin_25g[0x4];
8186         u8         fec_override_admin_10g_40g[0x4];
8187 };
8188
8189 struct mlx5_ifc_ppcnt_reg_bits {
8190         u8         swid[0x8];
8191         u8         local_port[0x8];
8192         u8         pnat[0x2];
8193         u8         reserved_at_12[0x8];
8194         u8         grp[0x6];
8195
8196         u8         clr[0x1];
8197         u8         reserved_at_21[0x1c];
8198         u8         prio_tc[0x3];
8199
8200         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8201 };
8202
8203 struct mlx5_ifc_mpein_reg_bits {
8204         u8         reserved_at_0[0x2];
8205         u8         depth[0x6];
8206         u8         pcie_index[0x8];
8207         u8         node[0x8];
8208         u8         reserved_at_18[0x8];
8209
8210         u8         capability_mask[0x20];
8211
8212         u8         reserved_at_40[0x8];
8213         u8         link_width_enabled[0x8];
8214         u8         link_speed_enabled[0x10];
8215
8216         u8         lane0_physical_position[0x8];
8217         u8         link_width_active[0x8];
8218         u8         link_speed_active[0x10];
8219
8220         u8         num_of_pfs[0x10];
8221         u8         num_of_vfs[0x10];
8222
8223         u8         bdf0[0x10];
8224         u8         reserved_at_b0[0x10];
8225
8226         u8         max_read_request_size[0x4];
8227         u8         max_payload_size[0x4];
8228         u8         reserved_at_c8[0x5];
8229         u8         pwr_status[0x3];
8230         u8         port_type[0x4];
8231         u8         reserved_at_d4[0xb];
8232         u8         lane_reversal[0x1];
8233
8234         u8         reserved_at_e0[0x14];
8235         u8         pci_power[0xc];
8236
8237         u8         reserved_at_100[0x20];
8238
8239         u8         device_status[0x10];
8240         u8         port_state[0x8];
8241         u8         reserved_at_138[0x8];
8242
8243         u8         reserved_at_140[0x10];
8244         u8         receiver_detect_result[0x10];
8245
8246         u8         reserved_at_160[0x20];
8247 };
8248
8249 struct mlx5_ifc_mpcnt_reg_bits {
8250         u8         reserved_at_0[0x8];
8251         u8         pcie_index[0x8];
8252         u8         reserved_at_10[0xa];
8253         u8         grp[0x6];
8254
8255         u8         clr[0x1];
8256         u8         reserved_at_21[0x1f];
8257
8258         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8259 };
8260
8261 struct mlx5_ifc_ppad_reg_bits {
8262         u8         reserved_at_0[0x3];
8263         u8         single_mac[0x1];
8264         u8         reserved_at_4[0x4];
8265         u8         local_port[0x8];
8266         u8         mac_47_32[0x10];
8267
8268         u8         mac_31_0[0x20];
8269
8270         u8         reserved_at_40[0x40];
8271 };
8272
8273 struct mlx5_ifc_pmtu_reg_bits {
8274         u8         reserved_at_0[0x8];
8275         u8         local_port[0x8];
8276         u8         reserved_at_10[0x10];
8277
8278         u8         max_mtu[0x10];
8279         u8         reserved_at_30[0x10];
8280
8281         u8         admin_mtu[0x10];
8282         u8         reserved_at_50[0x10];
8283
8284         u8         oper_mtu[0x10];
8285         u8         reserved_at_70[0x10];
8286 };
8287
8288 struct mlx5_ifc_pmpr_reg_bits {
8289         u8         reserved_at_0[0x8];
8290         u8         module[0x8];
8291         u8         reserved_at_10[0x10];
8292
8293         u8         reserved_at_20[0x18];
8294         u8         attenuation_5g[0x8];
8295
8296         u8         reserved_at_40[0x18];
8297         u8         attenuation_7g[0x8];
8298
8299         u8         reserved_at_60[0x18];
8300         u8         attenuation_12g[0x8];
8301 };
8302
8303 struct mlx5_ifc_pmpe_reg_bits {
8304         u8         reserved_at_0[0x8];
8305         u8         module[0x8];
8306         u8         reserved_at_10[0xc];
8307         u8         module_status[0x4];
8308
8309         u8         reserved_at_20[0x60];
8310 };
8311
8312 struct mlx5_ifc_pmpc_reg_bits {
8313         u8         module_state_updated[32][0x8];
8314 };
8315
8316 struct mlx5_ifc_pmlpn_reg_bits {
8317         u8         reserved_at_0[0x4];
8318         u8         mlpn_status[0x4];
8319         u8         local_port[0x8];
8320         u8         reserved_at_10[0x10];
8321
8322         u8         e[0x1];
8323         u8         reserved_at_21[0x1f];
8324 };
8325
8326 struct mlx5_ifc_pmlp_reg_bits {
8327         u8         rxtx[0x1];
8328         u8         reserved_at_1[0x7];
8329         u8         local_port[0x8];
8330         u8         reserved_at_10[0x8];
8331         u8         width[0x8];
8332
8333         u8         lane0_module_mapping[0x20];
8334
8335         u8         lane1_module_mapping[0x20];
8336
8337         u8         lane2_module_mapping[0x20];
8338
8339         u8         lane3_module_mapping[0x20];
8340
8341         u8         reserved_at_a0[0x160];
8342 };
8343
8344 struct mlx5_ifc_pmaos_reg_bits {
8345         u8         reserved_at_0[0x8];
8346         u8         module[0x8];
8347         u8         reserved_at_10[0x4];
8348         u8         admin_status[0x4];
8349         u8         reserved_at_18[0x4];
8350         u8         oper_status[0x4];
8351
8352         u8         ase[0x1];
8353         u8         ee[0x1];
8354         u8         reserved_at_22[0x1c];
8355         u8         e[0x2];
8356
8357         u8         reserved_at_40[0x40];
8358 };
8359
8360 struct mlx5_ifc_plpc_reg_bits {
8361         u8         reserved_at_0[0x4];
8362         u8         profile_id[0xc];
8363         u8         reserved_at_10[0x4];
8364         u8         proto_mask[0x4];
8365         u8         reserved_at_18[0x8];
8366
8367         u8         reserved_at_20[0x10];
8368         u8         lane_speed[0x10];
8369
8370         u8         reserved_at_40[0x17];
8371         u8         lpbf[0x1];
8372         u8         fec_mode_policy[0x8];
8373
8374         u8         retransmission_capability[0x8];
8375         u8         fec_mode_capability[0x18];
8376
8377         u8         retransmission_support_admin[0x8];
8378         u8         fec_mode_support_admin[0x18];
8379
8380         u8         retransmission_request_admin[0x8];
8381         u8         fec_mode_request_admin[0x18];
8382
8383         u8         reserved_at_c0[0x80];
8384 };
8385
8386 struct mlx5_ifc_plib_reg_bits {
8387         u8         reserved_at_0[0x8];
8388         u8         local_port[0x8];
8389         u8         reserved_at_10[0x8];
8390         u8         ib_port[0x8];
8391
8392         u8         reserved_at_20[0x60];
8393 };
8394
8395 struct mlx5_ifc_plbf_reg_bits {
8396         u8         reserved_at_0[0x8];
8397         u8         local_port[0x8];
8398         u8         reserved_at_10[0xd];
8399         u8         lbf_mode[0x3];
8400
8401         u8         reserved_at_20[0x20];
8402 };
8403
8404 struct mlx5_ifc_pipg_reg_bits {
8405         u8         reserved_at_0[0x8];
8406         u8         local_port[0x8];
8407         u8         reserved_at_10[0x10];
8408
8409         u8         dic[0x1];
8410         u8         reserved_at_21[0x19];
8411         u8         ipg[0x4];
8412         u8         reserved_at_3e[0x2];
8413 };
8414
8415 struct mlx5_ifc_pifr_reg_bits {
8416         u8         reserved_at_0[0x8];
8417         u8         local_port[0x8];
8418         u8         reserved_at_10[0x10];
8419
8420         u8         reserved_at_20[0xe0];
8421
8422         u8         port_filter[8][0x20];
8423
8424         u8         port_filter_update_en[8][0x20];
8425 };
8426
8427 struct mlx5_ifc_pfcc_reg_bits {
8428         u8         reserved_at_0[0x8];
8429         u8         local_port[0x8];
8430         u8         reserved_at_10[0xb];
8431         u8         ppan_mask_n[0x1];
8432         u8         minor_stall_mask[0x1];
8433         u8         critical_stall_mask[0x1];
8434         u8         reserved_at_1e[0x2];
8435
8436         u8         ppan[0x4];
8437         u8         reserved_at_24[0x4];
8438         u8         prio_mask_tx[0x8];
8439         u8         reserved_at_30[0x8];
8440         u8         prio_mask_rx[0x8];
8441
8442         u8         pptx[0x1];
8443         u8         aptx[0x1];
8444         u8         pptx_mask_n[0x1];
8445         u8         reserved_at_43[0x5];
8446         u8         pfctx[0x8];
8447         u8         reserved_at_50[0x10];
8448
8449         u8         pprx[0x1];
8450         u8         aprx[0x1];
8451         u8         pprx_mask_n[0x1];
8452         u8         reserved_at_63[0x5];
8453         u8         pfcrx[0x8];
8454         u8         reserved_at_70[0x10];
8455
8456         u8         device_stall_minor_watermark[0x10];
8457         u8         device_stall_critical_watermark[0x10];
8458
8459         u8         reserved_at_a0[0x60];
8460 };
8461
8462 struct mlx5_ifc_pelc_reg_bits {
8463         u8         op[0x4];
8464         u8         reserved_at_4[0x4];
8465         u8         local_port[0x8];
8466         u8         reserved_at_10[0x10];
8467
8468         u8         op_admin[0x8];
8469         u8         op_capability[0x8];
8470         u8         op_request[0x8];
8471         u8         op_active[0x8];
8472
8473         u8         admin[0x40];
8474
8475         u8         capability[0x40];
8476
8477         u8         request[0x40];
8478
8479         u8         active[0x40];
8480
8481         u8         reserved_at_140[0x80];
8482 };
8483
8484 struct mlx5_ifc_peir_reg_bits {
8485         u8         reserved_at_0[0x8];
8486         u8         local_port[0x8];
8487         u8         reserved_at_10[0x10];
8488
8489         u8         reserved_at_20[0xc];
8490         u8         error_count[0x4];
8491         u8         reserved_at_30[0x10];
8492
8493         u8         reserved_at_40[0xc];
8494         u8         lane[0x4];
8495         u8         reserved_at_50[0x8];
8496         u8         error_type[0x8];
8497 };
8498
8499 struct mlx5_ifc_mpegc_reg_bits {
8500         u8         reserved_at_0[0x30];
8501         u8         field_select[0x10];
8502
8503         u8         tx_overflow_sense[0x1];
8504         u8         mark_cqe[0x1];
8505         u8         mark_cnp[0x1];
8506         u8         reserved_at_43[0x1b];
8507         u8         tx_lossy_overflow_oper[0x2];
8508
8509         u8         reserved_at_60[0x100];
8510 };
8511
8512 struct mlx5_ifc_pcam_enhanced_features_bits {
8513         u8         reserved_at_0[0x6d];
8514         u8         rx_icrc_encapsulated_counter[0x1];
8515         u8         reserved_at_6e[0x4];
8516         u8         ptys_extended_ethernet[0x1];
8517         u8         reserved_at_73[0x3];
8518         u8         pfcc_mask[0x1];
8519         u8         reserved_at_77[0x3];
8520         u8         per_lane_error_counters[0x1];
8521         u8         rx_buffer_fullness_counters[0x1];
8522         u8         ptys_connector_type[0x1];
8523         u8         reserved_at_7d[0x1];
8524         u8         ppcnt_discard_group[0x1];
8525         u8         ppcnt_statistical_group[0x1];
8526 };
8527
8528 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8529         u8         port_access_reg_cap_mask_127_to_96[0x20];
8530         u8         port_access_reg_cap_mask_95_to_64[0x20];
8531
8532         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8533         u8         pplm[0x1];
8534         u8         port_access_reg_cap_mask_34_to_32[0x3];
8535
8536         u8         port_access_reg_cap_mask_31_to_13[0x13];
8537         u8         pbmc[0x1];
8538         u8         pptb[0x1];
8539         u8         port_access_reg_cap_mask_10_to_09[0x2];
8540         u8         ppcnt[0x1];
8541         u8         port_access_reg_cap_mask_07_to_00[0x8];
8542 };
8543
8544 struct mlx5_ifc_pcam_reg_bits {
8545         u8         reserved_at_0[0x8];
8546         u8         feature_group[0x8];
8547         u8         reserved_at_10[0x8];
8548         u8         access_reg_group[0x8];
8549
8550         u8         reserved_at_20[0x20];
8551
8552         union {
8553                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8554                 u8         reserved_at_0[0x80];
8555         } port_access_reg_cap_mask;
8556
8557         u8         reserved_at_c0[0x80];
8558
8559         union {
8560                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8561                 u8         reserved_at_0[0x80];
8562         } feature_cap_mask;
8563
8564         u8         reserved_at_1c0[0xc0];
8565 };
8566
8567 struct mlx5_ifc_mcam_enhanced_features_bits {
8568         u8         reserved_at_0[0x6e];
8569         u8         pci_status_and_power[0x1];
8570         u8         reserved_at_6f[0x5];
8571         u8         mark_tx_action_cnp[0x1];
8572         u8         mark_tx_action_cqe[0x1];
8573         u8         dynamic_tx_overflow[0x1];
8574         u8         reserved_at_77[0x4];
8575         u8         pcie_outbound_stalled[0x1];
8576         u8         tx_overflow_buffer_pkt[0x1];
8577         u8         mtpps_enh_out_per_adj[0x1];
8578         u8         mtpps_fs[0x1];
8579         u8         pcie_performance_group[0x1];
8580 };
8581
8582 struct mlx5_ifc_mcam_access_reg_bits {
8583         u8         reserved_at_0[0x1c];
8584         u8         mcda[0x1];
8585         u8         mcc[0x1];
8586         u8         mcqi[0x1];
8587         u8         mcqs[0x1];
8588
8589         u8         regs_95_to_87[0x9];
8590         u8         mpegc[0x1];
8591         u8         regs_85_to_68[0x12];
8592         u8         tracer_registers[0x4];
8593
8594         u8         regs_63_to_32[0x20];
8595         u8         regs_31_to_0[0x20];
8596 };
8597
8598 struct mlx5_ifc_mcam_reg_bits {
8599         u8         reserved_at_0[0x8];
8600         u8         feature_group[0x8];
8601         u8         reserved_at_10[0x8];
8602         u8         access_reg_group[0x8];
8603
8604         u8         reserved_at_20[0x20];
8605
8606         union {
8607                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8608                 u8         reserved_at_0[0x80];
8609         } mng_access_reg_cap_mask;
8610
8611         u8         reserved_at_c0[0x80];
8612
8613         union {
8614                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8615                 u8         reserved_at_0[0x80];
8616         } mng_feature_cap_mask;
8617
8618         u8         reserved_at_1c0[0x80];
8619 };
8620
8621 struct mlx5_ifc_qcam_access_reg_cap_mask {
8622         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8623         u8         qpdpm[0x1];
8624         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8625         u8         qdpm[0x1];
8626         u8         qpts[0x1];
8627         u8         qcap[0x1];
8628         u8         qcam_access_reg_cap_mask_0[0x1];
8629 };
8630
8631 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8632         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8633         u8         qpts_trust_both[0x1];
8634 };
8635
8636 struct mlx5_ifc_qcam_reg_bits {
8637         u8         reserved_at_0[0x8];
8638         u8         feature_group[0x8];
8639         u8         reserved_at_10[0x8];
8640         u8         access_reg_group[0x8];
8641         u8         reserved_at_20[0x20];
8642
8643         union {
8644                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8645                 u8  reserved_at_0[0x80];
8646         } qos_access_reg_cap_mask;
8647
8648         u8         reserved_at_c0[0x80];
8649
8650         union {
8651                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8652                 u8  reserved_at_0[0x80];
8653         } qos_feature_cap_mask;
8654
8655         u8         reserved_at_1c0[0x80];
8656 };
8657
8658 struct mlx5_ifc_core_dump_reg_bits {
8659         u8         reserved_at_0[0x18];
8660         u8         core_dump_type[0x8];
8661
8662         u8         reserved_at_20[0x30];
8663         u8         vhca_id[0x10];
8664
8665         u8         reserved_at_60[0x8];
8666         u8         qpn[0x18];
8667         u8         reserved_at_80[0x180];
8668 };
8669
8670 struct mlx5_ifc_pcap_reg_bits {
8671         u8         reserved_at_0[0x8];
8672         u8         local_port[0x8];
8673         u8         reserved_at_10[0x10];
8674
8675         u8         port_capability_mask[4][0x20];
8676 };
8677
8678 struct mlx5_ifc_paos_reg_bits {
8679         u8         swid[0x8];
8680         u8         local_port[0x8];
8681         u8         reserved_at_10[0x4];
8682         u8         admin_status[0x4];
8683         u8         reserved_at_18[0x4];
8684         u8         oper_status[0x4];
8685
8686         u8         ase[0x1];
8687         u8         ee[0x1];
8688         u8         reserved_at_22[0x1c];
8689         u8         e[0x2];
8690
8691         u8         reserved_at_40[0x40];
8692 };
8693
8694 struct mlx5_ifc_pamp_reg_bits {
8695         u8         reserved_at_0[0x8];
8696         u8         opamp_group[0x8];
8697         u8         reserved_at_10[0xc];
8698         u8         opamp_group_type[0x4];
8699
8700         u8         start_index[0x10];
8701         u8         reserved_at_30[0x4];
8702         u8         num_of_indices[0xc];
8703
8704         u8         index_data[18][0x10];
8705 };
8706
8707 struct mlx5_ifc_pcmr_reg_bits {
8708         u8         reserved_at_0[0x8];
8709         u8         local_port[0x8];
8710         u8         reserved_at_10[0x10];
8711         u8         entropy_force_cap[0x1];
8712         u8         entropy_calc_cap[0x1];
8713         u8         entropy_gre_calc_cap[0x1];
8714         u8         reserved_at_23[0x1b];
8715         u8         fcs_cap[0x1];
8716         u8         reserved_at_3f[0x1];
8717         u8         entropy_force[0x1];
8718         u8         entropy_calc[0x1];
8719         u8         entropy_gre_calc[0x1];
8720         u8         reserved_at_43[0x1b];
8721         u8         fcs_chk[0x1];
8722         u8         reserved_at_5f[0x1];
8723 };
8724
8725 struct mlx5_ifc_lane_2_module_mapping_bits {
8726         u8         reserved_at_0[0x6];
8727         u8         rx_lane[0x2];
8728         u8         reserved_at_8[0x6];
8729         u8         tx_lane[0x2];
8730         u8         reserved_at_10[0x8];
8731         u8         module[0x8];
8732 };
8733
8734 struct mlx5_ifc_bufferx_reg_bits {
8735         u8         reserved_at_0[0x6];
8736         u8         lossy[0x1];
8737         u8         epsb[0x1];
8738         u8         reserved_at_8[0xc];
8739         u8         size[0xc];
8740
8741         u8         xoff_threshold[0x10];
8742         u8         xon_threshold[0x10];
8743 };
8744
8745 struct mlx5_ifc_set_node_in_bits {
8746         u8         node_description[64][0x8];
8747 };
8748
8749 struct mlx5_ifc_register_power_settings_bits {
8750         u8         reserved_at_0[0x18];
8751         u8         power_settings_level[0x8];
8752
8753         u8         reserved_at_20[0x60];
8754 };
8755
8756 struct mlx5_ifc_register_host_endianness_bits {
8757         u8         he[0x1];
8758         u8         reserved_at_1[0x1f];
8759
8760         u8         reserved_at_20[0x60];
8761 };
8762
8763 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8764         u8         reserved_at_0[0x20];
8765
8766         u8         mkey[0x20];
8767
8768         u8         addressh_63_32[0x20];
8769
8770         u8         addressl_31_0[0x20];
8771 };
8772
8773 struct mlx5_ifc_ud_adrs_vector_bits {
8774         u8         dc_key[0x40];
8775
8776         u8         ext[0x1];
8777         u8         reserved_at_41[0x7];
8778         u8         destination_qp_dct[0x18];
8779
8780         u8         static_rate[0x4];
8781         u8         sl_eth_prio[0x4];
8782         u8         fl[0x1];
8783         u8         mlid[0x7];
8784         u8         rlid_udp_sport[0x10];
8785
8786         u8         reserved_at_80[0x20];
8787
8788         u8         rmac_47_16[0x20];
8789
8790         u8         rmac_15_0[0x10];
8791         u8         tclass[0x8];
8792         u8         hop_limit[0x8];
8793
8794         u8         reserved_at_e0[0x1];
8795         u8         grh[0x1];
8796         u8         reserved_at_e2[0x2];
8797         u8         src_addr_index[0x8];
8798         u8         flow_label[0x14];
8799
8800         u8         rgid_rip[16][0x8];
8801 };
8802
8803 struct mlx5_ifc_pages_req_event_bits {
8804         u8         reserved_at_0[0x10];
8805         u8         function_id[0x10];
8806
8807         u8         num_pages[0x20];
8808
8809         u8         reserved_at_40[0xa0];
8810 };
8811
8812 struct mlx5_ifc_eqe_bits {
8813         u8         reserved_at_0[0x8];
8814         u8         event_type[0x8];
8815         u8         reserved_at_10[0x8];
8816         u8         event_sub_type[0x8];
8817
8818         u8         reserved_at_20[0xe0];
8819
8820         union mlx5_ifc_event_auto_bits event_data;
8821
8822         u8         reserved_at_1e0[0x10];
8823         u8         signature[0x8];
8824         u8         reserved_at_1f8[0x7];
8825         u8         owner[0x1];
8826 };
8827
8828 enum {
8829         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8830 };
8831
8832 struct mlx5_ifc_cmd_queue_entry_bits {
8833         u8         type[0x8];
8834         u8         reserved_at_8[0x18];
8835
8836         u8         input_length[0x20];
8837
8838         u8         input_mailbox_pointer_63_32[0x20];
8839
8840         u8         input_mailbox_pointer_31_9[0x17];
8841         u8         reserved_at_77[0x9];
8842
8843         u8         command_input_inline_data[16][0x8];
8844
8845         u8         command_output_inline_data[16][0x8];
8846
8847         u8         output_mailbox_pointer_63_32[0x20];
8848
8849         u8         output_mailbox_pointer_31_9[0x17];
8850         u8         reserved_at_1b7[0x9];
8851
8852         u8         output_length[0x20];
8853
8854         u8         token[0x8];
8855         u8         signature[0x8];
8856         u8         reserved_at_1f0[0x8];
8857         u8         status[0x7];
8858         u8         ownership[0x1];
8859 };
8860
8861 struct mlx5_ifc_cmd_out_bits {
8862         u8         status[0x8];
8863         u8         reserved_at_8[0x18];
8864
8865         u8         syndrome[0x20];
8866
8867         u8         command_output[0x20];
8868 };
8869
8870 struct mlx5_ifc_cmd_in_bits {
8871         u8         opcode[0x10];
8872         u8         reserved_at_10[0x10];
8873
8874         u8         reserved_at_20[0x10];
8875         u8         op_mod[0x10];
8876
8877         u8         command[0][0x20];
8878 };
8879
8880 struct mlx5_ifc_cmd_if_box_bits {
8881         u8         mailbox_data[512][0x8];
8882
8883         u8         reserved_at_1000[0x180];
8884
8885         u8         next_pointer_63_32[0x20];
8886
8887         u8         next_pointer_31_10[0x16];
8888         u8         reserved_at_11b6[0xa];
8889
8890         u8         block_number[0x20];
8891
8892         u8         reserved_at_11e0[0x8];
8893         u8         token[0x8];
8894         u8         ctrl_signature[0x8];
8895         u8         signature[0x8];
8896 };
8897
8898 struct mlx5_ifc_mtt_bits {
8899         u8         ptag_63_32[0x20];
8900
8901         u8         ptag_31_8[0x18];
8902         u8         reserved_at_38[0x6];
8903         u8         wr_en[0x1];
8904         u8         rd_en[0x1];
8905 };
8906
8907 struct mlx5_ifc_query_wol_rol_out_bits {
8908         u8         status[0x8];
8909         u8         reserved_at_8[0x18];
8910
8911         u8         syndrome[0x20];
8912
8913         u8         reserved_at_40[0x10];
8914         u8         rol_mode[0x8];
8915         u8         wol_mode[0x8];
8916
8917         u8         reserved_at_60[0x20];
8918 };
8919
8920 struct mlx5_ifc_query_wol_rol_in_bits {
8921         u8         opcode[0x10];
8922         u8         reserved_at_10[0x10];
8923
8924         u8         reserved_at_20[0x10];
8925         u8         op_mod[0x10];
8926
8927         u8         reserved_at_40[0x40];
8928 };
8929
8930 struct mlx5_ifc_set_wol_rol_out_bits {
8931         u8         status[0x8];
8932         u8         reserved_at_8[0x18];
8933
8934         u8         syndrome[0x20];
8935
8936         u8         reserved_at_40[0x40];
8937 };
8938
8939 struct mlx5_ifc_set_wol_rol_in_bits {
8940         u8         opcode[0x10];
8941         u8         reserved_at_10[0x10];
8942
8943         u8         reserved_at_20[0x10];
8944         u8         op_mod[0x10];
8945
8946         u8         rol_mode_valid[0x1];
8947         u8         wol_mode_valid[0x1];
8948         u8         reserved_at_42[0xe];
8949         u8         rol_mode[0x8];
8950         u8         wol_mode[0x8];
8951
8952         u8         reserved_at_60[0x20];
8953 };
8954
8955 enum {
8956         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8957         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8958         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8959 };
8960
8961 enum {
8962         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8963         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8964         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8965 };
8966
8967 enum {
8968         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8969         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8970         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8971         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8972         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8973         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8974         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8975         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8976         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8977         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8978         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8979 };
8980
8981 struct mlx5_ifc_initial_seg_bits {
8982         u8         fw_rev_minor[0x10];
8983         u8         fw_rev_major[0x10];
8984
8985         u8         cmd_interface_rev[0x10];
8986         u8         fw_rev_subminor[0x10];
8987
8988         u8         reserved_at_40[0x40];
8989
8990         u8         cmdq_phy_addr_63_32[0x20];
8991
8992         u8         cmdq_phy_addr_31_12[0x14];
8993         u8         reserved_at_b4[0x2];
8994         u8         nic_interface[0x2];
8995         u8         log_cmdq_size[0x4];
8996         u8         log_cmdq_stride[0x4];
8997
8998         u8         command_doorbell_vector[0x20];
8999
9000         u8         reserved_at_e0[0xf00];
9001
9002         u8         initializing[0x1];
9003         u8         reserved_at_fe1[0x4];
9004         u8         nic_interface_supported[0x3];
9005         u8         embedded_cpu[0x1];
9006         u8         reserved_at_fe9[0x17];
9007
9008         struct mlx5_ifc_health_buffer_bits health_buffer;
9009
9010         u8         no_dram_nic_offset[0x20];
9011
9012         u8         reserved_at_1220[0x6e40];
9013
9014         u8         reserved_at_8060[0x1f];
9015         u8         clear_int[0x1];
9016
9017         u8         health_syndrome[0x8];
9018         u8         health_counter[0x18];
9019
9020         u8         reserved_at_80a0[0x17fc0];
9021 };
9022
9023 struct mlx5_ifc_mtpps_reg_bits {
9024         u8         reserved_at_0[0xc];
9025         u8         cap_number_of_pps_pins[0x4];
9026         u8         reserved_at_10[0x4];
9027         u8         cap_max_num_of_pps_in_pins[0x4];
9028         u8         reserved_at_18[0x4];
9029         u8         cap_max_num_of_pps_out_pins[0x4];
9030
9031         u8         reserved_at_20[0x24];
9032         u8         cap_pin_3_mode[0x4];
9033         u8         reserved_at_48[0x4];
9034         u8         cap_pin_2_mode[0x4];
9035         u8         reserved_at_50[0x4];
9036         u8         cap_pin_1_mode[0x4];
9037         u8         reserved_at_58[0x4];
9038         u8         cap_pin_0_mode[0x4];
9039
9040         u8         reserved_at_60[0x4];
9041         u8         cap_pin_7_mode[0x4];
9042         u8         reserved_at_68[0x4];
9043         u8         cap_pin_6_mode[0x4];
9044         u8         reserved_at_70[0x4];
9045         u8         cap_pin_5_mode[0x4];
9046         u8         reserved_at_78[0x4];
9047         u8         cap_pin_4_mode[0x4];
9048
9049         u8         field_select[0x20];
9050         u8         reserved_at_a0[0x60];
9051
9052         u8         enable[0x1];
9053         u8         reserved_at_101[0xb];
9054         u8         pattern[0x4];
9055         u8         reserved_at_110[0x4];
9056         u8         pin_mode[0x4];
9057         u8         pin[0x8];
9058
9059         u8         reserved_at_120[0x20];
9060
9061         u8         time_stamp[0x40];
9062
9063         u8         out_pulse_duration[0x10];
9064         u8         out_periodic_adjustment[0x10];
9065         u8         enhanced_out_periodic_adjustment[0x20];
9066
9067         u8         reserved_at_1c0[0x20];
9068 };
9069
9070 struct mlx5_ifc_mtppse_reg_bits {
9071         u8         reserved_at_0[0x18];
9072         u8         pin[0x8];
9073         u8         event_arm[0x1];
9074         u8         reserved_at_21[0x1b];
9075         u8         event_generation_mode[0x4];
9076         u8         reserved_at_40[0x40];
9077 };
9078
9079 struct mlx5_ifc_mcqs_reg_bits {
9080         u8         last_index_flag[0x1];
9081         u8         reserved_at_1[0x7];
9082         u8         fw_device[0x8];
9083         u8         component_index[0x10];
9084
9085         u8         reserved_at_20[0x10];
9086         u8         identifier[0x10];
9087
9088         u8         reserved_at_40[0x17];
9089         u8         component_status[0x5];
9090         u8         component_update_state[0x4];
9091
9092         u8         last_update_state_changer_type[0x4];
9093         u8         last_update_state_changer_host_id[0x4];
9094         u8         reserved_at_68[0x18];
9095 };
9096
9097 struct mlx5_ifc_mcqi_cap_bits {
9098         u8         supported_info_bitmask[0x20];
9099
9100         u8         component_size[0x20];
9101
9102         u8         max_component_size[0x20];
9103
9104         u8         log_mcda_word_size[0x4];
9105         u8         reserved_at_64[0xc];
9106         u8         mcda_max_write_size[0x10];
9107
9108         u8         rd_en[0x1];
9109         u8         reserved_at_81[0x1];
9110         u8         match_chip_id[0x1];
9111         u8         match_psid[0x1];
9112         u8         check_user_timestamp[0x1];
9113         u8         match_base_guid_mac[0x1];
9114         u8         reserved_at_86[0x1a];
9115 };
9116
9117 struct mlx5_ifc_mcqi_version_bits {
9118         u8         reserved_at_0[0x2];
9119         u8         build_time_valid[0x1];
9120         u8         user_defined_time_valid[0x1];
9121         u8         reserved_at_4[0x14];
9122         u8         version_string_length[0x8];
9123
9124         u8         version[0x20];
9125
9126         u8         build_time[0x40];
9127
9128         u8         user_defined_time[0x40];
9129
9130         u8         build_tool_version[0x20];
9131
9132         u8         reserved_at_e0[0x20];
9133
9134         u8         version_string[92][0x8];
9135 };
9136
9137 struct mlx5_ifc_mcqi_activation_method_bits {
9138         u8         pending_server_ac_power_cycle[0x1];
9139         u8         pending_server_dc_power_cycle[0x1];
9140         u8         pending_server_reboot[0x1];
9141         u8         pending_fw_reset[0x1];
9142         u8         auto_activate[0x1];
9143         u8         all_hosts_sync[0x1];
9144         u8         device_hw_reset[0x1];
9145         u8         reserved_at_7[0x19];
9146 };
9147
9148 union mlx5_ifc_mcqi_reg_data_bits {
9149         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9150         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9151         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9152 };
9153
9154 struct mlx5_ifc_mcqi_reg_bits {
9155         u8         read_pending_component[0x1];
9156         u8         reserved_at_1[0xf];
9157         u8         component_index[0x10];
9158
9159         u8         reserved_at_20[0x20];
9160
9161         u8         reserved_at_40[0x1b];
9162         u8         info_type[0x5];
9163
9164         u8         info_size[0x20];
9165
9166         u8         offset[0x20];
9167
9168         u8         reserved_at_a0[0x10];
9169         u8         data_size[0x10];
9170
9171         union mlx5_ifc_mcqi_reg_data_bits data[0];
9172 };
9173
9174 struct mlx5_ifc_mcc_reg_bits {
9175         u8         reserved_at_0[0x4];
9176         u8         time_elapsed_since_last_cmd[0xc];
9177         u8         reserved_at_10[0x8];
9178         u8         instruction[0x8];
9179
9180         u8         reserved_at_20[0x10];
9181         u8         component_index[0x10];
9182
9183         u8         reserved_at_40[0x8];
9184         u8         update_handle[0x18];
9185
9186         u8         handle_owner_type[0x4];
9187         u8         handle_owner_host_id[0x4];
9188         u8         reserved_at_68[0x1];
9189         u8         control_progress[0x7];
9190         u8         error_code[0x8];
9191         u8         reserved_at_78[0x4];
9192         u8         control_state[0x4];
9193
9194         u8         component_size[0x20];
9195
9196         u8         reserved_at_a0[0x60];
9197 };
9198
9199 struct mlx5_ifc_mcda_reg_bits {
9200         u8         reserved_at_0[0x8];
9201         u8         update_handle[0x18];
9202
9203         u8         offset[0x20];
9204
9205         u8         reserved_at_40[0x10];
9206         u8         size[0x10];
9207
9208         u8         reserved_at_60[0x20];
9209
9210         u8         data[0][0x20];
9211 };
9212
9213 union mlx5_ifc_ports_control_registers_document_bits {
9214         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9215         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9216         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9217         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9218         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9219         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9220         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9221         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9222         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9223         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9224         struct mlx5_ifc_paos_reg_bits paos_reg;
9225         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9226         struct mlx5_ifc_peir_reg_bits peir_reg;
9227         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9228         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9229         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9230         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9231         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9232         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9233         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9234         struct mlx5_ifc_plib_reg_bits plib_reg;
9235         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9236         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9237         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9238         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9239         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9240         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9241         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9242         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9243         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9244         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9245         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9246         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9247         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9248         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9249         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9250         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9251         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9252         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9253         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9254         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9255         struct mlx5_ifc_pude_reg_bits pude_reg;
9256         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9257         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9258         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9259         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9260         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9261         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9262         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9263         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9264         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9265         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9266         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9267         u8         reserved_at_0[0x60e0];
9268 };
9269
9270 union mlx5_ifc_debug_enhancements_document_bits {
9271         struct mlx5_ifc_health_buffer_bits health_buffer;
9272         u8         reserved_at_0[0x200];
9273 };
9274
9275 union mlx5_ifc_uplink_pci_interface_document_bits {
9276         struct mlx5_ifc_initial_seg_bits initial_seg;
9277         u8         reserved_at_0[0x20060];
9278 };
9279
9280 struct mlx5_ifc_set_flow_table_root_out_bits {
9281         u8         status[0x8];
9282         u8         reserved_at_8[0x18];
9283
9284         u8         syndrome[0x20];
9285
9286         u8         reserved_at_40[0x40];
9287 };
9288
9289 struct mlx5_ifc_set_flow_table_root_in_bits {
9290         u8         opcode[0x10];
9291         u8         reserved_at_10[0x10];
9292
9293         u8         reserved_at_20[0x10];
9294         u8         op_mod[0x10];
9295
9296         u8         other_vport[0x1];
9297         u8         reserved_at_41[0xf];
9298         u8         vport_number[0x10];
9299
9300         u8         reserved_at_60[0x20];
9301
9302         u8         table_type[0x8];
9303         u8         reserved_at_88[0x18];
9304
9305         u8         reserved_at_a0[0x8];
9306         u8         table_id[0x18];
9307
9308         u8         reserved_at_c0[0x8];
9309         u8         underlay_qpn[0x18];
9310         u8         reserved_at_e0[0x120];
9311 };
9312
9313 enum {
9314         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9315         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9316 };
9317
9318 struct mlx5_ifc_modify_flow_table_out_bits {
9319         u8         status[0x8];
9320         u8         reserved_at_8[0x18];
9321
9322         u8         syndrome[0x20];
9323
9324         u8         reserved_at_40[0x40];
9325 };
9326
9327 struct mlx5_ifc_modify_flow_table_in_bits {
9328         u8         opcode[0x10];
9329         u8         reserved_at_10[0x10];
9330
9331         u8         reserved_at_20[0x10];
9332         u8         op_mod[0x10];
9333
9334         u8         other_vport[0x1];
9335         u8         reserved_at_41[0xf];
9336         u8         vport_number[0x10];
9337
9338         u8         reserved_at_60[0x10];
9339         u8         modify_field_select[0x10];
9340
9341         u8         table_type[0x8];
9342         u8         reserved_at_88[0x18];
9343
9344         u8         reserved_at_a0[0x8];
9345         u8         table_id[0x18];
9346
9347         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9348 };
9349
9350 struct mlx5_ifc_ets_tcn_config_reg_bits {
9351         u8         g[0x1];
9352         u8         b[0x1];
9353         u8         r[0x1];
9354         u8         reserved_at_3[0x9];
9355         u8         group[0x4];
9356         u8         reserved_at_10[0x9];
9357         u8         bw_allocation[0x7];
9358
9359         u8         reserved_at_20[0xc];
9360         u8         max_bw_units[0x4];
9361         u8         reserved_at_30[0x8];
9362         u8         max_bw_value[0x8];
9363 };
9364
9365 struct mlx5_ifc_ets_global_config_reg_bits {
9366         u8         reserved_at_0[0x2];
9367         u8         r[0x1];
9368         u8         reserved_at_3[0x1d];
9369
9370         u8         reserved_at_20[0xc];
9371         u8         max_bw_units[0x4];
9372         u8         reserved_at_30[0x8];
9373         u8         max_bw_value[0x8];
9374 };
9375
9376 struct mlx5_ifc_qetc_reg_bits {
9377         u8                                         reserved_at_0[0x8];
9378         u8                                         port_number[0x8];
9379         u8                                         reserved_at_10[0x30];
9380
9381         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9382         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9383 };
9384
9385 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9386         u8         e[0x1];
9387         u8         reserved_at_01[0x0b];
9388         u8         prio[0x04];
9389 };
9390
9391 struct mlx5_ifc_qpdpm_reg_bits {
9392         u8                                     reserved_at_0[0x8];
9393         u8                                     local_port[0x8];
9394         u8                                     reserved_at_10[0x10];
9395         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9396 };
9397
9398 struct mlx5_ifc_qpts_reg_bits {
9399         u8         reserved_at_0[0x8];
9400         u8         local_port[0x8];
9401         u8         reserved_at_10[0x2d];
9402         u8         trust_state[0x3];
9403 };
9404
9405 struct mlx5_ifc_pptb_reg_bits {
9406         u8         reserved_at_0[0x2];
9407         u8         mm[0x2];
9408         u8         reserved_at_4[0x4];
9409         u8         local_port[0x8];
9410         u8         reserved_at_10[0x6];
9411         u8         cm[0x1];
9412         u8         um[0x1];
9413         u8         pm[0x8];
9414
9415         u8         prio_x_buff[0x20];
9416
9417         u8         pm_msb[0x8];
9418         u8         reserved_at_48[0x10];
9419         u8         ctrl_buff[0x4];
9420         u8         untagged_buff[0x4];
9421 };
9422
9423 struct mlx5_ifc_pbmc_reg_bits {
9424         u8         reserved_at_0[0x8];
9425         u8         local_port[0x8];
9426         u8         reserved_at_10[0x10];
9427
9428         u8         xoff_timer_value[0x10];
9429         u8         xoff_refresh[0x10];
9430
9431         u8         reserved_at_40[0x9];
9432         u8         fullness_threshold[0x7];
9433         u8         port_buffer_size[0x10];
9434
9435         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9436
9437         u8         reserved_at_2e0[0x40];
9438 };
9439
9440 struct mlx5_ifc_qtct_reg_bits {
9441         u8         reserved_at_0[0x8];
9442         u8         port_number[0x8];
9443         u8         reserved_at_10[0xd];
9444         u8         prio[0x3];
9445
9446         u8         reserved_at_20[0x1d];
9447         u8         tclass[0x3];
9448 };
9449
9450 struct mlx5_ifc_mcia_reg_bits {
9451         u8         l[0x1];
9452         u8         reserved_at_1[0x7];
9453         u8         module[0x8];
9454         u8         reserved_at_10[0x8];
9455         u8         status[0x8];
9456
9457         u8         i2c_device_address[0x8];
9458         u8         page_number[0x8];
9459         u8         device_address[0x10];
9460
9461         u8         reserved_at_40[0x10];
9462         u8         size[0x10];
9463
9464         u8         reserved_at_60[0x20];
9465
9466         u8         dword_0[0x20];
9467         u8         dword_1[0x20];
9468         u8         dword_2[0x20];
9469         u8         dword_3[0x20];
9470         u8         dword_4[0x20];
9471         u8         dword_5[0x20];
9472         u8         dword_6[0x20];
9473         u8         dword_7[0x20];
9474         u8         dword_8[0x20];
9475         u8         dword_9[0x20];
9476         u8         dword_10[0x20];
9477         u8         dword_11[0x20];
9478 };
9479
9480 struct mlx5_ifc_dcbx_param_bits {
9481         u8         dcbx_cee_cap[0x1];
9482         u8         dcbx_ieee_cap[0x1];
9483         u8         dcbx_standby_cap[0x1];
9484         u8         reserved_at_3[0x5];
9485         u8         port_number[0x8];
9486         u8         reserved_at_10[0xa];
9487         u8         max_application_table_size[6];
9488         u8         reserved_at_20[0x15];
9489         u8         version_oper[0x3];
9490         u8         reserved_at_38[5];
9491         u8         version_admin[0x3];
9492         u8         willing_admin[0x1];
9493         u8         reserved_at_41[0x3];
9494         u8         pfc_cap_oper[0x4];
9495         u8         reserved_at_48[0x4];
9496         u8         pfc_cap_admin[0x4];
9497         u8         reserved_at_50[0x4];
9498         u8         num_of_tc_oper[0x4];
9499         u8         reserved_at_58[0x4];
9500         u8         num_of_tc_admin[0x4];
9501         u8         remote_willing[0x1];
9502         u8         reserved_at_61[3];
9503         u8         remote_pfc_cap[4];
9504         u8         reserved_at_68[0x14];
9505         u8         remote_num_of_tc[0x4];
9506         u8         reserved_at_80[0x18];
9507         u8         error[0x8];
9508         u8         reserved_at_a0[0x160];
9509 };
9510
9511 struct mlx5_ifc_lagc_bits {
9512         u8         reserved_at_0[0x1d];
9513         u8         lag_state[0x3];
9514
9515         u8         reserved_at_20[0x14];
9516         u8         tx_remap_affinity_2[0x4];
9517         u8         reserved_at_38[0x4];
9518         u8         tx_remap_affinity_1[0x4];
9519 };
9520
9521 struct mlx5_ifc_create_lag_out_bits {
9522         u8         status[0x8];
9523         u8         reserved_at_8[0x18];
9524
9525         u8         syndrome[0x20];
9526
9527         u8         reserved_at_40[0x40];
9528 };
9529
9530 struct mlx5_ifc_create_lag_in_bits {
9531         u8         opcode[0x10];
9532         u8         reserved_at_10[0x10];
9533
9534         u8         reserved_at_20[0x10];
9535         u8         op_mod[0x10];
9536
9537         struct mlx5_ifc_lagc_bits ctx;
9538 };
9539
9540 struct mlx5_ifc_modify_lag_out_bits {
9541         u8         status[0x8];
9542         u8         reserved_at_8[0x18];
9543
9544         u8         syndrome[0x20];
9545
9546         u8         reserved_at_40[0x40];
9547 };
9548
9549 struct mlx5_ifc_modify_lag_in_bits {
9550         u8         opcode[0x10];
9551         u8         reserved_at_10[0x10];
9552
9553         u8         reserved_at_20[0x10];
9554         u8         op_mod[0x10];
9555
9556         u8         reserved_at_40[0x20];
9557         u8         field_select[0x20];
9558
9559         struct mlx5_ifc_lagc_bits ctx;
9560 };
9561
9562 struct mlx5_ifc_query_lag_out_bits {
9563         u8         status[0x8];
9564         u8         reserved_at_8[0x18];
9565
9566         u8         syndrome[0x20];
9567
9568         u8         reserved_at_40[0x40];
9569
9570         struct mlx5_ifc_lagc_bits ctx;
9571 };
9572
9573 struct mlx5_ifc_query_lag_in_bits {
9574         u8         opcode[0x10];
9575         u8         reserved_at_10[0x10];
9576
9577         u8         reserved_at_20[0x10];
9578         u8         op_mod[0x10];
9579
9580         u8         reserved_at_40[0x40];
9581 };
9582
9583 struct mlx5_ifc_destroy_lag_out_bits {
9584         u8         status[0x8];
9585         u8         reserved_at_8[0x18];
9586
9587         u8         syndrome[0x20];
9588
9589         u8         reserved_at_40[0x40];
9590 };
9591
9592 struct mlx5_ifc_destroy_lag_in_bits {
9593         u8         opcode[0x10];
9594         u8         reserved_at_10[0x10];
9595
9596         u8         reserved_at_20[0x10];
9597         u8         op_mod[0x10];
9598
9599         u8         reserved_at_40[0x40];
9600 };
9601
9602 struct mlx5_ifc_create_vport_lag_out_bits {
9603         u8         status[0x8];
9604         u8         reserved_at_8[0x18];
9605
9606         u8         syndrome[0x20];
9607
9608         u8         reserved_at_40[0x40];
9609 };
9610
9611 struct mlx5_ifc_create_vport_lag_in_bits {
9612         u8         opcode[0x10];
9613         u8         reserved_at_10[0x10];
9614
9615         u8         reserved_at_20[0x10];
9616         u8         op_mod[0x10];
9617
9618         u8         reserved_at_40[0x40];
9619 };
9620
9621 struct mlx5_ifc_destroy_vport_lag_out_bits {
9622         u8         status[0x8];
9623         u8         reserved_at_8[0x18];
9624
9625         u8         syndrome[0x20];
9626
9627         u8         reserved_at_40[0x40];
9628 };
9629
9630 struct mlx5_ifc_destroy_vport_lag_in_bits {
9631         u8         opcode[0x10];
9632         u8         reserved_at_10[0x10];
9633
9634         u8         reserved_at_20[0x10];
9635         u8         op_mod[0x10];
9636
9637         u8         reserved_at_40[0x40];
9638 };
9639
9640 struct mlx5_ifc_alloc_memic_in_bits {
9641         u8         opcode[0x10];
9642         u8         reserved_at_10[0x10];
9643
9644         u8         reserved_at_20[0x10];
9645         u8         op_mod[0x10];
9646
9647         u8         reserved_at_30[0x20];
9648
9649         u8         reserved_at_40[0x18];
9650         u8         log_memic_addr_alignment[0x8];
9651
9652         u8         range_start_addr[0x40];
9653
9654         u8         range_size[0x20];
9655
9656         u8         memic_size[0x20];
9657 };
9658
9659 struct mlx5_ifc_alloc_memic_out_bits {
9660         u8         status[0x8];
9661         u8         reserved_at_8[0x18];
9662
9663         u8         syndrome[0x20];
9664
9665         u8         memic_start_addr[0x40];
9666 };
9667
9668 struct mlx5_ifc_dealloc_memic_in_bits {
9669         u8         opcode[0x10];
9670         u8         reserved_at_10[0x10];
9671
9672         u8         reserved_at_20[0x10];
9673         u8         op_mod[0x10];
9674
9675         u8         reserved_at_40[0x40];
9676
9677         u8         memic_start_addr[0x40];
9678
9679         u8         memic_size[0x20];
9680
9681         u8         reserved_at_e0[0x20];
9682 };
9683
9684 struct mlx5_ifc_dealloc_memic_out_bits {
9685         u8         status[0x8];
9686         u8         reserved_at_8[0x18];
9687
9688         u8         syndrome[0x20];
9689
9690         u8         reserved_at_40[0x40];
9691 };
9692
9693 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9694         u8         opcode[0x10];
9695         u8         uid[0x10];
9696
9697         u8         reserved_at_20[0x10];
9698         u8         obj_type[0x10];
9699
9700         u8         obj_id[0x20];
9701
9702         u8         reserved_at_60[0x20];
9703 };
9704
9705 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9706         u8         status[0x8];
9707         u8         reserved_at_8[0x18];
9708
9709         u8         syndrome[0x20];
9710
9711         u8         obj_id[0x20];
9712
9713         u8         reserved_at_60[0x20];
9714 };
9715
9716 struct mlx5_ifc_umem_bits {
9717         u8         reserved_at_0[0x80];
9718
9719         u8         reserved_at_80[0x1b];
9720         u8         log_page_size[0x5];
9721
9722         u8         page_offset[0x20];
9723
9724         u8         num_of_mtt[0x40];
9725
9726         struct mlx5_ifc_mtt_bits  mtt[0];
9727 };
9728
9729 struct mlx5_ifc_uctx_bits {
9730         u8         cap[0x20];
9731
9732         u8         reserved_at_20[0x160];
9733 };
9734
9735 struct mlx5_ifc_sw_icm_bits {
9736         u8         modify_field_select[0x40];
9737
9738         u8         reserved_at_40[0x18];
9739         u8         log_sw_icm_size[0x8];
9740
9741         u8         reserved_at_60[0x20];
9742
9743         u8         sw_icm_start_addr[0x40];
9744
9745         u8         reserved_at_c0[0x140];
9746 };
9747
9748 struct mlx5_ifc_geneve_tlv_option_bits {
9749         u8         modify_field_select[0x40];
9750
9751         u8         reserved_at_40[0x18];
9752         u8         geneve_option_fte_index[0x8];
9753
9754         u8         option_class[0x10];
9755         u8         option_type[0x8];
9756         u8         reserved_at_78[0x3];
9757         u8         option_data_length[0x5];
9758
9759         u8         reserved_at_80[0x180];
9760 };
9761
9762 struct mlx5_ifc_create_umem_in_bits {
9763         u8         opcode[0x10];
9764         u8         uid[0x10];
9765
9766         u8         reserved_at_20[0x10];
9767         u8         op_mod[0x10];
9768
9769         u8         reserved_at_40[0x40];
9770
9771         struct mlx5_ifc_umem_bits  umem;
9772 };
9773
9774 struct mlx5_ifc_create_uctx_in_bits {
9775         u8         opcode[0x10];
9776         u8         reserved_at_10[0x10];
9777
9778         u8         reserved_at_20[0x10];
9779         u8         op_mod[0x10];
9780
9781         u8         reserved_at_40[0x40];
9782
9783         struct mlx5_ifc_uctx_bits  uctx;
9784 };
9785
9786 struct mlx5_ifc_destroy_uctx_in_bits {
9787         u8         opcode[0x10];
9788         u8         reserved_at_10[0x10];
9789
9790         u8         reserved_at_20[0x10];
9791         u8         op_mod[0x10];
9792
9793         u8         reserved_at_40[0x10];
9794         u8         uid[0x10];
9795
9796         u8         reserved_at_60[0x20];
9797 };
9798
9799 struct mlx5_ifc_create_sw_icm_in_bits {
9800         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9801         struct mlx5_ifc_sw_icm_bits                   sw_icm;
9802 };
9803
9804 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9805         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9806         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
9807 };
9808
9809 struct mlx5_ifc_mtrc_string_db_param_bits {
9810         u8         string_db_base_address[0x20];
9811
9812         u8         reserved_at_20[0x8];
9813         u8         string_db_size[0x18];
9814 };
9815
9816 struct mlx5_ifc_mtrc_cap_bits {
9817         u8         trace_owner[0x1];
9818         u8         trace_to_memory[0x1];
9819         u8         reserved_at_2[0x4];
9820         u8         trc_ver[0x2];
9821         u8         reserved_at_8[0x14];
9822         u8         num_string_db[0x4];
9823
9824         u8         first_string_trace[0x8];
9825         u8         num_string_trace[0x8];
9826         u8         reserved_at_30[0x28];
9827
9828         u8         log_max_trace_buffer_size[0x8];
9829
9830         u8         reserved_at_60[0x20];
9831
9832         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9833
9834         u8         reserved_at_280[0x180];
9835 };
9836
9837 struct mlx5_ifc_mtrc_conf_bits {
9838         u8         reserved_at_0[0x1c];
9839         u8         trace_mode[0x4];
9840         u8         reserved_at_20[0x18];
9841         u8         log_trace_buffer_size[0x8];
9842         u8         trace_mkey[0x20];
9843         u8         reserved_at_60[0x3a0];
9844 };
9845
9846 struct mlx5_ifc_mtrc_stdb_bits {
9847         u8         string_db_index[0x4];
9848         u8         reserved_at_4[0x4];
9849         u8         read_size[0x18];
9850         u8         start_offset[0x20];
9851         u8         string_db_data[0];
9852 };
9853
9854 struct mlx5_ifc_mtrc_ctrl_bits {
9855         u8         trace_status[0x2];
9856         u8         reserved_at_2[0x2];
9857         u8         arm_event[0x1];
9858         u8         reserved_at_5[0xb];
9859         u8         modify_field_select[0x10];
9860         u8         reserved_at_20[0x2b];
9861         u8         current_timestamp52_32[0x15];
9862         u8         current_timestamp31_0[0x20];
9863         u8         reserved_at_80[0x180];
9864 };
9865
9866 struct mlx5_ifc_host_params_context_bits {
9867         u8         host_number[0x8];
9868         u8         reserved_at_8[0x7];
9869         u8         host_pf_disabled[0x1];
9870         u8         host_num_of_vfs[0x10];
9871
9872         u8         host_total_vfs[0x10];
9873         u8         host_pci_bus[0x10];
9874
9875         u8         reserved_at_40[0x10];
9876         u8         host_pci_device[0x10];
9877
9878         u8         reserved_at_60[0x10];
9879         u8         host_pci_function[0x10];
9880
9881         u8         reserved_at_80[0x180];
9882 };
9883
9884 struct mlx5_ifc_query_esw_functions_in_bits {
9885         u8         opcode[0x10];
9886         u8         reserved_at_10[0x10];
9887
9888         u8         reserved_at_20[0x10];
9889         u8         op_mod[0x10];
9890
9891         u8         reserved_at_40[0x40];
9892 };
9893
9894 struct mlx5_ifc_query_esw_functions_out_bits {
9895         u8         status[0x8];
9896         u8         reserved_at_8[0x18];
9897
9898         u8         syndrome[0x20];
9899
9900         u8         reserved_at_40[0x40];
9901
9902         struct mlx5_ifc_host_params_context_bits host_params_context;
9903
9904         u8         reserved_at_280[0x180];
9905         u8         host_sf_enable[0][0x40];
9906 };
9907
9908 struct mlx5_ifc_sf_partition_bits {
9909         u8         reserved_at_0[0x10];
9910         u8         log_num_sf[0x8];
9911         u8         log_sf_bar_size[0x8];
9912 };
9913
9914 struct mlx5_ifc_query_sf_partitions_out_bits {
9915         u8         status[0x8];
9916         u8         reserved_at_8[0x18];
9917
9918         u8         syndrome[0x20];
9919
9920         u8         reserved_at_40[0x18];
9921         u8         num_sf_partitions[0x8];
9922
9923         u8         reserved_at_60[0x20];
9924
9925         struct mlx5_ifc_sf_partition_bits sf_partition[0];
9926 };
9927
9928 struct mlx5_ifc_query_sf_partitions_in_bits {
9929         u8         opcode[0x10];
9930         u8         reserved_at_10[0x10];
9931
9932         u8         reserved_at_20[0x10];
9933         u8         op_mod[0x10];
9934
9935         u8         reserved_at_40[0x40];
9936 };
9937
9938 struct mlx5_ifc_dealloc_sf_out_bits {
9939         u8         status[0x8];
9940         u8         reserved_at_8[0x18];
9941
9942         u8         syndrome[0x20];
9943
9944         u8         reserved_at_40[0x40];
9945 };
9946
9947 struct mlx5_ifc_dealloc_sf_in_bits {
9948         u8         opcode[0x10];
9949         u8         reserved_at_10[0x10];
9950
9951         u8         reserved_at_20[0x10];
9952         u8         op_mod[0x10];
9953
9954         u8         reserved_at_40[0x10];
9955         u8         function_id[0x10];
9956
9957         u8         reserved_at_60[0x20];
9958 };
9959
9960 struct mlx5_ifc_alloc_sf_out_bits {
9961         u8         status[0x8];
9962         u8         reserved_at_8[0x18];
9963
9964         u8         syndrome[0x20];
9965
9966         u8         reserved_at_40[0x40];
9967 };
9968
9969 struct mlx5_ifc_alloc_sf_in_bits {
9970         u8         opcode[0x10];
9971         u8         reserved_at_10[0x10];
9972
9973         u8         reserved_at_20[0x10];
9974         u8         op_mod[0x10];
9975
9976         u8         reserved_at_40[0x10];
9977         u8         function_id[0x10];
9978
9979         u8         reserved_at_60[0x20];
9980 };
9981
9982 struct mlx5_ifc_affiliated_event_header_bits {
9983         u8         reserved_at_0[0x10];
9984         u8         obj_type[0x10];
9985
9986         u8         obj_id[0x20];
9987 };
9988
9989 enum {
9990         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9991 };
9992
9993 enum {
9994         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
9995 };
9996
9997 struct mlx5_ifc_encryption_key_obj_bits {
9998         u8         modify_field_select[0x40];
9999
10000         u8         reserved_at_40[0x14];
10001         u8         key_size[0x4];
10002         u8         reserved_at_58[0x4];
10003         u8         key_type[0x4];
10004
10005         u8         reserved_at_60[0x8];
10006         u8         pd[0x18];
10007
10008         u8         reserved_at_80[0x180];
10009         u8         key[8][0x20];
10010
10011         u8         reserved_at_300[0x500];
10012 };
10013
10014 struct mlx5_ifc_create_encryption_key_in_bits {
10015         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10016         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10017 };
10018
10019 enum {
10020         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10021         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10022 };
10023
10024 enum {
10025         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10026 };
10027
10028 struct mlx5_ifc_tls_static_params_bits {
10029         u8         const_2[0x2];
10030         u8         tls_version[0x4];
10031         u8         const_1[0x2];
10032         u8         reserved_at_8[0x14];
10033         u8         encryption_standard[0x4];
10034
10035         u8         reserved_at_20[0x20];
10036
10037         u8         initial_record_number[0x40];
10038
10039         u8         resync_tcp_sn[0x20];
10040
10041         u8         gcm_iv[0x20];
10042
10043         u8         implicit_iv[0x40];
10044
10045         u8         reserved_at_100[0x8];
10046         u8         dek_index[0x18];
10047
10048         u8         reserved_at_120[0xe0];
10049 };
10050
10051 struct mlx5_ifc_tls_progress_params_bits {
10052         u8         valid[0x1];
10053         u8         reserved_at_1[0x7];
10054         u8         pd[0x18];
10055
10056         u8         next_record_tcp_sn[0x20];
10057
10058         u8         hw_resync_tcp_sn[0x20];
10059
10060         u8         record_tracker_state[0x2];
10061         u8         auth_state[0x2];
10062         u8         reserved_at_64[0x4];
10063         u8         hw_offset_record_number[0x18];
10064 };
10065
10066 #endif /* MLX5_IFC_H */