include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
  96         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
  97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 132         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 133         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 134         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 135         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 136         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 137         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 138         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 139         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 140         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 141         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 142         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 143         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 145         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 146         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 147         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 148         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 149         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 150         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 151         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 152         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 153         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 154         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 155         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 156         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 157         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 158         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 159         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 160         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 161         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 162         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 163         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 164         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 165         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 166         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 167         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 168         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 169         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 170         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 171         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 172         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 173         MLX5_CMD_OP_NOP                           = 0x80d,
 174         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 175         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 178         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 179         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 180         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 181         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 182         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 183         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 184         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 185         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 186         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 187         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 188         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 189         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 190         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 191         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 192         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 193         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 194         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 195         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 196         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 197         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 198         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 199         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 200         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 201         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 202         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 203         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 204         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 205         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 206         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 207         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 208         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 209         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 210         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 211         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 212         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 213         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 214         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 215         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 216         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 217         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 218         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 219         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 220         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 222         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 223         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 224         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 225         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 226         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 227         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 228         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 229         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 230         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 231         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 232         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 233         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 234         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 235         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 236         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 237         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 238         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 239         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 240         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 241         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 242         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 243         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 244         MLX5_CMD_OP_MAX
 245 };
 246
 247 struct mlx5_ifc_flow_table_fields_supported_bits {
 248         u8         outer_dmac[0x1];
 249         u8         outer_smac[0x1];
 250         u8         outer_ether_type[0x1];
 251         u8         outer_ip_version[0x1];
 252         u8         outer_first_prio[0x1];
 253         u8         outer_first_cfi[0x1];
 254         u8         outer_first_vid[0x1];
 255         u8         outer_ipv4_ttl[0x1];
 256         u8         outer_second_prio[0x1];
 257         u8         outer_second_cfi[0x1];
 258         u8         outer_second_vid[0x1];
 259         u8         reserved_at_b[0x1];
 260         u8         outer_sip[0x1];
 261         u8         outer_dip[0x1];
 262         u8         outer_frag[0x1];
 263         u8         outer_ip_protocol[0x1];
 264         u8         outer_ip_ecn[0x1];
 265         u8         outer_ip_dscp[0x1];
 266         u8         outer_udp_sport[0x1];
 267         u8         outer_udp_dport[0x1];
 268         u8         outer_tcp_sport[0x1];
 269         u8         outer_tcp_dport[0x1];
 270         u8         outer_tcp_flags[0x1];
 271         u8         outer_gre_protocol[0x1];
 272         u8         outer_gre_key[0x1];
 273         u8         outer_vxlan_vni[0x1];
 274         u8         reserved_at_1a[0x5];
 275         u8         source_eswitch_port[0x1];
 276
 277         u8         inner_dmac[0x1];
 278         u8         inner_smac[0x1];
 279         u8         inner_ether_type[0x1];
 280         u8         inner_ip_version[0x1];
 281         u8         inner_first_prio[0x1];
 282         u8         inner_first_cfi[0x1];
 283         u8         inner_first_vid[0x1];
 284         u8         reserved_at_27[0x1];
 285         u8         inner_second_prio[0x1];
 286         u8         inner_second_cfi[0x1];
 287         u8         inner_second_vid[0x1];
 288         u8         reserved_at_2b[0x1];
 289         u8         inner_sip[0x1];
 290         u8         inner_dip[0x1];
 291         u8         inner_frag[0x1];
 292         u8         inner_ip_protocol[0x1];
 293         u8         inner_ip_ecn[0x1];
 294         u8         inner_ip_dscp[0x1];
 295         u8         inner_udp_sport[0x1];
 296         u8         inner_udp_dport[0x1];
 297         u8         inner_tcp_sport[0x1];
 298         u8         inner_tcp_dport[0x1];
 299         u8         inner_tcp_flags[0x1];
 300         u8         reserved_at_37[0x9];
 301         u8         reserved_at_40[0x17];
 302         u8         outer_esp_spi[0x1];
 303         u8         reserved_at_58[0x2];
 304         u8         bth_dst_qp[0x1];
 305
 306         u8         reserved_at_5b[0x25];
 307 };
 308
 309 struct mlx5_ifc_flow_table_prop_layout_bits {
 310         u8         ft_support[0x1];
 311         u8         reserved_at_1[0x1];
 312         u8         flow_counter[0x1];
 313         u8         flow_modify_en[0x1];
 314         u8         modify_root[0x1];
 315         u8         identified_miss_table_mode[0x1];
 316         u8         flow_table_modify[0x1];
 317         u8         encap[0x1];
 318         u8         decap[0x1];
 319         u8         reserved_at_9[0x1];
 320         u8         pop_vlan[0x1];
 321         u8         push_vlan[0x1];
 322         u8         reserved_at_c[0x14];
 323
 324         u8         reserved_at_20[0x2];
 325         u8         log_max_ft_size[0x6];
 326         u8         log_max_modify_header_context[0x8];
 327         u8         max_modify_header_actions[0x8];
 328         u8         max_ft_level[0x8];
 329
 330         u8         reserved_at_40[0x20];
 331
 332         u8         reserved_at_60[0x18];
 333         u8         log_max_ft_num[0x8];
 334
 335         u8         reserved_at_80[0x18];
 336         u8         log_max_destination[0x8];
 337
 338         u8         log_max_flow_counter[0x8];
 339         u8         reserved_at_a8[0x10];
 340         u8         log_max_flow[0x8];
 341
 342         u8         reserved_at_c0[0x40];
 343
 344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 345
 346         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 347 };
 348
 349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 350         u8         send[0x1];
 351         u8         receive[0x1];
 352         u8         write[0x1];
 353         u8         read[0x1];
 354         u8         atomic[0x1];
 355         u8         srq_receive[0x1];
 356         u8         reserved_at_6[0x1a];
 357 };
 358
 359 struct mlx5_ifc_ipv4_layout_bits {
 360         u8         reserved_at_0[0x60];
 361
 362         u8         ipv4[0x20];
 363 };
 364
 365 struct mlx5_ifc_ipv6_layout_bits {
 366         u8         ipv6[16][0x8];
 367 };
 368
 369 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 370         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 371         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 372         u8         reserved_at_0[0x80];
 373 };
 374
 375 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 376         u8         smac_47_16[0x20];
 377
 378         u8         smac_15_0[0x10];
 379         u8         ethertype[0x10];
 380
 381         u8         dmac_47_16[0x20];
 382
 383         u8         dmac_15_0[0x10];
 384         u8         first_prio[0x3];
 385         u8         first_cfi[0x1];
 386         u8         first_vid[0xc];
 387
 388         u8         ip_protocol[0x8];
 389         u8         ip_dscp[0x6];
 390         u8         ip_ecn[0x2];
 391         u8         cvlan_tag[0x1];
 392         u8         svlan_tag[0x1];
 393         u8         frag[0x1];
 394         u8         ip_version[0x4];
 395         u8         tcp_flags[0x9];
 396
 397         u8         tcp_sport[0x10];
 398         u8         tcp_dport[0x10];
 399
 400         u8         reserved_at_c0[0x18];
 401         u8         ttl_hoplimit[0x8];
 402
 403         u8         udp_sport[0x10];
 404         u8         udp_dport[0x10];
 405
 406         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 407
 408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 409 };
 410
 411 struct mlx5_ifc_fte_match_set_misc_bits {
 412         u8         reserved_at_0[0x8];
 413         u8         source_sqn[0x18];
 414
 415         u8         reserved_at_20[0x10];
 416         u8         source_port[0x10];
 417
 418         u8         outer_second_prio[0x3];
 419         u8         outer_second_cfi[0x1];
 420         u8         outer_second_vid[0xc];
 421         u8         inner_second_prio[0x3];
 422         u8         inner_second_cfi[0x1];
 423         u8         inner_second_vid[0xc];
 424
 425         u8         outer_second_cvlan_tag[0x1];
 426         u8         inner_second_cvlan_tag[0x1];
 427         u8         outer_second_svlan_tag[0x1];
 428         u8         inner_second_svlan_tag[0x1];
 429         u8         reserved_at_64[0xc];
 430         u8         gre_protocol[0x10];
 431
 432         u8         gre_key_h[0x18];
 433         u8         gre_key_l[0x8];
 434
 435         u8         vxlan_vni[0x18];
 436         u8         reserved_at_b8[0x8];
 437
 438         u8         reserved_at_c0[0x20];
 439
 440         u8         reserved_at_e0[0xc];
 441         u8         outer_ipv6_flow_label[0x14];
 442
 443         u8         reserved_at_100[0xc];
 444         u8         inner_ipv6_flow_label[0x14];
 445
 446         u8         reserved_at_120[0x28];
 447         u8         bth_dst_qp[0x18];
 448         u8         reserved_at_160[0x20];
 449         u8         outer_esp_spi[0x20];
 450         u8         reserved_at_1a0[0x60];
 451 };
 452
 453 struct mlx5_ifc_cmd_pas_bits {
 454         u8         pa_h[0x20];
 455
 456         u8         pa_l[0x14];
 457         u8         reserved_at_34[0xc];
 458 };
 459
 460 struct mlx5_ifc_uint64_bits {
 461         u8         hi[0x20];
 462
 463         u8         lo[0x20];
 464 };
 465
 466 enum {
 467         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 468         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 469         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 470         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 471         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 472         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 473         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 474         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 475         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 476         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 477 };
 478
 479 struct mlx5_ifc_ads_bits {
 480         u8         fl[0x1];
 481         u8         free_ar[0x1];
 482         u8         reserved_at_2[0xe];
 483         u8         pkey_index[0x10];
 484
 485         u8         reserved_at_20[0x8];
 486         u8         grh[0x1];
 487         u8         mlid[0x7];
 488         u8         rlid[0x10];
 489
 490         u8         ack_timeout[0x5];
 491         u8         reserved_at_45[0x3];
 492         u8         src_addr_index[0x8];
 493         u8         reserved_at_50[0x4];
 494         u8         stat_rate[0x4];
 495         u8         hop_limit[0x8];
 496
 497         u8         reserved_at_60[0x4];
 498         u8         tclass[0x8];
 499         u8         flow_label[0x14];
 500
 501         u8         rgid_rip[16][0x8];
 502
 503         u8         reserved_at_100[0x4];
 504         u8         f_dscp[0x1];
 505         u8         f_ecn[0x1];
 506         u8         reserved_at_106[0x1];
 507         u8         f_eth_prio[0x1];
 508         u8         ecn[0x2];
 509         u8         dscp[0x6];
 510         u8         udp_sport[0x10];
 511
 512         u8         dei_cfi[0x1];
 513         u8         eth_prio[0x3];
 514         u8         sl[0x4];
 515         u8         vhca_port_num[0x8];
 516         u8         rmac_47_32[0x10];
 517
 518         u8         rmac_31_0[0x20];
 519 };
 520
 521 struct mlx5_ifc_flow_table_nic_cap_bits {
 522         u8         nic_rx_multi_path_tirs[0x1];
 523         u8         nic_rx_multi_path_tirs_fts[0x1];
 524         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 525         u8         reserved_at_3[0x1fd];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 528
 529         u8         reserved_at_400[0x200];
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 532
 533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 534
 535         u8         reserved_at_a00[0x200];
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 538
 539         u8         reserved_at_e00[0x7200];
 540 };
 541
 542 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 543         u8     reserved_at_0[0x200];
 544
 545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 546
 547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 548
 549         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 550
 551         u8      reserved_at_800[0x7800];
 552 };
 553
 554 struct mlx5_ifc_e_switch_cap_bits {
 555         u8         vport_svlan_strip[0x1];
 556         u8         vport_cvlan_strip[0x1];
 557         u8         vport_svlan_insert[0x1];
 558         u8         vport_cvlan_insert_if_not_exist[0x1];
 559         u8         vport_cvlan_insert_overwrite[0x1];
 560         u8         reserved_at_5[0x19];
 561         u8         nic_vport_node_guid_modify[0x1];
 562         u8         nic_vport_port_guid_modify[0x1];
 563
 564         u8         vxlan_encap_decap[0x1];
 565         u8         nvgre_encap_decap[0x1];
 566         u8         reserved_at_22[0x9];
 567         u8         log_max_encap_headers[0x5];
 568         u8         reserved_2b[0x6];
 569         u8         max_encap_header_size[0xa];
 570
 571         u8         reserved_40[0x7c0];
 572
 573 };
 574
 575 struct mlx5_ifc_qos_cap_bits {
 576         u8         packet_pacing[0x1];
 577         u8         esw_scheduling[0x1];
 578         u8         esw_bw_share[0x1];
 579         u8         esw_rate_limit[0x1];
 580         u8         reserved_at_4[0x1];
 581         u8         packet_pacing_burst_bound[0x1];
 582         u8         packet_pacing_typical_size[0x1];
 583         u8         reserved_at_7[0x19];
 584
 585         u8         reserved_at_20[0x20];
 586
 587         u8         packet_pacing_max_rate[0x20];
 588
 589         u8         packet_pacing_min_rate[0x20];
 590
 591         u8         reserved_at_80[0x10];
 592         u8         packet_pacing_rate_table_size[0x10];
 593
 594         u8         esw_element_type[0x10];
 595         u8         esw_tsar_type[0x10];
 596
 597         u8         reserved_at_c0[0x10];
 598         u8         max_qos_para_vport[0x10];
 599
 600         u8         max_tsar_bw_share[0x20];
 601
 602         u8         reserved_at_100[0x700];
 603 };
 604
 605 struct mlx5_ifc_debug_cap_bits {
 606         u8         reserved_at_0[0x20];
 607
 608         u8         reserved_at_20[0x2];
 609         u8         stall_detect[0x1];
 610         u8         reserved_at_23[0x1d];
 611
 612         u8         reserved_at_40[0x7c0];
 613 };
 614
 615 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 616         u8         csum_cap[0x1];
 617         u8         vlan_cap[0x1];
 618         u8         lro_cap[0x1];
 619         u8         lro_psh_flag[0x1];
 620         u8         lro_time_stamp[0x1];
 621         u8         reserved_at_5[0x2];
 622         u8         wqe_vlan_insert[0x1];
 623         u8         self_lb_en_modifiable[0x1];
 624         u8         reserved_at_9[0x2];
 625         u8         max_lso_cap[0x5];
 626         u8         multi_pkt_send_wqe[0x2];
 627         u8         wqe_inline_mode[0x2];
 628         u8         rss_ind_tbl_cap[0x4];
 629         u8         reg_umr_sq[0x1];
 630         u8         scatter_fcs[0x1];
 631         u8         enhanced_multi_pkt_send_wqe[0x1];
 632         u8         tunnel_lso_const_out_ip_id[0x1];
 633         u8         reserved_at_1c[0x2];
 634         u8         tunnel_stateless_gre[0x1];
 635         u8         tunnel_stateless_vxlan[0x1];
 636
 637         u8         swp[0x1];
 638         u8         swp_csum[0x1];
 639         u8         swp_lso[0x1];
 640         u8         reserved_at_23[0x1b];
 641         u8         max_geneve_opt_len[0x1];
 642         u8         tunnel_stateless_geneve_rx[0x1];
 643
 644         u8         reserved_at_40[0x10];
 645         u8         lro_min_mss_size[0x10];
 646
 647         u8         reserved_at_60[0x120];
 648
 649         u8         lro_timer_supported_periods[4][0x20];
 650
 651         u8         reserved_at_200[0x600];
 652 };
 653
 654 struct mlx5_ifc_roce_cap_bits {
 655         u8         roce_apm[0x1];
 656         u8         reserved_at_1[0x1f];
 657
 658         u8         reserved_at_20[0x60];
 659
 660         u8         reserved_at_80[0xc];
 661         u8         l3_type[0x4];
 662         u8         reserved_at_90[0x8];
 663         u8         roce_version[0x8];
 664
 665         u8         reserved_at_a0[0x10];
 666         u8         r_roce_dest_udp_port[0x10];
 667
 668         u8         r_roce_max_src_udp_port[0x10];
 669         u8         r_roce_min_src_udp_port[0x10];
 670
 671         u8         reserved_at_e0[0x10];
 672         u8         roce_address_table_size[0x10];
 673
 674         u8         reserved_at_100[0x700];
 675 };
 676
 677 struct mlx5_ifc_device_mem_cap_bits {
 678         u8         memic[0x1];
 679         u8         reserved_at_1[0x1f];
 680
 681         u8         reserved_at_20[0xb];
 682         u8         log_min_memic_alloc_size[0x5];
 683         u8         reserved_at_30[0x8];
 684         u8         log_max_memic_addr_alignment[0x8];
 685
 686         u8         memic_bar_start_addr[0x40];
 687
 688         u8         memic_bar_size[0x20];
 689
 690         u8         max_memic_size[0x20];
 691
 692         u8         reserved_at_c0[0x740];
 693 };
 694
 695 enum {
 696         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 701         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 702         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 703         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 704         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 705 };
 706
 707 enum {
 708         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 709         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 710         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 711         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 712         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 717 };
 718
 719 struct mlx5_ifc_atomic_caps_bits {
 720         u8         reserved_at_0[0x40];
 721
 722         u8         atomic_req_8B_endianness_mode[0x2];
 723         u8         reserved_at_42[0x4];
 724         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 725
 726         u8         reserved_at_47[0x19];
 727
 728         u8         reserved_at_60[0x20];
 729
 730         u8         reserved_at_80[0x10];
 731         u8         atomic_operations[0x10];
 732
 733         u8         reserved_at_a0[0x10];
 734         u8         atomic_size_qp[0x10];
 735
 736         u8         reserved_at_c0[0x10];
 737         u8         atomic_size_dc[0x10];
 738
 739         u8         reserved_at_e0[0x720];
 740 };
 741
 742 struct mlx5_ifc_odp_cap_bits {
 743         u8         reserved_at_0[0x40];
 744
 745         u8         sig[0x1];
 746         u8         reserved_at_41[0x1f];
 747
 748         u8         reserved_at_60[0x20];
 749
 750         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 751
 752         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 753
 754         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 755
 756         u8         reserved_at_e0[0x720];
 757 };
 758
 759 struct mlx5_ifc_calc_op {
 760         u8        reserved_at_0[0x10];
 761         u8        reserved_at_10[0x9];
 762         u8        op_swap_endianness[0x1];
 763         u8        op_min[0x1];
 764         u8        op_xor[0x1];
 765         u8        op_or[0x1];
 766         u8        op_and[0x1];
 767         u8        op_max[0x1];
 768         u8        op_add[0x1];
 769 };
 770
 771 struct mlx5_ifc_vector_calc_cap_bits {
 772         u8         calc_matrix[0x1];
 773         u8         reserved_at_1[0x1f];
 774         u8         reserved_at_20[0x8];
 775         u8         max_vec_count[0x8];
 776         u8         reserved_at_30[0xd];
 777         u8         max_chunk_size[0x3];
 778         struct mlx5_ifc_calc_op calc0;
 779         struct mlx5_ifc_calc_op calc1;
 780         struct mlx5_ifc_calc_op calc2;
 781         struct mlx5_ifc_calc_op calc3;
 782
 783         u8         reserved_at_e0[0x720];
 784 };
 785
 786 enum {
 787         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 788         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 789         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 790         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 791 };
 792
 793 enum {
 794         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 795         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 796 };
 797
 798 enum {
 799         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 800         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 801         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 802         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 803         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 804 };
 805
 806 enum {
 807         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 808         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 809         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 810         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 811         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 812         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 813 };
 814
 815 enum {
 816         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 817         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 818 };
 819
 820 enum {
 821         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 822         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 823         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 824 };
 825
 826 enum {
 827         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 828         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 829 };
 830
 831 enum {
 832         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 833         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 834         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 835 };
 836
 837 struct mlx5_ifc_cmd_hca_cap_bits {
 838         u8         reserved_at_0[0x30];
 839         u8         vhca_id[0x10];
 840
 841         u8         reserved_at_40[0x40];
 842
 843         u8         log_max_srq_sz[0x8];
 844         u8         log_max_qp_sz[0x8];
 845         u8         reserved_at_90[0xb];
 846         u8         log_max_qp[0x5];
 847
 848         u8         reserved_at_a0[0xb];
 849         u8         log_max_srq[0x5];
 850         u8         reserved_at_b0[0x10];
 851
 852         u8         reserved_at_c0[0x8];
 853         u8         log_max_cq_sz[0x8];
 854         u8         reserved_at_d0[0xb];
 855         u8         log_max_cq[0x5];
 856
 857         u8         log_max_eq_sz[0x8];
 858         u8         reserved_at_e8[0x2];
 859         u8         log_max_mkey[0x6];
 860         u8         reserved_at_f0[0xc];
 861         u8         log_max_eq[0x4];
 862
 863         u8         max_indirection[0x8];
 864         u8         fixed_buffer_size[0x1];
 865         u8         log_max_mrw_sz[0x7];
 866         u8         force_teardown[0x1];
 867         u8         reserved_at_111[0x1];
 868         u8         log_max_bsf_list_size[0x6];
 869         u8         umr_extended_translation_offset[0x1];
 870         u8         null_mkey[0x1];
 871         u8         log_max_klm_list_size[0x6];
 872
 873         u8         reserved_at_120[0xa];
 874         u8         log_max_ra_req_dc[0x6];
 875         u8         reserved_at_130[0xa];
 876         u8         log_max_ra_res_dc[0x6];
 877
 878         u8         reserved_at_140[0xa];
 879         u8         log_max_ra_req_qp[0x6];
 880         u8         reserved_at_150[0xa];
 881         u8         log_max_ra_res_qp[0x6];
 882
 883         u8         end_pad[0x1];
 884         u8         cc_query_allowed[0x1];
 885         u8         cc_modify_allowed[0x1];
 886         u8         start_pad[0x1];
 887         u8         cache_line_128byte[0x1];
 888         u8         reserved_at_165[0xa];
 889         u8         qcam_reg[0x1];
 890         u8         gid_table_size[0x10];
 891
 892         u8         out_of_seq_cnt[0x1];
 893         u8         vport_counters[0x1];
 894         u8         retransmission_q_counters[0x1];
 895         u8         debug[0x1];
 896         u8         modify_rq_counter_set_id[0x1];
 897         u8         rq_delay_drop[0x1];
 898         u8         max_qp_cnt[0xa];
 899         u8         pkey_table_size[0x10];
 900
 901         u8         vport_group_manager[0x1];
 902         u8         vhca_group_manager[0x1];
 903         u8         ib_virt[0x1];
 904         u8         eth_virt[0x1];
 905         u8         vnic_env_queue_counters[0x1];
 906         u8         ets[0x1];
 907         u8         nic_flow_table[0x1];
 908         u8         eswitch_flow_table[0x1];
 909         u8         device_memory[0x1];
 910         u8         mcam_reg[0x1];
 911         u8         pcam_reg[0x1];
 912         u8         local_ca_ack_delay[0x5];
 913         u8         port_module_event[0x1];
 914         u8         enhanced_error_q_counters[0x1];
 915         u8         ports_check[0x1];
 916         u8         reserved_at_1b3[0x1];
 917         u8         disable_link_up[0x1];
 918         u8         beacon_led[0x1];
 919         u8         port_type[0x2];
 920         u8         num_ports[0x8];
 921
 922         u8         reserved_at_1c0[0x1];
 923         u8         pps[0x1];
 924         u8         pps_modify[0x1];
 925         u8         log_max_msg[0x5];
 926         u8         reserved_at_1c8[0x4];
 927         u8         max_tc[0x4];
 928         u8         reserved_at_1d0[0x1];
 929         u8         dcbx[0x1];
 930         u8         general_notification_event[0x1];
 931         u8         reserved_at_1d3[0x2];
 932         u8         fpga[0x1];
 933         u8         rol_s[0x1];
 934         u8         rol_g[0x1];
 935         u8         reserved_at_1d8[0x1];
 936         u8         wol_s[0x1];
 937         u8         wol_g[0x1];
 938         u8         wol_a[0x1];
 939         u8         wol_b[0x1];
 940         u8         wol_m[0x1];
 941         u8         wol_u[0x1];
 942         u8         wol_p[0x1];
 943
 944         u8         stat_rate_support[0x10];
 945         u8         reserved_at_1f0[0xc];
 946         u8         cqe_version[0x4];
 947
 948         u8         compact_address_vector[0x1];
 949         u8         striding_rq[0x1];
 950         u8         reserved_at_202[0x1];
 951         u8         ipoib_enhanced_offloads[0x1];
 952         u8         ipoib_basic_offloads[0x1];
 953         u8         reserved_at_205[0x1];
 954         u8         repeated_block_disabled[0x1];
 955         u8         umr_modify_entity_size_disabled[0x1];
 956         u8         umr_modify_atomic_disabled[0x1];
 957         u8         umr_indirect_mkey_disabled[0x1];
 958         u8         umr_fence[0x2];
 959         u8         reserved_at_20c[0x3];
 960         u8         drain_sigerr[0x1];
 961         u8         cmdif_checksum[0x2];
 962         u8         sigerr_cqe[0x1];
 963         u8         reserved_at_213[0x1];
 964         u8         wq_signature[0x1];
 965         u8         sctr_data_cqe[0x1];
 966         u8         reserved_at_216[0x1];
 967         u8         sho[0x1];
 968         u8         tph[0x1];
 969         u8         rf[0x1];
 970         u8         dct[0x1];
 971         u8         qos[0x1];
 972         u8         eth_net_offloads[0x1];
 973         u8         roce[0x1];
 974         u8         atomic[0x1];
 975         u8         reserved_at_21f[0x1];
 976
 977         u8         cq_oi[0x1];
 978         u8         cq_resize[0x1];
 979         u8         cq_moderation[0x1];
 980         u8         reserved_at_223[0x3];
 981         u8         cq_eq_remap[0x1];
 982         u8         pg[0x1];
 983         u8         block_lb_mc[0x1];
 984         u8         reserved_at_229[0x1];
 985         u8         scqe_break_moderation[0x1];
 986         u8         cq_period_start_from_cqe[0x1];
 987         u8         cd[0x1];
 988         u8         reserved_at_22d[0x1];
 989         u8         apm[0x1];
 990         u8         vector_calc[0x1];
 991         u8         umr_ptr_rlky[0x1];
 992         u8         imaicl[0x1];
 993         u8         reserved_at_232[0x4];
 994         u8         qkv[0x1];
 995         u8         pkv[0x1];
 996         u8         set_deth_sqpn[0x1];
 997         u8         reserved_at_239[0x3];
 998         u8         xrc[0x1];
 999         u8         ud[0x1];
1000         u8         uc[0x1];
1001         u8         rc[0x1];
1002
1003         u8         uar_4k[0x1];
1004         u8         reserved_at_241[0x9];
1005         u8         uar_sz[0x6];
1006         u8         reserved_at_250[0x8];
1007         u8         log_pg_sz[0x8];
1008
1009         u8         bf[0x1];
1010         u8         driver_version[0x1];
1011         u8         pad_tx_eth_packet[0x1];
1012         u8         reserved_at_263[0x8];
1013         u8         log_bf_reg_size[0x5];
1014
1015         u8         reserved_at_270[0xb];
1016         u8         lag_master[0x1];
1017         u8         num_lag_ports[0x4];
1018
1019         u8         reserved_at_280[0x10];
1020         u8         max_wqe_sz_sq[0x10];
1021
1022         u8         reserved_at_2a0[0x10];
1023         u8         max_wqe_sz_rq[0x10];
1024
1025         u8         max_flow_counter_31_16[0x10];
1026         u8         max_wqe_sz_sq_dc[0x10];
1027
1028         u8         reserved_at_2e0[0x7];
1029         u8         max_qp_mcg[0x19];
1030
1031         u8         reserved_at_300[0x18];
1032         u8         log_max_mcg[0x8];
1033
1034         u8         reserved_at_320[0x3];
1035         u8         log_max_transport_domain[0x5];
1036         u8         reserved_at_328[0x3];
1037         u8         log_max_pd[0x5];
1038         u8         reserved_at_330[0xb];
1039         u8         log_max_xrcd[0x5];
1040
1041         u8         nic_receive_steering_discard[0x1];
1042         u8         receive_discard_vport_down[0x1];
1043         u8         transmit_discard_vport_down[0x1];
1044         u8         reserved_at_343[0x5];
1045         u8         log_max_flow_counter_bulk[0x8];
1046         u8         max_flow_counter_15_0[0x10];
1047
1048
1049         u8         reserved_at_360[0x3];
1050         u8         log_max_rq[0x5];
1051         u8         reserved_at_368[0x3];
1052         u8         log_max_sq[0x5];
1053         u8         reserved_at_370[0x3];
1054         u8         log_max_tir[0x5];
1055         u8         reserved_at_378[0x3];
1056         u8         log_max_tis[0x5];
1057
1058         u8         basic_cyclic_rcv_wqe[0x1];
1059         u8         reserved_at_381[0x2];
1060         u8         log_max_rmp[0x5];
1061         u8         reserved_at_388[0x3];
1062         u8         log_max_rqt[0x5];
1063         u8         reserved_at_390[0x3];
1064         u8         log_max_rqt_size[0x5];
1065         u8         reserved_at_398[0x3];
1066         u8         log_max_tis_per_sq[0x5];
1067
1068         u8         ext_stride_num_range[0x1];
1069         u8         reserved_at_3a1[0x2];
1070         u8         log_max_stride_sz_rq[0x5];
1071         u8         reserved_at_3a8[0x3];
1072         u8         log_min_stride_sz_rq[0x5];
1073         u8         reserved_at_3b0[0x3];
1074         u8         log_max_stride_sz_sq[0x5];
1075         u8         reserved_at_3b8[0x3];
1076         u8         log_min_stride_sz_sq[0x5];
1077
1078         u8         hairpin[0x1];
1079         u8         reserved_at_3c1[0x2];
1080         u8         log_max_hairpin_queues[0x5];
1081         u8         reserved_at_3c8[0x3];
1082         u8         log_max_hairpin_wq_data_sz[0x5];
1083         u8         reserved_at_3d0[0x3];
1084         u8         log_max_hairpin_num_packets[0x5];
1085         u8         reserved_at_3d8[0x3];
1086         u8         log_max_wq_sz[0x5];
1087
1088         u8         nic_vport_change_event[0x1];
1089         u8         disable_local_lb_uc[0x1];
1090         u8         disable_local_lb_mc[0x1];
1091         u8         log_min_hairpin_wq_data_sz[0x5];
1092         u8         reserved_at_3e8[0x3];
1093         u8         log_max_vlan_list[0x5];
1094         u8         reserved_at_3f0[0x3];
1095         u8         log_max_current_mc_list[0x5];
1096         u8         reserved_at_3f8[0x3];
1097         u8         log_max_current_uc_list[0x5];
1098
1099         u8         reserved_at_400[0x80];
1100
1101         u8         reserved_at_480[0x3];
1102         u8         log_max_l2_table[0x5];
1103         u8         reserved_at_488[0x8];
1104         u8         log_uar_page_sz[0x10];
1105
1106         u8         reserved_at_4a0[0x20];
1107         u8         device_frequency_mhz[0x20];
1108         u8         device_frequency_khz[0x20];
1109
1110         u8         reserved_at_500[0x20];
1111         u8         num_of_uars_per_page[0x20];
1112         u8         reserved_at_540[0x40];
1113
1114         u8         reserved_at_580[0x3d];
1115         u8         cqe_128_always[0x1];
1116         u8         cqe_compression_128[0x1];
1117         u8         cqe_compression[0x1];
1118
1119         u8         cqe_compression_timeout[0x10];
1120         u8         cqe_compression_max_num[0x10];
1121
1122         u8         reserved_at_5e0[0x10];
1123         u8         tag_matching[0x1];
1124         u8         rndv_offload_rc[0x1];
1125         u8         rndv_offload_dc[0x1];
1126         u8         log_tag_matching_list_sz[0x5];
1127         u8         reserved_at_5f8[0x3];
1128         u8         log_max_xrq[0x5];
1129
1130         u8         affiliate_nic_vport_criteria[0x8];
1131         u8         native_port_num[0x8];
1132         u8         num_vhca_ports[0x8];
1133         u8         reserved_at_618[0x6];
1134         u8         sw_owner_id[0x1];
1135         u8         reserved_at_61f[0x1e1];
1136 };
1137
1138 enum mlx5_flow_destination_type {
1139         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1140         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1141         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1142
1143         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1144         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1145 };
1146
1147 struct mlx5_ifc_dest_format_struct_bits {
1148         u8         destination_type[0x8];
1149         u8         destination_id[0x18];
1150
1151         u8         reserved_at_20[0x20];
1152 };
1153
1154 struct mlx5_ifc_flow_counter_list_bits {
1155         u8         flow_counter_id[0x20];
1156
1157         u8         reserved_at_20[0x20];
1158 };
1159
1160 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1161         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1162         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1163         u8         reserved_at_0[0x40];
1164 };
1165
1166 struct mlx5_ifc_fte_match_param_bits {
1167         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1168
1169         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1170
1171         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1172
1173         u8         reserved_at_600[0xa00];
1174 };
1175
1176 enum {
1177         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1178         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1179         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1180         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1181         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1182 };
1183
1184 struct mlx5_ifc_rx_hash_field_select_bits {
1185         u8         l3_prot_type[0x1];
1186         u8         l4_prot_type[0x1];
1187         u8         selected_fields[0x1e];
1188 };
1189
1190 enum {
1191         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1192         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1193 };
1194
1195 enum {
1196         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1197         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1198 };
1199
1200 struct mlx5_ifc_wq_bits {
1201         u8         wq_type[0x4];
1202         u8         wq_signature[0x1];
1203         u8         end_padding_mode[0x2];
1204         u8         cd_slave[0x1];
1205         u8         reserved_at_8[0x18];
1206
1207         u8         hds_skip_first_sge[0x1];
1208         u8         log2_hds_buf_size[0x3];
1209         u8         reserved_at_24[0x7];
1210         u8         page_offset[0x5];
1211         u8         lwm[0x10];
1212
1213         u8         reserved_at_40[0x8];
1214         u8         pd[0x18];
1215
1216         u8         reserved_at_60[0x8];
1217         u8         uar_page[0x18];
1218
1219         u8         dbr_addr[0x40];
1220
1221         u8         hw_counter[0x20];
1222
1223         u8         sw_counter[0x20];
1224
1225         u8         reserved_at_100[0xc];
1226         u8         log_wq_stride[0x4];
1227         u8         reserved_at_110[0x3];
1228         u8         log_wq_pg_sz[0x5];
1229         u8         reserved_at_118[0x3];
1230         u8         log_wq_sz[0x5];
1231
1232         u8         reserved_at_120[0x3];
1233         u8         log_hairpin_num_packets[0x5];
1234         u8         reserved_at_128[0x3];
1235         u8         log_hairpin_data_sz[0x5];
1236
1237         u8         reserved_at_130[0x4];
1238         u8         log_wqe_num_of_strides[0x4];
1239         u8         two_byte_shift_en[0x1];
1240         u8         reserved_at_139[0x4];
1241         u8         log_wqe_stride_size[0x3];
1242
1243         u8         reserved_at_140[0x4c0];
1244
1245         struct mlx5_ifc_cmd_pas_bits pas[0];
1246 };
1247
1248 struct mlx5_ifc_rq_num_bits {
1249         u8         reserved_at_0[0x8];
1250         u8         rq_num[0x18];
1251 };
1252
1253 struct mlx5_ifc_mac_address_layout_bits {
1254         u8         reserved_at_0[0x10];
1255         u8         mac_addr_47_32[0x10];
1256
1257         u8         mac_addr_31_0[0x20];
1258 };
1259
1260 struct mlx5_ifc_vlan_layout_bits {
1261         u8         reserved_at_0[0x14];
1262         u8         vlan[0x0c];
1263
1264         u8         reserved_at_20[0x20];
1265 };
1266
1267 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1268         u8         reserved_at_0[0xa0];
1269
1270         u8         min_time_between_cnps[0x20];
1271
1272         u8         reserved_at_c0[0x12];
1273         u8         cnp_dscp[0x6];
1274         u8         reserved_at_d8[0x4];
1275         u8         cnp_prio_mode[0x1];
1276         u8         cnp_802p_prio[0x3];
1277
1278         u8         reserved_at_e0[0x720];
1279 };
1280
1281 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1282         u8         reserved_at_0[0x60];
1283
1284         u8         reserved_at_60[0x4];
1285         u8         clamp_tgt_rate[0x1];
1286         u8         reserved_at_65[0x3];
1287         u8         clamp_tgt_rate_after_time_inc[0x1];
1288         u8         reserved_at_69[0x17];
1289
1290         u8         reserved_at_80[0x20];
1291
1292         u8         rpg_time_reset[0x20];
1293
1294         u8         rpg_byte_reset[0x20];
1295
1296         u8         rpg_threshold[0x20];
1297
1298         u8         rpg_max_rate[0x20];
1299
1300         u8         rpg_ai_rate[0x20];
1301
1302         u8         rpg_hai_rate[0x20];
1303
1304         u8         rpg_gd[0x20];
1305
1306         u8         rpg_min_dec_fac[0x20];
1307
1308         u8         rpg_min_rate[0x20];
1309
1310         u8         reserved_at_1c0[0xe0];
1311
1312         u8         rate_to_set_on_first_cnp[0x20];
1313
1314         u8         dce_tcp_g[0x20];
1315
1316         u8         dce_tcp_rtt[0x20];
1317
1318         u8         rate_reduce_monitor_period[0x20];
1319
1320         u8         reserved_at_320[0x20];
1321
1322         u8         initial_alpha_value[0x20];
1323
1324         u8         reserved_at_360[0x4a0];
1325 };
1326
1327 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1328         u8         reserved_at_0[0x80];
1329
1330         u8         rppp_max_rps[0x20];
1331
1332         u8         rpg_time_reset[0x20];
1333
1334         u8         rpg_byte_reset[0x20];
1335
1336         u8         rpg_threshold[0x20];
1337
1338         u8         rpg_max_rate[0x20];
1339
1340         u8         rpg_ai_rate[0x20];
1341
1342         u8         rpg_hai_rate[0x20];
1343
1344         u8         rpg_gd[0x20];
1345
1346         u8         rpg_min_dec_fac[0x20];
1347
1348         u8         rpg_min_rate[0x20];
1349
1350         u8         reserved_at_1c0[0x640];
1351 };
1352
1353 enum {
1354         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1355         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1356         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1357 };
1358
1359 struct mlx5_ifc_resize_field_select_bits {
1360         u8         resize_field_select[0x20];
1361 };
1362
1363 enum {
1364         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1365         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1366         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1367         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1368 };
1369
1370 struct mlx5_ifc_modify_field_select_bits {
1371         u8         modify_field_select[0x20];
1372 };
1373
1374 struct mlx5_ifc_field_select_r_roce_np_bits {
1375         u8         field_select_r_roce_np[0x20];
1376 };
1377
1378 struct mlx5_ifc_field_select_r_roce_rp_bits {
1379         u8         field_select_r_roce_rp[0x20];
1380 };
1381
1382 enum {
1383         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1384         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1385         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1392         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1393 };
1394
1395 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1396         u8         field_select_8021qaurp[0x20];
1397 };
1398
1399 struct mlx5_ifc_phys_layer_cntrs_bits {
1400         u8         time_since_last_clear_high[0x20];
1401
1402         u8         time_since_last_clear_low[0x20];
1403
1404         u8         symbol_errors_high[0x20];
1405
1406         u8         symbol_errors_low[0x20];
1407
1408         u8         sync_headers_errors_high[0x20];
1409
1410         u8         sync_headers_errors_low[0x20];
1411
1412         u8         edpl_bip_errors_lane0_high[0x20];
1413
1414         u8         edpl_bip_errors_lane0_low[0x20];
1415
1416         u8         edpl_bip_errors_lane1_high[0x20];
1417
1418         u8         edpl_bip_errors_lane1_low[0x20];
1419
1420         u8         edpl_bip_errors_lane2_high[0x20];
1421
1422         u8         edpl_bip_errors_lane2_low[0x20];
1423
1424         u8         edpl_bip_errors_lane3_high[0x20];
1425
1426         u8         edpl_bip_errors_lane3_low[0x20];
1427
1428         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1429
1430         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1431
1432         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1433
1434         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1435
1436         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1437
1438         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1439
1440         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1441
1442         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1443
1444         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1445
1446         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1447
1448         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1449
1450         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1451
1452         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1453
1454         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1455
1456         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1457
1458         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1459
1460         u8         rs_fec_corrected_blocks_high[0x20];
1461
1462         u8         rs_fec_corrected_blocks_low[0x20];
1463
1464         u8         rs_fec_uncorrectable_blocks_high[0x20];
1465
1466         u8         rs_fec_uncorrectable_blocks_low[0x20];
1467
1468         u8         rs_fec_no_errors_blocks_high[0x20];
1469
1470         u8         rs_fec_no_errors_blocks_low[0x20];
1471
1472         u8         rs_fec_single_error_blocks_high[0x20];
1473
1474         u8         rs_fec_single_error_blocks_low[0x20];
1475
1476         u8         rs_fec_corrected_symbols_total_high[0x20];
1477
1478         u8         rs_fec_corrected_symbols_total_low[0x20];
1479
1480         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1481
1482         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1483
1484         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1485
1486         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1487
1488         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1489
1490         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1491
1492         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1493
1494         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1495
1496         u8         link_down_events[0x20];
1497
1498         u8         successful_recovery_events[0x20];
1499
1500         u8         reserved_at_640[0x180];
1501 };
1502
1503 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1504         u8         time_since_last_clear_high[0x20];
1505
1506         u8         time_since_last_clear_low[0x20];
1507
1508         u8         phy_received_bits_high[0x20];
1509
1510         u8         phy_received_bits_low[0x20];
1511
1512         u8         phy_symbol_errors_high[0x20];
1513
1514         u8         phy_symbol_errors_low[0x20];
1515
1516         u8         phy_corrected_bits_high[0x20];
1517
1518         u8         phy_corrected_bits_low[0x20];
1519
1520         u8         phy_corrected_bits_lane0_high[0x20];
1521
1522         u8         phy_corrected_bits_lane0_low[0x20];
1523
1524         u8         phy_corrected_bits_lane1_high[0x20];
1525
1526         u8         phy_corrected_bits_lane1_low[0x20];
1527
1528         u8         phy_corrected_bits_lane2_high[0x20];
1529
1530         u8         phy_corrected_bits_lane2_low[0x20];
1531
1532         u8         phy_corrected_bits_lane3_high[0x20];
1533
1534         u8         phy_corrected_bits_lane3_low[0x20];
1535
1536         u8         reserved_at_200[0x5c0];
1537 };
1538
1539 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1540         u8         symbol_error_counter[0x10];
1541
1542         u8         link_error_recovery_counter[0x8];
1543
1544         u8         link_downed_counter[0x8];
1545
1546         u8         port_rcv_errors[0x10];
1547
1548         u8         port_rcv_remote_physical_errors[0x10];
1549
1550         u8         port_rcv_switch_relay_errors[0x10];
1551
1552         u8         port_xmit_discards[0x10];
1553
1554         u8         port_xmit_constraint_errors[0x8];
1555
1556         u8         port_rcv_constraint_errors[0x8];
1557
1558         u8         reserved_at_70[0x8];
1559
1560         u8         link_overrun_errors[0x8];
1561
1562         u8         reserved_at_80[0x10];
1563
1564         u8         vl_15_dropped[0x10];
1565
1566         u8         reserved_at_a0[0x80];
1567
1568         u8         port_xmit_wait[0x20];
1569 };
1570
1571 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1572         u8         transmit_queue_high[0x20];
1573
1574         u8         transmit_queue_low[0x20];
1575
1576         u8         reserved_at_40[0x780];
1577 };
1578
1579 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1580         u8         rx_octets_high[0x20];
1581
1582         u8         rx_octets_low[0x20];
1583
1584         u8         reserved_at_40[0xc0];
1585
1586         u8         rx_frames_high[0x20];
1587
1588         u8         rx_frames_low[0x20];
1589
1590         u8         tx_octets_high[0x20];
1591
1592         u8         tx_octets_low[0x20];
1593
1594         u8         reserved_at_180[0xc0];
1595
1596         u8         tx_frames_high[0x20];
1597
1598         u8         tx_frames_low[0x20];
1599
1600         u8         rx_pause_high[0x20];
1601
1602         u8         rx_pause_low[0x20];
1603
1604         u8         rx_pause_duration_high[0x20];
1605
1606         u8         rx_pause_duration_low[0x20];
1607
1608         u8         tx_pause_high[0x20];
1609
1610         u8         tx_pause_low[0x20];
1611
1612         u8         tx_pause_duration_high[0x20];
1613
1614         u8         tx_pause_duration_low[0x20];
1615
1616         u8         rx_pause_transition_high[0x20];
1617
1618         u8         rx_pause_transition_low[0x20];
1619
1620         u8         reserved_at_3c0[0x40];
1621
1622         u8         device_stall_minor_watermark_cnt_high[0x20];
1623
1624         u8         device_stall_minor_watermark_cnt_low[0x20];
1625
1626         u8         device_stall_critical_watermark_cnt_high[0x20];
1627
1628         u8         device_stall_critical_watermark_cnt_low[0x20];
1629
1630         u8         reserved_at_480[0x340];
1631 };
1632
1633 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1634         u8         port_transmit_wait_high[0x20];
1635
1636         u8         port_transmit_wait_low[0x20];
1637
1638         u8         reserved_at_40[0x100];
1639
1640         u8         rx_buffer_almost_full_high[0x20];
1641
1642         u8         rx_buffer_almost_full_low[0x20];
1643
1644         u8         rx_buffer_full_high[0x20];
1645
1646         u8         rx_buffer_full_low[0x20];
1647
1648         u8         reserved_at_1c0[0x600];
1649 };
1650
1651 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1652         u8         dot3stats_alignment_errors_high[0x20];
1653
1654         u8         dot3stats_alignment_errors_low[0x20];
1655
1656         u8         dot3stats_fcs_errors_high[0x20];
1657
1658         u8         dot3stats_fcs_errors_low[0x20];
1659
1660         u8         dot3stats_single_collision_frames_high[0x20];
1661
1662         u8         dot3stats_single_collision_frames_low[0x20];
1663
1664         u8         dot3stats_multiple_collision_frames_high[0x20];
1665
1666         u8         dot3stats_multiple_collision_frames_low[0x20];
1667
1668         u8         dot3stats_sqe_test_errors_high[0x20];
1669
1670         u8         dot3stats_sqe_test_errors_low[0x20];
1671
1672         u8         dot3stats_deferred_transmissions_high[0x20];
1673
1674         u8         dot3stats_deferred_transmissions_low[0x20];
1675
1676         u8         dot3stats_late_collisions_high[0x20];
1677
1678         u8         dot3stats_late_collisions_low[0x20];
1679
1680         u8         dot3stats_excessive_collisions_high[0x20];
1681
1682         u8         dot3stats_excessive_collisions_low[0x20];
1683
1684         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1685
1686         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1687
1688         u8         dot3stats_carrier_sense_errors_high[0x20];
1689
1690         u8         dot3stats_carrier_sense_errors_low[0x20];
1691
1692         u8         dot3stats_frame_too_longs_high[0x20];
1693
1694         u8         dot3stats_frame_too_longs_low[0x20];
1695
1696         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1697
1698         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1699
1700         u8         dot3stats_symbol_errors_high[0x20];
1701
1702         u8         dot3stats_symbol_errors_low[0x20];
1703
1704         u8         dot3control_in_unknown_opcodes_high[0x20];
1705
1706         u8         dot3control_in_unknown_opcodes_low[0x20];
1707
1708         u8         dot3in_pause_frames_high[0x20];
1709
1710         u8         dot3in_pause_frames_low[0x20];
1711
1712         u8         dot3out_pause_frames_high[0x20];
1713
1714         u8         dot3out_pause_frames_low[0x20];
1715
1716         u8         reserved_at_400[0x3c0];
1717 };
1718
1719 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1720         u8         ether_stats_drop_events_high[0x20];
1721
1722         u8         ether_stats_drop_events_low[0x20];
1723
1724         u8         ether_stats_octets_high[0x20];
1725
1726         u8         ether_stats_octets_low[0x20];
1727
1728         u8         ether_stats_pkts_high[0x20];
1729
1730         u8         ether_stats_pkts_low[0x20];
1731
1732         u8         ether_stats_broadcast_pkts_high[0x20];
1733
1734         u8         ether_stats_broadcast_pkts_low[0x20];
1735
1736         u8         ether_stats_multicast_pkts_high[0x20];
1737
1738         u8         ether_stats_multicast_pkts_low[0x20];
1739
1740         u8         ether_stats_crc_align_errors_high[0x20];
1741
1742         u8         ether_stats_crc_align_errors_low[0x20];
1743
1744         u8         ether_stats_undersize_pkts_high[0x20];
1745
1746         u8         ether_stats_undersize_pkts_low[0x20];
1747
1748         u8         ether_stats_oversize_pkts_high[0x20];
1749
1750         u8         ether_stats_oversize_pkts_low[0x20];
1751
1752         u8         ether_stats_fragments_high[0x20];
1753
1754         u8         ether_stats_fragments_low[0x20];
1755
1756         u8         ether_stats_jabbers_high[0x20];
1757
1758         u8         ether_stats_jabbers_low[0x20];
1759
1760         u8         ether_stats_collisions_high[0x20];
1761
1762         u8         ether_stats_collisions_low[0x20];
1763
1764         u8         ether_stats_pkts64octets_high[0x20];
1765
1766         u8         ether_stats_pkts64octets_low[0x20];
1767
1768         u8         ether_stats_pkts65to127octets_high[0x20];
1769
1770         u8         ether_stats_pkts65to127octets_low[0x20];
1771
1772         u8         ether_stats_pkts128to255octets_high[0x20];
1773
1774         u8         ether_stats_pkts128to255octets_low[0x20];
1775
1776         u8         ether_stats_pkts256to511octets_high[0x20];
1777
1778         u8         ether_stats_pkts256to511octets_low[0x20];
1779
1780         u8         ether_stats_pkts512to1023octets_high[0x20];
1781
1782         u8         ether_stats_pkts512to1023octets_low[0x20];
1783
1784         u8         ether_stats_pkts1024to1518octets_high[0x20];
1785
1786         u8         ether_stats_pkts1024to1518octets_low[0x20];
1787
1788         u8         ether_stats_pkts1519to2047octets_high[0x20];
1789
1790         u8         ether_stats_pkts1519to2047octets_low[0x20];
1791
1792         u8         ether_stats_pkts2048to4095octets_high[0x20];
1793
1794         u8         ether_stats_pkts2048to4095octets_low[0x20];
1795
1796         u8         ether_stats_pkts4096to8191octets_high[0x20];
1797
1798         u8         ether_stats_pkts4096to8191octets_low[0x20];
1799
1800         u8         ether_stats_pkts8192to10239octets_high[0x20];
1801
1802         u8         ether_stats_pkts8192to10239octets_low[0x20];
1803
1804         u8         reserved_at_540[0x280];
1805 };
1806
1807 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1808         u8         if_in_octets_high[0x20];
1809
1810         u8         if_in_octets_low[0x20];
1811
1812         u8         if_in_ucast_pkts_high[0x20];
1813
1814         u8         if_in_ucast_pkts_low[0x20];
1815
1816         u8         if_in_discards_high[0x20];
1817
1818         u8         if_in_discards_low[0x20];
1819
1820         u8         if_in_errors_high[0x20];
1821
1822         u8         if_in_errors_low[0x20];
1823
1824         u8         if_in_unknown_protos_high[0x20];
1825
1826         u8         if_in_unknown_protos_low[0x20];
1827
1828         u8         if_out_octets_high[0x20];
1829
1830         u8         if_out_octets_low[0x20];
1831
1832         u8         if_out_ucast_pkts_high[0x20];
1833
1834         u8         if_out_ucast_pkts_low[0x20];
1835
1836         u8         if_out_discards_high[0x20];
1837
1838         u8         if_out_discards_low[0x20];
1839
1840         u8         if_out_errors_high[0x20];
1841
1842         u8         if_out_errors_low[0x20];
1843
1844         u8         if_in_multicast_pkts_high[0x20];
1845
1846         u8         if_in_multicast_pkts_low[0x20];
1847
1848         u8         if_in_broadcast_pkts_high[0x20];
1849
1850         u8         if_in_broadcast_pkts_low[0x20];
1851
1852         u8         if_out_multicast_pkts_high[0x20];
1853
1854         u8         if_out_multicast_pkts_low[0x20];
1855
1856         u8         if_out_broadcast_pkts_high[0x20];
1857
1858         u8         if_out_broadcast_pkts_low[0x20];
1859
1860         u8         reserved_at_340[0x480];
1861 };
1862
1863 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1864         u8         a_frames_transmitted_ok_high[0x20];
1865
1866         u8         a_frames_transmitted_ok_low[0x20];
1867
1868         u8         a_frames_received_ok_high[0x20];
1869
1870         u8         a_frames_received_ok_low[0x20];
1871
1872         u8         a_frame_check_sequence_errors_high[0x20];
1873
1874         u8         a_frame_check_sequence_errors_low[0x20];
1875
1876         u8         a_alignment_errors_high[0x20];
1877
1878         u8         a_alignment_errors_low[0x20];
1879
1880         u8         a_octets_transmitted_ok_high[0x20];
1881
1882         u8         a_octets_transmitted_ok_low[0x20];
1883
1884         u8         a_octets_received_ok_high[0x20];
1885
1886         u8         a_octets_received_ok_low[0x20];
1887
1888         u8         a_multicast_frames_xmitted_ok_high[0x20];
1889
1890         u8         a_multicast_frames_xmitted_ok_low[0x20];
1891
1892         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1893
1894         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1895
1896         u8         a_multicast_frames_received_ok_high[0x20];
1897
1898         u8         a_multicast_frames_received_ok_low[0x20];
1899
1900         u8         a_broadcast_frames_received_ok_high[0x20];
1901
1902         u8         a_broadcast_frames_received_ok_low[0x20];
1903
1904         u8         a_in_range_length_errors_high[0x20];
1905
1906         u8         a_in_range_length_errors_low[0x20];
1907
1908         u8         a_out_of_range_length_field_high[0x20];
1909
1910         u8         a_out_of_range_length_field_low[0x20];
1911
1912         u8         a_frame_too_long_errors_high[0x20];
1913
1914         u8         a_frame_too_long_errors_low[0x20];
1915
1916         u8         a_symbol_error_during_carrier_high[0x20];
1917
1918         u8         a_symbol_error_during_carrier_low[0x20];
1919
1920         u8         a_mac_control_frames_transmitted_high[0x20];
1921
1922         u8         a_mac_control_frames_transmitted_low[0x20];
1923
1924         u8         a_mac_control_frames_received_high[0x20];
1925
1926         u8         a_mac_control_frames_received_low[0x20];
1927
1928         u8         a_unsupported_opcodes_received_high[0x20];
1929
1930         u8         a_unsupported_opcodes_received_low[0x20];
1931
1932         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1933
1934         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1935
1936         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1937
1938         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1939
1940         u8         reserved_at_4c0[0x300];
1941 };
1942
1943 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1944         u8         life_time_counter_high[0x20];
1945
1946         u8         life_time_counter_low[0x20];
1947
1948         u8         rx_errors[0x20];
1949
1950         u8         tx_errors[0x20];
1951
1952         u8         l0_to_recovery_eieos[0x20];
1953
1954         u8         l0_to_recovery_ts[0x20];
1955
1956         u8         l0_to_recovery_framing[0x20];
1957
1958         u8         l0_to_recovery_retrain[0x20];
1959
1960         u8         crc_error_dllp[0x20];
1961
1962         u8         crc_error_tlp[0x20];
1963
1964         u8         tx_overflow_buffer_pkt_high[0x20];
1965
1966         u8         tx_overflow_buffer_pkt_low[0x20];
1967
1968         u8         outbound_stalled_reads[0x20];
1969
1970         u8         outbound_stalled_writes[0x20];
1971
1972         u8         outbound_stalled_reads_events[0x20];
1973
1974         u8         outbound_stalled_writes_events[0x20];
1975
1976         u8         reserved_at_200[0x5c0];
1977 };
1978
1979 struct mlx5_ifc_cmd_inter_comp_event_bits {
1980         u8         command_completion_vector[0x20];
1981
1982         u8         reserved_at_20[0xc0];
1983 };
1984
1985 struct mlx5_ifc_stall_vl_event_bits {
1986         u8         reserved_at_0[0x18];
1987         u8         port_num[0x1];
1988         u8         reserved_at_19[0x3];
1989         u8         vl[0x4];
1990
1991         u8         reserved_at_20[0xa0];
1992 };
1993
1994 struct mlx5_ifc_db_bf_congestion_event_bits {
1995         u8         event_subtype[0x8];
1996         u8         reserved_at_8[0x8];
1997         u8         congestion_level[0x8];
1998         u8         reserved_at_18[0x8];
1999
2000         u8         reserved_at_20[0xa0];
2001 };
2002
2003 struct mlx5_ifc_gpio_event_bits {
2004         u8         reserved_at_0[0x60];
2005
2006         u8         gpio_event_hi[0x20];
2007
2008         u8         gpio_event_lo[0x20];
2009
2010         u8         reserved_at_a0[0x40];
2011 };
2012
2013 struct mlx5_ifc_port_state_change_event_bits {
2014         u8         reserved_at_0[0x40];
2015
2016         u8         port_num[0x4];
2017         u8         reserved_at_44[0x1c];
2018
2019         u8         reserved_at_60[0x80];
2020 };
2021
2022 struct mlx5_ifc_dropped_packet_logged_bits {
2023         u8         reserved_at_0[0xe0];
2024 };
2025
2026 enum {
2027         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2028         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2029 };
2030
2031 struct mlx5_ifc_cq_error_bits {
2032         u8         reserved_at_0[0x8];
2033         u8         cqn[0x18];
2034
2035         u8         reserved_at_20[0x20];
2036
2037         u8         reserved_at_40[0x18];
2038         u8         syndrome[0x8];
2039
2040         u8         reserved_at_60[0x80];
2041 };
2042
2043 struct mlx5_ifc_rdma_page_fault_event_bits {
2044         u8         bytes_committed[0x20];
2045
2046         u8         r_key[0x20];
2047
2048         u8         reserved_at_40[0x10];
2049         u8         packet_len[0x10];
2050
2051         u8         rdma_op_len[0x20];
2052
2053         u8         rdma_va[0x40];
2054
2055         u8         reserved_at_c0[0x5];
2056         u8         rdma[0x1];
2057         u8         write[0x1];
2058         u8         requestor[0x1];
2059         u8         qp_number[0x18];
2060 };
2061
2062 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2063         u8         bytes_committed[0x20];
2064
2065         u8         reserved_at_20[0x10];
2066         u8         wqe_index[0x10];
2067
2068         u8         reserved_at_40[0x10];
2069         u8         len[0x10];
2070
2071         u8         reserved_at_60[0x60];
2072
2073         u8         reserved_at_c0[0x5];
2074         u8         rdma[0x1];
2075         u8         write_read[0x1];
2076         u8         requestor[0x1];
2077         u8         qpn[0x18];
2078 };
2079
2080 struct mlx5_ifc_qp_events_bits {
2081         u8         reserved_at_0[0xa0];
2082
2083         u8         type[0x8];
2084         u8         reserved_at_a8[0x18];
2085
2086         u8         reserved_at_c0[0x8];
2087         u8         qpn_rqn_sqn[0x18];
2088 };
2089
2090 struct mlx5_ifc_dct_events_bits {
2091         u8         reserved_at_0[0xc0];
2092
2093         u8         reserved_at_c0[0x8];
2094         u8         dct_number[0x18];
2095 };
2096
2097 struct mlx5_ifc_comp_event_bits {
2098         u8         reserved_at_0[0xc0];
2099
2100         u8         reserved_at_c0[0x8];
2101         u8         cq_number[0x18];
2102 };
2103
2104 enum {
2105         MLX5_QPC_STATE_RST        = 0x0,
2106         MLX5_QPC_STATE_INIT       = 0x1,
2107         MLX5_QPC_STATE_RTR        = 0x2,
2108         MLX5_QPC_STATE_RTS        = 0x3,
2109         MLX5_QPC_STATE_SQER       = 0x4,
2110         MLX5_QPC_STATE_ERR        = 0x6,
2111         MLX5_QPC_STATE_SQD        = 0x7,
2112         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2113 };
2114
2115 enum {
2116         MLX5_QPC_ST_RC            = 0x0,
2117         MLX5_QPC_ST_UC            = 0x1,
2118         MLX5_QPC_ST_UD            = 0x2,
2119         MLX5_QPC_ST_XRC           = 0x3,
2120         MLX5_QPC_ST_DCI           = 0x5,
2121         MLX5_QPC_ST_QP0           = 0x7,
2122         MLX5_QPC_ST_QP1           = 0x8,
2123         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2124         MLX5_QPC_ST_REG_UMR       = 0xc,
2125 };
2126
2127 enum {
2128         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2129         MLX5_QPC_PM_STATE_REARM     = 0x1,
2130         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2131         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2132 };
2133
2134 enum {
2135         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2136 };
2137
2138 enum {
2139         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2140         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2141 };
2142
2143 enum {
2144         MLX5_QPC_MTU_256_BYTES        = 0x1,
2145         MLX5_QPC_MTU_512_BYTES        = 0x2,
2146         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2147         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2148         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2149         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2150 };
2151
2152 enum {
2153         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2154         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2155         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2156         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2157         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2158         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2159         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2160         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2161 };
2162
2163 enum {
2164         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2165         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2166         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2167 };
2168
2169 enum {
2170         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2171         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2172         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2173 };
2174
2175 struct mlx5_ifc_qpc_bits {
2176         u8         state[0x4];
2177         u8         lag_tx_port_affinity[0x4];
2178         u8         st[0x8];
2179         u8         reserved_at_10[0x3];
2180         u8         pm_state[0x2];
2181         u8         reserved_at_15[0x3];
2182         u8         offload_type[0x4];
2183         u8         end_padding_mode[0x2];
2184         u8         reserved_at_1e[0x2];
2185
2186         u8         wq_signature[0x1];
2187         u8         block_lb_mc[0x1];
2188         u8         atomic_like_write_en[0x1];
2189         u8         latency_sensitive[0x1];
2190         u8         reserved_at_24[0x1];
2191         u8         drain_sigerr[0x1];
2192         u8         reserved_at_26[0x2];
2193         u8         pd[0x18];
2194
2195         u8         mtu[0x3];
2196         u8         log_msg_max[0x5];
2197         u8         reserved_at_48[0x1];
2198         u8         log_rq_size[0x4];
2199         u8         log_rq_stride[0x3];
2200         u8         no_sq[0x1];
2201         u8         log_sq_size[0x4];
2202         u8         reserved_at_55[0x6];
2203         u8         rlky[0x1];
2204         u8         ulp_stateless_offload_mode[0x4];
2205
2206         u8         counter_set_id[0x8];
2207         u8         uar_page[0x18];
2208
2209         u8         reserved_at_80[0x8];
2210         u8         user_index[0x18];
2211
2212         u8         reserved_at_a0[0x3];
2213         u8         log_page_size[0x5];
2214         u8         remote_qpn[0x18];
2215
2216         struct mlx5_ifc_ads_bits primary_address_path;
2217
2218         struct mlx5_ifc_ads_bits secondary_address_path;
2219
2220         u8         log_ack_req_freq[0x4];
2221         u8         reserved_at_384[0x4];
2222         u8         log_sra_max[0x3];
2223         u8         reserved_at_38b[0x2];
2224         u8         retry_count[0x3];
2225         u8         rnr_retry[0x3];
2226         u8         reserved_at_393[0x1];
2227         u8         fre[0x1];
2228         u8         cur_rnr_retry[0x3];
2229         u8         cur_retry_count[0x3];
2230         u8         reserved_at_39b[0x5];
2231
2232         u8         reserved_at_3a0[0x20];
2233
2234         u8         reserved_at_3c0[0x8];
2235         u8         next_send_psn[0x18];
2236
2237         u8         reserved_at_3e0[0x8];
2238         u8         cqn_snd[0x18];
2239
2240         u8         reserved_at_400[0x8];
2241         u8         deth_sqpn[0x18];
2242
2243         u8         reserved_at_420[0x20];
2244
2245         u8         reserved_at_440[0x8];
2246         u8         last_acked_psn[0x18];
2247
2248         u8         reserved_at_460[0x8];
2249         u8         ssn[0x18];
2250
2251         u8         reserved_at_480[0x8];
2252         u8         log_rra_max[0x3];
2253         u8         reserved_at_48b[0x1];
2254         u8         atomic_mode[0x4];
2255         u8         rre[0x1];
2256         u8         rwe[0x1];
2257         u8         rae[0x1];
2258         u8         reserved_at_493[0x1];
2259         u8         page_offset[0x6];
2260         u8         reserved_at_49a[0x3];
2261         u8         cd_slave_receive[0x1];
2262         u8         cd_slave_send[0x1];
2263         u8         cd_master[0x1];
2264
2265         u8         reserved_at_4a0[0x3];
2266         u8         min_rnr_nak[0x5];
2267         u8         next_rcv_psn[0x18];
2268
2269         u8         reserved_at_4c0[0x8];
2270         u8         xrcd[0x18];
2271
2272         u8         reserved_at_4e0[0x8];
2273         u8         cqn_rcv[0x18];
2274
2275         u8         dbr_addr[0x40];
2276
2277         u8         q_key[0x20];
2278
2279         u8         reserved_at_560[0x5];
2280         u8         rq_type[0x3];
2281         u8         srqn_rmpn_xrqn[0x18];
2282
2283         u8         reserved_at_580[0x8];
2284         u8         rmsn[0x18];
2285
2286         u8         hw_sq_wqebb_counter[0x10];
2287         u8         sw_sq_wqebb_counter[0x10];
2288
2289         u8         hw_rq_counter[0x20];
2290
2291         u8         sw_rq_counter[0x20];
2292
2293         u8         reserved_at_600[0x20];
2294
2295         u8         reserved_at_620[0xf];
2296         u8         cgs[0x1];
2297         u8         cs_req[0x8];
2298         u8         cs_res[0x8];
2299
2300         u8         dc_access_key[0x40];
2301
2302         u8         reserved_at_680[0xc0];
2303 };
2304
2305 struct mlx5_ifc_roce_addr_layout_bits {
2306         u8         source_l3_address[16][0x8];
2307
2308         u8         reserved_at_80[0x3];
2309         u8         vlan_valid[0x1];
2310         u8         vlan_id[0xc];
2311         u8         source_mac_47_32[0x10];
2312
2313         u8         source_mac_31_0[0x20];
2314
2315         u8         reserved_at_c0[0x14];
2316         u8         roce_l3_type[0x4];
2317         u8         roce_version[0x8];
2318
2319         u8         reserved_at_e0[0x20];
2320 };
2321
2322 union mlx5_ifc_hca_cap_union_bits {
2323         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2324         struct mlx5_ifc_odp_cap_bits odp_cap;
2325         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2326         struct mlx5_ifc_roce_cap_bits roce_cap;
2327         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2328         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2329         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2330         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2331         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2332         struct mlx5_ifc_qos_cap_bits qos_cap;
2333         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2334         u8         reserved_at_0[0x8000];
2335 };
2336
2337 enum {
2338         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2339         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2340         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2341         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2342         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2343         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2344         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2345         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2346         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2347 };
2348
2349 struct mlx5_ifc_vlan_bits {
2350         u8         ethtype[0x10];
2351         u8         prio[0x3];
2352         u8         cfi[0x1];
2353         u8         vid[0xc];
2354 };
2355
2356 struct mlx5_ifc_flow_context_bits {
2357         struct mlx5_ifc_vlan_bits push_vlan;
2358
2359         u8         group_id[0x20];
2360
2361         u8         reserved_at_40[0x8];
2362         u8         flow_tag[0x18];
2363
2364         u8         reserved_at_60[0x10];
2365         u8         action[0x10];
2366
2367         u8         reserved_at_80[0x8];
2368         u8         destination_list_size[0x18];
2369
2370         u8         reserved_at_a0[0x8];
2371         u8         flow_counter_list_size[0x18];
2372
2373         u8         encap_id[0x20];
2374
2375         u8         modify_header_id[0x20];
2376
2377         u8         reserved_at_100[0x100];
2378
2379         struct mlx5_ifc_fte_match_param_bits match_value;
2380
2381         u8         reserved_at_1200[0x600];
2382
2383         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2384 };
2385
2386 enum {
2387         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2388         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2389 };
2390
2391 struct mlx5_ifc_xrc_srqc_bits {
2392         u8         state[0x4];
2393         u8         log_xrc_srq_size[0x4];
2394         u8         reserved_at_8[0x18];
2395
2396         u8         wq_signature[0x1];
2397         u8         cont_srq[0x1];
2398         u8         reserved_at_22[0x1];
2399         u8         rlky[0x1];
2400         u8         basic_cyclic_rcv_wqe[0x1];
2401         u8         log_rq_stride[0x3];
2402         u8         xrcd[0x18];
2403
2404         u8         page_offset[0x6];
2405         u8         reserved_at_46[0x2];
2406         u8         cqn[0x18];
2407
2408         u8         reserved_at_60[0x20];
2409
2410         u8         user_index_equal_xrc_srqn[0x1];
2411         u8         reserved_at_81[0x1];
2412         u8         log_page_size[0x6];
2413         u8         user_index[0x18];
2414
2415         u8         reserved_at_a0[0x20];
2416
2417         u8         reserved_at_c0[0x8];
2418         u8         pd[0x18];
2419
2420         u8         lwm[0x10];
2421         u8         wqe_cnt[0x10];
2422
2423         u8         reserved_at_100[0x40];
2424
2425         u8         db_record_addr_h[0x20];
2426
2427         u8         db_record_addr_l[0x1e];
2428         u8         reserved_at_17e[0x2];
2429
2430         u8         reserved_at_180[0x80];
2431 };
2432
2433 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2434         u8         counter_error_queues[0x20];
2435
2436         u8         total_error_queues[0x20];
2437
2438         u8         send_queue_priority_update_flow[0x20];
2439
2440         u8         reserved_at_60[0x20];
2441
2442         u8         nic_receive_steering_discard[0x40];
2443
2444         u8         receive_discard_vport_down[0x40];
2445
2446         u8         transmit_discard_vport_down[0x40];
2447
2448         u8         reserved_at_140[0xec0];
2449 };
2450
2451 struct mlx5_ifc_traffic_counter_bits {
2452         u8         packets[0x40];
2453
2454         u8         octets[0x40];
2455 };
2456
2457 struct mlx5_ifc_tisc_bits {
2458         u8         strict_lag_tx_port_affinity[0x1];
2459         u8         reserved_at_1[0x3];
2460         u8         lag_tx_port_affinity[0x04];
2461
2462         u8         reserved_at_8[0x4];
2463         u8         prio[0x4];
2464         u8         reserved_at_10[0x10];
2465
2466         u8         reserved_at_20[0x100];
2467
2468         u8         reserved_at_120[0x8];
2469         u8         transport_domain[0x18];
2470
2471         u8         reserved_at_140[0x8];
2472         u8         underlay_qpn[0x18];
2473         u8         reserved_at_160[0x3a0];
2474 };
2475
2476 enum {
2477         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2478         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2479 };
2480
2481 enum {
2482         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2483         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2484 };
2485
2486 enum {
2487         MLX5_RX_HASH_FN_NONE           = 0x0,
2488         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2489         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2490 };
2491
2492 enum {
2493         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2494         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2495 };
2496
2497 struct mlx5_ifc_tirc_bits {
2498         u8         reserved_at_0[0x20];
2499
2500         u8         disp_type[0x4];
2501         u8         reserved_at_24[0x1c];
2502
2503         u8         reserved_at_40[0x40];
2504
2505         u8         reserved_at_80[0x4];
2506         u8         lro_timeout_period_usecs[0x10];
2507         u8         lro_enable_mask[0x4];
2508         u8         lro_max_ip_payload_size[0x8];
2509
2510         u8         reserved_at_a0[0x40];
2511
2512         u8         reserved_at_e0[0x8];
2513         u8         inline_rqn[0x18];
2514
2515         u8         rx_hash_symmetric[0x1];
2516         u8         reserved_at_101[0x1];
2517         u8         tunneled_offload_en[0x1];
2518         u8         reserved_at_103[0x5];
2519         u8         indirect_table[0x18];
2520
2521         u8         rx_hash_fn[0x4];
2522         u8         reserved_at_124[0x2];
2523         u8         self_lb_block[0x2];
2524         u8         transport_domain[0x18];
2525
2526         u8         rx_hash_toeplitz_key[10][0x20];
2527
2528         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2529
2530         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2531
2532         u8         reserved_at_2c0[0x4c0];
2533 };
2534
2535 enum {
2536         MLX5_SRQC_STATE_GOOD   = 0x0,
2537         MLX5_SRQC_STATE_ERROR  = 0x1,
2538 };
2539
2540 struct mlx5_ifc_srqc_bits {
2541         u8         state[0x4];
2542         u8         log_srq_size[0x4];
2543         u8         reserved_at_8[0x18];
2544
2545         u8         wq_signature[0x1];
2546         u8         cont_srq[0x1];
2547         u8         reserved_at_22[0x1];
2548         u8         rlky[0x1];
2549         u8         reserved_at_24[0x1];
2550         u8         log_rq_stride[0x3];
2551         u8         xrcd[0x18];
2552
2553         u8         page_offset[0x6];
2554         u8         reserved_at_46[0x2];
2555         u8         cqn[0x18];
2556
2557         u8         reserved_at_60[0x20];
2558
2559         u8         reserved_at_80[0x2];
2560         u8         log_page_size[0x6];
2561         u8         reserved_at_88[0x18];
2562
2563         u8         reserved_at_a0[0x20];
2564
2565         u8         reserved_at_c0[0x8];
2566         u8         pd[0x18];
2567
2568         u8         lwm[0x10];
2569         u8         wqe_cnt[0x10];
2570
2571         u8         reserved_at_100[0x40];
2572
2573         u8         dbr_addr[0x40];
2574
2575         u8         reserved_at_180[0x80];
2576 };
2577
2578 enum {
2579         MLX5_SQC_STATE_RST  = 0x0,
2580         MLX5_SQC_STATE_RDY  = 0x1,
2581         MLX5_SQC_STATE_ERR  = 0x3,
2582 };
2583
2584 struct mlx5_ifc_sqc_bits {
2585         u8         rlky[0x1];
2586         u8         cd_master[0x1];
2587         u8         fre[0x1];
2588         u8         flush_in_error_en[0x1];
2589         u8         allow_multi_pkt_send_wqe[0x1];
2590         u8         min_wqe_inline_mode[0x3];
2591         u8         state[0x4];
2592         u8         reg_umr[0x1];
2593         u8         allow_swp[0x1];
2594         u8         hairpin[0x1];
2595         u8         reserved_at_f[0x11];
2596
2597         u8         reserved_at_20[0x8];
2598         u8         user_index[0x18];
2599
2600         u8         reserved_at_40[0x8];
2601         u8         cqn[0x18];
2602
2603         u8         reserved_at_60[0x8];
2604         u8         hairpin_peer_rq[0x18];
2605
2606         u8         reserved_at_80[0x10];
2607         u8         hairpin_peer_vhca[0x10];
2608
2609         u8         reserved_at_a0[0x50];
2610
2611         u8         packet_pacing_rate_limit_index[0x10];
2612         u8         tis_lst_sz[0x10];
2613         u8         reserved_at_110[0x10];
2614
2615         u8         reserved_at_120[0x40];
2616
2617         u8         reserved_at_160[0x8];
2618         u8         tis_num_0[0x18];
2619
2620         struct mlx5_ifc_wq_bits wq;
2621 };
2622
2623 enum {
2624         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2625         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2626         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2627         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2628 };
2629
2630 struct mlx5_ifc_scheduling_context_bits {
2631         u8         element_type[0x8];
2632         u8         reserved_at_8[0x18];
2633
2634         u8         element_attributes[0x20];
2635
2636         u8         parent_element_id[0x20];
2637
2638         u8         reserved_at_60[0x40];
2639
2640         u8         bw_share[0x20];
2641
2642         u8         max_average_bw[0x20];
2643
2644         u8         reserved_at_e0[0x120];
2645 };
2646
2647 struct mlx5_ifc_rqtc_bits {
2648         u8         reserved_at_0[0xa0];
2649
2650         u8         reserved_at_a0[0x10];
2651         u8         rqt_max_size[0x10];
2652
2653         u8         reserved_at_c0[0x10];
2654         u8         rqt_actual_size[0x10];
2655
2656         u8         reserved_at_e0[0x6a0];
2657
2658         struct mlx5_ifc_rq_num_bits rq_num[0];
2659 };
2660
2661 enum {
2662         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2663         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2664 };
2665
2666 enum {
2667         MLX5_RQC_STATE_RST  = 0x0,
2668         MLX5_RQC_STATE_RDY  = 0x1,
2669         MLX5_RQC_STATE_ERR  = 0x3,
2670 };
2671
2672 struct mlx5_ifc_rqc_bits {
2673         u8         rlky[0x1];
2674         u8         delay_drop_en[0x1];
2675         u8         scatter_fcs[0x1];
2676         u8         vsd[0x1];
2677         u8         mem_rq_type[0x4];
2678         u8         state[0x4];
2679         u8         reserved_at_c[0x1];
2680         u8         flush_in_error_en[0x1];
2681         u8         hairpin[0x1];
2682         u8         reserved_at_f[0x11];
2683
2684         u8         reserved_at_20[0x8];
2685         u8         user_index[0x18];
2686
2687         u8         reserved_at_40[0x8];
2688         u8         cqn[0x18];
2689
2690         u8         counter_set_id[0x8];
2691         u8         reserved_at_68[0x18];
2692
2693         u8         reserved_at_80[0x8];
2694         u8         rmpn[0x18];
2695
2696         u8         reserved_at_a0[0x8];
2697         u8         hairpin_peer_sq[0x18];
2698
2699         u8         reserved_at_c0[0x10];
2700         u8         hairpin_peer_vhca[0x10];
2701
2702         u8         reserved_at_e0[0xa0];
2703
2704         struct mlx5_ifc_wq_bits wq;
2705 };
2706
2707 enum {
2708         MLX5_RMPC_STATE_RDY  = 0x1,
2709         MLX5_RMPC_STATE_ERR  = 0x3,
2710 };
2711
2712 struct mlx5_ifc_rmpc_bits {
2713         u8         reserved_at_0[0x8];
2714         u8         state[0x4];
2715         u8         reserved_at_c[0x14];
2716
2717         u8         basic_cyclic_rcv_wqe[0x1];
2718         u8         reserved_at_21[0x1f];
2719
2720         u8         reserved_at_40[0x140];
2721
2722         struct mlx5_ifc_wq_bits wq;
2723 };
2724
2725 struct mlx5_ifc_nic_vport_context_bits {
2726         u8         reserved_at_0[0x5];
2727         u8         min_wqe_inline_mode[0x3];
2728         u8         reserved_at_8[0x15];
2729         u8         disable_mc_local_lb[0x1];
2730         u8         disable_uc_local_lb[0x1];
2731         u8         roce_en[0x1];
2732
2733         u8         arm_change_event[0x1];
2734         u8         reserved_at_21[0x1a];
2735         u8         event_on_mtu[0x1];
2736         u8         event_on_promisc_change[0x1];
2737         u8         event_on_vlan_change[0x1];
2738         u8         event_on_mc_address_change[0x1];
2739         u8         event_on_uc_address_change[0x1];
2740
2741         u8         reserved_at_40[0xc];
2742
2743         u8         affiliation_criteria[0x4];
2744         u8         affiliated_vhca_id[0x10];
2745
2746         u8         reserved_at_60[0xd0];
2747
2748         u8         mtu[0x10];
2749
2750         u8         system_image_guid[0x40];
2751         u8         port_guid[0x40];
2752         u8         node_guid[0x40];
2753
2754         u8         reserved_at_200[0x140];
2755         u8         qkey_violation_counter[0x10];
2756         u8         reserved_at_350[0x430];
2757
2758         u8         promisc_uc[0x1];
2759         u8         promisc_mc[0x1];
2760         u8         promisc_all[0x1];
2761         u8         reserved_at_783[0x2];
2762         u8         allowed_list_type[0x3];
2763         u8         reserved_at_788[0xc];
2764         u8         allowed_list_size[0xc];
2765
2766         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2767
2768         u8         reserved_at_7e0[0x20];
2769
2770         u8         current_uc_mac_address[0][0x40];
2771 };
2772
2773 enum {
2774         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2775         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2776         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2777         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2778         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2779 };
2780
2781 struct mlx5_ifc_mkc_bits {
2782         u8         reserved_at_0[0x1];
2783         u8         free[0x1];
2784         u8         reserved_at_2[0x1];
2785         u8         access_mode_4_2[0x3];
2786         u8         reserved_at_6[0x7];
2787         u8         relaxed_ordering_write[0x1];
2788         u8         reserved_at_e[0x1];
2789         u8         small_fence_on_rdma_read_response[0x1];
2790         u8         umr_en[0x1];
2791         u8         a[0x1];
2792         u8         rw[0x1];
2793         u8         rr[0x1];
2794         u8         lw[0x1];
2795         u8         lr[0x1];
2796         u8         access_mode_1_0[0x2];
2797         u8         reserved_at_18[0x8];
2798
2799         u8         qpn[0x18];
2800         u8         mkey_7_0[0x8];
2801
2802         u8         reserved_at_40[0x20];
2803
2804         u8         length64[0x1];
2805         u8         bsf_en[0x1];
2806         u8         sync_umr[0x1];
2807         u8         reserved_at_63[0x2];
2808         u8         expected_sigerr_count[0x1];
2809         u8         reserved_at_66[0x1];
2810         u8         en_rinval[0x1];
2811         u8         pd[0x18];
2812
2813         u8         start_addr[0x40];
2814
2815         u8         len[0x40];
2816
2817         u8         bsf_octword_size[0x20];
2818
2819         u8         reserved_at_120[0x80];
2820
2821         u8         translations_octword_size[0x20];
2822
2823         u8         reserved_at_1c0[0x1b];
2824         u8         log_page_size[0x5];
2825
2826         u8         reserved_at_1e0[0x20];
2827 };
2828
2829 struct mlx5_ifc_pkey_bits {
2830         u8         reserved_at_0[0x10];
2831         u8         pkey[0x10];
2832 };
2833
2834 struct mlx5_ifc_array128_auto_bits {
2835         u8         array128_auto[16][0x8];
2836 };
2837
2838 struct mlx5_ifc_hca_vport_context_bits {
2839         u8         field_select[0x20];
2840
2841         u8         reserved_at_20[0xe0];
2842
2843         u8         sm_virt_aware[0x1];
2844         u8         has_smi[0x1];
2845         u8         has_raw[0x1];
2846         u8         grh_required[0x1];
2847         u8         reserved_at_104[0xc];
2848         u8         port_physical_state[0x4];
2849         u8         vport_state_policy[0x4];
2850         u8         port_state[0x4];
2851         u8         vport_state[0x4];
2852
2853         u8         reserved_at_120[0x20];
2854
2855         u8         system_image_guid[0x40];
2856
2857         u8         port_guid[0x40];
2858
2859         u8         node_guid[0x40];
2860
2861         u8         cap_mask1[0x20];
2862
2863         u8         cap_mask1_field_select[0x20];
2864
2865         u8         cap_mask2[0x20];
2866
2867         u8         cap_mask2_field_select[0x20];
2868
2869         u8         reserved_at_280[0x80];
2870
2871         u8         lid[0x10];
2872         u8         reserved_at_310[0x4];
2873         u8         init_type_reply[0x4];
2874         u8         lmc[0x3];
2875         u8         subnet_timeout[0x5];
2876
2877         u8         sm_lid[0x10];
2878         u8         sm_sl[0x4];
2879         u8         reserved_at_334[0xc];
2880
2881         u8         qkey_violation_counter[0x10];
2882         u8         pkey_violation_counter[0x10];
2883
2884         u8         reserved_at_360[0xca0];
2885 };
2886
2887 struct mlx5_ifc_esw_vport_context_bits {
2888         u8         reserved_at_0[0x3];
2889         u8         vport_svlan_strip[0x1];
2890         u8         vport_cvlan_strip[0x1];
2891         u8         vport_svlan_insert[0x1];
2892         u8         vport_cvlan_insert[0x2];
2893         u8         reserved_at_8[0x18];
2894
2895         u8         reserved_at_20[0x20];
2896
2897         u8         svlan_cfi[0x1];
2898         u8         svlan_pcp[0x3];
2899         u8         svlan_id[0xc];
2900         u8         cvlan_cfi[0x1];
2901         u8         cvlan_pcp[0x3];
2902         u8         cvlan_id[0xc];
2903
2904         u8         reserved_at_60[0x7a0];
2905 };
2906
2907 enum {
2908         MLX5_EQC_STATUS_OK                = 0x0,
2909         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2910 };
2911
2912 enum {
2913         MLX5_EQC_ST_ARMED  = 0x9,
2914         MLX5_EQC_ST_FIRED  = 0xa,
2915 };
2916
2917 struct mlx5_ifc_eqc_bits {
2918         u8         status[0x4];
2919         u8         reserved_at_4[0x9];
2920         u8         ec[0x1];
2921         u8         oi[0x1];
2922         u8         reserved_at_f[0x5];
2923         u8         st[0x4];
2924         u8         reserved_at_18[0x8];
2925
2926         u8         reserved_at_20[0x20];
2927
2928         u8         reserved_at_40[0x14];
2929         u8         page_offset[0x6];
2930         u8         reserved_at_5a[0x6];
2931
2932         u8         reserved_at_60[0x3];
2933         u8         log_eq_size[0x5];
2934         u8         uar_page[0x18];
2935
2936         u8         reserved_at_80[0x20];
2937
2938         u8         reserved_at_a0[0x18];
2939         u8         intr[0x8];
2940
2941         u8         reserved_at_c0[0x3];
2942         u8         log_page_size[0x5];
2943         u8         reserved_at_c8[0x18];
2944
2945         u8         reserved_at_e0[0x60];
2946
2947         u8         reserved_at_140[0x8];
2948         u8         consumer_counter[0x18];
2949
2950         u8         reserved_at_160[0x8];
2951         u8         producer_counter[0x18];
2952
2953         u8         reserved_at_180[0x80];
2954 };
2955
2956 enum {
2957         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2958         MLX5_DCTC_STATE_DRAINING  = 0x1,
2959         MLX5_DCTC_STATE_DRAINED   = 0x2,
2960 };
2961
2962 enum {
2963         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2964         MLX5_DCTC_CS_RES_NA         = 0x1,
2965         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2966 };
2967
2968 enum {
2969         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2970         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2971         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2972         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2973         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2974 };
2975
2976 struct mlx5_ifc_dctc_bits {
2977         u8         reserved_at_0[0x4];
2978         u8         state[0x4];
2979         u8         reserved_at_8[0x18];
2980
2981         u8         reserved_at_20[0x8];
2982         u8         user_index[0x18];
2983
2984         u8         reserved_at_40[0x8];
2985         u8         cqn[0x18];
2986
2987         u8         counter_set_id[0x8];
2988         u8         atomic_mode[0x4];
2989         u8         rre[0x1];
2990         u8         rwe[0x1];
2991         u8         rae[0x1];
2992         u8         atomic_like_write_en[0x1];
2993         u8         latency_sensitive[0x1];
2994         u8         rlky[0x1];
2995         u8         free_ar[0x1];
2996         u8         reserved_at_73[0xd];
2997
2998         u8         reserved_at_80[0x8];
2999         u8         cs_res[0x8];
3000         u8         reserved_at_90[0x3];
3001         u8         min_rnr_nak[0x5];
3002         u8         reserved_at_98[0x8];
3003
3004         u8         reserved_at_a0[0x8];
3005         u8         srqn_xrqn[0x18];
3006
3007         u8         reserved_at_c0[0x8];
3008         u8         pd[0x18];
3009
3010         u8         tclass[0x8];
3011         u8         reserved_at_e8[0x4];
3012         u8         flow_label[0x14];
3013
3014         u8         dc_access_key[0x40];
3015
3016         u8         reserved_at_140[0x5];
3017         u8         mtu[0x3];
3018         u8         port[0x8];
3019         u8         pkey_index[0x10];
3020
3021         u8         reserved_at_160[0x8];
3022         u8         my_addr_index[0x8];
3023         u8         reserved_at_170[0x8];
3024         u8         hop_limit[0x8];
3025
3026         u8         dc_access_key_violation_count[0x20];
3027
3028         u8         reserved_at_1a0[0x14];
3029         u8         dei_cfi[0x1];
3030         u8         eth_prio[0x3];
3031         u8         ecn[0x2];
3032         u8         dscp[0x6];
3033
3034         u8         reserved_at_1c0[0x40];
3035 };
3036
3037 enum {
3038         MLX5_CQC_STATUS_OK             = 0x0,
3039         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3040         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3041 };
3042
3043 enum {
3044         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3045         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3046 };
3047
3048 enum {
3049         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3050         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3051         MLX5_CQC_ST_FIRED                                 = 0xa,
3052 };
3053
3054 enum {
3055         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3056         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3057         MLX5_CQ_PERIOD_NUM_MODES
3058 };
3059
3060 struct mlx5_ifc_cqc_bits {
3061         u8         status[0x4];
3062         u8         reserved_at_4[0x4];
3063         u8         cqe_sz[0x3];
3064         u8         cc[0x1];
3065         u8         reserved_at_c[0x1];
3066         u8         scqe_break_moderation_en[0x1];
3067         u8         oi[0x1];
3068         u8         cq_period_mode[0x2];
3069         u8         cqe_comp_en[0x1];
3070         u8         mini_cqe_res_format[0x2];
3071         u8         st[0x4];
3072         u8         reserved_at_18[0x8];
3073
3074         u8         reserved_at_20[0x20];
3075
3076         u8         reserved_at_40[0x14];
3077         u8         page_offset[0x6];
3078         u8         reserved_at_5a[0x6];
3079
3080         u8         reserved_at_60[0x3];
3081         u8         log_cq_size[0x5];
3082         u8         uar_page[0x18];
3083
3084         u8         reserved_at_80[0x4];
3085         u8         cq_period[0xc];
3086         u8         cq_max_count[0x10];
3087
3088         u8         reserved_at_a0[0x18];
3089         u8         c_eqn[0x8];
3090
3091         u8         reserved_at_c0[0x3];
3092         u8         log_page_size[0x5];
3093         u8         reserved_at_c8[0x18];
3094
3095         u8         reserved_at_e0[0x20];
3096
3097         u8         reserved_at_100[0x8];
3098         u8         last_notified_index[0x18];
3099
3100         u8         reserved_at_120[0x8];
3101         u8         last_solicit_index[0x18];
3102
3103         u8         reserved_at_140[0x8];
3104         u8         consumer_counter[0x18];
3105
3106         u8         reserved_at_160[0x8];
3107         u8         producer_counter[0x18];
3108
3109         u8         reserved_at_180[0x40];
3110
3111         u8         dbr_addr[0x40];
3112 };
3113
3114 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3115         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3116         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3117         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3118         u8         reserved_at_0[0x800];
3119 };
3120
3121 struct mlx5_ifc_query_adapter_param_block_bits {
3122         u8         reserved_at_0[0xc0];
3123
3124         u8         reserved_at_c0[0x8];
3125         u8         ieee_vendor_id[0x18];
3126
3127         u8         reserved_at_e0[0x10];
3128         u8         vsd_vendor_id[0x10];
3129
3130         u8         vsd[208][0x8];
3131
3132         u8         vsd_contd_psid[16][0x8];
3133 };
3134
3135 enum {
3136         MLX5_XRQC_STATE_GOOD   = 0x0,
3137         MLX5_XRQC_STATE_ERROR  = 0x1,
3138 };
3139
3140 enum {
3141         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3142         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3143 };
3144
3145 enum {
3146         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3147 };
3148
3149 struct mlx5_ifc_tag_matching_topology_context_bits {
3150         u8         log_matching_list_sz[0x4];
3151         u8         reserved_at_4[0xc];
3152         u8         append_next_index[0x10];
3153
3154         u8         sw_phase_cnt[0x10];
3155         u8         hw_phase_cnt[0x10];
3156
3157         u8         reserved_at_40[0x40];
3158 };
3159
3160 struct mlx5_ifc_xrqc_bits {
3161         u8         state[0x4];
3162         u8         rlkey[0x1];
3163         u8         reserved_at_5[0xf];
3164         u8         topology[0x4];
3165         u8         reserved_at_18[0x4];
3166         u8         offload[0x4];
3167
3168         u8         reserved_at_20[0x8];
3169         u8         user_index[0x18];
3170
3171         u8         reserved_at_40[0x8];
3172         u8         cqn[0x18];
3173
3174         u8         reserved_at_60[0xa0];
3175
3176         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3177
3178         u8         reserved_at_180[0x280];
3179
3180         struct mlx5_ifc_wq_bits wq;
3181 };
3182
3183 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3184         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3185         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3186         u8         reserved_at_0[0x20];
3187 };
3188
3189 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3190         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3191         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3192         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3193         u8         reserved_at_0[0x20];
3194 };
3195
3196 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3197         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3198         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3199         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3200         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3201         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3202         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3203         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3204         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3205         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3206         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3207         u8         reserved_at_0[0x7c0];
3208 };
3209
3210 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3211         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3212         u8         reserved_at_0[0x7c0];
3213 };
3214
3215 union mlx5_ifc_event_auto_bits {
3216         struct mlx5_ifc_comp_event_bits comp_event;
3217         struct mlx5_ifc_dct_events_bits dct_events;
3218         struct mlx5_ifc_qp_events_bits qp_events;
3219         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3220         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3221         struct mlx5_ifc_cq_error_bits cq_error;
3222         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3223         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3224         struct mlx5_ifc_gpio_event_bits gpio_event;
3225         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3226         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3227         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3228         u8         reserved_at_0[0xe0];
3229 };
3230
3231 struct mlx5_ifc_health_buffer_bits {
3232         u8         reserved_at_0[0x100];
3233
3234         u8         assert_existptr[0x20];
3235
3236         u8         assert_callra[0x20];
3237
3238         u8         reserved_at_140[0x40];
3239
3240         u8         fw_version[0x20];
3241
3242         u8         hw_id[0x20];
3243
3244         u8         reserved_at_1c0[0x20];
3245
3246         u8         irisc_index[0x8];
3247         u8         synd[0x8];
3248         u8         ext_synd[0x10];
3249 };
3250
3251 struct mlx5_ifc_register_loopback_control_bits {
3252         u8         no_lb[0x1];
3253         u8         reserved_at_1[0x7];
3254         u8         port[0x8];
3255         u8         reserved_at_10[0x10];
3256
3257         u8         reserved_at_20[0x60];
3258 };
3259
3260 struct mlx5_ifc_vport_tc_element_bits {
3261         u8         traffic_class[0x4];
3262         u8         reserved_at_4[0xc];
3263         u8         vport_number[0x10];
3264 };
3265
3266 struct mlx5_ifc_vport_element_bits {
3267         u8         reserved_at_0[0x10];
3268         u8         vport_number[0x10];
3269 };
3270
3271 enum {
3272         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3273         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3274         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3275 };
3276
3277 struct mlx5_ifc_tsar_element_bits {
3278         u8         reserved_at_0[0x8];
3279         u8         tsar_type[0x8];
3280         u8         reserved_at_10[0x10];
3281 };
3282
3283 enum {
3284         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3285         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3286 };
3287
3288 struct mlx5_ifc_teardown_hca_out_bits {
3289         u8         status[0x8];
3290         u8         reserved_at_8[0x18];
3291
3292         u8         syndrome[0x20];
3293
3294         u8         reserved_at_40[0x3f];
3295
3296         u8         force_state[0x1];
3297 };
3298
3299 enum {
3300         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3301         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3302 };
3303
3304 struct mlx5_ifc_teardown_hca_in_bits {
3305         u8         opcode[0x10];
3306         u8         reserved_at_10[0x10];
3307
3308         u8         reserved_at_20[0x10];
3309         u8         op_mod[0x10];
3310
3311         u8         reserved_at_40[0x10];
3312         u8         profile[0x10];
3313
3314         u8         reserved_at_60[0x20];
3315 };
3316
3317 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3318         u8         status[0x8];
3319         u8         reserved_at_8[0x18];
3320
3321         u8         syndrome[0x20];
3322
3323         u8         reserved_at_40[0x40];
3324 };
3325
3326 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3327         u8         opcode[0x10];
3328         u8         reserved_at_10[0x10];
3329
3330         u8         reserved_at_20[0x10];
3331         u8         op_mod[0x10];
3332
3333         u8         reserved_at_40[0x8];
3334         u8         qpn[0x18];
3335
3336         u8         reserved_at_60[0x20];
3337
3338         u8         opt_param_mask[0x20];
3339
3340         u8         reserved_at_a0[0x20];
3341
3342         struct mlx5_ifc_qpc_bits qpc;
3343
3344         u8         reserved_at_800[0x80];
3345 };
3346
3347 struct mlx5_ifc_sqd2rts_qp_out_bits {
3348         u8         status[0x8];
3349         u8         reserved_at_8[0x18];
3350
3351         u8         syndrome[0x20];
3352
3353         u8         reserved_at_40[0x40];
3354 };
3355
3356 struct mlx5_ifc_sqd2rts_qp_in_bits {
3357         u8         opcode[0x10];
3358         u8         reserved_at_10[0x10];
3359
3360         u8         reserved_at_20[0x10];
3361         u8         op_mod[0x10];
3362
3363         u8         reserved_at_40[0x8];
3364         u8         qpn[0x18];
3365
3366         u8         reserved_at_60[0x20];
3367
3368         u8         opt_param_mask[0x20];
3369
3370         u8         reserved_at_a0[0x20];
3371
3372         struct mlx5_ifc_qpc_bits qpc;
3373
3374         u8         reserved_at_800[0x80];
3375 };
3376
3377 struct mlx5_ifc_set_roce_address_out_bits {
3378         u8         status[0x8];
3379         u8         reserved_at_8[0x18];
3380
3381         u8         syndrome[0x20];
3382
3383         u8         reserved_at_40[0x40];
3384 };
3385
3386 struct mlx5_ifc_set_roce_address_in_bits {
3387         u8         opcode[0x10];
3388         u8         reserved_at_10[0x10];
3389
3390         u8         reserved_at_20[0x10];
3391         u8         op_mod[0x10];
3392
3393         u8         roce_address_index[0x10];
3394         u8         reserved_at_50[0xc];
3395         u8         vhca_port_num[0x4];
3396
3397         u8         reserved_at_60[0x20];
3398
3399         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3400 };
3401
3402 struct mlx5_ifc_set_mad_demux_out_bits {
3403         u8         status[0x8];
3404         u8         reserved_at_8[0x18];
3405
3406         u8         syndrome[0x20];
3407
3408         u8         reserved_at_40[0x40];
3409 };
3410
3411 enum {
3412         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3413         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3414 };
3415
3416 struct mlx5_ifc_set_mad_demux_in_bits {
3417         u8         opcode[0x10];
3418         u8         reserved_at_10[0x10];
3419
3420         u8         reserved_at_20[0x10];
3421         u8         op_mod[0x10];
3422
3423         u8         reserved_at_40[0x20];
3424
3425         u8         reserved_at_60[0x6];
3426         u8         demux_mode[0x2];
3427         u8         reserved_at_68[0x18];
3428 };
3429
3430 struct mlx5_ifc_set_l2_table_entry_out_bits {
3431         u8         status[0x8];
3432         u8         reserved_at_8[0x18];
3433
3434         u8         syndrome[0x20];
3435
3436         u8         reserved_at_40[0x40];
3437 };
3438
3439 struct mlx5_ifc_set_l2_table_entry_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_at_10[0x10];
3442
3443         u8         reserved_at_20[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         reserved_at_40[0x60];
3447
3448         u8         reserved_at_a0[0x8];
3449         u8         table_index[0x18];
3450
3451         u8         reserved_at_c0[0x20];
3452
3453         u8         reserved_at_e0[0x13];
3454         u8         vlan_valid[0x1];
3455         u8         vlan[0xc];
3456
3457         struct mlx5_ifc_mac_address_layout_bits mac_address;
3458
3459         u8         reserved_at_140[0xc0];
3460 };
3461
3462 struct mlx5_ifc_set_issi_out_bits {
3463         u8         status[0x8];
3464         u8         reserved_at_8[0x18];
3465
3466         u8         syndrome[0x20];
3467
3468         u8         reserved_at_40[0x40];
3469 };
3470
3471 struct mlx5_ifc_set_issi_in_bits {
3472         u8         opcode[0x10];
3473         u8         reserved_at_10[0x10];
3474
3475         u8         reserved_at_20[0x10];
3476         u8         op_mod[0x10];
3477
3478         u8         reserved_at_40[0x10];
3479         u8         current_issi[0x10];
3480
3481         u8         reserved_at_60[0x20];
3482 };
3483
3484 struct mlx5_ifc_set_hca_cap_out_bits {
3485         u8         status[0x8];
3486         u8         reserved_at_8[0x18];
3487
3488         u8         syndrome[0x20];
3489
3490         u8         reserved_at_40[0x40];
3491 };
3492
3493 struct mlx5_ifc_set_hca_cap_in_bits {
3494         u8         opcode[0x10];
3495         u8         reserved_at_10[0x10];
3496
3497         u8         reserved_at_20[0x10];
3498         u8         op_mod[0x10];
3499
3500         u8         reserved_at_40[0x40];
3501
3502         union mlx5_ifc_hca_cap_union_bits capability;
3503 };
3504
3505 enum {
3506         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3507         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3508         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3509         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3510 };
3511
3512 struct mlx5_ifc_set_fte_out_bits {
3513         u8         status[0x8];
3514         u8         reserved_at_8[0x18];
3515
3516         u8         syndrome[0x20];
3517
3518         u8         reserved_at_40[0x40];
3519 };
3520
3521 struct mlx5_ifc_set_fte_in_bits {
3522         u8         opcode[0x10];
3523         u8         reserved_at_10[0x10];
3524
3525         u8         reserved_at_20[0x10];
3526         u8         op_mod[0x10];
3527
3528         u8         other_vport[0x1];
3529         u8         reserved_at_41[0xf];
3530         u8         vport_number[0x10];
3531
3532         u8         reserved_at_60[0x20];
3533
3534         u8         table_type[0x8];
3535         u8         reserved_at_88[0x18];
3536
3537         u8         reserved_at_a0[0x8];
3538         u8         table_id[0x18];
3539
3540         u8         reserved_at_c0[0x18];
3541         u8         modify_enable_mask[0x8];
3542
3543         u8         reserved_at_e0[0x20];
3544
3545         u8         flow_index[0x20];
3546
3547         u8         reserved_at_120[0xe0];
3548
3549         struct mlx5_ifc_flow_context_bits flow_context;
3550 };
3551
3552 struct mlx5_ifc_rts2rts_qp_out_bits {
3553         u8         status[0x8];
3554         u8         reserved_at_8[0x18];
3555
3556         u8         syndrome[0x20];
3557
3558         u8         reserved_at_40[0x40];
3559 };
3560
3561 struct mlx5_ifc_rts2rts_qp_in_bits {
3562         u8         opcode[0x10];
3563         u8         reserved_at_10[0x10];
3564
3565         u8         reserved_at_20[0x10];
3566         u8         op_mod[0x10];
3567
3568         u8         reserved_at_40[0x8];
3569         u8         qpn[0x18];
3570
3571         u8         reserved_at_60[0x20];
3572
3573         u8         opt_param_mask[0x20];
3574
3575         u8         reserved_at_a0[0x20];
3576
3577         struct mlx5_ifc_qpc_bits qpc;
3578
3579         u8         reserved_at_800[0x80];
3580 };
3581
3582 struct mlx5_ifc_rtr2rts_qp_out_bits {
3583         u8         status[0x8];
3584         u8         reserved_at_8[0x18];
3585
3586         u8         syndrome[0x20];
3587
3588         u8         reserved_at_40[0x40];
3589 };
3590
3591 struct mlx5_ifc_rtr2rts_qp_in_bits {
3592         u8         opcode[0x10];
3593         u8         reserved_at_10[0x10];
3594
3595         u8         reserved_at_20[0x10];
3596         u8         op_mod[0x10];
3597
3598         u8         reserved_at_40[0x8];
3599         u8         qpn[0x18];
3600
3601         u8         reserved_at_60[0x20];
3602
3603         u8         opt_param_mask[0x20];
3604
3605         u8         reserved_at_a0[0x20];
3606
3607         struct mlx5_ifc_qpc_bits qpc;
3608
3609         u8         reserved_at_800[0x80];
3610 };
3611
3612 struct mlx5_ifc_rst2init_qp_out_bits {
3613         u8         status[0x8];
3614         u8         reserved_at_8[0x18];
3615
3616         u8         syndrome[0x20];
3617
3618         u8         reserved_at_40[0x40];
3619 };
3620
3621 struct mlx5_ifc_rst2init_qp_in_bits {
3622         u8         opcode[0x10];
3623         u8         reserved_at_10[0x10];
3624
3625         u8         reserved_at_20[0x10];
3626         u8         op_mod[0x10];
3627
3628         u8         reserved_at_40[0x8];
3629         u8         qpn[0x18];
3630
3631         u8         reserved_at_60[0x20];
3632
3633         u8         opt_param_mask[0x20];
3634
3635         u8         reserved_at_a0[0x20];
3636
3637         struct mlx5_ifc_qpc_bits qpc;
3638
3639         u8         reserved_at_800[0x80];
3640 };
3641
3642 struct mlx5_ifc_query_xrq_out_bits {
3643         u8         status[0x8];
3644         u8         reserved_at_8[0x18];
3645
3646         u8         syndrome[0x20];
3647
3648         u8         reserved_at_40[0x40];
3649
3650         struct mlx5_ifc_xrqc_bits xrq_context;
3651 };
3652
3653 struct mlx5_ifc_query_xrq_in_bits {
3654         u8         opcode[0x10];
3655         u8         reserved_at_10[0x10];
3656
3657         u8         reserved_at_20[0x10];
3658         u8         op_mod[0x10];
3659
3660         u8         reserved_at_40[0x8];
3661         u8         xrqn[0x18];
3662
3663         u8         reserved_at_60[0x20];
3664 };
3665
3666 struct mlx5_ifc_query_xrc_srq_out_bits {
3667         u8         status[0x8];
3668         u8         reserved_at_8[0x18];
3669
3670         u8         syndrome[0x20];
3671
3672         u8         reserved_at_40[0x40];
3673
3674         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3675
3676         u8         reserved_at_280[0x600];
3677
3678         u8         pas[0][0x40];
3679 };
3680
3681 struct mlx5_ifc_query_xrc_srq_in_bits {
3682         u8         opcode[0x10];
3683         u8         reserved_at_10[0x10];
3684
3685         u8         reserved_at_20[0x10];
3686         u8         op_mod[0x10];
3687
3688         u8         reserved_at_40[0x8];
3689         u8         xrc_srqn[0x18];
3690
3691         u8         reserved_at_60[0x20];
3692 };
3693
3694 enum {
3695         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3696         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3697 };
3698
3699 struct mlx5_ifc_query_vport_state_out_bits {
3700         u8         status[0x8];
3701         u8         reserved_at_8[0x18];
3702
3703         u8         syndrome[0x20];
3704
3705         u8         reserved_at_40[0x20];
3706
3707         u8         reserved_at_60[0x18];
3708         u8         admin_state[0x4];
3709         u8         state[0x4];
3710 };
3711
3712 enum {
3713         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3714         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3715 };
3716
3717 struct mlx5_ifc_query_vport_state_in_bits {
3718         u8         opcode[0x10];
3719         u8         reserved_at_10[0x10];
3720
3721         u8         reserved_at_20[0x10];
3722         u8         op_mod[0x10];
3723
3724         u8         other_vport[0x1];
3725         u8         reserved_at_41[0xf];
3726         u8         vport_number[0x10];
3727
3728         u8         reserved_at_60[0x20];
3729 };
3730
3731 struct mlx5_ifc_query_vnic_env_out_bits {
3732         u8         status[0x8];
3733         u8         reserved_at_8[0x18];
3734
3735         u8         syndrome[0x20];
3736
3737         u8         reserved_at_40[0x40];
3738
3739         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3740 };
3741
3742 enum {
3743         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3744 };
3745
3746 struct mlx5_ifc_query_vnic_env_in_bits {
3747         u8         opcode[0x10];
3748         u8         reserved_at_10[0x10];
3749
3750         u8         reserved_at_20[0x10];
3751         u8         op_mod[0x10];
3752
3753         u8         other_vport[0x1];
3754         u8         reserved_at_41[0xf];
3755         u8         vport_number[0x10];
3756
3757         u8         reserved_at_60[0x20];
3758 };
3759
3760 struct mlx5_ifc_query_vport_counter_out_bits {
3761         u8         status[0x8];
3762         u8         reserved_at_8[0x18];
3763
3764         u8         syndrome[0x20];
3765
3766         u8         reserved_at_40[0x40];
3767
3768         struct mlx5_ifc_traffic_counter_bits received_errors;
3769
3770         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3771
3772         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3773
3774         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3775
3776         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3777
3778         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3779
3780         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3781
3782         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3783
3784         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3785
3786         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3787
3788         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3789
3790         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3791
3792         u8         reserved_at_680[0xa00];
3793 };
3794
3795 enum {
3796         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3797 };
3798
3799 struct mlx5_ifc_query_vport_counter_in_bits {
3800         u8         opcode[0x10];
3801         u8         reserved_at_10[0x10];
3802
3803         u8         reserved_at_20[0x10];
3804         u8         op_mod[0x10];
3805
3806         u8         other_vport[0x1];
3807         u8         reserved_at_41[0xb];
3808         u8         port_num[0x4];
3809         u8         vport_number[0x10];
3810
3811         u8         reserved_at_60[0x60];
3812
3813         u8         clear[0x1];
3814         u8         reserved_at_c1[0x1f];
3815
3816         u8         reserved_at_e0[0x20];
3817 };
3818
3819 struct mlx5_ifc_query_tis_out_bits {
3820         u8         status[0x8];
3821         u8         reserved_at_8[0x18];
3822
3823         u8         syndrome[0x20];
3824
3825         u8         reserved_at_40[0x40];
3826
3827         struct mlx5_ifc_tisc_bits tis_context;
3828 };
3829
3830 struct mlx5_ifc_query_tis_in_bits {
3831         u8         opcode[0x10];
3832         u8         reserved_at_10[0x10];
3833
3834         u8         reserved_at_20[0x10];
3835         u8         op_mod[0x10];
3836
3837         u8         reserved_at_40[0x8];
3838         u8         tisn[0x18];
3839
3840         u8         reserved_at_60[0x20];
3841 };
3842
3843 struct mlx5_ifc_query_tir_out_bits {
3844         u8         status[0x8];
3845         u8         reserved_at_8[0x18];
3846
3847         u8         syndrome[0x20];
3848
3849         u8         reserved_at_40[0xc0];
3850
3851         struct mlx5_ifc_tirc_bits tir_context;
3852 };
3853
3854 struct mlx5_ifc_query_tir_in_bits {
3855         u8         opcode[0x10];
3856         u8         reserved_at_10[0x10];
3857
3858         u8         reserved_at_20[0x10];
3859         u8         op_mod[0x10];
3860
3861         u8         reserved_at_40[0x8];
3862         u8         tirn[0x18];
3863
3864         u8         reserved_at_60[0x20];
3865 };
3866
3867 struct mlx5_ifc_query_srq_out_bits {
3868         u8         status[0x8];
3869         u8         reserved_at_8[0x18];
3870
3871         u8         syndrome[0x20];
3872
3873         u8         reserved_at_40[0x40];
3874
3875         struct mlx5_ifc_srqc_bits srq_context_entry;
3876
3877         u8         reserved_at_280[0x600];
3878
3879         u8         pas[0][0x40];
3880 };
3881
3882 struct mlx5_ifc_query_srq_in_bits {
3883         u8         opcode[0x10];
3884         u8         reserved_at_10[0x10];
3885
3886         u8         reserved_at_20[0x10];
3887         u8         op_mod[0x10];
3888
3889         u8         reserved_at_40[0x8];
3890         u8         srqn[0x18];
3891
3892         u8         reserved_at_60[0x20];
3893 };
3894
3895 struct mlx5_ifc_query_sq_out_bits {
3896         u8         status[0x8];
3897         u8         reserved_at_8[0x18];
3898
3899         u8         syndrome[0x20];
3900
3901         u8         reserved_at_40[0xc0];
3902
3903         struct mlx5_ifc_sqc_bits sq_context;
3904 };
3905
3906 struct mlx5_ifc_query_sq_in_bits {
3907         u8         opcode[0x10];
3908         u8         reserved_at_10[0x10];
3909
3910         u8         reserved_at_20[0x10];
3911         u8         op_mod[0x10];
3912
3913         u8         reserved_at_40[0x8];
3914         u8         sqn[0x18];
3915
3916         u8         reserved_at_60[0x20];
3917 };
3918
3919 struct mlx5_ifc_query_special_contexts_out_bits {
3920         u8         status[0x8];
3921         u8         reserved_at_8[0x18];
3922
3923         u8         syndrome[0x20];
3924
3925         u8         dump_fill_mkey[0x20];
3926
3927         u8         resd_lkey[0x20];
3928
3929         u8         null_mkey[0x20];
3930
3931         u8         reserved_at_a0[0x60];
3932 };
3933
3934 struct mlx5_ifc_query_special_contexts_in_bits {
3935         u8         opcode[0x10];
3936         u8         reserved_at_10[0x10];
3937
3938         u8         reserved_at_20[0x10];
3939         u8         op_mod[0x10];
3940
3941         u8         reserved_at_40[0x40];
3942 };
3943
3944 struct mlx5_ifc_query_scheduling_element_out_bits {
3945         u8         opcode[0x10];
3946         u8         reserved_at_10[0x10];
3947
3948         u8         reserved_at_20[0x10];
3949         u8         op_mod[0x10];
3950
3951         u8         reserved_at_40[0xc0];
3952
3953         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3954
3955         u8         reserved_at_300[0x100];
3956 };
3957
3958 enum {
3959         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3960 };
3961
3962 struct mlx5_ifc_query_scheduling_element_in_bits {
3963         u8         opcode[0x10];
3964         u8         reserved_at_10[0x10];
3965
3966         u8         reserved_at_20[0x10];
3967         u8         op_mod[0x10];
3968
3969         u8         scheduling_hierarchy[0x8];
3970         u8         reserved_at_48[0x18];
3971
3972         u8         scheduling_element_id[0x20];
3973
3974         u8         reserved_at_80[0x180];
3975 };
3976
3977 struct mlx5_ifc_query_rqt_out_bits {
3978         u8         status[0x8];
3979         u8         reserved_at_8[0x18];
3980
3981         u8         syndrome[0x20];
3982
3983         u8         reserved_at_40[0xc0];
3984
3985         struct mlx5_ifc_rqtc_bits rqt_context;
3986 };
3987
3988 struct mlx5_ifc_query_rqt_in_bits {
3989         u8         opcode[0x10];
3990         u8         reserved_at_10[0x10];
3991
3992         u8         reserved_at_20[0x10];
3993         u8         op_mod[0x10];
3994
3995         u8         reserved_at_40[0x8];
3996         u8         rqtn[0x18];
3997
3998         u8         reserved_at_60[0x20];
3999 };
4000
4001 struct mlx5_ifc_query_rq_out_bits {
4002         u8         status[0x8];
4003         u8         reserved_at_8[0x18];
4004
4005         u8         syndrome[0x20];
4006
4007         u8         reserved_at_40[0xc0];
4008
4009         struct mlx5_ifc_rqc_bits rq_context;
4010 };
4011
4012 struct mlx5_ifc_query_rq_in_bits {
4013         u8         opcode[0x10];
4014         u8         reserved_at_10[0x10];
4015
4016         u8         reserved_at_20[0x10];
4017         u8         op_mod[0x10];
4018
4019         u8         reserved_at_40[0x8];
4020         u8         rqn[0x18];
4021
4022         u8         reserved_at_60[0x20];
4023 };
4024
4025 struct mlx5_ifc_query_roce_address_out_bits {
4026         u8         status[0x8];
4027         u8         reserved_at_8[0x18];
4028
4029         u8         syndrome[0x20];
4030
4031         u8         reserved_at_40[0x40];
4032
4033         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4034 };
4035
4036 struct mlx5_ifc_query_roce_address_in_bits {
4037         u8         opcode[0x10];
4038         u8         reserved_at_10[0x10];
4039
4040         u8         reserved_at_20[0x10];
4041         u8         op_mod[0x10];
4042
4043         u8         roce_address_index[0x10];
4044         u8         reserved_at_50[0xc];
4045         u8         vhca_port_num[0x4];
4046
4047         u8         reserved_at_60[0x20];
4048 };
4049
4050 struct mlx5_ifc_query_rmp_out_bits {
4051         u8         status[0x8];
4052         u8         reserved_at_8[0x18];
4053
4054         u8         syndrome[0x20];
4055
4056         u8         reserved_at_40[0xc0];
4057
4058         struct mlx5_ifc_rmpc_bits rmp_context;
4059 };
4060
4061 struct mlx5_ifc_query_rmp_in_bits {
4062         u8         opcode[0x10];
4063         u8         reserved_at_10[0x10];
4064
4065         u8         reserved_at_20[0x10];
4066         u8         op_mod[0x10];
4067
4068         u8         reserved_at_40[0x8];
4069         u8         rmpn[0x18];
4070
4071         u8         reserved_at_60[0x20];
4072 };
4073
4074 struct mlx5_ifc_query_qp_out_bits {
4075         u8         status[0x8];
4076         u8         reserved_at_8[0x18];
4077
4078         u8         syndrome[0x20];
4079
4080         u8         reserved_at_40[0x40];
4081
4082         u8         opt_param_mask[0x20];
4083
4084         u8         reserved_at_a0[0x20];
4085
4086         struct mlx5_ifc_qpc_bits qpc;
4087
4088         u8         reserved_at_800[0x80];
4089
4090         u8         pas[0][0x40];
4091 };
4092
4093 struct mlx5_ifc_query_qp_in_bits {
4094         u8         opcode[0x10];
4095         u8         reserved_at_10[0x10];
4096
4097         u8         reserved_at_20[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         reserved_at_40[0x8];
4101         u8         qpn[0x18];
4102
4103         u8         reserved_at_60[0x20];
4104 };
4105
4106 struct mlx5_ifc_query_q_counter_out_bits {
4107         u8         status[0x8];
4108         u8         reserved_at_8[0x18];
4109
4110         u8         syndrome[0x20];
4111
4112         u8         reserved_at_40[0x40];
4113
4114         u8         rx_write_requests[0x20];
4115
4116         u8         reserved_at_a0[0x20];
4117
4118         u8         rx_read_requests[0x20];
4119
4120         u8         reserved_at_e0[0x20];
4121
4122         u8         rx_atomic_requests[0x20];
4123
4124         u8         reserved_at_120[0x20];
4125
4126         u8         rx_dct_connect[0x20];
4127
4128         u8         reserved_at_160[0x20];
4129
4130         u8         out_of_buffer[0x20];
4131
4132         u8         reserved_at_1a0[0x20];
4133
4134         u8         out_of_sequence[0x20];
4135
4136         u8         reserved_at_1e0[0x20];
4137
4138         u8         duplicate_request[0x20];
4139
4140         u8         reserved_at_220[0x20];
4141
4142         u8         rnr_nak_retry_err[0x20];
4143
4144         u8         reserved_at_260[0x20];
4145
4146         u8         packet_seq_err[0x20];
4147
4148         u8         reserved_at_2a0[0x20];
4149
4150         u8         implied_nak_seq_err[0x20];
4151
4152         u8         reserved_at_2e0[0x20];
4153
4154         u8         local_ack_timeout_err[0x20];
4155
4156         u8         reserved_at_320[0xa0];
4157
4158         u8         resp_local_length_error[0x20];
4159
4160         u8         req_local_length_error[0x20];
4161
4162         u8         resp_local_qp_error[0x20];
4163
4164         u8         local_operation_error[0x20];
4165
4166         u8         resp_local_protection[0x20];
4167
4168         u8         req_local_protection[0x20];
4169
4170         u8         resp_cqe_error[0x20];
4171
4172         u8         req_cqe_error[0x20];
4173
4174         u8         req_mw_binding[0x20];
4175
4176         u8         req_bad_response[0x20];
4177
4178         u8         req_remote_invalid_request[0x20];
4179
4180         u8         resp_remote_invalid_request[0x20];
4181
4182         u8         req_remote_access_errors[0x20];
4183
4184         u8         resp_remote_access_errors[0x20];
4185
4186         u8         req_remote_operation_errors[0x20];
4187
4188         u8         req_transport_retries_exceeded[0x20];
4189
4190         u8         cq_overflow[0x20];
4191
4192         u8         resp_cqe_flush_error[0x20];
4193
4194         u8         req_cqe_flush_error[0x20];
4195
4196         u8         reserved_at_620[0x1e0];
4197 };
4198
4199 struct mlx5_ifc_query_q_counter_in_bits {
4200         u8         opcode[0x10];
4201         u8         reserved_at_10[0x10];
4202
4203         u8         reserved_at_20[0x10];
4204         u8         op_mod[0x10];
4205
4206         u8         reserved_at_40[0x80];
4207
4208         u8         clear[0x1];
4209         u8         reserved_at_c1[0x1f];
4210
4211         u8         reserved_at_e0[0x18];
4212         u8         counter_set_id[0x8];
4213 };
4214
4215 struct mlx5_ifc_query_pages_out_bits {
4216         u8         status[0x8];
4217         u8         reserved_at_8[0x18];
4218
4219         u8         syndrome[0x20];
4220
4221         u8         reserved_at_40[0x10];
4222         u8         function_id[0x10];
4223
4224         u8         num_pages[0x20];
4225 };
4226
4227 enum {
4228         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4229         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4230         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4231 };
4232
4233 struct mlx5_ifc_query_pages_in_bits {
4234         u8         opcode[0x10];
4235         u8         reserved_at_10[0x10];
4236
4237         u8         reserved_at_20[0x10];
4238         u8         op_mod[0x10];
4239
4240         u8         reserved_at_40[0x10];
4241         u8         function_id[0x10];
4242
4243         u8         reserved_at_60[0x20];
4244 };
4245
4246 struct mlx5_ifc_query_nic_vport_context_out_bits {
4247         u8         status[0x8];
4248         u8         reserved_at_8[0x18];
4249
4250         u8         syndrome[0x20];
4251
4252         u8         reserved_at_40[0x40];
4253
4254         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4255 };
4256
4257 struct mlx5_ifc_query_nic_vport_context_in_bits {
4258         u8         opcode[0x10];
4259         u8         reserved_at_10[0x10];
4260
4261         u8         reserved_at_20[0x10];
4262         u8         op_mod[0x10];
4263
4264         u8         other_vport[0x1];
4265         u8         reserved_at_41[0xf];
4266         u8         vport_number[0x10];
4267
4268         u8         reserved_at_60[0x5];
4269         u8         allowed_list_type[0x3];
4270         u8         reserved_at_68[0x18];
4271 };
4272
4273 struct mlx5_ifc_query_mkey_out_bits {
4274         u8         status[0x8];
4275         u8         reserved_at_8[0x18];
4276
4277         u8         syndrome[0x20];
4278
4279         u8         reserved_at_40[0x40];
4280
4281         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4282
4283         u8         reserved_at_280[0x600];
4284
4285         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4286
4287         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4288 };
4289
4290 struct mlx5_ifc_query_mkey_in_bits {
4291         u8         opcode[0x10];
4292         u8         reserved_at_10[0x10];
4293
4294         u8         reserved_at_20[0x10];
4295         u8         op_mod[0x10];
4296
4297         u8         reserved_at_40[0x8];
4298         u8         mkey_index[0x18];
4299
4300         u8         pg_access[0x1];
4301         u8         reserved_at_61[0x1f];
4302 };
4303
4304 struct mlx5_ifc_query_mad_demux_out_bits {
4305         u8         status[0x8];
4306         u8         reserved_at_8[0x18];
4307
4308         u8         syndrome[0x20];
4309
4310         u8         reserved_at_40[0x40];
4311
4312         u8         mad_dumux_parameters_block[0x20];
4313 };
4314
4315 struct mlx5_ifc_query_mad_demux_in_bits {
4316         u8         opcode[0x10];
4317         u8         reserved_at_10[0x10];
4318
4319         u8         reserved_at_20[0x10];
4320         u8         op_mod[0x10];
4321
4322         u8         reserved_at_40[0x40];
4323 };
4324
4325 struct mlx5_ifc_query_l2_table_entry_out_bits {
4326         u8         status[0x8];
4327         u8         reserved_at_8[0x18];
4328
4329         u8         syndrome[0x20];
4330
4331         u8         reserved_at_40[0xa0];
4332
4333         u8         reserved_at_e0[0x13];
4334         u8         vlan_valid[0x1];
4335         u8         vlan[0xc];
4336
4337         struct mlx5_ifc_mac_address_layout_bits mac_address;
4338
4339         u8         reserved_at_140[0xc0];
4340 };
4341
4342 struct mlx5_ifc_query_l2_table_entry_in_bits {
4343         u8         opcode[0x10];
4344         u8         reserved_at_10[0x10];
4345
4346         u8         reserved_at_20[0x10];
4347         u8         op_mod[0x10];
4348
4349         u8         reserved_at_40[0x60];
4350
4351         u8         reserved_at_a0[0x8];
4352         u8         table_index[0x18];
4353
4354         u8         reserved_at_c0[0x140];
4355 };
4356
4357 struct mlx5_ifc_query_issi_out_bits {
4358         u8         status[0x8];
4359         u8         reserved_at_8[0x18];
4360
4361         u8         syndrome[0x20];
4362
4363         u8         reserved_at_40[0x10];
4364         u8         current_issi[0x10];
4365
4366         u8         reserved_at_60[0xa0];
4367
4368         u8         reserved_at_100[76][0x8];
4369         u8         supported_issi_dw0[0x20];
4370 };
4371
4372 struct mlx5_ifc_query_issi_in_bits {
4373         u8         opcode[0x10];
4374         u8         reserved_at_10[0x10];
4375
4376         u8         reserved_at_20[0x10];
4377         u8         op_mod[0x10];
4378
4379         u8         reserved_at_40[0x40];
4380 };
4381
4382 struct mlx5_ifc_set_driver_version_out_bits {
4383         u8         status[0x8];
4384         u8         reserved_0[0x18];
4385
4386         u8         syndrome[0x20];
4387         u8         reserved_1[0x40];
4388 };
4389
4390 struct mlx5_ifc_set_driver_version_in_bits {
4391         u8         opcode[0x10];
4392         u8         reserved_0[0x10];
4393
4394         u8         reserved_1[0x10];
4395         u8         op_mod[0x10];
4396
4397         u8         reserved_2[0x40];
4398         u8         driver_version[64][0x8];
4399 };
4400
4401 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4402         u8         status[0x8];
4403         u8         reserved_at_8[0x18];
4404
4405         u8         syndrome[0x20];
4406
4407         u8         reserved_at_40[0x40];
4408
4409         struct mlx5_ifc_pkey_bits pkey[0];
4410 };
4411
4412 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4413         u8         opcode[0x10];
4414         u8         reserved_at_10[0x10];
4415
4416         u8         reserved_at_20[0x10];
4417         u8         op_mod[0x10];
4418
4419         u8         other_vport[0x1];
4420         u8         reserved_at_41[0xb];
4421         u8         port_num[0x4];
4422         u8         vport_number[0x10];
4423
4424         u8         reserved_at_60[0x10];
4425         u8         pkey_index[0x10];
4426 };
4427
4428 enum {
4429         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4430         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4431         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4432 };
4433
4434 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4435         u8         status[0x8];
4436         u8         reserved_at_8[0x18];
4437
4438         u8         syndrome[0x20];
4439
4440         u8         reserved_at_40[0x20];
4441
4442         u8         gids_num[0x10];
4443         u8         reserved_at_70[0x10];
4444
4445         struct mlx5_ifc_array128_auto_bits gid[0];
4446 };
4447
4448 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4449         u8         opcode[0x10];
4450         u8         reserved_at_10[0x10];
4451
4452         u8         reserved_at_20[0x10];
4453         u8         op_mod[0x10];
4454
4455         u8         other_vport[0x1];
4456         u8         reserved_at_41[0xb];
4457         u8         port_num[0x4];
4458         u8         vport_number[0x10];
4459
4460         u8         reserved_at_60[0x10];
4461         u8         gid_index[0x10];
4462 };
4463
4464 struct mlx5_ifc_query_hca_vport_context_out_bits {
4465         u8         status[0x8];
4466         u8         reserved_at_8[0x18];
4467
4468         u8         syndrome[0x20];
4469
4470         u8         reserved_at_40[0x40];
4471
4472         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4473 };
4474
4475 struct mlx5_ifc_query_hca_vport_context_in_bits {
4476         u8         opcode[0x10];
4477         u8         reserved_at_10[0x10];
4478
4479         u8         reserved_at_20[0x10];
4480         u8         op_mod[0x10];
4481
4482         u8         other_vport[0x1];
4483         u8         reserved_at_41[0xb];
4484         u8         port_num[0x4];
4485         u8         vport_number[0x10];
4486
4487         u8         reserved_at_60[0x20];
4488 };
4489
4490 struct mlx5_ifc_query_hca_cap_out_bits {
4491         u8         status[0x8];
4492         u8         reserved_at_8[0x18];
4493
4494         u8         syndrome[0x20];
4495
4496         u8         reserved_at_40[0x40];
4497
4498         union mlx5_ifc_hca_cap_union_bits capability;
4499 };
4500
4501 struct mlx5_ifc_query_hca_cap_in_bits {
4502         u8         opcode[0x10];
4503         u8         reserved_at_10[0x10];
4504
4505         u8         reserved_at_20[0x10];
4506         u8         op_mod[0x10];
4507
4508         u8         reserved_at_40[0x40];
4509 };
4510
4511 struct mlx5_ifc_query_flow_table_out_bits {
4512         u8         status[0x8];
4513         u8         reserved_at_8[0x18];
4514
4515         u8         syndrome[0x20];
4516
4517         u8         reserved_at_40[0x80];
4518
4519         u8         reserved_at_c0[0x8];
4520         u8         level[0x8];
4521         u8         reserved_at_d0[0x8];
4522         u8         log_size[0x8];
4523
4524         u8         reserved_at_e0[0x120];
4525 };
4526
4527 struct mlx5_ifc_query_flow_table_in_bits {
4528         u8         opcode[0x10];
4529         u8         reserved_at_10[0x10];
4530
4531         u8         reserved_at_20[0x10];
4532         u8         op_mod[0x10];
4533
4534         u8         reserved_at_40[0x40];
4535
4536         u8         table_type[0x8];
4537         u8         reserved_at_88[0x18];
4538
4539         u8         reserved_at_a0[0x8];
4540         u8         table_id[0x18];
4541
4542         u8         reserved_at_c0[0x140];
4543 };
4544
4545 struct mlx5_ifc_query_fte_out_bits {
4546         u8         status[0x8];
4547         u8         reserved_at_8[0x18];
4548
4549         u8         syndrome[0x20];
4550
4551         u8         reserved_at_40[0x1c0];
4552
4553         struct mlx5_ifc_flow_context_bits flow_context;
4554 };
4555
4556 struct mlx5_ifc_query_fte_in_bits {
4557         u8         opcode[0x10];
4558         u8         reserved_at_10[0x10];
4559
4560         u8         reserved_at_20[0x10];
4561         u8         op_mod[0x10];
4562
4563         u8         reserved_at_40[0x40];
4564
4565         u8         table_type[0x8];
4566         u8         reserved_at_88[0x18];
4567
4568         u8         reserved_at_a0[0x8];
4569         u8         table_id[0x18];
4570
4571         u8         reserved_at_c0[0x40];
4572
4573         u8         flow_index[0x20];
4574
4575         u8         reserved_at_120[0xe0];
4576 };
4577
4578 enum {
4579         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4580         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4581         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4582 };
4583
4584 struct mlx5_ifc_query_flow_group_out_bits {
4585         u8         status[0x8];
4586         u8         reserved_at_8[0x18];
4587
4588         u8         syndrome[0x20];
4589
4590         u8         reserved_at_40[0xa0];
4591
4592         u8         start_flow_index[0x20];
4593
4594         u8         reserved_at_100[0x20];
4595
4596         u8         end_flow_index[0x20];
4597
4598         u8         reserved_at_140[0xa0];
4599
4600         u8         reserved_at_1e0[0x18];
4601         u8         match_criteria_enable[0x8];
4602
4603         struct mlx5_ifc_fte_match_param_bits match_criteria;
4604
4605         u8         reserved_at_1200[0xe00];
4606 };
4607
4608 struct mlx5_ifc_query_flow_group_in_bits {
4609         u8         opcode[0x10];
4610         u8         reserved_at_10[0x10];
4611
4612         u8         reserved_at_20[0x10];
4613         u8         op_mod[0x10];
4614
4615         u8         reserved_at_40[0x40];
4616
4617         u8         table_type[0x8];
4618         u8         reserved_at_88[0x18];
4619
4620         u8         reserved_at_a0[0x8];
4621         u8         table_id[0x18];
4622
4623         u8         group_id[0x20];
4624
4625         u8         reserved_at_e0[0x120];
4626 };
4627
4628 struct mlx5_ifc_query_flow_counter_out_bits {
4629         u8         status[0x8];
4630         u8         reserved_at_8[0x18];
4631
4632         u8         syndrome[0x20];
4633
4634         u8         reserved_at_40[0x40];
4635
4636         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4637 };
4638
4639 struct mlx5_ifc_query_flow_counter_in_bits {
4640         u8         opcode[0x10];
4641         u8         reserved_at_10[0x10];
4642
4643         u8         reserved_at_20[0x10];
4644         u8         op_mod[0x10];
4645
4646         u8         reserved_at_40[0x80];
4647
4648         u8         clear[0x1];
4649         u8         reserved_at_c1[0xf];
4650         u8         num_of_counters[0x10];
4651
4652         u8         flow_counter_id[0x20];
4653 };
4654
4655 struct mlx5_ifc_query_esw_vport_context_out_bits {
4656         u8         status[0x8];
4657         u8         reserved_at_8[0x18];
4658
4659         u8         syndrome[0x20];
4660
4661         u8         reserved_at_40[0x40];
4662
4663         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4664 };
4665
4666 struct mlx5_ifc_query_esw_vport_context_in_bits {
4667         u8         opcode[0x10];
4668         u8         reserved_at_10[0x10];
4669
4670         u8         reserved_at_20[0x10];
4671         u8         op_mod[0x10];
4672
4673         u8         other_vport[0x1];
4674         u8         reserved_at_41[0xf];
4675         u8         vport_number[0x10];
4676
4677         u8         reserved_at_60[0x20];
4678 };
4679
4680 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4681         u8         status[0x8];
4682         u8         reserved_at_8[0x18];
4683
4684         u8         syndrome[0x20];
4685
4686         u8         reserved_at_40[0x40];
4687 };
4688
4689 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4690         u8         reserved_at_0[0x1c];
4691         u8         vport_cvlan_insert[0x1];
4692         u8         vport_svlan_insert[0x1];
4693         u8         vport_cvlan_strip[0x1];
4694         u8         vport_svlan_strip[0x1];
4695 };
4696
4697 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4698         u8         opcode[0x10];
4699         u8         reserved_at_10[0x10];
4700
4701         u8         reserved_at_20[0x10];
4702         u8         op_mod[0x10];
4703
4704         u8         other_vport[0x1];
4705         u8         reserved_at_41[0xf];
4706         u8         vport_number[0x10];
4707
4708         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4709
4710         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4711 };
4712
4713 struct mlx5_ifc_query_eq_out_bits {
4714         u8         status[0x8];
4715         u8         reserved_at_8[0x18];
4716
4717         u8         syndrome[0x20];
4718
4719         u8         reserved_at_40[0x40];
4720
4721         struct mlx5_ifc_eqc_bits eq_context_entry;
4722
4723         u8         reserved_at_280[0x40];
4724
4725         u8         event_bitmask[0x40];
4726
4727         u8         reserved_at_300[0x580];
4728
4729         u8         pas[0][0x40];
4730 };
4731
4732 struct mlx5_ifc_query_eq_in_bits {
4733         u8         opcode[0x10];
4734         u8         reserved_at_10[0x10];
4735
4736         u8         reserved_at_20[0x10];
4737         u8         op_mod[0x10];
4738
4739         u8         reserved_at_40[0x18];
4740         u8         eq_number[0x8];
4741
4742         u8         reserved_at_60[0x20];
4743 };
4744
4745 struct mlx5_ifc_encap_header_in_bits {
4746         u8         reserved_at_0[0x5];
4747         u8         header_type[0x3];
4748         u8         reserved_at_8[0xe];
4749         u8         encap_header_size[0xa];
4750
4751         u8         reserved_at_20[0x10];
4752         u8         encap_header[2][0x8];
4753
4754         u8         more_encap_header[0][0x8];
4755 };
4756
4757 struct mlx5_ifc_query_encap_header_out_bits {
4758         u8         status[0x8];
4759         u8         reserved_at_8[0x18];
4760
4761         u8         syndrome[0x20];
4762
4763         u8         reserved_at_40[0xa0];
4764
4765         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4766 };
4767
4768 struct mlx5_ifc_query_encap_header_in_bits {
4769         u8         opcode[0x10];
4770         u8         reserved_at_10[0x10];
4771
4772         u8         reserved_at_20[0x10];
4773         u8         op_mod[0x10];
4774
4775         u8         encap_id[0x20];
4776
4777         u8         reserved_at_60[0xa0];
4778 };
4779
4780 struct mlx5_ifc_alloc_encap_header_out_bits {
4781         u8         status[0x8];
4782         u8         reserved_at_8[0x18];
4783
4784         u8         syndrome[0x20];
4785
4786         u8         encap_id[0x20];
4787
4788         u8         reserved_at_60[0x20];
4789 };
4790
4791 struct mlx5_ifc_alloc_encap_header_in_bits {
4792         u8         opcode[0x10];
4793         u8         reserved_at_10[0x10];
4794
4795         u8         reserved_at_20[0x10];
4796         u8         op_mod[0x10];
4797
4798         u8         reserved_at_40[0xa0];
4799
4800         struct mlx5_ifc_encap_header_in_bits encap_header;
4801 };
4802
4803 struct mlx5_ifc_dealloc_encap_header_out_bits {
4804         u8         status[0x8];
4805         u8         reserved_at_8[0x18];
4806
4807         u8         syndrome[0x20];
4808
4809         u8         reserved_at_40[0x40];
4810 };
4811
4812 struct mlx5_ifc_dealloc_encap_header_in_bits {
4813         u8         opcode[0x10];
4814         u8         reserved_at_10[0x10];
4815
4816         u8         reserved_20[0x10];
4817         u8         op_mod[0x10];
4818
4819         u8         encap_id[0x20];
4820
4821         u8         reserved_60[0x20];
4822 };
4823
4824 struct mlx5_ifc_set_action_in_bits {
4825         u8         action_type[0x4];
4826         u8         field[0xc];
4827         u8         reserved_at_10[0x3];
4828         u8         offset[0x5];
4829         u8         reserved_at_18[0x3];
4830         u8         length[0x5];
4831
4832         u8         data[0x20];
4833 };
4834
4835 struct mlx5_ifc_add_action_in_bits {
4836         u8         action_type[0x4];
4837         u8         field[0xc];
4838         u8         reserved_at_10[0x10];
4839
4840         u8         data[0x20];
4841 };
4842
4843 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4844         struct mlx5_ifc_set_action_in_bits set_action_in;
4845         struct mlx5_ifc_add_action_in_bits add_action_in;
4846         u8         reserved_at_0[0x40];
4847 };
4848
4849 enum {
4850         MLX5_ACTION_TYPE_SET   = 0x1,
4851         MLX5_ACTION_TYPE_ADD   = 0x2,
4852 };
4853
4854 enum {
4855         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4856         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4857         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4858         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4859         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4860         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4861         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4862         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4863         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4864         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4865         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4866         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4867         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4868         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4869         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4870         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4871         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4872         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4873         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4874         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4875         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4876         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4877         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4878 };
4879
4880 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         modify_header_id[0x20];
4887
4888         u8         reserved_at_60[0x20];
4889 };
4890
4891 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4892         u8         opcode[0x10];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         reserved_at_20[0x10];
4896         u8         op_mod[0x10];
4897
4898         u8         reserved_at_40[0x20];
4899
4900         u8         table_type[0x8];
4901         u8         reserved_at_68[0x10];
4902         u8         num_of_actions[0x8];
4903
4904         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4905 };
4906
4907 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4908         u8         status[0x8];
4909         u8         reserved_at_8[0x18];
4910
4911         u8         syndrome[0x20];
4912
4913         u8         reserved_at_40[0x40];
4914 };
4915
4916 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4917         u8         opcode[0x10];
4918         u8         reserved_at_10[0x10];
4919
4920         u8         reserved_at_20[0x10];
4921         u8         op_mod[0x10];
4922
4923         u8         modify_header_id[0x20];
4924
4925         u8         reserved_at_60[0x20];
4926 };
4927
4928 struct mlx5_ifc_query_dct_out_bits {
4929         u8         status[0x8];
4930         u8         reserved_at_8[0x18];
4931
4932         u8         syndrome[0x20];
4933
4934         u8         reserved_at_40[0x40];
4935
4936         struct mlx5_ifc_dctc_bits dct_context_entry;
4937
4938         u8         reserved_at_280[0x180];
4939 };
4940
4941 struct mlx5_ifc_query_dct_in_bits {
4942         u8         opcode[0x10];
4943         u8         reserved_at_10[0x10];
4944
4945         u8         reserved_at_20[0x10];
4946         u8         op_mod[0x10];
4947
4948         u8         reserved_at_40[0x8];
4949         u8         dctn[0x18];
4950
4951         u8         reserved_at_60[0x20];
4952 };
4953
4954 struct mlx5_ifc_query_cq_out_bits {
4955         u8         status[0x8];
4956         u8         reserved_at_8[0x18];
4957
4958         u8         syndrome[0x20];
4959
4960         u8         reserved_at_40[0x40];
4961
4962         struct mlx5_ifc_cqc_bits cq_context;
4963
4964         u8         reserved_at_280[0x600];
4965
4966         u8         pas[0][0x40];
4967 };
4968
4969 struct mlx5_ifc_query_cq_in_bits {
4970         u8         opcode[0x10];
4971         u8         reserved_at_10[0x10];
4972
4973         u8         reserved_at_20[0x10];
4974         u8         op_mod[0x10];
4975
4976         u8         reserved_at_40[0x8];
4977         u8         cqn[0x18];
4978
4979         u8         reserved_at_60[0x20];
4980 };
4981
4982 struct mlx5_ifc_query_cong_status_out_bits {
4983         u8         status[0x8];
4984         u8         reserved_at_8[0x18];
4985
4986         u8         syndrome[0x20];
4987
4988         u8         reserved_at_40[0x20];
4989
4990         u8         enable[0x1];
4991         u8         tag_enable[0x1];
4992         u8         reserved_at_62[0x1e];
4993 };
4994
4995 struct mlx5_ifc_query_cong_status_in_bits {
4996         u8         opcode[0x10];
4997         u8         reserved_at_10[0x10];
4998
4999         u8         reserved_at_20[0x10];
5000         u8         op_mod[0x10];
5001
5002         u8         reserved_at_40[0x18];
5003         u8         priority[0x4];
5004         u8         cong_protocol[0x4];
5005
5006         u8         reserved_at_60[0x20];
5007 };
5008
5009 struct mlx5_ifc_query_cong_statistics_out_bits {
5010         u8         status[0x8];
5011         u8         reserved_at_8[0x18];
5012
5013         u8         syndrome[0x20];
5014
5015         u8         reserved_at_40[0x40];
5016
5017         u8         rp_cur_flows[0x20];
5018
5019         u8         sum_flows[0x20];
5020
5021         u8         rp_cnp_ignored_high[0x20];
5022
5023         u8         rp_cnp_ignored_low[0x20];
5024
5025         u8         rp_cnp_handled_high[0x20];
5026
5027         u8         rp_cnp_handled_low[0x20];
5028
5029         u8         reserved_at_140[0x100];
5030
5031         u8         time_stamp_high[0x20];
5032
5033         u8         time_stamp_low[0x20];
5034
5035         u8         accumulators_period[0x20];
5036
5037         u8         np_ecn_marked_roce_packets_high[0x20];
5038
5039         u8         np_ecn_marked_roce_packets_low[0x20];
5040
5041         u8         np_cnp_sent_high[0x20];
5042
5043         u8         np_cnp_sent_low[0x20];
5044
5045         u8         reserved_at_320[0x560];
5046 };
5047
5048 struct mlx5_ifc_query_cong_statistics_in_bits {
5049         u8         opcode[0x10];
5050         u8         reserved_at_10[0x10];
5051
5052         u8         reserved_at_20[0x10];
5053         u8         op_mod[0x10];
5054
5055         u8         clear[0x1];
5056         u8         reserved_at_41[0x1f];
5057
5058         u8         reserved_at_60[0x20];
5059 };
5060
5061 struct mlx5_ifc_query_cong_params_out_bits {
5062         u8         status[0x8];
5063         u8         reserved_at_8[0x18];
5064
5065         u8         syndrome[0x20];
5066
5067         u8         reserved_at_40[0x40];
5068
5069         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5070 };
5071
5072 struct mlx5_ifc_query_cong_params_in_bits {
5073         u8         opcode[0x10];
5074         u8         reserved_at_10[0x10];
5075
5076         u8         reserved_at_20[0x10];
5077         u8         op_mod[0x10];
5078
5079         u8         reserved_at_40[0x1c];
5080         u8         cong_protocol[0x4];
5081
5082         u8         reserved_at_60[0x20];
5083 };
5084
5085 struct mlx5_ifc_query_adapter_out_bits {
5086         u8         status[0x8];
5087         u8         reserved_at_8[0x18];
5088
5089         u8         syndrome[0x20];
5090
5091         u8         reserved_at_40[0x40];
5092
5093         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5094 };
5095
5096 struct mlx5_ifc_query_adapter_in_bits {
5097         u8         opcode[0x10];
5098         u8         reserved_at_10[0x10];
5099
5100         u8         reserved_at_20[0x10];
5101         u8         op_mod[0x10];
5102
5103         u8         reserved_at_40[0x40];
5104 };
5105
5106 struct mlx5_ifc_qp_2rst_out_bits {
5107         u8         status[0x8];
5108         u8         reserved_at_8[0x18];
5109
5110         u8         syndrome[0x20];
5111
5112         u8         reserved_at_40[0x40];
5113 };
5114
5115 struct mlx5_ifc_qp_2rst_in_bits {
5116         u8         opcode[0x10];
5117         u8         reserved_at_10[0x10];
5118
5119         u8         reserved_at_20[0x10];
5120         u8         op_mod[0x10];
5121
5122         u8         reserved_at_40[0x8];
5123         u8         qpn[0x18];
5124
5125         u8         reserved_at_60[0x20];
5126 };
5127
5128 struct mlx5_ifc_qp_2err_out_bits {
5129         u8         status[0x8];
5130         u8         reserved_at_8[0x18];
5131
5132         u8         syndrome[0x20];
5133
5134         u8         reserved_at_40[0x40];
5135 };
5136
5137 struct mlx5_ifc_qp_2err_in_bits {
5138         u8         opcode[0x10];
5139         u8         reserved_at_10[0x10];
5140
5141         u8         reserved_at_20[0x10];
5142         u8         op_mod[0x10];
5143
5144         u8         reserved_at_40[0x8];
5145         u8         qpn[0x18];
5146
5147         u8         reserved_at_60[0x20];
5148 };
5149
5150 struct mlx5_ifc_page_fault_resume_out_bits {
5151         u8         status[0x8];
5152         u8         reserved_at_8[0x18];
5153
5154         u8         syndrome[0x20];
5155
5156         u8         reserved_at_40[0x40];
5157 };
5158
5159 struct mlx5_ifc_page_fault_resume_in_bits {
5160         u8         opcode[0x10];
5161         u8         reserved_at_10[0x10];
5162
5163         u8         reserved_at_20[0x10];
5164         u8         op_mod[0x10];
5165
5166         u8         error[0x1];
5167         u8         reserved_at_41[0x4];
5168         u8         page_fault_type[0x3];
5169         u8         wq_number[0x18];
5170
5171         u8         reserved_at_60[0x8];
5172         u8         token[0x18];
5173 };
5174
5175 struct mlx5_ifc_nop_out_bits {
5176         u8         status[0x8];
5177         u8         reserved_at_8[0x18];
5178
5179         u8         syndrome[0x20];
5180
5181         u8         reserved_at_40[0x40];
5182 };
5183
5184 struct mlx5_ifc_nop_in_bits {
5185         u8         opcode[0x10];
5186         u8         reserved_at_10[0x10];
5187
5188         u8         reserved_at_20[0x10];
5189         u8         op_mod[0x10];
5190
5191         u8         reserved_at_40[0x40];
5192 };
5193
5194 struct mlx5_ifc_modify_vport_state_out_bits {
5195         u8         status[0x8];
5196         u8         reserved_at_8[0x18];
5197
5198         u8         syndrome[0x20];
5199
5200         u8         reserved_at_40[0x40];
5201 };
5202
5203 struct mlx5_ifc_modify_vport_state_in_bits {
5204         u8         opcode[0x10];
5205         u8         reserved_at_10[0x10];
5206
5207         u8         reserved_at_20[0x10];
5208         u8         op_mod[0x10];
5209
5210         u8         other_vport[0x1];
5211         u8         reserved_at_41[0xf];
5212         u8         vport_number[0x10];
5213
5214         u8         reserved_at_60[0x18];
5215         u8         admin_state[0x4];
5216         u8         reserved_at_7c[0x4];
5217 };
5218
5219 struct mlx5_ifc_modify_tis_out_bits {
5220         u8         status[0x8];
5221         u8         reserved_at_8[0x18];
5222
5223         u8         syndrome[0x20];
5224
5225         u8         reserved_at_40[0x40];
5226 };
5227
5228 struct mlx5_ifc_modify_tis_bitmask_bits {
5229         u8         reserved_at_0[0x20];
5230
5231         u8         reserved_at_20[0x1d];
5232         u8         lag_tx_port_affinity[0x1];
5233         u8         strict_lag_tx_port_affinity[0x1];
5234         u8         prio[0x1];
5235 };
5236
5237 struct mlx5_ifc_modify_tis_in_bits {
5238         u8         opcode[0x10];
5239         u8         reserved_at_10[0x10];
5240
5241         u8         reserved_at_20[0x10];
5242         u8         op_mod[0x10];
5243
5244         u8         reserved_at_40[0x8];
5245         u8         tisn[0x18];
5246
5247         u8         reserved_at_60[0x20];
5248
5249         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5250
5251         u8         reserved_at_c0[0x40];
5252
5253         struct mlx5_ifc_tisc_bits ctx;
5254 };
5255
5256 struct mlx5_ifc_modify_tir_bitmask_bits {
5257         u8         reserved_at_0[0x20];
5258
5259         u8         reserved_at_20[0x1b];
5260         u8         self_lb_en[0x1];
5261         u8         reserved_at_3c[0x1];
5262         u8         hash[0x1];
5263         u8         reserved_at_3e[0x1];
5264         u8         lro[0x1];
5265 };
5266
5267 struct mlx5_ifc_modify_tir_out_bits {
5268         u8         status[0x8];
5269         u8         reserved_at_8[0x18];
5270
5271         u8         syndrome[0x20];
5272
5273         u8         reserved_at_40[0x40];
5274 };
5275
5276 struct mlx5_ifc_modify_tir_in_bits {
5277         u8         opcode[0x10];
5278         u8         reserved_at_10[0x10];
5279
5280         u8         reserved_at_20[0x10];
5281         u8         op_mod[0x10];
5282
5283         u8         reserved_at_40[0x8];
5284         u8         tirn[0x18];
5285
5286         u8         reserved_at_60[0x20];
5287
5288         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5289
5290         u8         reserved_at_c0[0x40];
5291
5292         struct mlx5_ifc_tirc_bits ctx;
5293 };
5294
5295 struct mlx5_ifc_modify_sq_out_bits {
5296         u8         status[0x8];
5297         u8         reserved_at_8[0x18];
5298
5299         u8         syndrome[0x20];
5300
5301         u8         reserved_at_40[0x40];
5302 };
5303
5304 struct mlx5_ifc_modify_sq_in_bits {
5305         u8         opcode[0x10];
5306         u8         reserved_at_10[0x10];
5307
5308         u8         reserved_at_20[0x10];
5309         u8         op_mod[0x10];
5310
5311         u8         sq_state[0x4];
5312         u8         reserved_at_44[0x4];
5313         u8         sqn[0x18];
5314
5315         u8         reserved_at_60[0x20];
5316
5317         u8         modify_bitmask[0x40];
5318
5319         u8         reserved_at_c0[0x40];
5320
5321         struct mlx5_ifc_sqc_bits ctx;
5322 };
5323
5324 struct mlx5_ifc_modify_scheduling_element_out_bits {
5325         u8         status[0x8];
5326         u8         reserved_at_8[0x18];
5327
5328         u8         syndrome[0x20];
5329
5330         u8         reserved_at_40[0x1c0];
5331 };
5332
5333 enum {
5334         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5335         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5336 };
5337
5338 struct mlx5_ifc_modify_scheduling_element_in_bits {
5339         u8         opcode[0x10];
5340         u8         reserved_at_10[0x10];
5341
5342         u8         reserved_at_20[0x10];
5343         u8         op_mod[0x10];
5344
5345         u8         scheduling_hierarchy[0x8];
5346         u8         reserved_at_48[0x18];
5347
5348         u8         scheduling_element_id[0x20];
5349
5350         u8         reserved_at_80[0x20];
5351
5352         u8         modify_bitmask[0x20];
5353
5354         u8         reserved_at_c0[0x40];
5355
5356         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5357
5358         u8         reserved_at_300[0x100];
5359 };
5360
5361 struct mlx5_ifc_modify_rqt_out_bits {
5362         u8         status[0x8];
5363         u8         reserved_at_8[0x18];
5364
5365         u8         syndrome[0x20];
5366
5367         u8         reserved_at_40[0x40];
5368 };
5369
5370 struct mlx5_ifc_rqt_bitmask_bits {
5371         u8         reserved_at_0[0x20];
5372
5373         u8         reserved_at_20[0x1f];
5374         u8         rqn_list[0x1];
5375 };
5376
5377 struct mlx5_ifc_modify_rqt_in_bits {
5378         u8         opcode[0x10];
5379         u8         reserved_at_10[0x10];
5380
5381         u8         reserved_at_20[0x10];
5382         u8         op_mod[0x10];
5383
5384         u8         reserved_at_40[0x8];
5385         u8         rqtn[0x18];
5386
5387         u8         reserved_at_60[0x20];
5388
5389         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5390
5391         u8         reserved_at_c0[0x40];
5392
5393         struct mlx5_ifc_rqtc_bits ctx;
5394 };
5395
5396 struct mlx5_ifc_modify_rq_out_bits {
5397         u8         status[0x8];
5398         u8         reserved_at_8[0x18];
5399
5400         u8         syndrome[0x20];
5401
5402         u8         reserved_at_40[0x40];
5403 };
5404
5405 enum {
5406         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5407         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5408         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5409 };
5410
5411 struct mlx5_ifc_modify_rq_in_bits {
5412         u8         opcode[0x10];
5413         u8         reserved_at_10[0x10];
5414
5415         u8         reserved_at_20[0x10];
5416         u8         op_mod[0x10];
5417
5418         u8         rq_state[0x4];
5419         u8         reserved_at_44[0x4];
5420         u8         rqn[0x18];
5421
5422         u8         reserved_at_60[0x20];
5423
5424         u8         modify_bitmask[0x40];
5425
5426         u8         reserved_at_c0[0x40];
5427
5428         struct mlx5_ifc_rqc_bits ctx;
5429 };
5430
5431 struct mlx5_ifc_modify_rmp_out_bits {
5432         u8         status[0x8];
5433         u8         reserved_at_8[0x18];
5434
5435         u8         syndrome[0x20];
5436
5437         u8         reserved_at_40[0x40];
5438 };
5439
5440 struct mlx5_ifc_rmp_bitmask_bits {
5441         u8         reserved_at_0[0x20];
5442
5443         u8         reserved_at_20[0x1f];
5444         u8         lwm[0x1];
5445 };
5446
5447 struct mlx5_ifc_modify_rmp_in_bits {
5448         u8         opcode[0x10];
5449         u8         reserved_at_10[0x10];
5450
5451         u8         reserved_at_20[0x10];
5452         u8         op_mod[0x10];
5453
5454         u8         rmp_state[0x4];
5455         u8         reserved_at_44[0x4];
5456         u8         rmpn[0x18];
5457
5458         u8         reserved_at_60[0x20];
5459
5460         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5461
5462         u8         reserved_at_c0[0x40];
5463
5464         struct mlx5_ifc_rmpc_bits ctx;
5465 };
5466
5467 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5468         u8         status[0x8];
5469         u8         reserved_at_8[0x18];
5470
5471         u8         syndrome[0x20];
5472
5473         u8         reserved_at_40[0x40];
5474 };
5475
5476 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5477         u8         reserved_at_0[0x12];
5478         u8         affiliation[0x1];
5479         u8         reserved_at_e[0x1];
5480         u8         disable_uc_local_lb[0x1];
5481         u8         disable_mc_local_lb[0x1];
5482         u8         node_guid[0x1];
5483         u8         port_guid[0x1];
5484         u8         min_inline[0x1];
5485         u8         mtu[0x1];
5486         u8         change_event[0x1];
5487         u8         promisc[0x1];
5488         u8         permanent_address[0x1];
5489         u8         addresses_list[0x1];
5490         u8         roce_en[0x1];
5491         u8         reserved_at_1f[0x1];
5492 };
5493
5494 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5495         u8         opcode[0x10];
5496         u8         reserved_at_10[0x10];
5497
5498         u8         reserved_at_20[0x10];
5499         u8         op_mod[0x10];
5500
5501         u8         other_vport[0x1];
5502         u8         reserved_at_41[0xf];
5503         u8         vport_number[0x10];
5504
5505         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5506
5507         u8         reserved_at_80[0x780];
5508
5509         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5510 };
5511
5512 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5513         u8         status[0x8];
5514         u8         reserved_at_8[0x18];
5515
5516         u8         syndrome[0x20];
5517
5518         u8         reserved_at_40[0x40];
5519 };
5520
5521 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5522         u8         opcode[0x10];
5523         u8         reserved_at_10[0x10];
5524
5525         u8         reserved_at_20[0x10];
5526         u8         op_mod[0x10];
5527
5528         u8         other_vport[0x1];
5529         u8         reserved_at_41[0xb];
5530         u8         port_num[0x4];
5531         u8         vport_number[0x10];
5532
5533         u8         reserved_at_60[0x20];
5534
5535         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5536 };
5537
5538 struct mlx5_ifc_modify_cq_out_bits {
5539         u8         status[0x8];
5540         u8         reserved_at_8[0x18];
5541
5542         u8         syndrome[0x20];
5543
5544         u8         reserved_at_40[0x40];
5545 };
5546
5547 enum {
5548         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5549         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5550 };
5551
5552 struct mlx5_ifc_modify_cq_in_bits {
5553         u8         opcode[0x10];
5554         u8         reserved_at_10[0x10];
5555
5556         u8         reserved_at_20[0x10];
5557         u8         op_mod[0x10];
5558
5559         u8         reserved_at_40[0x8];
5560         u8         cqn[0x18];
5561
5562         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5563
5564         struct mlx5_ifc_cqc_bits cq_context;
5565
5566         u8         reserved_at_280[0x600];
5567
5568         u8         pas[0][0x40];
5569 };
5570
5571 struct mlx5_ifc_modify_cong_status_out_bits {
5572         u8         status[0x8];
5573         u8         reserved_at_8[0x18];
5574
5575         u8         syndrome[0x20];
5576
5577         u8         reserved_at_40[0x40];
5578 };
5579
5580 struct mlx5_ifc_modify_cong_status_in_bits {
5581         u8         opcode[0x10];
5582         u8         reserved_at_10[0x10];
5583
5584         u8         reserved_at_20[0x10];
5585         u8         op_mod[0x10];
5586
5587         u8         reserved_at_40[0x18];
5588         u8         priority[0x4];
5589         u8         cong_protocol[0x4];
5590
5591         u8         enable[0x1];
5592         u8         tag_enable[0x1];
5593         u8         reserved_at_62[0x1e];
5594 };
5595
5596 struct mlx5_ifc_modify_cong_params_out_bits {
5597         u8         status[0x8];
5598         u8         reserved_at_8[0x18];
5599
5600         u8         syndrome[0x20];
5601
5602         u8         reserved_at_40[0x40];
5603 };
5604
5605 struct mlx5_ifc_modify_cong_params_in_bits {
5606         u8         opcode[0x10];
5607         u8         reserved_at_10[0x10];
5608
5609         u8         reserved_at_20[0x10];
5610         u8         op_mod[0x10];
5611
5612         u8         reserved_at_40[0x1c];
5613         u8         cong_protocol[0x4];
5614
5615         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5616
5617         u8         reserved_at_80[0x80];
5618
5619         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5620 };
5621
5622 struct mlx5_ifc_manage_pages_out_bits {
5623         u8         status[0x8];
5624         u8         reserved_at_8[0x18];
5625
5626         u8         syndrome[0x20];
5627
5628         u8         output_num_entries[0x20];
5629
5630         u8         reserved_at_60[0x20];
5631
5632         u8         pas[0][0x40];
5633 };
5634
5635 enum {
5636         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5637         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5638         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5639 };
5640
5641 struct mlx5_ifc_manage_pages_in_bits {
5642         u8         opcode[0x10];
5643         u8         reserved_at_10[0x10];
5644
5645         u8         reserved_at_20[0x10];
5646         u8         op_mod[0x10];
5647
5648         u8         reserved_at_40[0x10];
5649         u8         function_id[0x10];
5650
5651         u8         input_num_entries[0x20];
5652
5653         u8         pas[0][0x40];
5654 };
5655
5656 struct mlx5_ifc_mad_ifc_out_bits {
5657         u8         status[0x8];
5658         u8         reserved_at_8[0x18];
5659
5660         u8         syndrome[0x20];
5661
5662         u8         reserved_at_40[0x40];
5663
5664         u8         response_mad_packet[256][0x8];
5665 };
5666
5667 struct mlx5_ifc_mad_ifc_in_bits {
5668         u8         opcode[0x10];
5669         u8         reserved_at_10[0x10];
5670
5671         u8         reserved_at_20[0x10];
5672         u8         op_mod[0x10];
5673
5674         u8         remote_lid[0x10];
5675         u8         reserved_at_50[0x8];
5676         u8         port[0x8];
5677
5678         u8         reserved_at_60[0x20];
5679
5680         u8         mad[256][0x8];
5681 };
5682
5683 struct mlx5_ifc_init_hca_out_bits {
5684         u8         status[0x8];
5685         u8         reserved_at_8[0x18];
5686
5687         u8         syndrome[0x20];
5688
5689         u8         reserved_at_40[0x40];
5690 };
5691
5692 struct mlx5_ifc_init_hca_in_bits {
5693         u8         opcode[0x10];
5694         u8         reserved_at_10[0x10];
5695
5696         u8         reserved_at_20[0x10];
5697         u8         op_mod[0x10];
5698
5699         u8         reserved_at_40[0x40];
5700         u8         sw_owner_id[4][0x20];
5701 };
5702
5703 struct mlx5_ifc_init2rtr_qp_out_bits {
5704         u8         status[0x8];
5705         u8         reserved_at_8[0x18];
5706
5707         u8         syndrome[0x20];
5708
5709         u8         reserved_at_40[0x40];
5710 };
5711
5712 struct mlx5_ifc_init2rtr_qp_in_bits {
5713         u8         opcode[0x10];
5714         u8         reserved_at_10[0x10];
5715
5716         u8         reserved_at_20[0x10];
5717         u8         op_mod[0x10];
5718
5719         u8         reserved_at_40[0x8];
5720         u8         qpn[0x18];
5721
5722         u8         reserved_at_60[0x20];
5723
5724         u8         opt_param_mask[0x20];
5725
5726         u8         reserved_at_a0[0x20];
5727
5728         struct mlx5_ifc_qpc_bits qpc;
5729
5730         u8         reserved_at_800[0x80];
5731 };
5732
5733 struct mlx5_ifc_init2init_qp_out_bits {
5734         u8         status[0x8];
5735         u8         reserved_at_8[0x18];
5736
5737         u8         syndrome[0x20];
5738
5739         u8         reserved_at_40[0x40];
5740 };
5741
5742 struct mlx5_ifc_init2init_qp_in_bits {
5743         u8         opcode[0x10];
5744         u8         reserved_at_10[0x10];
5745
5746         u8         reserved_at_20[0x10];
5747         u8         op_mod[0x10];
5748
5749         u8         reserved_at_40[0x8];
5750         u8         qpn[0x18];
5751
5752         u8         reserved_at_60[0x20];
5753
5754         u8         opt_param_mask[0x20];
5755
5756         u8         reserved_at_a0[0x20];
5757
5758         struct mlx5_ifc_qpc_bits qpc;
5759
5760         u8         reserved_at_800[0x80];
5761 };
5762
5763 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5764         u8         status[0x8];
5765         u8         reserved_at_8[0x18];
5766
5767         u8         syndrome[0x20];
5768
5769         u8         reserved_at_40[0x40];
5770
5771         u8         packet_headers_log[128][0x8];
5772
5773         u8         packet_syndrome[64][0x8];
5774 };
5775
5776 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5777         u8         opcode[0x10];
5778         u8         reserved_at_10[0x10];
5779
5780         u8         reserved_at_20[0x10];
5781         u8         op_mod[0x10];
5782
5783         u8         reserved_at_40[0x40];
5784 };
5785
5786 struct mlx5_ifc_gen_eqe_in_bits {
5787         u8         opcode[0x10];
5788         u8         reserved_at_10[0x10];
5789
5790         u8         reserved_at_20[0x10];
5791         u8         op_mod[0x10];
5792
5793         u8         reserved_at_40[0x18];
5794         u8         eq_number[0x8];
5795
5796         u8         reserved_at_60[0x20];
5797
5798         u8         eqe[64][0x8];
5799 };
5800
5801 struct mlx5_ifc_gen_eq_out_bits {
5802         u8         status[0x8];
5803         u8         reserved_at_8[0x18];
5804
5805         u8         syndrome[0x20];
5806
5807         u8         reserved_at_40[0x40];
5808 };
5809
5810 struct mlx5_ifc_enable_hca_out_bits {
5811         u8         status[0x8];
5812         u8         reserved_at_8[0x18];
5813
5814         u8         syndrome[0x20];
5815
5816         u8         reserved_at_40[0x20];
5817 };
5818
5819 struct mlx5_ifc_enable_hca_in_bits {
5820         u8         opcode[0x10];
5821         u8         reserved_at_10[0x10];
5822
5823         u8         reserved_at_20[0x10];
5824         u8         op_mod[0x10];
5825
5826         u8         reserved_at_40[0x10];
5827         u8         function_id[0x10];
5828
5829         u8         reserved_at_60[0x20];
5830 };
5831
5832 struct mlx5_ifc_drain_dct_out_bits {
5833         u8         status[0x8];
5834         u8         reserved_at_8[0x18];
5835
5836         u8         syndrome[0x20];
5837
5838         u8         reserved_at_40[0x40];
5839 };
5840
5841 struct mlx5_ifc_drain_dct_in_bits {
5842         u8         opcode[0x10];
5843         u8         reserved_at_10[0x10];
5844
5845         u8         reserved_at_20[0x10];
5846         u8         op_mod[0x10];
5847
5848         u8         reserved_at_40[0x8];
5849         u8         dctn[0x18];
5850
5851         u8         reserved_at_60[0x20];
5852 };
5853
5854 struct mlx5_ifc_disable_hca_out_bits {
5855         u8         status[0x8];
5856         u8         reserved_at_8[0x18];
5857
5858         u8         syndrome[0x20];
5859
5860         u8         reserved_at_40[0x20];
5861 };
5862
5863 struct mlx5_ifc_disable_hca_in_bits {
5864         u8         opcode[0x10];
5865         u8         reserved_at_10[0x10];
5866
5867         u8         reserved_at_20[0x10];
5868         u8         op_mod[0x10];
5869
5870         u8         reserved_at_40[0x10];
5871         u8         function_id[0x10];
5872
5873         u8         reserved_at_60[0x20];
5874 };
5875
5876 struct mlx5_ifc_detach_from_mcg_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x40];
5883 };
5884
5885 struct mlx5_ifc_detach_from_mcg_in_bits {
5886         u8         opcode[0x10];
5887         u8         reserved_at_10[0x10];
5888
5889         u8         reserved_at_20[0x10];
5890         u8         op_mod[0x10];
5891
5892         u8         reserved_at_40[0x8];
5893         u8         qpn[0x18];
5894
5895         u8         reserved_at_60[0x20];
5896
5897         u8         multicast_gid[16][0x8];
5898 };
5899
5900 struct mlx5_ifc_destroy_xrq_out_bits {
5901         u8         status[0x8];
5902         u8         reserved_at_8[0x18];
5903
5904         u8         syndrome[0x20];
5905
5906         u8         reserved_at_40[0x40];
5907 };
5908
5909 struct mlx5_ifc_destroy_xrq_in_bits {
5910         u8         opcode[0x10];
5911         u8         reserved_at_10[0x10];
5912
5913         u8         reserved_at_20[0x10];
5914         u8         op_mod[0x10];
5915
5916         u8         reserved_at_40[0x8];
5917         u8         xrqn[0x18];
5918
5919         u8         reserved_at_60[0x20];
5920 };
5921
5922 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5923         u8         status[0x8];
5924         u8         reserved_at_8[0x18];
5925
5926         u8         syndrome[0x20];
5927
5928         u8         reserved_at_40[0x40];
5929 };
5930
5931 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5932         u8         opcode[0x10];
5933         u8         reserved_at_10[0x10];
5934
5935         u8         reserved_at_20[0x10];
5936         u8         op_mod[0x10];
5937
5938         u8         reserved_at_40[0x8];
5939         u8         xrc_srqn[0x18];
5940
5941         u8         reserved_at_60[0x20];
5942 };
5943
5944 struct mlx5_ifc_destroy_tis_out_bits {
5945         u8         status[0x8];
5946         u8         reserved_at_8[0x18];
5947
5948         u8         syndrome[0x20];
5949
5950         u8         reserved_at_40[0x40];
5951 };
5952
5953 struct mlx5_ifc_destroy_tis_in_bits {
5954         u8         opcode[0x10];
5955         u8         reserved_at_10[0x10];
5956
5957         u8         reserved_at_20[0x10];
5958         u8         op_mod[0x10];
5959
5960         u8         reserved_at_40[0x8];
5961         u8         tisn[0x18];
5962
5963         u8         reserved_at_60[0x20];
5964 };
5965
5966 struct mlx5_ifc_destroy_tir_out_bits {
5967         u8         status[0x8];
5968         u8         reserved_at_8[0x18];
5969
5970         u8         syndrome[0x20];
5971
5972         u8         reserved_at_40[0x40];
5973 };
5974
5975 struct mlx5_ifc_destroy_tir_in_bits {
5976         u8         opcode[0x10];
5977         u8         reserved_at_10[0x10];
5978
5979         u8         reserved_at_20[0x10];
5980         u8         op_mod[0x10];
5981
5982         u8         reserved_at_40[0x8];
5983         u8         tirn[0x18];
5984
5985         u8         reserved_at_60[0x20];
5986 };
5987
5988 struct mlx5_ifc_destroy_srq_out_bits {
5989         u8         status[0x8];
5990         u8         reserved_at_8[0x18];
5991
5992         u8         syndrome[0x20];
5993
5994         u8         reserved_at_40[0x40];
5995 };
5996
5997 struct mlx5_ifc_destroy_srq_in_bits {
5998         u8         opcode[0x10];
5999         u8         reserved_at_10[0x10];
6000
6001         u8         reserved_at_20[0x10];
6002         u8         op_mod[0x10];
6003
6004         u8         reserved_at_40[0x8];
6005         u8         srqn[0x18];
6006
6007         u8         reserved_at_60[0x20];
6008 };
6009
6010 struct mlx5_ifc_destroy_sq_out_bits {
6011         u8         status[0x8];
6012         u8         reserved_at_8[0x18];
6013
6014         u8         syndrome[0x20];
6015
6016         u8         reserved_at_40[0x40];
6017 };
6018
6019 struct mlx5_ifc_destroy_sq_in_bits {
6020         u8         opcode[0x10];
6021         u8         reserved_at_10[0x10];
6022
6023         u8         reserved_at_20[0x10];
6024         u8         op_mod[0x10];
6025
6026         u8         reserved_at_40[0x8];
6027         u8         sqn[0x18];
6028
6029         u8         reserved_at_60[0x20];
6030 };
6031
6032 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6033         u8         status[0x8];
6034         u8         reserved_at_8[0x18];
6035
6036         u8         syndrome[0x20];
6037
6038         u8         reserved_at_40[0x1c0];
6039 };
6040
6041 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6042         u8         opcode[0x10];
6043         u8         reserved_at_10[0x10];
6044
6045         u8         reserved_at_20[0x10];
6046         u8         op_mod[0x10];
6047
6048         u8         scheduling_hierarchy[0x8];
6049         u8         reserved_at_48[0x18];
6050
6051         u8         scheduling_element_id[0x20];
6052
6053         u8         reserved_at_80[0x180];
6054 };
6055
6056 struct mlx5_ifc_destroy_rqt_out_bits {
6057         u8         status[0x8];
6058         u8         reserved_at_8[0x18];
6059
6060         u8         syndrome[0x20];
6061
6062         u8         reserved_at_40[0x40];
6063 };
6064
6065 struct mlx5_ifc_destroy_rqt_in_bits {
6066         u8         opcode[0x10];
6067         u8         reserved_at_10[0x10];
6068
6069         u8         reserved_at_20[0x10];
6070         u8         op_mod[0x10];
6071
6072         u8         reserved_at_40[0x8];
6073         u8         rqtn[0x18];
6074
6075         u8         reserved_at_60[0x20];
6076 };
6077
6078 struct mlx5_ifc_destroy_rq_out_bits {
6079         u8         status[0x8];
6080         u8         reserved_at_8[0x18];
6081
6082         u8         syndrome[0x20];
6083
6084         u8         reserved_at_40[0x40];
6085 };
6086
6087 struct mlx5_ifc_destroy_rq_in_bits {
6088         u8         opcode[0x10];
6089         u8         reserved_at_10[0x10];
6090
6091         u8         reserved_at_20[0x10];
6092         u8         op_mod[0x10];
6093
6094         u8         reserved_at_40[0x8];
6095         u8         rqn[0x18];
6096
6097         u8         reserved_at_60[0x20];
6098 };
6099
6100 struct mlx5_ifc_set_delay_drop_params_in_bits {
6101         u8         opcode[0x10];
6102         u8         reserved_at_10[0x10];
6103
6104         u8         reserved_at_20[0x10];
6105         u8         op_mod[0x10];
6106
6107         u8         reserved_at_40[0x20];
6108
6109         u8         reserved_at_60[0x10];
6110         u8         delay_drop_timeout[0x10];
6111 };
6112
6113 struct mlx5_ifc_set_delay_drop_params_out_bits {
6114         u8         status[0x8];
6115         u8         reserved_at_8[0x18];
6116
6117         u8         syndrome[0x20];
6118
6119         u8         reserved_at_40[0x40];
6120 };
6121
6122 struct mlx5_ifc_destroy_rmp_out_bits {
6123         u8         status[0x8];
6124         u8         reserved_at_8[0x18];
6125
6126         u8         syndrome[0x20];
6127
6128         u8         reserved_at_40[0x40];
6129 };
6130
6131 struct mlx5_ifc_destroy_rmp_in_bits {
6132         u8         opcode[0x10];
6133         u8         reserved_at_10[0x10];
6134
6135         u8         reserved_at_20[0x10];
6136         u8         op_mod[0x10];
6137
6138         u8         reserved_at_40[0x8];
6139         u8         rmpn[0x18];
6140
6141         u8         reserved_at_60[0x20];
6142 };
6143
6144 struct mlx5_ifc_destroy_qp_out_bits {
6145         u8         status[0x8];
6146         u8         reserved_at_8[0x18];
6147
6148         u8         syndrome[0x20];
6149
6150         u8         reserved_at_40[0x40];
6151 };
6152
6153 struct mlx5_ifc_destroy_qp_in_bits {
6154         u8         opcode[0x10];
6155         u8         reserved_at_10[0x10];
6156
6157         u8         reserved_at_20[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         reserved_at_40[0x8];
6161         u8         qpn[0x18];
6162
6163         u8         reserved_at_60[0x20];
6164 };
6165
6166 struct mlx5_ifc_destroy_psv_out_bits {
6167         u8         status[0x8];
6168         u8         reserved_at_8[0x18];
6169
6170         u8         syndrome[0x20];
6171
6172         u8         reserved_at_40[0x40];
6173 };
6174
6175 struct mlx5_ifc_destroy_psv_in_bits {
6176         u8         opcode[0x10];
6177         u8         reserved_at_10[0x10];
6178
6179         u8         reserved_at_20[0x10];
6180         u8         op_mod[0x10];
6181
6182         u8         reserved_at_40[0x8];
6183         u8         psvn[0x18];
6184
6185         u8         reserved_at_60[0x20];
6186 };
6187
6188 struct mlx5_ifc_destroy_mkey_out_bits {
6189         u8         status[0x8];
6190         u8         reserved_at_8[0x18];
6191
6192         u8         syndrome[0x20];
6193
6194         u8         reserved_at_40[0x40];
6195 };
6196
6197 struct mlx5_ifc_destroy_mkey_in_bits {
6198         u8         opcode[0x10];
6199         u8         reserved_at_10[0x10];
6200
6201         u8         reserved_at_20[0x10];
6202         u8         op_mod[0x10];
6203
6204         u8         reserved_at_40[0x8];
6205         u8         mkey_index[0x18];
6206
6207         u8         reserved_at_60[0x20];
6208 };
6209
6210 struct mlx5_ifc_destroy_flow_table_out_bits {
6211         u8         status[0x8];
6212         u8         reserved_at_8[0x18];
6213
6214         u8         syndrome[0x20];
6215
6216         u8         reserved_at_40[0x40];
6217 };
6218
6219 struct mlx5_ifc_destroy_flow_table_in_bits {
6220         u8         opcode[0x10];
6221         u8         reserved_at_10[0x10];
6222
6223         u8         reserved_at_20[0x10];
6224         u8         op_mod[0x10];
6225
6226         u8         other_vport[0x1];
6227         u8         reserved_at_41[0xf];
6228         u8         vport_number[0x10];
6229
6230         u8         reserved_at_60[0x20];
6231
6232         u8         table_type[0x8];
6233         u8         reserved_at_88[0x18];
6234
6235         u8         reserved_at_a0[0x8];
6236         u8         table_id[0x18];
6237
6238         u8         reserved_at_c0[0x140];
6239 };
6240
6241 struct mlx5_ifc_destroy_flow_group_out_bits {
6242         u8         status[0x8];
6243         u8         reserved_at_8[0x18];
6244
6245         u8         syndrome[0x20];
6246
6247         u8         reserved_at_40[0x40];
6248 };
6249
6250 struct mlx5_ifc_destroy_flow_group_in_bits {
6251         u8         opcode[0x10];
6252         u8         reserved_at_10[0x10];
6253
6254         u8         reserved_at_20[0x10];
6255         u8         op_mod[0x10];
6256
6257         u8         other_vport[0x1];
6258         u8         reserved_at_41[0xf];
6259         u8         vport_number[0x10];
6260
6261         u8         reserved_at_60[0x20];
6262
6263         u8         table_type[0x8];
6264         u8         reserved_at_88[0x18];
6265
6266         u8         reserved_at_a0[0x8];
6267         u8         table_id[0x18];
6268
6269         u8         group_id[0x20];
6270
6271         u8         reserved_at_e0[0x120];
6272 };
6273
6274 struct mlx5_ifc_destroy_eq_out_bits {
6275         u8         status[0x8];
6276         u8         reserved_at_8[0x18];
6277
6278         u8         syndrome[0x20];
6279
6280         u8         reserved_at_40[0x40];
6281 };
6282
6283 struct mlx5_ifc_destroy_eq_in_bits {
6284         u8         opcode[0x10];
6285         u8         reserved_at_10[0x10];
6286
6287         u8         reserved_at_20[0x10];
6288         u8         op_mod[0x10];
6289
6290         u8         reserved_at_40[0x18];
6291         u8         eq_number[0x8];
6292
6293         u8         reserved_at_60[0x20];
6294 };
6295
6296 struct mlx5_ifc_destroy_dct_out_bits {
6297         u8         status[0x8];
6298         u8         reserved_at_8[0x18];
6299
6300         u8         syndrome[0x20];
6301
6302         u8         reserved_at_40[0x40];
6303 };
6304
6305 struct mlx5_ifc_destroy_dct_in_bits {
6306         u8         opcode[0x10];
6307         u8         reserved_at_10[0x10];
6308
6309         u8         reserved_at_20[0x10];
6310         u8         op_mod[0x10];
6311
6312         u8         reserved_at_40[0x8];
6313         u8         dctn[0x18];
6314
6315         u8         reserved_at_60[0x20];
6316 };
6317
6318 struct mlx5_ifc_destroy_cq_out_bits {
6319         u8         status[0x8];
6320         u8         reserved_at_8[0x18];
6321
6322         u8         syndrome[0x20];
6323
6324         u8         reserved_at_40[0x40];
6325 };
6326
6327 struct mlx5_ifc_destroy_cq_in_bits {
6328         u8         opcode[0x10];
6329         u8         reserved_at_10[0x10];
6330
6331         u8         reserved_at_20[0x10];
6332         u8         op_mod[0x10];
6333
6334         u8         reserved_at_40[0x8];
6335         u8         cqn[0x18];
6336
6337         u8         reserved_at_60[0x20];
6338 };
6339
6340 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6341         u8         status[0x8];
6342         u8         reserved_at_8[0x18];
6343
6344         u8         syndrome[0x20];
6345
6346         u8         reserved_at_40[0x40];
6347 };
6348
6349 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6350         u8         opcode[0x10];
6351         u8         reserved_at_10[0x10];
6352
6353         u8         reserved_at_20[0x10];
6354         u8         op_mod[0x10];
6355
6356         u8         reserved_at_40[0x20];
6357
6358         u8         reserved_at_60[0x10];
6359         u8         vxlan_udp_port[0x10];
6360 };
6361
6362 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6363         u8         status[0x8];
6364         u8         reserved_at_8[0x18];
6365
6366         u8         syndrome[0x20];
6367
6368         u8         reserved_at_40[0x40];
6369 };
6370
6371 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6372         u8         opcode[0x10];
6373         u8         reserved_at_10[0x10];
6374
6375         u8         reserved_at_20[0x10];
6376         u8         op_mod[0x10];
6377
6378         u8         reserved_at_40[0x60];
6379
6380         u8         reserved_at_a0[0x8];
6381         u8         table_index[0x18];
6382
6383         u8         reserved_at_c0[0x140];
6384 };
6385
6386 struct mlx5_ifc_delete_fte_out_bits {
6387         u8         status[0x8];
6388         u8         reserved_at_8[0x18];
6389
6390         u8         syndrome[0x20];
6391
6392         u8         reserved_at_40[0x40];
6393 };
6394
6395 struct mlx5_ifc_delete_fte_in_bits {
6396         u8         opcode[0x10];
6397         u8         reserved_at_10[0x10];
6398
6399         u8         reserved_at_20[0x10];
6400         u8         op_mod[0x10];
6401
6402         u8         other_vport[0x1];
6403         u8         reserved_at_41[0xf];
6404         u8         vport_number[0x10];
6405
6406         u8         reserved_at_60[0x20];
6407
6408         u8         table_type[0x8];
6409         u8         reserved_at_88[0x18];
6410
6411         u8         reserved_at_a0[0x8];
6412         u8         table_id[0x18];
6413
6414         u8         reserved_at_c0[0x40];
6415
6416         u8         flow_index[0x20];
6417
6418         u8         reserved_at_120[0xe0];
6419 };
6420
6421 struct mlx5_ifc_dealloc_xrcd_out_bits {
6422         u8         status[0x8];
6423         u8         reserved_at_8[0x18];
6424
6425         u8         syndrome[0x20];
6426
6427         u8         reserved_at_40[0x40];
6428 };
6429
6430 struct mlx5_ifc_dealloc_xrcd_in_bits {
6431         u8         opcode[0x10];
6432         u8         reserved_at_10[0x10];
6433
6434         u8         reserved_at_20[0x10];
6435         u8         op_mod[0x10];
6436
6437         u8         reserved_at_40[0x8];
6438         u8         xrcd[0x18];
6439
6440         u8         reserved_at_60[0x20];
6441 };
6442
6443 struct mlx5_ifc_dealloc_uar_out_bits {
6444         u8         status[0x8];
6445         u8         reserved_at_8[0x18];
6446
6447         u8         syndrome[0x20];
6448
6449         u8         reserved_at_40[0x40];
6450 };
6451
6452 struct mlx5_ifc_dealloc_uar_in_bits {
6453         u8         opcode[0x10];
6454         u8         reserved_at_10[0x10];
6455
6456         u8         reserved_at_20[0x10];
6457         u8         op_mod[0x10];
6458
6459         u8         reserved_at_40[0x8];
6460         u8         uar[0x18];
6461
6462         u8         reserved_at_60[0x20];
6463 };
6464
6465 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6466         u8         status[0x8];
6467         u8         reserved_at_8[0x18];
6468
6469         u8         syndrome[0x20];
6470
6471         u8         reserved_at_40[0x40];
6472 };
6473
6474 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6475         u8         opcode[0x10];
6476         u8         reserved_at_10[0x10];
6477
6478         u8         reserved_at_20[0x10];
6479         u8         op_mod[0x10];
6480
6481         u8         reserved_at_40[0x8];
6482         u8         transport_domain[0x18];
6483
6484         u8         reserved_at_60[0x20];
6485 };
6486
6487 struct mlx5_ifc_dealloc_q_counter_out_bits {
6488         u8         status[0x8];
6489         u8         reserved_at_8[0x18];
6490
6491         u8         syndrome[0x20];
6492
6493         u8         reserved_at_40[0x40];
6494 };
6495
6496 struct mlx5_ifc_dealloc_q_counter_in_bits {
6497         u8         opcode[0x10];
6498         u8         reserved_at_10[0x10];
6499
6500         u8         reserved_at_20[0x10];
6501         u8         op_mod[0x10];
6502
6503         u8         reserved_at_40[0x18];
6504         u8         counter_set_id[0x8];
6505
6506         u8         reserved_at_60[0x20];
6507 };
6508
6509 struct mlx5_ifc_dealloc_pd_out_bits {
6510         u8         status[0x8];
6511         u8         reserved_at_8[0x18];
6512
6513         u8         syndrome[0x20];
6514
6515         u8         reserved_at_40[0x40];
6516 };
6517
6518 struct mlx5_ifc_dealloc_pd_in_bits {
6519         u8         opcode[0x10];
6520         u8         reserved_at_10[0x10];
6521
6522         u8         reserved_at_20[0x10];
6523         u8         op_mod[0x10];
6524
6525         u8         reserved_at_40[0x8];
6526         u8         pd[0x18];
6527
6528         u8         reserved_at_60[0x20];
6529 };
6530
6531 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x40];
6538 };
6539
6540 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6541         u8         opcode[0x10];
6542         u8         reserved_at_10[0x10];
6543
6544         u8         reserved_at_20[0x10];
6545         u8         op_mod[0x10];
6546
6547         u8         flow_counter_id[0x20];
6548
6549         u8         reserved_at_60[0x20];
6550 };
6551
6552 struct mlx5_ifc_create_xrq_out_bits {
6553         u8         status[0x8];
6554         u8         reserved_at_8[0x18];
6555
6556         u8         syndrome[0x20];
6557
6558         u8         reserved_at_40[0x8];
6559         u8         xrqn[0x18];
6560
6561         u8         reserved_at_60[0x20];
6562 };
6563
6564 struct mlx5_ifc_create_xrq_in_bits {
6565         u8         opcode[0x10];
6566         u8         reserved_at_10[0x10];
6567
6568         u8         reserved_at_20[0x10];
6569         u8         op_mod[0x10];
6570
6571         u8         reserved_at_40[0x40];
6572
6573         struct mlx5_ifc_xrqc_bits xrq_context;
6574 };
6575
6576 struct mlx5_ifc_create_xrc_srq_out_bits {
6577         u8         status[0x8];
6578         u8         reserved_at_8[0x18];
6579
6580         u8         syndrome[0x20];
6581
6582         u8         reserved_at_40[0x8];
6583         u8         xrc_srqn[0x18];
6584
6585         u8         reserved_at_60[0x20];
6586 };
6587
6588 struct mlx5_ifc_create_xrc_srq_in_bits {
6589         u8         opcode[0x10];
6590         u8         reserved_at_10[0x10];
6591
6592         u8         reserved_at_20[0x10];
6593         u8         op_mod[0x10];
6594
6595         u8         reserved_at_40[0x40];
6596
6597         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6598
6599         u8         reserved_at_280[0x600];
6600
6601         u8         pas[0][0x40];
6602 };
6603
6604 struct mlx5_ifc_create_tis_out_bits {
6605         u8         status[0x8];
6606         u8         reserved_at_8[0x18];
6607
6608         u8         syndrome[0x20];
6609
6610         u8         reserved_at_40[0x8];
6611         u8         tisn[0x18];
6612
6613         u8         reserved_at_60[0x20];
6614 };
6615
6616 struct mlx5_ifc_create_tis_in_bits {
6617         u8         opcode[0x10];
6618         u8         reserved_at_10[0x10];
6619
6620         u8         reserved_at_20[0x10];
6621         u8         op_mod[0x10];
6622
6623         u8         reserved_at_40[0xc0];
6624
6625         struct mlx5_ifc_tisc_bits ctx;
6626 };
6627
6628 struct mlx5_ifc_create_tir_out_bits {
6629         u8         status[0x8];
6630         u8         reserved_at_8[0x18];
6631
6632         u8         syndrome[0x20];
6633
6634         u8         reserved_at_40[0x8];
6635         u8         tirn[0x18];
6636
6637         u8         reserved_at_60[0x20];
6638 };
6639
6640 struct mlx5_ifc_create_tir_in_bits {
6641         u8         opcode[0x10];
6642         u8         reserved_at_10[0x10];
6643
6644         u8         reserved_at_20[0x10];
6645         u8         op_mod[0x10];
6646
6647         u8         reserved_at_40[0xc0];
6648
6649         struct mlx5_ifc_tirc_bits ctx;
6650 };
6651
6652 struct mlx5_ifc_create_srq_out_bits {
6653         u8         status[0x8];
6654         u8         reserved_at_8[0x18];
6655
6656         u8         syndrome[0x20];
6657
6658         u8         reserved_at_40[0x8];
6659         u8         srqn[0x18];
6660
6661         u8         reserved_at_60[0x20];
6662 };
6663
6664 struct mlx5_ifc_create_srq_in_bits {
6665         u8         opcode[0x10];
6666         u8         reserved_at_10[0x10];
6667
6668         u8         reserved_at_20[0x10];
6669         u8         op_mod[0x10];
6670
6671         u8         reserved_at_40[0x40];
6672
6673         struct mlx5_ifc_srqc_bits srq_context_entry;
6674
6675         u8         reserved_at_280[0x600];
6676
6677         u8         pas[0][0x40];
6678 };
6679
6680 struct mlx5_ifc_create_sq_out_bits {
6681         u8         status[0x8];
6682         u8         reserved_at_8[0x18];
6683
6684         u8         syndrome[0x20];
6685
6686         u8         reserved_at_40[0x8];
6687         u8         sqn[0x18];
6688
6689         u8         reserved_at_60[0x20];
6690 };
6691
6692 struct mlx5_ifc_create_sq_in_bits {
6693         u8         opcode[0x10];
6694         u8         reserved_at_10[0x10];
6695
6696         u8         reserved_at_20[0x10];
6697         u8         op_mod[0x10];
6698
6699         u8         reserved_at_40[0xc0];
6700
6701         struct mlx5_ifc_sqc_bits ctx;
6702 };
6703
6704 struct mlx5_ifc_create_scheduling_element_out_bits {
6705         u8         status[0x8];
6706         u8         reserved_at_8[0x18];
6707
6708         u8         syndrome[0x20];
6709
6710         u8         reserved_at_40[0x40];
6711
6712         u8         scheduling_element_id[0x20];
6713
6714         u8         reserved_at_a0[0x160];
6715 };
6716
6717 struct mlx5_ifc_create_scheduling_element_in_bits {
6718         u8         opcode[0x10];
6719         u8         reserved_at_10[0x10];
6720
6721         u8         reserved_at_20[0x10];
6722         u8         op_mod[0x10];
6723
6724         u8         scheduling_hierarchy[0x8];
6725         u8         reserved_at_48[0x18];
6726
6727         u8         reserved_at_60[0xa0];
6728
6729         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6730
6731         u8         reserved_at_300[0x100];
6732 };
6733
6734 struct mlx5_ifc_create_rqt_out_bits {
6735         u8         status[0x8];
6736         u8         reserved_at_8[0x18];
6737
6738         u8         syndrome[0x20];
6739
6740         u8         reserved_at_40[0x8];
6741         u8         rqtn[0x18];
6742
6743         u8         reserved_at_60[0x20];
6744 };
6745
6746 struct mlx5_ifc_create_rqt_in_bits {
6747         u8         opcode[0x10];
6748         u8         reserved_at_10[0x10];
6749
6750         u8         reserved_at_20[0x10];
6751         u8         op_mod[0x10];
6752
6753         u8         reserved_at_40[0xc0];
6754
6755         struct mlx5_ifc_rqtc_bits rqt_context;
6756 };
6757
6758 struct mlx5_ifc_create_rq_out_bits {
6759         u8         status[0x8];
6760         u8         reserved_at_8[0x18];
6761
6762         u8         syndrome[0x20];
6763
6764         u8         reserved_at_40[0x8];
6765         u8         rqn[0x18];
6766
6767         u8         reserved_at_60[0x20];
6768 };
6769
6770 struct mlx5_ifc_create_rq_in_bits {
6771         u8         opcode[0x10];
6772         u8         reserved_at_10[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0xc0];
6778
6779         struct mlx5_ifc_rqc_bits ctx;
6780 };
6781
6782 struct mlx5_ifc_create_rmp_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_at_8[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_at_40[0x8];
6789         u8         rmpn[0x18];
6790
6791         u8         reserved_at_60[0x20];
6792 };
6793
6794 struct mlx5_ifc_create_rmp_in_bits {
6795         u8         opcode[0x10];
6796         u8         reserved_at_10[0x10];
6797
6798         u8         reserved_at_20[0x10];
6799         u8         op_mod[0x10];
6800
6801         u8         reserved_at_40[0xc0];
6802
6803         struct mlx5_ifc_rmpc_bits ctx;
6804 };
6805
6806 struct mlx5_ifc_create_qp_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_at_8[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         reserved_at_40[0x8];
6813         u8         qpn[0x18];
6814
6815         u8         reserved_at_60[0x20];
6816 };
6817
6818 struct mlx5_ifc_create_qp_in_bits {
6819         u8         opcode[0x10];
6820         u8         reserved_at_10[0x10];
6821
6822         u8         reserved_at_20[0x10];
6823         u8         op_mod[0x10];
6824
6825         u8         reserved_at_40[0x40];
6826
6827         u8         opt_param_mask[0x20];
6828
6829         u8         reserved_at_a0[0x20];
6830
6831         struct mlx5_ifc_qpc_bits qpc;
6832
6833         u8         reserved_at_800[0x80];
6834
6835         u8         pas[0][0x40];
6836 };
6837
6838 struct mlx5_ifc_create_psv_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_at_8[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_at_40[0x40];
6845
6846         u8         reserved_at_80[0x8];
6847         u8         psv0_index[0x18];
6848
6849         u8         reserved_at_a0[0x8];
6850         u8         psv1_index[0x18];
6851
6852         u8         reserved_at_c0[0x8];
6853         u8         psv2_index[0x18];
6854
6855         u8         reserved_at_e0[0x8];
6856         u8         psv3_index[0x18];
6857 };
6858
6859 struct mlx5_ifc_create_psv_in_bits {
6860         u8         opcode[0x10];
6861         u8         reserved_at_10[0x10];
6862
6863         u8         reserved_at_20[0x10];
6864         u8         op_mod[0x10];
6865
6866         u8         num_psv[0x4];
6867         u8         reserved_at_44[0x4];
6868         u8         pd[0x18];
6869
6870         u8         reserved_at_60[0x20];
6871 };
6872
6873 struct mlx5_ifc_create_mkey_out_bits {
6874         u8         status[0x8];
6875         u8         reserved_at_8[0x18];
6876
6877         u8         syndrome[0x20];
6878
6879         u8         reserved_at_40[0x8];
6880         u8         mkey_index[0x18];
6881
6882         u8         reserved_at_60[0x20];
6883 };
6884
6885 struct mlx5_ifc_create_mkey_in_bits {
6886         u8         opcode[0x10];
6887         u8         reserved_at_10[0x10];
6888
6889         u8         reserved_at_20[0x10];
6890         u8         op_mod[0x10];
6891
6892         u8         reserved_at_40[0x20];
6893
6894         u8         pg_access[0x1];
6895         u8         reserved_at_61[0x1f];
6896
6897         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6898
6899         u8         reserved_at_280[0x80];
6900
6901         u8         translations_octword_actual_size[0x20];
6902
6903         u8         reserved_at_320[0x560];
6904
6905         u8         klm_pas_mtt[0][0x20];
6906 };
6907
6908 struct mlx5_ifc_create_flow_table_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x8];
6915         u8         table_id[0x18];
6916
6917         u8         reserved_at_60[0x20];
6918 };
6919
6920 struct mlx5_ifc_flow_table_context_bits {
6921         u8         encap_en[0x1];
6922         u8         decap_en[0x1];
6923         u8         reserved_at_2[0x2];
6924         u8         table_miss_action[0x4];
6925         u8         level[0x8];
6926         u8         reserved_at_10[0x8];
6927         u8         log_size[0x8];
6928
6929         u8         reserved_at_20[0x8];
6930         u8         table_miss_id[0x18];
6931
6932         u8         reserved_at_40[0x8];
6933         u8         lag_master_next_table_id[0x18];
6934
6935         u8         reserved_at_60[0xe0];
6936 };
6937
6938 struct mlx5_ifc_create_flow_table_in_bits {
6939         u8         opcode[0x10];
6940         u8         reserved_at_10[0x10];
6941
6942         u8         reserved_at_20[0x10];
6943         u8         op_mod[0x10];
6944
6945         u8         other_vport[0x1];
6946         u8         reserved_at_41[0xf];
6947         u8         vport_number[0x10];
6948
6949         u8         reserved_at_60[0x20];
6950
6951         u8         table_type[0x8];
6952         u8         reserved_at_88[0x18];
6953
6954         u8         reserved_at_a0[0x20];
6955
6956         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6957 };
6958
6959 struct mlx5_ifc_create_flow_group_out_bits {
6960         u8         status[0x8];
6961         u8         reserved_at_8[0x18];
6962
6963         u8         syndrome[0x20];
6964
6965         u8         reserved_at_40[0x8];
6966         u8         group_id[0x18];
6967
6968         u8         reserved_at_60[0x20];
6969 };
6970
6971 enum {
6972         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6973         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6974         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6975 };
6976
6977 struct mlx5_ifc_create_flow_group_in_bits {
6978         u8         opcode[0x10];
6979         u8         reserved_at_10[0x10];
6980
6981         u8         reserved_at_20[0x10];
6982         u8         op_mod[0x10];
6983
6984         u8         other_vport[0x1];
6985         u8         reserved_at_41[0xf];
6986         u8         vport_number[0x10];
6987
6988         u8         reserved_at_60[0x20];
6989
6990         u8         table_type[0x8];
6991         u8         reserved_at_88[0x18];
6992
6993         u8         reserved_at_a0[0x8];
6994         u8         table_id[0x18];
6995
6996         u8         reserved_at_c0[0x20];
6997
6998         u8         start_flow_index[0x20];
6999
7000         u8         reserved_at_100[0x20];
7001
7002         u8         end_flow_index[0x20];
7003
7004         u8         reserved_at_140[0xa0];
7005
7006         u8         reserved_at_1e0[0x18];
7007         u8         match_criteria_enable[0x8];
7008
7009         struct mlx5_ifc_fte_match_param_bits match_criteria;
7010
7011         u8         reserved_at_1200[0xe00];
7012 };
7013
7014 struct mlx5_ifc_create_eq_out_bits {
7015         u8         status[0x8];
7016         u8         reserved_at_8[0x18];
7017
7018         u8         syndrome[0x20];
7019
7020         u8         reserved_at_40[0x18];
7021         u8         eq_number[0x8];
7022
7023         u8         reserved_at_60[0x20];
7024 };
7025
7026 struct mlx5_ifc_create_eq_in_bits {
7027         u8         opcode[0x10];
7028         u8         reserved_at_10[0x10];
7029
7030         u8         reserved_at_20[0x10];
7031         u8         op_mod[0x10];
7032
7033         u8         reserved_at_40[0x40];
7034
7035         struct mlx5_ifc_eqc_bits eq_context_entry;
7036
7037         u8         reserved_at_280[0x40];
7038
7039         u8         event_bitmask[0x40];
7040
7041         u8         reserved_at_300[0x580];
7042
7043         u8         pas[0][0x40];
7044 };
7045
7046 struct mlx5_ifc_create_dct_out_bits {
7047         u8         status[0x8];
7048         u8         reserved_at_8[0x18];
7049
7050         u8         syndrome[0x20];
7051
7052         u8         reserved_at_40[0x8];
7053         u8         dctn[0x18];
7054
7055         u8         reserved_at_60[0x20];
7056 };
7057
7058 struct mlx5_ifc_create_dct_in_bits {
7059         u8         opcode[0x10];
7060         u8         reserved_at_10[0x10];
7061
7062         u8         reserved_at_20[0x10];
7063         u8         op_mod[0x10];
7064
7065         u8         reserved_at_40[0x40];
7066
7067         struct mlx5_ifc_dctc_bits dct_context_entry;
7068
7069         u8         reserved_at_280[0x180];
7070 };
7071
7072 struct mlx5_ifc_create_cq_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         cqn[0x18];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 struct mlx5_ifc_create_cq_in_bits {
7085         u8         opcode[0x10];
7086         u8         reserved_at_10[0x10];
7087
7088         u8         reserved_at_20[0x10];
7089         u8         op_mod[0x10];
7090
7091         u8         reserved_at_40[0x40];
7092
7093         struct mlx5_ifc_cqc_bits cq_context;
7094
7095         u8         reserved_at_280[0x600];
7096
7097         u8         pas[0][0x40];
7098 };
7099
7100 struct mlx5_ifc_config_int_moderation_out_bits {
7101         u8         status[0x8];
7102         u8         reserved_at_8[0x18];
7103
7104         u8         syndrome[0x20];
7105
7106         u8         reserved_at_40[0x4];
7107         u8         min_delay[0xc];
7108         u8         int_vector[0x10];
7109
7110         u8         reserved_at_60[0x20];
7111 };
7112
7113 enum {
7114         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7115         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7116 };
7117
7118 struct mlx5_ifc_config_int_moderation_in_bits {
7119         u8         opcode[0x10];
7120         u8         reserved_at_10[0x10];
7121
7122         u8         reserved_at_20[0x10];
7123         u8         op_mod[0x10];
7124
7125         u8         reserved_at_40[0x4];
7126         u8         min_delay[0xc];
7127         u8         int_vector[0x10];
7128
7129         u8         reserved_at_60[0x20];
7130 };
7131
7132 struct mlx5_ifc_attach_to_mcg_out_bits {
7133         u8         status[0x8];
7134         u8         reserved_at_8[0x18];
7135
7136         u8         syndrome[0x20];
7137
7138         u8         reserved_at_40[0x40];
7139 };
7140
7141 struct mlx5_ifc_attach_to_mcg_in_bits {
7142         u8         opcode[0x10];
7143         u8         reserved_at_10[0x10];
7144
7145         u8         reserved_at_20[0x10];
7146         u8         op_mod[0x10];
7147
7148         u8         reserved_at_40[0x8];
7149         u8         qpn[0x18];
7150
7151         u8         reserved_at_60[0x20];
7152
7153         u8         multicast_gid[16][0x8];
7154 };
7155
7156 struct mlx5_ifc_arm_xrq_out_bits {
7157         u8         status[0x8];
7158         u8         reserved_at_8[0x18];
7159
7160         u8         syndrome[0x20];
7161
7162         u8         reserved_at_40[0x40];
7163 };
7164
7165 struct mlx5_ifc_arm_xrq_in_bits {
7166         u8         opcode[0x10];
7167         u8         reserved_at_10[0x10];
7168
7169         u8         reserved_at_20[0x10];
7170         u8         op_mod[0x10];
7171
7172         u8         reserved_at_40[0x8];
7173         u8         xrqn[0x18];
7174
7175         u8         reserved_at_60[0x10];
7176         u8         lwm[0x10];
7177 };
7178
7179 struct mlx5_ifc_arm_xrc_srq_out_bits {
7180         u8         status[0x8];
7181         u8         reserved_at_8[0x18];
7182
7183         u8         syndrome[0x20];
7184
7185         u8         reserved_at_40[0x40];
7186 };
7187
7188 enum {
7189         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7190 };
7191
7192 struct mlx5_ifc_arm_xrc_srq_in_bits {
7193         u8         opcode[0x10];
7194         u8         reserved_at_10[0x10];
7195
7196         u8         reserved_at_20[0x10];
7197         u8         op_mod[0x10];
7198
7199         u8         reserved_at_40[0x8];
7200         u8         xrc_srqn[0x18];
7201
7202         u8         reserved_at_60[0x10];
7203         u8         lwm[0x10];
7204 };
7205
7206 struct mlx5_ifc_arm_rq_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_at_8[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_at_40[0x40];
7213 };
7214
7215 enum {
7216         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7217         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7218 };
7219
7220 struct mlx5_ifc_arm_rq_in_bits {
7221         u8         opcode[0x10];
7222         u8         reserved_at_10[0x10];
7223
7224         u8         reserved_at_20[0x10];
7225         u8         op_mod[0x10];
7226
7227         u8         reserved_at_40[0x8];
7228         u8         srq_number[0x18];
7229
7230         u8         reserved_at_60[0x10];
7231         u8         lwm[0x10];
7232 };
7233
7234 struct mlx5_ifc_arm_dct_out_bits {
7235         u8         status[0x8];
7236         u8         reserved_at_8[0x18];
7237
7238         u8         syndrome[0x20];
7239
7240         u8         reserved_at_40[0x40];
7241 };
7242
7243 struct mlx5_ifc_arm_dct_in_bits {
7244         u8         opcode[0x10];
7245         u8         reserved_at_10[0x10];
7246
7247         u8         reserved_at_20[0x10];
7248         u8         op_mod[0x10];
7249
7250         u8         reserved_at_40[0x8];
7251         u8         dct_number[0x18];
7252
7253         u8         reserved_at_60[0x20];
7254 };
7255
7256 struct mlx5_ifc_alloc_xrcd_out_bits {
7257         u8         status[0x8];
7258         u8         reserved_at_8[0x18];
7259
7260         u8         syndrome[0x20];
7261
7262         u8         reserved_at_40[0x8];
7263         u8         xrcd[0x18];
7264
7265         u8         reserved_at_60[0x20];
7266 };
7267
7268 struct mlx5_ifc_alloc_xrcd_in_bits {
7269         u8         opcode[0x10];
7270         u8         reserved_at_10[0x10];
7271
7272         u8         reserved_at_20[0x10];
7273         u8         op_mod[0x10];
7274
7275         u8         reserved_at_40[0x40];
7276 };
7277
7278 struct mlx5_ifc_alloc_uar_out_bits {
7279         u8         status[0x8];
7280         u8         reserved_at_8[0x18];
7281
7282         u8         syndrome[0x20];
7283
7284         u8         reserved_at_40[0x8];
7285         u8         uar[0x18];
7286
7287         u8         reserved_at_60[0x20];
7288 };
7289
7290 struct mlx5_ifc_alloc_uar_in_bits {
7291         u8         opcode[0x10];
7292         u8         reserved_at_10[0x10];
7293
7294         u8         reserved_at_20[0x10];
7295         u8         op_mod[0x10];
7296
7297         u8         reserved_at_40[0x40];
7298 };
7299
7300 struct mlx5_ifc_alloc_transport_domain_out_bits {
7301         u8         status[0x8];
7302         u8         reserved_at_8[0x18];
7303
7304         u8         syndrome[0x20];
7305
7306         u8         reserved_at_40[0x8];
7307         u8         transport_domain[0x18];
7308
7309         u8         reserved_at_60[0x20];
7310 };
7311
7312 struct mlx5_ifc_alloc_transport_domain_in_bits {
7313         u8         opcode[0x10];
7314         u8         reserved_at_10[0x10];
7315
7316         u8         reserved_at_20[0x10];
7317         u8         op_mod[0x10];
7318
7319         u8         reserved_at_40[0x40];
7320 };
7321
7322 struct mlx5_ifc_alloc_q_counter_out_bits {
7323         u8         status[0x8];
7324         u8         reserved_at_8[0x18];
7325
7326         u8         syndrome[0x20];
7327
7328         u8         reserved_at_40[0x18];
7329         u8         counter_set_id[0x8];
7330
7331         u8         reserved_at_60[0x20];
7332 };
7333
7334 struct mlx5_ifc_alloc_q_counter_in_bits {
7335         u8         opcode[0x10];
7336         u8         reserved_at_10[0x10];
7337
7338         u8         reserved_at_20[0x10];
7339         u8         op_mod[0x10];
7340
7341         u8         reserved_at_40[0x40];
7342 };
7343
7344 struct mlx5_ifc_alloc_pd_out_bits {
7345         u8         status[0x8];
7346         u8         reserved_at_8[0x18];
7347
7348         u8         syndrome[0x20];
7349
7350         u8         reserved_at_40[0x8];
7351         u8         pd[0x18];
7352
7353         u8         reserved_at_60[0x20];
7354 };
7355
7356 struct mlx5_ifc_alloc_pd_in_bits {
7357         u8         opcode[0x10];
7358         u8         reserved_at_10[0x10];
7359
7360         u8         reserved_at_20[0x10];
7361         u8         op_mod[0x10];
7362
7363         u8         reserved_at_40[0x40];
7364 };
7365
7366 struct mlx5_ifc_alloc_flow_counter_out_bits {
7367         u8         status[0x8];
7368         u8         reserved_at_8[0x18];
7369
7370         u8         syndrome[0x20];
7371
7372         u8         flow_counter_id[0x20];
7373
7374         u8         reserved_at_60[0x20];
7375 };
7376
7377 struct mlx5_ifc_alloc_flow_counter_in_bits {
7378         u8         opcode[0x10];
7379         u8         reserved_at_10[0x10];
7380
7381         u8         reserved_at_20[0x10];
7382         u8         op_mod[0x10];
7383
7384         u8         reserved_at_40[0x40];
7385 };
7386
7387 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7388         u8         status[0x8];
7389         u8         reserved_at_8[0x18];
7390
7391         u8         syndrome[0x20];
7392
7393         u8         reserved_at_40[0x40];
7394 };
7395
7396 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7397         u8         opcode[0x10];
7398         u8         reserved_at_10[0x10];
7399
7400         u8         reserved_at_20[0x10];
7401         u8         op_mod[0x10];
7402
7403         u8         reserved_at_40[0x20];
7404
7405         u8         reserved_at_60[0x10];
7406         u8         vxlan_udp_port[0x10];
7407 };
7408
7409 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7410         u8         status[0x8];
7411         u8         reserved_at_8[0x18];
7412
7413         u8         syndrome[0x20];
7414
7415         u8         reserved_at_40[0x40];
7416 };
7417
7418 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7419         u8         opcode[0x10];
7420         u8         reserved_at_10[0x10];
7421
7422         u8         reserved_at_20[0x10];
7423         u8         op_mod[0x10];
7424
7425         u8         reserved_at_40[0x10];
7426         u8         rate_limit_index[0x10];
7427
7428         u8         reserved_at_60[0x20];
7429
7430         u8         rate_limit[0x20];
7431
7432         u8         burst_upper_bound[0x20];
7433
7434         u8         reserved_at_c0[0x10];
7435         u8         typical_packet_size[0x10];
7436
7437         u8         reserved_at_e0[0x120];
7438 };
7439
7440 struct mlx5_ifc_access_register_out_bits {
7441         u8         status[0x8];
7442         u8         reserved_at_8[0x18];
7443
7444         u8         syndrome[0x20];
7445
7446         u8         reserved_at_40[0x40];
7447
7448         u8         register_data[0][0x20];
7449 };
7450
7451 enum {
7452         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7453         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7454 };
7455
7456 struct mlx5_ifc_access_register_in_bits {
7457         u8         opcode[0x10];
7458         u8         reserved_at_10[0x10];
7459
7460         u8         reserved_at_20[0x10];
7461         u8         op_mod[0x10];
7462
7463         u8         reserved_at_40[0x10];
7464         u8         register_id[0x10];
7465
7466         u8         argument[0x20];
7467
7468         u8         register_data[0][0x20];
7469 };
7470
7471 struct mlx5_ifc_sltp_reg_bits {
7472         u8         status[0x4];
7473         u8         version[0x4];
7474         u8         local_port[0x8];
7475         u8         pnat[0x2];
7476         u8         reserved_at_12[0x2];
7477         u8         lane[0x4];
7478         u8         reserved_at_18[0x8];
7479
7480         u8         reserved_at_20[0x20];
7481
7482         u8         reserved_at_40[0x7];
7483         u8         polarity[0x1];
7484         u8         ob_tap0[0x8];
7485         u8         ob_tap1[0x8];
7486         u8         ob_tap2[0x8];
7487
7488         u8         reserved_at_60[0xc];
7489         u8         ob_preemp_mode[0x4];
7490         u8         ob_reg[0x8];
7491         u8         ob_bias[0x8];
7492
7493         u8         reserved_at_80[0x20];
7494 };
7495
7496 struct mlx5_ifc_slrg_reg_bits {
7497         u8         status[0x4];
7498         u8         version[0x4];
7499         u8         local_port[0x8];
7500         u8         pnat[0x2];
7501         u8         reserved_at_12[0x2];
7502         u8         lane[0x4];
7503         u8         reserved_at_18[0x8];
7504
7505         u8         time_to_link_up[0x10];
7506         u8         reserved_at_30[0xc];
7507         u8         grade_lane_speed[0x4];
7508
7509         u8         grade_version[0x8];
7510         u8         grade[0x18];
7511
7512         u8         reserved_at_60[0x4];
7513         u8         height_grade_type[0x4];
7514         u8         height_grade[0x18];
7515
7516         u8         height_dz[0x10];
7517         u8         height_dv[0x10];
7518
7519         u8         reserved_at_a0[0x10];
7520         u8         height_sigma[0x10];
7521
7522         u8         reserved_at_c0[0x20];
7523
7524         u8         reserved_at_e0[0x4];
7525         u8         phase_grade_type[0x4];
7526         u8         phase_grade[0x18];
7527
7528         u8         reserved_at_100[0x8];
7529         u8         phase_eo_pos[0x8];
7530         u8         reserved_at_110[0x8];
7531         u8         phase_eo_neg[0x8];
7532
7533         u8         ffe_set_tested[0x10];
7534         u8         test_errors_per_lane[0x10];
7535 };
7536
7537 struct mlx5_ifc_pvlc_reg_bits {
7538         u8         reserved_at_0[0x8];
7539         u8         local_port[0x8];
7540         u8         reserved_at_10[0x10];
7541
7542         u8         reserved_at_20[0x1c];
7543         u8         vl_hw_cap[0x4];
7544
7545         u8         reserved_at_40[0x1c];
7546         u8         vl_admin[0x4];
7547
7548         u8         reserved_at_60[0x1c];
7549         u8         vl_operational[0x4];
7550 };
7551
7552 struct mlx5_ifc_pude_reg_bits {
7553         u8         swid[0x8];
7554         u8         local_port[0x8];
7555         u8         reserved_at_10[0x4];
7556         u8         admin_status[0x4];
7557         u8         reserved_at_18[0x4];
7558         u8         oper_status[0x4];
7559
7560         u8         reserved_at_20[0x60];
7561 };
7562
7563 struct mlx5_ifc_ptys_reg_bits {
7564         u8         reserved_at_0[0x1];
7565         u8         an_disable_admin[0x1];
7566         u8         an_disable_cap[0x1];
7567         u8         reserved_at_3[0x5];
7568         u8         local_port[0x8];
7569         u8         reserved_at_10[0xd];
7570         u8         proto_mask[0x3];
7571
7572         u8         an_status[0x4];
7573         u8         reserved_at_24[0x3c];
7574
7575         u8         eth_proto_capability[0x20];
7576
7577         u8         ib_link_width_capability[0x10];
7578         u8         ib_proto_capability[0x10];
7579
7580         u8         reserved_at_a0[0x20];
7581
7582         u8         eth_proto_admin[0x20];
7583
7584         u8         ib_link_width_admin[0x10];
7585         u8         ib_proto_admin[0x10];
7586
7587         u8         reserved_at_100[0x20];
7588
7589         u8         eth_proto_oper[0x20];
7590
7591         u8         ib_link_width_oper[0x10];
7592         u8         ib_proto_oper[0x10];
7593
7594         u8         reserved_at_160[0x1c];
7595         u8         connector_type[0x4];
7596
7597         u8         eth_proto_lp_advertise[0x20];
7598
7599         u8         reserved_at_1a0[0x60];
7600 };
7601
7602 struct mlx5_ifc_mlcr_reg_bits {
7603         u8         reserved_at_0[0x8];
7604         u8         local_port[0x8];
7605         u8         reserved_at_10[0x20];
7606
7607         u8         beacon_duration[0x10];
7608         u8         reserved_at_40[0x10];
7609
7610         u8         beacon_remain[0x10];
7611 };
7612
7613 struct mlx5_ifc_ptas_reg_bits {
7614         u8         reserved_at_0[0x20];
7615
7616         u8         algorithm_options[0x10];
7617         u8         reserved_at_30[0x4];
7618         u8         repetitions_mode[0x4];
7619         u8         num_of_repetitions[0x8];
7620
7621         u8         grade_version[0x8];
7622         u8         height_grade_type[0x4];
7623         u8         phase_grade_type[0x4];
7624         u8         height_grade_weight[0x8];
7625         u8         phase_grade_weight[0x8];
7626
7627         u8         gisim_measure_bits[0x10];
7628         u8         adaptive_tap_measure_bits[0x10];
7629
7630         u8         ber_bath_high_error_threshold[0x10];
7631         u8         ber_bath_mid_error_threshold[0x10];
7632
7633         u8         ber_bath_low_error_threshold[0x10];
7634         u8         one_ratio_high_threshold[0x10];
7635
7636         u8         one_ratio_high_mid_threshold[0x10];
7637         u8         one_ratio_low_mid_threshold[0x10];
7638
7639         u8         one_ratio_low_threshold[0x10];
7640         u8         ndeo_error_threshold[0x10];
7641
7642         u8         mixer_offset_step_size[0x10];
7643         u8         reserved_at_110[0x8];
7644         u8         mix90_phase_for_voltage_bath[0x8];
7645
7646         u8         mixer_offset_start[0x10];
7647         u8         mixer_offset_end[0x10];
7648
7649         u8         reserved_at_140[0x15];
7650         u8         ber_test_time[0xb];
7651 };
7652
7653 struct mlx5_ifc_pspa_reg_bits {
7654         u8         swid[0x8];
7655         u8         local_port[0x8];
7656         u8         sub_port[0x8];
7657         u8         reserved_at_18[0x8];
7658
7659         u8         reserved_at_20[0x20];
7660 };
7661
7662 struct mlx5_ifc_pqdr_reg_bits {
7663         u8         reserved_at_0[0x8];
7664         u8         local_port[0x8];
7665         u8         reserved_at_10[0x5];
7666         u8         prio[0x3];
7667         u8         reserved_at_18[0x6];
7668         u8         mode[0x2];
7669
7670         u8         reserved_at_20[0x20];
7671
7672         u8         reserved_at_40[0x10];
7673         u8         min_threshold[0x10];
7674
7675         u8         reserved_at_60[0x10];
7676         u8         max_threshold[0x10];
7677
7678         u8         reserved_at_80[0x10];
7679         u8         mark_probability_denominator[0x10];
7680
7681         u8         reserved_at_a0[0x60];
7682 };
7683
7684 struct mlx5_ifc_ppsc_reg_bits {
7685         u8         reserved_at_0[0x8];
7686         u8         local_port[0x8];
7687         u8         reserved_at_10[0x10];
7688
7689         u8         reserved_at_20[0x60];
7690
7691         u8         reserved_at_80[0x1c];
7692         u8         wrps_admin[0x4];
7693
7694         u8         reserved_at_a0[0x1c];
7695         u8         wrps_status[0x4];
7696
7697         u8         reserved_at_c0[0x8];
7698         u8         up_threshold[0x8];
7699         u8         reserved_at_d0[0x8];
7700         u8         down_threshold[0x8];
7701
7702         u8         reserved_at_e0[0x20];
7703
7704         u8         reserved_at_100[0x1c];
7705         u8         srps_admin[0x4];
7706
7707         u8         reserved_at_120[0x1c];
7708         u8         srps_status[0x4];
7709
7710         u8         reserved_at_140[0x40];
7711 };
7712
7713 struct mlx5_ifc_pplr_reg_bits {
7714         u8         reserved_at_0[0x8];
7715         u8         local_port[0x8];
7716         u8         reserved_at_10[0x10];
7717
7718         u8         reserved_at_20[0x8];
7719         u8         lb_cap[0x8];
7720         u8         reserved_at_30[0x8];
7721         u8         lb_en[0x8];
7722 };
7723
7724 struct mlx5_ifc_pplm_reg_bits {
7725         u8         reserved_at_0[0x8];
7726         u8         local_port[0x8];
7727         u8         reserved_at_10[0x10];
7728
7729         u8         reserved_at_20[0x20];
7730
7731         u8         port_profile_mode[0x8];
7732         u8         static_port_profile[0x8];
7733         u8         active_port_profile[0x8];
7734         u8         reserved_at_58[0x8];
7735
7736         u8         retransmission_active[0x8];
7737         u8         fec_mode_active[0x18];
7738
7739         u8         reserved_at_80[0x20];
7740 };
7741
7742 struct mlx5_ifc_ppcnt_reg_bits {
7743         u8         swid[0x8];
7744         u8         local_port[0x8];
7745         u8         pnat[0x2];
7746         u8         reserved_at_12[0x8];
7747         u8         grp[0x6];
7748
7749         u8         clr[0x1];
7750         u8         reserved_at_21[0x1c];
7751         u8         prio_tc[0x3];
7752
7753         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7754 };
7755
7756 struct mlx5_ifc_mpcnt_reg_bits {
7757         u8         reserved_at_0[0x8];
7758         u8         pcie_index[0x8];
7759         u8         reserved_at_10[0xa];
7760         u8         grp[0x6];
7761
7762         u8         clr[0x1];
7763         u8         reserved_at_21[0x1f];
7764
7765         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7766 };
7767
7768 struct mlx5_ifc_ppad_reg_bits {
7769         u8         reserved_at_0[0x3];
7770         u8         single_mac[0x1];
7771         u8         reserved_at_4[0x4];
7772         u8         local_port[0x8];
7773         u8         mac_47_32[0x10];
7774
7775         u8         mac_31_0[0x20];
7776
7777         u8         reserved_at_40[0x40];
7778 };
7779
7780 struct mlx5_ifc_pmtu_reg_bits {
7781         u8         reserved_at_0[0x8];
7782         u8         local_port[0x8];
7783         u8         reserved_at_10[0x10];
7784
7785         u8         max_mtu[0x10];
7786         u8         reserved_at_30[0x10];
7787
7788         u8         admin_mtu[0x10];
7789         u8         reserved_at_50[0x10];
7790
7791         u8         oper_mtu[0x10];
7792         u8         reserved_at_70[0x10];
7793 };
7794
7795 struct mlx5_ifc_pmpr_reg_bits {
7796         u8         reserved_at_0[0x8];
7797         u8         module[0x8];
7798         u8         reserved_at_10[0x10];
7799
7800         u8         reserved_at_20[0x18];
7801         u8         attenuation_5g[0x8];
7802
7803         u8         reserved_at_40[0x18];
7804         u8         attenuation_7g[0x8];
7805
7806         u8         reserved_at_60[0x18];
7807         u8         attenuation_12g[0x8];
7808 };
7809
7810 struct mlx5_ifc_pmpe_reg_bits {
7811         u8         reserved_at_0[0x8];
7812         u8         module[0x8];
7813         u8         reserved_at_10[0xc];
7814         u8         module_status[0x4];
7815
7816         u8         reserved_at_20[0x60];
7817 };
7818
7819 struct mlx5_ifc_pmpc_reg_bits {
7820         u8         module_state_updated[32][0x8];
7821 };
7822
7823 struct mlx5_ifc_pmlpn_reg_bits {
7824         u8         reserved_at_0[0x4];
7825         u8         mlpn_status[0x4];
7826         u8         local_port[0x8];
7827         u8         reserved_at_10[0x10];
7828
7829         u8         e[0x1];
7830         u8         reserved_at_21[0x1f];
7831 };
7832
7833 struct mlx5_ifc_pmlp_reg_bits {
7834         u8         rxtx[0x1];
7835         u8         reserved_at_1[0x7];
7836         u8         local_port[0x8];
7837         u8         reserved_at_10[0x8];
7838         u8         width[0x8];
7839
7840         u8         lane0_module_mapping[0x20];
7841
7842         u8         lane1_module_mapping[0x20];
7843
7844         u8         lane2_module_mapping[0x20];
7845
7846         u8         lane3_module_mapping[0x20];
7847
7848         u8         reserved_at_a0[0x160];
7849 };
7850
7851 struct mlx5_ifc_pmaos_reg_bits {
7852         u8         reserved_at_0[0x8];
7853         u8         module[0x8];
7854         u8         reserved_at_10[0x4];
7855         u8         admin_status[0x4];
7856         u8         reserved_at_18[0x4];
7857         u8         oper_status[0x4];
7858
7859         u8         ase[0x1];
7860         u8         ee[0x1];
7861         u8         reserved_at_22[0x1c];
7862         u8         e[0x2];
7863
7864         u8         reserved_at_40[0x40];
7865 };
7866
7867 struct mlx5_ifc_plpc_reg_bits {
7868         u8         reserved_at_0[0x4];
7869         u8         profile_id[0xc];
7870         u8         reserved_at_10[0x4];
7871         u8         proto_mask[0x4];
7872         u8         reserved_at_18[0x8];
7873
7874         u8         reserved_at_20[0x10];
7875         u8         lane_speed[0x10];
7876
7877         u8         reserved_at_40[0x17];
7878         u8         lpbf[0x1];
7879         u8         fec_mode_policy[0x8];
7880
7881         u8         retransmission_capability[0x8];
7882         u8         fec_mode_capability[0x18];
7883
7884         u8         retransmission_support_admin[0x8];
7885         u8         fec_mode_support_admin[0x18];
7886
7887         u8         retransmission_request_admin[0x8];
7888         u8         fec_mode_request_admin[0x18];
7889
7890         u8         reserved_at_c0[0x80];
7891 };
7892
7893 struct mlx5_ifc_plib_reg_bits {
7894         u8         reserved_at_0[0x8];
7895         u8         local_port[0x8];
7896         u8         reserved_at_10[0x8];
7897         u8         ib_port[0x8];
7898
7899         u8         reserved_at_20[0x60];
7900 };
7901
7902 struct mlx5_ifc_plbf_reg_bits {
7903         u8         reserved_at_0[0x8];
7904         u8         local_port[0x8];
7905         u8         reserved_at_10[0xd];
7906         u8         lbf_mode[0x3];
7907
7908         u8         reserved_at_20[0x20];
7909 };
7910
7911 struct mlx5_ifc_pipg_reg_bits {
7912         u8         reserved_at_0[0x8];
7913         u8         local_port[0x8];
7914         u8         reserved_at_10[0x10];
7915
7916         u8         dic[0x1];
7917         u8         reserved_at_21[0x19];
7918         u8         ipg[0x4];
7919         u8         reserved_at_3e[0x2];
7920 };
7921
7922 struct mlx5_ifc_pifr_reg_bits {
7923         u8         reserved_at_0[0x8];
7924         u8         local_port[0x8];
7925         u8         reserved_at_10[0x10];
7926
7927         u8         reserved_at_20[0xe0];
7928
7929         u8         port_filter[8][0x20];
7930
7931         u8         port_filter_update_en[8][0x20];
7932 };
7933
7934 struct mlx5_ifc_pfcc_reg_bits {
7935         u8         reserved_at_0[0x8];
7936         u8         local_port[0x8];
7937         u8         reserved_at_10[0xb];
7938         u8         ppan_mask_n[0x1];
7939         u8         minor_stall_mask[0x1];
7940         u8         critical_stall_mask[0x1];
7941         u8         reserved_at_1e[0x2];
7942
7943         u8         ppan[0x4];
7944         u8         reserved_at_24[0x4];
7945         u8         prio_mask_tx[0x8];
7946         u8         reserved_at_30[0x8];
7947         u8         prio_mask_rx[0x8];
7948
7949         u8         pptx[0x1];
7950         u8         aptx[0x1];
7951         u8         pptx_mask_n[0x1];
7952         u8         reserved_at_43[0x5];
7953         u8         pfctx[0x8];
7954         u8         reserved_at_50[0x10];
7955
7956         u8         pprx[0x1];
7957         u8         aprx[0x1];
7958         u8         pprx_mask_n[0x1];
7959         u8         reserved_at_63[0x5];
7960         u8         pfcrx[0x8];
7961         u8         reserved_at_70[0x10];
7962
7963         u8         device_stall_minor_watermark[0x10];
7964         u8         device_stall_critical_watermark[0x10];
7965
7966         u8         reserved_at_a0[0x60];
7967 };
7968
7969 struct mlx5_ifc_pelc_reg_bits {
7970         u8         op[0x4];
7971         u8         reserved_at_4[0x4];
7972         u8         local_port[0x8];
7973         u8         reserved_at_10[0x10];
7974
7975         u8         op_admin[0x8];
7976         u8         op_capability[0x8];
7977         u8         op_request[0x8];
7978         u8         op_active[0x8];
7979
7980         u8         admin[0x40];
7981
7982         u8         capability[0x40];
7983
7984         u8         request[0x40];
7985
7986         u8         active[0x40];
7987
7988         u8         reserved_at_140[0x80];
7989 };
7990
7991 struct mlx5_ifc_peir_reg_bits {
7992         u8         reserved_at_0[0x8];
7993         u8         local_port[0x8];
7994         u8         reserved_at_10[0x10];
7995
7996         u8         reserved_at_20[0xc];
7997         u8         error_count[0x4];
7998         u8         reserved_at_30[0x10];
7999
8000         u8         reserved_at_40[0xc];
8001         u8         lane[0x4];
8002         u8         reserved_at_50[0x8];
8003         u8         error_type[0x8];
8004 };
8005
8006 struct mlx5_ifc_pcam_enhanced_features_bits {
8007         u8         reserved_at_0[0x76];
8008
8009         u8         pfcc_mask[0x1];
8010         u8         reserved_at_77[0x4];
8011         u8         rx_buffer_fullness_counters[0x1];
8012         u8         ptys_connector_type[0x1];
8013         u8         reserved_at_7d[0x1];
8014         u8         ppcnt_discard_group[0x1];
8015         u8         ppcnt_statistical_group[0x1];
8016 };
8017
8018 struct mlx5_ifc_pcam_reg_bits {
8019         u8         reserved_at_0[0x8];
8020         u8         feature_group[0x8];
8021         u8         reserved_at_10[0x8];
8022         u8         access_reg_group[0x8];
8023
8024         u8         reserved_at_20[0x20];
8025
8026         union {
8027                 u8         reserved_at_0[0x80];
8028         } port_access_reg_cap_mask;
8029
8030         u8         reserved_at_c0[0x80];
8031
8032         union {
8033                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8034                 u8         reserved_at_0[0x80];
8035         } feature_cap_mask;
8036
8037         u8         reserved_at_1c0[0xc0];
8038 };
8039
8040 struct mlx5_ifc_mcam_enhanced_features_bits {
8041         u8         reserved_at_0[0x7b];
8042         u8         pcie_outbound_stalled[0x1];
8043         u8         tx_overflow_buffer_pkt[0x1];
8044         u8         mtpps_enh_out_per_adj[0x1];
8045         u8         mtpps_fs[0x1];
8046         u8         pcie_performance_group[0x1];
8047 };
8048
8049 struct mlx5_ifc_mcam_access_reg_bits {
8050         u8         reserved_at_0[0x1c];
8051         u8         mcda[0x1];
8052         u8         mcc[0x1];
8053         u8         mcqi[0x1];
8054         u8         reserved_at_1f[0x1];
8055
8056         u8         regs_95_to_64[0x20];
8057         u8         regs_63_to_32[0x20];
8058         u8         regs_31_to_0[0x20];
8059 };
8060
8061 struct mlx5_ifc_mcam_reg_bits {
8062         u8         reserved_at_0[0x8];
8063         u8         feature_group[0x8];
8064         u8         reserved_at_10[0x8];
8065         u8         access_reg_group[0x8];
8066
8067         u8         reserved_at_20[0x20];
8068
8069         union {
8070                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8071                 u8         reserved_at_0[0x80];
8072         } mng_access_reg_cap_mask;
8073
8074         u8         reserved_at_c0[0x80];
8075
8076         union {
8077                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8078                 u8         reserved_at_0[0x80];
8079         } mng_feature_cap_mask;
8080
8081         u8         reserved_at_1c0[0x80];
8082 };
8083
8084 struct mlx5_ifc_qcam_access_reg_cap_mask {
8085         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8086         u8         qpdpm[0x1];
8087         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8088         u8         qdpm[0x1];
8089         u8         qpts[0x1];
8090         u8         qcap[0x1];
8091         u8         qcam_access_reg_cap_mask_0[0x1];
8092 };
8093
8094 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8095         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8096         u8         qpts_trust_both[0x1];
8097 };
8098
8099 struct mlx5_ifc_qcam_reg_bits {
8100         u8         reserved_at_0[0x8];
8101         u8         feature_group[0x8];
8102         u8         reserved_at_10[0x8];
8103         u8         access_reg_group[0x8];
8104         u8         reserved_at_20[0x20];
8105
8106         union {
8107                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8108                 u8  reserved_at_0[0x80];
8109         } qos_access_reg_cap_mask;
8110
8111         u8         reserved_at_c0[0x80];
8112
8113         union {
8114                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8115                 u8  reserved_at_0[0x80];
8116         } qos_feature_cap_mask;
8117
8118         u8         reserved_at_1c0[0x80];
8119 };
8120
8121 struct mlx5_ifc_pcap_reg_bits {
8122         u8         reserved_at_0[0x8];
8123         u8         local_port[0x8];
8124         u8         reserved_at_10[0x10];
8125
8126         u8         port_capability_mask[4][0x20];
8127 };
8128
8129 struct mlx5_ifc_paos_reg_bits {
8130         u8         swid[0x8];
8131         u8         local_port[0x8];
8132         u8         reserved_at_10[0x4];
8133         u8         admin_status[0x4];
8134         u8         reserved_at_18[0x4];
8135         u8         oper_status[0x4];
8136
8137         u8         ase[0x1];
8138         u8         ee[0x1];
8139         u8         reserved_at_22[0x1c];
8140         u8         e[0x2];
8141
8142         u8         reserved_at_40[0x40];
8143 };
8144
8145 struct mlx5_ifc_pamp_reg_bits {
8146         u8         reserved_at_0[0x8];
8147         u8         opamp_group[0x8];
8148         u8         reserved_at_10[0xc];
8149         u8         opamp_group_type[0x4];
8150
8151         u8         start_index[0x10];
8152         u8         reserved_at_30[0x4];
8153         u8         num_of_indices[0xc];
8154
8155         u8         index_data[18][0x10];
8156 };
8157
8158 struct mlx5_ifc_pcmr_reg_bits {
8159         u8         reserved_at_0[0x8];
8160         u8         local_port[0x8];
8161         u8         reserved_at_10[0x2e];
8162         u8         fcs_cap[0x1];
8163         u8         reserved_at_3f[0x1f];
8164         u8         fcs_chk[0x1];
8165         u8         reserved_at_5f[0x1];
8166 };
8167
8168 struct mlx5_ifc_lane_2_module_mapping_bits {
8169         u8         reserved_at_0[0x6];
8170         u8         rx_lane[0x2];
8171         u8         reserved_at_8[0x6];
8172         u8         tx_lane[0x2];
8173         u8         reserved_at_10[0x8];
8174         u8         module[0x8];
8175 };
8176
8177 struct mlx5_ifc_bufferx_reg_bits {
8178         u8         reserved_at_0[0x6];
8179         u8         lossy[0x1];
8180         u8         epsb[0x1];
8181         u8         reserved_at_8[0xc];
8182         u8         size[0xc];
8183
8184         u8         xoff_threshold[0x10];
8185         u8         xon_threshold[0x10];
8186 };
8187
8188 struct mlx5_ifc_set_node_in_bits {
8189         u8         node_description[64][0x8];
8190 };
8191
8192 struct mlx5_ifc_register_power_settings_bits {
8193         u8         reserved_at_0[0x18];
8194         u8         power_settings_level[0x8];
8195
8196         u8         reserved_at_20[0x60];
8197 };
8198
8199 struct mlx5_ifc_register_host_endianness_bits {
8200         u8         he[0x1];
8201         u8         reserved_at_1[0x1f];
8202
8203         u8         reserved_at_20[0x60];
8204 };
8205
8206 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8207         u8         reserved_at_0[0x20];
8208
8209         u8         mkey[0x20];
8210
8211         u8         addressh_63_32[0x20];
8212
8213         u8         addressl_31_0[0x20];
8214 };
8215
8216 struct mlx5_ifc_ud_adrs_vector_bits {
8217         u8         dc_key[0x40];
8218
8219         u8         ext[0x1];
8220         u8         reserved_at_41[0x7];
8221         u8         destination_qp_dct[0x18];
8222
8223         u8         static_rate[0x4];
8224         u8         sl_eth_prio[0x4];
8225         u8         fl[0x1];
8226         u8         mlid[0x7];
8227         u8         rlid_udp_sport[0x10];
8228
8229         u8         reserved_at_80[0x20];
8230
8231         u8         rmac_47_16[0x20];
8232
8233         u8         rmac_15_0[0x10];
8234         u8         tclass[0x8];
8235         u8         hop_limit[0x8];
8236
8237         u8         reserved_at_e0[0x1];
8238         u8         grh[0x1];
8239         u8         reserved_at_e2[0x2];
8240         u8         src_addr_index[0x8];
8241         u8         flow_label[0x14];
8242
8243         u8         rgid_rip[16][0x8];
8244 };
8245
8246 struct mlx5_ifc_pages_req_event_bits {
8247         u8         reserved_at_0[0x10];
8248         u8         function_id[0x10];
8249
8250         u8         num_pages[0x20];
8251
8252         u8         reserved_at_40[0xa0];
8253 };
8254
8255 struct mlx5_ifc_eqe_bits {
8256         u8         reserved_at_0[0x8];
8257         u8         event_type[0x8];
8258         u8         reserved_at_10[0x8];
8259         u8         event_sub_type[0x8];
8260
8261         u8         reserved_at_20[0xe0];
8262
8263         union mlx5_ifc_event_auto_bits event_data;
8264
8265         u8         reserved_at_1e0[0x10];
8266         u8         signature[0x8];
8267         u8         reserved_at_1f8[0x7];
8268         u8         owner[0x1];
8269 };
8270
8271 enum {
8272         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8273 };
8274
8275 struct mlx5_ifc_cmd_queue_entry_bits {
8276         u8         type[0x8];
8277         u8         reserved_at_8[0x18];
8278
8279         u8         input_length[0x20];
8280
8281         u8         input_mailbox_pointer_63_32[0x20];
8282
8283         u8         input_mailbox_pointer_31_9[0x17];
8284         u8         reserved_at_77[0x9];
8285
8286         u8         command_input_inline_data[16][0x8];
8287
8288         u8         command_output_inline_data[16][0x8];
8289
8290         u8         output_mailbox_pointer_63_32[0x20];
8291
8292         u8         output_mailbox_pointer_31_9[0x17];
8293         u8         reserved_at_1b7[0x9];
8294
8295         u8         output_length[0x20];
8296
8297         u8         token[0x8];
8298         u8         signature[0x8];
8299         u8         reserved_at_1f0[0x8];
8300         u8         status[0x7];
8301         u8         ownership[0x1];
8302 };
8303
8304 struct mlx5_ifc_cmd_out_bits {
8305         u8         status[0x8];
8306         u8         reserved_at_8[0x18];
8307
8308         u8         syndrome[0x20];
8309
8310         u8         command_output[0x20];
8311 };
8312
8313 struct mlx5_ifc_cmd_in_bits {
8314         u8         opcode[0x10];
8315         u8         reserved_at_10[0x10];
8316
8317         u8         reserved_at_20[0x10];
8318         u8         op_mod[0x10];
8319
8320         u8         command[0][0x20];
8321 };
8322
8323 struct mlx5_ifc_cmd_if_box_bits {
8324         u8         mailbox_data[512][0x8];
8325
8326         u8         reserved_at_1000[0x180];
8327
8328         u8         next_pointer_63_32[0x20];
8329
8330         u8         next_pointer_31_10[0x16];
8331         u8         reserved_at_11b6[0xa];
8332
8333         u8         block_number[0x20];
8334
8335         u8         reserved_at_11e0[0x8];
8336         u8         token[0x8];
8337         u8         ctrl_signature[0x8];
8338         u8         signature[0x8];
8339 };
8340
8341 struct mlx5_ifc_mtt_bits {
8342         u8         ptag_63_32[0x20];
8343
8344         u8         ptag_31_8[0x18];
8345         u8         reserved_at_38[0x6];
8346         u8         wr_en[0x1];
8347         u8         rd_en[0x1];
8348 };
8349
8350 struct mlx5_ifc_query_wol_rol_out_bits {
8351         u8         status[0x8];
8352         u8         reserved_at_8[0x18];
8353
8354         u8         syndrome[0x20];
8355
8356         u8         reserved_at_40[0x10];
8357         u8         rol_mode[0x8];
8358         u8         wol_mode[0x8];
8359
8360         u8         reserved_at_60[0x20];
8361 };
8362
8363 struct mlx5_ifc_query_wol_rol_in_bits {
8364         u8         opcode[0x10];
8365         u8         reserved_at_10[0x10];
8366
8367         u8         reserved_at_20[0x10];
8368         u8         op_mod[0x10];
8369
8370         u8         reserved_at_40[0x40];
8371 };
8372
8373 struct mlx5_ifc_set_wol_rol_out_bits {
8374         u8         status[0x8];
8375         u8         reserved_at_8[0x18];
8376
8377         u8         syndrome[0x20];
8378
8379         u8         reserved_at_40[0x40];
8380 };
8381
8382 struct mlx5_ifc_set_wol_rol_in_bits {
8383         u8         opcode[0x10];
8384         u8         reserved_at_10[0x10];
8385
8386         u8         reserved_at_20[0x10];
8387         u8         op_mod[0x10];
8388
8389         u8         rol_mode_valid[0x1];
8390         u8         wol_mode_valid[0x1];
8391         u8         reserved_at_42[0xe];
8392         u8         rol_mode[0x8];
8393         u8         wol_mode[0x8];
8394
8395         u8         reserved_at_60[0x20];
8396 };
8397
8398 enum {
8399         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8400         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8401         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8402 };
8403
8404 enum {
8405         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8406         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8407         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8408 };
8409
8410 enum {
8411         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8412         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8413         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8414         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8415         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8416         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8417         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8418         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8419         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8420         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8421         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8422 };
8423
8424 struct mlx5_ifc_initial_seg_bits {
8425         u8         fw_rev_minor[0x10];
8426         u8         fw_rev_major[0x10];
8427
8428         u8         cmd_interface_rev[0x10];
8429         u8         fw_rev_subminor[0x10];
8430
8431         u8         reserved_at_40[0x40];
8432
8433         u8         cmdq_phy_addr_63_32[0x20];
8434
8435         u8         cmdq_phy_addr_31_12[0x14];
8436         u8         reserved_at_b4[0x2];
8437         u8         nic_interface[0x2];
8438         u8         log_cmdq_size[0x4];
8439         u8         log_cmdq_stride[0x4];
8440
8441         u8         command_doorbell_vector[0x20];
8442
8443         u8         reserved_at_e0[0xf00];
8444
8445         u8         initializing[0x1];
8446         u8         reserved_at_fe1[0x4];
8447         u8         nic_interface_supported[0x3];
8448         u8         reserved_at_fe8[0x18];
8449
8450         struct mlx5_ifc_health_buffer_bits health_buffer;
8451
8452         u8         no_dram_nic_offset[0x20];
8453
8454         u8         reserved_at_1220[0x6e40];
8455
8456         u8         reserved_at_8060[0x1f];
8457         u8         clear_int[0x1];
8458
8459         u8         health_syndrome[0x8];
8460         u8         health_counter[0x18];
8461
8462         u8         reserved_at_80a0[0x17fc0];
8463 };
8464
8465 struct mlx5_ifc_mtpps_reg_bits {
8466         u8         reserved_at_0[0xc];
8467         u8         cap_number_of_pps_pins[0x4];
8468         u8         reserved_at_10[0x4];
8469         u8         cap_max_num_of_pps_in_pins[0x4];
8470         u8         reserved_at_18[0x4];
8471         u8         cap_max_num_of_pps_out_pins[0x4];
8472
8473         u8         reserved_at_20[0x24];
8474         u8         cap_pin_3_mode[0x4];
8475         u8         reserved_at_48[0x4];
8476         u8         cap_pin_2_mode[0x4];
8477         u8         reserved_at_50[0x4];
8478         u8         cap_pin_1_mode[0x4];
8479         u8         reserved_at_58[0x4];
8480         u8         cap_pin_0_mode[0x4];
8481
8482         u8         reserved_at_60[0x4];
8483         u8         cap_pin_7_mode[0x4];
8484         u8         reserved_at_68[0x4];
8485         u8         cap_pin_6_mode[0x4];
8486         u8         reserved_at_70[0x4];
8487         u8         cap_pin_5_mode[0x4];
8488         u8         reserved_at_78[0x4];
8489         u8         cap_pin_4_mode[0x4];
8490
8491         u8         field_select[0x20];
8492         u8         reserved_at_a0[0x60];
8493
8494         u8         enable[0x1];
8495         u8         reserved_at_101[0xb];
8496         u8         pattern[0x4];
8497         u8         reserved_at_110[0x4];
8498         u8         pin_mode[0x4];
8499         u8         pin[0x8];
8500
8501         u8         reserved_at_120[0x20];
8502
8503         u8         time_stamp[0x40];
8504
8505         u8         out_pulse_duration[0x10];
8506         u8         out_periodic_adjustment[0x10];
8507         u8         enhanced_out_periodic_adjustment[0x20];
8508
8509         u8         reserved_at_1c0[0x20];
8510 };
8511
8512 struct mlx5_ifc_mtppse_reg_bits {
8513         u8         reserved_at_0[0x18];
8514         u8         pin[0x8];
8515         u8         event_arm[0x1];
8516         u8         reserved_at_21[0x1b];
8517         u8         event_generation_mode[0x4];
8518         u8         reserved_at_40[0x40];
8519 };
8520
8521 struct mlx5_ifc_mcqi_cap_bits {
8522         u8         supported_info_bitmask[0x20];
8523
8524         u8         component_size[0x20];
8525
8526         u8         max_component_size[0x20];
8527
8528         u8         log_mcda_word_size[0x4];
8529         u8         reserved_at_64[0xc];
8530         u8         mcda_max_write_size[0x10];
8531
8532         u8         rd_en[0x1];
8533         u8         reserved_at_81[0x1];
8534         u8         match_chip_id[0x1];
8535         u8         match_psid[0x1];
8536         u8         check_user_timestamp[0x1];
8537         u8         match_base_guid_mac[0x1];
8538         u8         reserved_at_86[0x1a];
8539 };
8540
8541 struct mlx5_ifc_mcqi_reg_bits {
8542         u8         read_pending_component[0x1];
8543         u8         reserved_at_1[0xf];
8544         u8         component_index[0x10];
8545
8546         u8         reserved_at_20[0x20];
8547
8548         u8         reserved_at_40[0x1b];
8549         u8         info_type[0x5];
8550
8551         u8         info_size[0x20];
8552
8553         u8         offset[0x20];
8554
8555         u8         reserved_at_a0[0x10];
8556         u8         data_size[0x10];
8557
8558         u8         data[0][0x20];
8559 };
8560
8561 struct mlx5_ifc_mcc_reg_bits {
8562         u8         reserved_at_0[0x4];
8563         u8         time_elapsed_since_last_cmd[0xc];
8564         u8         reserved_at_10[0x8];
8565         u8         instruction[0x8];
8566
8567         u8         reserved_at_20[0x10];
8568         u8         component_index[0x10];
8569
8570         u8         reserved_at_40[0x8];
8571         u8         update_handle[0x18];
8572
8573         u8         handle_owner_type[0x4];
8574         u8         handle_owner_host_id[0x4];
8575         u8         reserved_at_68[0x1];
8576         u8         control_progress[0x7];
8577         u8         error_code[0x8];
8578         u8         reserved_at_78[0x4];
8579         u8         control_state[0x4];
8580
8581         u8         component_size[0x20];
8582
8583         u8         reserved_at_a0[0x60];
8584 };
8585
8586 struct mlx5_ifc_mcda_reg_bits {
8587         u8         reserved_at_0[0x8];
8588         u8         update_handle[0x18];
8589
8590         u8         offset[0x20];
8591
8592         u8         reserved_at_40[0x10];
8593         u8         size[0x10];
8594
8595         u8         reserved_at_60[0x20];
8596
8597         u8         data[0][0x20];
8598 };
8599
8600 union mlx5_ifc_ports_control_registers_document_bits {
8601         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8602         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8603         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8604         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8605         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8606         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8607         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8608         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8609         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8610         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8611         struct mlx5_ifc_paos_reg_bits paos_reg;
8612         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8613         struct mlx5_ifc_peir_reg_bits peir_reg;
8614         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8615         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8616         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8617         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8618         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8619         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8620         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8621         struct mlx5_ifc_plib_reg_bits plib_reg;
8622         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8623         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8624         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8625         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8626         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8627         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8628         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8629         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8630         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8631         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8632         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8633         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8634         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8635         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8636         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8637         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8638         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8639         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8640         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8641         struct mlx5_ifc_pude_reg_bits pude_reg;
8642         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8643         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8644         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8645         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8646         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8647         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8648         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8649         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8650         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8651         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8652         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8653         u8         reserved_at_0[0x60e0];
8654 };
8655
8656 union mlx5_ifc_debug_enhancements_document_bits {
8657         struct mlx5_ifc_health_buffer_bits health_buffer;
8658         u8         reserved_at_0[0x200];
8659 };
8660
8661 union mlx5_ifc_uplink_pci_interface_document_bits {
8662         struct mlx5_ifc_initial_seg_bits initial_seg;
8663         u8         reserved_at_0[0x20060];
8664 };
8665
8666 struct mlx5_ifc_set_flow_table_root_out_bits {
8667         u8         status[0x8];
8668         u8         reserved_at_8[0x18];
8669
8670         u8         syndrome[0x20];
8671
8672         u8         reserved_at_40[0x40];
8673 };
8674
8675 struct mlx5_ifc_set_flow_table_root_in_bits {
8676         u8         opcode[0x10];
8677         u8         reserved_at_10[0x10];
8678
8679         u8         reserved_at_20[0x10];
8680         u8         op_mod[0x10];
8681
8682         u8         other_vport[0x1];
8683         u8         reserved_at_41[0xf];
8684         u8         vport_number[0x10];
8685
8686         u8         reserved_at_60[0x20];
8687
8688         u8         table_type[0x8];
8689         u8         reserved_at_88[0x18];
8690
8691         u8         reserved_at_a0[0x8];
8692         u8         table_id[0x18];
8693
8694         u8         reserved_at_c0[0x8];
8695         u8         underlay_qpn[0x18];
8696         u8         reserved_at_e0[0x120];
8697 };
8698
8699 enum {
8700         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8701         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8702 };
8703
8704 struct mlx5_ifc_modify_flow_table_out_bits {
8705         u8         status[0x8];
8706         u8         reserved_at_8[0x18];
8707
8708         u8         syndrome[0x20];
8709
8710         u8         reserved_at_40[0x40];
8711 };
8712
8713 struct mlx5_ifc_modify_flow_table_in_bits {
8714         u8         opcode[0x10];
8715         u8         reserved_at_10[0x10];
8716
8717         u8         reserved_at_20[0x10];
8718         u8         op_mod[0x10];
8719
8720         u8         other_vport[0x1];
8721         u8         reserved_at_41[0xf];
8722         u8         vport_number[0x10];
8723
8724         u8         reserved_at_60[0x10];
8725         u8         modify_field_select[0x10];
8726
8727         u8         table_type[0x8];
8728         u8         reserved_at_88[0x18];
8729
8730         u8         reserved_at_a0[0x8];
8731         u8         table_id[0x18];
8732
8733         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8734 };
8735
8736 struct mlx5_ifc_ets_tcn_config_reg_bits {
8737         u8         g[0x1];
8738         u8         b[0x1];
8739         u8         r[0x1];
8740         u8         reserved_at_3[0x9];
8741         u8         group[0x4];
8742         u8         reserved_at_10[0x9];
8743         u8         bw_allocation[0x7];
8744
8745         u8         reserved_at_20[0xc];
8746         u8         max_bw_units[0x4];
8747         u8         reserved_at_30[0x8];
8748         u8         max_bw_value[0x8];
8749 };
8750
8751 struct mlx5_ifc_ets_global_config_reg_bits {
8752         u8         reserved_at_0[0x2];
8753         u8         r[0x1];
8754         u8         reserved_at_3[0x1d];
8755
8756         u8         reserved_at_20[0xc];
8757         u8         max_bw_units[0x4];
8758         u8         reserved_at_30[0x8];
8759         u8         max_bw_value[0x8];
8760 };
8761
8762 struct mlx5_ifc_qetc_reg_bits {
8763         u8                                         reserved_at_0[0x8];
8764         u8                                         port_number[0x8];
8765         u8                                         reserved_at_10[0x30];
8766
8767         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8768         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8769 };
8770
8771 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8772         u8         e[0x1];
8773         u8         reserved_at_01[0x0b];
8774         u8         prio[0x04];
8775 };
8776
8777 struct mlx5_ifc_qpdpm_reg_bits {
8778         u8                                     reserved_at_0[0x8];
8779         u8                                     local_port[0x8];
8780         u8                                     reserved_at_10[0x10];
8781         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8782 };
8783
8784 struct mlx5_ifc_qpts_reg_bits {
8785         u8         reserved_at_0[0x8];
8786         u8         local_port[0x8];
8787         u8         reserved_at_10[0x2d];
8788         u8         trust_state[0x3];
8789 };
8790
8791 struct mlx5_ifc_qtct_reg_bits {
8792         u8         reserved_at_0[0x8];
8793         u8         port_number[0x8];
8794         u8         reserved_at_10[0xd];
8795         u8         prio[0x3];
8796
8797         u8         reserved_at_20[0x1d];
8798         u8         tclass[0x3];
8799 };
8800
8801 struct mlx5_ifc_mcia_reg_bits {
8802         u8         l[0x1];
8803         u8         reserved_at_1[0x7];
8804         u8         module[0x8];
8805         u8         reserved_at_10[0x8];
8806         u8         status[0x8];
8807
8808         u8         i2c_device_address[0x8];
8809         u8         page_number[0x8];
8810         u8         device_address[0x10];
8811
8812         u8         reserved_at_40[0x10];
8813         u8         size[0x10];
8814
8815         u8         reserved_at_60[0x20];
8816
8817         u8         dword_0[0x20];
8818         u8         dword_1[0x20];
8819         u8         dword_2[0x20];
8820         u8         dword_3[0x20];
8821         u8         dword_4[0x20];
8822         u8         dword_5[0x20];
8823         u8         dword_6[0x20];
8824         u8         dword_7[0x20];
8825         u8         dword_8[0x20];
8826         u8         dword_9[0x20];
8827         u8         dword_10[0x20];
8828         u8         dword_11[0x20];
8829 };
8830
8831 struct mlx5_ifc_dcbx_param_bits {
8832         u8         dcbx_cee_cap[0x1];
8833         u8         dcbx_ieee_cap[0x1];
8834         u8         dcbx_standby_cap[0x1];
8835         u8         reserved_at_0[0x5];
8836         u8         port_number[0x8];
8837         u8         reserved_at_10[0xa];
8838         u8         max_application_table_size[6];
8839         u8         reserved_at_20[0x15];
8840         u8         version_oper[0x3];
8841         u8         reserved_at_38[5];
8842         u8         version_admin[0x3];
8843         u8         willing_admin[0x1];
8844         u8         reserved_at_41[0x3];
8845         u8         pfc_cap_oper[0x4];
8846         u8         reserved_at_48[0x4];
8847         u8         pfc_cap_admin[0x4];
8848         u8         reserved_at_50[0x4];
8849         u8         num_of_tc_oper[0x4];
8850         u8         reserved_at_58[0x4];
8851         u8         num_of_tc_admin[0x4];
8852         u8         remote_willing[0x1];
8853         u8         reserved_at_61[3];
8854         u8         remote_pfc_cap[4];
8855         u8         reserved_at_68[0x14];
8856         u8         remote_num_of_tc[0x4];
8857         u8         reserved_at_80[0x18];
8858         u8         error[0x8];
8859         u8         reserved_at_a0[0x160];
8860 };
8861
8862 struct mlx5_ifc_lagc_bits {
8863         u8         reserved_at_0[0x1d];
8864         u8         lag_state[0x3];
8865
8866         u8         reserved_at_20[0x14];
8867         u8         tx_remap_affinity_2[0x4];
8868         u8         reserved_at_38[0x4];
8869         u8         tx_remap_affinity_1[0x4];
8870 };
8871
8872 struct mlx5_ifc_create_lag_out_bits {
8873         u8         status[0x8];
8874         u8         reserved_at_8[0x18];
8875
8876         u8         syndrome[0x20];
8877
8878         u8         reserved_at_40[0x40];
8879 };
8880
8881 struct mlx5_ifc_create_lag_in_bits {
8882         u8         opcode[0x10];
8883         u8         reserved_at_10[0x10];
8884
8885         u8         reserved_at_20[0x10];
8886         u8         op_mod[0x10];
8887
8888         struct mlx5_ifc_lagc_bits ctx;
8889 };
8890
8891 struct mlx5_ifc_modify_lag_out_bits {
8892         u8         status[0x8];
8893         u8         reserved_at_8[0x18];
8894
8895         u8         syndrome[0x20];
8896
8897         u8         reserved_at_40[0x40];
8898 };
8899
8900 struct mlx5_ifc_modify_lag_in_bits {
8901         u8         opcode[0x10];
8902         u8         reserved_at_10[0x10];
8903
8904         u8         reserved_at_20[0x10];
8905         u8         op_mod[0x10];
8906
8907         u8         reserved_at_40[0x20];
8908         u8         field_select[0x20];
8909
8910         struct mlx5_ifc_lagc_bits ctx;
8911 };
8912
8913 struct mlx5_ifc_query_lag_out_bits {
8914         u8         status[0x8];
8915         u8         reserved_at_8[0x18];
8916
8917         u8         syndrome[0x20];
8918
8919         u8         reserved_at_40[0x40];
8920
8921         struct mlx5_ifc_lagc_bits ctx;
8922 };
8923
8924 struct mlx5_ifc_query_lag_in_bits {
8925         u8         opcode[0x10];
8926         u8         reserved_at_10[0x10];
8927
8928         u8         reserved_at_20[0x10];
8929         u8         op_mod[0x10];
8930
8931         u8         reserved_at_40[0x40];
8932 };
8933
8934 struct mlx5_ifc_destroy_lag_out_bits {
8935         u8         status[0x8];
8936         u8         reserved_at_8[0x18];
8937
8938         u8         syndrome[0x20];
8939
8940         u8         reserved_at_40[0x40];
8941 };
8942
8943 struct mlx5_ifc_destroy_lag_in_bits {
8944         u8         opcode[0x10];
8945         u8         reserved_at_10[0x10];
8946
8947         u8         reserved_at_20[0x10];
8948         u8         op_mod[0x10];
8949
8950         u8         reserved_at_40[0x40];
8951 };
8952
8953 struct mlx5_ifc_create_vport_lag_out_bits {
8954         u8         status[0x8];
8955         u8         reserved_at_8[0x18];
8956
8957         u8         syndrome[0x20];
8958
8959         u8         reserved_at_40[0x40];
8960 };
8961
8962 struct mlx5_ifc_create_vport_lag_in_bits {
8963         u8         opcode[0x10];
8964         u8         reserved_at_10[0x10];
8965
8966         u8         reserved_at_20[0x10];
8967         u8         op_mod[0x10];
8968
8969         u8         reserved_at_40[0x40];
8970 };
8971
8972 struct mlx5_ifc_destroy_vport_lag_out_bits {
8973         u8         status[0x8];
8974         u8         reserved_at_8[0x18];
8975
8976         u8         syndrome[0x20];
8977
8978         u8         reserved_at_40[0x40];
8979 };
8980
8981 struct mlx5_ifc_destroy_vport_lag_in_bits {
8982         u8         opcode[0x10];
8983         u8         reserved_at_10[0x10];
8984
8985         u8         reserved_at_20[0x10];
8986         u8         op_mod[0x10];
8987
8988         u8         reserved_at_40[0x40];
8989 };
8990
8991 struct mlx5_ifc_alloc_memic_in_bits {
8992         u8         opcode[0x10];
8993         u8         reserved_at_10[0x10];
8994
8995         u8         reserved_at_20[0x10];
8996         u8         op_mod[0x10];
8997
8998         u8         reserved_at_30[0x20];
8999
9000         u8         reserved_at_40[0x18];
9001         u8         log_memic_addr_alignment[0x8];
9002
9003         u8         range_start_addr[0x40];
9004
9005         u8         range_size[0x20];
9006
9007         u8         memic_size[0x20];
9008 };
9009
9010 struct mlx5_ifc_alloc_memic_out_bits {
9011         u8         status[0x8];
9012         u8         reserved_at_8[0x18];
9013
9014         u8         syndrome[0x20];
9015
9016         u8         memic_start_addr[0x40];
9017 };
9018
9019 struct mlx5_ifc_dealloc_memic_in_bits {
9020         u8         opcode[0x10];
9021         u8         reserved_at_10[0x10];
9022
9023         u8         reserved_at_20[0x10];
9024         u8         op_mod[0x10];
9025
9026         u8         reserved_at_40[0x40];
9027
9028         u8         memic_start_addr[0x40];
9029
9030         u8         memic_size[0x20];
9031
9032         u8         reserved_at_e0[0x20];
9033 };
9034
9035 struct mlx5_ifc_dealloc_memic_out_bits {
9036         u8         status[0x8];
9037         u8         reserved_at_8[0x18];
9038
9039         u8         syndrome[0x20];
9040
9041         u8         reserved_at_40[0x40];
9042 };
9043
9044 #endif /* MLX5_IFC_H */