2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
233 struct mlx5_ifc_flow_table_fields_supported_bits {
236 u8 outer_ether_type[0x1];
237 u8 reserved_at_3[0x1];
238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
241 u8 reserved_at_7[0x1];
242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
245 u8 reserved_at_b[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
260 u8 reserved_at_1a[0x5];
261 u8 source_eswitch_port[0x1];
265 u8 inner_ether_type[0x1];
266 u8 reserved_at_23[0x1];
267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
270 u8 reserved_at_27[0x1];
271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
274 u8 reserved_at_2b[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
286 u8 reserved_at_37[0x9];
288 u8 reserved_at_40[0x40];
291 struct mlx5_ifc_flow_table_prop_layout_bits {
293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
295 u8 flow_modify_en[0x1];
297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
301 u8 reserved_at_9[0x17];
303 u8 reserved_at_20[0x2];
304 u8 log_max_ft_size[0x6];
305 u8 reserved_at_28[0x10];
306 u8 max_ft_level[0x8];
308 u8 reserved_at_40[0x20];
310 u8 reserved_at_60[0x18];
311 u8 log_max_ft_num[0x8];
313 u8 reserved_at_80[0x18];
314 u8 log_max_destination[0x8];
316 u8 reserved_at_a0[0x18];
317 u8 log_max_flow[0x8];
319 u8 reserved_at_c0[0x40];
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
331 u8 reserved_at_4[0x1];
333 u8 reserved_at_6[0x1a];
336 struct mlx5_ifc_ipv4_layout_bits {
337 u8 reserved_at_0[0x60];
342 struct mlx5_ifc_ipv6_layout_bits {
346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
349 u8 reserved_at_0[0x80];
352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
369 u8 reserved_at_91[0x1];
371 u8 reserved_at_93[0x4];
377 u8 reserved_at_c0[0x20];
382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
387 struct mlx5_ifc_fte_match_set_misc_bits {
388 u8 reserved_at_0[0x8];
391 u8 reserved_at_20[0x10];
392 u8 source_port[0x10];
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
401 u8 outer_second_vlan_tag[0x1];
402 u8 inner_second_vlan_tag[0x1];
403 u8 reserved_at_62[0xe];
404 u8 gre_protocol[0x10];
410 u8 reserved_at_b8[0x8];
412 u8 reserved_at_c0[0x20];
414 u8 reserved_at_e0[0xc];
415 u8 outer_ipv6_flow_label[0x14];
417 u8 reserved_at_100[0xc];
418 u8 inner_ipv6_flow_label[0x14];
420 u8 reserved_at_120[0xe0];
423 struct mlx5_ifc_cmd_pas_bits {
427 u8 reserved_at_34[0xc];
430 struct mlx5_ifc_uint64_bits {
437 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
438 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
439 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
440 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
441 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
442 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
443 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
444 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
445 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
446 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
449 struct mlx5_ifc_ads_bits {
452 u8 reserved_at_2[0xe];
455 u8 reserved_at_20[0x8];
461 u8 reserved_at_45[0x3];
462 u8 src_addr_index[0x8];
463 u8 reserved_at_50[0x4];
467 u8 reserved_at_60[0x4];
471 u8 rgid_rip[16][0x8];
473 u8 reserved_at_100[0x4];
476 u8 reserved_at_106[0x1];
491 struct mlx5_ifc_flow_table_nic_cap_bits {
492 u8 nic_rx_multi_path_tirs[0x1];
493 u8 nic_rx_multi_path_tirs_fts[0x1];
494 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
495 u8 reserved_at_3[0x1fd];
497 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
499 u8 reserved_at_400[0x200];
501 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
505 u8 reserved_at_a00[0x200];
507 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
509 u8 reserved_at_e00[0x7200];
512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
513 u8 reserved_at_0[0x200];
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
521 u8 reserved_at_800[0x7800];
524 struct mlx5_ifc_e_switch_cap_bits {
525 u8 vport_svlan_strip[0x1];
526 u8 vport_cvlan_strip[0x1];
527 u8 vport_svlan_insert[0x1];
528 u8 vport_cvlan_insert_if_not_exist[0x1];
529 u8 vport_cvlan_insert_overwrite[0x1];
530 u8 reserved_at_5[0x19];
531 u8 nic_vport_node_guid_modify[0x1];
532 u8 nic_vport_port_guid_modify[0x1];
534 u8 vxlan_encap_decap[0x1];
535 u8 nvgre_encap_decap[0x1];
536 u8 reserved_at_22[0x9];
537 u8 log_max_encap_headers[0x5];
539 u8 max_encap_header_size[0xa];
541 u8 reserved_40[0x7c0];
545 struct mlx5_ifc_qos_cap_bits {
546 u8 packet_pacing[0x1];
547 u8 esw_scheduling[0x1];
548 u8 reserved_at_2[0x1e];
550 u8 reserved_at_20[0x20];
552 u8 packet_pacing_max_rate[0x20];
554 u8 packet_pacing_min_rate[0x20];
556 u8 reserved_at_80[0x10];
557 u8 packet_pacing_rate_table_size[0x10];
559 u8 esw_element_type[0x10];
560 u8 esw_tsar_type[0x10];
562 u8 reserved_at_c0[0x10];
563 u8 max_qos_para_vport[0x10];
565 u8 max_tsar_bw_share[0x20];
567 u8 reserved_at_100[0x700];
570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
574 u8 lro_psh_flag[0x1];
575 u8 lro_time_stamp[0x1];
576 u8 reserved_at_5[0x3];
577 u8 self_lb_en_modifiable[0x1];
578 u8 reserved_at_9[0x2];
580 u8 multi_pkt_send_wqe[0x2];
581 u8 wqe_inline_mode[0x2];
582 u8 rss_ind_tbl_cap[0x4];
585 u8 reserved_at_1a[0x1];
586 u8 tunnel_lso_const_out_ip_id[0x1];
587 u8 reserved_at_1c[0x2];
588 u8 tunnel_statless_gre[0x1];
589 u8 tunnel_stateless_vxlan[0x1];
591 u8 reserved_at_20[0x20];
593 u8 reserved_at_40[0x10];
594 u8 lro_min_mss_size[0x10];
596 u8 reserved_at_60[0x120];
598 u8 lro_timer_supported_periods[4][0x20];
600 u8 reserved_at_200[0x600];
603 struct mlx5_ifc_roce_cap_bits {
605 u8 reserved_at_1[0x1f];
607 u8 reserved_at_20[0x60];
609 u8 reserved_at_80[0xc];
611 u8 reserved_at_90[0x8];
612 u8 roce_version[0x8];
614 u8 reserved_at_a0[0x10];
615 u8 r_roce_dest_udp_port[0x10];
617 u8 r_roce_max_src_udp_port[0x10];
618 u8 r_roce_min_src_udp_port[0x10];
620 u8 reserved_at_e0[0x10];
621 u8 roce_address_table_size[0x10];
623 u8 reserved_at_100[0x700];
627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
650 struct mlx5_ifc_atomic_caps_bits {
651 u8 reserved_at_0[0x40];
653 u8 atomic_req_8B_endianess_mode[0x2];
654 u8 reserved_at_42[0x4];
655 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
657 u8 reserved_at_47[0x19];
659 u8 reserved_at_60[0x20];
661 u8 reserved_at_80[0x10];
662 u8 atomic_operations[0x10];
664 u8 reserved_at_a0[0x10];
665 u8 atomic_size_qp[0x10];
667 u8 reserved_at_c0[0x10];
668 u8 atomic_size_dc[0x10];
670 u8 reserved_at_e0[0x720];
673 struct mlx5_ifc_odp_cap_bits {
674 u8 reserved_at_0[0x40];
677 u8 reserved_at_41[0x1f];
679 u8 reserved_at_60[0x20];
681 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
683 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
685 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
687 u8 reserved_at_e0[0x720];
690 struct mlx5_ifc_calc_op {
691 u8 reserved_at_0[0x10];
692 u8 reserved_at_10[0x9];
693 u8 op_swap_endianness[0x1];
702 struct mlx5_ifc_vector_calc_cap_bits {
704 u8 reserved_at_1[0x1f];
705 u8 reserved_at_20[0x8];
706 u8 max_vec_count[0x8];
707 u8 reserved_at_30[0xd];
708 u8 max_chunk_size[0x3];
709 struct mlx5_ifc_calc_op calc0;
710 struct mlx5_ifc_calc_op calc1;
711 struct mlx5_ifc_calc_op calc2;
712 struct mlx5_ifc_calc_op calc3;
714 u8 reserved_at_e0[0x720];
718 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
719 MLX5_WQ_TYPE_CYCLIC = 0x1,
720 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
724 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
725 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
746 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
747 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
757 MLX5_CAP_PORT_TYPE_IB = 0x0,
758 MLX5_CAP_PORT_TYPE_ETH = 0x1,
761 struct mlx5_ifc_cmd_hca_cap_bits {
762 u8 reserved_at_0[0x80];
764 u8 log_max_srq_sz[0x8];
765 u8 log_max_qp_sz[0x8];
766 u8 reserved_at_90[0xb];
769 u8 reserved_at_a0[0xb];
771 u8 reserved_at_b0[0x10];
773 u8 reserved_at_c0[0x8];
774 u8 log_max_cq_sz[0x8];
775 u8 reserved_at_d0[0xb];
778 u8 log_max_eq_sz[0x8];
779 u8 reserved_at_e8[0x2];
780 u8 log_max_mkey[0x6];
781 u8 reserved_at_f0[0xc];
784 u8 max_indirection[0x8];
785 u8 reserved_at_108[0x1];
786 u8 log_max_mrw_sz[0x7];
787 u8 reserved_at_110[0x2];
788 u8 log_max_bsf_list_size[0x6];
789 u8 reserved_at_118[0x2];
790 u8 log_max_klm_list_size[0x6];
792 u8 reserved_at_120[0xa];
793 u8 log_max_ra_req_dc[0x6];
794 u8 reserved_at_130[0xa];
795 u8 log_max_ra_res_dc[0x6];
797 u8 reserved_at_140[0xa];
798 u8 log_max_ra_req_qp[0x6];
799 u8 reserved_at_150[0xa];
800 u8 log_max_ra_res_qp[0x6];
803 u8 cc_query_allowed[0x1];
804 u8 cc_modify_allowed[0x1];
805 u8 reserved_at_163[0xd];
806 u8 gid_table_size[0x10];
808 u8 out_of_seq_cnt[0x1];
809 u8 vport_counters[0x1];
810 u8 retransmission_q_counters[0x1];
811 u8 reserved_at_183[0x1];
812 u8 modify_rq_counter_set_id[0x1];
813 u8 reserved_at_185[0x1];
815 u8 pkey_table_size[0x10];
817 u8 vport_group_manager[0x1];
818 u8 vhca_group_manager[0x1];
821 u8 reserved_at_1a4[0x1];
823 u8 nic_flow_table[0x1];
824 u8 eswitch_flow_table[0x1];
825 u8 early_vf_enable[0x1];
826 u8 reserved_at_1a9[0x2];
827 u8 local_ca_ack_delay[0x5];
828 u8 port_module_event[0x1];
829 u8 reserved_at_1b0[0x1];
831 u8 reserved_at_1b2[0x1];
832 u8 disable_link_up[0x1];
837 u8 reserved_at_1c0[0x3];
839 u8 reserved_at_1c8[0x4];
841 u8 reserved_at_1d0[0x1];
843 u8 reserved_at_1d2[0x4];
846 u8 reserved_at_1d8[0x1];
855 u8 stat_rate_support[0x10];
856 u8 reserved_at_1f0[0xc];
859 u8 compact_address_vector[0x1];
861 u8 reserved_at_201[0x2];
862 u8 ipoib_basic_offloads[0x1];
863 u8 reserved_at_205[0xa];
864 u8 drain_sigerr[0x1];
865 u8 cmdif_checksum[0x2];
867 u8 reserved_at_213[0x1];
868 u8 wq_signature[0x1];
869 u8 sctr_data_cqe[0x1];
870 u8 reserved_at_216[0x1];
876 u8 eth_net_offloads[0x1];
879 u8 reserved_at_21f[0x1];
883 u8 cq_moderation[0x1];
884 u8 reserved_at_223[0x3];
888 u8 reserved_at_229[0x1];
889 u8 scqe_break_moderation[0x1];
890 u8 cq_period_start_from_cqe[0x1];
892 u8 reserved_at_22d[0x1];
895 u8 umr_ptr_rlky[0x1];
897 u8 reserved_at_232[0x4];
900 u8 set_deth_sqpn[0x1];
901 u8 reserved_at_239[0x3];
907 u8 reserved_at_240[0xa];
909 u8 reserved_at_250[0x8];
913 u8 driver_version[0x1];
914 u8 pad_tx_eth_packet[0x1];
915 u8 reserved_at_263[0x8];
916 u8 log_bf_reg_size[0x5];
918 u8 reserved_at_270[0xb];
920 u8 num_lag_ports[0x4];
922 u8 reserved_at_280[0x10];
923 u8 max_wqe_sz_sq[0x10];
925 u8 reserved_at_2a0[0x10];
926 u8 max_wqe_sz_rq[0x10];
928 u8 reserved_at_2c0[0x10];
929 u8 max_wqe_sz_sq_dc[0x10];
931 u8 reserved_at_2e0[0x7];
934 u8 reserved_at_300[0x18];
937 u8 reserved_at_320[0x3];
938 u8 log_max_transport_domain[0x5];
939 u8 reserved_at_328[0x3];
941 u8 reserved_at_330[0xb];
942 u8 log_max_xrcd[0x5];
944 u8 reserved_at_340[0x8];
945 u8 log_max_flow_counter_bulk[0x8];
946 u8 max_flow_counter[0x10];
949 u8 reserved_at_360[0x3];
951 u8 reserved_at_368[0x3];
953 u8 reserved_at_370[0x3];
955 u8 reserved_at_378[0x3];
958 u8 basic_cyclic_rcv_wqe[0x1];
959 u8 reserved_at_381[0x2];
961 u8 reserved_at_388[0x3];
963 u8 reserved_at_390[0x3];
964 u8 log_max_rqt_size[0x5];
965 u8 reserved_at_398[0x3];
966 u8 log_max_tis_per_sq[0x5];
968 u8 reserved_at_3a0[0x3];
969 u8 log_max_stride_sz_rq[0x5];
970 u8 reserved_at_3a8[0x3];
971 u8 log_min_stride_sz_rq[0x5];
972 u8 reserved_at_3b0[0x3];
973 u8 log_max_stride_sz_sq[0x5];
974 u8 reserved_at_3b8[0x3];
975 u8 log_min_stride_sz_sq[0x5];
977 u8 reserved_at_3c0[0x1b];
978 u8 log_max_wq_sz[0x5];
980 u8 nic_vport_change_event[0x1];
981 u8 reserved_at_3e1[0xa];
982 u8 log_max_vlan_list[0x5];
983 u8 reserved_at_3f0[0x3];
984 u8 log_max_current_mc_list[0x5];
985 u8 reserved_at_3f8[0x3];
986 u8 log_max_current_uc_list[0x5];
988 u8 reserved_at_400[0x80];
990 u8 reserved_at_480[0x3];
991 u8 log_max_l2_table[0x5];
992 u8 reserved_at_488[0x8];
993 u8 log_uar_page_sz[0x10];
995 u8 reserved_at_4a0[0x20];
996 u8 device_frequency_mhz[0x20];
997 u8 device_frequency_khz[0x20];
999 u8 reserved_at_500[0x80];
1001 u8 reserved_at_580[0x3f];
1002 u8 cqe_compression[0x1];
1004 u8 cqe_compression_timeout[0x10];
1005 u8 cqe_compression_max_num[0x10];
1007 u8 reserved_at_5e0[0x10];
1008 u8 tag_matching[0x1];
1009 u8 rndv_offload_rc[0x1];
1010 u8 rndv_offload_dc[0x1];
1011 u8 log_tag_matching_list_sz[0x5];
1012 u8 reserved_at_5e8[0x3];
1013 u8 log_max_xrq[0x5];
1015 u8 reserved_at_5f0[0x200];
1018 enum mlx5_flow_destination_type {
1019 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1020 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1021 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1023 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1026 struct mlx5_ifc_dest_format_struct_bits {
1027 u8 destination_type[0x8];
1028 u8 destination_id[0x18];
1030 u8 reserved_at_20[0x20];
1033 struct mlx5_ifc_flow_counter_list_bits {
1035 u8 num_of_counters[0xf];
1036 u8 flow_counter_id[0x10];
1038 u8 reserved_at_20[0x20];
1041 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1042 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1043 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1044 u8 reserved_at_0[0x40];
1047 struct mlx5_ifc_fte_match_param_bits {
1048 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1050 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1052 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1054 u8 reserved_at_600[0xa00];
1058 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1065 struct mlx5_ifc_rx_hash_field_select_bits {
1066 u8 l3_prot_type[0x1];
1067 u8 l4_prot_type[0x1];
1068 u8 selected_fields[0x1e];
1072 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1073 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1077 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1078 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1081 struct mlx5_ifc_wq_bits {
1083 u8 wq_signature[0x1];
1084 u8 end_padding_mode[0x2];
1086 u8 reserved_at_8[0x18];
1088 u8 hds_skip_first_sge[0x1];
1089 u8 log2_hds_buf_size[0x3];
1090 u8 reserved_at_24[0x7];
1091 u8 page_offset[0x5];
1094 u8 reserved_at_40[0x8];
1097 u8 reserved_at_60[0x8];
1102 u8 hw_counter[0x20];
1104 u8 sw_counter[0x20];
1106 u8 reserved_at_100[0xc];
1107 u8 log_wq_stride[0x4];
1108 u8 reserved_at_110[0x3];
1109 u8 log_wq_pg_sz[0x5];
1110 u8 reserved_at_118[0x3];
1113 u8 reserved_at_120[0x15];
1114 u8 log_wqe_num_of_strides[0x3];
1115 u8 two_byte_shift_en[0x1];
1116 u8 reserved_at_139[0x4];
1117 u8 log_wqe_stride_size[0x3];
1119 u8 reserved_at_140[0x4c0];
1121 struct mlx5_ifc_cmd_pas_bits pas[0];
1124 struct mlx5_ifc_rq_num_bits {
1125 u8 reserved_at_0[0x8];
1129 struct mlx5_ifc_mac_address_layout_bits {
1130 u8 reserved_at_0[0x10];
1131 u8 mac_addr_47_32[0x10];
1133 u8 mac_addr_31_0[0x20];
1136 struct mlx5_ifc_vlan_layout_bits {
1137 u8 reserved_at_0[0x14];
1140 u8 reserved_at_20[0x20];
1143 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1144 u8 reserved_at_0[0xa0];
1146 u8 min_time_between_cnps[0x20];
1148 u8 reserved_at_c0[0x12];
1150 u8 reserved_at_d8[0x5];
1151 u8 cnp_802p_prio[0x3];
1153 u8 reserved_at_e0[0x720];
1156 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1157 u8 reserved_at_0[0x60];
1159 u8 reserved_at_60[0x4];
1160 u8 clamp_tgt_rate[0x1];
1161 u8 reserved_at_65[0x3];
1162 u8 clamp_tgt_rate_after_time_inc[0x1];
1163 u8 reserved_at_69[0x17];
1165 u8 reserved_at_80[0x20];
1167 u8 rpg_time_reset[0x20];
1169 u8 rpg_byte_reset[0x20];
1171 u8 rpg_threshold[0x20];
1173 u8 rpg_max_rate[0x20];
1175 u8 rpg_ai_rate[0x20];
1177 u8 rpg_hai_rate[0x20];
1181 u8 rpg_min_dec_fac[0x20];
1183 u8 rpg_min_rate[0x20];
1185 u8 reserved_at_1c0[0xe0];
1187 u8 rate_to_set_on_first_cnp[0x20];
1191 u8 dce_tcp_rtt[0x20];
1193 u8 rate_reduce_monitor_period[0x20];
1195 u8 reserved_at_320[0x20];
1197 u8 initial_alpha_value[0x20];
1199 u8 reserved_at_360[0x4a0];
1202 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1203 u8 reserved_at_0[0x80];
1205 u8 rppp_max_rps[0x20];
1207 u8 rpg_time_reset[0x20];
1209 u8 rpg_byte_reset[0x20];
1211 u8 rpg_threshold[0x20];
1213 u8 rpg_max_rate[0x20];
1215 u8 rpg_ai_rate[0x20];
1217 u8 rpg_hai_rate[0x20];
1221 u8 rpg_min_dec_fac[0x20];
1223 u8 rpg_min_rate[0x20];
1225 u8 reserved_at_1c0[0x640];
1229 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1230 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1231 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1234 struct mlx5_ifc_resize_field_select_bits {
1235 u8 resize_field_select[0x20];
1239 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1241 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1242 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1245 struct mlx5_ifc_modify_field_select_bits {
1246 u8 modify_field_select[0x20];
1249 struct mlx5_ifc_field_select_r_roce_np_bits {
1250 u8 field_select_r_roce_np[0x20];
1253 struct mlx5_ifc_field_select_r_roce_rp_bits {
1254 u8 field_select_r_roce_rp[0x20];
1258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1270 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1271 u8 field_select_8021qaurp[0x20];
1274 struct mlx5_ifc_phys_layer_cntrs_bits {
1275 u8 time_since_last_clear_high[0x20];
1277 u8 time_since_last_clear_low[0x20];
1279 u8 symbol_errors_high[0x20];
1281 u8 symbol_errors_low[0x20];
1283 u8 sync_headers_errors_high[0x20];
1285 u8 sync_headers_errors_low[0x20];
1287 u8 edpl_bip_errors_lane0_high[0x20];
1289 u8 edpl_bip_errors_lane0_low[0x20];
1291 u8 edpl_bip_errors_lane1_high[0x20];
1293 u8 edpl_bip_errors_lane1_low[0x20];
1295 u8 edpl_bip_errors_lane2_high[0x20];
1297 u8 edpl_bip_errors_lane2_low[0x20];
1299 u8 edpl_bip_errors_lane3_high[0x20];
1301 u8 edpl_bip_errors_lane3_low[0x20];
1303 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1305 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1307 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1309 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1311 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1313 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1315 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1317 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1319 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1321 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1323 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1325 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1327 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1329 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1331 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1333 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1335 u8 rs_fec_corrected_blocks_high[0x20];
1337 u8 rs_fec_corrected_blocks_low[0x20];
1339 u8 rs_fec_uncorrectable_blocks_high[0x20];
1341 u8 rs_fec_uncorrectable_blocks_low[0x20];
1343 u8 rs_fec_no_errors_blocks_high[0x20];
1345 u8 rs_fec_no_errors_blocks_low[0x20];
1347 u8 rs_fec_single_error_blocks_high[0x20];
1349 u8 rs_fec_single_error_blocks_low[0x20];
1351 u8 rs_fec_corrected_symbols_total_high[0x20];
1353 u8 rs_fec_corrected_symbols_total_low[0x20];
1355 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1357 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1359 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1361 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1363 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1365 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1367 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1369 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1371 u8 link_down_events[0x20];
1373 u8 successful_recovery_events[0x20];
1375 u8 reserved_at_640[0x180];
1378 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1379 u8 symbol_error_counter[0x10];
1381 u8 link_error_recovery_counter[0x8];
1383 u8 link_downed_counter[0x8];
1385 u8 port_rcv_errors[0x10];
1387 u8 port_rcv_remote_physical_errors[0x10];
1389 u8 port_rcv_switch_relay_errors[0x10];
1391 u8 port_xmit_discards[0x10];
1393 u8 port_xmit_constraint_errors[0x8];
1395 u8 port_rcv_constraint_errors[0x8];
1397 u8 reserved_at_70[0x8];
1399 u8 link_overrun_errors[0x8];
1401 u8 reserved_at_80[0x10];
1403 u8 vl_15_dropped[0x10];
1405 u8 reserved_at_a0[0xa0];
1408 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1409 u8 transmit_queue_high[0x20];
1411 u8 transmit_queue_low[0x20];
1413 u8 reserved_at_40[0x780];
1416 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1417 u8 rx_octets_high[0x20];
1419 u8 rx_octets_low[0x20];
1421 u8 reserved_at_40[0xc0];
1423 u8 rx_frames_high[0x20];
1425 u8 rx_frames_low[0x20];
1427 u8 tx_octets_high[0x20];
1429 u8 tx_octets_low[0x20];
1431 u8 reserved_at_180[0xc0];
1433 u8 tx_frames_high[0x20];
1435 u8 tx_frames_low[0x20];
1437 u8 rx_pause_high[0x20];
1439 u8 rx_pause_low[0x20];
1441 u8 rx_pause_duration_high[0x20];
1443 u8 rx_pause_duration_low[0x20];
1445 u8 tx_pause_high[0x20];
1447 u8 tx_pause_low[0x20];
1449 u8 tx_pause_duration_high[0x20];
1451 u8 tx_pause_duration_low[0x20];
1453 u8 rx_pause_transition_high[0x20];
1455 u8 rx_pause_transition_low[0x20];
1457 u8 reserved_at_3c0[0x400];
1460 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1461 u8 port_transmit_wait_high[0x20];
1463 u8 port_transmit_wait_low[0x20];
1465 u8 reserved_at_40[0x780];
1468 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1469 u8 dot3stats_alignment_errors_high[0x20];
1471 u8 dot3stats_alignment_errors_low[0x20];
1473 u8 dot3stats_fcs_errors_high[0x20];
1475 u8 dot3stats_fcs_errors_low[0x20];
1477 u8 dot3stats_single_collision_frames_high[0x20];
1479 u8 dot3stats_single_collision_frames_low[0x20];
1481 u8 dot3stats_multiple_collision_frames_high[0x20];
1483 u8 dot3stats_multiple_collision_frames_low[0x20];
1485 u8 dot3stats_sqe_test_errors_high[0x20];
1487 u8 dot3stats_sqe_test_errors_low[0x20];
1489 u8 dot3stats_deferred_transmissions_high[0x20];
1491 u8 dot3stats_deferred_transmissions_low[0x20];
1493 u8 dot3stats_late_collisions_high[0x20];
1495 u8 dot3stats_late_collisions_low[0x20];
1497 u8 dot3stats_excessive_collisions_high[0x20];
1499 u8 dot3stats_excessive_collisions_low[0x20];
1501 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1503 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1505 u8 dot3stats_carrier_sense_errors_high[0x20];
1507 u8 dot3stats_carrier_sense_errors_low[0x20];
1509 u8 dot3stats_frame_too_longs_high[0x20];
1511 u8 dot3stats_frame_too_longs_low[0x20];
1513 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1515 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1517 u8 dot3stats_symbol_errors_high[0x20];
1519 u8 dot3stats_symbol_errors_low[0x20];
1521 u8 dot3control_in_unknown_opcodes_high[0x20];
1523 u8 dot3control_in_unknown_opcodes_low[0x20];
1525 u8 dot3in_pause_frames_high[0x20];
1527 u8 dot3in_pause_frames_low[0x20];
1529 u8 dot3out_pause_frames_high[0x20];
1531 u8 dot3out_pause_frames_low[0x20];
1533 u8 reserved_at_400[0x3c0];
1536 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1537 u8 ether_stats_drop_events_high[0x20];
1539 u8 ether_stats_drop_events_low[0x20];
1541 u8 ether_stats_octets_high[0x20];
1543 u8 ether_stats_octets_low[0x20];
1545 u8 ether_stats_pkts_high[0x20];
1547 u8 ether_stats_pkts_low[0x20];
1549 u8 ether_stats_broadcast_pkts_high[0x20];
1551 u8 ether_stats_broadcast_pkts_low[0x20];
1553 u8 ether_stats_multicast_pkts_high[0x20];
1555 u8 ether_stats_multicast_pkts_low[0x20];
1557 u8 ether_stats_crc_align_errors_high[0x20];
1559 u8 ether_stats_crc_align_errors_low[0x20];
1561 u8 ether_stats_undersize_pkts_high[0x20];
1563 u8 ether_stats_undersize_pkts_low[0x20];
1565 u8 ether_stats_oversize_pkts_high[0x20];
1567 u8 ether_stats_oversize_pkts_low[0x20];
1569 u8 ether_stats_fragments_high[0x20];
1571 u8 ether_stats_fragments_low[0x20];
1573 u8 ether_stats_jabbers_high[0x20];
1575 u8 ether_stats_jabbers_low[0x20];
1577 u8 ether_stats_collisions_high[0x20];
1579 u8 ether_stats_collisions_low[0x20];
1581 u8 ether_stats_pkts64octets_high[0x20];
1583 u8 ether_stats_pkts64octets_low[0x20];
1585 u8 ether_stats_pkts65to127octets_high[0x20];
1587 u8 ether_stats_pkts65to127octets_low[0x20];
1589 u8 ether_stats_pkts128to255octets_high[0x20];
1591 u8 ether_stats_pkts128to255octets_low[0x20];
1593 u8 ether_stats_pkts256to511octets_high[0x20];
1595 u8 ether_stats_pkts256to511octets_low[0x20];
1597 u8 ether_stats_pkts512to1023octets_high[0x20];
1599 u8 ether_stats_pkts512to1023octets_low[0x20];
1601 u8 ether_stats_pkts1024to1518octets_high[0x20];
1603 u8 ether_stats_pkts1024to1518octets_low[0x20];
1605 u8 ether_stats_pkts1519to2047octets_high[0x20];
1607 u8 ether_stats_pkts1519to2047octets_low[0x20];
1609 u8 ether_stats_pkts2048to4095octets_high[0x20];
1611 u8 ether_stats_pkts2048to4095octets_low[0x20];
1613 u8 ether_stats_pkts4096to8191octets_high[0x20];
1615 u8 ether_stats_pkts4096to8191octets_low[0x20];
1617 u8 ether_stats_pkts8192to10239octets_high[0x20];
1619 u8 ether_stats_pkts8192to10239octets_low[0x20];
1621 u8 reserved_at_540[0x280];
1624 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1625 u8 if_in_octets_high[0x20];
1627 u8 if_in_octets_low[0x20];
1629 u8 if_in_ucast_pkts_high[0x20];
1631 u8 if_in_ucast_pkts_low[0x20];
1633 u8 if_in_discards_high[0x20];
1635 u8 if_in_discards_low[0x20];
1637 u8 if_in_errors_high[0x20];
1639 u8 if_in_errors_low[0x20];
1641 u8 if_in_unknown_protos_high[0x20];
1643 u8 if_in_unknown_protos_low[0x20];
1645 u8 if_out_octets_high[0x20];
1647 u8 if_out_octets_low[0x20];
1649 u8 if_out_ucast_pkts_high[0x20];
1651 u8 if_out_ucast_pkts_low[0x20];
1653 u8 if_out_discards_high[0x20];
1655 u8 if_out_discards_low[0x20];
1657 u8 if_out_errors_high[0x20];
1659 u8 if_out_errors_low[0x20];
1661 u8 if_in_multicast_pkts_high[0x20];
1663 u8 if_in_multicast_pkts_low[0x20];
1665 u8 if_in_broadcast_pkts_high[0x20];
1667 u8 if_in_broadcast_pkts_low[0x20];
1669 u8 if_out_multicast_pkts_high[0x20];
1671 u8 if_out_multicast_pkts_low[0x20];
1673 u8 if_out_broadcast_pkts_high[0x20];
1675 u8 if_out_broadcast_pkts_low[0x20];
1677 u8 reserved_at_340[0x480];
1680 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1681 u8 a_frames_transmitted_ok_high[0x20];
1683 u8 a_frames_transmitted_ok_low[0x20];
1685 u8 a_frames_received_ok_high[0x20];
1687 u8 a_frames_received_ok_low[0x20];
1689 u8 a_frame_check_sequence_errors_high[0x20];
1691 u8 a_frame_check_sequence_errors_low[0x20];
1693 u8 a_alignment_errors_high[0x20];
1695 u8 a_alignment_errors_low[0x20];
1697 u8 a_octets_transmitted_ok_high[0x20];
1699 u8 a_octets_transmitted_ok_low[0x20];
1701 u8 a_octets_received_ok_high[0x20];
1703 u8 a_octets_received_ok_low[0x20];
1705 u8 a_multicast_frames_xmitted_ok_high[0x20];
1707 u8 a_multicast_frames_xmitted_ok_low[0x20];
1709 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1711 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1713 u8 a_multicast_frames_received_ok_high[0x20];
1715 u8 a_multicast_frames_received_ok_low[0x20];
1717 u8 a_broadcast_frames_received_ok_high[0x20];
1719 u8 a_broadcast_frames_received_ok_low[0x20];
1721 u8 a_in_range_length_errors_high[0x20];
1723 u8 a_in_range_length_errors_low[0x20];
1725 u8 a_out_of_range_length_field_high[0x20];
1727 u8 a_out_of_range_length_field_low[0x20];
1729 u8 a_frame_too_long_errors_high[0x20];
1731 u8 a_frame_too_long_errors_low[0x20];
1733 u8 a_symbol_error_during_carrier_high[0x20];
1735 u8 a_symbol_error_during_carrier_low[0x20];
1737 u8 a_mac_control_frames_transmitted_high[0x20];
1739 u8 a_mac_control_frames_transmitted_low[0x20];
1741 u8 a_mac_control_frames_received_high[0x20];
1743 u8 a_mac_control_frames_received_low[0x20];
1745 u8 a_unsupported_opcodes_received_high[0x20];
1747 u8 a_unsupported_opcodes_received_low[0x20];
1749 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1751 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1753 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1755 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1757 u8 reserved_at_4c0[0x300];
1760 struct mlx5_ifc_cmd_inter_comp_event_bits {
1761 u8 command_completion_vector[0x20];
1763 u8 reserved_at_20[0xc0];
1766 struct mlx5_ifc_stall_vl_event_bits {
1767 u8 reserved_at_0[0x18];
1769 u8 reserved_at_19[0x3];
1772 u8 reserved_at_20[0xa0];
1775 struct mlx5_ifc_db_bf_congestion_event_bits {
1776 u8 event_subtype[0x8];
1777 u8 reserved_at_8[0x8];
1778 u8 congestion_level[0x8];
1779 u8 reserved_at_18[0x8];
1781 u8 reserved_at_20[0xa0];
1784 struct mlx5_ifc_gpio_event_bits {
1785 u8 reserved_at_0[0x60];
1787 u8 gpio_event_hi[0x20];
1789 u8 gpio_event_lo[0x20];
1791 u8 reserved_at_a0[0x40];
1794 struct mlx5_ifc_port_state_change_event_bits {
1795 u8 reserved_at_0[0x40];
1798 u8 reserved_at_44[0x1c];
1800 u8 reserved_at_60[0x80];
1803 struct mlx5_ifc_dropped_packet_logged_bits {
1804 u8 reserved_at_0[0xe0];
1808 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1809 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1812 struct mlx5_ifc_cq_error_bits {
1813 u8 reserved_at_0[0x8];
1816 u8 reserved_at_20[0x20];
1818 u8 reserved_at_40[0x18];
1821 u8 reserved_at_60[0x80];
1824 struct mlx5_ifc_rdma_page_fault_event_bits {
1825 u8 bytes_committed[0x20];
1829 u8 reserved_at_40[0x10];
1830 u8 packet_len[0x10];
1832 u8 rdma_op_len[0x20];
1836 u8 reserved_at_c0[0x5];
1843 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1844 u8 bytes_committed[0x20];
1846 u8 reserved_at_20[0x10];
1849 u8 reserved_at_40[0x10];
1852 u8 reserved_at_60[0x60];
1854 u8 reserved_at_c0[0x5];
1861 struct mlx5_ifc_qp_events_bits {
1862 u8 reserved_at_0[0xa0];
1865 u8 reserved_at_a8[0x18];
1867 u8 reserved_at_c0[0x8];
1868 u8 qpn_rqn_sqn[0x18];
1871 struct mlx5_ifc_dct_events_bits {
1872 u8 reserved_at_0[0xc0];
1874 u8 reserved_at_c0[0x8];
1875 u8 dct_number[0x18];
1878 struct mlx5_ifc_comp_event_bits {
1879 u8 reserved_at_0[0xc0];
1881 u8 reserved_at_c0[0x8];
1886 MLX5_QPC_STATE_RST = 0x0,
1887 MLX5_QPC_STATE_INIT = 0x1,
1888 MLX5_QPC_STATE_RTR = 0x2,
1889 MLX5_QPC_STATE_RTS = 0x3,
1890 MLX5_QPC_STATE_SQER = 0x4,
1891 MLX5_QPC_STATE_ERR = 0x6,
1892 MLX5_QPC_STATE_SQD = 0x7,
1893 MLX5_QPC_STATE_SUSPENDED = 0x9,
1897 MLX5_QPC_ST_RC = 0x0,
1898 MLX5_QPC_ST_UC = 0x1,
1899 MLX5_QPC_ST_UD = 0x2,
1900 MLX5_QPC_ST_XRC = 0x3,
1901 MLX5_QPC_ST_DCI = 0x5,
1902 MLX5_QPC_ST_QP0 = 0x7,
1903 MLX5_QPC_ST_QP1 = 0x8,
1904 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1905 MLX5_QPC_ST_REG_UMR = 0xc,
1909 MLX5_QPC_PM_STATE_ARMED = 0x0,
1910 MLX5_QPC_PM_STATE_REARM = 0x1,
1911 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1912 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1916 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1917 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1921 MLX5_QPC_MTU_256_BYTES = 0x1,
1922 MLX5_QPC_MTU_512_BYTES = 0x2,
1923 MLX5_QPC_MTU_1K_BYTES = 0x3,
1924 MLX5_QPC_MTU_2K_BYTES = 0x4,
1925 MLX5_QPC_MTU_4K_BYTES = 0x5,
1926 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1930 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1931 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1932 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1933 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1934 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1935 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1936 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1937 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1941 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1942 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1943 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1947 MLX5_QPC_CS_RES_DISABLE = 0x0,
1948 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1949 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1952 struct mlx5_ifc_qpc_bits {
1954 u8 lag_tx_port_affinity[0x4];
1956 u8 reserved_at_10[0x3];
1958 u8 reserved_at_15[0x7];
1959 u8 end_padding_mode[0x2];
1960 u8 reserved_at_1e[0x2];
1962 u8 wq_signature[0x1];
1963 u8 block_lb_mc[0x1];
1964 u8 atomic_like_write_en[0x1];
1965 u8 latency_sensitive[0x1];
1966 u8 reserved_at_24[0x1];
1967 u8 drain_sigerr[0x1];
1968 u8 reserved_at_26[0x2];
1972 u8 log_msg_max[0x5];
1973 u8 reserved_at_48[0x1];
1974 u8 log_rq_size[0x4];
1975 u8 log_rq_stride[0x3];
1977 u8 log_sq_size[0x4];
1978 u8 reserved_at_55[0x6];
1980 u8 ulp_stateless_offload_mode[0x4];
1982 u8 counter_set_id[0x8];
1985 u8 reserved_at_80[0x8];
1986 u8 user_index[0x18];
1988 u8 reserved_at_a0[0x3];
1989 u8 log_page_size[0x5];
1990 u8 remote_qpn[0x18];
1992 struct mlx5_ifc_ads_bits primary_address_path;
1994 struct mlx5_ifc_ads_bits secondary_address_path;
1996 u8 log_ack_req_freq[0x4];
1997 u8 reserved_at_384[0x4];
1998 u8 log_sra_max[0x3];
1999 u8 reserved_at_38b[0x2];
2000 u8 retry_count[0x3];
2002 u8 reserved_at_393[0x1];
2004 u8 cur_rnr_retry[0x3];
2005 u8 cur_retry_count[0x3];
2006 u8 reserved_at_39b[0x5];
2008 u8 reserved_at_3a0[0x20];
2010 u8 reserved_at_3c0[0x8];
2011 u8 next_send_psn[0x18];
2013 u8 reserved_at_3e0[0x8];
2016 u8 reserved_at_400[0x8];
2019 u8 reserved_at_420[0x20];
2021 u8 reserved_at_440[0x8];
2022 u8 last_acked_psn[0x18];
2024 u8 reserved_at_460[0x8];
2027 u8 reserved_at_480[0x8];
2028 u8 log_rra_max[0x3];
2029 u8 reserved_at_48b[0x1];
2030 u8 atomic_mode[0x4];
2034 u8 reserved_at_493[0x1];
2035 u8 page_offset[0x6];
2036 u8 reserved_at_49a[0x3];
2037 u8 cd_slave_receive[0x1];
2038 u8 cd_slave_send[0x1];
2041 u8 reserved_at_4a0[0x3];
2042 u8 min_rnr_nak[0x5];
2043 u8 next_rcv_psn[0x18];
2045 u8 reserved_at_4c0[0x8];
2048 u8 reserved_at_4e0[0x8];
2055 u8 reserved_at_560[0x5];
2057 u8 srqn_rmpn_xrqn[0x18];
2059 u8 reserved_at_580[0x8];
2062 u8 hw_sq_wqebb_counter[0x10];
2063 u8 sw_sq_wqebb_counter[0x10];
2065 u8 hw_rq_counter[0x20];
2067 u8 sw_rq_counter[0x20];
2069 u8 reserved_at_600[0x20];
2071 u8 reserved_at_620[0xf];
2076 u8 dc_access_key[0x40];
2078 u8 reserved_at_680[0xc0];
2081 struct mlx5_ifc_roce_addr_layout_bits {
2082 u8 source_l3_address[16][0x8];
2084 u8 reserved_at_80[0x3];
2087 u8 source_mac_47_32[0x10];
2089 u8 source_mac_31_0[0x20];
2091 u8 reserved_at_c0[0x14];
2092 u8 roce_l3_type[0x4];
2093 u8 roce_version[0x8];
2095 u8 reserved_at_e0[0x20];
2098 union mlx5_ifc_hca_cap_union_bits {
2099 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2100 struct mlx5_ifc_odp_cap_bits odp_cap;
2101 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2102 struct mlx5_ifc_roce_cap_bits roce_cap;
2103 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2104 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2105 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2106 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2107 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2108 struct mlx5_ifc_qos_cap_bits qos_cap;
2109 u8 reserved_at_0[0x8000];
2113 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2114 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2115 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2116 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2117 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2118 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2121 struct mlx5_ifc_flow_context_bits {
2122 u8 reserved_at_0[0x20];
2126 u8 reserved_at_40[0x8];
2129 u8 reserved_at_60[0x10];
2132 u8 reserved_at_80[0x8];
2133 u8 destination_list_size[0x18];
2135 u8 reserved_at_a0[0x8];
2136 u8 flow_counter_list_size[0x18];
2140 u8 reserved_at_e0[0x120];
2142 struct mlx5_ifc_fte_match_param_bits match_value;
2144 u8 reserved_at_1200[0x600];
2146 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2150 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2151 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2154 struct mlx5_ifc_xrc_srqc_bits {
2156 u8 log_xrc_srq_size[0x4];
2157 u8 reserved_at_8[0x18];
2159 u8 wq_signature[0x1];
2161 u8 reserved_at_22[0x1];
2163 u8 basic_cyclic_rcv_wqe[0x1];
2164 u8 log_rq_stride[0x3];
2167 u8 page_offset[0x6];
2168 u8 reserved_at_46[0x2];
2171 u8 reserved_at_60[0x20];
2173 u8 user_index_equal_xrc_srqn[0x1];
2174 u8 reserved_at_81[0x1];
2175 u8 log_page_size[0x6];
2176 u8 user_index[0x18];
2178 u8 reserved_at_a0[0x20];
2180 u8 reserved_at_c0[0x8];
2186 u8 reserved_at_100[0x40];
2188 u8 db_record_addr_h[0x20];
2190 u8 db_record_addr_l[0x1e];
2191 u8 reserved_at_17e[0x2];
2193 u8 reserved_at_180[0x80];
2196 struct mlx5_ifc_traffic_counter_bits {
2202 struct mlx5_ifc_tisc_bits {
2203 u8 strict_lag_tx_port_affinity[0x1];
2204 u8 reserved_at_1[0x3];
2205 u8 lag_tx_port_affinity[0x04];
2207 u8 reserved_at_8[0x4];
2209 u8 reserved_at_10[0x10];
2211 u8 reserved_at_20[0x100];
2213 u8 reserved_at_120[0x8];
2214 u8 transport_domain[0x18];
2216 u8 reserved_at_140[0x3c0];
2220 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2221 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2225 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2226 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2230 MLX5_RX_HASH_FN_NONE = 0x0,
2231 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2232 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2236 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2237 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2240 struct mlx5_ifc_tirc_bits {
2241 u8 reserved_at_0[0x20];
2244 u8 reserved_at_24[0x1c];
2246 u8 reserved_at_40[0x40];
2248 u8 reserved_at_80[0x4];
2249 u8 lro_timeout_period_usecs[0x10];
2250 u8 lro_enable_mask[0x4];
2251 u8 lro_max_ip_payload_size[0x8];
2253 u8 reserved_at_a0[0x40];
2255 u8 reserved_at_e0[0x8];
2256 u8 inline_rqn[0x18];
2258 u8 rx_hash_symmetric[0x1];
2259 u8 reserved_at_101[0x1];
2260 u8 tunneled_offload_en[0x1];
2261 u8 reserved_at_103[0x5];
2262 u8 indirect_table[0x18];
2265 u8 reserved_at_124[0x2];
2266 u8 self_lb_block[0x2];
2267 u8 transport_domain[0x18];
2269 u8 rx_hash_toeplitz_key[10][0x20];
2271 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2273 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2275 u8 reserved_at_2c0[0x4c0];
2279 MLX5_SRQC_STATE_GOOD = 0x0,
2280 MLX5_SRQC_STATE_ERROR = 0x1,
2283 struct mlx5_ifc_srqc_bits {
2285 u8 log_srq_size[0x4];
2286 u8 reserved_at_8[0x18];
2288 u8 wq_signature[0x1];
2290 u8 reserved_at_22[0x1];
2292 u8 reserved_at_24[0x1];
2293 u8 log_rq_stride[0x3];
2296 u8 page_offset[0x6];
2297 u8 reserved_at_46[0x2];
2300 u8 reserved_at_60[0x20];
2302 u8 reserved_at_80[0x2];
2303 u8 log_page_size[0x6];
2304 u8 reserved_at_88[0x18];
2306 u8 reserved_at_a0[0x20];
2308 u8 reserved_at_c0[0x8];
2314 u8 reserved_at_100[0x40];
2318 u8 reserved_at_180[0x80];
2322 MLX5_SQC_STATE_RST = 0x0,
2323 MLX5_SQC_STATE_RDY = 0x1,
2324 MLX5_SQC_STATE_ERR = 0x3,
2327 struct mlx5_ifc_sqc_bits {
2331 u8 flush_in_error_en[0x1];
2332 u8 reserved_at_4[0x1];
2333 u8 min_wqe_inline_mode[0x3];
2336 u8 reserved_at_d[0x13];
2338 u8 reserved_at_20[0x8];
2339 u8 user_index[0x18];
2341 u8 reserved_at_40[0x8];
2344 u8 reserved_at_60[0x90];
2346 u8 packet_pacing_rate_limit_index[0x10];
2347 u8 tis_lst_sz[0x10];
2348 u8 reserved_at_110[0x10];
2350 u8 reserved_at_120[0x40];
2352 u8 reserved_at_160[0x8];
2355 struct mlx5_ifc_wq_bits wq;
2359 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2360 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2361 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2362 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2365 struct mlx5_ifc_scheduling_context_bits {
2366 u8 element_type[0x8];
2367 u8 reserved_at_8[0x18];
2369 u8 element_attributes[0x20];
2371 u8 parent_element_id[0x20];
2373 u8 reserved_at_60[0x40];
2377 u8 max_average_bw[0x20];
2379 u8 reserved_at_e0[0x120];
2382 struct mlx5_ifc_rqtc_bits {
2383 u8 reserved_at_0[0xa0];
2385 u8 reserved_at_a0[0x10];
2386 u8 rqt_max_size[0x10];
2388 u8 reserved_at_c0[0x10];
2389 u8 rqt_actual_size[0x10];
2391 u8 reserved_at_e0[0x6a0];
2393 struct mlx5_ifc_rq_num_bits rq_num[0];
2397 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2398 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2402 MLX5_RQC_STATE_RST = 0x0,
2403 MLX5_RQC_STATE_RDY = 0x1,
2404 MLX5_RQC_STATE_ERR = 0x3,
2407 struct mlx5_ifc_rqc_bits {
2409 u8 reserved_at_1[0x1];
2410 u8 scatter_fcs[0x1];
2412 u8 mem_rq_type[0x4];
2414 u8 reserved_at_c[0x1];
2415 u8 flush_in_error_en[0x1];
2416 u8 reserved_at_e[0x12];
2418 u8 reserved_at_20[0x8];
2419 u8 user_index[0x18];
2421 u8 reserved_at_40[0x8];
2424 u8 counter_set_id[0x8];
2425 u8 reserved_at_68[0x18];
2427 u8 reserved_at_80[0x8];
2430 u8 reserved_at_a0[0xe0];
2432 struct mlx5_ifc_wq_bits wq;
2436 MLX5_RMPC_STATE_RDY = 0x1,
2437 MLX5_RMPC_STATE_ERR = 0x3,
2440 struct mlx5_ifc_rmpc_bits {
2441 u8 reserved_at_0[0x8];
2443 u8 reserved_at_c[0x14];
2445 u8 basic_cyclic_rcv_wqe[0x1];
2446 u8 reserved_at_21[0x1f];
2448 u8 reserved_at_40[0x140];
2450 struct mlx5_ifc_wq_bits wq;
2453 struct mlx5_ifc_nic_vport_context_bits {
2454 u8 reserved_at_0[0x5];
2455 u8 min_wqe_inline_mode[0x3];
2456 u8 reserved_at_8[0x17];
2459 u8 arm_change_event[0x1];
2460 u8 reserved_at_21[0x1a];
2461 u8 event_on_mtu[0x1];
2462 u8 event_on_promisc_change[0x1];
2463 u8 event_on_vlan_change[0x1];
2464 u8 event_on_mc_address_change[0x1];
2465 u8 event_on_uc_address_change[0x1];
2467 u8 reserved_at_40[0xf0];
2471 u8 system_image_guid[0x40];
2475 u8 reserved_at_200[0x140];
2476 u8 qkey_violation_counter[0x10];
2477 u8 reserved_at_350[0x430];
2481 u8 promisc_all[0x1];
2482 u8 reserved_at_783[0x2];
2483 u8 allowed_list_type[0x3];
2484 u8 reserved_at_788[0xc];
2485 u8 allowed_list_size[0xc];
2487 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2489 u8 reserved_at_7e0[0x20];
2491 u8 current_uc_mac_address[0][0x40];
2495 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2496 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2497 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2500 struct mlx5_ifc_mkc_bits {
2501 u8 reserved_at_0[0x1];
2503 u8 reserved_at_2[0xd];
2504 u8 small_fence_on_rdma_read_response[0x1];
2511 u8 access_mode[0x2];
2512 u8 reserved_at_18[0x8];
2517 u8 reserved_at_40[0x20];
2522 u8 reserved_at_63[0x2];
2523 u8 expected_sigerr_count[0x1];
2524 u8 reserved_at_66[0x1];
2528 u8 start_addr[0x40];
2532 u8 bsf_octword_size[0x20];
2534 u8 reserved_at_120[0x80];
2536 u8 translations_octword_size[0x20];
2538 u8 reserved_at_1c0[0x1b];
2539 u8 log_page_size[0x5];
2541 u8 reserved_at_1e0[0x20];
2544 struct mlx5_ifc_pkey_bits {
2545 u8 reserved_at_0[0x10];
2549 struct mlx5_ifc_array128_auto_bits {
2550 u8 array128_auto[16][0x8];
2553 struct mlx5_ifc_hca_vport_context_bits {
2554 u8 field_select[0x20];
2556 u8 reserved_at_20[0xe0];
2558 u8 sm_virt_aware[0x1];
2561 u8 grh_required[0x1];
2562 u8 reserved_at_104[0xc];
2563 u8 port_physical_state[0x4];
2564 u8 vport_state_policy[0x4];
2566 u8 vport_state[0x4];
2568 u8 reserved_at_120[0x20];
2570 u8 system_image_guid[0x40];
2578 u8 cap_mask1_field_select[0x20];
2582 u8 cap_mask2_field_select[0x20];
2584 u8 reserved_at_280[0x80];
2587 u8 reserved_at_310[0x4];
2588 u8 init_type_reply[0x4];
2590 u8 subnet_timeout[0x5];
2594 u8 reserved_at_334[0xc];
2596 u8 qkey_violation_counter[0x10];
2597 u8 pkey_violation_counter[0x10];
2599 u8 reserved_at_360[0xca0];
2602 struct mlx5_ifc_esw_vport_context_bits {
2603 u8 reserved_at_0[0x3];
2604 u8 vport_svlan_strip[0x1];
2605 u8 vport_cvlan_strip[0x1];
2606 u8 vport_svlan_insert[0x1];
2607 u8 vport_cvlan_insert[0x2];
2608 u8 reserved_at_8[0x18];
2610 u8 reserved_at_20[0x20];
2619 u8 reserved_at_60[0x7a0];
2623 MLX5_EQC_STATUS_OK = 0x0,
2624 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2628 MLX5_EQC_ST_ARMED = 0x9,
2629 MLX5_EQC_ST_FIRED = 0xa,
2632 struct mlx5_ifc_eqc_bits {
2634 u8 reserved_at_4[0x9];
2637 u8 reserved_at_f[0x5];
2639 u8 reserved_at_18[0x8];
2641 u8 reserved_at_20[0x20];
2643 u8 reserved_at_40[0x14];
2644 u8 page_offset[0x6];
2645 u8 reserved_at_5a[0x6];
2647 u8 reserved_at_60[0x3];
2648 u8 log_eq_size[0x5];
2651 u8 reserved_at_80[0x20];
2653 u8 reserved_at_a0[0x18];
2656 u8 reserved_at_c0[0x3];
2657 u8 log_page_size[0x5];
2658 u8 reserved_at_c8[0x18];
2660 u8 reserved_at_e0[0x60];
2662 u8 reserved_at_140[0x8];
2663 u8 consumer_counter[0x18];
2665 u8 reserved_at_160[0x8];
2666 u8 producer_counter[0x18];
2668 u8 reserved_at_180[0x80];
2672 MLX5_DCTC_STATE_ACTIVE = 0x0,
2673 MLX5_DCTC_STATE_DRAINING = 0x1,
2674 MLX5_DCTC_STATE_DRAINED = 0x2,
2678 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2679 MLX5_DCTC_CS_RES_NA = 0x1,
2680 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2684 MLX5_DCTC_MTU_256_BYTES = 0x1,
2685 MLX5_DCTC_MTU_512_BYTES = 0x2,
2686 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2687 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2688 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2691 struct mlx5_ifc_dctc_bits {
2692 u8 reserved_at_0[0x4];
2694 u8 reserved_at_8[0x18];
2696 u8 reserved_at_20[0x8];
2697 u8 user_index[0x18];
2699 u8 reserved_at_40[0x8];
2702 u8 counter_set_id[0x8];
2703 u8 atomic_mode[0x4];
2707 u8 atomic_like_write_en[0x1];
2708 u8 latency_sensitive[0x1];
2711 u8 reserved_at_73[0xd];
2713 u8 reserved_at_80[0x8];
2715 u8 reserved_at_90[0x3];
2716 u8 min_rnr_nak[0x5];
2717 u8 reserved_at_98[0x8];
2719 u8 reserved_at_a0[0x8];
2722 u8 reserved_at_c0[0x8];
2726 u8 reserved_at_e8[0x4];
2727 u8 flow_label[0x14];
2729 u8 dc_access_key[0x40];
2731 u8 reserved_at_140[0x5];
2734 u8 pkey_index[0x10];
2736 u8 reserved_at_160[0x8];
2737 u8 my_addr_index[0x8];
2738 u8 reserved_at_170[0x8];
2741 u8 dc_access_key_violation_count[0x20];
2743 u8 reserved_at_1a0[0x14];
2749 u8 reserved_at_1c0[0x40];
2753 MLX5_CQC_STATUS_OK = 0x0,
2754 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2755 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2759 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2760 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2764 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2765 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2766 MLX5_CQC_ST_FIRED = 0xa,
2770 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2771 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2772 MLX5_CQ_PERIOD_NUM_MODES
2775 struct mlx5_ifc_cqc_bits {
2777 u8 reserved_at_4[0x4];
2780 u8 reserved_at_c[0x1];
2781 u8 scqe_break_moderation_en[0x1];
2783 u8 cq_period_mode[0x2];
2784 u8 cqe_comp_en[0x1];
2785 u8 mini_cqe_res_format[0x2];
2787 u8 reserved_at_18[0x8];
2789 u8 reserved_at_20[0x20];
2791 u8 reserved_at_40[0x14];
2792 u8 page_offset[0x6];
2793 u8 reserved_at_5a[0x6];
2795 u8 reserved_at_60[0x3];
2796 u8 log_cq_size[0x5];
2799 u8 reserved_at_80[0x4];
2801 u8 cq_max_count[0x10];
2803 u8 reserved_at_a0[0x18];
2806 u8 reserved_at_c0[0x3];
2807 u8 log_page_size[0x5];
2808 u8 reserved_at_c8[0x18];
2810 u8 reserved_at_e0[0x20];
2812 u8 reserved_at_100[0x8];
2813 u8 last_notified_index[0x18];
2815 u8 reserved_at_120[0x8];
2816 u8 last_solicit_index[0x18];
2818 u8 reserved_at_140[0x8];
2819 u8 consumer_counter[0x18];
2821 u8 reserved_at_160[0x8];
2822 u8 producer_counter[0x18];
2824 u8 reserved_at_180[0x40];
2829 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2830 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2831 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2832 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2833 u8 reserved_at_0[0x800];
2836 struct mlx5_ifc_query_adapter_param_block_bits {
2837 u8 reserved_at_0[0xc0];
2839 u8 reserved_at_c0[0x8];
2840 u8 ieee_vendor_id[0x18];
2842 u8 reserved_at_e0[0x10];
2843 u8 vsd_vendor_id[0x10];
2847 u8 vsd_contd_psid[16][0x8];
2851 MLX5_XRQC_STATE_GOOD = 0x0,
2852 MLX5_XRQC_STATE_ERROR = 0x1,
2856 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2857 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2861 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2864 struct mlx5_ifc_tag_matching_topology_context_bits {
2865 u8 log_matching_list_sz[0x4];
2866 u8 reserved_at_4[0xc];
2867 u8 append_next_index[0x10];
2869 u8 sw_phase_cnt[0x10];
2870 u8 hw_phase_cnt[0x10];
2872 u8 reserved_at_40[0x40];
2875 struct mlx5_ifc_xrqc_bits {
2878 u8 reserved_at_5[0xf];
2880 u8 reserved_at_18[0x4];
2883 u8 reserved_at_20[0x8];
2884 u8 user_index[0x18];
2886 u8 reserved_at_40[0x8];
2889 u8 reserved_at_60[0xa0];
2891 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2893 u8 reserved_at_180[0x880];
2895 struct mlx5_ifc_wq_bits wq;
2898 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2899 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2900 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2901 u8 reserved_at_0[0x20];
2904 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2905 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2906 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2907 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2908 u8 reserved_at_0[0x20];
2911 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2912 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2913 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2914 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2915 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2916 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2917 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2918 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2919 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2920 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2921 u8 reserved_at_0[0x7c0];
2924 union mlx5_ifc_event_auto_bits {
2925 struct mlx5_ifc_comp_event_bits comp_event;
2926 struct mlx5_ifc_dct_events_bits dct_events;
2927 struct mlx5_ifc_qp_events_bits qp_events;
2928 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2929 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2930 struct mlx5_ifc_cq_error_bits cq_error;
2931 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2932 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2933 struct mlx5_ifc_gpio_event_bits gpio_event;
2934 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2935 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2936 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2937 u8 reserved_at_0[0xe0];
2940 struct mlx5_ifc_health_buffer_bits {
2941 u8 reserved_at_0[0x100];
2943 u8 assert_existptr[0x20];
2945 u8 assert_callra[0x20];
2947 u8 reserved_at_140[0x40];
2949 u8 fw_version[0x20];
2953 u8 reserved_at_1c0[0x20];
2955 u8 irisc_index[0x8];
2960 struct mlx5_ifc_register_loopback_control_bits {
2962 u8 reserved_at_1[0x7];
2964 u8 reserved_at_10[0x10];
2966 u8 reserved_at_20[0x60];
2969 struct mlx5_ifc_vport_tc_element_bits {
2970 u8 traffic_class[0x4];
2971 u8 reserved_at_4[0xc];
2972 u8 vport_number[0x10];
2975 struct mlx5_ifc_vport_element_bits {
2976 u8 reserved_at_0[0x10];
2977 u8 vport_number[0x10];
2981 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2982 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2983 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2986 struct mlx5_ifc_tsar_element_bits {
2987 u8 reserved_at_0[0x8];
2989 u8 reserved_at_10[0x10];
2992 struct mlx5_ifc_teardown_hca_out_bits {
2994 u8 reserved_at_8[0x18];
2998 u8 reserved_at_40[0x40];
3002 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3003 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3006 struct mlx5_ifc_teardown_hca_in_bits {
3008 u8 reserved_at_10[0x10];
3010 u8 reserved_at_20[0x10];
3013 u8 reserved_at_40[0x10];
3016 u8 reserved_at_60[0x20];
3019 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3021 u8 reserved_at_8[0x18];
3025 u8 reserved_at_40[0x40];
3028 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3030 u8 reserved_at_10[0x10];
3032 u8 reserved_at_20[0x10];
3035 u8 reserved_at_40[0x8];
3038 u8 reserved_at_60[0x20];
3040 u8 opt_param_mask[0x20];
3042 u8 reserved_at_a0[0x20];
3044 struct mlx5_ifc_qpc_bits qpc;
3046 u8 reserved_at_800[0x80];
3049 struct mlx5_ifc_sqd2rts_qp_out_bits {
3051 u8 reserved_at_8[0x18];
3055 u8 reserved_at_40[0x40];
3058 struct mlx5_ifc_sqd2rts_qp_in_bits {
3060 u8 reserved_at_10[0x10];
3062 u8 reserved_at_20[0x10];
3065 u8 reserved_at_40[0x8];
3068 u8 reserved_at_60[0x20];
3070 u8 opt_param_mask[0x20];
3072 u8 reserved_at_a0[0x20];
3074 struct mlx5_ifc_qpc_bits qpc;
3076 u8 reserved_at_800[0x80];
3079 struct mlx5_ifc_set_roce_address_out_bits {
3081 u8 reserved_at_8[0x18];
3085 u8 reserved_at_40[0x40];
3088 struct mlx5_ifc_set_roce_address_in_bits {
3090 u8 reserved_at_10[0x10];
3092 u8 reserved_at_20[0x10];
3095 u8 roce_address_index[0x10];
3096 u8 reserved_at_50[0x10];
3098 u8 reserved_at_60[0x20];
3100 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3103 struct mlx5_ifc_set_mad_demux_out_bits {
3105 u8 reserved_at_8[0x18];
3109 u8 reserved_at_40[0x40];
3113 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3114 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3117 struct mlx5_ifc_set_mad_demux_in_bits {
3119 u8 reserved_at_10[0x10];
3121 u8 reserved_at_20[0x10];
3124 u8 reserved_at_40[0x20];
3126 u8 reserved_at_60[0x6];
3128 u8 reserved_at_68[0x18];
3131 struct mlx5_ifc_set_l2_table_entry_out_bits {
3133 u8 reserved_at_8[0x18];
3137 u8 reserved_at_40[0x40];
3140 struct mlx5_ifc_set_l2_table_entry_in_bits {
3142 u8 reserved_at_10[0x10];
3144 u8 reserved_at_20[0x10];
3147 u8 reserved_at_40[0x60];
3149 u8 reserved_at_a0[0x8];
3150 u8 table_index[0x18];
3152 u8 reserved_at_c0[0x20];
3154 u8 reserved_at_e0[0x13];
3158 struct mlx5_ifc_mac_address_layout_bits mac_address;
3160 u8 reserved_at_140[0xc0];
3163 struct mlx5_ifc_set_issi_out_bits {
3165 u8 reserved_at_8[0x18];
3169 u8 reserved_at_40[0x40];
3172 struct mlx5_ifc_set_issi_in_bits {
3174 u8 reserved_at_10[0x10];
3176 u8 reserved_at_20[0x10];
3179 u8 reserved_at_40[0x10];
3180 u8 current_issi[0x10];
3182 u8 reserved_at_60[0x20];
3185 struct mlx5_ifc_set_hca_cap_out_bits {
3187 u8 reserved_at_8[0x18];
3191 u8 reserved_at_40[0x40];
3194 struct mlx5_ifc_set_hca_cap_in_bits {
3196 u8 reserved_at_10[0x10];
3198 u8 reserved_at_20[0x10];
3201 u8 reserved_at_40[0x40];
3203 union mlx5_ifc_hca_cap_union_bits capability;
3207 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3208 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3209 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3210 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3213 struct mlx5_ifc_set_fte_out_bits {
3215 u8 reserved_at_8[0x18];
3219 u8 reserved_at_40[0x40];
3222 struct mlx5_ifc_set_fte_in_bits {
3224 u8 reserved_at_10[0x10];
3226 u8 reserved_at_20[0x10];
3229 u8 other_vport[0x1];
3230 u8 reserved_at_41[0xf];
3231 u8 vport_number[0x10];
3233 u8 reserved_at_60[0x20];
3236 u8 reserved_at_88[0x18];
3238 u8 reserved_at_a0[0x8];
3241 u8 reserved_at_c0[0x18];
3242 u8 modify_enable_mask[0x8];
3244 u8 reserved_at_e0[0x20];
3246 u8 flow_index[0x20];
3248 u8 reserved_at_120[0xe0];
3250 struct mlx5_ifc_flow_context_bits flow_context;
3253 struct mlx5_ifc_rts2rts_qp_out_bits {
3255 u8 reserved_at_8[0x18];
3259 u8 reserved_at_40[0x40];
3262 struct mlx5_ifc_rts2rts_qp_in_bits {
3264 u8 reserved_at_10[0x10];
3266 u8 reserved_at_20[0x10];
3269 u8 reserved_at_40[0x8];
3272 u8 reserved_at_60[0x20];
3274 u8 opt_param_mask[0x20];
3276 u8 reserved_at_a0[0x20];
3278 struct mlx5_ifc_qpc_bits qpc;
3280 u8 reserved_at_800[0x80];
3283 struct mlx5_ifc_rtr2rts_qp_out_bits {
3285 u8 reserved_at_8[0x18];
3289 u8 reserved_at_40[0x40];
3292 struct mlx5_ifc_rtr2rts_qp_in_bits {
3294 u8 reserved_at_10[0x10];
3296 u8 reserved_at_20[0x10];
3299 u8 reserved_at_40[0x8];
3302 u8 reserved_at_60[0x20];
3304 u8 opt_param_mask[0x20];
3306 u8 reserved_at_a0[0x20];
3308 struct mlx5_ifc_qpc_bits qpc;
3310 u8 reserved_at_800[0x80];
3313 struct mlx5_ifc_rst2init_qp_out_bits {
3315 u8 reserved_at_8[0x18];
3319 u8 reserved_at_40[0x40];
3322 struct mlx5_ifc_rst2init_qp_in_bits {
3324 u8 reserved_at_10[0x10];
3326 u8 reserved_at_20[0x10];
3329 u8 reserved_at_40[0x8];
3332 u8 reserved_at_60[0x20];
3334 u8 opt_param_mask[0x20];
3336 u8 reserved_at_a0[0x20];
3338 struct mlx5_ifc_qpc_bits qpc;
3340 u8 reserved_at_800[0x80];
3343 struct mlx5_ifc_query_xrq_out_bits {
3345 u8 reserved_at_8[0x18];
3349 u8 reserved_at_40[0x40];
3351 struct mlx5_ifc_xrqc_bits xrq_context;
3354 struct mlx5_ifc_query_xrq_in_bits {
3356 u8 reserved_at_10[0x10];
3358 u8 reserved_at_20[0x10];
3361 u8 reserved_at_40[0x8];
3364 u8 reserved_at_60[0x20];
3367 struct mlx5_ifc_query_xrc_srq_out_bits {
3369 u8 reserved_at_8[0x18];
3373 u8 reserved_at_40[0x40];
3375 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3377 u8 reserved_at_280[0x600];
3382 struct mlx5_ifc_query_xrc_srq_in_bits {
3384 u8 reserved_at_10[0x10];
3386 u8 reserved_at_20[0x10];
3389 u8 reserved_at_40[0x8];
3392 u8 reserved_at_60[0x20];
3396 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3397 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3400 struct mlx5_ifc_query_vport_state_out_bits {
3402 u8 reserved_at_8[0x18];
3406 u8 reserved_at_40[0x20];
3408 u8 reserved_at_60[0x18];
3409 u8 admin_state[0x4];
3414 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3415 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3418 struct mlx5_ifc_query_vport_state_in_bits {
3420 u8 reserved_at_10[0x10];
3422 u8 reserved_at_20[0x10];
3425 u8 other_vport[0x1];
3426 u8 reserved_at_41[0xf];
3427 u8 vport_number[0x10];
3429 u8 reserved_at_60[0x20];
3432 struct mlx5_ifc_query_vport_counter_out_bits {
3434 u8 reserved_at_8[0x18];
3438 u8 reserved_at_40[0x40];
3440 struct mlx5_ifc_traffic_counter_bits received_errors;
3442 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3444 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3446 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3448 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3450 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3452 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3454 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3456 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3458 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3460 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3462 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3464 u8 reserved_at_680[0xa00];
3468 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3471 struct mlx5_ifc_query_vport_counter_in_bits {
3473 u8 reserved_at_10[0x10];
3475 u8 reserved_at_20[0x10];
3478 u8 other_vport[0x1];
3479 u8 reserved_at_41[0xb];
3481 u8 vport_number[0x10];
3483 u8 reserved_at_60[0x60];
3486 u8 reserved_at_c1[0x1f];
3488 u8 reserved_at_e0[0x20];
3491 struct mlx5_ifc_query_tis_out_bits {
3493 u8 reserved_at_8[0x18];
3497 u8 reserved_at_40[0x40];
3499 struct mlx5_ifc_tisc_bits tis_context;
3502 struct mlx5_ifc_query_tis_in_bits {
3504 u8 reserved_at_10[0x10];
3506 u8 reserved_at_20[0x10];
3509 u8 reserved_at_40[0x8];
3512 u8 reserved_at_60[0x20];
3515 struct mlx5_ifc_query_tir_out_bits {
3517 u8 reserved_at_8[0x18];
3521 u8 reserved_at_40[0xc0];
3523 struct mlx5_ifc_tirc_bits tir_context;
3526 struct mlx5_ifc_query_tir_in_bits {
3528 u8 reserved_at_10[0x10];
3530 u8 reserved_at_20[0x10];
3533 u8 reserved_at_40[0x8];
3536 u8 reserved_at_60[0x20];
3539 struct mlx5_ifc_query_srq_out_bits {
3541 u8 reserved_at_8[0x18];
3545 u8 reserved_at_40[0x40];
3547 struct mlx5_ifc_srqc_bits srq_context_entry;
3549 u8 reserved_at_280[0x600];
3554 struct mlx5_ifc_query_srq_in_bits {
3556 u8 reserved_at_10[0x10];
3558 u8 reserved_at_20[0x10];
3561 u8 reserved_at_40[0x8];
3564 u8 reserved_at_60[0x20];
3567 struct mlx5_ifc_query_sq_out_bits {
3569 u8 reserved_at_8[0x18];
3573 u8 reserved_at_40[0xc0];
3575 struct mlx5_ifc_sqc_bits sq_context;
3578 struct mlx5_ifc_query_sq_in_bits {
3580 u8 reserved_at_10[0x10];
3582 u8 reserved_at_20[0x10];
3585 u8 reserved_at_40[0x8];
3588 u8 reserved_at_60[0x20];
3591 struct mlx5_ifc_query_special_contexts_out_bits {
3593 u8 reserved_at_8[0x18];
3597 u8 dump_fill_mkey[0x20];
3602 struct mlx5_ifc_query_special_contexts_in_bits {
3604 u8 reserved_at_10[0x10];
3606 u8 reserved_at_20[0x10];
3609 u8 reserved_at_40[0x40];
3612 struct mlx5_ifc_query_scheduling_element_out_bits {
3614 u8 reserved_at_10[0x10];
3616 u8 reserved_at_20[0x10];
3619 u8 reserved_at_40[0xc0];
3621 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3623 u8 reserved_at_300[0x100];
3627 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3630 struct mlx5_ifc_query_scheduling_element_in_bits {
3632 u8 reserved_at_10[0x10];
3634 u8 reserved_at_20[0x10];
3637 u8 scheduling_hierarchy[0x8];
3638 u8 reserved_at_48[0x18];
3640 u8 scheduling_element_id[0x20];
3642 u8 reserved_at_80[0x180];
3645 struct mlx5_ifc_query_rqt_out_bits {
3647 u8 reserved_at_8[0x18];
3651 u8 reserved_at_40[0xc0];
3653 struct mlx5_ifc_rqtc_bits rqt_context;
3656 struct mlx5_ifc_query_rqt_in_bits {
3658 u8 reserved_at_10[0x10];
3660 u8 reserved_at_20[0x10];
3663 u8 reserved_at_40[0x8];
3666 u8 reserved_at_60[0x20];
3669 struct mlx5_ifc_query_rq_out_bits {
3671 u8 reserved_at_8[0x18];
3675 u8 reserved_at_40[0xc0];
3677 struct mlx5_ifc_rqc_bits rq_context;
3680 struct mlx5_ifc_query_rq_in_bits {
3682 u8 reserved_at_10[0x10];
3684 u8 reserved_at_20[0x10];
3687 u8 reserved_at_40[0x8];
3690 u8 reserved_at_60[0x20];
3693 struct mlx5_ifc_query_roce_address_out_bits {
3695 u8 reserved_at_8[0x18];
3699 u8 reserved_at_40[0x40];
3701 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3704 struct mlx5_ifc_query_roce_address_in_bits {
3706 u8 reserved_at_10[0x10];
3708 u8 reserved_at_20[0x10];
3711 u8 roce_address_index[0x10];
3712 u8 reserved_at_50[0x10];
3714 u8 reserved_at_60[0x20];
3717 struct mlx5_ifc_query_rmp_out_bits {
3719 u8 reserved_at_8[0x18];
3723 u8 reserved_at_40[0xc0];
3725 struct mlx5_ifc_rmpc_bits rmp_context;
3728 struct mlx5_ifc_query_rmp_in_bits {
3730 u8 reserved_at_10[0x10];
3732 u8 reserved_at_20[0x10];
3735 u8 reserved_at_40[0x8];
3738 u8 reserved_at_60[0x20];
3741 struct mlx5_ifc_query_qp_out_bits {
3743 u8 reserved_at_8[0x18];
3747 u8 reserved_at_40[0x40];
3749 u8 opt_param_mask[0x20];
3751 u8 reserved_at_a0[0x20];
3753 struct mlx5_ifc_qpc_bits qpc;
3755 u8 reserved_at_800[0x80];
3760 struct mlx5_ifc_query_qp_in_bits {
3762 u8 reserved_at_10[0x10];
3764 u8 reserved_at_20[0x10];
3767 u8 reserved_at_40[0x8];
3770 u8 reserved_at_60[0x20];
3773 struct mlx5_ifc_query_q_counter_out_bits {
3775 u8 reserved_at_8[0x18];
3779 u8 reserved_at_40[0x40];
3781 u8 rx_write_requests[0x20];
3783 u8 reserved_at_a0[0x20];
3785 u8 rx_read_requests[0x20];
3787 u8 reserved_at_e0[0x20];
3789 u8 rx_atomic_requests[0x20];
3791 u8 reserved_at_120[0x20];
3793 u8 rx_dct_connect[0x20];
3795 u8 reserved_at_160[0x20];
3797 u8 out_of_buffer[0x20];
3799 u8 reserved_at_1a0[0x20];
3801 u8 out_of_sequence[0x20];
3803 u8 reserved_at_1e0[0x20];
3805 u8 duplicate_request[0x20];
3807 u8 reserved_at_220[0x20];
3809 u8 rnr_nak_retry_err[0x20];
3811 u8 reserved_at_260[0x20];
3813 u8 packet_seq_err[0x20];
3815 u8 reserved_at_2a0[0x20];
3817 u8 implied_nak_seq_err[0x20];
3819 u8 reserved_at_2e0[0x20];
3821 u8 local_ack_timeout_err[0x20];
3823 u8 reserved_at_320[0x4e0];
3826 struct mlx5_ifc_query_q_counter_in_bits {
3828 u8 reserved_at_10[0x10];
3830 u8 reserved_at_20[0x10];
3833 u8 reserved_at_40[0x80];
3836 u8 reserved_at_c1[0x1f];
3838 u8 reserved_at_e0[0x18];
3839 u8 counter_set_id[0x8];
3842 struct mlx5_ifc_query_pages_out_bits {
3844 u8 reserved_at_8[0x18];
3848 u8 reserved_at_40[0x10];
3849 u8 function_id[0x10];
3855 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3856 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3857 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3860 struct mlx5_ifc_query_pages_in_bits {
3862 u8 reserved_at_10[0x10];
3864 u8 reserved_at_20[0x10];
3867 u8 reserved_at_40[0x10];
3868 u8 function_id[0x10];
3870 u8 reserved_at_60[0x20];
3873 struct mlx5_ifc_query_nic_vport_context_out_bits {
3875 u8 reserved_at_8[0x18];
3879 u8 reserved_at_40[0x40];
3881 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3884 struct mlx5_ifc_query_nic_vport_context_in_bits {
3886 u8 reserved_at_10[0x10];
3888 u8 reserved_at_20[0x10];
3891 u8 other_vport[0x1];
3892 u8 reserved_at_41[0xf];
3893 u8 vport_number[0x10];
3895 u8 reserved_at_60[0x5];
3896 u8 allowed_list_type[0x3];
3897 u8 reserved_at_68[0x18];
3900 struct mlx5_ifc_query_mkey_out_bits {
3902 u8 reserved_at_8[0x18];
3906 u8 reserved_at_40[0x40];
3908 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3910 u8 reserved_at_280[0x600];
3912 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3914 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3917 struct mlx5_ifc_query_mkey_in_bits {
3919 u8 reserved_at_10[0x10];
3921 u8 reserved_at_20[0x10];
3924 u8 reserved_at_40[0x8];
3925 u8 mkey_index[0x18];
3928 u8 reserved_at_61[0x1f];
3931 struct mlx5_ifc_query_mad_demux_out_bits {
3933 u8 reserved_at_8[0x18];
3937 u8 reserved_at_40[0x40];
3939 u8 mad_dumux_parameters_block[0x20];
3942 struct mlx5_ifc_query_mad_demux_in_bits {
3944 u8 reserved_at_10[0x10];
3946 u8 reserved_at_20[0x10];
3949 u8 reserved_at_40[0x40];
3952 struct mlx5_ifc_query_l2_table_entry_out_bits {
3954 u8 reserved_at_8[0x18];
3958 u8 reserved_at_40[0xa0];
3960 u8 reserved_at_e0[0x13];
3964 struct mlx5_ifc_mac_address_layout_bits mac_address;
3966 u8 reserved_at_140[0xc0];
3969 struct mlx5_ifc_query_l2_table_entry_in_bits {
3971 u8 reserved_at_10[0x10];
3973 u8 reserved_at_20[0x10];
3976 u8 reserved_at_40[0x60];
3978 u8 reserved_at_a0[0x8];
3979 u8 table_index[0x18];
3981 u8 reserved_at_c0[0x140];
3984 struct mlx5_ifc_query_issi_out_bits {
3986 u8 reserved_at_8[0x18];
3990 u8 reserved_at_40[0x10];
3991 u8 current_issi[0x10];
3993 u8 reserved_at_60[0xa0];
3995 u8 reserved_at_100[76][0x8];
3996 u8 supported_issi_dw0[0x20];
3999 struct mlx5_ifc_query_issi_in_bits {
4001 u8 reserved_at_10[0x10];
4003 u8 reserved_at_20[0x10];
4006 u8 reserved_at_40[0x40];
4009 struct mlx5_ifc_set_driver_version_out_bits {
4011 u8 reserved_0[0x18];
4014 u8 reserved_1[0x40];
4017 struct mlx5_ifc_set_driver_version_in_bits {
4019 u8 reserved_0[0x10];
4021 u8 reserved_1[0x10];
4024 u8 reserved_2[0x40];
4025 u8 driver_version[64][0x8];
4028 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4030 u8 reserved_at_8[0x18];
4034 u8 reserved_at_40[0x40];
4036 struct mlx5_ifc_pkey_bits pkey[0];
4039 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4041 u8 reserved_at_10[0x10];
4043 u8 reserved_at_20[0x10];
4046 u8 other_vport[0x1];
4047 u8 reserved_at_41[0xb];
4049 u8 vport_number[0x10];
4051 u8 reserved_at_60[0x10];
4052 u8 pkey_index[0x10];
4056 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4057 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4058 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4061 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4063 u8 reserved_at_8[0x18];
4067 u8 reserved_at_40[0x20];
4070 u8 reserved_at_70[0x10];
4072 struct mlx5_ifc_array128_auto_bits gid[0];
4075 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4077 u8 reserved_at_10[0x10];
4079 u8 reserved_at_20[0x10];
4082 u8 other_vport[0x1];
4083 u8 reserved_at_41[0xb];
4085 u8 vport_number[0x10];
4087 u8 reserved_at_60[0x10];
4091 struct mlx5_ifc_query_hca_vport_context_out_bits {
4093 u8 reserved_at_8[0x18];
4097 u8 reserved_at_40[0x40];
4099 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4102 struct mlx5_ifc_query_hca_vport_context_in_bits {
4104 u8 reserved_at_10[0x10];
4106 u8 reserved_at_20[0x10];
4109 u8 other_vport[0x1];
4110 u8 reserved_at_41[0xb];
4112 u8 vport_number[0x10];
4114 u8 reserved_at_60[0x20];
4117 struct mlx5_ifc_query_hca_cap_out_bits {
4119 u8 reserved_at_8[0x18];
4123 u8 reserved_at_40[0x40];
4125 union mlx5_ifc_hca_cap_union_bits capability;
4128 struct mlx5_ifc_query_hca_cap_in_bits {
4130 u8 reserved_at_10[0x10];
4132 u8 reserved_at_20[0x10];
4135 u8 reserved_at_40[0x40];
4138 struct mlx5_ifc_query_flow_table_out_bits {
4140 u8 reserved_at_8[0x18];
4144 u8 reserved_at_40[0x80];
4146 u8 reserved_at_c0[0x8];
4148 u8 reserved_at_d0[0x8];
4151 u8 reserved_at_e0[0x120];
4154 struct mlx5_ifc_query_flow_table_in_bits {
4156 u8 reserved_at_10[0x10];
4158 u8 reserved_at_20[0x10];
4161 u8 reserved_at_40[0x40];
4164 u8 reserved_at_88[0x18];
4166 u8 reserved_at_a0[0x8];
4169 u8 reserved_at_c0[0x140];
4172 struct mlx5_ifc_query_fte_out_bits {
4174 u8 reserved_at_8[0x18];
4178 u8 reserved_at_40[0x1c0];
4180 struct mlx5_ifc_flow_context_bits flow_context;
4183 struct mlx5_ifc_query_fte_in_bits {
4185 u8 reserved_at_10[0x10];
4187 u8 reserved_at_20[0x10];
4190 u8 reserved_at_40[0x40];
4193 u8 reserved_at_88[0x18];
4195 u8 reserved_at_a0[0x8];
4198 u8 reserved_at_c0[0x40];
4200 u8 flow_index[0x20];
4202 u8 reserved_at_120[0xe0];
4206 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4207 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4208 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4211 struct mlx5_ifc_query_flow_group_out_bits {
4213 u8 reserved_at_8[0x18];
4217 u8 reserved_at_40[0xa0];
4219 u8 start_flow_index[0x20];
4221 u8 reserved_at_100[0x20];
4223 u8 end_flow_index[0x20];
4225 u8 reserved_at_140[0xa0];
4227 u8 reserved_at_1e0[0x18];
4228 u8 match_criteria_enable[0x8];
4230 struct mlx5_ifc_fte_match_param_bits match_criteria;
4232 u8 reserved_at_1200[0xe00];
4235 struct mlx5_ifc_query_flow_group_in_bits {
4237 u8 reserved_at_10[0x10];
4239 u8 reserved_at_20[0x10];
4242 u8 reserved_at_40[0x40];
4245 u8 reserved_at_88[0x18];
4247 u8 reserved_at_a0[0x8];
4252 u8 reserved_at_e0[0x120];
4255 struct mlx5_ifc_query_flow_counter_out_bits {
4257 u8 reserved_at_8[0x18];
4261 u8 reserved_at_40[0x40];
4263 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4266 struct mlx5_ifc_query_flow_counter_in_bits {
4268 u8 reserved_at_10[0x10];
4270 u8 reserved_at_20[0x10];
4273 u8 reserved_at_40[0x80];
4276 u8 reserved_at_c1[0xf];
4277 u8 num_of_counters[0x10];
4279 u8 reserved_at_e0[0x10];
4280 u8 flow_counter_id[0x10];
4283 struct mlx5_ifc_query_esw_vport_context_out_bits {
4285 u8 reserved_at_8[0x18];
4289 u8 reserved_at_40[0x40];
4291 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4294 struct mlx5_ifc_query_esw_vport_context_in_bits {
4296 u8 reserved_at_10[0x10];
4298 u8 reserved_at_20[0x10];
4301 u8 other_vport[0x1];
4302 u8 reserved_at_41[0xf];
4303 u8 vport_number[0x10];
4305 u8 reserved_at_60[0x20];
4308 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4310 u8 reserved_at_8[0x18];
4314 u8 reserved_at_40[0x40];
4317 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4318 u8 reserved_at_0[0x1c];
4319 u8 vport_cvlan_insert[0x1];
4320 u8 vport_svlan_insert[0x1];
4321 u8 vport_cvlan_strip[0x1];
4322 u8 vport_svlan_strip[0x1];
4325 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4327 u8 reserved_at_10[0x10];
4329 u8 reserved_at_20[0x10];
4332 u8 other_vport[0x1];
4333 u8 reserved_at_41[0xf];
4334 u8 vport_number[0x10];
4336 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4338 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4341 struct mlx5_ifc_query_eq_out_bits {
4343 u8 reserved_at_8[0x18];
4347 u8 reserved_at_40[0x40];
4349 struct mlx5_ifc_eqc_bits eq_context_entry;
4351 u8 reserved_at_280[0x40];
4353 u8 event_bitmask[0x40];
4355 u8 reserved_at_300[0x580];
4360 struct mlx5_ifc_query_eq_in_bits {
4362 u8 reserved_at_10[0x10];
4364 u8 reserved_at_20[0x10];
4367 u8 reserved_at_40[0x18];
4370 u8 reserved_at_60[0x20];
4373 struct mlx5_ifc_encap_header_in_bits {
4374 u8 reserved_at_0[0x5];
4375 u8 header_type[0x3];
4376 u8 reserved_at_8[0xe];
4377 u8 encap_header_size[0xa];
4379 u8 reserved_at_20[0x10];
4380 u8 encap_header[2][0x8];
4382 u8 more_encap_header[0][0x8];
4385 struct mlx5_ifc_query_encap_header_out_bits {
4387 u8 reserved_at_8[0x18];
4391 u8 reserved_at_40[0xa0];
4393 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4396 struct mlx5_ifc_query_encap_header_in_bits {
4398 u8 reserved_at_10[0x10];
4400 u8 reserved_at_20[0x10];
4405 u8 reserved_at_60[0xa0];
4408 struct mlx5_ifc_alloc_encap_header_out_bits {
4410 u8 reserved_at_8[0x18];
4416 u8 reserved_at_60[0x20];
4419 struct mlx5_ifc_alloc_encap_header_in_bits {
4421 u8 reserved_at_10[0x10];
4423 u8 reserved_at_20[0x10];
4426 u8 reserved_at_40[0xa0];
4428 struct mlx5_ifc_encap_header_in_bits encap_header;
4431 struct mlx5_ifc_dealloc_encap_header_out_bits {
4433 u8 reserved_at_8[0x18];
4437 u8 reserved_at_40[0x40];
4440 struct mlx5_ifc_dealloc_encap_header_in_bits {
4442 u8 reserved_at_10[0x10];
4444 u8 reserved_20[0x10];
4449 u8 reserved_60[0x20];
4452 struct mlx5_ifc_query_dct_out_bits {
4454 u8 reserved_at_8[0x18];
4458 u8 reserved_at_40[0x40];
4460 struct mlx5_ifc_dctc_bits dct_context_entry;
4462 u8 reserved_at_280[0x180];
4465 struct mlx5_ifc_query_dct_in_bits {
4467 u8 reserved_at_10[0x10];
4469 u8 reserved_at_20[0x10];
4472 u8 reserved_at_40[0x8];
4475 u8 reserved_at_60[0x20];
4478 struct mlx5_ifc_query_cq_out_bits {
4480 u8 reserved_at_8[0x18];
4484 u8 reserved_at_40[0x40];
4486 struct mlx5_ifc_cqc_bits cq_context;
4488 u8 reserved_at_280[0x600];
4493 struct mlx5_ifc_query_cq_in_bits {
4495 u8 reserved_at_10[0x10];
4497 u8 reserved_at_20[0x10];
4500 u8 reserved_at_40[0x8];
4503 u8 reserved_at_60[0x20];
4506 struct mlx5_ifc_query_cong_status_out_bits {
4508 u8 reserved_at_8[0x18];
4512 u8 reserved_at_40[0x20];
4516 u8 reserved_at_62[0x1e];
4519 struct mlx5_ifc_query_cong_status_in_bits {
4521 u8 reserved_at_10[0x10];
4523 u8 reserved_at_20[0x10];
4526 u8 reserved_at_40[0x18];
4528 u8 cong_protocol[0x4];
4530 u8 reserved_at_60[0x20];
4533 struct mlx5_ifc_query_cong_statistics_out_bits {
4535 u8 reserved_at_8[0x18];
4539 u8 reserved_at_40[0x40];
4545 u8 cnp_ignored_high[0x20];
4547 u8 cnp_ignored_low[0x20];
4549 u8 cnp_handled_high[0x20];
4551 u8 cnp_handled_low[0x20];
4553 u8 reserved_at_140[0x100];
4555 u8 time_stamp_high[0x20];
4557 u8 time_stamp_low[0x20];
4559 u8 accumulators_period[0x20];
4561 u8 ecn_marked_roce_packets_high[0x20];
4563 u8 ecn_marked_roce_packets_low[0x20];
4565 u8 cnps_sent_high[0x20];
4567 u8 cnps_sent_low[0x20];
4569 u8 reserved_at_320[0x560];
4572 struct mlx5_ifc_query_cong_statistics_in_bits {
4574 u8 reserved_at_10[0x10];
4576 u8 reserved_at_20[0x10];
4580 u8 reserved_at_41[0x1f];
4582 u8 reserved_at_60[0x20];
4585 struct mlx5_ifc_query_cong_params_out_bits {
4587 u8 reserved_at_8[0x18];
4591 u8 reserved_at_40[0x40];
4593 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4596 struct mlx5_ifc_query_cong_params_in_bits {
4598 u8 reserved_at_10[0x10];
4600 u8 reserved_at_20[0x10];
4603 u8 reserved_at_40[0x1c];
4604 u8 cong_protocol[0x4];
4606 u8 reserved_at_60[0x20];
4609 struct mlx5_ifc_query_adapter_out_bits {
4611 u8 reserved_at_8[0x18];
4615 u8 reserved_at_40[0x40];
4617 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4620 struct mlx5_ifc_query_adapter_in_bits {
4622 u8 reserved_at_10[0x10];
4624 u8 reserved_at_20[0x10];
4627 u8 reserved_at_40[0x40];
4630 struct mlx5_ifc_qp_2rst_out_bits {
4632 u8 reserved_at_8[0x18];
4636 u8 reserved_at_40[0x40];
4639 struct mlx5_ifc_qp_2rst_in_bits {
4641 u8 reserved_at_10[0x10];
4643 u8 reserved_at_20[0x10];
4646 u8 reserved_at_40[0x8];
4649 u8 reserved_at_60[0x20];
4652 struct mlx5_ifc_qp_2err_out_bits {
4654 u8 reserved_at_8[0x18];
4658 u8 reserved_at_40[0x40];
4661 struct mlx5_ifc_qp_2err_in_bits {
4663 u8 reserved_at_10[0x10];
4665 u8 reserved_at_20[0x10];
4668 u8 reserved_at_40[0x8];
4671 u8 reserved_at_60[0x20];
4674 struct mlx5_ifc_page_fault_resume_out_bits {
4676 u8 reserved_at_8[0x18];
4680 u8 reserved_at_40[0x40];
4683 struct mlx5_ifc_page_fault_resume_in_bits {
4685 u8 reserved_at_10[0x10];
4687 u8 reserved_at_20[0x10];
4691 u8 reserved_at_41[0x4];
4697 u8 reserved_at_60[0x20];
4700 struct mlx5_ifc_nop_out_bits {
4702 u8 reserved_at_8[0x18];
4706 u8 reserved_at_40[0x40];
4709 struct mlx5_ifc_nop_in_bits {
4711 u8 reserved_at_10[0x10];
4713 u8 reserved_at_20[0x10];
4716 u8 reserved_at_40[0x40];
4719 struct mlx5_ifc_modify_vport_state_out_bits {
4721 u8 reserved_at_8[0x18];
4725 u8 reserved_at_40[0x40];
4728 struct mlx5_ifc_modify_vport_state_in_bits {
4730 u8 reserved_at_10[0x10];
4732 u8 reserved_at_20[0x10];
4735 u8 other_vport[0x1];
4736 u8 reserved_at_41[0xf];
4737 u8 vport_number[0x10];
4739 u8 reserved_at_60[0x18];
4740 u8 admin_state[0x4];
4741 u8 reserved_at_7c[0x4];
4744 struct mlx5_ifc_modify_tis_out_bits {
4746 u8 reserved_at_8[0x18];
4750 u8 reserved_at_40[0x40];
4753 struct mlx5_ifc_modify_tis_bitmask_bits {
4754 u8 reserved_at_0[0x20];
4756 u8 reserved_at_20[0x1d];
4757 u8 lag_tx_port_affinity[0x1];
4758 u8 strict_lag_tx_port_affinity[0x1];
4762 struct mlx5_ifc_modify_tis_in_bits {
4764 u8 reserved_at_10[0x10];
4766 u8 reserved_at_20[0x10];
4769 u8 reserved_at_40[0x8];
4772 u8 reserved_at_60[0x20];
4774 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4776 u8 reserved_at_c0[0x40];
4778 struct mlx5_ifc_tisc_bits ctx;
4781 struct mlx5_ifc_modify_tir_bitmask_bits {
4782 u8 reserved_at_0[0x20];
4784 u8 reserved_at_20[0x1b];
4786 u8 reserved_at_3c[0x1];
4788 u8 reserved_at_3e[0x1];
4792 struct mlx5_ifc_modify_tir_out_bits {
4794 u8 reserved_at_8[0x18];
4798 u8 reserved_at_40[0x40];
4801 struct mlx5_ifc_modify_tir_in_bits {
4803 u8 reserved_at_10[0x10];
4805 u8 reserved_at_20[0x10];
4808 u8 reserved_at_40[0x8];
4811 u8 reserved_at_60[0x20];
4813 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4815 u8 reserved_at_c0[0x40];
4817 struct mlx5_ifc_tirc_bits ctx;
4820 struct mlx5_ifc_modify_sq_out_bits {
4822 u8 reserved_at_8[0x18];
4826 u8 reserved_at_40[0x40];
4829 struct mlx5_ifc_modify_sq_in_bits {
4831 u8 reserved_at_10[0x10];
4833 u8 reserved_at_20[0x10];
4837 u8 reserved_at_44[0x4];
4840 u8 reserved_at_60[0x20];
4842 u8 modify_bitmask[0x40];
4844 u8 reserved_at_c0[0x40];
4846 struct mlx5_ifc_sqc_bits ctx;
4849 struct mlx5_ifc_modify_scheduling_element_out_bits {
4851 u8 reserved_at_8[0x18];
4855 u8 reserved_at_40[0x1c0];
4859 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4860 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4863 struct mlx5_ifc_modify_scheduling_element_in_bits {
4865 u8 reserved_at_10[0x10];
4867 u8 reserved_at_20[0x10];
4870 u8 scheduling_hierarchy[0x8];
4871 u8 reserved_at_48[0x18];
4873 u8 scheduling_element_id[0x20];
4875 u8 reserved_at_80[0x20];
4877 u8 modify_bitmask[0x20];
4879 u8 reserved_at_c0[0x40];
4881 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4883 u8 reserved_at_300[0x100];
4886 struct mlx5_ifc_modify_rqt_out_bits {
4888 u8 reserved_at_8[0x18];
4892 u8 reserved_at_40[0x40];
4895 struct mlx5_ifc_rqt_bitmask_bits {
4896 u8 reserved_at_0[0x20];
4898 u8 reserved_at_20[0x1f];
4902 struct mlx5_ifc_modify_rqt_in_bits {
4904 u8 reserved_at_10[0x10];
4906 u8 reserved_at_20[0x10];
4909 u8 reserved_at_40[0x8];
4912 u8 reserved_at_60[0x20];
4914 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4916 u8 reserved_at_c0[0x40];
4918 struct mlx5_ifc_rqtc_bits ctx;
4921 struct mlx5_ifc_modify_rq_out_bits {
4923 u8 reserved_at_8[0x18];
4927 u8 reserved_at_40[0x40];
4931 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4932 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4935 struct mlx5_ifc_modify_rq_in_bits {
4937 u8 reserved_at_10[0x10];
4939 u8 reserved_at_20[0x10];
4943 u8 reserved_at_44[0x4];
4946 u8 reserved_at_60[0x20];
4948 u8 modify_bitmask[0x40];
4950 u8 reserved_at_c0[0x40];
4952 struct mlx5_ifc_rqc_bits ctx;
4955 struct mlx5_ifc_modify_rmp_out_bits {
4957 u8 reserved_at_8[0x18];
4961 u8 reserved_at_40[0x40];
4964 struct mlx5_ifc_rmp_bitmask_bits {
4965 u8 reserved_at_0[0x20];
4967 u8 reserved_at_20[0x1f];
4971 struct mlx5_ifc_modify_rmp_in_bits {
4973 u8 reserved_at_10[0x10];
4975 u8 reserved_at_20[0x10];
4979 u8 reserved_at_44[0x4];
4982 u8 reserved_at_60[0x20];
4984 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4986 u8 reserved_at_c0[0x40];
4988 struct mlx5_ifc_rmpc_bits ctx;
4991 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4993 u8 reserved_at_8[0x18];
4997 u8 reserved_at_40[0x40];
5000 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5001 u8 reserved_at_0[0x16];
5006 u8 change_event[0x1];
5008 u8 permanent_address[0x1];
5009 u8 addresses_list[0x1];
5011 u8 reserved_at_1f[0x1];
5014 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5016 u8 reserved_at_10[0x10];
5018 u8 reserved_at_20[0x10];
5021 u8 other_vport[0x1];
5022 u8 reserved_at_41[0xf];
5023 u8 vport_number[0x10];
5025 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5027 u8 reserved_at_80[0x780];
5029 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5032 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5034 u8 reserved_at_8[0x18];
5038 u8 reserved_at_40[0x40];
5041 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5043 u8 reserved_at_10[0x10];
5045 u8 reserved_at_20[0x10];
5048 u8 other_vport[0x1];
5049 u8 reserved_at_41[0xb];
5051 u8 vport_number[0x10];
5053 u8 reserved_at_60[0x20];
5055 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5058 struct mlx5_ifc_modify_cq_out_bits {
5060 u8 reserved_at_8[0x18];
5064 u8 reserved_at_40[0x40];
5068 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5069 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5072 struct mlx5_ifc_modify_cq_in_bits {
5074 u8 reserved_at_10[0x10];
5076 u8 reserved_at_20[0x10];
5079 u8 reserved_at_40[0x8];
5082 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5084 struct mlx5_ifc_cqc_bits cq_context;
5086 u8 reserved_at_280[0x600];
5091 struct mlx5_ifc_modify_cong_status_out_bits {
5093 u8 reserved_at_8[0x18];
5097 u8 reserved_at_40[0x40];
5100 struct mlx5_ifc_modify_cong_status_in_bits {
5102 u8 reserved_at_10[0x10];
5104 u8 reserved_at_20[0x10];
5107 u8 reserved_at_40[0x18];
5109 u8 cong_protocol[0x4];
5113 u8 reserved_at_62[0x1e];
5116 struct mlx5_ifc_modify_cong_params_out_bits {
5118 u8 reserved_at_8[0x18];
5122 u8 reserved_at_40[0x40];
5125 struct mlx5_ifc_modify_cong_params_in_bits {
5127 u8 reserved_at_10[0x10];
5129 u8 reserved_at_20[0x10];
5132 u8 reserved_at_40[0x1c];
5133 u8 cong_protocol[0x4];
5135 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5137 u8 reserved_at_80[0x80];
5139 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5142 struct mlx5_ifc_manage_pages_out_bits {
5144 u8 reserved_at_8[0x18];
5148 u8 output_num_entries[0x20];
5150 u8 reserved_at_60[0x20];
5156 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5157 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5158 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5161 struct mlx5_ifc_manage_pages_in_bits {
5163 u8 reserved_at_10[0x10];
5165 u8 reserved_at_20[0x10];
5168 u8 reserved_at_40[0x10];
5169 u8 function_id[0x10];
5171 u8 input_num_entries[0x20];
5176 struct mlx5_ifc_mad_ifc_out_bits {
5178 u8 reserved_at_8[0x18];
5182 u8 reserved_at_40[0x40];
5184 u8 response_mad_packet[256][0x8];
5187 struct mlx5_ifc_mad_ifc_in_bits {
5189 u8 reserved_at_10[0x10];
5191 u8 reserved_at_20[0x10];
5194 u8 remote_lid[0x10];
5195 u8 reserved_at_50[0x8];
5198 u8 reserved_at_60[0x20];
5203 struct mlx5_ifc_init_hca_out_bits {
5205 u8 reserved_at_8[0x18];
5209 u8 reserved_at_40[0x40];
5212 struct mlx5_ifc_init_hca_in_bits {
5214 u8 reserved_at_10[0x10];
5216 u8 reserved_at_20[0x10];
5219 u8 reserved_at_40[0x40];
5222 struct mlx5_ifc_init2rtr_qp_out_bits {
5224 u8 reserved_at_8[0x18];
5228 u8 reserved_at_40[0x40];
5231 struct mlx5_ifc_init2rtr_qp_in_bits {
5233 u8 reserved_at_10[0x10];
5235 u8 reserved_at_20[0x10];
5238 u8 reserved_at_40[0x8];
5241 u8 reserved_at_60[0x20];
5243 u8 opt_param_mask[0x20];
5245 u8 reserved_at_a0[0x20];
5247 struct mlx5_ifc_qpc_bits qpc;
5249 u8 reserved_at_800[0x80];
5252 struct mlx5_ifc_init2init_qp_out_bits {
5254 u8 reserved_at_8[0x18];
5258 u8 reserved_at_40[0x40];
5261 struct mlx5_ifc_init2init_qp_in_bits {
5263 u8 reserved_at_10[0x10];
5265 u8 reserved_at_20[0x10];
5268 u8 reserved_at_40[0x8];
5271 u8 reserved_at_60[0x20];
5273 u8 opt_param_mask[0x20];
5275 u8 reserved_at_a0[0x20];
5277 struct mlx5_ifc_qpc_bits qpc;
5279 u8 reserved_at_800[0x80];
5282 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5284 u8 reserved_at_8[0x18];
5288 u8 reserved_at_40[0x40];
5290 u8 packet_headers_log[128][0x8];
5292 u8 packet_syndrome[64][0x8];
5295 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5297 u8 reserved_at_10[0x10];
5299 u8 reserved_at_20[0x10];
5302 u8 reserved_at_40[0x40];
5305 struct mlx5_ifc_gen_eqe_in_bits {
5307 u8 reserved_at_10[0x10];
5309 u8 reserved_at_20[0x10];
5312 u8 reserved_at_40[0x18];
5315 u8 reserved_at_60[0x20];
5320 struct mlx5_ifc_gen_eq_out_bits {
5322 u8 reserved_at_8[0x18];
5326 u8 reserved_at_40[0x40];
5329 struct mlx5_ifc_enable_hca_out_bits {
5331 u8 reserved_at_8[0x18];
5335 u8 reserved_at_40[0x20];
5338 struct mlx5_ifc_enable_hca_in_bits {
5340 u8 reserved_at_10[0x10];
5342 u8 reserved_at_20[0x10];
5345 u8 reserved_at_40[0x10];
5346 u8 function_id[0x10];
5348 u8 reserved_at_60[0x20];
5351 struct mlx5_ifc_drain_dct_out_bits {
5353 u8 reserved_at_8[0x18];
5357 u8 reserved_at_40[0x40];
5360 struct mlx5_ifc_drain_dct_in_bits {
5362 u8 reserved_at_10[0x10];
5364 u8 reserved_at_20[0x10];
5367 u8 reserved_at_40[0x8];
5370 u8 reserved_at_60[0x20];
5373 struct mlx5_ifc_disable_hca_out_bits {
5375 u8 reserved_at_8[0x18];
5379 u8 reserved_at_40[0x20];
5382 struct mlx5_ifc_disable_hca_in_bits {
5384 u8 reserved_at_10[0x10];
5386 u8 reserved_at_20[0x10];
5389 u8 reserved_at_40[0x10];
5390 u8 function_id[0x10];
5392 u8 reserved_at_60[0x20];
5395 struct mlx5_ifc_detach_from_mcg_out_bits {
5397 u8 reserved_at_8[0x18];
5401 u8 reserved_at_40[0x40];
5404 struct mlx5_ifc_detach_from_mcg_in_bits {
5406 u8 reserved_at_10[0x10];
5408 u8 reserved_at_20[0x10];
5411 u8 reserved_at_40[0x8];
5414 u8 reserved_at_60[0x20];
5416 u8 multicast_gid[16][0x8];
5419 struct mlx5_ifc_destroy_xrq_out_bits {
5421 u8 reserved_at_8[0x18];
5425 u8 reserved_at_40[0x40];
5428 struct mlx5_ifc_destroy_xrq_in_bits {
5430 u8 reserved_at_10[0x10];
5432 u8 reserved_at_20[0x10];
5435 u8 reserved_at_40[0x8];
5438 u8 reserved_at_60[0x20];
5441 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5443 u8 reserved_at_8[0x18];
5447 u8 reserved_at_40[0x40];
5450 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5452 u8 reserved_at_10[0x10];
5454 u8 reserved_at_20[0x10];
5457 u8 reserved_at_40[0x8];
5460 u8 reserved_at_60[0x20];
5463 struct mlx5_ifc_destroy_tis_out_bits {
5465 u8 reserved_at_8[0x18];
5469 u8 reserved_at_40[0x40];
5472 struct mlx5_ifc_destroy_tis_in_bits {
5474 u8 reserved_at_10[0x10];
5476 u8 reserved_at_20[0x10];
5479 u8 reserved_at_40[0x8];
5482 u8 reserved_at_60[0x20];
5485 struct mlx5_ifc_destroy_tir_out_bits {
5487 u8 reserved_at_8[0x18];
5491 u8 reserved_at_40[0x40];
5494 struct mlx5_ifc_destroy_tir_in_bits {
5496 u8 reserved_at_10[0x10];
5498 u8 reserved_at_20[0x10];
5501 u8 reserved_at_40[0x8];
5504 u8 reserved_at_60[0x20];
5507 struct mlx5_ifc_destroy_srq_out_bits {
5509 u8 reserved_at_8[0x18];
5513 u8 reserved_at_40[0x40];
5516 struct mlx5_ifc_destroy_srq_in_bits {
5518 u8 reserved_at_10[0x10];
5520 u8 reserved_at_20[0x10];
5523 u8 reserved_at_40[0x8];
5526 u8 reserved_at_60[0x20];
5529 struct mlx5_ifc_destroy_sq_out_bits {
5531 u8 reserved_at_8[0x18];
5535 u8 reserved_at_40[0x40];
5538 struct mlx5_ifc_destroy_sq_in_bits {
5540 u8 reserved_at_10[0x10];
5542 u8 reserved_at_20[0x10];
5545 u8 reserved_at_40[0x8];
5548 u8 reserved_at_60[0x20];
5551 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5553 u8 reserved_at_8[0x18];
5557 u8 reserved_at_40[0x1c0];
5560 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5562 u8 reserved_at_10[0x10];
5564 u8 reserved_at_20[0x10];
5567 u8 scheduling_hierarchy[0x8];
5568 u8 reserved_at_48[0x18];
5570 u8 scheduling_element_id[0x20];
5572 u8 reserved_at_80[0x180];
5575 struct mlx5_ifc_destroy_rqt_out_bits {
5577 u8 reserved_at_8[0x18];
5581 u8 reserved_at_40[0x40];
5584 struct mlx5_ifc_destroy_rqt_in_bits {
5586 u8 reserved_at_10[0x10];
5588 u8 reserved_at_20[0x10];
5591 u8 reserved_at_40[0x8];
5594 u8 reserved_at_60[0x20];
5597 struct mlx5_ifc_destroy_rq_out_bits {
5599 u8 reserved_at_8[0x18];
5603 u8 reserved_at_40[0x40];
5606 struct mlx5_ifc_destroy_rq_in_bits {
5608 u8 reserved_at_10[0x10];
5610 u8 reserved_at_20[0x10];
5613 u8 reserved_at_40[0x8];
5616 u8 reserved_at_60[0x20];
5619 struct mlx5_ifc_destroy_rmp_out_bits {
5621 u8 reserved_at_8[0x18];
5625 u8 reserved_at_40[0x40];
5628 struct mlx5_ifc_destroy_rmp_in_bits {
5630 u8 reserved_at_10[0x10];
5632 u8 reserved_at_20[0x10];
5635 u8 reserved_at_40[0x8];
5638 u8 reserved_at_60[0x20];
5641 struct mlx5_ifc_destroy_qp_out_bits {
5643 u8 reserved_at_8[0x18];
5647 u8 reserved_at_40[0x40];
5650 struct mlx5_ifc_destroy_qp_in_bits {
5652 u8 reserved_at_10[0x10];
5654 u8 reserved_at_20[0x10];
5657 u8 reserved_at_40[0x8];
5660 u8 reserved_at_60[0x20];
5663 struct mlx5_ifc_destroy_psv_out_bits {
5665 u8 reserved_at_8[0x18];
5669 u8 reserved_at_40[0x40];
5672 struct mlx5_ifc_destroy_psv_in_bits {
5674 u8 reserved_at_10[0x10];
5676 u8 reserved_at_20[0x10];
5679 u8 reserved_at_40[0x8];
5682 u8 reserved_at_60[0x20];
5685 struct mlx5_ifc_destroy_mkey_out_bits {
5687 u8 reserved_at_8[0x18];
5691 u8 reserved_at_40[0x40];
5694 struct mlx5_ifc_destroy_mkey_in_bits {
5696 u8 reserved_at_10[0x10];
5698 u8 reserved_at_20[0x10];
5701 u8 reserved_at_40[0x8];
5702 u8 mkey_index[0x18];
5704 u8 reserved_at_60[0x20];
5707 struct mlx5_ifc_destroy_flow_table_out_bits {
5709 u8 reserved_at_8[0x18];
5713 u8 reserved_at_40[0x40];
5716 struct mlx5_ifc_destroy_flow_table_in_bits {
5718 u8 reserved_at_10[0x10];
5720 u8 reserved_at_20[0x10];
5723 u8 other_vport[0x1];
5724 u8 reserved_at_41[0xf];
5725 u8 vport_number[0x10];
5727 u8 reserved_at_60[0x20];
5730 u8 reserved_at_88[0x18];
5732 u8 reserved_at_a0[0x8];
5735 u8 reserved_at_c0[0x140];
5738 struct mlx5_ifc_destroy_flow_group_out_bits {
5740 u8 reserved_at_8[0x18];
5744 u8 reserved_at_40[0x40];
5747 struct mlx5_ifc_destroy_flow_group_in_bits {
5749 u8 reserved_at_10[0x10];
5751 u8 reserved_at_20[0x10];
5754 u8 other_vport[0x1];
5755 u8 reserved_at_41[0xf];
5756 u8 vport_number[0x10];
5758 u8 reserved_at_60[0x20];
5761 u8 reserved_at_88[0x18];
5763 u8 reserved_at_a0[0x8];
5768 u8 reserved_at_e0[0x120];
5771 struct mlx5_ifc_destroy_eq_out_bits {
5773 u8 reserved_at_8[0x18];
5777 u8 reserved_at_40[0x40];
5780 struct mlx5_ifc_destroy_eq_in_bits {
5782 u8 reserved_at_10[0x10];
5784 u8 reserved_at_20[0x10];
5787 u8 reserved_at_40[0x18];
5790 u8 reserved_at_60[0x20];
5793 struct mlx5_ifc_destroy_dct_out_bits {
5795 u8 reserved_at_8[0x18];
5799 u8 reserved_at_40[0x40];
5802 struct mlx5_ifc_destroy_dct_in_bits {
5804 u8 reserved_at_10[0x10];
5806 u8 reserved_at_20[0x10];
5809 u8 reserved_at_40[0x8];
5812 u8 reserved_at_60[0x20];
5815 struct mlx5_ifc_destroy_cq_out_bits {
5817 u8 reserved_at_8[0x18];
5821 u8 reserved_at_40[0x40];
5824 struct mlx5_ifc_destroy_cq_in_bits {
5826 u8 reserved_at_10[0x10];
5828 u8 reserved_at_20[0x10];
5831 u8 reserved_at_40[0x8];
5834 u8 reserved_at_60[0x20];
5837 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5839 u8 reserved_at_8[0x18];
5843 u8 reserved_at_40[0x40];
5846 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5848 u8 reserved_at_10[0x10];
5850 u8 reserved_at_20[0x10];
5853 u8 reserved_at_40[0x20];
5855 u8 reserved_at_60[0x10];
5856 u8 vxlan_udp_port[0x10];
5859 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5861 u8 reserved_at_8[0x18];
5865 u8 reserved_at_40[0x40];
5868 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5870 u8 reserved_at_10[0x10];
5872 u8 reserved_at_20[0x10];
5875 u8 reserved_at_40[0x60];
5877 u8 reserved_at_a0[0x8];
5878 u8 table_index[0x18];
5880 u8 reserved_at_c0[0x140];
5883 struct mlx5_ifc_delete_fte_out_bits {
5885 u8 reserved_at_8[0x18];
5889 u8 reserved_at_40[0x40];
5892 struct mlx5_ifc_delete_fte_in_bits {
5894 u8 reserved_at_10[0x10];
5896 u8 reserved_at_20[0x10];
5899 u8 other_vport[0x1];
5900 u8 reserved_at_41[0xf];
5901 u8 vport_number[0x10];
5903 u8 reserved_at_60[0x20];
5906 u8 reserved_at_88[0x18];
5908 u8 reserved_at_a0[0x8];
5911 u8 reserved_at_c0[0x40];
5913 u8 flow_index[0x20];
5915 u8 reserved_at_120[0xe0];
5918 struct mlx5_ifc_dealloc_xrcd_out_bits {
5920 u8 reserved_at_8[0x18];
5924 u8 reserved_at_40[0x40];
5927 struct mlx5_ifc_dealloc_xrcd_in_bits {
5929 u8 reserved_at_10[0x10];
5931 u8 reserved_at_20[0x10];
5934 u8 reserved_at_40[0x8];
5937 u8 reserved_at_60[0x20];
5940 struct mlx5_ifc_dealloc_uar_out_bits {
5942 u8 reserved_at_8[0x18];
5946 u8 reserved_at_40[0x40];
5949 struct mlx5_ifc_dealloc_uar_in_bits {
5951 u8 reserved_at_10[0x10];
5953 u8 reserved_at_20[0x10];
5956 u8 reserved_at_40[0x8];
5959 u8 reserved_at_60[0x20];
5962 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5964 u8 reserved_at_8[0x18];
5968 u8 reserved_at_40[0x40];
5971 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5973 u8 reserved_at_10[0x10];
5975 u8 reserved_at_20[0x10];
5978 u8 reserved_at_40[0x8];
5979 u8 transport_domain[0x18];
5981 u8 reserved_at_60[0x20];
5984 struct mlx5_ifc_dealloc_q_counter_out_bits {
5986 u8 reserved_at_8[0x18];
5990 u8 reserved_at_40[0x40];
5993 struct mlx5_ifc_dealloc_q_counter_in_bits {
5995 u8 reserved_at_10[0x10];
5997 u8 reserved_at_20[0x10];
6000 u8 reserved_at_40[0x18];
6001 u8 counter_set_id[0x8];
6003 u8 reserved_at_60[0x20];
6006 struct mlx5_ifc_dealloc_pd_out_bits {
6008 u8 reserved_at_8[0x18];
6012 u8 reserved_at_40[0x40];
6015 struct mlx5_ifc_dealloc_pd_in_bits {
6017 u8 reserved_at_10[0x10];
6019 u8 reserved_at_20[0x10];
6022 u8 reserved_at_40[0x8];
6025 u8 reserved_at_60[0x20];
6028 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6030 u8 reserved_at_8[0x18];
6034 u8 reserved_at_40[0x40];
6037 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6039 u8 reserved_at_10[0x10];
6041 u8 reserved_at_20[0x10];
6044 u8 reserved_at_40[0x10];
6045 u8 flow_counter_id[0x10];
6047 u8 reserved_at_60[0x20];
6050 struct mlx5_ifc_create_xrq_out_bits {
6052 u8 reserved_at_8[0x18];
6056 u8 reserved_at_40[0x8];
6059 u8 reserved_at_60[0x20];
6062 struct mlx5_ifc_create_xrq_in_bits {
6064 u8 reserved_at_10[0x10];
6066 u8 reserved_at_20[0x10];
6069 u8 reserved_at_40[0x40];
6071 struct mlx5_ifc_xrqc_bits xrq_context;
6074 struct mlx5_ifc_create_xrc_srq_out_bits {
6076 u8 reserved_at_8[0x18];
6080 u8 reserved_at_40[0x8];
6083 u8 reserved_at_60[0x20];
6086 struct mlx5_ifc_create_xrc_srq_in_bits {
6088 u8 reserved_at_10[0x10];
6090 u8 reserved_at_20[0x10];
6093 u8 reserved_at_40[0x40];
6095 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6097 u8 reserved_at_280[0x600];
6102 struct mlx5_ifc_create_tis_out_bits {
6104 u8 reserved_at_8[0x18];
6108 u8 reserved_at_40[0x8];
6111 u8 reserved_at_60[0x20];
6114 struct mlx5_ifc_create_tis_in_bits {
6116 u8 reserved_at_10[0x10];
6118 u8 reserved_at_20[0x10];
6121 u8 reserved_at_40[0xc0];
6123 struct mlx5_ifc_tisc_bits ctx;
6126 struct mlx5_ifc_create_tir_out_bits {
6128 u8 reserved_at_8[0x18];
6132 u8 reserved_at_40[0x8];
6135 u8 reserved_at_60[0x20];
6138 struct mlx5_ifc_create_tir_in_bits {
6140 u8 reserved_at_10[0x10];
6142 u8 reserved_at_20[0x10];
6145 u8 reserved_at_40[0xc0];
6147 struct mlx5_ifc_tirc_bits ctx;
6150 struct mlx5_ifc_create_srq_out_bits {
6152 u8 reserved_at_8[0x18];
6156 u8 reserved_at_40[0x8];
6159 u8 reserved_at_60[0x20];
6162 struct mlx5_ifc_create_srq_in_bits {
6164 u8 reserved_at_10[0x10];
6166 u8 reserved_at_20[0x10];
6169 u8 reserved_at_40[0x40];
6171 struct mlx5_ifc_srqc_bits srq_context_entry;
6173 u8 reserved_at_280[0x600];
6178 struct mlx5_ifc_create_sq_out_bits {
6180 u8 reserved_at_8[0x18];
6184 u8 reserved_at_40[0x8];
6187 u8 reserved_at_60[0x20];
6190 struct mlx5_ifc_create_sq_in_bits {
6192 u8 reserved_at_10[0x10];
6194 u8 reserved_at_20[0x10];
6197 u8 reserved_at_40[0xc0];
6199 struct mlx5_ifc_sqc_bits ctx;
6202 struct mlx5_ifc_create_scheduling_element_out_bits {
6204 u8 reserved_at_8[0x18];
6208 u8 reserved_at_40[0x40];
6210 u8 scheduling_element_id[0x20];
6212 u8 reserved_at_a0[0x160];
6215 struct mlx5_ifc_create_scheduling_element_in_bits {
6217 u8 reserved_at_10[0x10];
6219 u8 reserved_at_20[0x10];
6222 u8 scheduling_hierarchy[0x8];
6223 u8 reserved_at_48[0x18];
6225 u8 reserved_at_60[0xa0];
6227 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6229 u8 reserved_at_300[0x100];
6232 struct mlx5_ifc_create_rqt_out_bits {
6234 u8 reserved_at_8[0x18];
6238 u8 reserved_at_40[0x8];
6241 u8 reserved_at_60[0x20];
6244 struct mlx5_ifc_create_rqt_in_bits {
6246 u8 reserved_at_10[0x10];
6248 u8 reserved_at_20[0x10];
6251 u8 reserved_at_40[0xc0];
6253 struct mlx5_ifc_rqtc_bits rqt_context;
6256 struct mlx5_ifc_create_rq_out_bits {
6258 u8 reserved_at_8[0x18];
6262 u8 reserved_at_40[0x8];
6265 u8 reserved_at_60[0x20];
6268 struct mlx5_ifc_create_rq_in_bits {
6270 u8 reserved_at_10[0x10];
6272 u8 reserved_at_20[0x10];
6275 u8 reserved_at_40[0xc0];
6277 struct mlx5_ifc_rqc_bits ctx;
6280 struct mlx5_ifc_create_rmp_out_bits {
6282 u8 reserved_at_8[0x18];
6286 u8 reserved_at_40[0x8];
6289 u8 reserved_at_60[0x20];
6292 struct mlx5_ifc_create_rmp_in_bits {
6294 u8 reserved_at_10[0x10];
6296 u8 reserved_at_20[0x10];
6299 u8 reserved_at_40[0xc0];
6301 struct mlx5_ifc_rmpc_bits ctx;
6304 struct mlx5_ifc_create_qp_out_bits {
6306 u8 reserved_at_8[0x18];
6310 u8 reserved_at_40[0x8];
6313 u8 reserved_at_60[0x20];
6316 struct mlx5_ifc_create_qp_in_bits {
6318 u8 reserved_at_10[0x10];
6320 u8 reserved_at_20[0x10];
6323 u8 reserved_at_40[0x40];
6325 u8 opt_param_mask[0x20];
6327 u8 reserved_at_a0[0x20];
6329 struct mlx5_ifc_qpc_bits qpc;
6331 u8 reserved_at_800[0x80];
6336 struct mlx5_ifc_create_psv_out_bits {
6338 u8 reserved_at_8[0x18];
6342 u8 reserved_at_40[0x40];
6344 u8 reserved_at_80[0x8];
6345 u8 psv0_index[0x18];
6347 u8 reserved_at_a0[0x8];
6348 u8 psv1_index[0x18];
6350 u8 reserved_at_c0[0x8];
6351 u8 psv2_index[0x18];
6353 u8 reserved_at_e0[0x8];
6354 u8 psv3_index[0x18];
6357 struct mlx5_ifc_create_psv_in_bits {
6359 u8 reserved_at_10[0x10];
6361 u8 reserved_at_20[0x10];
6365 u8 reserved_at_44[0x4];
6368 u8 reserved_at_60[0x20];
6371 struct mlx5_ifc_create_mkey_out_bits {
6373 u8 reserved_at_8[0x18];
6377 u8 reserved_at_40[0x8];
6378 u8 mkey_index[0x18];
6380 u8 reserved_at_60[0x20];
6383 struct mlx5_ifc_create_mkey_in_bits {
6385 u8 reserved_at_10[0x10];
6387 u8 reserved_at_20[0x10];
6390 u8 reserved_at_40[0x20];
6393 u8 reserved_at_61[0x1f];
6395 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6397 u8 reserved_at_280[0x80];
6399 u8 translations_octword_actual_size[0x20];
6401 u8 reserved_at_320[0x560];
6403 u8 klm_pas_mtt[0][0x20];
6406 struct mlx5_ifc_create_flow_table_out_bits {
6408 u8 reserved_at_8[0x18];
6412 u8 reserved_at_40[0x8];
6415 u8 reserved_at_60[0x20];
6418 struct mlx5_ifc_create_flow_table_in_bits {
6420 u8 reserved_at_10[0x10];
6422 u8 reserved_at_20[0x10];
6425 u8 other_vport[0x1];
6426 u8 reserved_at_41[0xf];
6427 u8 vport_number[0x10];
6429 u8 reserved_at_60[0x20];
6432 u8 reserved_at_88[0x18];
6434 u8 reserved_at_a0[0x20];
6438 u8 reserved_at_c2[0x2];
6439 u8 table_miss_mode[0x4];
6441 u8 reserved_at_d0[0x8];
6444 u8 reserved_at_e0[0x8];
6445 u8 table_miss_id[0x18];
6447 u8 reserved_at_100[0x8];
6448 u8 lag_master_next_table_id[0x18];
6450 u8 reserved_at_120[0x80];
6453 struct mlx5_ifc_create_flow_group_out_bits {
6455 u8 reserved_at_8[0x18];
6459 u8 reserved_at_40[0x8];
6462 u8 reserved_at_60[0x20];
6466 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6467 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6468 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6471 struct mlx5_ifc_create_flow_group_in_bits {
6473 u8 reserved_at_10[0x10];
6475 u8 reserved_at_20[0x10];
6478 u8 other_vport[0x1];
6479 u8 reserved_at_41[0xf];
6480 u8 vport_number[0x10];
6482 u8 reserved_at_60[0x20];
6485 u8 reserved_at_88[0x18];
6487 u8 reserved_at_a0[0x8];
6490 u8 reserved_at_c0[0x20];
6492 u8 start_flow_index[0x20];
6494 u8 reserved_at_100[0x20];
6496 u8 end_flow_index[0x20];
6498 u8 reserved_at_140[0xa0];
6500 u8 reserved_at_1e0[0x18];
6501 u8 match_criteria_enable[0x8];
6503 struct mlx5_ifc_fte_match_param_bits match_criteria;
6505 u8 reserved_at_1200[0xe00];
6508 struct mlx5_ifc_create_eq_out_bits {
6510 u8 reserved_at_8[0x18];
6514 u8 reserved_at_40[0x18];
6517 u8 reserved_at_60[0x20];
6520 struct mlx5_ifc_create_eq_in_bits {
6522 u8 reserved_at_10[0x10];
6524 u8 reserved_at_20[0x10];
6527 u8 reserved_at_40[0x40];
6529 struct mlx5_ifc_eqc_bits eq_context_entry;
6531 u8 reserved_at_280[0x40];
6533 u8 event_bitmask[0x40];
6535 u8 reserved_at_300[0x580];
6540 struct mlx5_ifc_create_dct_out_bits {
6542 u8 reserved_at_8[0x18];
6546 u8 reserved_at_40[0x8];
6549 u8 reserved_at_60[0x20];
6552 struct mlx5_ifc_create_dct_in_bits {
6554 u8 reserved_at_10[0x10];
6556 u8 reserved_at_20[0x10];
6559 u8 reserved_at_40[0x40];
6561 struct mlx5_ifc_dctc_bits dct_context_entry;
6563 u8 reserved_at_280[0x180];
6566 struct mlx5_ifc_create_cq_out_bits {
6568 u8 reserved_at_8[0x18];
6572 u8 reserved_at_40[0x8];
6575 u8 reserved_at_60[0x20];
6578 struct mlx5_ifc_create_cq_in_bits {
6580 u8 reserved_at_10[0x10];
6582 u8 reserved_at_20[0x10];
6585 u8 reserved_at_40[0x40];
6587 struct mlx5_ifc_cqc_bits cq_context;
6589 u8 reserved_at_280[0x600];
6594 struct mlx5_ifc_config_int_moderation_out_bits {
6596 u8 reserved_at_8[0x18];
6600 u8 reserved_at_40[0x4];
6602 u8 int_vector[0x10];
6604 u8 reserved_at_60[0x20];
6608 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6609 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6612 struct mlx5_ifc_config_int_moderation_in_bits {
6614 u8 reserved_at_10[0x10];
6616 u8 reserved_at_20[0x10];
6619 u8 reserved_at_40[0x4];
6621 u8 int_vector[0x10];
6623 u8 reserved_at_60[0x20];
6626 struct mlx5_ifc_attach_to_mcg_out_bits {
6628 u8 reserved_at_8[0x18];
6632 u8 reserved_at_40[0x40];
6635 struct mlx5_ifc_attach_to_mcg_in_bits {
6637 u8 reserved_at_10[0x10];
6639 u8 reserved_at_20[0x10];
6642 u8 reserved_at_40[0x8];
6645 u8 reserved_at_60[0x20];
6647 u8 multicast_gid[16][0x8];
6650 struct mlx5_ifc_arm_xrq_out_bits {
6652 u8 reserved_at_8[0x18];
6656 u8 reserved_at_40[0x40];
6659 struct mlx5_ifc_arm_xrq_in_bits {
6661 u8 reserved_at_10[0x10];
6663 u8 reserved_at_20[0x10];
6666 u8 reserved_at_40[0x8];
6669 u8 reserved_at_60[0x10];
6673 struct mlx5_ifc_arm_xrc_srq_out_bits {
6675 u8 reserved_at_8[0x18];
6679 u8 reserved_at_40[0x40];
6683 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6686 struct mlx5_ifc_arm_xrc_srq_in_bits {
6688 u8 reserved_at_10[0x10];
6690 u8 reserved_at_20[0x10];
6693 u8 reserved_at_40[0x8];
6696 u8 reserved_at_60[0x10];
6700 struct mlx5_ifc_arm_rq_out_bits {
6702 u8 reserved_at_8[0x18];
6706 u8 reserved_at_40[0x40];
6710 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6711 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6714 struct mlx5_ifc_arm_rq_in_bits {
6716 u8 reserved_at_10[0x10];
6718 u8 reserved_at_20[0x10];
6721 u8 reserved_at_40[0x8];
6722 u8 srq_number[0x18];
6724 u8 reserved_at_60[0x10];
6728 struct mlx5_ifc_arm_dct_out_bits {
6730 u8 reserved_at_8[0x18];
6734 u8 reserved_at_40[0x40];
6737 struct mlx5_ifc_arm_dct_in_bits {
6739 u8 reserved_at_10[0x10];
6741 u8 reserved_at_20[0x10];
6744 u8 reserved_at_40[0x8];
6745 u8 dct_number[0x18];
6747 u8 reserved_at_60[0x20];
6750 struct mlx5_ifc_alloc_xrcd_out_bits {
6752 u8 reserved_at_8[0x18];
6756 u8 reserved_at_40[0x8];
6759 u8 reserved_at_60[0x20];
6762 struct mlx5_ifc_alloc_xrcd_in_bits {
6764 u8 reserved_at_10[0x10];
6766 u8 reserved_at_20[0x10];
6769 u8 reserved_at_40[0x40];
6772 struct mlx5_ifc_alloc_uar_out_bits {
6774 u8 reserved_at_8[0x18];
6778 u8 reserved_at_40[0x8];
6781 u8 reserved_at_60[0x20];
6784 struct mlx5_ifc_alloc_uar_in_bits {
6786 u8 reserved_at_10[0x10];
6788 u8 reserved_at_20[0x10];
6791 u8 reserved_at_40[0x40];
6794 struct mlx5_ifc_alloc_transport_domain_out_bits {
6796 u8 reserved_at_8[0x18];
6800 u8 reserved_at_40[0x8];
6801 u8 transport_domain[0x18];
6803 u8 reserved_at_60[0x20];
6806 struct mlx5_ifc_alloc_transport_domain_in_bits {
6808 u8 reserved_at_10[0x10];
6810 u8 reserved_at_20[0x10];
6813 u8 reserved_at_40[0x40];
6816 struct mlx5_ifc_alloc_q_counter_out_bits {
6818 u8 reserved_at_8[0x18];
6822 u8 reserved_at_40[0x18];
6823 u8 counter_set_id[0x8];
6825 u8 reserved_at_60[0x20];
6828 struct mlx5_ifc_alloc_q_counter_in_bits {
6830 u8 reserved_at_10[0x10];
6832 u8 reserved_at_20[0x10];
6835 u8 reserved_at_40[0x40];
6838 struct mlx5_ifc_alloc_pd_out_bits {
6840 u8 reserved_at_8[0x18];
6844 u8 reserved_at_40[0x8];
6847 u8 reserved_at_60[0x20];
6850 struct mlx5_ifc_alloc_pd_in_bits {
6852 u8 reserved_at_10[0x10];
6854 u8 reserved_at_20[0x10];
6857 u8 reserved_at_40[0x40];
6860 struct mlx5_ifc_alloc_flow_counter_out_bits {
6862 u8 reserved_at_8[0x18];
6866 u8 reserved_at_40[0x10];
6867 u8 flow_counter_id[0x10];
6869 u8 reserved_at_60[0x20];
6872 struct mlx5_ifc_alloc_flow_counter_in_bits {
6874 u8 reserved_at_10[0x10];
6876 u8 reserved_at_20[0x10];
6879 u8 reserved_at_40[0x40];
6882 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6884 u8 reserved_at_8[0x18];
6888 u8 reserved_at_40[0x40];
6891 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6893 u8 reserved_at_10[0x10];
6895 u8 reserved_at_20[0x10];
6898 u8 reserved_at_40[0x20];
6900 u8 reserved_at_60[0x10];
6901 u8 vxlan_udp_port[0x10];
6904 struct mlx5_ifc_set_rate_limit_out_bits {
6906 u8 reserved_at_8[0x18];
6910 u8 reserved_at_40[0x40];
6913 struct mlx5_ifc_set_rate_limit_in_bits {
6915 u8 reserved_at_10[0x10];
6917 u8 reserved_at_20[0x10];
6920 u8 reserved_at_40[0x10];
6921 u8 rate_limit_index[0x10];
6923 u8 reserved_at_60[0x20];
6925 u8 rate_limit[0x20];
6928 struct mlx5_ifc_access_register_out_bits {
6930 u8 reserved_at_8[0x18];
6934 u8 reserved_at_40[0x40];
6936 u8 register_data[0][0x20];
6940 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6941 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6944 struct mlx5_ifc_access_register_in_bits {
6946 u8 reserved_at_10[0x10];
6948 u8 reserved_at_20[0x10];
6951 u8 reserved_at_40[0x10];
6952 u8 register_id[0x10];
6956 u8 register_data[0][0x20];
6959 struct mlx5_ifc_sltp_reg_bits {
6964 u8 reserved_at_12[0x2];
6966 u8 reserved_at_18[0x8];
6968 u8 reserved_at_20[0x20];
6970 u8 reserved_at_40[0x7];
6976 u8 reserved_at_60[0xc];
6977 u8 ob_preemp_mode[0x4];
6981 u8 reserved_at_80[0x20];
6984 struct mlx5_ifc_slrg_reg_bits {
6989 u8 reserved_at_12[0x2];
6991 u8 reserved_at_18[0x8];
6993 u8 time_to_link_up[0x10];
6994 u8 reserved_at_30[0xc];
6995 u8 grade_lane_speed[0x4];
6997 u8 grade_version[0x8];
7000 u8 reserved_at_60[0x4];
7001 u8 height_grade_type[0x4];
7002 u8 height_grade[0x18];
7007 u8 reserved_at_a0[0x10];
7008 u8 height_sigma[0x10];
7010 u8 reserved_at_c0[0x20];
7012 u8 reserved_at_e0[0x4];
7013 u8 phase_grade_type[0x4];
7014 u8 phase_grade[0x18];
7016 u8 reserved_at_100[0x8];
7017 u8 phase_eo_pos[0x8];
7018 u8 reserved_at_110[0x8];
7019 u8 phase_eo_neg[0x8];
7021 u8 ffe_set_tested[0x10];
7022 u8 test_errors_per_lane[0x10];
7025 struct mlx5_ifc_pvlc_reg_bits {
7026 u8 reserved_at_0[0x8];
7028 u8 reserved_at_10[0x10];
7030 u8 reserved_at_20[0x1c];
7033 u8 reserved_at_40[0x1c];
7036 u8 reserved_at_60[0x1c];
7037 u8 vl_operational[0x4];
7040 struct mlx5_ifc_pude_reg_bits {
7043 u8 reserved_at_10[0x4];
7044 u8 admin_status[0x4];
7045 u8 reserved_at_18[0x4];
7046 u8 oper_status[0x4];
7048 u8 reserved_at_20[0x60];
7051 struct mlx5_ifc_ptys_reg_bits {
7052 u8 reserved_at_0[0x1];
7053 u8 an_disable_admin[0x1];
7054 u8 an_disable_cap[0x1];
7055 u8 reserved_at_3[0x5];
7057 u8 reserved_at_10[0xd];
7061 u8 reserved_at_24[0x3c];
7063 u8 eth_proto_capability[0x20];
7065 u8 ib_link_width_capability[0x10];
7066 u8 ib_proto_capability[0x10];
7068 u8 reserved_at_a0[0x20];
7070 u8 eth_proto_admin[0x20];
7072 u8 ib_link_width_admin[0x10];
7073 u8 ib_proto_admin[0x10];
7075 u8 reserved_at_100[0x20];
7077 u8 eth_proto_oper[0x20];
7079 u8 ib_link_width_oper[0x10];
7080 u8 ib_proto_oper[0x10];
7082 u8 reserved_at_160[0x20];
7084 u8 eth_proto_lp_advertise[0x20];
7086 u8 reserved_at_1a0[0x60];
7089 struct mlx5_ifc_mlcr_reg_bits {
7090 u8 reserved_at_0[0x8];
7092 u8 reserved_at_10[0x20];
7094 u8 beacon_duration[0x10];
7095 u8 reserved_at_40[0x10];
7097 u8 beacon_remain[0x10];
7100 struct mlx5_ifc_ptas_reg_bits {
7101 u8 reserved_at_0[0x20];
7103 u8 algorithm_options[0x10];
7104 u8 reserved_at_30[0x4];
7105 u8 repetitions_mode[0x4];
7106 u8 num_of_repetitions[0x8];
7108 u8 grade_version[0x8];
7109 u8 height_grade_type[0x4];
7110 u8 phase_grade_type[0x4];
7111 u8 height_grade_weight[0x8];
7112 u8 phase_grade_weight[0x8];
7114 u8 gisim_measure_bits[0x10];
7115 u8 adaptive_tap_measure_bits[0x10];
7117 u8 ber_bath_high_error_threshold[0x10];
7118 u8 ber_bath_mid_error_threshold[0x10];
7120 u8 ber_bath_low_error_threshold[0x10];
7121 u8 one_ratio_high_threshold[0x10];
7123 u8 one_ratio_high_mid_threshold[0x10];
7124 u8 one_ratio_low_mid_threshold[0x10];
7126 u8 one_ratio_low_threshold[0x10];
7127 u8 ndeo_error_threshold[0x10];
7129 u8 mixer_offset_step_size[0x10];
7130 u8 reserved_at_110[0x8];
7131 u8 mix90_phase_for_voltage_bath[0x8];
7133 u8 mixer_offset_start[0x10];
7134 u8 mixer_offset_end[0x10];
7136 u8 reserved_at_140[0x15];
7137 u8 ber_test_time[0xb];
7140 struct mlx5_ifc_pspa_reg_bits {
7144 u8 reserved_at_18[0x8];
7146 u8 reserved_at_20[0x20];
7149 struct mlx5_ifc_pqdr_reg_bits {
7150 u8 reserved_at_0[0x8];
7152 u8 reserved_at_10[0x5];
7154 u8 reserved_at_18[0x6];
7157 u8 reserved_at_20[0x20];
7159 u8 reserved_at_40[0x10];
7160 u8 min_threshold[0x10];
7162 u8 reserved_at_60[0x10];
7163 u8 max_threshold[0x10];
7165 u8 reserved_at_80[0x10];
7166 u8 mark_probability_denominator[0x10];
7168 u8 reserved_at_a0[0x60];
7171 struct mlx5_ifc_ppsc_reg_bits {
7172 u8 reserved_at_0[0x8];
7174 u8 reserved_at_10[0x10];
7176 u8 reserved_at_20[0x60];
7178 u8 reserved_at_80[0x1c];
7181 u8 reserved_at_a0[0x1c];
7182 u8 wrps_status[0x4];
7184 u8 reserved_at_c0[0x8];
7185 u8 up_threshold[0x8];
7186 u8 reserved_at_d0[0x8];
7187 u8 down_threshold[0x8];
7189 u8 reserved_at_e0[0x20];
7191 u8 reserved_at_100[0x1c];
7194 u8 reserved_at_120[0x1c];
7195 u8 srps_status[0x4];
7197 u8 reserved_at_140[0x40];
7200 struct mlx5_ifc_pplr_reg_bits {
7201 u8 reserved_at_0[0x8];
7203 u8 reserved_at_10[0x10];
7205 u8 reserved_at_20[0x8];
7207 u8 reserved_at_30[0x8];
7211 struct mlx5_ifc_pplm_reg_bits {
7212 u8 reserved_at_0[0x8];
7214 u8 reserved_at_10[0x10];
7216 u8 reserved_at_20[0x20];
7218 u8 port_profile_mode[0x8];
7219 u8 static_port_profile[0x8];
7220 u8 active_port_profile[0x8];
7221 u8 reserved_at_58[0x8];
7223 u8 retransmission_active[0x8];
7224 u8 fec_mode_active[0x18];
7226 u8 reserved_at_80[0x20];
7229 struct mlx5_ifc_ppcnt_reg_bits {
7233 u8 reserved_at_12[0x8];
7237 u8 reserved_at_21[0x1c];
7240 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7243 struct mlx5_ifc_ppad_reg_bits {
7244 u8 reserved_at_0[0x3];
7246 u8 reserved_at_4[0x4];
7252 u8 reserved_at_40[0x40];
7255 struct mlx5_ifc_pmtu_reg_bits {
7256 u8 reserved_at_0[0x8];
7258 u8 reserved_at_10[0x10];
7261 u8 reserved_at_30[0x10];
7264 u8 reserved_at_50[0x10];
7267 u8 reserved_at_70[0x10];
7270 struct mlx5_ifc_pmpr_reg_bits {
7271 u8 reserved_at_0[0x8];
7273 u8 reserved_at_10[0x10];
7275 u8 reserved_at_20[0x18];
7276 u8 attenuation_5g[0x8];
7278 u8 reserved_at_40[0x18];
7279 u8 attenuation_7g[0x8];
7281 u8 reserved_at_60[0x18];
7282 u8 attenuation_12g[0x8];
7285 struct mlx5_ifc_pmpe_reg_bits {
7286 u8 reserved_at_0[0x8];
7288 u8 reserved_at_10[0xc];
7289 u8 module_status[0x4];
7291 u8 reserved_at_20[0x60];
7294 struct mlx5_ifc_pmpc_reg_bits {
7295 u8 module_state_updated[32][0x8];
7298 struct mlx5_ifc_pmlpn_reg_bits {
7299 u8 reserved_at_0[0x4];
7300 u8 mlpn_status[0x4];
7302 u8 reserved_at_10[0x10];
7305 u8 reserved_at_21[0x1f];
7308 struct mlx5_ifc_pmlp_reg_bits {
7310 u8 reserved_at_1[0x7];
7312 u8 reserved_at_10[0x8];
7315 u8 lane0_module_mapping[0x20];
7317 u8 lane1_module_mapping[0x20];
7319 u8 lane2_module_mapping[0x20];
7321 u8 lane3_module_mapping[0x20];
7323 u8 reserved_at_a0[0x160];
7326 struct mlx5_ifc_pmaos_reg_bits {
7327 u8 reserved_at_0[0x8];
7329 u8 reserved_at_10[0x4];
7330 u8 admin_status[0x4];
7331 u8 reserved_at_18[0x4];
7332 u8 oper_status[0x4];
7336 u8 reserved_at_22[0x1c];
7339 u8 reserved_at_40[0x40];
7342 struct mlx5_ifc_plpc_reg_bits {
7343 u8 reserved_at_0[0x4];
7345 u8 reserved_at_10[0x4];
7347 u8 reserved_at_18[0x8];
7349 u8 reserved_at_20[0x10];
7350 u8 lane_speed[0x10];
7352 u8 reserved_at_40[0x17];
7354 u8 fec_mode_policy[0x8];
7356 u8 retransmission_capability[0x8];
7357 u8 fec_mode_capability[0x18];
7359 u8 retransmission_support_admin[0x8];
7360 u8 fec_mode_support_admin[0x18];
7362 u8 retransmission_request_admin[0x8];
7363 u8 fec_mode_request_admin[0x18];
7365 u8 reserved_at_c0[0x80];
7368 struct mlx5_ifc_plib_reg_bits {
7369 u8 reserved_at_0[0x8];
7371 u8 reserved_at_10[0x8];
7374 u8 reserved_at_20[0x60];
7377 struct mlx5_ifc_plbf_reg_bits {
7378 u8 reserved_at_0[0x8];
7380 u8 reserved_at_10[0xd];
7383 u8 reserved_at_20[0x20];
7386 struct mlx5_ifc_pipg_reg_bits {
7387 u8 reserved_at_0[0x8];
7389 u8 reserved_at_10[0x10];
7392 u8 reserved_at_21[0x19];
7394 u8 reserved_at_3e[0x2];
7397 struct mlx5_ifc_pifr_reg_bits {
7398 u8 reserved_at_0[0x8];
7400 u8 reserved_at_10[0x10];
7402 u8 reserved_at_20[0xe0];
7404 u8 port_filter[8][0x20];
7406 u8 port_filter_update_en[8][0x20];
7409 struct mlx5_ifc_pfcc_reg_bits {
7410 u8 reserved_at_0[0x8];
7412 u8 reserved_at_10[0x10];
7415 u8 reserved_at_24[0x4];
7416 u8 prio_mask_tx[0x8];
7417 u8 reserved_at_30[0x8];
7418 u8 prio_mask_rx[0x8];
7422 u8 reserved_at_42[0x6];
7424 u8 reserved_at_50[0x10];
7428 u8 reserved_at_62[0x6];
7430 u8 reserved_at_70[0x10];
7432 u8 reserved_at_80[0x80];
7435 struct mlx5_ifc_pelc_reg_bits {
7437 u8 reserved_at_4[0x4];
7439 u8 reserved_at_10[0x10];
7442 u8 op_capability[0x8];
7448 u8 capability[0x40];
7454 u8 reserved_at_140[0x80];
7457 struct mlx5_ifc_peir_reg_bits {
7458 u8 reserved_at_0[0x8];
7460 u8 reserved_at_10[0x10];
7462 u8 reserved_at_20[0xc];
7463 u8 error_count[0x4];
7464 u8 reserved_at_30[0x10];
7466 u8 reserved_at_40[0xc];
7468 u8 reserved_at_50[0x8];
7472 struct mlx5_ifc_pcap_reg_bits {
7473 u8 reserved_at_0[0x8];
7475 u8 reserved_at_10[0x10];
7477 u8 port_capability_mask[4][0x20];
7480 struct mlx5_ifc_paos_reg_bits {
7483 u8 reserved_at_10[0x4];
7484 u8 admin_status[0x4];
7485 u8 reserved_at_18[0x4];
7486 u8 oper_status[0x4];
7490 u8 reserved_at_22[0x1c];
7493 u8 reserved_at_40[0x40];
7496 struct mlx5_ifc_pamp_reg_bits {
7497 u8 reserved_at_0[0x8];
7498 u8 opamp_group[0x8];
7499 u8 reserved_at_10[0xc];
7500 u8 opamp_group_type[0x4];
7502 u8 start_index[0x10];
7503 u8 reserved_at_30[0x4];
7504 u8 num_of_indices[0xc];
7506 u8 index_data[18][0x10];
7509 struct mlx5_ifc_pcmr_reg_bits {
7510 u8 reserved_at_0[0x8];
7512 u8 reserved_at_10[0x2e];
7514 u8 reserved_at_3f[0x1f];
7516 u8 reserved_at_5f[0x1];
7519 struct mlx5_ifc_lane_2_module_mapping_bits {
7520 u8 reserved_at_0[0x6];
7522 u8 reserved_at_8[0x6];
7524 u8 reserved_at_10[0x8];
7528 struct mlx5_ifc_bufferx_reg_bits {
7529 u8 reserved_at_0[0x6];
7532 u8 reserved_at_8[0xc];
7535 u8 xoff_threshold[0x10];
7536 u8 xon_threshold[0x10];
7539 struct mlx5_ifc_set_node_in_bits {
7540 u8 node_description[64][0x8];
7543 struct mlx5_ifc_register_power_settings_bits {
7544 u8 reserved_at_0[0x18];
7545 u8 power_settings_level[0x8];
7547 u8 reserved_at_20[0x60];
7550 struct mlx5_ifc_register_host_endianness_bits {
7552 u8 reserved_at_1[0x1f];
7554 u8 reserved_at_20[0x60];
7557 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7558 u8 reserved_at_0[0x20];
7562 u8 addressh_63_32[0x20];
7564 u8 addressl_31_0[0x20];
7567 struct mlx5_ifc_ud_adrs_vector_bits {
7571 u8 reserved_at_41[0x7];
7572 u8 destination_qp_dct[0x18];
7574 u8 static_rate[0x4];
7575 u8 sl_eth_prio[0x4];
7578 u8 rlid_udp_sport[0x10];
7580 u8 reserved_at_80[0x20];
7582 u8 rmac_47_16[0x20];
7588 u8 reserved_at_e0[0x1];
7590 u8 reserved_at_e2[0x2];
7591 u8 src_addr_index[0x8];
7592 u8 flow_label[0x14];
7594 u8 rgid_rip[16][0x8];
7597 struct mlx5_ifc_pages_req_event_bits {
7598 u8 reserved_at_0[0x10];
7599 u8 function_id[0x10];
7603 u8 reserved_at_40[0xa0];
7606 struct mlx5_ifc_eqe_bits {
7607 u8 reserved_at_0[0x8];
7609 u8 reserved_at_10[0x8];
7610 u8 event_sub_type[0x8];
7612 u8 reserved_at_20[0xe0];
7614 union mlx5_ifc_event_auto_bits event_data;
7616 u8 reserved_at_1e0[0x10];
7618 u8 reserved_at_1f8[0x7];
7623 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7626 struct mlx5_ifc_cmd_queue_entry_bits {
7628 u8 reserved_at_8[0x18];
7630 u8 input_length[0x20];
7632 u8 input_mailbox_pointer_63_32[0x20];
7634 u8 input_mailbox_pointer_31_9[0x17];
7635 u8 reserved_at_77[0x9];
7637 u8 command_input_inline_data[16][0x8];
7639 u8 command_output_inline_data[16][0x8];
7641 u8 output_mailbox_pointer_63_32[0x20];
7643 u8 output_mailbox_pointer_31_9[0x17];
7644 u8 reserved_at_1b7[0x9];
7646 u8 output_length[0x20];
7650 u8 reserved_at_1f0[0x8];
7655 struct mlx5_ifc_cmd_out_bits {
7657 u8 reserved_at_8[0x18];
7661 u8 command_output[0x20];
7664 struct mlx5_ifc_cmd_in_bits {
7666 u8 reserved_at_10[0x10];
7668 u8 reserved_at_20[0x10];
7671 u8 command[0][0x20];
7674 struct mlx5_ifc_cmd_if_box_bits {
7675 u8 mailbox_data[512][0x8];
7677 u8 reserved_at_1000[0x180];
7679 u8 next_pointer_63_32[0x20];
7681 u8 next_pointer_31_10[0x16];
7682 u8 reserved_at_11b6[0xa];
7684 u8 block_number[0x20];
7686 u8 reserved_at_11e0[0x8];
7688 u8 ctrl_signature[0x8];
7692 struct mlx5_ifc_mtt_bits {
7693 u8 ptag_63_32[0x20];
7696 u8 reserved_at_38[0x6];
7701 struct mlx5_ifc_query_wol_rol_out_bits {
7703 u8 reserved_at_8[0x18];
7707 u8 reserved_at_40[0x10];
7711 u8 reserved_at_60[0x20];
7714 struct mlx5_ifc_query_wol_rol_in_bits {
7716 u8 reserved_at_10[0x10];
7718 u8 reserved_at_20[0x10];
7721 u8 reserved_at_40[0x40];
7724 struct mlx5_ifc_set_wol_rol_out_bits {
7726 u8 reserved_at_8[0x18];
7730 u8 reserved_at_40[0x40];
7733 struct mlx5_ifc_set_wol_rol_in_bits {
7735 u8 reserved_at_10[0x10];
7737 u8 reserved_at_20[0x10];
7740 u8 rol_mode_valid[0x1];
7741 u8 wol_mode_valid[0x1];
7742 u8 reserved_at_42[0xe];
7746 u8 reserved_at_60[0x20];
7750 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7751 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7752 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7756 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7757 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7758 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7762 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7763 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7764 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7765 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7766 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7767 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7768 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7769 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7770 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7771 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7772 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7775 struct mlx5_ifc_initial_seg_bits {
7776 u8 fw_rev_minor[0x10];
7777 u8 fw_rev_major[0x10];
7779 u8 cmd_interface_rev[0x10];
7780 u8 fw_rev_subminor[0x10];
7782 u8 reserved_at_40[0x40];
7784 u8 cmdq_phy_addr_63_32[0x20];
7786 u8 cmdq_phy_addr_31_12[0x14];
7787 u8 reserved_at_b4[0x2];
7788 u8 nic_interface[0x2];
7789 u8 log_cmdq_size[0x4];
7790 u8 log_cmdq_stride[0x4];
7792 u8 command_doorbell_vector[0x20];
7794 u8 reserved_at_e0[0xf00];
7796 u8 initializing[0x1];
7797 u8 reserved_at_fe1[0x4];
7798 u8 nic_interface_supported[0x3];
7799 u8 reserved_at_fe8[0x18];
7801 struct mlx5_ifc_health_buffer_bits health_buffer;
7803 u8 no_dram_nic_offset[0x20];
7805 u8 reserved_at_1220[0x6e40];
7807 u8 reserved_at_8060[0x1f];
7810 u8 health_syndrome[0x8];
7811 u8 health_counter[0x18];
7813 u8 reserved_at_80a0[0x17fc0];
7816 union mlx5_ifc_ports_control_registers_document_bits {
7817 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7818 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7819 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7820 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7821 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7822 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7823 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7824 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7825 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7826 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7827 struct mlx5_ifc_paos_reg_bits paos_reg;
7828 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7829 struct mlx5_ifc_peir_reg_bits peir_reg;
7830 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7831 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7832 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7833 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7834 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7835 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7836 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7837 struct mlx5_ifc_plib_reg_bits plib_reg;
7838 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7839 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7840 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7841 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7842 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7843 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7844 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7845 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7846 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7847 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7848 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7849 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7850 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7851 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7852 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7853 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7854 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7855 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7856 struct mlx5_ifc_pude_reg_bits pude_reg;
7857 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7858 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7859 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7860 u8 reserved_at_0[0x60e0];
7863 union mlx5_ifc_debug_enhancements_document_bits {
7864 struct mlx5_ifc_health_buffer_bits health_buffer;
7865 u8 reserved_at_0[0x200];
7868 union mlx5_ifc_uplink_pci_interface_document_bits {
7869 struct mlx5_ifc_initial_seg_bits initial_seg;
7870 u8 reserved_at_0[0x20060];
7873 struct mlx5_ifc_set_flow_table_root_out_bits {
7875 u8 reserved_at_8[0x18];
7879 u8 reserved_at_40[0x40];
7882 struct mlx5_ifc_set_flow_table_root_in_bits {
7884 u8 reserved_at_10[0x10];
7886 u8 reserved_at_20[0x10];
7889 u8 other_vport[0x1];
7890 u8 reserved_at_41[0xf];
7891 u8 vport_number[0x10];
7893 u8 reserved_at_60[0x20];
7896 u8 reserved_at_88[0x18];
7898 u8 reserved_at_a0[0x8];
7901 u8 reserved_at_c0[0x140];
7905 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7906 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7909 struct mlx5_ifc_modify_flow_table_out_bits {
7911 u8 reserved_at_8[0x18];
7915 u8 reserved_at_40[0x40];
7918 struct mlx5_ifc_modify_flow_table_in_bits {
7920 u8 reserved_at_10[0x10];
7922 u8 reserved_at_20[0x10];
7925 u8 other_vport[0x1];
7926 u8 reserved_at_41[0xf];
7927 u8 vport_number[0x10];
7929 u8 reserved_at_60[0x10];
7930 u8 modify_field_select[0x10];
7933 u8 reserved_at_88[0x18];
7935 u8 reserved_at_a0[0x8];
7938 u8 reserved_at_c0[0x4];
7939 u8 table_miss_mode[0x4];
7940 u8 reserved_at_c8[0x18];
7942 u8 reserved_at_e0[0x8];
7943 u8 table_miss_id[0x18];
7945 u8 reserved_at_100[0x8];
7946 u8 lag_master_next_table_id[0x18];
7948 u8 reserved_at_120[0x80];
7951 struct mlx5_ifc_ets_tcn_config_reg_bits {
7955 u8 reserved_at_3[0x9];
7957 u8 reserved_at_10[0x9];
7958 u8 bw_allocation[0x7];
7960 u8 reserved_at_20[0xc];
7961 u8 max_bw_units[0x4];
7962 u8 reserved_at_30[0x8];
7963 u8 max_bw_value[0x8];
7966 struct mlx5_ifc_ets_global_config_reg_bits {
7967 u8 reserved_at_0[0x2];
7969 u8 reserved_at_3[0x1d];
7971 u8 reserved_at_20[0xc];
7972 u8 max_bw_units[0x4];
7973 u8 reserved_at_30[0x8];
7974 u8 max_bw_value[0x8];
7977 struct mlx5_ifc_qetc_reg_bits {
7978 u8 reserved_at_0[0x8];
7979 u8 port_number[0x8];
7980 u8 reserved_at_10[0x30];
7982 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7983 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7986 struct mlx5_ifc_qtct_reg_bits {
7987 u8 reserved_at_0[0x8];
7988 u8 port_number[0x8];
7989 u8 reserved_at_10[0xd];
7992 u8 reserved_at_20[0x1d];
7996 struct mlx5_ifc_mcia_reg_bits {
7998 u8 reserved_at_1[0x7];
8000 u8 reserved_at_10[0x8];
8003 u8 i2c_device_address[0x8];
8004 u8 page_number[0x8];
8005 u8 device_address[0x10];
8007 u8 reserved_at_40[0x10];
8010 u8 reserved_at_60[0x20];
8026 struct mlx5_ifc_dcbx_param_bits {
8027 u8 dcbx_cee_cap[0x1];
8028 u8 dcbx_ieee_cap[0x1];
8029 u8 dcbx_standby_cap[0x1];
8030 u8 reserved_at_0[0x5];
8031 u8 port_number[0x8];
8032 u8 reserved_at_10[0xa];
8033 u8 max_application_table_size[6];
8034 u8 reserved_at_20[0x15];
8035 u8 version_oper[0x3];
8036 u8 reserved_at_38[5];
8037 u8 version_admin[0x3];
8038 u8 willing_admin[0x1];
8039 u8 reserved_at_41[0x3];
8040 u8 pfc_cap_oper[0x4];
8041 u8 reserved_at_48[0x4];
8042 u8 pfc_cap_admin[0x4];
8043 u8 reserved_at_50[0x4];
8044 u8 num_of_tc_oper[0x4];
8045 u8 reserved_at_58[0x4];
8046 u8 num_of_tc_admin[0x4];
8047 u8 remote_willing[0x1];
8048 u8 reserved_at_61[3];
8049 u8 remote_pfc_cap[4];
8050 u8 reserved_at_68[0x14];
8051 u8 remote_num_of_tc[0x4];
8052 u8 reserved_at_80[0x18];
8054 u8 reserved_at_a0[0x160];
8057 struct mlx5_ifc_lagc_bits {
8058 u8 reserved_at_0[0x1d];
8061 u8 reserved_at_20[0x14];
8062 u8 tx_remap_affinity_2[0x4];
8063 u8 reserved_at_38[0x4];
8064 u8 tx_remap_affinity_1[0x4];
8067 struct mlx5_ifc_create_lag_out_bits {
8069 u8 reserved_at_8[0x18];
8073 u8 reserved_at_40[0x40];
8076 struct mlx5_ifc_create_lag_in_bits {
8078 u8 reserved_at_10[0x10];
8080 u8 reserved_at_20[0x10];
8083 struct mlx5_ifc_lagc_bits ctx;
8086 struct mlx5_ifc_modify_lag_out_bits {
8088 u8 reserved_at_8[0x18];
8092 u8 reserved_at_40[0x40];
8095 struct mlx5_ifc_modify_lag_in_bits {
8097 u8 reserved_at_10[0x10];
8099 u8 reserved_at_20[0x10];
8102 u8 reserved_at_40[0x20];
8103 u8 field_select[0x20];
8105 struct mlx5_ifc_lagc_bits ctx;
8108 struct mlx5_ifc_query_lag_out_bits {
8110 u8 reserved_at_8[0x18];
8114 u8 reserved_at_40[0x40];
8116 struct mlx5_ifc_lagc_bits ctx;
8119 struct mlx5_ifc_query_lag_in_bits {
8121 u8 reserved_at_10[0x10];
8123 u8 reserved_at_20[0x10];
8126 u8 reserved_at_40[0x40];
8129 struct mlx5_ifc_destroy_lag_out_bits {
8131 u8 reserved_at_8[0x18];
8135 u8 reserved_at_40[0x40];
8138 struct mlx5_ifc_destroy_lag_in_bits {
8140 u8 reserved_at_10[0x10];
8142 u8 reserved_at_20[0x10];
8145 u8 reserved_at_40[0x40];
8148 struct mlx5_ifc_create_vport_lag_out_bits {
8150 u8 reserved_at_8[0x18];
8154 u8 reserved_at_40[0x40];
8157 struct mlx5_ifc_create_vport_lag_in_bits {
8159 u8 reserved_at_10[0x10];
8161 u8 reserved_at_20[0x10];
8164 u8 reserved_at_40[0x40];
8167 struct mlx5_ifc_destroy_vport_lag_out_bits {
8169 u8 reserved_at_8[0x18];
8173 u8 reserved_at_40[0x40];
8176 struct mlx5_ifc_destroy_vport_lag_in_bits {
8178 u8 reserved_at_10[0x10];
8180 u8 reserved_at_20[0x10];
8183 u8 reserved_at_40[0x40];
8186 #endif /* MLX5_IFC_H */