include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 204         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 205         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 206         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 207         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 208         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 209         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 210         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 211         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 212         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 213         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 214         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 215         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 216         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 217         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 218         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 219         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 220         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 221         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 222         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 223         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 224         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 225         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 226         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 227         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 228         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 229         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 230         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 231         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 232         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 233         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 234         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 235         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 236         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 237         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 238         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 239         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 240         MLX5_CMD_OP_MAX
 241 };
 242
 243 struct mlx5_ifc_flow_table_fields_supported_bits {
 244         u8         outer_dmac[0x1];
 245         u8         outer_smac[0x1];
 246         u8         outer_ether_type[0x1];
 247         u8         outer_ip_version[0x1];
 248         u8         outer_first_prio[0x1];
 249         u8         outer_first_cfi[0x1];
 250         u8         outer_first_vid[0x1];
 251         u8         outer_ipv4_ttl[0x1];
 252         u8         outer_second_prio[0x1];
 253         u8         outer_second_cfi[0x1];
 254         u8         outer_second_vid[0x1];
 255         u8         reserved_at_b[0x1];
 256         u8         outer_sip[0x1];
 257         u8         outer_dip[0x1];
 258         u8         outer_frag[0x1];
 259         u8         outer_ip_protocol[0x1];
 260         u8         outer_ip_ecn[0x1];
 261         u8         outer_ip_dscp[0x1];
 262         u8         outer_udp_sport[0x1];
 263         u8         outer_udp_dport[0x1];
 264         u8         outer_tcp_sport[0x1];
 265         u8         outer_tcp_dport[0x1];
 266         u8         outer_tcp_flags[0x1];
 267         u8         outer_gre_protocol[0x1];
 268         u8         outer_gre_key[0x1];
 269         u8         outer_vxlan_vni[0x1];
 270         u8         reserved_at_1a[0x5];
 271         u8         source_eswitch_port[0x1];
 272
 273         u8         inner_dmac[0x1];
 274         u8         inner_smac[0x1];
 275         u8         inner_ether_type[0x1];
 276         u8         inner_ip_version[0x1];
 277         u8         inner_first_prio[0x1];
 278         u8         inner_first_cfi[0x1];
 279         u8         inner_first_vid[0x1];
 280         u8         reserved_at_27[0x1];
 281         u8         inner_second_prio[0x1];
 282         u8         inner_second_cfi[0x1];
 283         u8         inner_second_vid[0x1];
 284         u8         reserved_at_2b[0x1];
 285         u8         inner_sip[0x1];
 286         u8         inner_dip[0x1];
 287         u8         inner_frag[0x1];
 288         u8         inner_ip_protocol[0x1];
 289         u8         inner_ip_ecn[0x1];
 290         u8         inner_ip_dscp[0x1];
 291         u8         inner_udp_sport[0x1];
 292         u8         inner_udp_dport[0x1];
 293         u8         inner_tcp_sport[0x1];
 294         u8         inner_tcp_dport[0x1];
 295         u8         inner_tcp_flags[0x1];
 296         u8         reserved_at_37[0x9];
 297
 298         u8         reserved_at_40[0x40];
 299 };
 300
 301 struct mlx5_ifc_flow_table_prop_layout_bits {
 302         u8         ft_support[0x1];
 303         u8         reserved_at_1[0x1];
 304         u8         flow_counter[0x1];
 305         u8         flow_modify_en[0x1];
 306         u8         modify_root[0x1];
 307         u8         identified_miss_table_mode[0x1];
 308         u8         flow_table_modify[0x1];
 309         u8         encap[0x1];
 310         u8         decap[0x1];
 311         u8         reserved_at_9[0x17];
 312
 313         u8         reserved_at_20[0x2];
 314         u8         log_max_ft_size[0x6];
 315         u8         log_max_modify_header_context[0x8];
 316         u8         max_modify_header_actions[0x8];
 317         u8         max_ft_level[0x8];
 318
 319         u8         reserved_at_40[0x20];
 320
 321         u8         reserved_at_60[0x18];
 322         u8         log_max_ft_num[0x8];
 323
 324         u8         reserved_at_80[0x18];
 325         u8         log_max_destination[0x8];
 326
 327         u8         reserved_at_a0[0x18];
 328         u8         log_max_flow[0x8];
 329
 330         u8         reserved_at_c0[0x40];
 331
 332         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 333
 334         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 335 };
 336
 337 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 338         u8         send[0x1];
 339         u8         receive[0x1];
 340         u8         write[0x1];
 341         u8         read[0x1];
 342         u8         atomic[0x1];
 343         u8         srq_receive[0x1];
 344         u8         reserved_at_6[0x1a];
 345 };
 346
 347 struct mlx5_ifc_ipv4_layout_bits {
 348         u8         reserved_at_0[0x60];
 349
 350         u8         ipv4[0x20];
 351 };
 352
 353 struct mlx5_ifc_ipv6_layout_bits {
 354         u8         ipv6[16][0x8];
 355 };
 356
 357 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 358         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 359         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 360         u8         reserved_at_0[0x80];
 361 };
 362
 363 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 364         u8         smac_47_16[0x20];
 365
 366         u8         smac_15_0[0x10];
 367         u8         ethertype[0x10];
 368
 369         u8         dmac_47_16[0x20];
 370
 371         u8         dmac_15_0[0x10];
 372         u8         first_prio[0x3];
 373         u8         first_cfi[0x1];
 374         u8         first_vid[0xc];
 375
 376         u8         ip_protocol[0x8];
 377         u8         ip_dscp[0x6];
 378         u8         ip_ecn[0x2];
 379         u8         cvlan_tag[0x1];
 380         u8         svlan_tag[0x1];
 381         u8         frag[0x1];
 382         u8         ip_version[0x4];
 383         u8         tcp_flags[0x9];
 384
 385         u8         tcp_sport[0x10];
 386         u8         tcp_dport[0x10];
 387
 388         u8         reserved_at_c0[0x18];
 389         u8         ttl_hoplimit[0x8];
 390
 391         u8         udp_sport[0x10];
 392         u8         udp_dport[0x10];
 393
 394         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 395
 396         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 397 };
 398
 399 struct mlx5_ifc_fte_match_set_misc_bits {
 400         u8         reserved_at_0[0x8];
 401         u8         source_sqn[0x18];
 402
 403         u8         reserved_at_20[0x10];
 404         u8         source_port[0x10];
 405
 406         u8         outer_second_prio[0x3];
 407         u8         outer_second_cfi[0x1];
 408         u8         outer_second_vid[0xc];
 409         u8         inner_second_prio[0x3];
 410         u8         inner_second_cfi[0x1];
 411         u8         inner_second_vid[0xc];
 412
 413         u8         outer_second_cvlan_tag[0x1];
 414         u8         inner_second_cvlan_tag[0x1];
 415         u8         outer_second_svlan_tag[0x1];
 416         u8         inner_second_svlan_tag[0x1];
 417         u8         reserved_at_64[0xc];
 418         u8         gre_protocol[0x10];
 419
 420         u8         gre_key_h[0x18];
 421         u8         gre_key_l[0x8];
 422
 423         u8         vxlan_vni[0x18];
 424         u8         reserved_at_b8[0x8];
 425
 426         u8         reserved_at_c0[0x20];
 427
 428         u8         reserved_at_e0[0xc];
 429         u8         outer_ipv6_flow_label[0x14];
 430
 431         u8         reserved_at_100[0xc];
 432         u8         inner_ipv6_flow_label[0x14];
 433
 434         u8         reserved_at_120[0xe0];
 435 };
 436
 437 struct mlx5_ifc_cmd_pas_bits {
 438         u8         pa_h[0x20];
 439
 440         u8         pa_l[0x14];
 441         u8         reserved_at_34[0xc];
 442 };
 443
 444 struct mlx5_ifc_uint64_bits {
 445         u8         hi[0x20];
 446
 447         u8         lo[0x20];
 448 };
 449
 450 enum {
 451         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 452         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 453         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 454         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 455         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 456         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 457         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 458         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 459         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 460         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 461 };
 462
 463 struct mlx5_ifc_ads_bits {
 464         u8         fl[0x1];
 465         u8         free_ar[0x1];
 466         u8         reserved_at_2[0xe];
 467         u8         pkey_index[0x10];
 468
 469         u8         reserved_at_20[0x8];
 470         u8         grh[0x1];
 471         u8         mlid[0x7];
 472         u8         rlid[0x10];
 473
 474         u8         ack_timeout[0x5];
 475         u8         reserved_at_45[0x3];
 476         u8         src_addr_index[0x8];
 477         u8         reserved_at_50[0x4];
 478         u8         stat_rate[0x4];
 479         u8         hop_limit[0x8];
 480
 481         u8         reserved_at_60[0x4];
 482         u8         tclass[0x8];
 483         u8         flow_label[0x14];
 484
 485         u8         rgid_rip[16][0x8];
 486
 487         u8         reserved_at_100[0x4];
 488         u8         f_dscp[0x1];
 489         u8         f_ecn[0x1];
 490         u8         reserved_at_106[0x1];
 491         u8         f_eth_prio[0x1];
 492         u8         ecn[0x2];
 493         u8         dscp[0x6];
 494         u8         udp_sport[0x10];
 495
 496         u8         dei_cfi[0x1];
 497         u8         eth_prio[0x3];
 498         u8         sl[0x4];
 499         u8         port[0x8];
 500         u8         rmac_47_32[0x10];
 501
 502         u8         rmac_31_0[0x20];
 503 };
 504
 505 struct mlx5_ifc_flow_table_nic_cap_bits {
 506         u8         nic_rx_multi_path_tirs[0x1];
 507         u8         nic_rx_multi_path_tirs_fts[0x1];
 508         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 509         u8         reserved_at_3[0x1fd];
 510
 511         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 512
 513         u8         reserved_at_400[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 518
 519         u8         reserved_at_a00[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 522
 523         u8         reserved_at_e00[0x7200];
 524 };
 525
 526 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 527         u8     reserved_at_0[0x200];
 528
 529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 532
 533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 534
 535         u8      reserved_at_800[0x7800];
 536 };
 537
 538 struct mlx5_ifc_e_switch_cap_bits {
 539         u8         vport_svlan_strip[0x1];
 540         u8         vport_cvlan_strip[0x1];
 541         u8         vport_svlan_insert[0x1];
 542         u8         vport_cvlan_insert_if_not_exist[0x1];
 543         u8         vport_cvlan_insert_overwrite[0x1];
 544         u8         reserved_at_5[0x19];
 545         u8         nic_vport_node_guid_modify[0x1];
 546         u8         nic_vport_port_guid_modify[0x1];
 547
 548         u8         vxlan_encap_decap[0x1];
 549         u8         nvgre_encap_decap[0x1];
 550         u8         reserved_at_22[0x9];
 551         u8         log_max_encap_headers[0x5];
 552         u8         reserved_2b[0x6];
 553         u8         max_encap_header_size[0xa];
 554
 555         u8         reserved_40[0x7c0];
 556
 557 };
 558
 559 struct mlx5_ifc_qos_cap_bits {
 560         u8         packet_pacing[0x1];
 561         u8         esw_scheduling[0x1];
 562         u8         esw_bw_share[0x1];
 563         u8         esw_rate_limit[0x1];
 564         u8         reserved_at_4[0x1c];
 565
 566         u8         reserved_at_20[0x20];
 567
 568         u8         packet_pacing_max_rate[0x20];
 569
 570         u8         packet_pacing_min_rate[0x20];
 571
 572         u8         reserved_at_80[0x10];
 573         u8         packet_pacing_rate_table_size[0x10];
 574
 575         u8         esw_element_type[0x10];
 576         u8         esw_tsar_type[0x10];
 577
 578         u8         reserved_at_c0[0x10];
 579         u8         max_qos_para_vport[0x10];
 580
 581         u8         max_tsar_bw_share[0x20];
 582
 583         u8         reserved_at_100[0x700];
 584 };
 585
 586 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 587         u8         csum_cap[0x1];
 588         u8         vlan_cap[0x1];
 589         u8         lro_cap[0x1];
 590         u8         lro_psh_flag[0x1];
 591         u8         lro_time_stamp[0x1];
 592         u8         reserved_at_5[0x2];
 593         u8         wqe_vlan_insert[0x1];
 594         u8         self_lb_en_modifiable[0x1];
 595         u8         reserved_at_9[0x2];
 596         u8         max_lso_cap[0x5];
 597         u8         multi_pkt_send_wqe[0x2];
 598         u8         wqe_inline_mode[0x2];
 599         u8         rss_ind_tbl_cap[0x4];
 600         u8         reg_umr_sq[0x1];
 601         u8         scatter_fcs[0x1];
 602         u8         reserved_at_1a[0x1];
 603         u8         tunnel_lso_const_out_ip_id[0x1];
 604         u8         reserved_at_1c[0x2];
 605         u8         tunnel_statless_gre[0x1];
 606         u8         tunnel_stateless_vxlan[0x1];
 607
 608         u8         swp[0x1];
 609         u8         swp_csum[0x1];
 610         u8         swp_lso[0x1];
 611         u8         reserved_at_23[0x1d];
 612
 613         u8         reserved_at_40[0x10];
 614         u8         lro_min_mss_size[0x10];
 615
 616         u8         reserved_at_60[0x120];
 617
 618         u8         lro_timer_supported_periods[4][0x20];
 619
 620         u8         reserved_at_200[0x600];
 621 };
 622
 623 struct mlx5_ifc_roce_cap_bits {
 624         u8         roce_apm[0x1];
 625         u8         reserved_at_1[0x1f];
 626
 627         u8         reserved_at_20[0x60];
 628
 629         u8         reserved_at_80[0xc];
 630         u8         l3_type[0x4];
 631         u8         reserved_at_90[0x8];
 632         u8         roce_version[0x8];
 633
 634         u8         reserved_at_a0[0x10];
 635         u8         r_roce_dest_udp_port[0x10];
 636
 637         u8         r_roce_max_src_udp_port[0x10];
 638         u8         r_roce_min_src_udp_port[0x10];
 639
 640         u8         reserved_at_e0[0x10];
 641         u8         roce_address_table_size[0x10];
 642
 643         u8         reserved_at_100[0x700];
 644 };
 645
 646 enum {
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 650         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 656 };
 657
 658 enum {
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 664         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 665         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 666         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 668 };
 669
 670 struct mlx5_ifc_atomic_caps_bits {
 671         u8         reserved_at_0[0x40];
 672
 673         u8         atomic_req_8B_endianness_mode[0x2];
 674         u8         reserved_at_42[0x4];
 675         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 676
 677         u8         reserved_at_47[0x19];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         u8         reserved_at_80[0x10];
 682         u8         atomic_operations[0x10];
 683
 684         u8         reserved_at_a0[0x10];
 685         u8         atomic_size_qp[0x10];
 686
 687         u8         reserved_at_c0[0x10];
 688         u8         atomic_size_dc[0x10];
 689
 690         u8         reserved_at_e0[0x720];
 691 };
 692
 693 struct mlx5_ifc_odp_cap_bits {
 694         u8         reserved_at_0[0x40];
 695
 696         u8         sig[0x1];
 697         u8         reserved_at_41[0x1f];
 698
 699         u8         reserved_at_60[0x20];
 700
 701         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 702
 703         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 704
 705         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 706
 707         u8         reserved_at_e0[0x720];
 708 };
 709
 710 struct mlx5_ifc_calc_op {
 711         u8        reserved_at_0[0x10];
 712         u8        reserved_at_10[0x9];
 713         u8        op_swap_endianness[0x1];
 714         u8        op_min[0x1];
 715         u8        op_xor[0x1];
 716         u8        op_or[0x1];
 717         u8        op_and[0x1];
 718         u8        op_max[0x1];
 719         u8        op_add[0x1];
 720 };
 721
 722 struct mlx5_ifc_vector_calc_cap_bits {
 723         u8         calc_matrix[0x1];
 724         u8         reserved_at_1[0x1f];
 725         u8         reserved_at_20[0x8];
 726         u8         max_vec_count[0x8];
 727         u8         reserved_at_30[0xd];
 728         u8         max_chunk_size[0x3];
 729         struct mlx5_ifc_calc_op calc0;
 730         struct mlx5_ifc_calc_op calc1;
 731         struct mlx5_ifc_calc_op calc2;
 732         struct mlx5_ifc_calc_op calc3;
 733
 734         u8         reserved_at_e0[0x720];
 735 };
 736
 737 enum {
 738         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 739         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 740         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 741 };
 742
 743 enum {
 744         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 745         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 746 };
 747
 748 enum {
 749         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 750         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 751         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 752         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 753         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 754 };
 755
 756 enum {
 757         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 758         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 759         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 760         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 761         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 762         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 763 };
 764
 765 enum {
 766         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 767         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 768 };
 769
 770 enum {
 771         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 772         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 773         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 774 };
 775
 776 enum {
 777         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 778         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 779 };
 780
 781 enum {
 782         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 783         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 784         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 785 };
 786
 787 struct mlx5_ifc_cmd_hca_cap_bits {
 788         u8         reserved_at_0[0x80];
 789
 790         u8         log_max_srq_sz[0x8];
 791         u8         log_max_qp_sz[0x8];
 792         u8         reserved_at_90[0xb];
 793         u8         log_max_qp[0x5];
 794
 795         u8         reserved_at_a0[0xb];
 796         u8         log_max_srq[0x5];
 797         u8         reserved_at_b0[0x10];
 798
 799         u8         reserved_at_c0[0x8];
 800         u8         log_max_cq_sz[0x8];
 801         u8         reserved_at_d0[0xb];
 802         u8         log_max_cq[0x5];
 803
 804         u8         log_max_eq_sz[0x8];
 805         u8         reserved_at_e8[0x2];
 806         u8         log_max_mkey[0x6];
 807         u8         reserved_at_f0[0xc];
 808         u8         log_max_eq[0x4];
 809
 810         u8         max_indirection[0x8];
 811         u8         fixed_buffer_size[0x1];
 812         u8         log_max_mrw_sz[0x7];
 813         u8         force_teardown[0x1];
 814         u8         reserved_at_111[0x1];
 815         u8         log_max_bsf_list_size[0x6];
 816         u8         umr_extended_translation_offset[0x1];
 817         u8         null_mkey[0x1];
 818         u8         log_max_klm_list_size[0x6];
 819
 820         u8         reserved_at_120[0xa];
 821         u8         log_max_ra_req_dc[0x6];
 822         u8         reserved_at_130[0xa];
 823         u8         log_max_ra_res_dc[0x6];
 824
 825         u8         reserved_at_140[0xa];
 826         u8         log_max_ra_req_qp[0x6];
 827         u8         reserved_at_150[0xa];
 828         u8         log_max_ra_res_qp[0x6];
 829
 830         u8         end_pad[0x1];
 831         u8         cc_query_allowed[0x1];
 832         u8         cc_modify_allowed[0x1];
 833         u8         start_pad[0x1];
 834         u8         cache_line_128byte[0x1];
 835         u8         reserved_at_165[0xb];
 836         u8         gid_table_size[0x10];
 837
 838         u8         out_of_seq_cnt[0x1];
 839         u8         vport_counters[0x1];
 840         u8         retransmission_q_counters[0x1];
 841         u8         reserved_at_183[0x1];
 842         u8         modify_rq_counter_set_id[0x1];
 843         u8         reserved_at_185[0x1];
 844         u8         max_qp_cnt[0xa];
 845         u8         pkey_table_size[0x10];
 846
 847         u8         vport_group_manager[0x1];
 848         u8         vhca_group_manager[0x1];
 849         u8         ib_virt[0x1];
 850         u8         eth_virt[0x1];
 851         u8         reserved_at_1a4[0x1];
 852         u8         ets[0x1];
 853         u8         nic_flow_table[0x1];
 854         u8         eswitch_flow_table[0x1];
 855         u8         early_vf_enable[0x1];
 856         u8         mcam_reg[0x1];
 857         u8         pcam_reg[0x1];
 858         u8         local_ca_ack_delay[0x5];
 859         u8         port_module_event[0x1];
 860         u8         reserved_at_1b1[0x1];
 861         u8         ports_check[0x1];
 862         u8         reserved_at_1b3[0x1];
 863         u8         disable_link_up[0x1];
 864         u8         beacon_led[0x1];
 865         u8         port_type[0x2];
 866         u8         num_ports[0x8];
 867
 868         u8         reserved_at_1c0[0x1];
 869         u8         pps[0x1];
 870         u8         pps_modify[0x1];
 871         u8         log_max_msg[0x5];
 872         u8         reserved_at_1c8[0x4];
 873         u8         max_tc[0x4];
 874         u8         reserved_at_1d0[0x1];
 875         u8         dcbx[0x1];
 876         u8         reserved_at_1d2[0x3];
 877         u8         fpga[0x1];
 878         u8         rol_s[0x1];
 879         u8         rol_g[0x1];
 880         u8         reserved_at_1d8[0x1];
 881         u8         wol_s[0x1];
 882         u8         wol_g[0x1];
 883         u8         wol_a[0x1];
 884         u8         wol_b[0x1];
 885         u8         wol_m[0x1];
 886         u8         wol_u[0x1];
 887         u8         wol_p[0x1];
 888
 889         u8         stat_rate_support[0x10];
 890         u8         reserved_at_1f0[0xc];
 891         u8         cqe_version[0x4];
 892
 893         u8         compact_address_vector[0x1];
 894         u8         striding_rq[0x1];
 895         u8         reserved_at_202[0x1];
 896         u8         ipoib_enhanced_offloads[0x1];
 897         u8         ipoib_basic_offloads[0x1];
 898         u8         reserved_at_205[0x5];
 899         u8         umr_fence[0x2];
 900         u8         reserved_at_20c[0x3];
 901         u8         drain_sigerr[0x1];
 902         u8         cmdif_checksum[0x2];
 903         u8         sigerr_cqe[0x1];
 904         u8         reserved_at_213[0x1];
 905         u8         wq_signature[0x1];
 906         u8         sctr_data_cqe[0x1];
 907         u8         reserved_at_216[0x1];
 908         u8         sho[0x1];
 909         u8         tph[0x1];
 910         u8         rf[0x1];
 911         u8         dct[0x1];
 912         u8         qos[0x1];
 913         u8         eth_net_offloads[0x1];
 914         u8         roce[0x1];
 915         u8         atomic[0x1];
 916         u8         reserved_at_21f[0x1];
 917
 918         u8         cq_oi[0x1];
 919         u8         cq_resize[0x1];
 920         u8         cq_moderation[0x1];
 921         u8         reserved_at_223[0x3];
 922         u8         cq_eq_remap[0x1];
 923         u8         pg[0x1];
 924         u8         block_lb_mc[0x1];
 925         u8         reserved_at_229[0x1];
 926         u8         scqe_break_moderation[0x1];
 927         u8         cq_period_start_from_cqe[0x1];
 928         u8         cd[0x1];
 929         u8         reserved_at_22d[0x1];
 930         u8         apm[0x1];
 931         u8         vector_calc[0x1];
 932         u8         umr_ptr_rlky[0x1];
 933         u8         imaicl[0x1];
 934         u8         reserved_at_232[0x4];
 935         u8         qkv[0x1];
 936         u8         pkv[0x1];
 937         u8         set_deth_sqpn[0x1];
 938         u8         reserved_at_239[0x3];
 939         u8         xrc[0x1];
 940         u8         ud[0x1];
 941         u8         uc[0x1];
 942         u8         rc[0x1];
 943
 944         u8         uar_4k[0x1];
 945         u8         reserved_at_241[0x9];
 946         u8         uar_sz[0x6];
 947         u8         reserved_at_250[0x8];
 948         u8         log_pg_sz[0x8];
 949
 950         u8         bf[0x1];
 951         u8         driver_version[0x1];
 952         u8         pad_tx_eth_packet[0x1];
 953         u8         reserved_at_263[0x8];
 954         u8         log_bf_reg_size[0x5];
 955
 956         u8         reserved_at_270[0xb];
 957         u8         lag_master[0x1];
 958         u8         num_lag_ports[0x4];
 959
 960         u8         reserved_at_280[0x10];
 961         u8         max_wqe_sz_sq[0x10];
 962
 963         u8         reserved_at_2a0[0x10];
 964         u8         max_wqe_sz_rq[0x10];
 965
 966         u8         reserved_at_2c0[0x10];
 967         u8         max_wqe_sz_sq_dc[0x10];
 968
 969         u8         reserved_at_2e0[0x7];
 970         u8         max_qp_mcg[0x19];
 971
 972         u8         reserved_at_300[0x18];
 973         u8         log_max_mcg[0x8];
 974
 975         u8         reserved_at_320[0x3];
 976         u8         log_max_transport_domain[0x5];
 977         u8         reserved_at_328[0x3];
 978         u8         log_max_pd[0x5];
 979         u8         reserved_at_330[0xb];
 980         u8         log_max_xrcd[0x5];
 981
 982         u8         reserved_at_340[0x8];
 983         u8         log_max_flow_counter_bulk[0x8];
 984         u8         max_flow_counter[0x10];
 985
 986
 987         u8         reserved_at_360[0x3];
 988         u8         log_max_rq[0x5];
 989         u8         reserved_at_368[0x3];
 990         u8         log_max_sq[0x5];
 991         u8         reserved_at_370[0x3];
 992         u8         log_max_tir[0x5];
 993         u8         reserved_at_378[0x3];
 994         u8         log_max_tis[0x5];
 995
 996         u8         basic_cyclic_rcv_wqe[0x1];
 997         u8         reserved_at_381[0x2];
 998         u8         log_max_rmp[0x5];
 999         u8         reserved_at_388[0x3];
1000         u8         log_max_rqt[0x5];
1001         u8         reserved_at_390[0x3];
1002         u8         log_max_rqt_size[0x5];
1003         u8         reserved_at_398[0x3];
1004         u8         log_max_tis_per_sq[0x5];
1005
1006         u8         reserved_at_3a0[0x3];
1007         u8         log_max_stride_sz_rq[0x5];
1008         u8         reserved_at_3a8[0x3];
1009         u8         log_min_stride_sz_rq[0x5];
1010         u8         reserved_at_3b0[0x3];
1011         u8         log_max_stride_sz_sq[0x5];
1012         u8         reserved_at_3b8[0x3];
1013         u8         log_min_stride_sz_sq[0x5];
1014
1015         u8         reserved_at_3c0[0x1b];
1016         u8         log_max_wq_sz[0x5];
1017
1018         u8         nic_vport_change_event[0x1];
1019         u8         reserved_at_3e1[0xa];
1020         u8         log_max_vlan_list[0x5];
1021         u8         reserved_at_3f0[0x3];
1022         u8         log_max_current_mc_list[0x5];
1023         u8         reserved_at_3f8[0x3];
1024         u8         log_max_current_uc_list[0x5];
1025
1026         u8         reserved_at_400[0x80];
1027
1028         u8         reserved_at_480[0x3];
1029         u8         log_max_l2_table[0x5];
1030         u8         reserved_at_488[0x8];
1031         u8         log_uar_page_sz[0x10];
1032
1033         u8         reserved_at_4a0[0x20];
1034         u8         device_frequency_mhz[0x20];
1035         u8         device_frequency_khz[0x20];
1036
1037         u8         reserved_at_500[0x20];
1038         u8         num_of_uars_per_page[0x20];
1039         u8         reserved_at_540[0x40];
1040
1041         u8         reserved_at_580[0x3f];
1042         u8         cqe_compression[0x1];
1043
1044         u8         cqe_compression_timeout[0x10];
1045         u8         cqe_compression_max_num[0x10];
1046
1047         u8         reserved_at_5e0[0x10];
1048         u8         tag_matching[0x1];
1049         u8         rndv_offload_rc[0x1];
1050         u8         rndv_offload_dc[0x1];
1051         u8         log_tag_matching_list_sz[0x5];
1052         u8         reserved_at_5f8[0x3];
1053         u8         log_max_xrq[0x5];
1054
1055         u8         reserved_at_600[0x200];
1056 };
1057
1058 enum mlx5_flow_destination_type {
1059         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1060         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1061         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1062
1063         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1064 };
1065
1066 struct mlx5_ifc_dest_format_struct_bits {
1067         u8         destination_type[0x8];
1068         u8         destination_id[0x18];
1069
1070         u8         reserved_at_20[0x20];
1071 };
1072
1073 struct mlx5_ifc_flow_counter_list_bits {
1074         u8         reserved_at_0[0x10];
1075         u8         flow_counter_id[0x10];
1076
1077         u8         reserved_at_20[0x20];
1078 };
1079
1080 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1081         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1082         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1083         u8         reserved_at_0[0x40];
1084 };
1085
1086 struct mlx5_ifc_fte_match_param_bits {
1087         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1088
1089         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1090
1091         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1092
1093         u8         reserved_at_600[0xa00];
1094 };
1095
1096 enum {
1097         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1098         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1099         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1100         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1101         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1102 };
1103
1104 struct mlx5_ifc_rx_hash_field_select_bits {
1105         u8         l3_prot_type[0x1];
1106         u8         l4_prot_type[0x1];
1107         u8         selected_fields[0x1e];
1108 };
1109
1110 enum {
1111         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1112         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1113 };
1114
1115 enum {
1116         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1117         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1118 };
1119
1120 struct mlx5_ifc_wq_bits {
1121         u8         wq_type[0x4];
1122         u8         wq_signature[0x1];
1123         u8         end_padding_mode[0x2];
1124         u8         cd_slave[0x1];
1125         u8         reserved_at_8[0x18];
1126
1127         u8         hds_skip_first_sge[0x1];
1128         u8         log2_hds_buf_size[0x3];
1129         u8         reserved_at_24[0x7];
1130         u8         page_offset[0x5];
1131         u8         lwm[0x10];
1132
1133         u8         reserved_at_40[0x8];
1134         u8         pd[0x18];
1135
1136         u8         reserved_at_60[0x8];
1137         u8         uar_page[0x18];
1138
1139         u8         dbr_addr[0x40];
1140
1141         u8         hw_counter[0x20];
1142
1143         u8         sw_counter[0x20];
1144
1145         u8         reserved_at_100[0xc];
1146         u8         log_wq_stride[0x4];
1147         u8         reserved_at_110[0x3];
1148         u8         log_wq_pg_sz[0x5];
1149         u8         reserved_at_118[0x3];
1150         u8         log_wq_sz[0x5];
1151
1152         u8         reserved_at_120[0x15];
1153         u8         log_wqe_num_of_strides[0x3];
1154         u8         two_byte_shift_en[0x1];
1155         u8         reserved_at_139[0x4];
1156         u8         log_wqe_stride_size[0x3];
1157
1158         u8         reserved_at_140[0x4c0];
1159
1160         struct mlx5_ifc_cmd_pas_bits pas[0];
1161 };
1162
1163 struct mlx5_ifc_rq_num_bits {
1164         u8         reserved_at_0[0x8];
1165         u8         rq_num[0x18];
1166 };
1167
1168 struct mlx5_ifc_mac_address_layout_bits {
1169         u8         reserved_at_0[0x10];
1170         u8         mac_addr_47_32[0x10];
1171
1172         u8         mac_addr_31_0[0x20];
1173 };
1174
1175 struct mlx5_ifc_vlan_layout_bits {
1176         u8         reserved_at_0[0x14];
1177         u8         vlan[0x0c];
1178
1179         u8         reserved_at_20[0x20];
1180 };
1181
1182 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1183         u8         reserved_at_0[0xa0];
1184
1185         u8         min_time_between_cnps[0x20];
1186
1187         u8         reserved_at_c0[0x12];
1188         u8         cnp_dscp[0x6];
1189         u8         reserved_at_d8[0x5];
1190         u8         cnp_802p_prio[0x3];
1191
1192         u8         reserved_at_e0[0x720];
1193 };
1194
1195 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1196         u8         reserved_at_0[0x60];
1197
1198         u8         reserved_at_60[0x4];
1199         u8         clamp_tgt_rate[0x1];
1200         u8         reserved_at_65[0x3];
1201         u8         clamp_tgt_rate_after_time_inc[0x1];
1202         u8         reserved_at_69[0x17];
1203
1204         u8         reserved_at_80[0x20];
1205
1206         u8         rpg_time_reset[0x20];
1207
1208         u8         rpg_byte_reset[0x20];
1209
1210         u8         rpg_threshold[0x20];
1211
1212         u8         rpg_max_rate[0x20];
1213
1214         u8         rpg_ai_rate[0x20];
1215
1216         u8         rpg_hai_rate[0x20];
1217
1218         u8         rpg_gd[0x20];
1219
1220         u8         rpg_min_dec_fac[0x20];
1221
1222         u8         rpg_min_rate[0x20];
1223
1224         u8         reserved_at_1c0[0xe0];
1225
1226         u8         rate_to_set_on_first_cnp[0x20];
1227
1228         u8         dce_tcp_g[0x20];
1229
1230         u8         dce_tcp_rtt[0x20];
1231
1232         u8         rate_reduce_monitor_period[0x20];
1233
1234         u8         reserved_at_320[0x20];
1235
1236         u8         initial_alpha_value[0x20];
1237
1238         u8         reserved_at_360[0x4a0];
1239 };
1240
1241 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1242         u8         reserved_at_0[0x80];
1243
1244         u8         rppp_max_rps[0x20];
1245
1246         u8         rpg_time_reset[0x20];
1247
1248         u8         rpg_byte_reset[0x20];
1249
1250         u8         rpg_threshold[0x20];
1251
1252         u8         rpg_max_rate[0x20];
1253
1254         u8         rpg_ai_rate[0x20];
1255
1256         u8         rpg_hai_rate[0x20];
1257
1258         u8         rpg_gd[0x20];
1259
1260         u8         rpg_min_dec_fac[0x20];
1261
1262         u8         rpg_min_rate[0x20];
1263
1264         u8         reserved_at_1c0[0x640];
1265 };
1266
1267 enum {
1268         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1269         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1270         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1271 };
1272
1273 struct mlx5_ifc_resize_field_select_bits {
1274         u8         resize_field_select[0x20];
1275 };
1276
1277 enum {
1278         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1279         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1280         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1281         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1282 };
1283
1284 struct mlx5_ifc_modify_field_select_bits {
1285         u8         modify_field_select[0x20];
1286 };
1287
1288 struct mlx5_ifc_field_select_r_roce_np_bits {
1289         u8         field_select_r_roce_np[0x20];
1290 };
1291
1292 struct mlx5_ifc_field_select_r_roce_rp_bits {
1293         u8         field_select_r_roce_rp[0x20];
1294 };
1295
1296 enum {
1297         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1298         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1299         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1300         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1301         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1302         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1303         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1304         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1305         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1306         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1307 };
1308
1309 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1310         u8         field_select_8021qaurp[0x20];
1311 };
1312
1313 struct mlx5_ifc_phys_layer_cntrs_bits {
1314         u8         time_since_last_clear_high[0x20];
1315
1316         u8         time_since_last_clear_low[0x20];
1317
1318         u8         symbol_errors_high[0x20];
1319
1320         u8         symbol_errors_low[0x20];
1321
1322         u8         sync_headers_errors_high[0x20];
1323
1324         u8         sync_headers_errors_low[0x20];
1325
1326         u8         edpl_bip_errors_lane0_high[0x20];
1327
1328         u8         edpl_bip_errors_lane0_low[0x20];
1329
1330         u8         edpl_bip_errors_lane1_high[0x20];
1331
1332         u8         edpl_bip_errors_lane1_low[0x20];
1333
1334         u8         edpl_bip_errors_lane2_high[0x20];
1335
1336         u8         edpl_bip_errors_lane2_low[0x20];
1337
1338         u8         edpl_bip_errors_lane3_high[0x20];
1339
1340         u8         edpl_bip_errors_lane3_low[0x20];
1341
1342         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1343
1344         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1345
1346         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1347
1348         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1349
1350         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1351
1352         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1353
1354         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1355
1356         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1357
1358         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1359
1360         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1361
1362         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1363
1364         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1365
1366         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1367
1368         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1369
1370         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1371
1372         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1373
1374         u8         rs_fec_corrected_blocks_high[0x20];
1375
1376         u8         rs_fec_corrected_blocks_low[0x20];
1377
1378         u8         rs_fec_uncorrectable_blocks_high[0x20];
1379
1380         u8         rs_fec_uncorrectable_blocks_low[0x20];
1381
1382         u8         rs_fec_no_errors_blocks_high[0x20];
1383
1384         u8         rs_fec_no_errors_blocks_low[0x20];
1385
1386         u8         rs_fec_single_error_blocks_high[0x20];
1387
1388         u8         rs_fec_single_error_blocks_low[0x20];
1389
1390         u8         rs_fec_corrected_symbols_total_high[0x20];
1391
1392         u8         rs_fec_corrected_symbols_total_low[0x20];
1393
1394         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1395
1396         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1397
1398         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1399
1400         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1401
1402         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1403
1404         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1405
1406         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1407
1408         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1409
1410         u8         link_down_events[0x20];
1411
1412         u8         successful_recovery_events[0x20];
1413
1414         u8         reserved_at_640[0x180];
1415 };
1416
1417 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1418         u8         time_since_last_clear_high[0x20];
1419
1420         u8         time_since_last_clear_low[0x20];
1421
1422         u8         phy_received_bits_high[0x20];
1423
1424         u8         phy_received_bits_low[0x20];
1425
1426         u8         phy_symbol_errors_high[0x20];
1427
1428         u8         phy_symbol_errors_low[0x20];
1429
1430         u8         phy_corrected_bits_high[0x20];
1431
1432         u8         phy_corrected_bits_low[0x20];
1433
1434         u8         phy_corrected_bits_lane0_high[0x20];
1435
1436         u8         phy_corrected_bits_lane0_low[0x20];
1437
1438         u8         phy_corrected_bits_lane1_high[0x20];
1439
1440         u8         phy_corrected_bits_lane1_low[0x20];
1441
1442         u8         phy_corrected_bits_lane2_high[0x20];
1443
1444         u8         phy_corrected_bits_lane2_low[0x20];
1445
1446         u8         phy_corrected_bits_lane3_high[0x20];
1447
1448         u8         phy_corrected_bits_lane3_low[0x20];
1449
1450         u8         reserved_at_200[0x5c0];
1451 };
1452
1453 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1454         u8         symbol_error_counter[0x10];
1455
1456         u8         link_error_recovery_counter[0x8];
1457
1458         u8         link_downed_counter[0x8];
1459
1460         u8         port_rcv_errors[0x10];
1461
1462         u8         port_rcv_remote_physical_errors[0x10];
1463
1464         u8         port_rcv_switch_relay_errors[0x10];
1465
1466         u8         port_xmit_discards[0x10];
1467
1468         u8         port_xmit_constraint_errors[0x8];
1469
1470         u8         port_rcv_constraint_errors[0x8];
1471
1472         u8         reserved_at_70[0x8];
1473
1474         u8         link_overrun_errors[0x8];
1475
1476         u8         reserved_at_80[0x10];
1477
1478         u8         vl_15_dropped[0x10];
1479
1480         u8         reserved_at_a0[0x80];
1481
1482         u8         port_xmit_wait[0x20];
1483 };
1484
1485 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1486         u8         transmit_queue_high[0x20];
1487
1488         u8         transmit_queue_low[0x20];
1489
1490         u8         reserved_at_40[0x780];
1491 };
1492
1493 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1494         u8         rx_octets_high[0x20];
1495
1496         u8         rx_octets_low[0x20];
1497
1498         u8         reserved_at_40[0xc0];
1499
1500         u8         rx_frames_high[0x20];
1501
1502         u8         rx_frames_low[0x20];
1503
1504         u8         tx_octets_high[0x20];
1505
1506         u8         tx_octets_low[0x20];
1507
1508         u8         reserved_at_180[0xc0];
1509
1510         u8         tx_frames_high[0x20];
1511
1512         u8         tx_frames_low[0x20];
1513
1514         u8         rx_pause_high[0x20];
1515
1516         u8         rx_pause_low[0x20];
1517
1518         u8         rx_pause_duration_high[0x20];
1519
1520         u8         rx_pause_duration_low[0x20];
1521
1522         u8         tx_pause_high[0x20];
1523
1524         u8         tx_pause_low[0x20];
1525
1526         u8         tx_pause_duration_high[0x20];
1527
1528         u8         tx_pause_duration_low[0x20];
1529
1530         u8         rx_pause_transition_high[0x20];
1531
1532         u8         rx_pause_transition_low[0x20];
1533
1534         u8         reserved_at_3c0[0x400];
1535 };
1536
1537 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1538         u8         port_transmit_wait_high[0x20];
1539
1540         u8         port_transmit_wait_low[0x20];
1541
1542         u8         reserved_at_40[0x780];
1543 };
1544
1545 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1546         u8         dot3stats_alignment_errors_high[0x20];
1547
1548         u8         dot3stats_alignment_errors_low[0x20];
1549
1550         u8         dot3stats_fcs_errors_high[0x20];
1551
1552         u8         dot3stats_fcs_errors_low[0x20];
1553
1554         u8         dot3stats_single_collision_frames_high[0x20];
1555
1556         u8         dot3stats_single_collision_frames_low[0x20];
1557
1558         u8         dot3stats_multiple_collision_frames_high[0x20];
1559
1560         u8         dot3stats_multiple_collision_frames_low[0x20];
1561
1562         u8         dot3stats_sqe_test_errors_high[0x20];
1563
1564         u8         dot3stats_sqe_test_errors_low[0x20];
1565
1566         u8         dot3stats_deferred_transmissions_high[0x20];
1567
1568         u8         dot3stats_deferred_transmissions_low[0x20];
1569
1570         u8         dot3stats_late_collisions_high[0x20];
1571
1572         u8         dot3stats_late_collisions_low[0x20];
1573
1574         u8         dot3stats_excessive_collisions_high[0x20];
1575
1576         u8         dot3stats_excessive_collisions_low[0x20];
1577
1578         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1579
1580         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1581
1582         u8         dot3stats_carrier_sense_errors_high[0x20];
1583
1584         u8         dot3stats_carrier_sense_errors_low[0x20];
1585
1586         u8         dot3stats_frame_too_longs_high[0x20];
1587
1588         u8         dot3stats_frame_too_longs_low[0x20];
1589
1590         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1591
1592         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1593
1594         u8         dot3stats_symbol_errors_high[0x20];
1595
1596         u8         dot3stats_symbol_errors_low[0x20];
1597
1598         u8         dot3control_in_unknown_opcodes_high[0x20];
1599
1600         u8         dot3control_in_unknown_opcodes_low[0x20];
1601
1602         u8         dot3in_pause_frames_high[0x20];
1603
1604         u8         dot3in_pause_frames_low[0x20];
1605
1606         u8         dot3out_pause_frames_high[0x20];
1607
1608         u8         dot3out_pause_frames_low[0x20];
1609
1610         u8         reserved_at_400[0x3c0];
1611 };
1612
1613 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1614         u8         ether_stats_drop_events_high[0x20];
1615
1616         u8         ether_stats_drop_events_low[0x20];
1617
1618         u8         ether_stats_octets_high[0x20];
1619
1620         u8         ether_stats_octets_low[0x20];
1621
1622         u8         ether_stats_pkts_high[0x20];
1623
1624         u8         ether_stats_pkts_low[0x20];
1625
1626         u8         ether_stats_broadcast_pkts_high[0x20];
1627
1628         u8         ether_stats_broadcast_pkts_low[0x20];
1629
1630         u8         ether_stats_multicast_pkts_high[0x20];
1631
1632         u8         ether_stats_multicast_pkts_low[0x20];
1633
1634         u8         ether_stats_crc_align_errors_high[0x20];
1635
1636         u8         ether_stats_crc_align_errors_low[0x20];
1637
1638         u8         ether_stats_undersize_pkts_high[0x20];
1639
1640         u8         ether_stats_undersize_pkts_low[0x20];
1641
1642         u8         ether_stats_oversize_pkts_high[0x20];
1643
1644         u8         ether_stats_oversize_pkts_low[0x20];
1645
1646         u8         ether_stats_fragments_high[0x20];
1647
1648         u8         ether_stats_fragments_low[0x20];
1649
1650         u8         ether_stats_jabbers_high[0x20];
1651
1652         u8         ether_stats_jabbers_low[0x20];
1653
1654         u8         ether_stats_collisions_high[0x20];
1655
1656         u8         ether_stats_collisions_low[0x20];
1657
1658         u8         ether_stats_pkts64octets_high[0x20];
1659
1660         u8         ether_stats_pkts64octets_low[0x20];
1661
1662         u8         ether_stats_pkts65to127octets_high[0x20];
1663
1664         u8         ether_stats_pkts65to127octets_low[0x20];
1665
1666         u8         ether_stats_pkts128to255octets_high[0x20];
1667
1668         u8         ether_stats_pkts128to255octets_low[0x20];
1669
1670         u8         ether_stats_pkts256to511octets_high[0x20];
1671
1672         u8         ether_stats_pkts256to511octets_low[0x20];
1673
1674         u8         ether_stats_pkts512to1023octets_high[0x20];
1675
1676         u8         ether_stats_pkts512to1023octets_low[0x20];
1677
1678         u8         ether_stats_pkts1024to1518octets_high[0x20];
1679
1680         u8         ether_stats_pkts1024to1518octets_low[0x20];
1681
1682         u8         ether_stats_pkts1519to2047octets_high[0x20];
1683
1684         u8         ether_stats_pkts1519to2047octets_low[0x20];
1685
1686         u8         ether_stats_pkts2048to4095octets_high[0x20];
1687
1688         u8         ether_stats_pkts2048to4095octets_low[0x20];
1689
1690         u8         ether_stats_pkts4096to8191octets_high[0x20];
1691
1692         u8         ether_stats_pkts4096to8191octets_low[0x20];
1693
1694         u8         ether_stats_pkts8192to10239octets_high[0x20];
1695
1696         u8         ether_stats_pkts8192to10239octets_low[0x20];
1697
1698         u8         reserved_at_540[0x280];
1699 };
1700
1701 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1702         u8         if_in_octets_high[0x20];
1703
1704         u8         if_in_octets_low[0x20];
1705
1706         u8         if_in_ucast_pkts_high[0x20];
1707
1708         u8         if_in_ucast_pkts_low[0x20];
1709
1710         u8         if_in_discards_high[0x20];
1711
1712         u8         if_in_discards_low[0x20];
1713
1714         u8         if_in_errors_high[0x20];
1715
1716         u8         if_in_errors_low[0x20];
1717
1718         u8         if_in_unknown_protos_high[0x20];
1719
1720         u8         if_in_unknown_protos_low[0x20];
1721
1722         u8         if_out_octets_high[0x20];
1723
1724         u8         if_out_octets_low[0x20];
1725
1726         u8         if_out_ucast_pkts_high[0x20];
1727
1728         u8         if_out_ucast_pkts_low[0x20];
1729
1730         u8         if_out_discards_high[0x20];
1731
1732         u8         if_out_discards_low[0x20];
1733
1734         u8         if_out_errors_high[0x20];
1735
1736         u8         if_out_errors_low[0x20];
1737
1738         u8         if_in_multicast_pkts_high[0x20];
1739
1740         u8         if_in_multicast_pkts_low[0x20];
1741
1742         u8         if_in_broadcast_pkts_high[0x20];
1743
1744         u8         if_in_broadcast_pkts_low[0x20];
1745
1746         u8         if_out_multicast_pkts_high[0x20];
1747
1748         u8         if_out_multicast_pkts_low[0x20];
1749
1750         u8         if_out_broadcast_pkts_high[0x20];
1751
1752         u8         if_out_broadcast_pkts_low[0x20];
1753
1754         u8         reserved_at_340[0x480];
1755 };
1756
1757 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1758         u8         a_frames_transmitted_ok_high[0x20];
1759
1760         u8         a_frames_transmitted_ok_low[0x20];
1761
1762         u8         a_frames_received_ok_high[0x20];
1763
1764         u8         a_frames_received_ok_low[0x20];
1765
1766         u8         a_frame_check_sequence_errors_high[0x20];
1767
1768         u8         a_frame_check_sequence_errors_low[0x20];
1769
1770         u8         a_alignment_errors_high[0x20];
1771
1772         u8         a_alignment_errors_low[0x20];
1773
1774         u8         a_octets_transmitted_ok_high[0x20];
1775
1776         u8         a_octets_transmitted_ok_low[0x20];
1777
1778         u8         a_octets_received_ok_high[0x20];
1779
1780         u8         a_octets_received_ok_low[0x20];
1781
1782         u8         a_multicast_frames_xmitted_ok_high[0x20];
1783
1784         u8         a_multicast_frames_xmitted_ok_low[0x20];
1785
1786         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1787
1788         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1789
1790         u8         a_multicast_frames_received_ok_high[0x20];
1791
1792         u8         a_multicast_frames_received_ok_low[0x20];
1793
1794         u8         a_broadcast_frames_received_ok_high[0x20];
1795
1796         u8         a_broadcast_frames_received_ok_low[0x20];
1797
1798         u8         a_in_range_length_errors_high[0x20];
1799
1800         u8         a_in_range_length_errors_low[0x20];
1801
1802         u8         a_out_of_range_length_field_high[0x20];
1803
1804         u8         a_out_of_range_length_field_low[0x20];
1805
1806         u8         a_frame_too_long_errors_high[0x20];
1807
1808         u8         a_frame_too_long_errors_low[0x20];
1809
1810         u8         a_symbol_error_during_carrier_high[0x20];
1811
1812         u8         a_symbol_error_during_carrier_low[0x20];
1813
1814         u8         a_mac_control_frames_transmitted_high[0x20];
1815
1816         u8         a_mac_control_frames_transmitted_low[0x20];
1817
1818         u8         a_mac_control_frames_received_high[0x20];
1819
1820         u8         a_mac_control_frames_received_low[0x20];
1821
1822         u8         a_unsupported_opcodes_received_high[0x20];
1823
1824         u8         a_unsupported_opcodes_received_low[0x20];
1825
1826         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1827
1828         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1829
1830         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1831
1832         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1833
1834         u8         reserved_at_4c0[0x300];
1835 };
1836
1837 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1838         u8         life_time_counter_high[0x20];
1839
1840         u8         life_time_counter_low[0x20];
1841
1842         u8         rx_errors[0x20];
1843
1844         u8         tx_errors[0x20];
1845
1846         u8         l0_to_recovery_eieos[0x20];
1847
1848         u8         l0_to_recovery_ts[0x20];
1849
1850         u8         l0_to_recovery_framing[0x20];
1851
1852         u8         l0_to_recovery_retrain[0x20];
1853
1854         u8         crc_error_dllp[0x20];
1855
1856         u8         crc_error_tlp[0x20];
1857
1858         u8         reserved_at_140[0x680];
1859 };
1860
1861 struct mlx5_ifc_cmd_inter_comp_event_bits {
1862         u8         command_completion_vector[0x20];
1863
1864         u8         reserved_at_20[0xc0];
1865 };
1866
1867 struct mlx5_ifc_stall_vl_event_bits {
1868         u8         reserved_at_0[0x18];
1869         u8         port_num[0x1];
1870         u8         reserved_at_19[0x3];
1871         u8         vl[0x4];
1872
1873         u8         reserved_at_20[0xa0];
1874 };
1875
1876 struct mlx5_ifc_db_bf_congestion_event_bits {
1877         u8         event_subtype[0x8];
1878         u8         reserved_at_8[0x8];
1879         u8         congestion_level[0x8];
1880         u8         reserved_at_18[0x8];
1881
1882         u8         reserved_at_20[0xa0];
1883 };
1884
1885 struct mlx5_ifc_gpio_event_bits {
1886         u8         reserved_at_0[0x60];
1887
1888         u8         gpio_event_hi[0x20];
1889
1890         u8         gpio_event_lo[0x20];
1891
1892         u8         reserved_at_a0[0x40];
1893 };
1894
1895 struct mlx5_ifc_port_state_change_event_bits {
1896         u8         reserved_at_0[0x40];
1897
1898         u8         port_num[0x4];
1899         u8         reserved_at_44[0x1c];
1900
1901         u8         reserved_at_60[0x80];
1902 };
1903
1904 struct mlx5_ifc_dropped_packet_logged_bits {
1905         u8         reserved_at_0[0xe0];
1906 };
1907
1908 enum {
1909         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1910         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1911 };
1912
1913 struct mlx5_ifc_cq_error_bits {
1914         u8         reserved_at_0[0x8];
1915         u8         cqn[0x18];
1916
1917         u8         reserved_at_20[0x20];
1918
1919         u8         reserved_at_40[0x18];
1920         u8         syndrome[0x8];
1921
1922         u8         reserved_at_60[0x80];
1923 };
1924
1925 struct mlx5_ifc_rdma_page_fault_event_bits {
1926         u8         bytes_committed[0x20];
1927
1928         u8         r_key[0x20];
1929
1930         u8         reserved_at_40[0x10];
1931         u8         packet_len[0x10];
1932
1933         u8         rdma_op_len[0x20];
1934
1935         u8         rdma_va[0x40];
1936
1937         u8         reserved_at_c0[0x5];
1938         u8         rdma[0x1];
1939         u8         write[0x1];
1940         u8         requestor[0x1];
1941         u8         qp_number[0x18];
1942 };
1943
1944 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1945         u8         bytes_committed[0x20];
1946
1947         u8         reserved_at_20[0x10];
1948         u8         wqe_index[0x10];
1949
1950         u8         reserved_at_40[0x10];
1951         u8         len[0x10];
1952
1953         u8         reserved_at_60[0x60];
1954
1955         u8         reserved_at_c0[0x5];
1956         u8         rdma[0x1];
1957         u8         write_read[0x1];
1958         u8         requestor[0x1];
1959         u8         qpn[0x18];
1960 };
1961
1962 struct mlx5_ifc_qp_events_bits {
1963         u8         reserved_at_0[0xa0];
1964
1965         u8         type[0x8];
1966         u8         reserved_at_a8[0x18];
1967
1968         u8         reserved_at_c0[0x8];
1969         u8         qpn_rqn_sqn[0x18];
1970 };
1971
1972 struct mlx5_ifc_dct_events_bits {
1973         u8         reserved_at_0[0xc0];
1974
1975         u8         reserved_at_c0[0x8];
1976         u8         dct_number[0x18];
1977 };
1978
1979 struct mlx5_ifc_comp_event_bits {
1980         u8         reserved_at_0[0xc0];
1981
1982         u8         reserved_at_c0[0x8];
1983         u8         cq_number[0x18];
1984 };
1985
1986 enum {
1987         MLX5_QPC_STATE_RST        = 0x0,
1988         MLX5_QPC_STATE_INIT       = 0x1,
1989         MLX5_QPC_STATE_RTR        = 0x2,
1990         MLX5_QPC_STATE_RTS        = 0x3,
1991         MLX5_QPC_STATE_SQER       = 0x4,
1992         MLX5_QPC_STATE_ERR        = 0x6,
1993         MLX5_QPC_STATE_SQD        = 0x7,
1994         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1995 };
1996
1997 enum {
1998         MLX5_QPC_ST_RC            = 0x0,
1999         MLX5_QPC_ST_UC            = 0x1,
2000         MLX5_QPC_ST_UD            = 0x2,
2001         MLX5_QPC_ST_XRC           = 0x3,
2002         MLX5_QPC_ST_DCI           = 0x5,
2003         MLX5_QPC_ST_QP0           = 0x7,
2004         MLX5_QPC_ST_QP1           = 0x8,
2005         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2006         MLX5_QPC_ST_REG_UMR       = 0xc,
2007 };
2008
2009 enum {
2010         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2011         MLX5_QPC_PM_STATE_REARM     = 0x1,
2012         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2013         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2014 };
2015
2016 enum {
2017         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2018         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2019 };
2020
2021 enum {
2022         MLX5_QPC_MTU_256_BYTES        = 0x1,
2023         MLX5_QPC_MTU_512_BYTES        = 0x2,
2024         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2025         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2026         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2027         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2028 };
2029
2030 enum {
2031         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2032         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2033         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2034         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2035         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2036         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2037         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2038         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2039 };
2040
2041 enum {
2042         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2043         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2044         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2045 };
2046
2047 enum {
2048         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2049         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2050         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2051 };
2052
2053 struct mlx5_ifc_qpc_bits {
2054         u8         state[0x4];
2055         u8         lag_tx_port_affinity[0x4];
2056         u8         st[0x8];
2057         u8         reserved_at_10[0x3];
2058         u8         pm_state[0x2];
2059         u8         reserved_at_15[0x7];
2060         u8         end_padding_mode[0x2];
2061         u8         reserved_at_1e[0x2];
2062
2063         u8         wq_signature[0x1];
2064         u8         block_lb_mc[0x1];
2065         u8         atomic_like_write_en[0x1];
2066         u8         latency_sensitive[0x1];
2067         u8         reserved_at_24[0x1];
2068         u8         drain_sigerr[0x1];
2069         u8         reserved_at_26[0x2];
2070         u8         pd[0x18];
2071
2072         u8         mtu[0x3];
2073         u8         log_msg_max[0x5];
2074         u8         reserved_at_48[0x1];
2075         u8         log_rq_size[0x4];
2076         u8         log_rq_stride[0x3];
2077         u8         no_sq[0x1];
2078         u8         log_sq_size[0x4];
2079         u8         reserved_at_55[0x6];
2080         u8         rlky[0x1];
2081         u8         ulp_stateless_offload_mode[0x4];
2082
2083         u8         counter_set_id[0x8];
2084         u8         uar_page[0x18];
2085
2086         u8         reserved_at_80[0x8];
2087         u8         user_index[0x18];
2088
2089         u8         reserved_at_a0[0x3];
2090         u8         log_page_size[0x5];
2091         u8         remote_qpn[0x18];
2092
2093         struct mlx5_ifc_ads_bits primary_address_path;
2094
2095         struct mlx5_ifc_ads_bits secondary_address_path;
2096
2097         u8         log_ack_req_freq[0x4];
2098         u8         reserved_at_384[0x4];
2099         u8         log_sra_max[0x3];
2100         u8         reserved_at_38b[0x2];
2101         u8         retry_count[0x3];
2102         u8         rnr_retry[0x3];
2103         u8         reserved_at_393[0x1];
2104         u8         fre[0x1];
2105         u8         cur_rnr_retry[0x3];
2106         u8         cur_retry_count[0x3];
2107         u8         reserved_at_39b[0x5];
2108
2109         u8         reserved_at_3a0[0x20];
2110
2111         u8         reserved_at_3c0[0x8];
2112         u8         next_send_psn[0x18];
2113
2114         u8         reserved_at_3e0[0x8];
2115         u8         cqn_snd[0x18];
2116
2117         u8         reserved_at_400[0x8];
2118         u8         deth_sqpn[0x18];
2119
2120         u8         reserved_at_420[0x20];
2121
2122         u8         reserved_at_440[0x8];
2123         u8         last_acked_psn[0x18];
2124
2125         u8         reserved_at_460[0x8];
2126         u8         ssn[0x18];
2127
2128         u8         reserved_at_480[0x8];
2129         u8         log_rra_max[0x3];
2130         u8         reserved_at_48b[0x1];
2131         u8         atomic_mode[0x4];
2132         u8         rre[0x1];
2133         u8         rwe[0x1];
2134         u8         rae[0x1];
2135         u8         reserved_at_493[0x1];
2136         u8         page_offset[0x6];
2137         u8         reserved_at_49a[0x3];
2138         u8         cd_slave_receive[0x1];
2139         u8         cd_slave_send[0x1];
2140         u8         cd_master[0x1];
2141
2142         u8         reserved_at_4a0[0x3];
2143         u8         min_rnr_nak[0x5];
2144         u8         next_rcv_psn[0x18];
2145
2146         u8         reserved_at_4c0[0x8];
2147         u8         xrcd[0x18];
2148
2149         u8         reserved_at_4e0[0x8];
2150         u8         cqn_rcv[0x18];
2151
2152         u8         dbr_addr[0x40];
2153
2154         u8         q_key[0x20];
2155
2156         u8         reserved_at_560[0x5];
2157         u8         rq_type[0x3];
2158         u8         srqn_rmpn_xrqn[0x18];
2159
2160         u8         reserved_at_580[0x8];
2161         u8         rmsn[0x18];
2162
2163         u8         hw_sq_wqebb_counter[0x10];
2164         u8         sw_sq_wqebb_counter[0x10];
2165
2166         u8         hw_rq_counter[0x20];
2167
2168         u8         sw_rq_counter[0x20];
2169
2170         u8         reserved_at_600[0x20];
2171
2172         u8         reserved_at_620[0xf];
2173         u8         cgs[0x1];
2174         u8         cs_req[0x8];
2175         u8         cs_res[0x8];
2176
2177         u8         dc_access_key[0x40];
2178
2179         u8         reserved_at_680[0xc0];
2180 };
2181
2182 struct mlx5_ifc_roce_addr_layout_bits {
2183         u8         source_l3_address[16][0x8];
2184
2185         u8         reserved_at_80[0x3];
2186         u8         vlan_valid[0x1];
2187         u8         vlan_id[0xc];
2188         u8         source_mac_47_32[0x10];
2189
2190         u8         source_mac_31_0[0x20];
2191
2192         u8         reserved_at_c0[0x14];
2193         u8         roce_l3_type[0x4];
2194         u8         roce_version[0x8];
2195
2196         u8         reserved_at_e0[0x20];
2197 };
2198
2199 union mlx5_ifc_hca_cap_union_bits {
2200         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2201         struct mlx5_ifc_odp_cap_bits odp_cap;
2202         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2203         struct mlx5_ifc_roce_cap_bits roce_cap;
2204         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2205         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2206         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2207         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2208         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2209         struct mlx5_ifc_qos_cap_bits qos_cap;
2210         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2211         u8         reserved_at_0[0x8000];
2212 };
2213
2214 enum {
2215         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2216         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2217         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2218         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2219         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2220         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2221         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2222 };
2223
2224 struct mlx5_ifc_flow_context_bits {
2225         u8         reserved_at_0[0x20];
2226
2227         u8         group_id[0x20];
2228
2229         u8         reserved_at_40[0x8];
2230         u8         flow_tag[0x18];
2231
2232         u8         reserved_at_60[0x10];
2233         u8         action[0x10];
2234
2235         u8         reserved_at_80[0x8];
2236         u8         destination_list_size[0x18];
2237
2238         u8         reserved_at_a0[0x8];
2239         u8         flow_counter_list_size[0x18];
2240
2241         u8         encap_id[0x20];
2242
2243         u8         modify_header_id[0x20];
2244
2245         u8         reserved_at_100[0x100];
2246
2247         struct mlx5_ifc_fte_match_param_bits match_value;
2248
2249         u8         reserved_at_1200[0x600];
2250
2251         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2252 };
2253
2254 enum {
2255         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2256         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2257 };
2258
2259 struct mlx5_ifc_xrc_srqc_bits {
2260         u8         state[0x4];
2261         u8         log_xrc_srq_size[0x4];
2262         u8         reserved_at_8[0x18];
2263
2264         u8         wq_signature[0x1];
2265         u8         cont_srq[0x1];
2266         u8         reserved_at_22[0x1];
2267         u8         rlky[0x1];
2268         u8         basic_cyclic_rcv_wqe[0x1];
2269         u8         log_rq_stride[0x3];
2270         u8         xrcd[0x18];
2271
2272         u8         page_offset[0x6];
2273         u8         reserved_at_46[0x2];
2274         u8         cqn[0x18];
2275
2276         u8         reserved_at_60[0x20];
2277
2278         u8         user_index_equal_xrc_srqn[0x1];
2279         u8         reserved_at_81[0x1];
2280         u8         log_page_size[0x6];
2281         u8         user_index[0x18];
2282
2283         u8         reserved_at_a0[0x20];
2284
2285         u8         reserved_at_c0[0x8];
2286         u8         pd[0x18];
2287
2288         u8         lwm[0x10];
2289         u8         wqe_cnt[0x10];
2290
2291         u8         reserved_at_100[0x40];
2292
2293         u8         db_record_addr_h[0x20];
2294
2295         u8         db_record_addr_l[0x1e];
2296         u8         reserved_at_17e[0x2];
2297
2298         u8         reserved_at_180[0x80];
2299 };
2300
2301 struct mlx5_ifc_traffic_counter_bits {
2302         u8         packets[0x40];
2303
2304         u8         octets[0x40];
2305 };
2306
2307 struct mlx5_ifc_tisc_bits {
2308         u8         strict_lag_tx_port_affinity[0x1];
2309         u8         reserved_at_1[0x3];
2310         u8         lag_tx_port_affinity[0x04];
2311
2312         u8         reserved_at_8[0x4];
2313         u8         prio[0x4];
2314         u8         reserved_at_10[0x10];
2315
2316         u8         reserved_at_20[0x100];
2317
2318         u8         reserved_at_120[0x8];
2319         u8         transport_domain[0x18];
2320
2321         u8         reserved_at_140[0x8];
2322         u8         underlay_qpn[0x18];
2323         u8         reserved_at_160[0x3a0];
2324 };
2325
2326 enum {
2327         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2328         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2329 };
2330
2331 enum {
2332         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2333         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2334 };
2335
2336 enum {
2337         MLX5_RX_HASH_FN_NONE           = 0x0,
2338         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2339         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2340 };
2341
2342 enum {
2343         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2344         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2345 };
2346
2347 struct mlx5_ifc_tirc_bits {
2348         u8         reserved_at_0[0x20];
2349
2350         u8         disp_type[0x4];
2351         u8         reserved_at_24[0x1c];
2352
2353         u8         reserved_at_40[0x40];
2354
2355         u8         reserved_at_80[0x4];
2356         u8         lro_timeout_period_usecs[0x10];
2357         u8         lro_enable_mask[0x4];
2358         u8         lro_max_ip_payload_size[0x8];
2359
2360         u8         reserved_at_a0[0x40];
2361
2362         u8         reserved_at_e0[0x8];
2363         u8         inline_rqn[0x18];
2364
2365         u8         rx_hash_symmetric[0x1];
2366         u8         reserved_at_101[0x1];
2367         u8         tunneled_offload_en[0x1];
2368         u8         reserved_at_103[0x5];
2369         u8         indirect_table[0x18];
2370
2371         u8         rx_hash_fn[0x4];
2372         u8         reserved_at_124[0x2];
2373         u8         self_lb_block[0x2];
2374         u8         transport_domain[0x18];
2375
2376         u8         rx_hash_toeplitz_key[10][0x20];
2377
2378         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2379
2380         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2381
2382         u8         reserved_at_2c0[0x4c0];
2383 };
2384
2385 enum {
2386         MLX5_SRQC_STATE_GOOD   = 0x0,
2387         MLX5_SRQC_STATE_ERROR  = 0x1,
2388 };
2389
2390 struct mlx5_ifc_srqc_bits {
2391         u8         state[0x4];
2392         u8         log_srq_size[0x4];
2393         u8         reserved_at_8[0x18];
2394
2395         u8         wq_signature[0x1];
2396         u8         cont_srq[0x1];
2397         u8         reserved_at_22[0x1];
2398         u8         rlky[0x1];
2399         u8         reserved_at_24[0x1];
2400         u8         log_rq_stride[0x3];
2401         u8         xrcd[0x18];
2402
2403         u8         page_offset[0x6];
2404         u8         reserved_at_46[0x2];
2405         u8         cqn[0x18];
2406
2407         u8         reserved_at_60[0x20];
2408
2409         u8         reserved_at_80[0x2];
2410         u8         log_page_size[0x6];
2411         u8         reserved_at_88[0x18];
2412
2413         u8         reserved_at_a0[0x20];
2414
2415         u8         reserved_at_c0[0x8];
2416         u8         pd[0x18];
2417
2418         u8         lwm[0x10];
2419         u8         wqe_cnt[0x10];
2420
2421         u8         reserved_at_100[0x40];
2422
2423         u8         dbr_addr[0x40];
2424
2425         u8         reserved_at_180[0x80];
2426 };
2427
2428 enum {
2429         MLX5_SQC_STATE_RST  = 0x0,
2430         MLX5_SQC_STATE_RDY  = 0x1,
2431         MLX5_SQC_STATE_ERR  = 0x3,
2432 };
2433
2434 struct mlx5_ifc_sqc_bits {
2435         u8         rlky[0x1];
2436         u8         cd_master[0x1];
2437         u8         fre[0x1];
2438         u8         flush_in_error_en[0x1];
2439         u8         reserved_at_4[0x1];
2440         u8         min_wqe_inline_mode[0x3];
2441         u8         state[0x4];
2442         u8         reg_umr[0x1];
2443         u8         allow_swp[0x1];
2444         u8         reserved_at_e[0x12];
2445
2446         u8         reserved_at_20[0x8];
2447         u8         user_index[0x18];
2448
2449         u8         reserved_at_40[0x8];
2450         u8         cqn[0x18];
2451
2452         u8         reserved_at_60[0x90];
2453
2454         u8         packet_pacing_rate_limit_index[0x10];
2455         u8         tis_lst_sz[0x10];
2456         u8         reserved_at_110[0x10];
2457
2458         u8         reserved_at_120[0x40];
2459
2460         u8         reserved_at_160[0x8];
2461         u8         tis_num_0[0x18];
2462
2463         struct mlx5_ifc_wq_bits wq;
2464 };
2465
2466 enum {
2467         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2468         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2469         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2470         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2471 };
2472
2473 struct mlx5_ifc_scheduling_context_bits {
2474         u8         element_type[0x8];
2475         u8         reserved_at_8[0x18];
2476
2477         u8         element_attributes[0x20];
2478
2479         u8         parent_element_id[0x20];
2480
2481         u8         reserved_at_60[0x40];
2482
2483         u8         bw_share[0x20];
2484
2485         u8         max_average_bw[0x20];
2486
2487         u8         reserved_at_e0[0x120];
2488 };
2489
2490 struct mlx5_ifc_rqtc_bits {
2491         u8         reserved_at_0[0xa0];
2492
2493         u8         reserved_at_a0[0x10];
2494         u8         rqt_max_size[0x10];
2495
2496         u8         reserved_at_c0[0x10];
2497         u8         rqt_actual_size[0x10];
2498
2499         u8         reserved_at_e0[0x6a0];
2500
2501         struct mlx5_ifc_rq_num_bits rq_num[0];
2502 };
2503
2504 enum {
2505         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2506         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2507 };
2508
2509 enum {
2510         MLX5_RQC_STATE_RST  = 0x0,
2511         MLX5_RQC_STATE_RDY  = 0x1,
2512         MLX5_RQC_STATE_ERR  = 0x3,
2513 };
2514
2515 struct mlx5_ifc_rqc_bits {
2516         u8         rlky[0x1];
2517         u8         reserved_at_1[0x1];
2518         u8         scatter_fcs[0x1];
2519         u8         vsd[0x1];
2520         u8         mem_rq_type[0x4];
2521         u8         state[0x4];
2522         u8         reserved_at_c[0x1];
2523         u8         flush_in_error_en[0x1];
2524         u8         reserved_at_e[0x12];
2525
2526         u8         reserved_at_20[0x8];
2527         u8         user_index[0x18];
2528
2529         u8         reserved_at_40[0x8];
2530         u8         cqn[0x18];
2531
2532         u8         counter_set_id[0x8];
2533         u8         reserved_at_68[0x18];
2534
2535         u8         reserved_at_80[0x8];
2536         u8         rmpn[0x18];
2537
2538         u8         reserved_at_a0[0xe0];
2539
2540         struct mlx5_ifc_wq_bits wq;
2541 };
2542
2543 enum {
2544         MLX5_RMPC_STATE_RDY  = 0x1,
2545         MLX5_RMPC_STATE_ERR  = 0x3,
2546 };
2547
2548 struct mlx5_ifc_rmpc_bits {
2549         u8         reserved_at_0[0x8];
2550         u8         state[0x4];
2551         u8         reserved_at_c[0x14];
2552
2553         u8         basic_cyclic_rcv_wqe[0x1];
2554         u8         reserved_at_21[0x1f];
2555
2556         u8         reserved_at_40[0x140];
2557
2558         struct mlx5_ifc_wq_bits wq;
2559 };
2560
2561 struct mlx5_ifc_nic_vport_context_bits {
2562         u8         reserved_at_0[0x5];
2563         u8         min_wqe_inline_mode[0x3];
2564         u8         reserved_at_8[0x17];
2565         u8         roce_en[0x1];
2566
2567         u8         arm_change_event[0x1];
2568         u8         reserved_at_21[0x1a];
2569         u8         event_on_mtu[0x1];
2570         u8         event_on_promisc_change[0x1];
2571         u8         event_on_vlan_change[0x1];
2572         u8         event_on_mc_address_change[0x1];
2573         u8         event_on_uc_address_change[0x1];
2574
2575         u8         reserved_at_40[0xf0];
2576
2577         u8         mtu[0x10];
2578
2579         u8         system_image_guid[0x40];
2580         u8         port_guid[0x40];
2581         u8         node_guid[0x40];
2582
2583         u8         reserved_at_200[0x140];
2584         u8         qkey_violation_counter[0x10];
2585         u8         reserved_at_350[0x430];
2586
2587         u8         promisc_uc[0x1];
2588         u8         promisc_mc[0x1];
2589         u8         promisc_all[0x1];
2590         u8         reserved_at_783[0x2];
2591         u8         allowed_list_type[0x3];
2592         u8         reserved_at_788[0xc];
2593         u8         allowed_list_size[0xc];
2594
2595         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2596
2597         u8         reserved_at_7e0[0x20];
2598
2599         u8         current_uc_mac_address[0][0x40];
2600 };
2601
2602 enum {
2603         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2604         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2605         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2606         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2607 };
2608
2609 struct mlx5_ifc_mkc_bits {
2610         u8         reserved_at_0[0x1];
2611         u8         free[0x1];
2612         u8         reserved_at_2[0xd];
2613         u8         small_fence_on_rdma_read_response[0x1];
2614         u8         umr_en[0x1];
2615         u8         a[0x1];
2616         u8         rw[0x1];
2617         u8         rr[0x1];
2618         u8         lw[0x1];
2619         u8         lr[0x1];
2620         u8         access_mode[0x2];
2621         u8         reserved_at_18[0x8];
2622
2623         u8         qpn[0x18];
2624         u8         mkey_7_0[0x8];
2625
2626         u8         reserved_at_40[0x20];
2627
2628         u8         length64[0x1];
2629         u8         bsf_en[0x1];
2630         u8         sync_umr[0x1];
2631         u8         reserved_at_63[0x2];
2632         u8         expected_sigerr_count[0x1];
2633         u8         reserved_at_66[0x1];
2634         u8         en_rinval[0x1];
2635         u8         pd[0x18];
2636
2637         u8         start_addr[0x40];
2638
2639         u8         len[0x40];
2640
2641         u8         bsf_octword_size[0x20];
2642
2643         u8         reserved_at_120[0x80];
2644
2645         u8         translations_octword_size[0x20];
2646
2647         u8         reserved_at_1c0[0x1b];
2648         u8         log_page_size[0x5];
2649
2650         u8         reserved_at_1e0[0x20];
2651 };
2652
2653 struct mlx5_ifc_pkey_bits {
2654         u8         reserved_at_0[0x10];
2655         u8         pkey[0x10];
2656 };
2657
2658 struct mlx5_ifc_array128_auto_bits {
2659         u8         array128_auto[16][0x8];
2660 };
2661
2662 struct mlx5_ifc_hca_vport_context_bits {
2663         u8         field_select[0x20];
2664
2665         u8         reserved_at_20[0xe0];
2666
2667         u8         sm_virt_aware[0x1];
2668         u8         has_smi[0x1];
2669         u8         has_raw[0x1];
2670         u8         grh_required[0x1];
2671         u8         reserved_at_104[0xc];
2672         u8         port_physical_state[0x4];
2673         u8         vport_state_policy[0x4];
2674         u8         port_state[0x4];
2675         u8         vport_state[0x4];
2676
2677         u8         reserved_at_120[0x20];
2678
2679         u8         system_image_guid[0x40];
2680
2681         u8         port_guid[0x40];
2682
2683         u8         node_guid[0x40];
2684
2685         u8         cap_mask1[0x20];
2686
2687         u8         cap_mask1_field_select[0x20];
2688
2689         u8         cap_mask2[0x20];
2690
2691         u8         cap_mask2_field_select[0x20];
2692
2693         u8         reserved_at_280[0x80];
2694
2695         u8         lid[0x10];
2696         u8         reserved_at_310[0x4];
2697         u8         init_type_reply[0x4];
2698         u8         lmc[0x3];
2699         u8         subnet_timeout[0x5];
2700
2701         u8         sm_lid[0x10];
2702         u8         sm_sl[0x4];
2703         u8         reserved_at_334[0xc];
2704
2705         u8         qkey_violation_counter[0x10];
2706         u8         pkey_violation_counter[0x10];
2707
2708         u8         reserved_at_360[0xca0];
2709 };
2710
2711 struct mlx5_ifc_esw_vport_context_bits {
2712         u8         reserved_at_0[0x3];
2713         u8         vport_svlan_strip[0x1];
2714         u8         vport_cvlan_strip[0x1];
2715         u8         vport_svlan_insert[0x1];
2716         u8         vport_cvlan_insert[0x2];
2717         u8         reserved_at_8[0x18];
2718
2719         u8         reserved_at_20[0x20];
2720
2721         u8         svlan_cfi[0x1];
2722         u8         svlan_pcp[0x3];
2723         u8         svlan_id[0xc];
2724         u8         cvlan_cfi[0x1];
2725         u8         cvlan_pcp[0x3];
2726         u8         cvlan_id[0xc];
2727
2728         u8         reserved_at_60[0x7a0];
2729 };
2730
2731 enum {
2732         MLX5_EQC_STATUS_OK                = 0x0,
2733         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2734 };
2735
2736 enum {
2737         MLX5_EQC_ST_ARMED  = 0x9,
2738         MLX5_EQC_ST_FIRED  = 0xa,
2739 };
2740
2741 struct mlx5_ifc_eqc_bits {
2742         u8         status[0x4];
2743         u8         reserved_at_4[0x9];
2744         u8         ec[0x1];
2745         u8         oi[0x1];
2746         u8         reserved_at_f[0x5];
2747         u8         st[0x4];
2748         u8         reserved_at_18[0x8];
2749
2750         u8         reserved_at_20[0x20];
2751
2752         u8         reserved_at_40[0x14];
2753         u8         page_offset[0x6];
2754         u8         reserved_at_5a[0x6];
2755
2756         u8         reserved_at_60[0x3];
2757         u8         log_eq_size[0x5];
2758         u8         uar_page[0x18];
2759
2760         u8         reserved_at_80[0x20];
2761
2762         u8         reserved_at_a0[0x18];
2763         u8         intr[0x8];
2764
2765         u8         reserved_at_c0[0x3];
2766         u8         log_page_size[0x5];
2767         u8         reserved_at_c8[0x18];
2768
2769         u8         reserved_at_e0[0x60];
2770
2771         u8         reserved_at_140[0x8];
2772         u8         consumer_counter[0x18];
2773
2774         u8         reserved_at_160[0x8];
2775         u8         producer_counter[0x18];
2776
2777         u8         reserved_at_180[0x80];
2778 };
2779
2780 enum {
2781         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2782         MLX5_DCTC_STATE_DRAINING  = 0x1,
2783         MLX5_DCTC_STATE_DRAINED   = 0x2,
2784 };
2785
2786 enum {
2787         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2788         MLX5_DCTC_CS_RES_NA         = 0x1,
2789         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2790 };
2791
2792 enum {
2793         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2794         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2795         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2796         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2797         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2798 };
2799
2800 struct mlx5_ifc_dctc_bits {
2801         u8         reserved_at_0[0x4];
2802         u8         state[0x4];
2803         u8         reserved_at_8[0x18];
2804
2805         u8         reserved_at_20[0x8];
2806         u8         user_index[0x18];
2807
2808         u8         reserved_at_40[0x8];
2809         u8         cqn[0x18];
2810
2811         u8         counter_set_id[0x8];
2812         u8         atomic_mode[0x4];
2813         u8         rre[0x1];
2814         u8         rwe[0x1];
2815         u8         rae[0x1];
2816         u8         atomic_like_write_en[0x1];
2817         u8         latency_sensitive[0x1];
2818         u8         rlky[0x1];
2819         u8         free_ar[0x1];
2820         u8         reserved_at_73[0xd];
2821
2822         u8         reserved_at_80[0x8];
2823         u8         cs_res[0x8];
2824         u8         reserved_at_90[0x3];
2825         u8         min_rnr_nak[0x5];
2826         u8         reserved_at_98[0x8];
2827
2828         u8         reserved_at_a0[0x8];
2829         u8         srqn_xrqn[0x18];
2830
2831         u8         reserved_at_c0[0x8];
2832         u8         pd[0x18];
2833
2834         u8         tclass[0x8];
2835         u8         reserved_at_e8[0x4];
2836         u8         flow_label[0x14];
2837
2838         u8         dc_access_key[0x40];
2839
2840         u8         reserved_at_140[0x5];
2841         u8         mtu[0x3];
2842         u8         port[0x8];
2843         u8         pkey_index[0x10];
2844
2845         u8         reserved_at_160[0x8];
2846         u8         my_addr_index[0x8];
2847         u8         reserved_at_170[0x8];
2848         u8         hop_limit[0x8];
2849
2850         u8         dc_access_key_violation_count[0x20];
2851
2852         u8         reserved_at_1a0[0x14];
2853         u8         dei_cfi[0x1];
2854         u8         eth_prio[0x3];
2855         u8         ecn[0x2];
2856         u8         dscp[0x6];
2857
2858         u8         reserved_at_1c0[0x40];
2859 };
2860
2861 enum {
2862         MLX5_CQC_STATUS_OK             = 0x0,
2863         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2864         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2865 };
2866
2867 enum {
2868         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2869         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2870 };
2871
2872 enum {
2873         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2874         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2875         MLX5_CQC_ST_FIRED                                 = 0xa,
2876 };
2877
2878 enum {
2879         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2880         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2881         MLX5_CQ_PERIOD_NUM_MODES
2882 };
2883
2884 struct mlx5_ifc_cqc_bits {
2885         u8         status[0x4];
2886         u8         reserved_at_4[0x4];
2887         u8         cqe_sz[0x3];
2888         u8         cc[0x1];
2889         u8         reserved_at_c[0x1];
2890         u8         scqe_break_moderation_en[0x1];
2891         u8         oi[0x1];
2892         u8         cq_period_mode[0x2];
2893         u8         cqe_comp_en[0x1];
2894         u8         mini_cqe_res_format[0x2];
2895         u8         st[0x4];
2896         u8         reserved_at_18[0x8];
2897
2898         u8         reserved_at_20[0x20];
2899
2900         u8         reserved_at_40[0x14];
2901         u8         page_offset[0x6];
2902         u8         reserved_at_5a[0x6];
2903
2904         u8         reserved_at_60[0x3];
2905         u8         log_cq_size[0x5];
2906         u8         uar_page[0x18];
2907
2908         u8         reserved_at_80[0x4];
2909         u8         cq_period[0xc];
2910         u8         cq_max_count[0x10];
2911
2912         u8         reserved_at_a0[0x18];
2913         u8         c_eqn[0x8];
2914
2915         u8         reserved_at_c0[0x3];
2916         u8         log_page_size[0x5];
2917         u8         reserved_at_c8[0x18];
2918
2919         u8         reserved_at_e0[0x20];
2920
2921         u8         reserved_at_100[0x8];
2922         u8         last_notified_index[0x18];
2923
2924         u8         reserved_at_120[0x8];
2925         u8         last_solicit_index[0x18];
2926
2927         u8         reserved_at_140[0x8];
2928         u8         consumer_counter[0x18];
2929
2930         u8         reserved_at_160[0x8];
2931         u8         producer_counter[0x18];
2932
2933         u8         reserved_at_180[0x40];
2934
2935         u8         dbr_addr[0x40];
2936 };
2937
2938 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2939         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2940         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2941         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2942         u8         reserved_at_0[0x800];
2943 };
2944
2945 struct mlx5_ifc_query_adapter_param_block_bits {
2946         u8         reserved_at_0[0xc0];
2947
2948         u8         reserved_at_c0[0x8];
2949         u8         ieee_vendor_id[0x18];
2950
2951         u8         reserved_at_e0[0x10];
2952         u8         vsd_vendor_id[0x10];
2953
2954         u8         vsd[208][0x8];
2955
2956         u8         vsd_contd_psid[16][0x8];
2957 };
2958
2959 enum {
2960         MLX5_XRQC_STATE_GOOD   = 0x0,
2961         MLX5_XRQC_STATE_ERROR  = 0x1,
2962 };
2963
2964 enum {
2965         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2966         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2967 };
2968
2969 enum {
2970         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2971 };
2972
2973 struct mlx5_ifc_tag_matching_topology_context_bits {
2974         u8         log_matching_list_sz[0x4];
2975         u8         reserved_at_4[0xc];
2976         u8         append_next_index[0x10];
2977
2978         u8         sw_phase_cnt[0x10];
2979         u8         hw_phase_cnt[0x10];
2980
2981         u8         reserved_at_40[0x40];
2982 };
2983
2984 struct mlx5_ifc_xrqc_bits {
2985         u8         state[0x4];
2986         u8         rlkey[0x1];
2987         u8         reserved_at_5[0xf];
2988         u8         topology[0x4];
2989         u8         reserved_at_18[0x4];
2990         u8         offload[0x4];
2991
2992         u8         reserved_at_20[0x8];
2993         u8         user_index[0x18];
2994
2995         u8         reserved_at_40[0x8];
2996         u8         cqn[0x18];
2997
2998         u8         reserved_at_60[0xa0];
2999
3000         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3001
3002         u8         reserved_at_180[0x880];
3003
3004         struct mlx5_ifc_wq_bits wq;
3005 };
3006
3007 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3008         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3009         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3010         u8         reserved_at_0[0x20];
3011 };
3012
3013 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3014         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3015         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3016         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3017         u8         reserved_at_0[0x20];
3018 };
3019
3020 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3021         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3022         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3023         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3024         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3025         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3026         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3027         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3028         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3029         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3030         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3031         u8         reserved_at_0[0x7c0];
3032 };
3033
3034 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3035         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3036         u8         reserved_at_0[0x7c0];
3037 };
3038
3039 union mlx5_ifc_event_auto_bits {
3040         struct mlx5_ifc_comp_event_bits comp_event;
3041         struct mlx5_ifc_dct_events_bits dct_events;
3042         struct mlx5_ifc_qp_events_bits qp_events;
3043         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3044         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3045         struct mlx5_ifc_cq_error_bits cq_error;
3046         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3047         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3048         struct mlx5_ifc_gpio_event_bits gpio_event;
3049         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3050         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3051         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3052         u8         reserved_at_0[0xe0];
3053 };
3054
3055 struct mlx5_ifc_health_buffer_bits {
3056         u8         reserved_at_0[0x100];
3057
3058         u8         assert_existptr[0x20];
3059
3060         u8         assert_callra[0x20];
3061
3062         u8         reserved_at_140[0x40];
3063
3064         u8         fw_version[0x20];
3065
3066         u8         hw_id[0x20];
3067
3068         u8         reserved_at_1c0[0x20];
3069
3070         u8         irisc_index[0x8];
3071         u8         synd[0x8];
3072         u8         ext_synd[0x10];
3073 };
3074
3075 struct mlx5_ifc_register_loopback_control_bits {
3076         u8         no_lb[0x1];
3077         u8         reserved_at_1[0x7];
3078         u8         port[0x8];
3079         u8         reserved_at_10[0x10];
3080
3081         u8         reserved_at_20[0x60];
3082 };
3083
3084 struct mlx5_ifc_vport_tc_element_bits {
3085         u8         traffic_class[0x4];
3086         u8         reserved_at_4[0xc];
3087         u8         vport_number[0x10];
3088 };
3089
3090 struct mlx5_ifc_vport_element_bits {
3091         u8         reserved_at_0[0x10];
3092         u8         vport_number[0x10];
3093 };
3094
3095 enum {
3096         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3097         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3098         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3099 };
3100
3101 struct mlx5_ifc_tsar_element_bits {
3102         u8         reserved_at_0[0x8];
3103         u8         tsar_type[0x8];
3104         u8         reserved_at_10[0x10];
3105 };
3106
3107 enum {
3108         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3109         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3110 };
3111
3112 struct mlx5_ifc_teardown_hca_out_bits {
3113         u8         status[0x8];
3114         u8         reserved_at_8[0x18];
3115
3116         u8         syndrome[0x20];
3117
3118         u8         reserved_at_40[0x3f];
3119
3120         u8         force_state[0x1];
3121 };
3122
3123 enum {
3124         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3125         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3126 };
3127
3128 struct mlx5_ifc_teardown_hca_in_bits {
3129         u8         opcode[0x10];
3130         u8         reserved_at_10[0x10];
3131
3132         u8         reserved_at_20[0x10];
3133         u8         op_mod[0x10];
3134
3135         u8         reserved_at_40[0x10];
3136         u8         profile[0x10];
3137
3138         u8         reserved_at_60[0x20];
3139 };
3140
3141 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3142         u8         status[0x8];
3143         u8         reserved_at_8[0x18];
3144
3145         u8         syndrome[0x20];
3146
3147         u8         reserved_at_40[0x40];
3148 };
3149
3150 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3151         u8         opcode[0x10];
3152         u8         reserved_at_10[0x10];
3153
3154         u8         reserved_at_20[0x10];
3155         u8         op_mod[0x10];
3156
3157         u8         reserved_at_40[0x8];
3158         u8         qpn[0x18];
3159
3160         u8         reserved_at_60[0x20];
3161
3162         u8         opt_param_mask[0x20];
3163
3164         u8         reserved_at_a0[0x20];
3165
3166         struct mlx5_ifc_qpc_bits qpc;
3167
3168         u8         reserved_at_800[0x80];
3169 };
3170
3171 struct mlx5_ifc_sqd2rts_qp_out_bits {
3172         u8         status[0x8];
3173         u8         reserved_at_8[0x18];
3174
3175         u8         syndrome[0x20];
3176
3177         u8         reserved_at_40[0x40];
3178 };
3179
3180 struct mlx5_ifc_sqd2rts_qp_in_bits {
3181         u8         opcode[0x10];
3182         u8         reserved_at_10[0x10];
3183
3184         u8         reserved_at_20[0x10];
3185         u8         op_mod[0x10];
3186
3187         u8         reserved_at_40[0x8];
3188         u8         qpn[0x18];
3189
3190         u8         reserved_at_60[0x20];
3191
3192         u8         opt_param_mask[0x20];
3193
3194         u8         reserved_at_a0[0x20];
3195
3196         struct mlx5_ifc_qpc_bits qpc;
3197
3198         u8         reserved_at_800[0x80];
3199 };
3200
3201 struct mlx5_ifc_set_roce_address_out_bits {
3202         u8         status[0x8];
3203         u8         reserved_at_8[0x18];
3204
3205         u8         syndrome[0x20];
3206
3207         u8         reserved_at_40[0x40];
3208 };
3209
3210 struct mlx5_ifc_set_roce_address_in_bits {
3211         u8         opcode[0x10];
3212         u8         reserved_at_10[0x10];
3213
3214         u8         reserved_at_20[0x10];
3215         u8         op_mod[0x10];
3216
3217         u8         roce_address_index[0x10];
3218         u8         reserved_at_50[0x10];
3219
3220         u8         reserved_at_60[0x20];
3221
3222         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3223 };
3224
3225 struct mlx5_ifc_set_mad_demux_out_bits {
3226         u8         status[0x8];
3227         u8         reserved_at_8[0x18];
3228
3229         u8         syndrome[0x20];
3230
3231         u8         reserved_at_40[0x40];
3232 };
3233
3234 enum {
3235         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3236         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3237 };
3238
3239 struct mlx5_ifc_set_mad_demux_in_bits {
3240         u8         opcode[0x10];
3241         u8         reserved_at_10[0x10];
3242
3243         u8         reserved_at_20[0x10];
3244         u8         op_mod[0x10];
3245
3246         u8         reserved_at_40[0x20];
3247
3248         u8         reserved_at_60[0x6];
3249         u8         demux_mode[0x2];
3250         u8         reserved_at_68[0x18];
3251 };
3252
3253 struct mlx5_ifc_set_l2_table_entry_out_bits {
3254         u8         status[0x8];
3255         u8         reserved_at_8[0x18];
3256
3257         u8         syndrome[0x20];
3258
3259         u8         reserved_at_40[0x40];
3260 };
3261
3262 struct mlx5_ifc_set_l2_table_entry_in_bits {
3263         u8         opcode[0x10];
3264         u8         reserved_at_10[0x10];
3265
3266         u8         reserved_at_20[0x10];
3267         u8         op_mod[0x10];
3268
3269         u8         reserved_at_40[0x60];
3270
3271         u8         reserved_at_a0[0x8];
3272         u8         table_index[0x18];
3273
3274         u8         reserved_at_c0[0x20];
3275
3276         u8         reserved_at_e0[0x13];
3277         u8         vlan_valid[0x1];
3278         u8         vlan[0xc];
3279
3280         struct mlx5_ifc_mac_address_layout_bits mac_address;
3281
3282         u8         reserved_at_140[0xc0];
3283 };
3284
3285 struct mlx5_ifc_set_issi_out_bits {
3286         u8         status[0x8];
3287         u8         reserved_at_8[0x18];
3288
3289         u8         syndrome[0x20];
3290
3291         u8         reserved_at_40[0x40];
3292 };
3293
3294 struct mlx5_ifc_set_issi_in_bits {
3295         u8         opcode[0x10];
3296         u8         reserved_at_10[0x10];
3297
3298         u8         reserved_at_20[0x10];
3299         u8         op_mod[0x10];
3300
3301         u8         reserved_at_40[0x10];
3302         u8         current_issi[0x10];
3303
3304         u8         reserved_at_60[0x20];
3305 };
3306
3307 struct mlx5_ifc_set_hca_cap_out_bits {
3308         u8         status[0x8];
3309         u8         reserved_at_8[0x18];
3310
3311         u8         syndrome[0x20];
3312
3313         u8         reserved_at_40[0x40];
3314 };
3315
3316 struct mlx5_ifc_set_hca_cap_in_bits {
3317         u8         opcode[0x10];
3318         u8         reserved_at_10[0x10];
3319
3320         u8         reserved_at_20[0x10];
3321         u8         op_mod[0x10];
3322
3323         u8         reserved_at_40[0x40];
3324
3325         union mlx5_ifc_hca_cap_union_bits capability;
3326 };
3327
3328 enum {
3329         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3330         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3331         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3332         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3333 };
3334
3335 struct mlx5_ifc_set_fte_out_bits {
3336         u8         status[0x8];
3337         u8         reserved_at_8[0x18];
3338
3339         u8         syndrome[0x20];
3340
3341         u8         reserved_at_40[0x40];
3342 };
3343
3344 struct mlx5_ifc_set_fte_in_bits {
3345         u8         opcode[0x10];
3346         u8         reserved_at_10[0x10];
3347
3348         u8         reserved_at_20[0x10];
3349         u8         op_mod[0x10];
3350
3351         u8         other_vport[0x1];
3352         u8         reserved_at_41[0xf];
3353         u8         vport_number[0x10];
3354
3355         u8         reserved_at_60[0x20];
3356
3357         u8         table_type[0x8];
3358         u8         reserved_at_88[0x18];
3359
3360         u8         reserved_at_a0[0x8];
3361         u8         table_id[0x18];
3362
3363         u8         reserved_at_c0[0x18];
3364         u8         modify_enable_mask[0x8];
3365
3366         u8         reserved_at_e0[0x20];
3367
3368         u8         flow_index[0x20];
3369
3370         u8         reserved_at_120[0xe0];
3371
3372         struct mlx5_ifc_flow_context_bits flow_context;
3373 };
3374
3375 struct mlx5_ifc_rts2rts_qp_out_bits {
3376         u8         status[0x8];
3377         u8         reserved_at_8[0x18];
3378
3379         u8         syndrome[0x20];
3380
3381         u8         reserved_at_40[0x40];
3382 };
3383
3384 struct mlx5_ifc_rts2rts_qp_in_bits {
3385         u8         opcode[0x10];
3386         u8         reserved_at_10[0x10];
3387
3388         u8         reserved_at_20[0x10];
3389         u8         op_mod[0x10];
3390
3391         u8         reserved_at_40[0x8];
3392         u8         qpn[0x18];
3393
3394         u8         reserved_at_60[0x20];
3395
3396         u8         opt_param_mask[0x20];
3397
3398         u8         reserved_at_a0[0x20];
3399
3400         struct mlx5_ifc_qpc_bits qpc;
3401
3402         u8         reserved_at_800[0x80];
3403 };
3404
3405 struct mlx5_ifc_rtr2rts_qp_out_bits {
3406         u8         status[0x8];
3407         u8         reserved_at_8[0x18];
3408
3409         u8         syndrome[0x20];
3410
3411         u8         reserved_at_40[0x40];
3412 };
3413
3414 struct mlx5_ifc_rtr2rts_qp_in_bits {
3415         u8         opcode[0x10];
3416         u8         reserved_at_10[0x10];
3417
3418         u8         reserved_at_20[0x10];
3419         u8         op_mod[0x10];
3420
3421         u8         reserved_at_40[0x8];
3422         u8         qpn[0x18];
3423
3424         u8         reserved_at_60[0x20];
3425
3426         u8         opt_param_mask[0x20];
3427
3428         u8         reserved_at_a0[0x20];
3429
3430         struct mlx5_ifc_qpc_bits qpc;
3431
3432         u8         reserved_at_800[0x80];
3433 };
3434
3435 struct mlx5_ifc_rst2init_qp_out_bits {
3436         u8         status[0x8];
3437         u8         reserved_at_8[0x18];
3438
3439         u8         syndrome[0x20];
3440
3441         u8         reserved_at_40[0x40];
3442 };
3443
3444 struct mlx5_ifc_rst2init_qp_in_bits {
3445         u8         opcode[0x10];
3446         u8         reserved_at_10[0x10];
3447
3448         u8         reserved_at_20[0x10];
3449         u8         op_mod[0x10];
3450
3451         u8         reserved_at_40[0x8];
3452         u8         qpn[0x18];
3453
3454         u8         reserved_at_60[0x20];
3455
3456         u8         opt_param_mask[0x20];
3457
3458         u8         reserved_at_a0[0x20];
3459
3460         struct mlx5_ifc_qpc_bits qpc;
3461
3462         u8         reserved_at_800[0x80];
3463 };
3464
3465 struct mlx5_ifc_query_xrq_out_bits {
3466         u8         status[0x8];
3467         u8         reserved_at_8[0x18];
3468
3469         u8         syndrome[0x20];
3470
3471         u8         reserved_at_40[0x40];
3472
3473         struct mlx5_ifc_xrqc_bits xrq_context;
3474 };
3475
3476 struct mlx5_ifc_query_xrq_in_bits {
3477         u8         opcode[0x10];
3478         u8         reserved_at_10[0x10];
3479
3480         u8         reserved_at_20[0x10];
3481         u8         op_mod[0x10];
3482
3483         u8         reserved_at_40[0x8];
3484         u8         xrqn[0x18];
3485
3486         u8         reserved_at_60[0x20];
3487 };
3488
3489 struct mlx5_ifc_query_xrc_srq_out_bits {
3490         u8         status[0x8];
3491         u8         reserved_at_8[0x18];
3492
3493         u8         syndrome[0x20];
3494
3495         u8         reserved_at_40[0x40];
3496
3497         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3498
3499         u8         reserved_at_280[0x600];
3500
3501         u8         pas[0][0x40];
3502 };
3503
3504 struct mlx5_ifc_query_xrc_srq_in_bits {
3505         u8         opcode[0x10];
3506         u8         reserved_at_10[0x10];
3507
3508         u8         reserved_at_20[0x10];
3509         u8         op_mod[0x10];
3510
3511         u8         reserved_at_40[0x8];
3512         u8         xrc_srqn[0x18];
3513
3514         u8         reserved_at_60[0x20];
3515 };
3516
3517 enum {
3518         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3519         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3520 };
3521
3522 struct mlx5_ifc_query_vport_state_out_bits {
3523         u8         status[0x8];
3524         u8         reserved_at_8[0x18];
3525
3526         u8         syndrome[0x20];
3527
3528         u8         reserved_at_40[0x20];
3529
3530         u8         reserved_at_60[0x18];
3531         u8         admin_state[0x4];
3532         u8         state[0x4];
3533 };
3534
3535 enum {
3536         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3537         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3538 };
3539
3540 struct mlx5_ifc_query_vport_state_in_bits {
3541         u8         opcode[0x10];
3542         u8         reserved_at_10[0x10];
3543
3544         u8         reserved_at_20[0x10];
3545         u8         op_mod[0x10];
3546
3547         u8         other_vport[0x1];
3548         u8         reserved_at_41[0xf];
3549         u8         vport_number[0x10];
3550
3551         u8         reserved_at_60[0x20];
3552 };
3553
3554 struct mlx5_ifc_query_vport_counter_out_bits {
3555         u8         status[0x8];
3556         u8         reserved_at_8[0x18];
3557
3558         u8         syndrome[0x20];
3559
3560         u8         reserved_at_40[0x40];
3561
3562         struct mlx5_ifc_traffic_counter_bits received_errors;
3563
3564         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3565
3566         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3567
3568         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3569
3570         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3571
3572         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3573
3574         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3575
3576         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3577
3578         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3579
3580         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3581
3582         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3583
3584         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3585
3586         u8         reserved_at_680[0xa00];
3587 };
3588
3589 enum {
3590         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3591 };
3592
3593 struct mlx5_ifc_query_vport_counter_in_bits {
3594         u8         opcode[0x10];
3595         u8         reserved_at_10[0x10];
3596
3597         u8         reserved_at_20[0x10];
3598         u8         op_mod[0x10];
3599
3600         u8         other_vport[0x1];
3601         u8         reserved_at_41[0xb];
3602         u8         port_num[0x4];
3603         u8         vport_number[0x10];
3604
3605         u8         reserved_at_60[0x60];
3606
3607         u8         clear[0x1];
3608         u8         reserved_at_c1[0x1f];
3609
3610         u8         reserved_at_e0[0x20];
3611 };
3612
3613 struct mlx5_ifc_query_tis_out_bits {
3614         u8         status[0x8];
3615         u8         reserved_at_8[0x18];
3616
3617         u8         syndrome[0x20];
3618
3619         u8         reserved_at_40[0x40];
3620
3621         struct mlx5_ifc_tisc_bits tis_context;
3622 };
3623
3624 struct mlx5_ifc_query_tis_in_bits {
3625         u8         opcode[0x10];
3626         u8         reserved_at_10[0x10];
3627
3628         u8         reserved_at_20[0x10];
3629         u8         op_mod[0x10];
3630
3631         u8         reserved_at_40[0x8];
3632         u8         tisn[0x18];
3633
3634         u8         reserved_at_60[0x20];
3635 };
3636
3637 struct mlx5_ifc_query_tir_out_bits {
3638         u8         status[0x8];
3639         u8         reserved_at_8[0x18];
3640
3641         u8         syndrome[0x20];
3642
3643         u8         reserved_at_40[0xc0];
3644
3645         struct mlx5_ifc_tirc_bits tir_context;
3646 };
3647
3648 struct mlx5_ifc_query_tir_in_bits {
3649         u8         opcode[0x10];
3650         u8         reserved_at_10[0x10];
3651
3652         u8         reserved_at_20[0x10];
3653         u8         op_mod[0x10];
3654
3655         u8         reserved_at_40[0x8];
3656         u8         tirn[0x18];
3657
3658         u8         reserved_at_60[0x20];
3659 };
3660
3661 struct mlx5_ifc_query_srq_out_bits {
3662         u8         status[0x8];
3663         u8         reserved_at_8[0x18];
3664
3665         u8         syndrome[0x20];
3666
3667         u8         reserved_at_40[0x40];
3668
3669         struct mlx5_ifc_srqc_bits srq_context_entry;
3670
3671         u8         reserved_at_280[0x600];
3672
3673         u8         pas[0][0x40];
3674 };
3675
3676 struct mlx5_ifc_query_srq_in_bits {
3677         u8         opcode[0x10];
3678         u8         reserved_at_10[0x10];
3679
3680         u8         reserved_at_20[0x10];
3681         u8         op_mod[0x10];
3682
3683         u8         reserved_at_40[0x8];
3684         u8         srqn[0x18];
3685
3686         u8         reserved_at_60[0x20];
3687 };
3688
3689 struct mlx5_ifc_query_sq_out_bits {
3690         u8         status[0x8];
3691         u8         reserved_at_8[0x18];
3692
3693         u8         syndrome[0x20];
3694
3695         u8         reserved_at_40[0xc0];
3696
3697         struct mlx5_ifc_sqc_bits sq_context;
3698 };
3699
3700 struct mlx5_ifc_query_sq_in_bits {
3701         u8         opcode[0x10];
3702         u8         reserved_at_10[0x10];
3703
3704         u8         reserved_at_20[0x10];
3705         u8         op_mod[0x10];
3706
3707         u8         reserved_at_40[0x8];
3708         u8         sqn[0x18];
3709
3710         u8         reserved_at_60[0x20];
3711 };
3712
3713 struct mlx5_ifc_query_special_contexts_out_bits {
3714         u8         status[0x8];
3715         u8         reserved_at_8[0x18];
3716
3717         u8         syndrome[0x20];
3718
3719         u8         dump_fill_mkey[0x20];
3720
3721         u8         resd_lkey[0x20];
3722
3723         u8         null_mkey[0x20];
3724
3725         u8         reserved_at_a0[0x60];
3726 };
3727
3728 struct mlx5_ifc_query_special_contexts_in_bits {
3729         u8         opcode[0x10];
3730         u8         reserved_at_10[0x10];
3731
3732         u8         reserved_at_20[0x10];
3733         u8         op_mod[0x10];
3734
3735         u8         reserved_at_40[0x40];
3736 };
3737
3738 struct mlx5_ifc_query_scheduling_element_out_bits {
3739         u8         opcode[0x10];
3740         u8         reserved_at_10[0x10];
3741
3742         u8         reserved_at_20[0x10];
3743         u8         op_mod[0x10];
3744
3745         u8         reserved_at_40[0xc0];
3746
3747         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3748
3749         u8         reserved_at_300[0x100];
3750 };
3751
3752 enum {
3753         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3754 };
3755
3756 struct mlx5_ifc_query_scheduling_element_in_bits {
3757         u8         opcode[0x10];
3758         u8         reserved_at_10[0x10];
3759
3760         u8         reserved_at_20[0x10];
3761         u8         op_mod[0x10];
3762
3763         u8         scheduling_hierarchy[0x8];
3764         u8         reserved_at_48[0x18];
3765
3766         u8         scheduling_element_id[0x20];
3767
3768         u8         reserved_at_80[0x180];
3769 };
3770
3771 struct mlx5_ifc_query_rqt_out_bits {
3772         u8         status[0x8];
3773         u8         reserved_at_8[0x18];
3774
3775         u8         syndrome[0x20];
3776
3777         u8         reserved_at_40[0xc0];
3778
3779         struct mlx5_ifc_rqtc_bits rqt_context;
3780 };
3781
3782 struct mlx5_ifc_query_rqt_in_bits {
3783         u8         opcode[0x10];
3784         u8         reserved_at_10[0x10];
3785
3786         u8         reserved_at_20[0x10];
3787         u8         op_mod[0x10];
3788
3789         u8         reserved_at_40[0x8];
3790         u8         rqtn[0x18];
3791
3792         u8         reserved_at_60[0x20];
3793 };
3794
3795 struct mlx5_ifc_query_rq_out_bits {
3796         u8         status[0x8];
3797         u8         reserved_at_8[0x18];
3798
3799         u8         syndrome[0x20];
3800
3801         u8         reserved_at_40[0xc0];
3802
3803         struct mlx5_ifc_rqc_bits rq_context;
3804 };
3805
3806 struct mlx5_ifc_query_rq_in_bits {
3807         u8         opcode[0x10];
3808         u8         reserved_at_10[0x10];
3809
3810         u8         reserved_at_20[0x10];
3811         u8         op_mod[0x10];
3812
3813         u8         reserved_at_40[0x8];
3814         u8         rqn[0x18];
3815
3816         u8         reserved_at_60[0x20];
3817 };
3818
3819 struct mlx5_ifc_query_roce_address_out_bits {
3820         u8         status[0x8];
3821         u8         reserved_at_8[0x18];
3822
3823         u8         syndrome[0x20];
3824
3825         u8         reserved_at_40[0x40];
3826
3827         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3828 };
3829
3830 struct mlx5_ifc_query_roce_address_in_bits {
3831         u8         opcode[0x10];
3832         u8         reserved_at_10[0x10];
3833
3834         u8         reserved_at_20[0x10];
3835         u8         op_mod[0x10];
3836
3837         u8         roce_address_index[0x10];
3838         u8         reserved_at_50[0x10];
3839
3840         u8         reserved_at_60[0x20];
3841 };
3842
3843 struct mlx5_ifc_query_rmp_out_bits {
3844         u8         status[0x8];
3845         u8         reserved_at_8[0x18];
3846
3847         u8         syndrome[0x20];
3848
3849         u8         reserved_at_40[0xc0];
3850
3851         struct mlx5_ifc_rmpc_bits rmp_context;
3852 };
3853
3854 struct mlx5_ifc_query_rmp_in_bits {
3855         u8         opcode[0x10];
3856         u8         reserved_at_10[0x10];
3857
3858         u8         reserved_at_20[0x10];
3859         u8         op_mod[0x10];
3860
3861         u8         reserved_at_40[0x8];
3862         u8         rmpn[0x18];
3863
3864         u8         reserved_at_60[0x20];
3865 };
3866
3867 struct mlx5_ifc_query_qp_out_bits {
3868         u8         status[0x8];
3869         u8         reserved_at_8[0x18];
3870
3871         u8         syndrome[0x20];
3872
3873         u8         reserved_at_40[0x40];
3874
3875         u8         opt_param_mask[0x20];
3876
3877         u8         reserved_at_a0[0x20];
3878
3879         struct mlx5_ifc_qpc_bits qpc;
3880
3881         u8         reserved_at_800[0x80];
3882
3883         u8         pas[0][0x40];
3884 };
3885
3886 struct mlx5_ifc_query_qp_in_bits {
3887         u8         opcode[0x10];
3888         u8         reserved_at_10[0x10];
3889
3890         u8         reserved_at_20[0x10];
3891         u8         op_mod[0x10];
3892
3893         u8         reserved_at_40[0x8];
3894         u8         qpn[0x18];
3895
3896         u8         reserved_at_60[0x20];
3897 };
3898
3899 struct mlx5_ifc_query_q_counter_out_bits {
3900         u8         status[0x8];
3901         u8         reserved_at_8[0x18];
3902
3903         u8         syndrome[0x20];
3904
3905         u8         reserved_at_40[0x40];
3906
3907         u8         rx_write_requests[0x20];
3908
3909         u8         reserved_at_a0[0x20];
3910
3911         u8         rx_read_requests[0x20];
3912
3913         u8         reserved_at_e0[0x20];
3914
3915         u8         rx_atomic_requests[0x20];
3916
3917         u8         reserved_at_120[0x20];
3918
3919         u8         rx_dct_connect[0x20];
3920
3921         u8         reserved_at_160[0x20];
3922
3923         u8         out_of_buffer[0x20];
3924
3925         u8         reserved_at_1a0[0x20];
3926
3927         u8         out_of_sequence[0x20];
3928
3929         u8         reserved_at_1e0[0x20];
3930
3931         u8         duplicate_request[0x20];
3932
3933         u8         reserved_at_220[0x20];
3934
3935         u8         rnr_nak_retry_err[0x20];
3936
3937         u8         reserved_at_260[0x20];
3938
3939         u8         packet_seq_err[0x20];
3940
3941         u8         reserved_at_2a0[0x20];
3942
3943         u8         implied_nak_seq_err[0x20];
3944
3945         u8         reserved_at_2e0[0x20];
3946
3947         u8         local_ack_timeout_err[0x20];
3948
3949         u8         reserved_at_320[0x4e0];
3950 };
3951
3952 struct mlx5_ifc_query_q_counter_in_bits {
3953         u8         opcode[0x10];
3954         u8         reserved_at_10[0x10];
3955
3956         u8         reserved_at_20[0x10];
3957         u8         op_mod[0x10];
3958
3959         u8         reserved_at_40[0x80];
3960
3961         u8         clear[0x1];
3962         u8         reserved_at_c1[0x1f];
3963
3964         u8         reserved_at_e0[0x18];
3965         u8         counter_set_id[0x8];
3966 };
3967
3968 struct mlx5_ifc_query_pages_out_bits {
3969         u8         status[0x8];
3970         u8         reserved_at_8[0x18];
3971
3972         u8         syndrome[0x20];
3973
3974         u8         reserved_at_40[0x10];
3975         u8         function_id[0x10];
3976
3977         u8         num_pages[0x20];
3978 };
3979
3980 enum {
3981         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3982         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3983         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3984 };
3985
3986 struct mlx5_ifc_query_pages_in_bits {
3987         u8         opcode[0x10];
3988         u8         reserved_at_10[0x10];
3989
3990         u8         reserved_at_20[0x10];
3991         u8         op_mod[0x10];
3992
3993         u8         reserved_at_40[0x10];
3994         u8         function_id[0x10];
3995
3996         u8         reserved_at_60[0x20];
3997 };
3998
3999 struct mlx5_ifc_query_nic_vport_context_out_bits {
4000         u8         status[0x8];
4001         u8         reserved_at_8[0x18];
4002
4003         u8         syndrome[0x20];
4004
4005         u8         reserved_at_40[0x40];
4006
4007         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4008 };
4009
4010 struct mlx5_ifc_query_nic_vport_context_in_bits {
4011         u8         opcode[0x10];
4012         u8         reserved_at_10[0x10];
4013
4014         u8         reserved_at_20[0x10];
4015         u8         op_mod[0x10];
4016
4017         u8         other_vport[0x1];
4018         u8         reserved_at_41[0xf];
4019         u8         vport_number[0x10];
4020
4021         u8         reserved_at_60[0x5];
4022         u8         allowed_list_type[0x3];
4023         u8         reserved_at_68[0x18];
4024 };
4025
4026 struct mlx5_ifc_query_mkey_out_bits {
4027         u8         status[0x8];
4028         u8         reserved_at_8[0x18];
4029
4030         u8         syndrome[0x20];
4031
4032         u8         reserved_at_40[0x40];
4033
4034         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4035
4036         u8         reserved_at_280[0x600];
4037
4038         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4039
4040         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4041 };
4042
4043 struct mlx5_ifc_query_mkey_in_bits {
4044         u8         opcode[0x10];
4045         u8         reserved_at_10[0x10];
4046
4047         u8         reserved_at_20[0x10];
4048         u8         op_mod[0x10];
4049
4050         u8         reserved_at_40[0x8];
4051         u8         mkey_index[0x18];
4052
4053         u8         pg_access[0x1];
4054         u8         reserved_at_61[0x1f];
4055 };
4056
4057 struct mlx5_ifc_query_mad_demux_out_bits {
4058         u8         status[0x8];
4059         u8         reserved_at_8[0x18];
4060
4061         u8         syndrome[0x20];
4062
4063         u8         reserved_at_40[0x40];
4064
4065         u8         mad_dumux_parameters_block[0x20];
4066 };
4067
4068 struct mlx5_ifc_query_mad_demux_in_bits {
4069         u8         opcode[0x10];
4070         u8         reserved_at_10[0x10];
4071
4072         u8         reserved_at_20[0x10];
4073         u8         op_mod[0x10];
4074
4075         u8         reserved_at_40[0x40];
4076 };
4077
4078 struct mlx5_ifc_query_l2_table_entry_out_bits {
4079         u8         status[0x8];
4080         u8         reserved_at_8[0x18];
4081
4082         u8         syndrome[0x20];
4083
4084         u8         reserved_at_40[0xa0];
4085
4086         u8         reserved_at_e0[0x13];
4087         u8         vlan_valid[0x1];
4088         u8         vlan[0xc];
4089
4090         struct mlx5_ifc_mac_address_layout_bits mac_address;
4091
4092         u8         reserved_at_140[0xc0];
4093 };
4094
4095 struct mlx5_ifc_query_l2_table_entry_in_bits {
4096         u8         opcode[0x10];
4097         u8         reserved_at_10[0x10];
4098
4099         u8         reserved_at_20[0x10];
4100         u8         op_mod[0x10];
4101
4102         u8         reserved_at_40[0x60];
4103
4104         u8         reserved_at_a0[0x8];
4105         u8         table_index[0x18];
4106
4107         u8         reserved_at_c0[0x140];
4108 };
4109
4110 struct mlx5_ifc_query_issi_out_bits {
4111         u8         status[0x8];
4112         u8         reserved_at_8[0x18];
4113
4114         u8         syndrome[0x20];
4115
4116         u8         reserved_at_40[0x10];
4117         u8         current_issi[0x10];
4118
4119         u8         reserved_at_60[0xa0];
4120
4121         u8         reserved_at_100[76][0x8];
4122         u8         supported_issi_dw0[0x20];
4123 };
4124
4125 struct mlx5_ifc_query_issi_in_bits {
4126         u8         opcode[0x10];
4127         u8         reserved_at_10[0x10];
4128
4129         u8         reserved_at_20[0x10];
4130         u8         op_mod[0x10];
4131
4132         u8         reserved_at_40[0x40];
4133 };
4134
4135 struct mlx5_ifc_set_driver_version_out_bits {
4136         u8         status[0x8];
4137         u8         reserved_0[0x18];
4138
4139         u8         syndrome[0x20];
4140         u8         reserved_1[0x40];
4141 };
4142
4143 struct mlx5_ifc_set_driver_version_in_bits {
4144         u8         opcode[0x10];
4145         u8         reserved_0[0x10];
4146
4147         u8         reserved_1[0x10];
4148         u8         op_mod[0x10];
4149
4150         u8         reserved_2[0x40];
4151         u8         driver_version[64][0x8];
4152 };
4153
4154 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4155         u8         status[0x8];
4156         u8         reserved_at_8[0x18];
4157
4158         u8         syndrome[0x20];
4159
4160         u8         reserved_at_40[0x40];
4161
4162         struct mlx5_ifc_pkey_bits pkey[0];
4163 };
4164
4165 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4166         u8         opcode[0x10];
4167         u8         reserved_at_10[0x10];
4168
4169         u8         reserved_at_20[0x10];
4170         u8         op_mod[0x10];
4171
4172         u8         other_vport[0x1];
4173         u8         reserved_at_41[0xb];
4174         u8         port_num[0x4];
4175         u8         vport_number[0x10];
4176
4177         u8         reserved_at_60[0x10];
4178         u8         pkey_index[0x10];
4179 };
4180
4181 enum {
4182         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4183         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4184         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4185 };
4186
4187 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4188         u8         status[0x8];
4189         u8         reserved_at_8[0x18];
4190
4191         u8         syndrome[0x20];
4192
4193         u8         reserved_at_40[0x20];
4194
4195         u8         gids_num[0x10];
4196         u8         reserved_at_70[0x10];
4197
4198         struct mlx5_ifc_array128_auto_bits gid[0];
4199 };
4200
4201 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4202         u8         opcode[0x10];
4203         u8         reserved_at_10[0x10];
4204
4205         u8         reserved_at_20[0x10];
4206         u8         op_mod[0x10];
4207
4208         u8         other_vport[0x1];
4209         u8         reserved_at_41[0xb];
4210         u8         port_num[0x4];
4211         u8         vport_number[0x10];
4212
4213         u8         reserved_at_60[0x10];
4214         u8         gid_index[0x10];
4215 };
4216
4217 struct mlx5_ifc_query_hca_vport_context_out_bits {
4218         u8         status[0x8];
4219         u8         reserved_at_8[0x18];
4220
4221         u8         syndrome[0x20];
4222
4223         u8         reserved_at_40[0x40];
4224
4225         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4226 };
4227
4228 struct mlx5_ifc_query_hca_vport_context_in_bits {
4229         u8         opcode[0x10];
4230         u8         reserved_at_10[0x10];
4231
4232         u8         reserved_at_20[0x10];
4233         u8         op_mod[0x10];
4234
4235         u8         other_vport[0x1];
4236         u8         reserved_at_41[0xb];
4237         u8         port_num[0x4];
4238         u8         vport_number[0x10];
4239
4240         u8         reserved_at_60[0x20];
4241 };
4242
4243 struct mlx5_ifc_query_hca_cap_out_bits {
4244         u8         status[0x8];
4245         u8         reserved_at_8[0x18];
4246
4247         u8         syndrome[0x20];
4248
4249         u8         reserved_at_40[0x40];
4250
4251         union mlx5_ifc_hca_cap_union_bits capability;
4252 };
4253
4254 struct mlx5_ifc_query_hca_cap_in_bits {
4255         u8         opcode[0x10];
4256         u8         reserved_at_10[0x10];
4257
4258         u8         reserved_at_20[0x10];
4259         u8         op_mod[0x10];
4260
4261         u8         reserved_at_40[0x40];
4262 };
4263
4264 struct mlx5_ifc_query_flow_table_out_bits {
4265         u8         status[0x8];
4266         u8         reserved_at_8[0x18];
4267
4268         u8         syndrome[0x20];
4269
4270         u8         reserved_at_40[0x80];
4271
4272         u8         reserved_at_c0[0x8];
4273         u8         level[0x8];
4274         u8         reserved_at_d0[0x8];
4275         u8         log_size[0x8];
4276
4277         u8         reserved_at_e0[0x120];
4278 };
4279
4280 struct mlx5_ifc_query_flow_table_in_bits {
4281         u8         opcode[0x10];
4282         u8         reserved_at_10[0x10];
4283
4284         u8         reserved_at_20[0x10];
4285         u8         op_mod[0x10];
4286
4287         u8         reserved_at_40[0x40];
4288
4289         u8         table_type[0x8];
4290         u8         reserved_at_88[0x18];
4291
4292         u8         reserved_at_a0[0x8];
4293         u8         table_id[0x18];
4294
4295         u8         reserved_at_c0[0x140];
4296 };
4297
4298 struct mlx5_ifc_query_fte_out_bits {
4299         u8         status[0x8];
4300         u8         reserved_at_8[0x18];
4301
4302         u8         syndrome[0x20];
4303
4304         u8         reserved_at_40[0x1c0];
4305
4306         struct mlx5_ifc_flow_context_bits flow_context;
4307 };
4308
4309 struct mlx5_ifc_query_fte_in_bits {
4310         u8         opcode[0x10];
4311         u8         reserved_at_10[0x10];
4312
4313         u8         reserved_at_20[0x10];
4314         u8         op_mod[0x10];
4315
4316         u8         reserved_at_40[0x40];
4317
4318         u8         table_type[0x8];
4319         u8         reserved_at_88[0x18];
4320
4321         u8         reserved_at_a0[0x8];
4322         u8         table_id[0x18];
4323
4324         u8         reserved_at_c0[0x40];
4325
4326         u8         flow_index[0x20];
4327
4328         u8         reserved_at_120[0xe0];
4329 };
4330
4331 enum {
4332         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4333         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4334         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4335 };
4336
4337 struct mlx5_ifc_query_flow_group_out_bits {
4338         u8         status[0x8];
4339         u8         reserved_at_8[0x18];
4340
4341         u8         syndrome[0x20];
4342
4343         u8         reserved_at_40[0xa0];
4344
4345         u8         start_flow_index[0x20];
4346
4347         u8         reserved_at_100[0x20];
4348
4349         u8         end_flow_index[0x20];
4350
4351         u8         reserved_at_140[0xa0];
4352
4353         u8         reserved_at_1e0[0x18];
4354         u8         match_criteria_enable[0x8];
4355
4356         struct mlx5_ifc_fte_match_param_bits match_criteria;
4357
4358         u8         reserved_at_1200[0xe00];
4359 };
4360
4361 struct mlx5_ifc_query_flow_group_in_bits {
4362         u8         opcode[0x10];
4363         u8         reserved_at_10[0x10];
4364
4365         u8         reserved_at_20[0x10];
4366         u8         op_mod[0x10];
4367
4368         u8         reserved_at_40[0x40];
4369
4370         u8         table_type[0x8];
4371         u8         reserved_at_88[0x18];
4372
4373         u8         reserved_at_a0[0x8];
4374         u8         table_id[0x18];
4375
4376         u8         group_id[0x20];
4377
4378         u8         reserved_at_e0[0x120];
4379 };
4380
4381 struct mlx5_ifc_query_flow_counter_out_bits {
4382         u8         status[0x8];
4383         u8         reserved_at_8[0x18];
4384
4385         u8         syndrome[0x20];
4386
4387         u8         reserved_at_40[0x40];
4388
4389         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4390 };
4391
4392 struct mlx5_ifc_query_flow_counter_in_bits {
4393         u8         opcode[0x10];
4394         u8         reserved_at_10[0x10];
4395
4396         u8         reserved_at_20[0x10];
4397         u8         op_mod[0x10];
4398
4399         u8         reserved_at_40[0x80];
4400
4401         u8         clear[0x1];
4402         u8         reserved_at_c1[0xf];
4403         u8         num_of_counters[0x10];
4404
4405         u8         reserved_at_e0[0x10];
4406         u8         flow_counter_id[0x10];
4407 };
4408
4409 struct mlx5_ifc_query_esw_vport_context_out_bits {
4410         u8         status[0x8];
4411         u8         reserved_at_8[0x18];
4412
4413         u8         syndrome[0x20];
4414
4415         u8         reserved_at_40[0x40];
4416
4417         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4418 };
4419
4420 struct mlx5_ifc_query_esw_vport_context_in_bits {
4421         u8         opcode[0x10];
4422         u8         reserved_at_10[0x10];
4423
4424         u8         reserved_at_20[0x10];
4425         u8         op_mod[0x10];
4426
4427         u8         other_vport[0x1];
4428         u8         reserved_at_41[0xf];
4429         u8         vport_number[0x10];
4430
4431         u8         reserved_at_60[0x20];
4432 };
4433
4434 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4435         u8         status[0x8];
4436         u8         reserved_at_8[0x18];
4437
4438         u8         syndrome[0x20];
4439
4440         u8         reserved_at_40[0x40];
4441 };
4442
4443 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4444         u8         reserved_at_0[0x1c];
4445         u8         vport_cvlan_insert[0x1];
4446         u8         vport_svlan_insert[0x1];
4447         u8         vport_cvlan_strip[0x1];
4448         u8         vport_svlan_strip[0x1];
4449 };
4450
4451 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4452         u8         opcode[0x10];
4453         u8         reserved_at_10[0x10];
4454
4455         u8         reserved_at_20[0x10];
4456         u8         op_mod[0x10];
4457
4458         u8         other_vport[0x1];
4459         u8         reserved_at_41[0xf];
4460         u8         vport_number[0x10];
4461
4462         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4463
4464         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4465 };
4466
4467 struct mlx5_ifc_query_eq_out_bits {
4468         u8         status[0x8];
4469         u8         reserved_at_8[0x18];
4470
4471         u8         syndrome[0x20];
4472
4473         u8         reserved_at_40[0x40];
4474
4475         struct mlx5_ifc_eqc_bits eq_context_entry;
4476
4477         u8         reserved_at_280[0x40];
4478
4479         u8         event_bitmask[0x40];
4480
4481         u8         reserved_at_300[0x580];
4482
4483         u8         pas[0][0x40];
4484 };
4485
4486 struct mlx5_ifc_query_eq_in_bits {
4487         u8         opcode[0x10];
4488         u8         reserved_at_10[0x10];
4489
4490         u8         reserved_at_20[0x10];
4491         u8         op_mod[0x10];
4492
4493         u8         reserved_at_40[0x18];
4494         u8         eq_number[0x8];
4495
4496         u8         reserved_at_60[0x20];
4497 };
4498
4499 struct mlx5_ifc_encap_header_in_bits {
4500         u8         reserved_at_0[0x5];
4501         u8         header_type[0x3];
4502         u8         reserved_at_8[0xe];
4503         u8         encap_header_size[0xa];
4504
4505         u8         reserved_at_20[0x10];
4506         u8         encap_header[2][0x8];
4507
4508         u8         more_encap_header[0][0x8];
4509 };
4510
4511 struct mlx5_ifc_query_encap_header_out_bits {
4512         u8         status[0x8];
4513         u8         reserved_at_8[0x18];
4514
4515         u8         syndrome[0x20];
4516
4517         u8         reserved_at_40[0xa0];
4518
4519         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4520 };
4521
4522 struct mlx5_ifc_query_encap_header_in_bits {
4523         u8         opcode[0x10];
4524         u8         reserved_at_10[0x10];
4525
4526         u8         reserved_at_20[0x10];
4527         u8         op_mod[0x10];
4528
4529         u8         encap_id[0x20];
4530
4531         u8         reserved_at_60[0xa0];
4532 };
4533
4534 struct mlx5_ifc_alloc_encap_header_out_bits {
4535         u8         status[0x8];
4536         u8         reserved_at_8[0x18];
4537
4538         u8         syndrome[0x20];
4539
4540         u8         encap_id[0x20];
4541
4542         u8         reserved_at_60[0x20];
4543 };
4544
4545 struct mlx5_ifc_alloc_encap_header_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_at_10[0x10];
4548
4549         u8         reserved_at_20[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         reserved_at_40[0xa0];
4553
4554         struct mlx5_ifc_encap_header_in_bits encap_header;
4555 };
4556
4557 struct mlx5_ifc_dealloc_encap_header_out_bits {
4558         u8         status[0x8];
4559         u8         reserved_at_8[0x18];
4560
4561         u8         syndrome[0x20];
4562
4563         u8         reserved_at_40[0x40];
4564 };
4565
4566 struct mlx5_ifc_dealloc_encap_header_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_at_10[0x10];
4569
4570         u8         reserved_20[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         encap_id[0x20];
4574
4575         u8         reserved_60[0x20];
4576 };
4577
4578 struct mlx5_ifc_set_action_in_bits {
4579         u8         action_type[0x4];
4580         u8         field[0xc];
4581         u8         reserved_at_10[0x3];
4582         u8         offset[0x5];
4583         u8         reserved_at_18[0x3];
4584         u8         length[0x5];
4585
4586         u8         data[0x20];
4587 };
4588
4589 struct mlx5_ifc_add_action_in_bits {
4590         u8         action_type[0x4];
4591         u8         field[0xc];
4592         u8         reserved_at_10[0x10];
4593
4594         u8         data[0x20];
4595 };
4596
4597 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4598         struct mlx5_ifc_set_action_in_bits set_action_in;
4599         struct mlx5_ifc_add_action_in_bits add_action_in;
4600         u8         reserved_at_0[0x40];
4601 };
4602
4603 enum {
4604         MLX5_ACTION_TYPE_SET   = 0x1,
4605         MLX5_ACTION_TYPE_ADD   = 0x2,
4606 };
4607
4608 enum {
4609         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4610         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4611         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4612         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4613         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4614         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4615         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4616         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4617         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4618         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4619         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4620         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4621         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4622         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4623         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4624         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4625         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4626         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4627         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4628         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4629         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4630         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4631         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4632 };
4633
4634 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4635         u8         status[0x8];
4636         u8         reserved_at_8[0x18];
4637
4638         u8         syndrome[0x20];
4639
4640         u8         modify_header_id[0x20];
4641
4642         u8         reserved_at_60[0x20];
4643 };
4644
4645 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4646         u8         opcode[0x10];
4647         u8         reserved_at_10[0x10];
4648
4649         u8         reserved_at_20[0x10];
4650         u8         op_mod[0x10];
4651
4652         u8         reserved_at_40[0x20];
4653
4654         u8         table_type[0x8];
4655         u8         reserved_at_68[0x10];
4656         u8         num_of_actions[0x8];
4657
4658         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4659 };
4660
4661 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4662         u8         status[0x8];
4663         u8         reserved_at_8[0x18];
4664
4665         u8         syndrome[0x20];
4666
4667         u8         reserved_at_40[0x40];
4668 };
4669
4670 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_at_10[0x10];
4673
4674         u8         reserved_at_20[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         modify_header_id[0x20];
4678
4679         u8         reserved_at_60[0x20];
4680 };
4681
4682 struct mlx5_ifc_query_dct_out_bits {
4683         u8         status[0x8];
4684         u8         reserved_at_8[0x18];
4685
4686         u8         syndrome[0x20];
4687
4688         u8         reserved_at_40[0x40];
4689
4690         struct mlx5_ifc_dctc_bits dct_context_entry;
4691
4692         u8         reserved_at_280[0x180];
4693 };
4694
4695 struct mlx5_ifc_query_dct_in_bits {
4696         u8         opcode[0x10];
4697         u8         reserved_at_10[0x10];
4698
4699         u8         reserved_at_20[0x10];
4700         u8         op_mod[0x10];
4701
4702         u8         reserved_at_40[0x8];
4703         u8         dctn[0x18];
4704
4705         u8         reserved_at_60[0x20];
4706 };
4707
4708 struct mlx5_ifc_query_cq_out_bits {
4709         u8         status[0x8];
4710         u8         reserved_at_8[0x18];
4711
4712         u8         syndrome[0x20];
4713
4714         u8         reserved_at_40[0x40];
4715
4716         struct mlx5_ifc_cqc_bits cq_context;
4717
4718         u8         reserved_at_280[0x600];
4719
4720         u8         pas[0][0x40];
4721 };
4722
4723 struct mlx5_ifc_query_cq_in_bits {
4724         u8         opcode[0x10];
4725         u8         reserved_at_10[0x10];
4726
4727         u8         reserved_at_20[0x10];
4728         u8         op_mod[0x10];
4729
4730         u8         reserved_at_40[0x8];
4731         u8         cqn[0x18];
4732
4733         u8         reserved_at_60[0x20];
4734 };
4735
4736 struct mlx5_ifc_query_cong_status_out_bits {
4737         u8         status[0x8];
4738         u8         reserved_at_8[0x18];
4739
4740         u8         syndrome[0x20];
4741
4742         u8         reserved_at_40[0x20];
4743
4744         u8         enable[0x1];
4745         u8         tag_enable[0x1];
4746         u8         reserved_at_62[0x1e];
4747 };
4748
4749 struct mlx5_ifc_query_cong_status_in_bits {
4750         u8         opcode[0x10];
4751         u8         reserved_at_10[0x10];
4752
4753         u8         reserved_at_20[0x10];
4754         u8         op_mod[0x10];
4755
4756         u8         reserved_at_40[0x18];
4757         u8         priority[0x4];
4758         u8         cong_protocol[0x4];
4759
4760         u8         reserved_at_60[0x20];
4761 };
4762
4763 struct mlx5_ifc_query_cong_statistics_out_bits {
4764         u8         status[0x8];
4765         u8         reserved_at_8[0x18];
4766
4767         u8         syndrome[0x20];
4768
4769         u8         reserved_at_40[0x40];
4770
4771         u8         rp_cur_flows[0x20];
4772
4773         u8         sum_flows[0x20];
4774
4775         u8         rp_cnp_ignored_high[0x20];
4776
4777         u8         rp_cnp_ignored_low[0x20];
4778
4779         u8         rp_cnp_handled_high[0x20];
4780
4781         u8         rp_cnp_handled_low[0x20];
4782
4783         u8         reserved_at_140[0x100];
4784
4785         u8         time_stamp_high[0x20];
4786
4787         u8         time_stamp_low[0x20];
4788
4789         u8         accumulators_period[0x20];
4790
4791         u8         np_ecn_marked_roce_packets_high[0x20];
4792
4793         u8         np_ecn_marked_roce_packets_low[0x20];
4794
4795         u8         np_cnp_sent_high[0x20];
4796
4797         u8         np_cnp_sent_low[0x20];
4798
4799         u8         reserved_at_320[0x560];
4800 };
4801
4802 struct mlx5_ifc_query_cong_statistics_in_bits {
4803         u8         opcode[0x10];
4804         u8         reserved_at_10[0x10];
4805
4806         u8         reserved_at_20[0x10];
4807         u8         op_mod[0x10];
4808
4809         u8         clear[0x1];
4810         u8         reserved_at_41[0x1f];
4811
4812         u8         reserved_at_60[0x20];
4813 };
4814
4815 struct mlx5_ifc_query_cong_params_out_bits {
4816         u8         status[0x8];
4817         u8         reserved_at_8[0x18];
4818
4819         u8         syndrome[0x20];
4820
4821         u8         reserved_at_40[0x40];
4822
4823         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4824 };
4825
4826 struct mlx5_ifc_query_cong_params_in_bits {
4827         u8         opcode[0x10];
4828         u8         reserved_at_10[0x10];
4829
4830         u8         reserved_at_20[0x10];
4831         u8         op_mod[0x10];
4832
4833         u8         reserved_at_40[0x1c];
4834         u8         cong_protocol[0x4];
4835
4836         u8         reserved_at_60[0x20];
4837 };
4838
4839 struct mlx5_ifc_query_adapter_out_bits {
4840         u8         status[0x8];
4841         u8         reserved_at_8[0x18];
4842
4843         u8         syndrome[0x20];
4844
4845         u8         reserved_at_40[0x40];
4846
4847         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4848 };
4849
4850 struct mlx5_ifc_query_adapter_in_bits {
4851         u8         opcode[0x10];
4852         u8         reserved_at_10[0x10];
4853
4854         u8         reserved_at_20[0x10];
4855         u8         op_mod[0x10];
4856
4857         u8         reserved_at_40[0x40];
4858 };
4859
4860 struct mlx5_ifc_qp_2rst_out_bits {
4861         u8         status[0x8];
4862         u8         reserved_at_8[0x18];
4863
4864         u8         syndrome[0x20];
4865
4866         u8         reserved_at_40[0x40];
4867 };
4868
4869 struct mlx5_ifc_qp_2rst_in_bits {
4870         u8         opcode[0x10];
4871         u8         reserved_at_10[0x10];
4872
4873         u8         reserved_at_20[0x10];
4874         u8         op_mod[0x10];
4875
4876         u8         reserved_at_40[0x8];
4877         u8         qpn[0x18];
4878
4879         u8         reserved_at_60[0x20];
4880 };
4881
4882 struct mlx5_ifc_qp_2err_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         reserved_at_40[0x40];
4889 };
4890
4891 struct mlx5_ifc_qp_2err_in_bits {
4892         u8         opcode[0x10];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         reserved_at_20[0x10];
4896         u8         op_mod[0x10];
4897
4898         u8         reserved_at_40[0x8];
4899         u8         qpn[0x18];
4900
4901         u8         reserved_at_60[0x20];
4902 };
4903
4904 struct mlx5_ifc_page_fault_resume_out_bits {
4905         u8         status[0x8];
4906         u8         reserved_at_8[0x18];
4907
4908         u8         syndrome[0x20];
4909
4910         u8         reserved_at_40[0x40];
4911 };
4912
4913 struct mlx5_ifc_page_fault_resume_in_bits {
4914         u8         opcode[0x10];
4915         u8         reserved_at_10[0x10];
4916
4917         u8         reserved_at_20[0x10];
4918         u8         op_mod[0x10];
4919
4920         u8         error[0x1];
4921         u8         reserved_at_41[0x4];
4922         u8         page_fault_type[0x3];
4923         u8         wq_number[0x18];
4924
4925         u8         reserved_at_60[0x8];
4926         u8         token[0x18];
4927 };
4928
4929 struct mlx5_ifc_nop_out_bits {
4930         u8         status[0x8];
4931         u8         reserved_at_8[0x18];
4932
4933         u8         syndrome[0x20];
4934
4935         u8         reserved_at_40[0x40];
4936 };
4937
4938 struct mlx5_ifc_nop_in_bits {
4939         u8         opcode[0x10];
4940         u8         reserved_at_10[0x10];
4941
4942         u8         reserved_at_20[0x10];
4943         u8         op_mod[0x10];
4944
4945         u8         reserved_at_40[0x40];
4946 };
4947
4948 struct mlx5_ifc_modify_vport_state_out_bits {
4949         u8         status[0x8];
4950         u8         reserved_at_8[0x18];
4951
4952         u8         syndrome[0x20];
4953
4954         u8         reserved_at_40[0x40];
4955 };
4956
4957 struct mlx5_ifc_modify_vport_state_in_bits {
4958         u8         opcode[0x10];
4959         u8         reserved_at_10[0x10];
4960
4961         u8         reserved_at_20[0x10];
4962         u8         op_mod[0x10];
4963
4964         u8         other_vport[0x1];
4965         u8         reserved_at_41[0xf];
4966         u8         vport_number[0x10];
4967
4968         u8         reserved_at_60[0x18];
4969         u8         admin_state[0x4];
4970         u8         reserved_at_7c[0x4];
4971 };
4972
4973 struct mlx5_ifc_modify_tis_out_bits {
4974         u8         status[0x8];
4975         u8         reserved_at_8[0x18];
4976
4977         u8         syndrome[0x20];
4978
4979         u8         reserved_at_40[0x40];
4980 };
4981
4982 struct mlx5_ifc_modify_tis_bitmask_bits {
4983         u8         reserved_at_0[0x20];
4984
4985         u8         reserved_at_20[0x1d];
4986         u8         lag_tx_port_affinity[0x1];
4987         u8         strict_lag_tx_port_affinity[0x1];
4988         u8         prio[0x1];
4989 };
4990
4991 struct mlx5_ifc_modify_tis_in_bits {
4992         u8         opcode[0x10];
4993         u8         reserved_at_10[0x10];
4994
4995         u8         reserved_at_20[0x10];
4996         u8         op_mod[0x10];
4997
4998         u8         reserved_at_40[0x8];
4999         u8         tisn[0x18];
5000
5001         u8         reserved_at_60[0x20];
5002
5003         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5004
5005         u8         reserved_at_c0[0x40];
5006
5007         struct mlx5_ifc_tisc_bits ctx;
5008 };
5009
5010 struct mlx5_ifc_modify_tir_bitmask_bits {
5011         u8         reserved_at_0[0x20];
5012
5013         u8         reserved_at_20[0x1b];
5014         u8         self_lb_en[0x1];
5015         u8         reserved_at_3c[0x1];
5016         u8         hash[0x1];
5017         u8         reserved_at_3e[0x1];
5018         u8         lro[0x1];
5019 };
5020
5021 struct mlx5_ifc_modify_tir_out_bits {
5022         u8         status[0x8];
5023         u8         reserved_at_8[0x18];
5024
5025         u8         syndrome[0x20];
5026
5027         u8         reserved_at_40[0x40];
5028 };
5029
5030 struct mlx5_ifc_modify_tir_in_bits {
5031         u8         opcode[0x10];
5032         u8         reserved_at_10[0x10];
5033
5034         u8         reserved_at_20[0x10];
5035         u8         op_mod[0x10];
5036
5037         u8         reserved_at_40[0x8];
5038         u8         tirn[0x18];
5039
5040         u8         reserved_at_60[0x20];
5041
5042         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5043
5044         u8         reserved_at_c0[0x40];
5045
5046         struct mlx5_ifc_tirc_bits ctx;
5047 };
5048
5049 struct mlx5_ifc_modify_sq_out_bits {
5050         u8         status[0x8];
5051         u8         reserved_at_8[0x18];
5052
5053         u8         syndrome[0x20];
5054
5055         u8         reserved_at_40[0x40];
5056 };
5057
5058 struct mlx5_ifc_modify_sq_in_bits {
5059         u8         opcode[0x10];
5060         u8         reserved_at_10[0x10];
5061
5062         u8         reserved_at_20[0x10];
5063         u8         op_mod[0x10];
5064
5065         u8         sq_state[0x4];
5066         u8         reserved_at_44[0x4];
5067         u8         sqn[0x18];
5068
5069         u8         reserved_at_60[0x20];
5070
5071         u8         modify_bitmask[0x40];
5072
5073         u8         reserved_at_c0[0x40];
5074
5075         struct mlx5_ifc_sqc_bits ctx;
5076 };
5077
5078 struct mlx5_ifc_modify_scheduling_element_out_bits {
5079         u8         status[0x8];
5080         u8         reserved_at_8[0x18];
5081
5082         u8         syndrome[0x20];
5083
5084         u8         reserved_at_40[0x1c0];
5085 };
5086
5087 enum {
5088         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5089         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5090 };
5091
5092 struct mlx5_ifc_modify_scheduling_element_in_bits {
5093         u8         opcode[0x10];
5094         u8         reserved_at_10[0x10];
5095
5096         u8         reserved_at_20[0x10];
5097         u8         op_mod[0x10];
5098
5099         u8         scheduling_hierarchy[0x8];
5100         u8         reserved_at_48[0x18];
5101
5102         u8         scheduling_element_id[0x20];
5103
5104         u8         reserved_at_80[0x20];
5105
5106         u8         modify_bitmask[0x20];
5107
5108         u8         reserved_at_c0[0x40];
5109
5110         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5111
5112         u8         reserved_at_300[0x100];
5113 };
5114
5115 struct mlx5_ifc_modify_rqt_out_bits {
5116         u8         status[0x8];
5117         u8         reserved_at_8[0x18];
5118
5119         u8         syndrome[0x20];
5120
5121         u8         reserved_at_40[0x40];
5122 };
5123
5124 struct mlx5_ifc_rqt_bitmask_bits {
5125         u8         reserved_at_0[0x20];
5126
5127         u8         reserved_at_20[0x1f];
5128         u8         rqn_list[0x1];
5129 };
5130
5131 struct mlx5_ifc_modify_rqt_in_bits {
5132         u8         opcode[0x10];
5133         u8         reserved_at_10[0x10];
5134
5135         u8         reserved_at_20[0x10];
5136         u8         op_mod[0x10];
5137
5138         u8         reserved_at_40[0x8];
5139         u8         rqtn[0x18];
5140
5141         u8         reserved_at_60[0x20];
5142
5143         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5144
5145         u8         reserved_at_c0[0x40];
5146
5147         struct mlx5_ifc_rqtc_bits ctx;
5148 };
5149
5150 struct mlx5_ifc_modify_rq_out_bits {
5151         u8         status[0x8];
5152         u8         reserved_at_8[0x18];
5153
5154         u8         syndrome[0x20];
5155
5156         u8         reserved_at_40[0x40];
5157 };
5158
5159 enum {
5160         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5161         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5162         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5163 };
5164
5165 struct mlx5_ifc_modify_rq_in_bits {
5166         u8         opcode[0x10];
5167         u8         reserved_at_10[0x10];
5168
5169         u8         reserved_at_20[0x10];
5170         u8         op_mod[0x10];
5171
5172         u8         rq_state[0x4];
5173         u8         reserved_at_44[0x4];
5174         u8         rqn[0x18];
5175
5176         u8         reserved_at_60[0x20];
5177
5178         u8         modify_bitmask[0x40];
5179
5180         u8         reserved_at_c0[0x40];
5181
5182         struct mlx5_ifc_rqc_bits ctx;
5183 };
5184
5185 struct mlx5_ifc_modify_rmp_out_bits {
5186         u8         status[0x8];
5187         u8         reserved_at_8[0x18];
5188
5189         u8         syndrome[0x20];
5190
5191         u8         reserved_at_40[0x40];
5192 };
5193
5194 struct mlx5_ifc_rmp_bitmask_bits {
5195         u8         reserved_at_0[0x20];
5196
5197         u8         reserved_at_20[0x1f];
5198         u8         lwm[0x1];
5199 };
5200
5201 struct mlx5_ifc_modify_rmp_in_bits {
5202         u8         opcode[0x10];
5203         u8         reserved_at_10[0x10];
5204
5205         u8         reserved_at_20[0x10];
5206         u8         op_mod[0x10];
5207
5208         u8         rmp_state[0x4];
5209         u8         reserved_at_44[0x4];
5210         u8         rmpn[0x18];
5211
5212         u8         reserved_at_60[0x20];
5213
5214         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5215
5216         u8         reserved_at_c0[0x40];
5217
5218         struct mlx5_ifc_rmpc_bits ctx;
5219 };
5220
5221 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5222         u8         status[0x8];
5223         u8         reserved_at_8[0x18];
5224
5225         u8         syndrome[0x20];
5226
5227         u8         reserved_at_40[0x40];
5228 };
5229
5230 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5231         u8         reserved_at_0[0x16];
5232         u8         node_guid[0x1];
5233         u8         port_guid[0x1];
5234         u8         min_inline[0x1];
5235         u8         mtu[0x1];
5236         u8         change_event[0x1];
5237         u8         promisc[0x1];
5238         u8         permanent_address[0x1];
5239         u8         addresses_list[0x1];
5240         u8         roce_en[0x1];
5241         u8         reserved_at_1f[0x1];
5242 };
5243
5244 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         other_vport[0x1];
5252         u8         reserved_at_41[0xf];
5253         u8         vport_number[0x10];
5254
5255         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5256
5257         u8         reserved_at_80[0x780];
5258
5259         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5260 };
5261
5262 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5263         u8         status[0x8];
5264         u8         reserved_at_8[0x18];
5265
5266         u8         syndrome[0x20];
5267
5268         u8         reserved_at_40[0x40];
5269 };
5270
5271 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5272         u8         opcode[0x10];
5273         u8         reserved_at_10[0x10];
5274
5275         u8         reserved_at_20[0x10];
5276         u8         op_mod[0x10];
5277
5278         u8         other_vport[0x1];
5279         u8         reserved_at_41[0xb];
5280         u8         port_num[0x4];
5281         u8         vport_number[0x10];
5282
5283         u8         reserved_at_60[0x20];
5284
5285         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5286 };
5287
5288 struct mlx5_ifc_modify_cq_out_bits {
5289         u8         status[0x8];
5290         u8         reserved_at_8[0x18];
5291
5292         u8         syndrome[0x20];
5293
5294         u8         reserved_at_40[0x40];
5295 };
5296
5297 enum {
5298         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5299         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5300 };
5301
5302 struct mlx5_ifc_modify_cq_in_bits {
5303         u8         opcode[0x10];
5304         u8         reserved_at_10[0x10];
5305
5306         u8         reserved_at_20[0x10];
5307         u8         op_mod[0x10];
5308
5309         u8         reserved_at_40[0x8];
5310         u8         cqn[0x18];
5311
5312         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5313
5314         struct mlx5_ifc_cqc_bits cq_context;
5315
5316         u8         reserved_at_280[0x600];
5317
5318         u8         pas[0][0x40];
5319 };
5320
5321 struct mlx5_ifc_modify_cong_status_out_bits {
5322         u8         status[0x8];
5323         u8         reserved_at_8[0x18];
5324
5325         u8         syndrome[0x20];
5326
5327         u8         reserved_at_40[0x40];
5328 };
5329
5330 struct mlx5_ifc_modify_cong_status_in_bits {
5331         u8         opcode[0x10];
5332         u8         reserved_at_10[0x10];
5333
5334         u8         reserved_at_20[0x10];
5335         u8         op_mod[0x10];
5336
5337         u8         reserved_at_40[0x18];
5338         u8         priority[0x4];
5339         u8         cong_protocol[0x4];
5340
5341         u8         enable[0x1];
5342         u8         tag_enable[0x1];
5343         u8         reserved_at_62[0x1e];
5344 };
5345
5346 struct mlx5_ifc_modify_cong_params_out_bits {
5347         u8         status[0x8];
5348         u8         reserved_at_8[0x18];
5349
5350         u8         syndrome[0x20];
5351
5352         u8         reserved_at_40[0x40];
5353 };
5354
5355 struct mlx5_ifc_modify_cong_params_in_bits {
5356         u8         opcode[0x10];
5357         u8         reserved_at_10[0x10];
5358
5359         u8         reserved_at_20[0x10];
5360         u8         op_mod[0x10];
5361
5362         u8         reserved_at_40[0x1c];
5363         u8         cong_protocol[0x4];
5364
5365         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5366
5367         u8         reserved_at_80[0x80];
5368
5369         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5370 };
5371
5372 struct mlx5_ifc_manage_pages_out_bits {
5373         u8         status[0x8];
5374         u8         reserved_at_8[0x18];
5375
5376         u8         syndrome[0x20];
5377
5378         u8         output_num_entries[0x20];
5379
5380         u8         reserved_at_60[0x20];
5381
5382         u8         pas[0][0x40];
5383 };
5384
5385 enum {
5386         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5387         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5388         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5389 };
5390
5391 struct mlx5_ifc_manage_pages_in_bits {
5392         u8         opcode[0x10];
5393         u8         reserved_at_10[0x10];
5394
5395         u8         reserved_at_20[0x10];
5396         u8         op_mod[0x10];
5397
5398         u8         reserved_at_40[0x10];
5399         u8         function_id[0x10];
5400
5401         u8         input_num_entries[0x20];
5402
5403         u8         pas[0][0x40];
5404 };
5405
5406 struct mlx5_ifc_mad_ifc_out_bits {
5407         u8         status[0x8];
5408         u8         reserved_at_8[0x18];
5409
5410         u8         syndrome[0x20];
5411
5412         u8         reserved_at_40[0x40];
5413
5414         u8         response_mad_packet[256][0x8];
5415 };
5416
5417 struct mlx5_ifc_mad_ifc_in_bits {
5418         u8         opcode[0x10];
5419         u8         reserved_at_10[0x10];
5420
5421         u8         reserved_at_20[0x10];
5422         u8         op_mod[0x10];
5423
5424         u8         remote_lid[0x10];
5425         u8         reserved_at_50[0x8];
5426         u8         port[0x8];
5427
5428         u8         reserved_at_60[0x20];
5429
5430         u8         mad[256][0x8];
5431 };
5432
5433 struct mlx5_ifc_init_hca_out_bits {
5434         u8         status[0x8];
5435         u8         reserved_at_8[0x18];
5436
5437         u8         syndrome[0x20];
5438
5439         u8         reserved_at_40[0x40];
5440 };
5441
5442 struct mlx5_ifc_init_hca_in_bits {
5443         u8         opcode[0x10];
5444         u8         reserved_at_10[0x10];
5445
5446         u8         reserved_at_20[0x10];
5447         u8         op_mod[0x10];
5448
5449         u8         reserved_at_40[0x40];
5450 };
5451
5452 struct mlx5_ifc_init2rtr_qp_out_bits {
5453         u8         status[0x8];
5454         u8         reserved_at_8[0x18];
5455
5456         u8         syndrome[0x20];
5457
5458         u8         reserved_at_40[0x40];
5459 };
5460
5461 struct mlx5_ifc_init2rtr_qp_in_bits {
5462         u8         opcode[0x10];
5463         u8         reserved_at_10[0x10];
5464
5465         u8         reserved_at_20[0x10];
5466         u8         op_mod[0x10];
5467
5468         u8         reserved_at_40[0x8];
5469         u8         qpn[0x18];
5470
5471         u8         reserved_at_60[0x20];
5472
5473         u8         opt_param_mask[0x20];
5474
5475         u8         reserved_at_a0[0x20];
5476
5477         struct mlx5_ifc_qpc_bits qpc;
5478
5479         u8         reserved_at_800[0x80];
5480 };
5481
5482 struct mlx5_ifc_init2init_qp_out_bits {
5483         u8         status[0x8];
5484         u8         reserved_at_8[0x18];
5485
5486         u8         syndrome[0x20];
5487
5488         u8         reserved_at_40[0x40];
5489 };
5490
5491 struct mlx5_ifc_init2init_qp_in_bits {
5492         u8         opcode[0x10];
5493         u8         reserved_at_10[0x10];
5494
5495         u8         reserved_at_20[0x10];
5496         u8         op_mod[0x10];
5497
5498         u8         reserved_at_40[0x8];
5499         u8         qpn[0x18];
5500
5501         u8         reserved_at_60[0x20];
5502
5503         u8         opt_param_mask[0x20];
5504
5505         u8         reserved_at_a0[0x20];
5506
5507         struct mlx5_ifc_qpc_bits qpc;
5508
5509         u8         reserved_at_800[0x80];
5510 };
5511
5512 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5513         u8         status[0x8];
5514         u8         reserved_at_8[0x18];
5515
5516         u8         syndrome[0x20];
5517
5518         u8         reserved_at_40[0x40];
5519
5520         u8         packet_headers_log[128][0x8];
5521
5522         u8         packet_syndrome[64][0x8];
5523 };
5524
5525 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5526         u8         opcode[0x10];
5527         u8         reserved_at_10[0x10];
5528
5529         u8         reserved_at_20[0x10];
5530         u8         op_mod[0x10];
5531
5532         u8         reserved_at_40[0x40];
5533 };
5534
5535 struct mlx5_ifc_gen_eqe_in_bits {
5536         u8         opcode[0x10];
5537         u8         reserved_at_10[0x10];
5538
5539         u8         reserved_at_20[0x10];
5540         u8         op_mod[0x10];
5541
5542         u8         reserved_at_40[0x18];
5543         u8         eq_number[0x8];
5544
5545         u8         reserved_at_60[0x20];
5546
5547         u8         eqe[64][0x8];
5548 };
5549
5550 struct mlx5_ifc_gen_eq_out_bits {
5551         u8         status[0x8];
5552         u8         reserved_at_8[0x18];
5553
5554         u8         syndrome[0x20];
5555
5556         u8         reserved_at_40[0x40];
5557 };
5558
5559 struct mlx5_ifc_enable_hca_out_bits {
5560         u8         status[0x8];
5561         u8         reserved_at_8[0x18];
5562
5563         u8         syndrome[0x20];
5564
5565         u8         reserved_at_40[0x20];
5566 };
5567
5568 struct mlx5_ifc_enable_hca_in_bits {
5569         u8         opcode[0x10];
5570         u8         reserved_at_10[0x10];
5571
5572         u8         reserved_at_20[0x10];
5573         u8         op_mod[0x10];
5574
5575         u8         reserved_at_40[0x10];
5576         u8         function_id[0x10];
5577
5578         u8         reserved_at_60[0x20];
5579 };
5580
5581 struct mlx5_ifc_drain_dct_out_bits {
5582         u8         status[0x8];
5583         u8         reserved_at_8[0x18];
5584
5585         u8         syndrome[0x20];
5586
5587         u8         reserved_at_40[0x40];
5588 };
5589
5590 struct mlx5_ifc_drain_dct_in_bits {
5591         u8         opcode[0x10];
5592         u8         reserved_at_10[0x10];
5593
5594         u8         reserved_at_20[0x10];
5595         u8         op_mod[0x10];
5596
5597         u8         reserved_at_40[0x8];
5598         u8         dctn[0x18];
5599
5600         u8         reserved_at_60[0x20];
5601 };
5602
5603 struct mlx5_ifc_disable_hca_out_bits {
5604         u8         status[0x8];
5605         u8         reserved_at_8[0x18];
5606
5607         u8         syndrome[0x20];
5608
5609         u8         reserved_at_40[0x20];
5610 };
5611
5612 struct mlx5_ifc_disable_hca_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_at_10[0x10];
5615
5616         u8         reserved_at_20[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         reserved_at_40[0x10];
5620         u8         function_id[0x10];
5621
5622         u8         reserved_at_60[0x20];
5623 };
5624
5625 struct mlx5_ifc_detach_from_mcg_out_bits {
5626         u8         status[0x8];
5627         u8         reserved_at_8[0x18];
5628
5629         u8         syndrome[0x20];
5630
5631         u8         reserved_at_40[0x40];
5632 };
5633
5634 struct mlx5_ifc_detach_from_mcg_in_bits {
5635         u8         opcode[0x10];
5636         u8         reserved_at_10[0x10];
5637
5638         u8         reserved_at_20[0x10];
5639         u8         op_mod[0x10];
5640
5641         u8         reserved_at_40[0x8];
5642         u8         qpn[0x18];
5643
5644         u8         reserved_at_60[0x20];
5645
5646         u8         multicast_gid[16][0x8];
5647 };
5648
5649 struct mlx5_ifc_destroy_xrq_out_bits {
5650         u8         status[0x8];
5651         u8         reserved_at_8[0x18];
5652
5653         u8         syndrome[0x20];
5654
5655         u8         reserved_at_40[0x40];
5656 };
5657
5658 struct mlx5_ifc_destroy_xrq_in_bits {
5659         u8         opcode[0x10];
5660         u8         reserved_at_10[0x10];
5661
5662         u8         reserved_at_20[0x10];
5663         u8         op_mod[0x10];
5664
5665         u8         reserved_at_40[0x8];
5666         u8         xrqn[0x18];
5667
5668         u8         reserved_at_60[0x20];
5669 };
5670
5671 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5672         u8         status[0x8];
5673         u8         reserved_at_8[0x18];
5674
5675         u8         syndrome[0x20];
5676
5677         u8         reserved_at_40[0x40];
5678 };
5679
5680 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5681         u8         opcode[0x10];
5682         u8         reserved_at_10[0x10];
5683
5684         u8         reserved_at_20[0x10];
5685         u8         op_mod[0x10];
5686
5687         u8         reserved_at_40[0x8];
5688         u8         xrc_srqn[0x18];
5689
5690         u8         reserved_at_60[0x20];
5691 };
5692
5693 struct mlx5_ifc_destroy_tis_out_bits {
5694         u8         status[0x8];
5695         u8         reserved_at_8[0x18];
5696
5697         u8         syndrome[0x20];
5698
5699         u8         reserved_at_40[0x40];
5700 };
5701
5702 struct mlx5_ifc_destroy_tis_in_bits {
5703         u8         opcode[0x10];
5704         u8         reserved_at_10[0x10];
5705
5706         u8         reserved_at_20[0x10];
5707         u8         op_mod[0x10];
5708
5709         u8         reserved_at_40[0x8];
5710         u8         tisn[0x18];
5711
5712         u8         reserved_at_60[0x20];
5713 };
5714
5715 struct mlx5_ifc_destroy_tir_out_bits {
5716         u8         status[0x8];
5717         u8         reserved_at_8[0x18];
5718
5719         u8         syndrome[0x20];
5720
5721         u8         reserved_at_40[0x40];
5722 };
5723
5724 struct mlx5_ifc_destroy_tir_in_bits {
5725         u8         opcode[0x10];
5726         u8         reserved_at_10[0x10];
5727
5728         u8         reserved_at_20[0x10];
5729         u8         op_mod[0x10];
5730
5731         u8         reserved_at_40[0x8];
5732         u8         tirn[0x18];
5733
5734         u8         reserved_at_60[0x20];
5735 };
5736
5737 struct mlx5_ifc_destroy_srq_out_bits {
5738         u8         status[0x8];
5739         u8         reserved_at_8[0x18];
5740
5741         u8         syndrome[0x20];
5742
5743         u8         reserved_at_40[0x40];
5744 };
5745
5746 struct mlx5_ifc_destroy_srq_in_bits {
5747         u8         opcode[0x10];
5748         u8         reserved_at_10[0x10];
5749
5750         u8         reserved_at_20[0x10];
5751         u8         op_mod[0x10];
5752
5753         u8         reserved_at_40[0x8];
5754         u8         srqn[0x18];
5755
5756         u8         reserved_at_60[0x20];
5757 };
5758
5759 struct mlx5_ifc_destroy_sq_out_bits {
5760         u8         status[0x8];
5761         u8         reserved_at_8[0x18];
5762
5763         u8         syndrome[0x20];
5764
5765         u8         reserved_at_40[0x40];
5766 };
5767
5768 struct mlx5_ifc_destroy_sq_in_bits {
5769         u8         opcode[0x10];
5770         u8         reserved_at_10[0x10];
5771
5772         u8         reserved_at_20[0x10];
5773         u8         op_mod[0x10];
5774
5775         u8         reserved_at_40[0x8];
5776         u8         sqn[0x18];
5777
5778         u8         reserved_at_60[0x20];
5779 };
5780
5781 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5782         u8         status[0x8];
5783         u8         reserved_at_8[0x18];
5784
5785         u8         syndrome[0x20];
5786
5787         u8         reserved_at_40[0x1c0];
5788 };
5789
5790 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5791         u8         opcode[0x10];
5792         u8         reserved_at_10[0x10];
5793
5794         u8         reserved_at_20[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         scheduling_hierarchy[0x8];
5798         u8         reserved_at_48[0x18];
5799
5800         u8         scheduling_element_id[0x20];
5801
5802         u8         reserved_at_80[0x180];
5803 };
5804
5805 struct mlx5_ifc_destroy_rqt_out_bits {
5806         u8         status[0x8];
5807         u8         reserved_at_8[0x18];
5808
5809         u8         syndrome[0x20];
5810
5811         u8         reserved_at_40[0x40];
5812 };
5813
5814 struct mlx5_ifc_destroy_rqt_in_bits {
5815         u8         opcode[0x10];
5816         u8         reserved_at_10[0x10];
5817
5818         u8         reserved_at_20[0x10];
5819         u8         op_mod[0x10];
5820
5821         u8         reserved_at_40[0x8];
5822         u8         rqtn[0x18];
5823
5824         u8         reserved_at_60[0x20];
5825 };
5826
5827 struct mlx5_ifc_destroy_rq_out_bits {
5828         u8         status[0x8];
5829         u8         reserved_at_8[0x18];
5830
5831         u8         syndrome[0x20];
5832
5833         u8         reserved_at_40[0x40];
5834 };
5835
5836 struct mlx5_ifc_destroy_rq_in_bits {
5837         u8         opcode[0x10];
5838         u8         reserved_at_10[0x10];
5839
5840         u8         reserved_at_20[0x10];
5841         u8         op_mod[0x10];
5842
5843         u8         reserved_at_40[0x8];
5844         u8         rqn[0x18];
5845
5846         u8         reserved_at_60[0x20];
5847 };
5848
5849 struct mlx5_ifc_destroy_rmp_out_bits {
5850         u8         status[0x8];
5851         u8         reserved_at_8[0x18];
5852
5853         u8         syndrome[0x20];
5854
5855         u8         reserved_at_40[0x40];
5856 };
5857
5858 struct mlx5_ifc_destroy_rmp_in_bits {
5859         u8         opcode[0x10];
5860         u8         reserved_at_10[0x10];
5861
5862         u8         reserved_at_20[0x10];
5863         u8         op_mod[0x10];
5864
5865         u8         reserved_at_40[0x8];
5866         u8         rmpn[0x18];
5867
5868         u8         reserved_at_60[0x20];
5869 };
5870
5871 struct mlx5_ifc_destroy_qp_out_bits {
5872         u8         status[0x8];
5873         u8         reserved_at_8[0x18];
5874
5875         u8         syndrome[0x20];
5876
5877         u8         reserved_at_40[0x40];
5878 };
5879
5880 struct mlx5_ifc_destroy_qp_in_bits {
5881         u8         opcode[0x10];
5882         u8         reserved_at_10[0x10];
5883
5884         u8         reserved_at_20[0x10];
5885         u8         op_mod[0x10];
5886
5887         u8         reserved_at_40[0x8];
5888         u8         qpn[0x18];
5889
5890         u8         reserved_at_60[0x20];
5891 };
5892
5893 struct mlx5_ifc_destroy_psv_out_bits {
5894         u8         status[0x8];
5895         u8         reserved_at_8[0x18];
5896
5897         u8         syndrome[0x20];
5898
5899         u8         reserved_at_40[0x40];
5900 };
5901
5902 struct mlx5_ifc_destroy_psv_in_bits {
5903         u8         opcode[0x10];
5904         u8         reserved_at_10[0x10];
5905
5906         u8         reserved_at_20[0x10];
5907         u8         op_mod[0x10];
5908
5909         u8         reserved_at_40[0x8];
5910         u8         psvn[0x18];
5911
5912         u8         reserved_at_60[0x20];
5913 };
5914
5915 struct mlx5_ifc_destroy_mkey_out_bits {
5916         u8         status[0x8];
5917         u8         reserved_at_8[0x18];
5918
5919         u8         syndrome[0x20];
5920
5921         u8         reserved_at_40[0x40];
5922 };
5923
5924 struct mlx5_ifc_destroy_mkey_in_bits {
5925         u8         opcode[0x10];
5926         u8         reserved_at_10[0x10];
5927
5928         u8         reserved_at_20[0x10];
5929         u8         op_mod[0x10];
5930
5931         u8         reserved_at_40[0x8];
5932         u8         mkey_index[0x18];
5933
5934         u8         reserved_at_60[0x20];
5935 };
5936
5937 struct mlx5_ifc_destroy_flow_table_out_bits {
5938         u8         status[0x8];
5939         u8         reserved_at_8[0x18];
5940
5941         u8         syndrome[0x20];
5942
5943         u8         reserved_at_40[0x40];
5944 };
5945
5946 struct mlx5_ifc_destroy_flow_table_in_bits {
5947         u8         opcode[0x10];
5948         u8         reserved_at_10[0x10];
5949
5950         u8         reserved_at_20[0x10];
5951         u8         op_mod[0x10];
5952
5953         u8         other_vport[0x1];
5954         u8         reserved_at_41[0xf];
5955         u8         vport_number[0x10];
5956
5957         u8         reserved_at_60[0x20];
5958
5959         u8         table_type[0x8];
5960         u8         reserved_at_88[0x18];
5961
5962         u8         reserved_at_a0[0x8];
5963         u8         table_id[0x18];
5964
5965         u8         reserved_at_c0[0x140];
5966 };
5967
5968 struct mlx5_ifc_destroy_flow_group_out_bits {
5969         u8         status[0x8];
5970         u8         reserved_at_8[0x18];
5971
5972         u8         syndrome[0x20];
5973
5974         u8         reserved_at_40[0x40];
5975 };
5976
5977 struct mlx5_ifc_destroy_flow_group_in_bits {
5978         u8         opcode[0x10];
5979         u8         reserved_at_10[0x10];
5980
5981         u8         reserved_at_20[0x10];
5982         u8         op_mod[0x10];
5983
5984         u8         other_vport[0x1];
5985         u8         reserved_at_41[0xf];
5986         u8         vport_number[0x10];
5987
5988         u8         reserved_at_60[0x20];
5989
5990         u8         table_type[0x8];
5991         u8         reserved_at_88[0x18];
5992
5993         u8         reserved_at_a0[0x8];
5994         u8         table_id[0x18];
5995
5996         u8         group_id[0x20];
5997
5998         u8         reserved_at_e0[0x120];
5999 };
6000
6001 struct mlx5_ifc_destroy_eq_out_bits {
6002         u8         status[0x8];
6003         u8         reserved_at_8[0x18];
6004
6005         u8         syndrome[0x20];
6006
6007         u8         reserved_at_40[0x40];
6008 };
6009
6010 struct mlx5_ifc_destroy_eq_in_bits {
6011         u8         opcode[0x10];
6012         u8         reserved_at_10[0x10];
6013
6014         u8         reserved_at_20[0x10];
6015         u8         op_mod[0x10];
6016
6017         u8         reserved_at_40[0x18];
6018         u8         eq_number[0x8];
6019
6020         u8         reserved_at_60[0x20];
6021 };
6022
6023 struct mlx5_ifc_destroy_dct_out_bits {
6024         u8         status[0x8];
6025         u8         reserved_at_8[0x18];
6026
6027         u8         syndrome[0x20];
6028
6029         u8         reserved_at_40[0x40];
6030 };
6031
6032 struct mlx5_ifc_destroy_dct_in_bits {
6033         u8         opcode[0x10];
6034         u8         reserved_at_10[0x10];
6035
6036         u8         reserved_at_20[0x10];
6037         u8         op_mod[0x10];
6038
6039         u8         reserved_at_40[0x8];
6040         u8         dctn[0x18];
6041
6042         u8         reserved_at_60[0x20];
6043 };
6044
6045 struct mlx5_ifc_destroy_cq_out_bits {
6046         u8         status[0x8];
6047         u8         reserved_at_8[0x18];
6048
6049         u8         syndrome[0x20];
6050
6051         u8         reserved_at_40[0x40];
6052 };
6053
6054 struct mlx5_ifc_destroy_cq_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_at_10[0x10];
6057
6058         u8         reserved_at_20[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         reserved_at_40[0x8];
6062         u8         cqn[0x18];
6063
6064         u8         reserved_at_60[0x20];
6065 };
6066
6067 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6068         u8         status[0x8];
6069         u8         reserved_at_8[0x18];
6070
6071         u8         syndrome[0x20];
6072
6073         u8         reserved_at_40[0x40];
6074 };
6075
6076 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6077         u8         opcode[0x10];
6078         u8         reserved_at_10[0x10];
6079
6080         u8         reserved_at_20[0x10];
6081         u8         op_mod[0x10];
6082
6083         u8         reserved_at_40[0x20];
6084
6085         u8         reserved_at_60[0x10];
6086         u8         vxlan_udp_port[0x10];
6087 };
6088
6089 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6090         u8         status[0x8];
6091         u8         reserved_at_8[0x18];
6092
6093         u8         syndrome[0x20];
6094
6095         u8         reserved_at_40[0x40];
6096 };
6097
6098 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6099         u8         opcode[0x10];
6100         u8         reserved_at_10[0x10];
6101
6102         u8         reserved_at_20[0x10];
6103         u8         op_mod[0x10];
6104
6105         u8         reserved_at_40[0x60];
6106
6107         u8         reserved_at_a0[0x8];
6108         u8         table_index[0x18];
6109
6110         u8         reserved_at_c0[0x140];
6111 };
6112
6113 struct mlx5_ifc_delete_fte_out_bits {
6114         u8         status[0x8];
6115         u8         reserved_at_8[0x18];
6116
6117         u8         syndrome[0x20];
6118
6119         u8         reserved_at_40[0x40];
6120 };
6121
6122 struct mlx5_ifc_delete_fte_in_bits {
6123         u8         opcode[0x10];
6124         u8         reserved_at_10[0x10];
6125
6126         u8         reserved_at_20[0x10];
6127         u8         op_mod[0x10];
6128
6129         u8         other_vport[0x1];
6130         u8         reserved_at_41[0xf];
6131         u8         vport_number[0x10];
6132
6133         u8         reserved_at_60[0x20];
6134
6135         u8         table_type[0x8];
6136         u8         reserved_at_88[0x18];
6137
6138         u8         reserved_at_a0[0x8];
6139         u8         table_id[0x18];
6140
6141         u8         reserved_at_c0[0x40];
6142
6143         u8         flow_index[0x20];
6144
6145         u8         reserved_at_120[0xe0];
6146 };
6147
6148 struct mlx5_ifc_dealloc_xrcd_out_bits {
6149         u8         status[0x8];
6150         u8         reserved_at_8[0x18];
6151
6152         u8         syndrome[0x20];
6153
6154         u8         reserved_at_40[0x40];
6155 };
6156
6157 struct mlx5_ifc_dealloc_xrcd_in_bits {
6158         u8         opcode[0x10];
6159         u8         reserved_at_10[0x10];
6160
6161         u8         reserved_at_20[0x10];
6162         u8         op_mod[0x10];
6163
6164         u8         reserved_at_40[0x8];
6165         u8         xrcd[0x18];
6166
6167         u8         reserved_at_60[0x20];
6168 };
6169
6170 struct mlx5_ifc_dealloc_uar_out_bits {
6171         u8         status[0x8];
6172         u8         reserved_at_8[0x18];
6173
6174         u8         syndrome[0x20];
6175
6176         u8         reserved_at_40[0x40];
6177 };
6178
6179 struct mlx5_ifc_dealloc_uar_in_bits {
6180         u8         opcode[0x10];
6181         u8         reserved_at_10[0x10];
6182
6183         u8         reserved_at_20[0x10];
6184         u8         op_mod[0x10];
6185
6186         u8         reserved_at_40[0x8];
6187         u8         uar[0x18];
6188
6189         u8         reserved_at_60[0x20];
6190 };
6191
6192 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6193         u8         status[0x8];
6194         u8         reserved_at_8[0x18];
6195
6196         u8         syndrome[0x20];
6197
6198         u8         reserved_at_40[0x40];
6199 };
6200
6201 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6202         u8         opcode[0x10];
6203         u8         reserved_at_10[0x10];
6204
6205         u8         reserved_at_20[0x10];
6206         u8         op_mod[0x10];
6207
6208         u8         reserved_at_40[0x8];
6209         u8         transport_domain[0x18];
6210
6211         u8         reserved_at_60[0x20];
6212 };
6213
6214 struct mlx5_ifc_dealloc_q_counter_out_bits {
6215         u8         status[0x8];
6216         u8         reserved_at_8[0x18];
6217
6218         u8         syndrome[0x20];
6219
6220         u8         reserved_at_40[0x40];
6221 };
6222
6223 struct mlx5_ifc_dealloc_q_counter_in_bits {
6224         u8         opcode[0x10];
6225         u8         reserved_at_10[0x10];
6226
6227         u8         reserved_at_20[0x10];
6228         u8         op_mod[0x10];
6229
6230         u8         reserved_at_40[0x18];
6231         u8         counter_set_id[0x8];
6232
6233         u8         reserved_at_60[0x20];
6234 };
6235
6236 struct mlx5_ifc_dealloc_pd_out_bits {
6237         u8         status[0x8];
6238         u8         reserved_at_8[0x18];
6239
6240         u8         syndrome[0x20];
6241
6242         u8         reserved_at_40[0x40];
6243 };
6244
6245 struct mlx5_ifc_dealloc_pd_in_bits {
6246         u8         opcode[0x10];
6247         u8         reserved_at_10[0x10];
6248
6249         u8         reserved_at_20[0x10];
6250         u8         op_mod[0x10];
6251
6252         u8         reserved_at_40[0x8];
6253         u8         pd[0x18];
6254
6255         u8         reserved_at_60[0x20];
6256 };
6257
6258 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6259         u8         status[0x8];
6260         u8         reserved_at_8[0x18];
6261
6262         u8         syndrome[0x20];
6263
6264         u8         reserved_at_40[0x40];
6265 };
6266
6267 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6268         u8         opcode[0x10];
6269         u8         reserved_at_10[0x10];
6270
6271         u8         reserved_at_20[0x10];
6272         u8         op_mod[0x10];
6273
6274         u8         reserved_at_40[0x10];
6275         u8         flow_counter_id[0x10];
6276
6277         u8         reserved_at_60[0x20];
6278 };
6279
6280 struct mlx5_ifc_create_xrq_out_bits {
6281         u8         status[0x8];
6282         u8         reserved_at_8[0x18];
6283
6284         u8         syndrome[0x20];
6285
6286         u8         reserved_at_40[0x8];
6287         u8         xrqn[0x18];
6288
6289         u8         reserved_at_60[0x20];
6290 };
6291
6292 struct mlx5_ifc_create_xrq_in_bits {
6293         u8         opcode[0x10];
6294         u8         reserved_at_10[0x10];
6295
6296         u8         reserved_at_20[0x10];
6297         u8         op_mod[0x10];
6298
6299         u8         reserved_at_40[0x40];
6300
6301         struct mlx5_ifc_xrqc_bits xrq_context;
6302 };
6303
6304 struct mlx5_ifc_create_xrc_srq_out_bits {
6305         u8         status[0x8];
6306         u8         reserved_at_8[0x18];
6307
6308         u8         syndrome[0x20];
6309
6310         u8         reserved_at_40[0x8];
6311         u8         xrc_srqn[0x18];
6312
6313         u8         reserved_at_60[0x20];
6314 };
6315
6316 struct mlx5_ifc_create_xrc_srq_in_bits {
6317         u8         opcode[0x10];
6318         u8         reserved_at_10[0x10];
6319
6320         u8         reserved_at_20[0x10];
6321         u8         op_mod[0x10];
6322
6323         u8         reserved_at_40[0x40];
6324
6325         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6326
6327         u8         reserved_at_280[0x600];
6328
6329         u8         pas[0][0x40];
6330 };
6331
6332 struct mlx5_ifc_create_tis_out_bits {
6333         u8         status[0x8];
6334         u8         reserved_at_8[0x18];
6335
6336         u8         syndrome[0x20];
6337
6338         u8         reserved_at_40[0x8];
6339         u8         tisn[0x18];
6340
6341         u8         reserved_at_60[0x20];
6342 };
6343
6344 struct mlx5_ifc_create_tis_in_bits {
6345         u8         opcode[0x10];
6346         u8         reserved_at_10[0x10];
6347
6348         u8         reserved_at_20[0x10];
6349         u8         op_mod[0x10];
6350
6351         u8         reserved_at_40[0xc0];
6352
6353         struct mlx5_ifc_tisc_bits ctx;
6354 };
6355
6356 struct mlx5_ifc_create_tir_out_bits {
6357         u8         status[0x8];
6358         u8         reserved_at_8[0x18];
6359
6360         u8         syndrome[0x20];
6361
6362         u8         reserved_at_40[0x8];
6363         u8         tirn[0x18];
6364
6365         u8         reserved_at_60[0x20];
6366 };
6367
6368 struct mlx5_ifc_create_tir_in_bits {
6369         u8         opcode[0x10];
6370         u8         reserved_at_10[0x10];
6371
6372         u8         reserved_at_20[0x10];
6373         u8         op_mod[0x10];
6374
6375         u8         reserved_at_40[0xc0];
6376
6377         struct mlx5_ifc_tirc_bits ctx;
6378 };
6379
6380 struct mlx5_ifc_create_srq_out_bits {
6381         u8         status[0x8];
6382         u8         reserved_at_8[0x18];
6383
6384         u8         syndrome[0x20];
6385
6386         u8         reserved_at_40[0x8];
6387         u8         srqn[0x18];
6388
6389         u8         reserved_at_60[0x20];
6390 };
6391
6392 struct mlx5_ifc_create_srq_in_bits {
6393         u8         opcode[0x10];
6394         u8         reserved_at_10[0x10];
6395
6396         u8         reserved_at_20[0x10];
6397         u8         op_mod[0x10];
6398
6399         u8         reserved_at_40[0x40];
6400
6401         struct mlx5_ifc_srqc_bits srq_context_entry;
6402
6403         u8         reserved_at_280[0x600];
6404
6405         u8         pas[0][0x40];
6406 };
6407
6408 struct mlx5_ifc_create_sq_out_bits {
6409         u8         status[0x8];
6410         u8         reserved_at_8[0x18];
6411
6412         u8         syndrome[0x20];
6413
6414         u8         reserved_at_40[0x8];
6415         u8         sqn[0x18];
6416
6417         u8         reserved_at_60[0x20];
6418 };
6419
6420 struct mlx5_ifc_create_sq_in_bits {
6421         u8         opcode[0x10];
6422         u8         reserved_at_10[0x10];
6423
6424         u8         reserved_at_20[0x10];
6425         u8         op_mod[0x10];
6426
6427         u8         reserved_at_40[0xc0];
6428
6429         struct mlx5_ifc_sqc_bits ctx;
6430 };
6431
6432 struct mlx5_ifc_create_scheduling_element_out_bits {
6433         u8         status[0x8];
6434         u8         reserved_at_8[0x18];
6435
6436         u8         syndrome[0x20];
6437
6438         u8         reserved_at_40[0x40];
6439
6440         u8         scheduling_element_id[0x20];
6441
6442         u8         reserved_at_a0[0x160];
6443 };
6444
6445 struct mlx5_ifc_create_scheduling_element_in_bits {
6446         u8         opcode[0x10];
6447         u8         reserved_at_10[0x10];
6448
6449         u8         reserved_at_20[0x10];
6450         u8         op_mod[0x10];
6451
6452         u8         scheduling_hierarchy[0x8];
6453         u8         reserved_at_48[0x18];
6454
6455         u8         reserved_at_60[0xa0];
6456
6457         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6458
6459         u8         reserved_at_300[0x100];
6460 };
6461
6462 struct mlx5_ifc_create_rqt_out_bits {
6463         u8         status[0x8];
6464         u8         reserved_at_8[0x18];
6465
6466         u8         syndrome[0x20];
6467
6468         u8         reserved_at_40[0x8];
6469         u8         rqtn[0x18];
6470
6471         u8         reserved_at_60[0x20];
6472 };
6473
6474 struct mlx5_ifc_create_rqt_in_bits {
6475         u8         opcode[0x10];
6476         u8         reserved_at_10[0x10];
6477
6478         u8         reserved_at_20[0x10];
6479         u8         op_mod[0x10];
6480
6481         u8         reserved_at_40[0xc0];
6482
6483         struct mlx5_ifc_rqtc_bits rqt_context;
6484 };
6485
6486 struct mlx5_ifc_create_rq_out_bits {
6487         u8         status[0x8];
6488         u8         reserved_at_8[0x18];
6489
6490         u8         syndrome[0x20];
6491
6492         u8         reserved_at_40[0x8];
6493         u8         rqn[0x18];
6494
6495         u8         reserved_at_60[0x20];
6496 };
6497
6498 struct mlx5_ifc_create_rq_in_bits {
6499         u8         opcode[0x10];
6500         u8         reserved_at_10[0x10];
6501
6502         u8         reserved_at_20[0x10];
6503         u8         op_mod[0x10];
6504
6505         u8         reserved_at_40[0xc0];
6506
6507         struct mlx5_ifc_rqc_bits ctx;
6508 };
6509
6510 struct mlx5_ifc_create_rmp_out_bits {
6511         u8         status[0x8];
6512         u8         reserved_at_8[0x18];
6513
6514         u8         syndrome[0x20];
6515
6516         u8         reserved_at_40[0x8];
6517         u8         rmpn[0x18];
6518
6519         u8         reserved_at_60[0x20];
6520 };
6521
6522 struct mlx5_ifc_create_rmp_in_bits {
6523         u8         opcode[0x10];
6524         u8         reserved_at_10[0x10];
6525
6526         u8         reserved_at_20[0x10];
6527         u8         op_mod[0x10];
6528
6529         u8         reserved_at_40[0xc0];
6530
6531         struct mlx5_ifc_rmpc_bits ctx;
6532 };
6533
6534 struct mlx5_ifc_create_qp_out_bits {
6535         u8         status[0x8];
6536         u8         reserved_at_8[0x18];
6537
6538         u8         syndrome[0x20];
6539
6540         u8         reserved_at_40[0x8];
6541         u8         qpn[0x18];
6542
6543         u8         reserved_at_60[0x20];
6544 };
6545
6546 struct mlx5_ifc_create_qp_in_bits {
6547         u8         opcode[0x10];
6548         u8         reserved_at_10[0x10];
6549
6550         u8         reserved_at_20[0x10];
6551         u8         op_mod[0x10];
6552
6553         u8         reserved_at_40[0x40];
6554
6555         u8         opt_param_mask[0x20];
6556
6557         u8         reserved_at_a0[0x20];
6558
6559         struct mlx5_ifc_qpc_bits qpc;
6560
6561         u8         reserved_at_800[0x80];
6562
6563         u8         pas[0][0x40];
6564 };
6565
6566 struct mlx5_ifc_create_psv_out_bits {
6567         u8         status[0x8];
6568         u8         reserved_at_8[0x18];
6569
6570         u8         syndrome[0x20];
6571
6572         u8         reserved_at_40[0x40];
6573
6574         u8         reserved_at_80[0x8];
6575         u8         psv0_index[0x18];
6576
6577         u8         reserved_at_a0[0x8];
6578         u8         psv1_index[0x18];
6579
6580         u8         reserved_at_c0[0x8];
6581         u8         psv2_index[0x18];
6582
6583         u8         reserved_at_e0[0x8];
6584         u8         psv3_index[0x18];
6585 };
6586
6587 struct mlx5_ifc_create_psv_in_bits {
6588         u8         opcode[0x10];
6589         u8         reserved_at_10[0x10];
6590
6591         u8         reserved_at_20[0x10];
6592         u8         op_mod[0x10];
6593
6594         u8         num_psv[0x4];
6595         u8         reserved_at_44[0x4];
6596         u8         pd[0x18];
6597
6598         u8         reserved_at_60[0x20];
6599 };
6600
6601 struct mlx5_ifc_create_mkey_out_bits {
6602         u8         status[0x8];
6603         u8         reserved_at_8[0x18];
6604
6605         u8         syndrome[0x20];
6606
6607         u8         reserved_at_40[0x8];
6608         u8         mkey_index[0x18];
6609
6610         u8         reserved_at_60[0x20];
6611 };
6612
6613 struct mlx5_ifc_create_mkey_in_bits {
6614         u8         opcode[0x10];
6615         u8         reserved_at_10[0x10];
6616
6617         u8         reserved_at_20[0x10];
6618         u8         op_mod[0x10];
6619
6620         u8         reserved_at_40[0x20];
6621
6622         u8         pg_access[0x1];
6623         u8         reserved_at_61[0x1f];
6624
6625         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6626
6627         u8         reserved_at_280[0x80];
6628
6629         u8         translations_octword_actual_size[0x20];
6630
6631         u8         reserved_at_320[0x560];
6632
6633         u8         klm_pas_mtt[0][0x20];
6634 };
6635
6636 struct mlx5_ifc_create_flow_table_out_bits {
6637         u8         status[0x8];
6638         u8         reserved_at_8[0x18];
6639
6640         u8         syndrome[0x20];
6641
6642         u8         reserved_at_40[0x8];
6643         u8         table_id[0x18];
6644
6645         u8         reserved_at_60[0x20];
6646 };
6647
6648 struct mlx5_ifc_flow_table_context_bits {
6649         u8         encap_en[0x1];
6650         u8         decap_en[0x1];
6651         u8         reserved_at_2[0x2];
6652         u8         table_miss_action[0x4];
6653         u8         level[0x8];
6654         u8         reserved_at_10[0x8];
6655         u8         log_size[0x8];
6656
6657         u8         reserved_at_20[0x8];
6658         u8         table_miss_id[0x18];
6659
6660         u8         reserved_at_40[0x8];
6661         u8         lag_master_next_table_id[0x18];
6662
6663         u8         reserved_at_60[0xe0];
6664 };
6665
6666 struct mlx5_ifc_create_flow_table_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         other_vport[0x1];
6674         u8         reserved_at_41[0xf];
6675         u8         vport_number[0x10];
6676
6677         u8         reserved_at_60[0x20];
6678
6679         u8         table_type[0x8];
6680         u8         reserved_at_88[0x18];
6681
6682         u8         reserved_at_a0[0x20];
6683
6684         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6685 };
6686
6687 struct mlx5_ifc_create_flow_group_out_bits {
6688         u8         status[0x8];
6689         u8         reserved_at_8[0x18];
6690
6691         u8         syndrome[0x20];
6692
6693         u8         reserved_at_40[0x8];
6694         u8         group_id[0x18];
6695
6696         u8         reserved_at_60[0x20];
6697 };
6698
6699 enum {
6700         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6701         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6702         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6703 };
6704
6705 struct mlx5_ifc_create_flow_group_in_bits {
6706         u8         opcode[0x10];
6707         u8         reserved_at_10[0x10];
6708
6709         u8         reserved_at_20[0x10];
6710         u8         op_mod[0x10];
6711
6712         u8         other_vport[0x1];
6713         u8         reserved_at_41[0xf];
6714         u8         vport_number[0x10];
6715
6716         u8         reserved_at_60[0x20];
6717
6718         u8         table_type[0x8];
6719         u8         reserved_at_88[0x18];
6720
6721         u8         reserved_at_a0[0x8];
6722         u8         table_id[0x18];
6723
6724         u8         reserved_at_c0[0x20];
6725
6726         u8         start_flow_index[0x20];
6727
6728         u8         reserved_at_100[0x20];
6729
6730         u8         end_flow_index[0x20];
6731
6732         u8         reserved_at_140[0xa0];
6733
6734         u8         reserved_at_1e0[0x18];
6735         u8         match_criteria_enable[0x8];
6736
6737         struct mlx5_ifc_fte_match_param_bits match_criteria;
6738
6739         u8         reserved_at_1200[0xe00];
6740 };
6741
6742 struct mlx5_ifc_create_eq_out_bits {
6743         u8         status[0x8];
6744         u8         reserved_at_8[0x18];
6745
6746         u8         syndrome[0x20];
6747
6748         u8         reserved_at_40[0x18];
6749         u8         eq_number[0x8];
6750
6751         u8         reserved_at_60[0x20];
6752 };
6753
6754 struct mlx5_ifc_create_eq_in_bits {
6755         u8         opcode[0x10];
6756         u8         reserved_at_10[0x10];
6757
6758         u8         reserved_at_20[0x10];
6759         u8         op_mod[0x10];
6760
6761         u8         reserved_at_40[0x40];
6762
6763         struct mlx5_ifc_eqc_bits eq_context_entry;
6764
6765         u8         reserved_at_280[0x40];
6766
6767         u8         event_bitmask[0x40];
6768
6769         u8         reserved_at_300[0x580];
6770
6771         u8         pas[0][0x40];
6772 };
6773
6774 struct mlx5_ifc_create_dct_out_bits {
6775         u8         status[0x8];
6776         u8         reserved_at_8[0x18];
6777
6778         u8         syndrome[0x20];
6779
6780         u8         reserved_at_40[0x8];
6781         u8         dctn[0x18];
6782
6783         u8         reserved_at_60[0x20];
6784 };
6785
6786 struct mlx5_ifc_create_dct_in_bits {
6787         u8         opcode[0x10];
6788         u8         reserved_at_10[0x10];
6789
6790         u8         reserved_at_20[0x10];
6791         u8         op_mod[0x10];
6792
6793         u8         reserved_at_40[0x40];
6794
6795         struct mlx5_ifc_dctc_bits dct_context_entry;
6796
6797         u8         reserved_at_280[0x180];
6798 };
6799
6800 struct mlx5_ifc_create_cq_out_bits {
6801         u8         status[0x8];
6802         u8         reserved_at_8[0x18];
6803
6804         u8         syndrome[0x20];
6805
6806         u8         reserved_at_40[0x8];
6807         u8         cqn[0x18];
6808
6809         u8         reserved_at_60[0x20];
6810 };
6811
6812 struct mlx5_ifc_create_cq_in_bits {
6813         u8         opcode[0x10];
6814         u8         reserved_at_10[0x10];
6815
6816         u8         reserved_at_20[0x10];
6817         u8         op_mod[0x10];
6818
6819         u8         reserved_at_40[0x40];
6820
6821         struct mlx5_ifc_cqc_bits cq_context;
6822
6823         u8         reserved_at_280[0x600];
6824
6825         u8         pas[0][0x40];
6826 };
6827
6828 struct mlx5_ifc_config_int_moderation_out_bits {
6829         u8         status[0x8];
6830         u8         reserved_at_8[0x18];
6831
6832         u8         syndrome[0x20];
6833
6834         u8         reserved_at_40[0x4];
6835         u8         min_delay[0xc];
6836         u8         int_vector[0x10];
6837
6838         u8         reserved_at_60[0x20];
6839 };
6840
6841 enum {
6842         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6843         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6844 };
6845
6846 struct mlx5_ifc_config_int_moderation_in_bits {
6847         u8         opcode[0x10];
6848         u8         reserved_at_10[0x10];
6849
6850         u8         reserved_at_20[0x10];
6851         u8         op_mod[0x10];
6852
6853         u8         reserved_at_40[0x4];
6854         u8         min_delay[0xc];
6855         u8         int_vector[0x10];
6856
6857         u8         reserved_at_60[0x20];
6858 };
6859
6860 struct mlx5_ifc_attach_to_mcg_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_at_8[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_at_40[0x40];
6867 };
6868
6869 struct mlx5_ifc_attach_to_mcg_in_bits {
6870         u8         opcode[0x10];
6871         u8         reserved_at_10[0x10];
6872
6873         u8         reserved_at_20[0x10];
6874         u8         op_mod[0x10];
6875
6876         u8         reserved_at_40[0x8];
6877         u8         qpn[0x18];
6878
6879         u8         reserved_at_60[0x20];
6880
6881         u8         multicast_gid[16][0x8];
6882 };
6883
6884 struct mlx5_ifc_arm_xrq_out_bits {
6885         u8         status[0x8];
6886         u8         reserved_at_8[0x18];
6887
6888         u8         syndrome[0x20];
6889
6890         u8         reserved_at_40[0x40];
6891 };
6892
6893 struct mlx5_ifc_arm_xrq_in_bits {
6894         u8         opcode[0x10];
6895         u8         reserved_at_10[0x10];
6896
6897         u8         reserved_at_20[0x10];
6898         u8         op_mod[0x10];
6899
6900         u8         reserved_at_40[0x8];
6901         u8         xrqn[0x18];
6902
6903         u8         reserved_at_60[0x10];
6904         u8         lwm[0x10];
6905 };
6906
6907 struct mlx5_ifc_arm_xrc_srq_out_bits {
6908         u8         status[0x8];
6909         u8         reserved_at_8[0x18];
6910
6911         u8         syndrome[0x20];
6912
6913         u8         reserved_at_40[0x40];
6914 };
6915
6916 enum {
6917         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6918 };
6919
6920 struct mlx5_ifc_arm_xrc_srq_in_bits {
6921         u8         opcode[0x10];
6922         u8         reserved_at_10[0x10];
6923
6924         u8         reserved_at_20[0x10];
6925         u8         op_mod[0x10];
6926
6927         u8         reserved_at_40[0x8];
6928         u8         xrc_srqn[0x18];
6929
6930         u8         reserved_at_60[0x10];
6931         u8         lwm[0x10];
6932 };
6933
6934 struct mlx5_ifc_arm_rq_out_bits {
6935         u8         status[0x8];
6936         u8         reserved_at_8[0x18];
6937
6938         u8         syndrome[0x20];
6939
6940         u8         reserved_at_40[0x40];
6941 };
6942
6943 enum {
6944         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6945         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6946 };
6947
6948 struct mlx5_ifc_arm_rq_in_bits {
6949         u8         opcode[0x10];
6950         u8         reserved_at_10[0x10];
6951
6952         u8         reserved_at_20[0x10];
6953         u8         op_mod[0x10];
6954
6955         u8         reserved_at_40[0x8];
6956         u8         srq_number[0x18];
6957
6958         u8         reserved_at_60[0x10];
6959         u8         lwm[0x10];
6960 };
6961
6962 struct mlx5_ifc_arm_dct_out_bits {
6963         u8         status[0x8];
6964         u8         reserved_at_8[0x18];
6965
6966         u8         syndrome[0x20];
6967
6968         u8         reserved_at_40[0x40];
6969 };
6970
6971 struct mlx5_ifc_arm_dct_in_bits {
6972         u8         opcode[0x10];
6973         u8         reserved_at_10[0x10];
6974
6975         u8         reserved_at_20[0x10];
6976         u8         op_mod[0x10];
6977
6978         u8         reserved_at_40[0x8];
6979         u8         dct_number[0x18];
6980
6981         u8         reserved_at_60[0x20];
6982 };
6983
6984 struct mlx5_ifc_alloc_xrcd_out_bits {
6985         u8         status[0x8];
6986         u8         reserved_at_8[0x18];
6987
6988         u8         syndrome[0x20];
6989
6990         u8         reserved_at_40[0x8];
6991         u8         xrcd[0x18];
6992
6993         u8         reserved_at_60[0x20];
6994 };
6995
6996 struct mlx5_ifc_alloc_xrcd_in_bits {
6997         u8         opcode[0x10];
6998         u8         reserved_at_10[0x10];
6999
7000         u8         reserved_at_20[0x10];
7001         u8         op_mod[0x10];
7002
7003         u8         reserved_at_40[0x40];
7004 };
7005
7006 struct mlx5_ifc_alloc_uar_out_bits {
7007         u8         status[0x8];
7008         u8         reserved_at_8[0x18];
7009
7010         u8         syndrome[0x20];
7011
7012         u8         reserved_at_40[0x8];
7013         u8         uar[0x18];
7014
7015         u8         reserved_at_60[0x20];
7016 };
7017
7018 struct mlx5_ifc_alloc_uar_in_bits {
7019         u8         opcode[0x10];
7020         u8         reserved_at_10[0x10];
7021
7022         u8         reserved_at_20[0x10];
7023         u8         op_mod[0x10];
7024
7025         u8         reserved_at_40[0x40];
7026 };
7027
7028 struct mlx5_ifc_alloc_transport_domain_out_bits {
7029         u8         status[0x8];
7030         u8         reserved_at_8[0x18];
7031
7032         u8         syndrome[0x20];
7033
7034         u8         reserved_at_40[0x8];
7035         u8         transport_domain[0x18];
7036
7037         u8         reserved_at_60[0x20];
7038 };
7039
7040 struct mlx5_ifc_alloc_transport_domain_in_bits {
7041         u8         opcode[0x10];
7042         u8         reserved_at_10[0x10];
7043
7044         u8         reserved_at_20[0x10];
7045         u8         op_mod[0x10];
7046
7047         u8         reserved_at_40[0x40];
7048 };
7049
7050 struct mlx5_ifc_alloc_q_counter_out_bits {
7051         u8         status[0x8];
7052         u8         reserved_at_8[0x18];
7053
7054         u8         syndrome[0x20];
7055
7056         u8         reserved_at_40[0x18];
7057         u8         counter_set_id[0x8];
7058
7059         u8         reserved_at_60[0x20];
7060 };
7061
7062 struct mlx5_ifc_alloc_q_counter_in_bits {
7063         u8         opcode[0x10];
7064         u8         reserved_at_10[0x10];
7065
7066         u8         reserved_at_20[0x10];
7067         u8         op_mod[0x10];
7068
7069         u8         reserved_at_40[0x40];
7070 };
7071
7072 struct mlx5_ifc_alloc_pd_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         pd[0x18];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 struct mlx5_ifc_alloc_pd_in_bits {
7085         u8         opcode[0x10];
7086         u8         reserved_at_10[0x10];
7087
7088         u8         reserved_at_20[0x10];
7089         u8         op_mod[0x10];
7090
7091         u8         reserved_at_40[0x40];
7092 };
7093
7094 struct mlx5_ifc_alloc_flow_counter_out_bits {
7095         u8         status[0x8];
7096         u8         reserved_at_8[0x18];
7097
7098         u8         syndrome[0x20];
7099
7100         u8         reserved_at_40[0x10];
7101         u8         flow_counter_id[0x10];
7102
7103         u8         reserved_at_60[0x20];
7104 };
7105
7106 struct mlx5_ifc_alloc_flow_counter_in_bits {
7107         u8         opcode[0x10];
7108         u8         reserved_at_10[0x10];
7109
7110         u8         reserved_at_20[0x10];
7111         u8         op_mod[0x10];
7112
7113         u8         reserved_at_40[0x40];
7114 };
7115
7116 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7117         u8         status[0x8];
7118         u8         reserved_at_8[0x18];
7119
7120         u8         syndrome[0x20];
7121
7122         u8         reserved_at_40[0x40];
7123 };
7124
7125 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7126         u8         opcode[0x10];
7127         u8         reserved_at_10[0x10];
7128
7129         u8         reserved_at_20[0x10];
7130         u8         op_mod[0x10];
7131
7132         u8         reserved_at_40[0x20];
7133
7134         u8         reserved_at_60[0x10];
7135         u8         vxlan_udp_port[0x10];
7136 };
7137
7138 struct mlx5_ifc_set_rate_limit_out_bits {
7139         u8         status[0x8];
7140         u8         reserved_at_8[0x18];
7141
7142         u8         syndrome[0x20];
7143
7144         u8         reserved_at_40[0x40];
7145 };
7146
7147 struct mlx5_ifc_set_rate_limit_in_bits {
7148         u8         opcode[0x10];
7149         u8         reserved_at_10[0x10];
7150
7151         u8         reserved_at_20[0x10];
7152         u8         op_mod[0x10];
7153
7154         u8         reserved_at_40[0x10];
7155         u8         rate_limit_index[0x10];
7156
7157         u8         reserved_at_60[0x20];
7158
7159         u8         rate_limit[0x20];
7160 };
7161
7162 struct mlx5_ifc_access_register_out_bits {
7163         u8         status[0x8];
7164         u8         reserved_at_8[0x18];
7165
7166         u8         syndrome[0x20];
7167
7168         u8         reserved_at_40[0x40];
7169
7170         u8         register_data[0][0x20];
7171 };
7172
7173 enum {
7174         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7175         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7176 };
7177
7178 struct mlx5_ifc_access_register_in_bits {
7179         u8         opcode[0x10];
7180         u8         reserved_at_10[0x10];
7181
7182         u8         reserved_at_20[0x10];
7183         u8         op_mod[0x10];
7184
7185         u8         reserved_at_40[0x10];
7186         u8         register_id[0x10];
7187
7188         u8         argument[0x20];
7189
7190         u8         register_data[0][0x20];
7191 };
7192
7193 struct mlx5_ifc_sltp_reg_bits {
7194         u8         status[0x4];
7195         u8         version[0x4];
7196         u8         local_port[0x8];
7197         u8         pnat[0x2];
7198         u8         reserved_at_12[0x2];
7199         u8         lane[0x4];
7200         u8         reserved_at_18[0x8];
7201
7202         u8         reserved_at_20[0x20];
7203
7204         u8         reserved_at_40[0x7];
7205         u8         polarity[0x1];
7206         u8         ob_tap0[0x8];
7207         u8         ob_tap1[0x8];
7208         u8         ob_tap2[0x8];
7209
7210         u8         reserved_at_60[0xc];
7211         u8         ob_preemp_mode[0x4];
7212         u8         ob_reg[0x8];
7213         u8         ob_bias[0x8];
7214
7215         u8         reserved_at_80[0x20];
7216 };
7217
7218 struct mlx5_ifc_slrg_reg_bits {
7219         u8         status[0x4];
7220         u8         version[0x4];
7221         u8         local_port[0x8];
7222         u8         pnat[0x2];
7223         u8         reserved_at_12[0x2];
7224         u8         lane[0x4];
7225         u8         reserved_at_18[0x8];
7226
7227         u8         time_to_link_up[0x10];
7228         u8         reserved_at_30[0xc];
7229         u8         grade_lane_speed[0x4];
7230
7231         u8         grade_version[0x8];
7232         u8         grade[0x18];
7233
7234         u8         reserved_at_60[0x4];
7235         u8         height_grade_type[0x4];
7236         u8         height_grade[0x18];
7237
7238         u8         height_dz[0x10];
7239         u8         height_dv[0x10];
7240
7241         u8         reserved_at_a0[0x10];
7242         u8         height_sigma[0x10];
7243
7244         u8         reserved_at_c0[0x20];
7245
7246         u8         reserved_at_e0[0x4];
7247         u8         phase_grade_type[0x4];
7248         u8         phase_grade[0x18];
7249
7250         u8         reserved_at_100[0x8];
7251         u8         phase_eo_pos[0x8];
7252         u8         reserved_at_110[0x8];
7253         u8         phase_eo_neg[0x8];
7254
7255         u8         ffe_set_tested[0x10];
7256         u8         test_errors_per_lane[0x10];
7257 };
7258
7259 struct mlx5_ifc_pvlc_reg_bits {
7260         u8         reserved_at_0[0x8];
7261         u8         local_port[0x8];
7262         u8         reserved_at_10[0x10];
7263
7264         u8         reserved_at_20[0x1c];
7265         u8         vl_hw_cap[0x4];
7266
7267         u8         reserved_at_40[0x1c];
7268         u8         vl_admin[0x4];
7269
7270         u8         reserved_at_60[0x1c];
7271         u8         vl_operational[0x4];
7272 };
7273
7274 struct mlx5_ifc_pude_reg_bits {
7275         u8         swid[0x8];
7276         u8         local_port[0x8];
7277         u8         reserved_at_10[0x4];
7278         u8         admin_status[0x4];
7279         u8         reserved_at_18[0x4];
7280         u8         oper_status[0x4];
7281
7282         u8         reserved_at_20[0x60];
7283 };
7284
7285 struct mlx5_ifc_ptys_reg_bits {
7286         u8         reserved_at_0[0x1];
7287         u8         an_disable_admin[0x1];
7288         u8         an_disable_cap[0x1];
7289         u8         reserved_at_3[0x5];
7290         u8         local_port[0x8];
7291         u8         reserved_at_10[0xd];
7292         u8         proto_mask[0x3];
7293
7294         u8         an_status[0x4];
7295         u8         reserved_at_24[0x3c];
7296
7297         u8         eth_proto_capability[0x20];
7298
7299         u8         ib_link_width_capability[0x10];
7300         u8         ib_proto_capability[0x10];
7301
7302         u8         reserved_at_a0[0x20];
7303
7304         u8         eth_proto_admin[0x20];
7305
7306         u8         ib_link_width_admin[0x10];
7307         u8         ib_proto_admin[0x10];
7308
7309         u8         reserved_at_100[0x20];
7310
7311         u8         eth_proto_oper[0x20];
7312
7313         u8         ib_link_width_oper[0x10];
7314         u8         ib_proto_oper[0x10];
7315
7316         u8         reserved_at_160[0x1c];
7317         u8         connector_type[0x4];
7318
7319         u8         eth_proto_lp_advertise[0x20];
7320
7321         u8         reserved_at_1a0[0x60];
7322 };
7323
7324 struct mlx5_ifc_mlcr_reg_bits {
7325         u8         reserved_at_0[0x8];
7326         u8         local_port[0x8];
7327         u8         reserved_at_10[0x20];
7328
7329         u8         beacon_duration[0x10];
7330         u8         reserved_at_40[0x10];
7331
7332         u8         beacon_remain[0x10];
7333 };
7334
7335 struct mlx5_ifc_ptas_reg_bits {
7336         u8         reserved_at_0[0x20];
7337
7338         u8         algorithm_options[0x10];
7339         u8         reserved_at_30[0x4];
7340         u8         repetitions_mode[0x4];
7341         u8         num_of_repetitions[0x8];
7342
7343         u8         grade_version[0x8];
7344         u8         height_grade_type[0x4];
7345         u8         phase_grade_type[0x4];
7346         u8         height_grade_weight[0x8];
7347         u8         phase_grade_weight[0x8];
7348
7349         u8         gisim_measure_bits[0x10];
7350         u8         adaptive_tap_measure_bits[0x10];
7351
7352         u8         ber_bath_high_error_threshold[0x10];
7353         u8         ber_bath_mid_error_threshold[0x10];
7354
7355         u8         ber_bath_low_error_threshold[0x10];
7356         u8         one_ratio_high_threshold[0x10];
7357
7358         u8         one_ratio_high_mid_threshold[0x10];
7359         u8         one_ratio_low_mid_threshold[0x10];
7360
7361         u8         one_ratio_low_threshold[0x10];
7362         u8         ndeo_error_threshold[0x10];
7363
7364         u8         mixer_offset_step_size[0x10];
7365         u8         reserved_at_110[0x8];
7366         u8         mix90_phase_for_voltage_bath[0x8];
7367
7368         u8         mixer_offset_start[0x10];
7369         u8         mixer_offset_end[0x10];
7370
7371         u8         reserved_at_140[0x15];
7372         u8         ber_test_time[0xb];
7373 };
7374
7375 struct mlx5_ifc_pspa_reg_bits {
7376         u8         swid[0x8];
7377         u8         local_port[0x8];
7378         u8         sub_port[0x8];
7379         u8         reserved_at_18[0x8];
7380
7381         u8         reserved_at_20[0x20];
7382 };
7383
7384 struct mlx5_ifc_pqdr_reg_bits {
7385         u8         reserved_at_0[0x8];
7386         u8         local_port[0x8];
7387         u8         reserved_at_10[0x5];
7388         u8         prio[0x3];
7389         u8         reserved_at_18[0x6];
7390         u8         mode[0x2];
7391
7392         u8         reserved_at_20[0x20];
7393
7394         u8         reserved_at_40[0x10];
7395         u8         min_threshold[0x10];
7396
7397         u8         reserved_at_60[0x10];
7398         u8         max_threshold[0x10];
7399
7400         u8         reserved_at_80[0x10];
7401         u8         mark_probability_denominator[0x10];
7402
7403         u8         reserved_at_a0[0x60];
7404 };
7405
7406 struct mlx5_ifc_ppsc_reg_bits {
7407         u8         reserved_at_0[0x8];
7408         u8         local_port[0x8];
7409         u8         reserved_at_10[0x10];
7410
7411         u8         reserved_at_20[0x60];
7412
7413         u8         reserved_at_80[0x1c];
7414         u8         wrps_admin[0x4];
7415
7416         u8         reserved_at_a0[0x1c];
7417         u8         wrps_status[0x4];
7418
7419         u8         reserved_at_c0[0x8];
7420         u8         up_threshold[0x8];
7421         u8         reserved_at_d0[0x8];
7422         u8         down_threshold[0x8];
7423
7424         u8         reserved_at_e0[0x20];
7425
7426         u8         reserved_at_100[0x1c];
7427         u8         srps_admin[0x4];
7428
7429         u8         reserved_at_120[0x1c];
7430         u8         srps_status[0x4];
7431
7432         u8         reserved_at_140[0x40];
7433 };
7434
7435 struct mlx5_ifc_pplr_reg_bits {
7436         u8         reserved_at_0[0x8];
7437         u8         local_port[0x8];
7438         u8         reserved_at_10[0x10];
7439
7440         u8         reserved_at_20[0x8];
7441         u8         lb_cap[0x8];
7442         u8         reserved_at_30[0x8];
7443         u8         lb_en[0x8];
7444 };
7445
7446 struct mlx5_ifc_pplm_reg_bits {
7447         u8         reserved_at_0[0x8];
7448         u8         local_port[0x8];
7449         u8         reserved_at_10[0x10];
7450
7451         u8         reserved_at_20[0x20];
7452
7453         u8         port_profile_mode[0x8];
7454         u8         static_port_profile[0x8];
7455         u8         active_port_profile[0x8];
7456         u8         reserved_at_58[0x8];
7457
7458         u8         retransmission_active[0x8];
7459         u8         fec_mode_active[0x18];
7460
7461         u8         reserved_at_80[0x20];
7462 };
7463
7464 struct mlx5_ifc_ppcnt_reg_bits {
7465         u8         swid[0x8];
7466         u8         local_port[0x8];
7467         u8         pnat[0x2];
7468         u8         reserved_at_12[0x8];
7469         u8         grp[0x6];
7470
7471         u8         clr[0x1];
7472         u8         reserved_at_21[0x1c];
7473         u8         prio_tc[0x3];
7474
7475         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7476 };
7477
7478 struct mlx5_ifc_mpcnt_reg_bits {
7479         u8         reserved_at_0[0x8];
7480         u8         pcie_index[0x8];
7481         u8         reserved_at_10[0xa];
7482         u8         grp[0x6];
7483
7484         u8         clr[0x1];
7485         u8         reserved_at_21[0x1f];
7486
7487         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7488 };
7489
7490 struct mlx5_ifc_ppad_reg_bits {
7491         u8         reserved_at_0[0x3];
7492         u8         single_mac[0x1];
7493         u8         reserved_at_4[0x4];
7494         u8         local_port[0x8];
7495         u8         mac_47_32[0x10];
7496
7497         u8         mac_31_0[0x20];
7498
7499         u8         reserved_at_40[0x40];
7500 };
7501
7502 struct mlx5_ifc_pmtu_reg_bits {
7503         u8         reserved_at_0[0x8];
7504         u8         local_port[0x8];
7505         u8         reserved_at_10[0x10];
7506
7507         u8         max_mtu[0x10];
7508         u8         reserved_at_30[0x10];
7509
7510         u8         admin_mtu[0x10];
7511         u8         reserved_at_50[0x10];
7512
7513         u8         oper_mtu[0x10];
7514         u8         reserved_at_70[0x10];
7515 };
7516
7517 struct mlx5_ifc_pmpr_reg_bits {
7518         u8         reserved_at_0[0x8];
7519         u8         module[0x8];
7520         u8         reserved_at_10[0x10];
7521
7522         u8         reserved_at_20[0x18];
7523         u8         attenuation_5g[0x8];
7524
7525         u8         reserved_at_40[0x18];
7526         u8         attenuation_7g[0x8];
7527
7528         u8         reserved_at_60[0x18];
7529         u8         attenuation_12g[0x8];
7530 };
7531
7532 struct mlx5_ifc_pmpe_reg_bits {
7533         u8         reserved_at_0[0x8];
7534         u8         module[0x8];
7535         u8         reserved_at_10[0xc];
7536         u8         module_status[0x4];
7537
7538         u8         reserved_at_20[0x60];
7539 };
7540
7541 struct mlx5_ifc_pmpc_reg_bits {
7542         u8         module_state_updated[32][0x8];
7543 };
7544
7545 struct mlx5_ifc_pmlpn_reg_bits {
7546         u8         reserved_at_0[0x4];
7547         u8         mlpn_status[0x4];
7548         u8         local_port[0x8];
7549         u8         reserved_at_10[0x10];
7550
7551         u8         e[0x1];
7552         u8         reserved_at_21[0x1f];
7553 };
7554
7555 struct mlx5_ifc_pmlp_reg_bits {
7556         u8         rxtx[0x1];
7557         u8         reserved_at_1[0x7];
7558         u8         local_port[0x8];
7559         u8         reserved_at_10[0x8];
7560         u8         width[0x8];
7561
7562         u8         lane0_module_mapping[0x20];
7563
7564         u8         lane1_module_mapping[0x20];
7565
7566         u8         lane2_module_mapping[0x20];
7567
7568         u8         lane3_module_mapping[0x20];
7569
7570         u8         reserved_at_a0[0x160];
7571 };
7572
7573 struct mlx5_ifc_pmaos_reg_bits {
7574         u8         reserved_at_0[0x8];
7575         u8         module[0x8];
7576         u8         reserved_at_10[0x4];
7577         u8         admin_status[0x4];
7578         u8         reserved_at_18[0x4];
7579         u8         oper_status[0x4];
7580
7581         u8         ase[0x1];
7582         u8         ee[0x1];
7583         u8         reserved_at_22[0x1c];
7584         u8         e[0x2];
7585
7586         u8         reserved_at_40[0x40];
7587 };
7588
7589 struct mlx5_ifc_plpc_reg_bits {
7590         u8         reserved_at_0[0x4];
7591         u8         profile_id[0xc];
7592         u8         reserved_at_10[0x4];
7593         u8         proto_mask[0x4];
7594         u8         reserved_at_18[0x8];
7595
7596         u8         reserved_at_20[0x10];
7597         u8         lane_speed[0x10];
7598
7599         u8         reserved_at_40[0x17];
7600         u8         lpbf[0x1];
7601         u8         fec_mode_policy[0x8];
7602
7603         u8         retransmission_capability[0x8];
7604         u8         fec_mode_capability[0x18];
7605
7606         u8         retransmission_support_admin[0x8];
7607         u8         fec_mode_support_admin[0x18];
7608
7609         u8         retransmission_request_admin[0x8];
7610         u8         fec_mode_request_admin[0x18];
7611
7612         u8         reserved_at_c0[0x80];
7613 };
7614
7615 struct mlx5_ifc_plib_reg_bits {
7616         u8         reserved_at_0[0x8];
7617         u8         local_port[0x8];
7618         u8         reserved_at_10[0x8];
7619         u8         ib_port[0x8];
7620
7621         u8         reserved_at_20[0x60];
7622 };
7623
7624 struct mlx5_ifc_plbf_reg_bits {
7625         u8         reserved_at_0[0x8];
7626         u8         local_port[0x8];
7627         u8         reserved_at_10[0xd];
7628         u8         lbf_mode[0x3];
7629
7630         u8         reserved_at_20[0x20];
7631 };
7632
7633 struct mlx5_ifc_pipg_reg_bits {
7634         u8         reserved_at_0[0x8];
7635         u8         local_port[0x8];
7636         u8         reserved_at_10[0x10];
7637
7638         u8         dic[0x1];
7639         u8         reserved_at_21[0x19];
7640         u8         ipg[0x4];
7641         u8         reserved_at_3e[0x2];
7642 };
7643
7644 struct mlx5_ifc_pifr_reg_bits {
7645         u8         reserved_at_0[0x8];
7646         u8         local_port[0x8];
7647         u8         reserved_at_10[0x10];
7648
7649         u8         reserved_at_20[0xe0];
7650
7651         u8         port_filter[8][0x20];
7652
7653         u8         port_filter_update_en[8][0x20];
7654 };
7655
7656 struct mlx5_ifc_pfcc_reg_bits {
7657         u8         reserved_at_0[0x8];
7658         u8         local_port[0x8];
7659         u8         reserved_at_10[0x10];
7660
7661         u8         ppan[0x4];
7662         u8         reserved_at_24[0x4];
7663         u8         prio_mask_tx[0x8];
7664         u8         reserved_at_30[0x8];
7665         u8         prio_mask_rx[0x8];
7666
7667         u8         pptx[0x1];
7668         u8         aptx[0x1];
7669         u8         reserved_at_42[0x6];
7670         u8         pfctx[0x8];
7671         u8         reserved_at_50[0x10];
7672
7673         u8         pprx[0x1];
7674         u8         aprx[0x1];
7675         u8         reserved_at_62[0x6];
7676         u8         pfcrx[0x8];
7677         u8         reserved_at_70[0x10];
7678
7679         u8         reserved_at_80[0x80];
7680 };
7681
7682 struct mlx5_ifc_pelc_reg_bits {
7683         u8         op[0x4];
7684         u8         reserved_at_4[0x4];
7685         u8         local_port[0x8];
7686         u8         reserved_at_10[0x10];
7687
7688         u8         op_admin[0x8];
7689         u8         op_capability[0x8];
7690         u8         op_request[0x8];
7691         u8         op_active[0x8];
7692
7693         u8         admin[0x40];
7694
7695         u8         capability[0x40];
7696
7697         u8         request[0x40];
7698
7699         u8         active[0x40];
7700
7701         u8         reserved_at_140[0x80];
7702 };
7703
7704 struct mlx5_ifc_peir_reg_bits {
7705         u8         reserved_at_0[0x8];
7706         u8         local_port[0x8];
7707         u8         reserved_at_10[0x10];
7708
7709         u8         reserved_at_20[0xc];
7710         u8         error_count[0x4];
7711         u8         reserved_at_30[0x10];
7712
7713         u8         reserved_at_40[0xc];
7714         u8         lane[0x4];
7715         u8         reserved_at_50[0x8];
7716         u8         error_type[0x8];
7717 };
7718
7719 struct mlx5_ifc_pcam_enhanced_features_bits {
7720         u8         reserved_at_0[0x7c];
7721
7722         u8         ptys_connector_type[0x1];
7723         u8         reserved_at_7d[0x1];
7724         u8         ppcnt_discard_group[0x1];
7725         u8         ppcnt_statistical_group[0x1];
7726 };
7727
7728 struct mlx5_ifc_pcam_reg_bits {
7729         u8         reserved_at_0[0x8];
7730         u8         feature_group[0x8];
7731         u8         reserved_at_10[0x8];
7732         u8         access_reg_group[0x8];
7733
7734         u8         reserved_at_20[0x20];
7735
7736         union {
7737                 u8         reserved_at_0[0x80];
7738         } port_access_reg_cap_mask;
7739
7740         u8         reserved_at_c0[0x80];
7741
7742         union {
7743                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7744                 u8         reserved_at_0[0x80];
7745         } feature_cap_mask;
7746
7747         u8         reserved_at_1c0[0xc0];
7748 };
7749
7750 struct mlx5_ifc_mcam_enhanced_features_bits {
7751         u8         reserved_at_0[0x7d];
7752
7753         u8         mtpps_enh_out_per_adj[0x1];
7754         u8         mtpps_fs[0x1];
7755         u8         pcie_performance_group[0x1];
7756 };
7757
7758 struct mlx5_ifc_mcam_access_reg_bits {
7759         u8         reserved_at_0[0x1c];
7760         u8         mcda[0x1];
7761         u8         mcc[0x1];
7762         u8         mcqi[0x1];
7763         u8         reserved_at_1f[0x1];
7764
7765         u8         regs_95_to_64[0x20];
7766         u8         regs_63_to_32[0x20];
7767         u8         regs_31_to_0[0x20];
7768 };
7769
7770 struct mlx5_ifc_mcam_reg_bits {
7771         u8         reserved_at_0[0x8];
7772         u8         feature_group[0x8];
7773         u8         reserved_at_10[0x8];
7774         u8         access_reg_group[0x8];
7775
7776         u8         reserved_at_20[0x20];
7777
7778         union {
7779                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7780                 u8         reserved_at_0[0x80];
7781         } mng_access_reg_cap_mask;
7782
7783         u8         reserved_at_c0[0x80];
7784
7785         union {
7786                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7787                 u8         reserved_at_0[0x80];
7788         } mng_feature_cap_mask;
7789
7790         u8         reserved_at_1c0[0x80];
7791 };
7792
7793 struct mlx5_ifc_pcap_reg_bits {
7794         u8         reserved_at_0[0x8];
7795         u8         local_port[0x8];
7796         u8         reserved_at_10[0x10];
7797
7798         u8         port_capability_mask[4][0x20];
7799 };
7800
7801 struct mlx5_ifc_paos_reg_bits {
7802         u8         swid[0x8];
7803         u8         local_port[0x8];
7804         u8         reserved_at_10[0x4];
7805         u8         admin_status[0x4];
7806         u8         reserved_at_18[0x4];
7807         u8         oper_status[0x4];
7808
7809         u8         ase[0x1];
7810         u8         ee[0x1];
7811         u8         reserved_at_22[0x1c];
7812         u8         e[0x2];
7813
7814         u8         reserved_at_40[0x40];
7815 };
7816
7817 struct mlx5_ifc_pamp_reg_bits {
7818         u8         reserved_at_0[0x8];
7819         u8         opamp_group[0x8];
7820         u8         reserved_at_10[0xc];
7821         u8         opamp_group_type[0x4];
7822
7823         u8         start_index[0x10];
7824         u8         reserved_at_30[0x4];
7825         u8         num_of_indices[0xc];
7826
7827         u8         index_data[18][0x10];
7828 };
7829
7830 struct mlx5_ifc_pcmr_reg_bits {
7831         u8         reserved_at_0[0x8];
7832         u8         local_port[0x8];
7833         u8         reserved_at_10[0x2e];
7834         u8         fcs_cap[0x1];
7835         u8         reserved_at_3f[0x1f];
7836         u8         fcs_chk[0x1];
7837         u8         reserved_at_5f[0x1];
7838 };
7839
7840 struct mlx5_ifc_lane_2_module_mapping_bits {
7841         u8         reserved_at_0[0x6];
7842         u8         rx_lane[0x2];
7843         u8         reserved_at_8[0x6];
7844         u8         tx_lane[0x2];
7845         u8         reserved_at_10[0x8];
7846         u8         module[0x8];
7847 };
7848
7849 struct mlx5_ifc_bufferx_reg_bits {
7850         u8         reserved_at_0[0x6];
7851         u8         lossy[0x1];
7852         u8         epsb[0x1];
7853         u8         reserved_at_8[0xc];
7854         u8         size[0xc];
7855
7856         u8         xoff_threshold[0x10];
7857         u8         xon_threshold[0x10];
7858 };
7859
7860 struct mlx5_ifc_set_node_in_bits {
7861         u8         node_description[64][0x8];
7862 };
7863
7864 struct mlx5_ifc_register_power_settings_bits {
7865         u8         reserved_at_0[0x18];
7866         u8         power_settings_level[0x8];
7867
7868         u8         reserved_at_20[0x60];
7869 };
7870
7871 struct mlx5_ifc_register_host_endianness_bits {
7872         u8         he[0x1];
7873         u8         reserved_at_1[0x1f];
7874
7875         u8         reserved_at_20[0x60];
7876 };
7877
7878 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7879         u8         reserved_at_0[0x20];
7880
7881         u8         mkey[0x20];
7882
7883         u8         addressh_63_32[0x20];
7884
7885         u8         addressl_31_0[0x20];
7886 };
7887
7888 struct mlx5_ifc_ud_adrs_vector_bits {
7889         u8         dc_key[0x40];
7890
7891         u8         ext[0x1];
7892         u8         reserved_at_41[0x7];
7893         u8         destination_qp_dct[0x18];
7894
7895         u8         static_rate[0x4];
7896         u8         sl_eth_prio[0x4];
7897         u8         fl[0x1];
7898         u8         mlid[0x7];
7899         u8         rlid_udp_sport[0x10];
7900
7901         u8         reserved_at_80[0x20];
7902
7903         u8         rmac_47_16[0x20];
7904
7905         u8         rmac_15_0[0x10];
7906         u8         tclass[0x8];
7907         u8         hop_limit[0x8];
7908
7909         u8         reserved_at_e0[0x1];
7910         u8         grh[0x1];
7911         u8         reserved_at_e2[0x2];
7912         u8         src_addr_index[0x8];
7913         u8         flow_label[0x14];
7914
7915         u8         rgid_rip[16][0x8];
7916 };
7917
7918 struct mlx5_ifc_pages_req_event_bits {
7919         u8         reserved_at_0[0x10];
7920         u8         function_id[0x10];
7921
7922         u8         num_pages[0x20];
7923
7924         u8         reserved_at_40[0xa0];
7925 };
7926
7927 struct mlx5_ifc_eqe_bits {
7928         u8         reserved_at_0[0x8];
7929         u8         event_type[0x8];
7930         u8         reserved_at_10[0x8];
7931         u8         event_sub_type[0x8];
7932
7933         u8         reserved_at_20[0xe0];
7934
7935         union mlx5_ifc_event_auto_bits event_data;
7936
7937         u8         reserved_at_1e0[0x10];
7938         u8         signature[0x8];
7939         u8         reserved_at_1f8[0x7];
7940         u8         owner[0x1];
7941 };
7942
7943 enum {
7944         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7945 };
7946
7947 struct mlx5_ifc_cmd_queue_entry_bits {
7948         u8         type[0x8];
7949         u8         reserved_at_8[0x18];
7950
7951         u8         input_length[0x20];
7952
7953         u8         input_mailbox_pointer_63_32[0x20];
7954
7955         u8         input_mailbox_pointer_31_9[0x17];
7956         u8         reserved_at_77[0x9];
7957
7958         u8         command_input_inline_data[16][0x8];
7959
7960         u8         command_output_inline_data[16][0x8];
7961
7962         u8         output_mailbox_pointer_63_32[0x20];
7963
7964         u8         output_mailbox_pointer_31_9[0x17];
7965         u8         reserved_at_1b7[0x9];
7966
7967         u8         output_length[0x20];
7968
7969         u8         token[0x8];
7970         u8         signature[0x8];
7971         u8         reserved_at_1f0[0x8];
7972         u8         status[0x7];
7973         u8         ownership[0x1];
7974 };
7975
7976 struct mlx5_ifc_cmd_out_bits {
7977         u8         status[0x8];
7978         u8         reserved_at_8[0x18];
7979
7980         u8         syndrome[0x20];
7981
7982         u8         command_output[0x20];
7983 };
7984
7985 struct mlx5_ifc_cmd_in_bits {
7986         u8         opcode[0x10];
7987         u8         reserved_at_10[0x10];
7988
7989         u8         reserved_at_20[0x10];
7990         u8         op_mod[0x10];
7991
7992         u8         command[0][0x20];
7993 };
7994
7995 struct mlx5_ifc_cmd_if_box_bits {
7996         u8         mailbox_data[512][0x8];
7997
7998         u8         reserved_at_1000[0x180];
7999
8000         u8         next_pointer_63_32[0x20];
8001
8002         u8         next_pointer_31_10[0x16];
8003         u8         reserved_at_11b6[0xa];
8004
8005         u8         block_number[0x20];
8006
8007         u8         reserved_at_11e0[0x8];
8008         u8         token[0x8];
8009         u8         ctrl_signature[0x8];
8010         u8         signature[0x8];
8011 };
8012
8013 struct mlx5_ifc_mtt_bits {
8014         u8         ptag_63_32[0x20];
8015
8016         u8         ptag_31_8[0x18];
8017         u8         reserved_at_38[0x6];
8018         u8         wr_en[0x1];
8019         u8         rd_en[0x1];
8020 };
8021
8022 struct mlx5_ifc_query_wol_rol_out_bits {
8023         u8         status[0x8];
8024         u8         reserved_at_8[0x18];
8025
8026         u8         syndrome[0x20];
8027
8028         u8         reserved_at_40[0x10];
8029         u8         rol_mode[0x8];
8030         u8         wol_mode[0x8];
8031
8032         u8         reserved_at_60[0x20];
8033 };
8034
8035 struct mlx5_ifc_query_wol_rol_in_bits {
8036         u8         opcode[0x10];
8037         u8         reserved_at_10[0x10];
8038
8039         u8         reserved_at_20[0x10];
8040         u8         op_mod[0x10];
8041
8042         u8         reserved_at_40[0x40];
8043 };
8044
8045 struct mlx5_ifc_set_wol_rol_out_bits {
8046         u8         status[0x8];
8047         u8         reserved_at_8[0x18];
8048
8049         u8         syndrome[0x20];
8050
8051         u8         reserved_at_40[0x40];
8052 };
8053
8054 struct mlx5_ifc_set_wol_rol_in_bits {
8055         u8         opcode[0x10];
8056         u8         reserved_at_10[0x10];
8057
8058         u8         reserved_at_20[0x10];
8059         u8         op_mod[0x10];
8060
8061         u8         rol_mode_valid[0x1];
8062         u8         wol_mode_valid[0x1];
8063         u8         reserved_at_42[0xe];
8064         u8         rol_mode[0x8];
8065         u8         wol_mode[0x8];
8066
8067         u8         reserved_at_60[0x20];
8068 };
8069
8070 enum {
8071         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8072         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8073         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8074 };
8075
8076 enum {
8077         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8078         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8079         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8080 };
8081
8082 enum {
8083         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8084         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8085         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8086         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8087         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8088         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8089         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8090         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8091         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8092         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8093         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8094 };
8095
8096 struct mlx5_ifc_initial_seg_bits {
8097         u8         fw_rev_minor[0x10];
8098         u8         fw_rev_major[0x10];
8099
8100         u8         cmd_interface_rev[0x10];
8101         u8         fw_rev_subminor[0x10];
8102
8103         u8         reserved_at_40[0x40];
8104
8105         u8         cmdq_phy_addr_63_32[0x20];
8106
8107         u8         cmdq_phy_addr_31_12[0x14];
8108         u8         reserved_at_b4[0x2];
8109         u8         nic_interface[0x2];
8110         u8         log_cmdq_size[0x4];
8111         u8         log_cmdq_stride[0x4];
8112
8113         u8         command_doorbell_vector[0x20];
8114
8115         u8         reserved_at_e0[0xf00];
8116
8117         u8         initializing[0x1];
8118         u8         reserved_at_fe1[0x4];
8119         u8         nic_interface_supported[0x3];
8120         u8         reserved_at_fe8[0x18];
8121
8122         struct mlx5_ifc_health_buffer_bits health_buffer;
8123
8124         u8         no_dram_nic_offset[0x20];
8125
8126         u8         reserved_at_1220[0x6e40];
8127
8128         u8         reserved_at_8060[0x1f];
8129         u8         clear_int[0x1];
8130
8131         u8         health_syndrome[0x8];
8132         u8         health_counter[0x18];
8133
8134         u8         reserved_at_80a0[0x17fc0];
8135 };
8136
8137 struct mlx5_ifc_mtpps_reg_bits {
8138         u8         reserved_at_0[0xc];
8139         u8         cap_number_of_pps_pins[0x4];
8140         u8         reserved_at_10[0x4];
8141         u8         cap_max_num_of_pps_in_pins[0x4];
8142         u8         reserved_at_18[0x4];
8143         u8         cap_max_num_of_pps_out_pins[0x4];
8144
8145         u8         reserved_at_20[0x24];
8146         u8         cap_pin_3_mode[0x4];
8147         u8         reserved_at_48[0x4];
8148         u8         cap_pin_2_mode[0x4];
8149         u8         reserved_at_50[0x4];
8150         u8         cap_pin_1_mode[0x4];
8151         u8         reserved_at_58[0x4];
8152         u8         cap_pin_0_mode[0x4];
8153
8154         u8         reserved_at_60[0x4];
8155         u8         cap_pin_7_mode[0x4];
8156         u8         reserved_at_68[0x4];
8157         u8         cap_pin_6_mode[0x4];
8158         u8         reserved_at_70[0x4];
8159         u8         cap_pin_5_mode[0x4];
8160         u8         reserved_at_78[0x4];
8161         u8         cap_pin_4_mode[0x4];
8162
8163         u8         field_select[0x20];
8164         u8         reserved_at_a0[0x60];
8165
8166         u8         enable[0x1];
8167         u8         reserved_at_101[0xb];
8168         u8         pattern[0x4];
8169         u8         reserved_at_110[0x4];
8170         u8         pin_mode[0x4];
8171         u8         pin[0x8];
8172
8173         u8         reserved_at_120[0x20];
8174
8175         u8         time_stamp[0x40];
8176
8177         u8         out_pulse_duration[0x10];
8178         u8         out_periodic_adjustment[0x10];
8179         u8         enhanced_out_periodic_adjustment[0x20];
8180
8181         u8         reserved_at_1c0[0x20];
8182 };
8183
8184 struct mlx5_ifc_mtppse_reg_bits {
8185         u8         reserved_at_0[0x18];
8186         u8         pin[0x8];
8187         u8         event_arm[0x1];
8188         u8         reserved_at_21[0x1b];
8189         u8         event_generation_mode[0x4];
8190         u8         reserved_at_40[0x40];
8191 };
8192
8193 struct mlx5_ifc_mcqi_cap_bits {
8194         u8         supported_info_bitmask[0x20];
8195
8196         u8         component_size[0x20];
8197
8198         u8         max_component_size[0x20];
8199
8200         u8         log_mcda_word_size[0x4];
8201         u8         reserved_at_64[0xc];
8202         u8         mcda_max_write_size[0x10];
8203
8204         u8         rd_en[0x1];
8205         u8         reserved_at_81[0x1];
8206         u8         match_chip_id[0x1];
8207         u8         match_psid[0x1];
8208         u8         check_user_timestamp[0x1];
8209         u8         match_base_guid_mac[0x1];
8210         u8         reserved_at_86[0x1a];
8211 };
8212
8213 struct mlx5_ifc_mcqi_reg_bits {
8214         u8         read_pending_component[0x1];
8215         u8         reserved_at_1[0xf];
8216         u8         component_index[0x10];
8217
8218         u8         reserved_at_20[0x20];
8219
8220         u8         reserved_at_40[0x1b];
8221         u8         info_type[0x5];
8222
8223         u8         info_size[0x20];
8224
8225         u8         offset[0x20];
8226
8227         u8         reserved_at_a0[0x10];
8228         u8         data_size[0x10];
8229
8230         u8         data[0][0x20];
8231 };
8232
8233 struct mlx5_ifc_mcc_reg_bits {
8234         u8         reserved_at_0[0x4];
8235         u8         time_elapsed_since_last_cmd[0xc];
8236         u8         reserved_at_10[0x8];
8237         u8         instruction[0x8];
8238
8239         u8         reserved_at_20[0x10];
8240         u8         component_index[0x10];
8241
8242         u8         reserved_at_40[0x8];
8243         u8         update_handle[0x18];
8244
8245         u8         handle_owner_type[0x4];
8246         u8         handle_owner_host_id[0x4];
8247         u8         reserved_at_68[0x1];
8248         u8         control_progress[0x7];
8249         u8         error_code[0x8];
8250         u8         reserved_at_78[0x4];
8251         u8         control_state[0x4];
8252
8253         u8         component_size[0x20];
8254
8255         u8         reserved_at_a0[0x60];
8256 };
8257
8258 struct mlx5_ifc_mcda_reg_bits {
8259         u8         reserved_at_0[0x8];
8260         u8         update_handle[0x18];
8261
8262         u8         offset[0x20];
8263
8264         u8         reserved_at_40[0x10];
8265         u8         size[0x10];
8266
8267         u8         reserved_at_60[0x20];
8268
8269         u8         data[0][0x20];
8270 };
8271
8272 union mlx5_ifc_ports_control_registers_document_bits {
8273         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8274         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8275         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8276         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8277         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8278         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8279         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8280         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8281         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8282         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8283         struct mlx5_ifc_paos_reg_bits paos_reg;
8284         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8285         struct mlx5_ifc_peir_reg_bits peir_reg;
8286         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8287         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8288         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8289         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8290         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8291         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8292         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8293         struct mlx5_ifc_plib_reg_bits plib_reg;
8294         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8295         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8296         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8297         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8298         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8299         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8300         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8301         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8302         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8303         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8304         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8305         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8306         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8307         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8308         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8309         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8310         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8311         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8312         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8313         struct mlx5_ifc_pude_reg_bits pude_reg;
8314         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8315         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8316         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8317         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8318         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8319         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8320         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8321         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8322         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8323         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8324         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8325         u8         reserved_at_0[0x60e0];
8326 };
8327
8328 union mlx5_ifc_debug_enhancements_document_bits {
8329         struct mlx5_ifc_health_buffer_bits health_buffer;
8330         u8         reserved_at_0[0x200];
8331 };
8332
8333 union mlx5_ifc_uplink_pci_interface_document_bits {
8334         struct mlx5_ifc_initial_seg_bits initial_seg;
8335         u8         reserved_at_0[0x20060];
8336 };
8337
8338 struct mlx5_ifc_set_flow_table_root_out_bits {
8339         u8         status[0x8];
8340         u8         reserved_at_8[0x18];
8341
8342         u8         syndrome[0x20];
8343
8344         u8         reserved_at_40[0x40];
8345 };
8346
8347 struct mlx5_ifc_set_flow_table_root_in_bits {
8348         u8         opcode[0x10];
8349         u8         reserved_at_10[0x10];
8350
8351         u8         reserved_at_20[0x10];
8352         u8         op_mod[0x10];
8353
8354         u8         other_vport[0x1];
8355         u8         reserved_at_41[0xf];
8356         u8         vport_number[0x10];
8357
8358         u8         reserved_at_60[0x20];
8359
8360         u8         table_type[0x8];
8361         u8         reserved_at_88[0x18];
8362
8363         u8         reserved_at_a0[0x8];
8364         u8         table_id[0x18];
8365
8366         u8         reserved_at_c0[0x8];
8367         u8         underlay_qpn[0x18];
8368         u8         reserved_at_e0[0x120];
8369 };
8370
8371 enum {
8372         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8373         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8374 };
8375
8376 struct mlx5_ifc_modify_flow_table_out_bits {
8377         u8         status[0x8];
8378         u8         reserved_at_8[0x18];
8379
8380         u8         syndrome[0x20];
8381
8382         u8         reserved_at_40[0x40];
8383 };
8384
8385 struct mlx5_ifc_modify_flow_table_in_bits {
8386         u8         opcode[0x10];
8387         u8         reserved_at_10[0x10];
8388
8389         u8         reserved_at_20[0x10];
8390         u8         op_mod[0x10];
8391
8392         u8         other_vport[0x1];
8393         u8         reserved_at_41[0xf];
8394         u8         vport_number[0x10];
8395
8396         u8         reserved_at_60[0x10];
8397         u8         modify_field_select[0x10];
8398
8399         u8         table_type[0x8];
8400         u8         reserved_at_88[0x18];
8401
8402         u8         reserved_at_a0[0x8];
8403         u8         table_id[0x18];
8404
8405         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8406 };
8407
8408 struct mlx5_ifc_ets_tcn_config_reg_bits {
8409         u8         g[0x1];
8410         u8         b[0x1];
8411         u8         r[0x1];
8412         u8         reserved_at_3[0x9];
8413         u8         group[0x4];
8414         u8         reserved_at_10[0x9];
8415         u8         bw_allocation[0x7];
8416
8417         u8         reserved_at_20[0xc];
8418         u8         max_bw_units[0x4];
8419         u8         reserved_at_30[0x8];
8420         u8         max_bw_value[0x8];
8421 };
8422
8423 struct mlx5_ifc_ets_global_config_reg_bits {
8424         u8         reserved_at_0[0x2];
8425         u8         r[0x1];
8426         u8         reserved_at_3[0x1d];
8427
8428         u8         reserved_at_20[0xc];
8429         u8         max_bw_units[0x4];
8430         u8         reserved_at_30[0x8];
8431         u8         max_bw_value[0x8];
8432 };
8433
8434 struct mlx5_ifc_qetc_reg_bits {
8435         u8                                         reserved_at_0[0x8];
8436         u8                                         port_number[0x8];
8437         u8                                         reserved_at_10[0x30];
8438
8439         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8440         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8441 };
8442
8443 struct mlx5_ifc_qtct_reg_bits {
8444         u8         reserved_at_0[0x8];
8445         u8         port_number[0x8];
8446         u8         reserved_at_10[0xd];
8447         u8         prio[0x3];
8448
8449         u8         reserved_at_20[0x1d];
8450         u8         tclass[0x3];
8451 };
8452
8453 struct mlx5_ifc_mcia_reg_bits {
8454         u8         l[0x1];
8455         u8         reserved_at_1[0x7];
8456         u8         module[0x8];
8457         u8         reserved_at_10[0x8];
8458         u8         status[0x8];
8459
8460         u8         i2c_device_address[0x8];
8461         u8         page_number[0x8];
8462         u8         device_address[0x10];
8463
8464         u8         reserved_at_40[0x10];
8465         u8         size[0x10];
8466
8467         u8         reserved_at_60[0x20];
8468
8469         u8         dword_0[0x20];
8470         u8         dword_1[0x20];
8471         u8         dword_2[0x20];
8472         u8         dword_3[0x20];
8473         u8         dword_4[0x20];
8474         u8         dword_5[0x20];
8475         u8         dword_6[0x20];
8476         u8         dword_7[0x20];
8477         u8         dword_8[0x20];
8478         u8         dword_9[0x20];
8479         u8         dword_10[0x20];
8480         u8         dword_11[0x20];
8481 };
8482
8483 struct mlx5_ifc_dcbx_param_bits {
8484         u8         dcbx_cee_cap[0x1];
8485         u8         dcbx_ieee_cap[0x1];
8486         u8         dcbx_standby_cap[0x1];
8487         u8         reserved_at_0[0x5];
8488         u8         port_number[0x8];
8489         u8         reserved_at_10[0xa];
8490         u8         max_application_table_size[6];
8491         u8         reserved_at_20[0x15];
8492         u8         version_oper[0x3];
8493         u8         reserved_at_38[5];
8494         u8         version_admin[0x3];
8495         u8         willing_admin[0x1];
8496         u8         reserved_at_41[0x3];
8497         u8         pfc_cap_oper[0x4];
8498         u8         reserved_at_48[0x4];
8499         u8         pfc_cap_admin[0x4];
8500         u8         reserved_at_50[0x4];
8501         u8         num_of_tc_oper[0x4];
8502         u8         reserved_at_58[0x4];
8503         u8         num_of_tc_admin[0x4];
8504         u8         remote_willing[0x1];
8505         u8         reserved_at_61[3];
8506         u8         remote_pfc_cap[4];
8507         u8         reserved_at_68[0x14];
8508         u8         remote_num_of_tc[0x4];
8509         u8         reserved_at_80[0x18];
8510         u8         error[0x8];
8511         u8         reserved_at_a0[0x160];
8512 };
8513
8514 struct mlx5_ifc_lagc_bits {
8515         u8         reserved_at_0[0x1d];
8516         u8         lag_state[0x3];
8517
8518         u8         reserved_at_20[0x14];
8519         u8         tx_remap_affinity_2[0x4];
8520         u8         reserved_at_38[0x4];
8521         u8         tx_remap_affinity_1[0x4];
8522 };
8523
8524 struct mlx5_ifc_create_lag_out_bits {
8525         u8         status[0x8];
8526         u8         reserved_at_8[0x18];
8527
8528         u8         syndrome[0x20];
8529
8530         u8         reserved_at_40[0x40];
8531 };
8532
8533 struct mlx5_ifc_create_lag_in_bits {
8534         u8         opcode[0x10];
8535         u8         reserved_at_10[0x10];
8536
8537         u8         reserved_at_20[0x10];
8538         u8         op_mod[0x10];
8539
8540         struct mlx5_ifc_lagc_bits ctx;
8541 };
8542
8543 struct mlx5_ifc_modify_lag_out_bits {
8544         u8         status[0x8];
8545         u8         reserved_at_8[0x18];
8546
8547         u8         syndrome[0x20];
8548
8549         u8         reserved_at_40[0x40];
8550 };
8551
8552 struct mlx5_ifc_modify_lag_in_bits {
8553         u8         opcode[0x10];
8554         u8         reserved_at_10[0x10];
8555
8556         u8         reserved_at_20[0x10];
8557         u8         op_mod[0x10];
8558
8559         u8         reserved_at_40[0x20];
8560         u8         field_select[0x20];
8561
8562         struct mlx5_ifc_lagc_bits ctx;
8563 };
8564
8565 struct mlx5_ifc_query_lag_out_bits {
8566         u8         status[0x8];
8567         u8         reserved_at_8[0x18];
8568
8569         u8         syndrome[0x20];
8570
8571         u8         reserved_at_40[0x40];
8572
8573         struct mlx5_ifc_lagc_bits ctx;
8574 };
8575
8576 struct mlx5_ifc_query_lag_in_bits {
8577         u8         opcode[0x10];
8578         u8         reserved_at_10[0x10];
8579
8580         u8         reserved_at_20[0x10];
8581         u8         op_mod[0x10];
8582
8583         u8         reserved_at_40[0x40];
8584 };
8585
8586 struct mlx5_ifc_destroy_lag_out_bits {
8587         u8         status[0x8];
8588         u8         reserved_at_8[0x18];
8589
8590         u8         syndrome[0x20];
8591
8592         u8         reserved_at_40[0x40];
8593 };
8594
8595 struct mlx5_ifc_destroy_lag_in_bits {
8596         u8         opcode[0x10];
8597         u8         reserved_at_10[0x10];
8598
8599         u8         reserved_at_20[0x10];
8600         u8         op_mod[0x10];
8601
8602         u8         reserved_at_40[0x40];
8603 };
8604
8605 struct mlx5_ifc_create_vport_lag_out_bits {
8606         u8         status[0x8];
8607         u8         reserved_at_8[0x18];
8608
8609         u8         syndrome[0x20];
8610
8611         u8         reserved_at_40[0x40];
8612 };
8613
8614 struct mlx5_ifc_create_vport_lag_in_bits {
8615         u8         opcode[0x10];
8616         u8         reserved_at_10[0x10];
8617
8618         u8         reserved_at_20[0x10];
8619         u8         op_mod[0x10];
8620
8621         u8         reserved_at_40[0x40];
8622 };
8623
8624 struct mlx5_ifc_destroy_vport_lag_out_bits {
8625         u8         status[0x8];
8626         u8         reserved_at_8[0x18];
8627
8628         u8         syndrome[0x20];
8629
8630         u8         reserved_at_40[0x40];
8631 };
8632
8633 struct mlx5_ifc_destroy_vport_lag_in_bits {
8634         u8         opcode[0x10];
8635         u8         reserved_at_10[0x10];
8636
8637         u8         reserved_at_20[0x10];
8638         u8         op_mod[0x10];
8639
8640         u8         reserved_at_40[0x40];
8641 };
8642
8643 #endif /* MLX5_IFC_H */