include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         atomic[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         vlan_tag[0x1];
 369         u8         reserved_at_91[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_vlan_tag[0x1];
 402         u8         inner_second_vlan_tag[0x1];
 403         u8         reserved_at_62[0xe];
 404         u8         gre_protocol[0x10];
 405
 406         u8         gre_key_h[0x18];
 407         u8         gre_key_l[0x8];
 408
 409         u8         vxlan_vni[0x18];
 410         u8         reserved_at_b8[0x8];
 411
 412         u8         reserved_at_c0[0x20];
 413
 414         u8         reserved_at_e0[0xc];
 415         u8         outer_ipv6_flow_label[0x14];
 416
 417         u8         reserved_at_100[0xc];
 418         u8         inner_ipv6_flow_label[0x14];
 419
 420         u8         reserved_at_120[0xe0];
 421 };
 422
 423 struct mlx5_ifc_cmd_pas_bits {
 424         u8         pa_h[0x20];
 425
 426         u8         pa_l[0x14];
 427         u8         reserved_at_34[0xc];
 428 };
 429
 430 struct mlx5_ifc_uint64_bits {
 431         u8         hi[0x20];
 432
 433         u8         lo[0x20];
 434 };
 435
 436 enum {
 437         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 438         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 439         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 440         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 441         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 442         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 443         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 444         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 445         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 446         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 447 };
 448
 449 struct mlx5_ifc_ads_bits {
 450         u8         fl[0x1];
 451         u8         free_ar[0x1];
 452         u8         reserved_at_2[0xe];
 453         u8         pkey_index[0x10];
 454
 455         u8         reserved_at_20[0x8];
 456         u8         grh[0x1];
 457         u8         mlid[0x7];
 458         u8         rlid[0x10];
 459
 460         u8         ack_timeout[0x5];
 461         u8         reserved_at_45[0x3];
 462         u8         src_addr_index[0x8];
 463         u8         reserved_at_50[0x4];
 464         u8         stat_rate[0x4];
 465         u8         hop_limit[0x8];
 466
 467         u8         reserved_at_60[0x4];
 468         u8         tclass[0x8];
 469         u8         flow_label[0x14];
 470
 471         u8         rgid_rip[16][0x8];
 472
 473         u8         reserved_at_100[0x4];
 474         u8         f_dscp[0x1];
 475         u8         f_ecn[0x1];
 476         u8         reserved_at_106[0x1];
 477         u8         f_eth_prio[0x1];
 478         u8         ecn[0x2];
 479         u8         dscp[0x6];
 480         u8         udp_sport[0x10];
 481
 482         u8         dei_cfi[0x1];
 483         u8         eth_prio[0x3];
 484         u8         sl[0x4];
 485         u8         port[0x8];
 486         u8         rmac_47_32[0x10];
 487
 488         u8         rmac_31_0[0x20];
 489 };
 490
 491 struct mlx5_ifc_flow_table_nic_cap_bits {
 492         u8         nic_rx_multi_path_tirs[0x1];
 493         u8         nic_rx_multi_path_tirs_fts[0x1];
 494         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 495         u8         reserved_at_3[0x1fd];
 496
 497         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 498
 499         u8         reserved_at_400[0x200];
 500
 501         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 504
 505         u8         reserved_at_a00[0x200];
 506
 507         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 508
 509         u8         reserved_at_e00[0x7200];
 510 };
 511
 512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 513         u8     reserved_at_0[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 520
 521         u8      reserved_at_800[0x7800];
 522 };
 523
 524 struct mlx5_ifc_e_switch_cap_bits {
 525         u8         vport_svlan_strip[0x1];
 526         u8         vport_cvlan_strip[0x1];
 527         u8         vport_svlan_insert[0x1];
 528         u8         vport_cvlan_insert_if_not_exist[0x1];
 529         u8         vport_cvlan_insert_overwrite[0x1];
 530         u8         reserved_at_5[0x19];
 531         u8         nic_vport_node_guid_modify[0x1];
 532         u8         nic_vport_port_guid_modify[0x1];
 533
 534         u8         vxlan_encap_decap[0x1];
 535         u8         nvgre_encap_decap[0x1];
 536         u8         reserved_at_22[0x9];
 537         u8         log_max_encap_headers[0x5];
 538         u8         reserved_2b[0x6];
 539         u8         max_encap_header_size[0xa];
 540
 541         u8         reserved_40[0x7c0];
 542
 543 };
 544
 545 struct mlx5_ifc_qos_cap_bits {
 546         u8         packet_pacing[0x1];
 547         u8         esw_scheduling[0x1];
 548         u8         reserved_at_2[0x1e];
 549
 550         u8         reserved_at_20[0x20];
 551
 552         u8         packet_pacing_max_rate[0x20];
 553
 554         u8         packet_pacing_min_rate[0x20];
 555
 556         u8         reserved_at_80[0x10];
 557         u8         packet_pacing_rate_table_size[0x10];
 558
 559         u8         esw_element_type[0x10];
 560         u8         esw_tsar_type[0x10];
 561
 562         u8         reserved_at_c0[0x10];
 563         u8         max_qos_para_vport[0x10];
 564
 565         u8         max_tsar_bw_share[0x20];
 566
 567         u8         reserved_at_100[0x700];
 568 };
 569
 570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 571         u8         csum_cap[0x1];
 572         u8         vlan_cap[0x1];
 573         u8         lro_cap[0x1];
 574         u8         lro_psh_flag[0x1];
 575         u8         lro_time_stamp[0x1];
 576         u8         reserved_at_5[0x3];
 577         u8         self_lb_en_modifiable[0x1];
 578         u8         reserved_at_9[0x2];
 579         u8         max_lso_cap[0x5];
 580         u8         multi_pkt_send_wqe[0x2];
 581         u8         wqe_inline_mode[0x2];
 582         u8         rss_ind_tbl_cap[0x4];
 583         u8         reg_umr_sq[0x1];
 584         u8         scatter_fcs[0x1];
 585         u8         reserved_at_1a[0x1];
 586         u8         tunnel_lso_const_out_ip_id[0x1];
 587         u8         reserved_at_1c[0x2];
 588         u8         tunnel_statless_gre[0x1];
 589         u8         tunnel_stateless_vxlan[0x1];
 590
 591         u8         reserved_at_20[0x20];
 592
 593         u8         reserved_at_40[0x10];
 594         u8         lro_min_mss_size[0x10];
 595
 596         u8         reserved_at_60[0x120];
 597
 598         u8         lro_timer_supported_periods[4][0x20];
 599
 600         u8         reserved_at_200[0x600];
 601 };
 602
 603 struct mlx5_ifc_roce_cap_bits {
 604         u8         roce_apm[0x1];
 605         u8         reserved_at_1[0x1f];
 606
 607         u8         reserved_at_20[0x60];
 608
 609         u8         reserved_at_80[0xc];
 610         u8         l3_type[0x4];
 611         u8         reserved_at_90[0x8];
 612         u8         roce_version[0x8];
 613
 614         u8         reserved_at_a0[0x10];
 615         u8         r_roce_dest_udp_port[0x10];
 616
 617         u8         r_roce_max_src_udp_port[0x10];
 618         u8         r_roce_min_src_udp_port[0x10];
 619
 620         u8         reserved_at_e0[0x10];
 621         u8         roce_address_table_size[0x10];
 622
 623         u8         reserved_at_100[0x700];
 624 };
 625
 626 enum {
 627         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 628         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 636 };
 637
 638 enum {
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 648 };
 649
 650 struct mlx5_ifc_atomic_caps_bits {
 651         u8         reserved_at_0[0x40];
 652
 653         u8         atomic_req_8B_endianess_mode[0x2];
 654         u8         reserved_at_42[0x4];
 655         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 656
 657         u8         reserved_at_47[0x19];
 658
 659         u8         reserved_at_60[0x20];
 660
 661         u8         reserved_at_80[0x10];
 662         u8         atomic_operations[0x10];
 663
 664         u8         reserved_at_a0[0x10];
 665         u8         atomic_size_qp[0x10];
 666
 667         u8         reserved_at_c0[0x10];
 668         u8         atomic_size_dc[0x10];
 669
 670         u8         reserved_at_e0[0x720];
 671 };
 672
 673 struct mlx5_ifc_odp_cap_bits {
 674         u8         reserved_at_0[0x40];
 675
 676         u8         sig[0x1];
 677         u8         reserved_at_41[0x1f];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 682
 683         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 686
 687         u8         reserved_at_e0[0x720];
 688 };
 689
 690 struct mlx5_ifc_calc_op {
 691         u8        reserved_at_0[0x10];
 692         u8        reserved_at_10[0x9];
 693         u8        op_swap_endianness[0x1];
 694         u8        op_min[0x1];
 695         u8        op_xor[0x1];
 696         u8        op_or[0x1];
 697         u8        op_and[0x1];
 698         u8        op_max[0x1];
 699         u8        op_add[0x1];
 700 };
 701
 702 struct mlx5_ifc_vector_calc_cap_bits {
 703         u8         calc_matrix[0x1];
 704         u8         reserved_at_1[0x1f];
 705         u8         reserved_at_20[0x8];
 706         u8         max_vec_count[0x8];
 707         u8         reserved_at_30[0xd];
 708         u8         max_chunk_size[0x3];
 709         struct mlx5_ifc_calc_op calc0;
 710         struct mlx5_ifc_calc_op calc1;
 711         struct mlx5_ifc_calc_op calc2;
 712         struct mlx5_ifc_calc_op calc3;
 713
 714         u8         reserved_at_e0[0x720];
 715 };
 716
 717 enum {
 718         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 719         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 720         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 721 };
 722
 723 enum {
 724         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 725         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 726 };
 727
 728 enum {
 729         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 730         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 734 };
 735
 736 enum {
 737         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 738         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 743 };
 744
 745 enum {
 746         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 747         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 748 };
 749
 750 enum {
 751         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 752         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 754 };
 755
 756 enum {
 757         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 758         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 759 };
 760
 761 struct mlx5_ifc_cmd_hca_cap_bits {
 762         u8         reserved_at_0[0x80];
 763
 764         u8         log_max_srq_sz[0x8];
 765         u8         log_max_qp_sz[0x8];
 766         u8         reserved_at_90[0xb];
 767         u8         log_max_qp[0x5];
 768
 769         u8         reserved_at_a0[0xb];
 770         u8         log_max_srq[0x5];
 771         u8         reserved_at_b0[0x10];
 772
 773         u8         reserved_at_c0[0x8];
 774         u8         log_max_cq_sz[0x8];
 775         u8         reserved_at_d0[0xb];
 776         u8         log_max_cq[0x5];
 777
 778         u8         log_max_eq_sz[0x8];
 779         u8         reserved_at_e8[0x2];
 780         u8         log_max_mkey[0x6];
 781         u8         reserved_at_f0[0xc];
 782         u8         log_max_eq[0x4];
 783
 784         u8         max_indirection[0x8];
 785         u8         fixed_buffer_size[0x1];
 786         u8         log_max_mrw_sz[0x7];
 787         u8         reserved_at_110[0x2];
 788         u8         log_max_bsf_list_size[0x6];
 789         u8         umr_extended_translation_offset[0x1];
 790         u8         null_mkey[0x1];
 791         u8         log_max_klm_list_size[0x6];
 792
 793         u8         reserved_at_120[0xa];
 794         u8         log_max_ra_req_dc[0x6];
 795         u8         reserved_at_130[0xa];
 796         u8         log_max_ra_res_dc[0x6];
 797
 798         u8         reserved_at_140[0xa];
 799         u8         log_max_ra_req_qp[0x6];
 800         u8         reserved_at_150[0xa];
 801         u8         log_max_ra_res_qp[0x6];
 802
 803         u8         pad_cap[0x1];
 804         u8         cc_query_allowed[0x1];
 805         u8         cc_modify_allowed[0x1];
 806         u8         reserved_at_163[0xd];
 807         u8         gid_table_size[0x10];
 808
 809         u8         out_of_seq_cnt[0x1];
 810         u8         vport_counters[0x1];
 811         u8         retransmission_q_counters[0x1];
 812         u8         reserved_at_183[0x1];
 813         u8         modify_rq_counter_set_id[0x1];
 814         u8         reserved_at_185[0x1];
 815         u8         max_qp_cnt[0xa];
 816         u8         pkey_table_size[0x10];
 817
 818         u8         vport_group_manager[0x1];
 819         u8         vhca_group_manager[0x1];
 820         u8         ib_virt[0x1];
 821         u8         eth_virt[0x1];
 822         u8         reserved_at_1a4[0x1];
 823         u8         ets[0x1];
 824         u8         nic_flow_table[0x1];
 825         u8         eswitch_flow_table[0x1];
 826         u8         early_vf_enable[0x1];
 827         u8         reserved_at_1a9[0x2];
 828         u8         local_ca_ack_delay[0x5];
 829         u8         port_module_event[0x1];
 830         u8         reserved_at_1b1[0x1];
 831         u8         ports_check[0x1];
 832         u8         reserved_at_1b3[0x1];
 833         u8         disable_link_up[0x1];
 834         u8         beacon_led[0x1];
 835         u8         port_type[0x2];
 836         u8         num_ports[0x8];
 837
 838         u8         reserved_at_1c0[0x3];
 839         u8         log_max_msg[0x5];
 840         u8         reserved_at_1c8[0x4];
 841         u8         max_tc[0x4];
 842         u8         reserved_at_1d0[0x1];
 843         u8         dcbx[0x1];
 844         u8         reserved_at_1d2[0x4];
 845         u8         rol_s[0x1];
 846         u8         rol_g[0x1];
 847         u8         reserved_at_1d8[0x1];
 848         u8         wol_s[0x1];
 849         u8         wol_g[0x1];
 850         u8         wol_a[0x1];
 851         u8         wol_b[0x1];
 852         u8         wol_m[0x1];
 853         u8         wol_u[0x1];
 854         u8         wol_p[0x1];
 855
 856         u8         stat_rate_support[0x10];
 857         u8         reserved_at_1f0[0xc];
 858         u8         cqe_version[0x4];
 859
 860         u8         compact_address_vector[0x1];
 861         u8         striding_rq[0x1];
 862         u8         reserved_at_202[0x2];
 863         u8         ipoib_basic_offloads[0x1];
 864         u8         reserved_at_205[0xa];
 865         u8         drain_sigerr[0x1];
 866         u8         cmdif_checksum[0x2];
 867         u8         sigerr_cqe[0x1];
 868         u8         reserved_at_213[0x1];
 869         u8         wq_signature[0x1];
 870         u8         sctr_data_cqe[0x1];
 871         u8         reserved_at_216[0x1];
 872         u8         sho[0x1];
 873         u8         tph[0x1];
 874         u8         rf[0x1];
 875         u8         dct[0x1];
 876         u8         qos[0x1];
 877         u8         eth_net_offloads[0x1];
 878         u8         roce[0x1];
 879         u8         atomic[0x1];
 880         u8         reserved_at_21f[0x1];
 881
 882         u8         cq_oi[0x1];
 883         u8         cq_resize[0x1];
 884         u8         cq_moderation[0x1];
 885         u8         reserved_at_223[0x3];
 886         u8         cq_eq_remap[0x1];
 887         u8         pg[0x1];
 888         u8         block_lb_mc[0x1];
 889         u8         reserved_at_229[0x1];
 890         u8         scqe_break_moderation[0x1];
 891         u8         cq_period_start_from_cqe[0x1];
 892         u8         cd[0x1];
 893         u8         reserved_at_22d[0x1];
 894         u8         apm[0x1];
 895         u8         vector_calc[0x1];
 896         u8         umr_ptr_rlky[0x1];
 897         u8         imaicl[0x1];
 898         u8         reserved_at_232[0x4];
 899         u8         qkv[0x1];
 900         u8         pkv[0x1];
 901         u8         set_deth_sqpn[0x1];
 902         u8         reserved_at_239[0x3];
 903         u8         xrc[0x1];
 904         u8         ud[0x1];
 905         u8         uc[0x1];
 906         u8         rc[0x1];
 907
 908         u8         uar_4k[0x1];
 909         u8         reserved_at_241[0x9];
 910         u8         uar_sz[0x6];
 911         u8         reserved_at_250[0x8];
 912         u8         log_pg_sz[0x8];
 913
 914         u8         bf[0x1];
 915         u8         driver_version[0x1];
 916         u8         pad_tx_eth_packet[0x1];
 917         u8         reserved_at_263[0x8];
 918         u8         log_bf_reg_size[0x5];
 919
 920         u8         reserved_at_270[0xb];
 921         u8         lag_master[0x1];
 922         u8         num_lag_ports[0x4];
 923
 924         u8         reserved_at_280[0x10];
 925         u8         max_wqe_sz_sq[0x10];
 926
 927         u8         reserved_at_2a0[0x10];
 928         u8         max_wqe_sz_rq[0x10];
 929
 930         u8         reserved_at_2c0[0x10];
 931         u8         max_wqe_sz_sq_dc[0x10];
 932
 933         u8         reserved_at_2e0[0x7];
 934         u8         max_qp_mcg[0x19];
 935
 936         u8         reserved_at_300[0x18];
 937         u8         log_max_mcg[0x8];
 938
 939         u8         reserved_at_320[0x3];
 940         u8         log_max_transport_domain[0x5];
 941         u8         reserved_at_328[0x3];
 942         u8         log_max_pd[0x5];
 943         u8         reserved_at_330[0xb];
 944         u8         log_max_xrcd[0x5];
 945
 946         u8         reserved_at_340[0x8];
 947         u8         log_max_flow_counter_bulk[0x8];
 948         u8         max_flow_counter[0x10];
 949
 950
 951         u8         reserved_at_360[0x3];
 952         u8         log_max_rq[0x5];
 953         u8         reserved_at_368[0x3];
 954         u8         log_max_sq[0x5];
 955         u8         reserved_at_370[0x3];
 956         u8         log_max_tir[0x5];
 957         u8         reserved_at_378[0x3];
 958         u8         log_max_tis[0x5];
 959
 960         u8         basic_cyclic_rcv_wqe[0x1];
 961         u8         reserved_at_381[0x2];
 962         u8         log_max_rmp[0x5];
 963         u8         reserved_at_388[0x3];
 964         u8         log_max_rqt[0x5];
 965         u8         reserved_at_390[0x3];
 966         u8         log_max_rqt_size[0x5];
 967         u8         reserved_at_398[0x3];
 968         u8         log_max_tis_per_sq[0x5];
 969
 970         u8         reserved_at_3a0[0x3];
 971         u8         log_max_stride_sz_rq[0x5];
 972         u8         reserved_at_3a8[0x3];
 973         u8         log_min_stride_sz_rq[0x5];
 974         u8         reserved_at_3b0[0x3];
 975         u8         log_max_stride_sz_sq[0x5];
 976         u8         reserved_at_3b8[0x3];
 977         u8         log_min_stride_sz_sq[0x5];
 978
 979         u8         reserved_at_3c0[0x1b];
 980         u8         log_max_wq_sz[0x5];
 981
 982         u8         nic_vport_change_event[0x1];
 983         u8         reserved_at_3e1[0xa];
 984         u8         log_max_vlan_list[0x5];
 985         u8         reserved_at_3f0[0x3];
 986         u8         log_max_current_mc_list[0x5];
 987         u8         reserved_at_3f8[0x3];
 988         u8         log_max_current_uc_list[0x5];
 989
 990         u8         reserved_at_400[0x80];
 991
 992         u8         reserved_at_480[0x3];
 993         u8         log_max_l2_table[0x5];
 994         u8         reserved_at_488[0x8];
 995         u8         log_uar_page_sz[0x10];
 996
 997         u8         reserved_at_4a0[0x20];
 998         u8         device_frequency_mhz[0x20];
 999         u8         device_frequency_khz[0x20];
1000
1001         u8         reserved_at_500[0x20];
1002         u8         num_of_uars_per_page[0x20];
1003         u8         reserved_at_540[0x40];
1004
1005         u8         reserved_at_580[0x3f];
1006         u8         cqe_compression[0x1];
1007
1008         u8         cqe_compression_timeout[0x10];
1009         u8         cqe_compression_max_num[0x10];
1010
1011         u8         reserved_at_5e0[0x10];
1012         u8         tag_matching[0x1];
1013         u8         rndv_offload_rc[0x1];
1014         u8         rndv_offload_dc[0x1];
1015         u8         log_tag_matching_list_sz[0x5];
1016         u8         reserved_at_5f8[0x3];
1017         u8         log_max_xrq[0x5];
1018
1019         u8         reserved_at_600[0x200];
1020 };
1021
1022 enum mlx5_flow_destination_type {
1023         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1024         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1025         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1026
1027         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1028 };
1029
1030 struct mlx5_ifc_dest_format_struct_bits {
1031         u8         destination_type[0x8];
1032         u8         destination_id[0x18];
1033
1034         u8         reserved_at_20[0x20];
1035 };
1036
1037 struct mlx5_ifc_flow_counter_list_bits {
1038         u8         clear[0x1];
1039         u8         num_of_counters[0xf];
1040         u8         flow_counter_id[0x10];
1041
1042         u8         reserved_at_20[0x20];
1043 };
1044
1045 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1046         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1047         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1048         u8         reserved_at_0[0x40];
1049 };
1050
1051 struct mlx5_ifc_fte_match_param_bits {
1052         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1053
1054         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1055
1056         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1057
1058         u8         reserved_at_600[0xa00];
1059 };
1060
1061 enum {
1062         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1063         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1064         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1065         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1066         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1067 };
1068
1069 struct mlx5_ifc_rx_hash_field_select_bits {
1070         u8         l3_prot_type[0x1];
1071         u8         l4_prot_type[0x1];
1072         u8         selected_fields[0x1e];
1073 };
1074
1075 enum {
1076         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1077         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1078 };
1079
1080 enum {
1081         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1082         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1083 };
1084
1085 struct mlx5_ifc_wq_bits {
1086         u8         wq_type[0x4];
1087         u8         wq_signature[0x1];
1088         u8         end_padding_mode[0x2];
1089         u8         cd_slave[0x1];
1090         u8         reserved_at_8[0x18];
1091
1092         u8         hds_skip_first_sge[0x1];
1093         u8         log2_hds_buf_size[0x3];
1094         u8         reserved_at_24[0x7];
1095         u8         page_offset[0x5];
1096         u8         lwm[0x10];
1097
1098         u8         reserved_at_40[0x8];
1099         u8         pd[0x18];
1100
1101         u8         reserved_at_60[0x8];
1102         u8         uar_page[0x18];
1103
1104         u8         dbr_addr[0x40];
1105
1106         u8         hw_counter[0x20];
1107
1108         u8         sw_counter[0x20];
1109
1110         u8         reserved_at_100[0xc];
1111         u8         log_wq_stride[0x4];
1112         u8         reserved_at_110[0x3];
1113         u8         log_wq_pg_sz[0x5];
1114         u8         reserved_at_118[0x3];
1115         u8         log_wq_sz[0x5];
1116
1117         u8         reserved_at_120[0x15];
1118         u8         log_wqe_num_of_strides[0x3];
1119         u8         two_byte_shift_en[0x1];
1120         u8         reserved_at_139[0x4];
1121         u8         log_wqe_stride_size[0x3];
1122
1123         u8         reserved_at_140[0x4c0];
1124
1125         struct mlx5_ifc_cmd_pas_bits pas[0];
1126 };
1127
1128 struct mlx5_ifc_rq_num_bits {
1129         u8         reserved_at_0[0x8];
1130         u8         rq_num[0x18];
1131 };
1132
1133 struct mlx5_ifc_mac_address_layout_bits {
1134         u8         reserved_at_0[0x10];
1135         u8         mac_addr_47_32[0x10];
1136
1137         u8         mac_addr_31_0[0x20];
1138 };
1139
1140 struct mlx5_ifc_vlan_layout_bits {
1141         u8         reserved_at_0[0x14];
1142         u8         vlan[0x0c];
1143
1144         u8         reserved_at_20[0x20];
1145 };
1146
1147 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1148         u8         reserved_at_0[0xa0];
1149
1150         u8         min_time_between_cnps[0x20];
1151
1152         u8         reserved_at_c0[0x12];
1153         u8         cnp_dscp[0x6];
1154         u8         reserved_at_d8[0x5];
1155         u8         cnp_802p_prio[0x3];
1156
1157         u8         reserved_at_e0[0x720];
1158 };
1159
1160 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1161         u8         reserved_at_0[0x60];
1162
1163         u8         reserved_at_60[0x4];
1164         u8         clamp_tgt_rate[0x1];
1165         u8         reserved_at_65[0x3];
1166         u8         clamp_tgt_rate_after_time_inc[0x1];
1167         u8         reserved_at_69[0x17];
1168
1169         u8         reserved_at_80[0x20];
1170
1171         u8         rpg_time_reset[0x20];
1172
1173         u8         rpg_byte_reset[0x20];
1174
1175         u8         rpg_threshold[0x20];
1176
1177         u8         rpg_max_rate[0x20];
1178
1179         u8         rpg_ai_rate[0x20];
1180
1181         u8         rpg_hai_rate[0x20];
1182
1183         u8         rpg_gd[0x20];
1184
1185         u8         rpg_min_dec_fac[0x20];
1186
1187         u8         rpg_min_rate[0x20];
1188
1189         u8         reserved_at_1c0[0xe0];
1190
1191         u8         rate_to_set_on_first_cnp[0x20];
1192
1193         u8         dce_tcp_g[0x20];
1194
1195         u8         dce_tcp_rtt[0x20];
1196
1197         u8         rate_reduce_monitor_period[0x20];
1198
1199         u8         reserved_at_320[0x20];
1200
1201         u8         initial_alpha_value[0x20];
1202
1203         u8         reserved_at_360[0x4a0];
1204 };
1205
1206 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1207         u8         reserved_at_0[0x80];
1208
1209         u8         rppp_max_rps[0x20];
1210
1211         u8         rpg_time_reset[0x20];
1212
1213         u8         rpg_byte_reset[0x20];
1214
1215         u8         rpg_threshold[0x20];
1216
1217         u8         rpg_max_rate[0x20];
1218
1219         u8         rpg_ai_rate[0x20];
1220
1221         u8         rpg_hai_rate[0x20];
1222
1223         u8         rpg_gd[0x20];
1224
1225         u8         rpg_min_dec_fac[0x20];
1226
1227         u8         rpg_min_rate[0x20];
1228
1229         u8         reserved_at_1c0[0x640];
1230 };
1231
1232 enum {
1233         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1234         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1235         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1236 };
1237
1238 struct mlx5_ifc_resize_field_select_bits {
1239         u8         resize_field_select[0x20];
1240 };
1241
1242 enum {
1243         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1244         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1245         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1246         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1247 };
1248
1249 struct mlx5_ifc_modify_field_select_bits {
1250         u8         modify_field_select[0x20];
1251 };
1252
1253 struct mlx5_ifc_field_select_r_roce_np_bits {
1254         u8         field_select_r_roce_np[0x20];
1255 };
1256
1257 struct mlx5_ifc_field_select_r_roce_rp_bits {
1258         u8         field_select_r_roce_rp[0x20];
1259 };
1260
1261 enum {
1262         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1268         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1269         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1270         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1272 };
1273
1274 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1275         u8         field_select_8021qaurp[0x20];
1276 };
1277
1278 struct mlx5_ifc_phys_layer_cntrs_bits {
1279         u8         time_since_last_clear_high[0x20];
1280
1281         u8         time_since_last_clear_low[0x20];
1282
1283         u8         symbol_errors_high[0x20];
1284
1285         u8         symbol_errors_low[0x20];
1286
1287         u8         sync_headers_errors_high[0x20];
1288
1289         u8         sync_headers_errors_low[0x20];
1290
1291         u8         edpl_bip_errors_lane0_high[0x20];
1292
1293         u8         edpl_bip_errors_lane0_low[0x20];
1294
1295         u8         edpl_bip_errors_lane1_high[0x20];
1296
1297         u8         edpl_bip_errors_lane1_low[0x20];
1298
1299         u8         edpl_bip_errors_lane2_high[0x20];
1300
1301         u8         edpl_bip_errors_lane2_low[0x20];
1302
1303         u8         edpl_bip_errors_lane3_high[0x20];
1304
1305         u8         edpl_bip_errors_lane3_low[0x20];
1306
1307         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1308
1309         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1310
1311         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1312
1313         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1314
1315         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1316
1317         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1318
1319         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1320
1321         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1322
1323         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1324
1325         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1326
1327         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1328
1329         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1330
1331         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1332
1333         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1334
1335         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1336
1337         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1338
1339         u8         rs_fec_corrected_blocks_high[0x20];
1340
1341         u8         rs_fec_corrected_blocks_low[0x20];
1342
1343         u8         rs_fec_uncorrectable_blocks_high[0x20];
1344
1345         u8         rs_fec_uncorrectable_blocks_low[0x20];
1346
1347         u8         rs_fec_no_errors_blocks_high[0x20];
1348
1349         u8         rs_fec_no_errors_blocks_low[0x20];
1350
1351         u8         rs_fec_single_error_blocks_high[0x20];
1352
1353         u8         rs_fec_single_error_blocks_low[0x20];
1354
1355         u8         rs_fec_corrected_symbols_total_high[0x20];
1356
1357         u8         rs_fec_corrected_symbols_total_low[0x20];
1358
1359         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1360
1361         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1362
1363         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1364
1365         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1366
1367         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1368
1369         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1370
1371         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1372
1373         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1374
1375         u8         link_down_events[0x20];
1376
1377         u8         successful_recovery_events[0x20];
1378
1379         u8         reserved_at_640[0x180];
1380 };
1381
1382 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1383         u8         symbol_error_counter[0x10];
1384
1385         u8         link_error_recovery_counter[0x8];
1386
1387         u8         link_downed_counter[0x8];
1388
1389         u8         port_rcv_errors[0x10];
1390
1391         u8         port_rcv_remote_physical_errors[0x10];
1392
1393         u8         port_rcv_switch_relay_errors[0x10];
1394
1395         u8         port_xmit_discards[0x10];
1396
1397         u8         port_xmit_constraint_errors[0x8];
1398
1399         u8         port_rcv_constraint_errors[0x8];
1400
1401         u8         reserved_at_70[0x8];
1402
1403         u8         link_overrun_errors[0x8];
1404
1405         u8         reserved_at_80[0x10];
1406
1407         u8         vl_15_dropped[0x10];
1408
1409         u8         reserved_at_a0[0xa0];
1410 };
1411
1412 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1413         u8         transmit_queue_high[0x20];
1414
1415         u8         transmit_queue_low[0x20];
1416
1417         u8         reserved_at_40[0x780];
1418 };
1419
1420 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1421         u8         rx_octets_high[0x20];
1422
1423         u8         rx_octets_low[0x20];
1424
1425         u8         reserved_at_40[0xc0];
1426
1427         u8         rx_frames_high[0x20];
1428
1429         u8         rx_frames_low[0x20];
1430
1431         u8         tx_octets_high[0x20];
1432
1433         u8         tx_octets_low[0x20];
1434
1435         u8         reserved_at_180[0xc0];
1436
1437         u8         tx_frames_high[0x20];
1438
1439         u8         tx_frames_low[0x20];
1440
1441         u8         rx_pause_high[0x20];
1442
1443         u8         rx_pause_low[0x20];
1444
1445         u8         rx_pause_duration_high[0x20];
1446
1447         u8         rx_pause_duration_low[0x20];
1448
1449         u8         tx_pause_high[0x20];
1450
1451         u8         tx_pause_low[0x20];
1452
1453         u8         tx_pause_duration_high[0x20];
1454
1455         u8         tx_pause_duration_low[0x20];
1456
1457         u8         rx_pause_transition_high[0x20];
1458
1459         u8         rx_pause_transition_low[0x20];
1460
1461         u8         reserved_at_3c0[0x400];
1462 };
1463
1464 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1465         u8         port_transmit_wait_high[0x20];
1466
1467         u8         port_transmit_wait_low[0x20];
1468
1469         u8         reserved_at_40[0x780];
1470 };
1471
1472 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1473         u8         dot3stats_alignment_errors_high[0x20];
1474
1475         u8         dot3stats_alignment_errors_low[0x20];
1476
1477         u8         dot3stats_fcs_errors_high[0x20];
1478
1479         u8         dot3stats_fcs_errors_low[0x20];
1480
1481         u8         dot3stats_single_collision_frames_high[0x20];
1482
1483         u8         dot3stats_single_collision_frames_low[0x20];
1484
1485         u8         dot3stats_multiple_collision_frames_high[0x20];
1486
1487         u8         dot3stats_multiple_collision_frames_low[0x20];
1488
1489         u8         dot3stats_sqe_test_errors_high[0x20];
1490
1491         u8         dot3stats_sqe_test_errors_low[0x20];
1492
1493         u8         dot3stats_deferred_transmissions_high[0x20];
1494
1495         u8         dot3stats_deferred_transmissions_low[0x20];
1496
1497         u8         dot3stats_late_collisions_high[0x20];
1498
1499         u8         dot3stats_late_collisions_low[0x20];
1500
1501         u8         dot3stats_excessive_collisions_high[0x20];
1502
1503         u8         dot3stats_excessive_collisions_low[0x20];
1504
1505         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1506
1507         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1508
1509         u8         dot3stats_carrier_sense_errors_high[0x20];
1510
1511         u8         dot3stats_carrier_sense_errors_low[0x20];
1512
1513         u8         dot3stats_frame_too_longs_high[0x20];
1514
1515         u8         dot3stats_frame_too_longs_low[0x20];
1516
1517         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1518
1519         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1520
1521         u8         dot3stats_symbol_errors_high[0x20];
1522
1523         u8         dot3stats_symbol_errors_low[0x20];
1524
1525         u8         dot3control_in_unknown_opcodes_high[0x20];
1526
1527         u8         dot3control_in_unknown_opcodes_low[0x20];
1528
1529         u8         dot3in_pause_frames_high[0x20];
1530
1531         u8         dot3in_pause_frames_low[0x20];
1532
1533         u8         dot3out_pause_frames_high[0x20];
1534
1535         u8         dot3out_pause_frames_low[0x20];
1536
1537         u8         reserved_at_400[0x3c0];
1538 };
1539
1540 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1541         u8         ether_stats_drop_events_high[0x20];
1542
1543         u8         ether_stats_drop_events_low[0x20];
1544
1545         u8         ether_stats_octets_high[0x20];
1546
1547         u8         ether_stats_octets_low[0x20];
1548
1549         u8         ether_stats_pkts_high[0x20];
1550
1551         u8         ether_stats_pkts_low[0x20];
1552
1553         u8         ether_stats_broadcast_pkts_high[0x20];
1554
1555         u8         ether_stats_broadcast_pkts_low[0x20];
1556
1557         u8         ether_stats_multicast_pkts_high[0x20];
1558
1559         u8         ether_stats_multicast_pkts_low[0x20];
1560
1561         u8         ether_stats_crc_align_errors_high[0x20];
1562
1563         u8         ether_stats_crc_align_errors_low[0x20];
1564
1565         u8         ether_stats_undersize_pkts_high[0x20];
1566
1567         u8         ether_stats_undersize_pkts_low[0x20];
1568
1569         u8         ether_stats_oversize_pkts_high[0x20];
1570
1571         u8         ether_stats_oversize_pkts_low[0x20];
1572
1573         u8         ether_stats_fragments_high[0x20];
1574
1575         u8         ether_stats_fragments_low[0x20];
1576
1577         u8         ether_stats_jabbers_high[0x20];
1578
1579         u8         ether_stats_jabbers_low[0x20];
1580
1581         u8         ether_stats_collisions_high[0x20];
1582
1583         u8         ether_stats_collisions_low[0x20];
1584
1585         u8         ether_stats_pkts64octets_high[0x20];
1586
1587         u8         ether_stats_pkts64octets_low[0x20];
1588
1589         u8         ether_stats_pkts65to127octets_high[0x20];
1590
1591         u8         ether_stats_pkts65to127octets_low[0x20];
1592
1593         u8         ether_stats_pkts128to255octets_high[0x20];
1594
1595         u8         ether_stats_pkts128to255octets_low[0x20];
1596
1597         u8         ether_stats_pkts256to511octets_high[0x20];
1598
1599         u8         ether_stats_pkts256to511octets_low[0x20];
1600
1601         u8         ether_stats_pkts512to1023octets_high[0x20];
1602
1603         u8         ether_stats_pkts512to1023octets_low[0x20];
1604
1605         u8         ether_stats_pkts1024to1518octets_high[0x20];
1606
1607         u8         ether_stats_pkts1024to1518octets_low[0x20];
1608
1609         u8         ether_stats_pkts1519to2047octets_high[0x20];
1610
1611         u8         ether_stats_pkts1519to2047octets_low[0x20];
1612
1613         u8         ether_stats_pkts2048to4095octets_high[0x20];
1614
1615         u8         ether_stats_pkts2048to4095octets_low[0x20];
1616
1617         u8         ether_stats_pkts4096to8191octets_high[0x20];
1618
1619         u8         ether_stats_pkts4096to8191octets_low[0x20];
1620
1621         u8         ether_stats_pkts8192to10239octets_high[0x20];
1622
1623         u8         ether_stats_pkts8192to10239octets_low[0x20];
1624
1625         u8         reserved_at_540[0x280];
1626 };
1627
1628 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1629         u8         if_in_octets_high[0x20];
1630
1631         u8         if_in_octets_low[0x20];
1632
1633         u8         if_in_ucast_pkts_high[0x20];
1634
1635         u8         if_in_ucast_pkts_low[0x20];
1636
1637         u8         if_in_discards_high[0x20];
1638
1639         u8         if_in_discards_low[0x20];
1640
1641         u8         if_in_errors_high[0x20];
1642
1643         u8         if_in_errors_low[0x20];
1644
1645         u8         if_in_unknown_protos_high[0x20];
1646
1647         u8         if_in_unknown_protos_low[0x20];
1648
1649         u8         if_out_octets_high[0x20];
1650
1651         u8         if_out_octets_low[0x20];
1652
1653         u8         if_out_ucast_pkts_high[0x20];
1654
1655         u8         if_out_ucast_pkts_low[0x20];
1656
1657         u8         if_out_discards_high[0x20];
1658
1659         u8         if_out_discards_low[0x20];
1660
1661         u8         if_out_errors_high[0x20];
1662
1663         u8         if_out_errors_low[0x20];
1664
1665         u8         if_in_multicast_pkts_high[0x20];
1666
1667         u8         if_in_multicast_pkts_low[0x20];
1668
1669         u8         if_in_broadcast_pkts_high[0x20];
1670
1671         u8         if_in_broadcast_pkts_low[0x20];
1672
1673         u8         if_out_multicast_pkts_high[0x20];
1674
1675         u8         if_out_multicast_pkts_low[0x20];
1676
1677         u8         if_out_broadcast_pkts_high[0x20];
1678
1679         u8         if_out_broadcast_pkts_low[0x20];
1680
1681         u8         reserved_at_340[0x480];
1682 };
1683
1684 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1685         u8         a_frames_transmitted_ok_high[0x20];
1686
1687         u8         a_frames_transmitted_ok_low[0x20];
1688
1689         u8         a_frames_received_ok_high[0x20];
1690
1691         u8         a_frames_received_ok_low[0x20];
1692
1693         u8         a_frame_check_sequence_errors_high[0x20];
1694
1695         u8         a_frame_check_sequence_errors_low[0x20];
1696
1697         u8         a_alignment_errors_high[0x20];
1698
1699         u8         a_alignment_errors_low[0x20];
1700
1701         u8         a_octets_transmitted_ok_high[0x20];
1702
1703         u8         a_octets_transmitted_ok_low[0x20];
1704
1705         u8         a_octets_received_ok_high[0x20];
1706
1707         u8         a_octets_received_ok_low[0x20];
1708
1709         u8         a_multicast_frames_xmitted_ok_high[0x20];
1710
1711         u8         a_multicast_frames_xmitted_ok_low[0x20];
1712
1713         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1714
1715         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1716
1717         u8         a_multicast_frames_received_ok_high[0x20];
1718
1719         u8         a_multicast_frames_received_ok_low[0x20];
1720
1721         u8         a_broadcast_frames_received_ok_high[0x20];
1722
1723         u8         a_broadcast_frames_received_ok_low[0x20];
1724
1725         u8         a_in_range_length_errors_high[0x20];
1726
1727         u8         a_in_range_length_errors_low[0x20];
1728
1729         u8         a_out_of_range_length_field_high[0x20];
1730
1731         u8         a_out_of_range_length_field_low[0x20];
1732
1733         u8         a_frame_too_long_errors_high[0x20];
1734
1735         u8         a_frame_too_long_errors_low[0x20];
1736
1737         u8         a_symbol_error_during_carrier_high[0x20];
1738
1739         u8         a_symbol_error_during_carrier_low[0x20];
1740
1741         u8         a_mac_control_frames_transmitted_high[0x20];
1742
1743         u8         a_mac_control_frames_transmitted_low[0x20];
1744
1745         u8         a_mac_control_frames_received_high[0x20];
1746
1747         u8         a_mac_control_frames_received_low[0x20];
1748
1749         u8         a_unsupported_opcodes_received_high[0x20];
1750
1751         u8         a_unsupported_opcodes_received_low[0x20];
1752
1753         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1754
1755         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1756
1757         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1758
1759         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1760
1761         u8         reserved_at_4c0[0x300];
1762 };
1763
1764 struct mlx5_ifc_cmd_inter_comp_event_bits {
1765         u8         command_completion_vector[0x20];
1766
1767         u8         reserved_at_20[0xc0];
1768 };
1769
1770 struct mlx5_ifc_stall_vl_event_bits {
1771         u8         reserved_at_0[0x18];
1772         u8         port_num[0x1];
1773         u8         reserved_at_19[0x3];
1774         u8         vl[0x4];
1775
1776         u8         reserved_at_20[0xa0];
1777 };
1778
1779 struct mlx5_ifc_db_bf_congestion_event_bits {
1780         u8         event_subtype[0x8];
1781         u8         reserved_at_8[0x8];
1782         u8         congestion_level[0x8];
1783         u8         reserved_at_18[0x8];
1784
1785         u8         reserved_at_20[0xa0];
1786 };
1787
1788 struct mlx5_ifc_gpio_event_bits {
1789         u8         reserved_at_0[0x60];
1790
1791         u8         gpio_event_hi[0x20];
1792
1793         u8         gpio_event_lo[0x20];
1794
1795         u8         reserved_at_a0[0x40];
1796 };
1797
1798 struct mlx5_ifc_port_state_change_event_bits {
1799         u8         reserved_at_0[0x40];
1800
1801         u8         port_num[0x4];
1802         u8         reserved_at_44[0x1c];
1803
1804         u8         reserved_at_60[0x80];
1805 };
1806
1807 struct mlx5_ifc_dropped_packet_logged_bits {
1808         u8         reserved_at_0[0xe0];
1809 };
1810
1811 enum {
1812         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1813         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1814 };
1815
1816 struct mlx5_ifc_cq_error_bits {
1817         u8         reserved_at_0[0x8];
1818         u8         cqn[0x18];
1819
1820         u8         reserved_at_20[0x20];
1821
1822         u8         reserved_at_40[0x18];
1823         u8         syndrome[0x8];
1824
1825         u8         reserved_at_60[0x80];
1826 };
1827
1828 struct mlx5_ifc_rdma_page_fault_event_bits {
1829         u8         bytes_committed[0x20];
1830
1831         u8         r_key[0x20];
1832
1833         u8         reserved_at_40[0x10];
1834         u8         packet_len[0x10];
1835
1836         u8         rdma_op_len[0x20];
1837
1838         u8         rdma_va[0x40];
1839
1840         u8         reserved_at_c0[0x5];
1841         u8         rdma[0x1];
1842         u8         write[0x1];
1843         u8         requestor[0x1];
1844         u8         qp_number[0x18];
1845 };
1846
1847 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1848         u8         bytes_committed[0x20];
1849
1850         u8         reserved_at_20[0x10];
1851         u8         wqe_index[0x10];
1852
1853         u8         reserved_at_40[0x10];
1854         u8         len[0x10];
1855
1856         u8         reserved_at_60[0x60];
1857
1858         u8         reserved_at_c0[0x5];
1859         u8         rdma[0x1];
1860         u8         write_read[0x1];
1861         u8         requestor[0x1];
1862         u8         qpn[0x18];
1863 };
1864
1865 struct mlx5_ifc_qp_events_bits {
1866         u8         reserved_at_0[0xa0];
1867
1868         u8         type[0x8];
1869         u8         reserved_at_a8[0x18];
1870
1871         u8         reserved_at_c0[0x8];
1872         u8         qpn_rqn_sqn[0x18];
1873 };
1874
1875 struct mlx5_ifc_dct_events_bits {
1876         u8         reserved_at_0[0xc0];
1877
1878         u8         reserved_at_c0[0x8];
1879         u8         dct_number[0x18];
1880 };
1881
1882 struct mlx5_ifc_comp_event_bits {
1883         u8         reserved_at_0[0xc0];
1884
1885         u8         reserved_at_c0[0x8];
1886         u8         cq_number[0x18];
1887 };
1888
1889 enum {
1890         MLX5_QPC_STATE_RST        = 0x0,
1891         MLX5_QPC_STATE_INIT       = 0x1,
1892         MLX5_QPC_STATE_RTR        = 0x2,
1893         MLX5_QPC_STATE_RTS        = 0x3,
1894         MLX5_QPC_STATE_SQER       = 0x4,
1895         MLX5_QPC_STATE_ERR        = 0x6,
1896         MLX5_QPC_STATE_SQD        = 0x7,
1897         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1898 };
1899
1900 enum {
1901         MLX5_QPC_ST_RC            = 0x0,
1902         MLX5_QPC_ST_UC            = 0x1,
1903         MLX5_QPC_ST_UD            = 0x2,
1904         MLX5_QPC_ST_XRC           = 0x3,
1905         MLX5_QPC_ST_DCI           = 0x5,
1906         MLX5_QPC_ST_QP0           = 0x7,
1907         MLX5_QPC_ST_QP1           = 0x8,
1908         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1909         MLX5_QPC_ST_REG_UMR       = 0xc,
1910 };
1911
1912 enum {
1913         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1914         MLX5_QPC_PM_STATE_REARM     = 0x1,
1915         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1916         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1917 };
1918
1919 enum {
1920         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1921         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1922 };
1923
1924 enum {
1925         MLX5_QPC_MTU_256_BYTES        = 0x1,
1926         MLX5_QPC_MTU_512_BYTES        = 0x2,
1927         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1928         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1929         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1930         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1931 };
1932
1933 enum {
1934         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1935         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1936         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1937         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1938         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1939         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1940         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1941         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1942 };
1943
1944 enum {
1945         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1946         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1947         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1948 };
1949
1950 enum {
1951         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1952         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1953         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1954 };
1955
1956 struct mlx5_ifc_qpc_bits {
1957         u8         state[0x4];
1958         u8         lag_tx_port_affinity[0x4];
1959         u8         st[0x8];
1960         u8         reserved_at_10[0x3];
1961         u8         pm_state[0x2];
1962         u8         reserved_at_15[0x7];
1963         u8         end_padding_mode[0x2];
1964         u8         reserved_at_1e[0x2];
1965
1966         u8         wq_signature[0x1];
1967         u8         block_lb_mc[0x1];
1968         u8         atomic_like_write_en[0x1];
1969         u8         latency_sensitive[0x1];
1970         u8         reserved_at_24[0x1];
1971         u8         drain_sigerr[0x1];
1972         u8         reserved_at_26[0x2];
1973         u8         pd[0x18];
1974
1975         u8         mtu[0x3];
1976         u8         log_msg_max[0x5];
1977         u8         reserved_at_48[0x1];
1978         u8         log_rq_size[0x4];
1979         u8         log_rq_stride[0x3];
1980         u8         no_sq[0x1];
1981         u8         log_sq_size[0x4];
1982         u8         reserved_at_55[0x6];
1983         u8         rlky[0x1];
1984         u8         ulp_stateless_offload_mode[0x4];
1985
1986         u8         counter_set_id[0x8];
1987         u8         uar_page[0x18];
1988
1989         u8         reserved_at_80[0x8];
1990         u8         user_index[0x18];
1991
1992         u8         reserved_at_a0[0x3];
1993         u8         log_page_size[0x5];
1994         u8         remote_qpn[0x18];
1995
1996         struct mlx5_ifc_ads_bits primary_address_path;
1997
1998         struct mlx5_ifc_ads_bits secondary_address_path;
1999
2000         u8         log_ack_req_freq[0x4];
2001         u8         reserved_at_384[0x4];
2002         u8         log_sra_max[0x3];
2003         u8         reserved_at_38b[0x2];
2004         u8         retry_count[0x3];
2005         u8         rnr_retry[0x3];
2006         u8         reserved_at_393[0x1];
2007         u8         fre[0x1];
2008         u8         cur_rnr_retry[0x3];
2009         u8         cur_retry_count[0x3];
2010         u8         reserved_at_39b[0x5];
2011
2012         u8         reserved_at_3a0[0x20];
2013
2014         u8         reserved_at_3c0[0x8];
2015         u8         next_send_psn[0x18];
2016
2017         u8         reserved_at_3e0[0x8];
2018         u8         cqn_snd[0x18];
2019
2020         u8         reserved_at_400[0x8];
2021         u8         deth_sqpn[0x18];
2022
2023         u8         reserved_at_420[0x20];
2024
2025         u8         reserved_at_440[0x8];
2026         u8         last_acked_psn[0x18];
2027
2028         u8         reserved_at_460[0x8];
2029         u8         ssn[0x18];
2030
2031         u8         reserved_at_480[0x8];
2032         u8         log_rra_max[0x3];
2033         u8         reserved_at_48b[0x1];
2034         u8         atomic_mode[0x4];
2035         u8         rre[0x1];
2036         u8         rwe[0x1];
2037         u8         rae[0x1];
2038         u8         reserved_at_493[0x1];
2039         u8         page_offset[0x6];
2040         u8         reserved_at_49a[0x3];
2041         u8         cd_slave_receive[0x1];
2042         u8         cd_slave_send[0x1];
2043         u8         cd_master[0x1];
2044
2045         u8         reserved_at_4a0[0x3];
2046         u8         min_rnr_nak[0x5];
2047         u8         next_rcv_psn[0x18];
2048
2049         u8         reserved_at_4c0[0x8];
2050         u8         xrcd[0x18];
2051
2052         u8         reserved_at_4e0[0x8];
2053         u8         cqn_rcv[0x18];
2054
2055         u8         dbr_addr[0x40];
2056
2057         u8         q_key[0x20];
2058
2059         u8         reserved_at_560[0x5];
2060         u8         rq_type[0x3];
2061         u8         srqn_rmpn_xrqn[0x18];
2062
2063         u8         reserved_at_580[0x8];
2064         u8         rmsn[0x18];
2065
2066         u8         hw_sq_wqebb_counter[0x10];
2067         u8         sw_sq_wqebb_counter[0x10];
2068
2069         u8         hw_rq_counter[0x20];
2070
2071         u8         sw_rq_counter[0x20];
2072
2073         u8         reserved_at_600[0x20];
2074
2075         u8         reserved_at_620[0xf];
2076         u8         cgs[0x1];
2077         u8         cs_req[0x8];
2078         u8         cs_res[0x8];
2079
2080         u8         dc_access_key[0x40];
2081
2082         u8         reserved_at_680[0xc0];
2083 };
2084
2085 struct mlx5_ifc_roce_addr_layout_bits {
2086         u8         source_l3_address[16][0x8];
2087
2088         u8         reserved_at_80[0x3];
2089         u8         vlan_valid[0x1];
2090         u8         vlan_id[0xc];
2091         u8         source_mac_47_32[0x10];
2092
2093         u8         source_mac_31_0[0x20];
2094
2095         u8         reserved_at_c0[0x14];
2096         u8         roce_l3_type[0x4];
2097         u8         roce_version[0x8];
2098
2099         u8         reserved_at_e0[0x20];
2100 };
2101
2102 union mlx5_ifc_hca_cap_union_bits {
2103         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2104         struct mlx5_ifc_odp_cap_bits odp_cap;
2105         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2106         struct mlx5_ifc_roce_cap_bits roce_cap;
2107         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2108         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2109         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2110         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2111         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2112         struct mlx5_ifc_qos_cap_bits qos_cap;
2113         u8         reserved_at_0[0x8000];
2114 };
2115
2116 enum {
2117         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2118         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2119         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2120         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2121         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2122         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2123 };
2124
2125 struct mlx5_ifc_flow_context_bits {
2126         u8         reserved_at_0[0x20];
2127
2128         u8         group_id[0x20];
2129
2130         u8         reserved_at_40[0x8];
2131         u8         flow_tag[0x18];
2132
2133         u8         reserved_at_60[0x10];
2134         u8         action[0x10];
2135
2136         u8         reserved_at_80[0x8];
2137         u8         destination_list_size[0x18];
2138
2139         u8         reserved_at_a0[0x8];
2140         u8         flow_counter_list_size[0x18];
2141
2142         u8         encap_id[0x20];
2143
2144         u8         reserved_at_e0[0x120];
2145
2146         struct mlx5_ifc_fte_match_param_bits match_value;
2147
2148         u8         reserved_at_1200[0x600];
2149
2150         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2151 };
2152
2153 enum {
2154         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2155         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2156 };
2157
2158 struct mlx5_ifc_xrc_srqc_bits {
2159         u8         state[0x4];
2160         u8         log_xrc_srq_size[0x4];
2161         u8         reserved_at_8[0x18];
2162
2163         u8         wq_signature[0x1];
2164         u8         cont_srq[0x1];
2165         u8         reserved_at_22[0x1];
2166         u8         rlky[0x1];
2167         u8         basic_cyclic_rcv_wqe[0x1];
2168         u8         log_rq_stride[0x3];
2169         u8         xrcd[0x18];
2170
2171         u8         page_offset[0x6];
2172         u8         reserved_at_46[0x2];
2173         u8         cqn[0x18];
2174
2175         u8         reserved_at_60[0x20];
2176
2177         u8         user_index_equal_xrc_srqn[0x1];
2178         u8         reserved_at_81[0x1];
2179         u8         log_page_size[0x6];
2180         u8         user_index[0x18];
2181
2182         u8         reserved_at_a0[0x20];
2183
2184         u8         reserved_at_c0[0x8];
2185         u8         pd[0x18];
2186
2187         u8         lwm[0x10];
2188         u8         wqe_cnt[0x10];
2189
2190         u8         reserved_at_100[0x40];
2191
2192         u8         db_record_addr_h[0x20];
2193
2194         u8         db_record_addr_l[0x1e];
2195         u8         reserved_at_17e[0x2];
2196
2197         u8         reserved_at_180[0x80];
2198 };
2199
2200 struct mlx5_ifc_traffic_counter_bits {
2201         u8         packets[0x40];
2202
2203         u8         octets[0x40];
2204 };
2205
2206 struct mlx5_ifc_tisc_bits {
2207         u8         strict_lag_tx_port_affinity[0x1];
2208         u8         reserved_at_1[0x3];
2209         u8         lag_tx_port_affinity[0x04];
2210
2211         u8         reserved_at_8[0x4];
2212         u8         prio[0x4];
2213         u8         reserved_at_10[0x10];
2214
2215         u8         reserved_at_20[0x100];
2216
2217         u8         reserved_at_120[0x8];
2218         u8         transport_domain[0x18];
2219
2220         u8         reserved_at_140[0x3c0];
2221 };
2222
2223 enum {
2224         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2225         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2226 };
2227
2228 enum {
2229         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2230         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2231 };
2232
2233 enum {
2234         MLX5_RX_HASH_FN_NONE           = 0x0,
2235         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2236         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2237 };
2238
2239 enum {
2240         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2241         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2242 };
2243
2244 struct mlx5_ifc_tirc_bits {
2245         u8         reserved_at_0[0x20];
2246
2247         u8         disp_type[0x4];
2248         u8         reserved_at_24[0x1c];
2249
2250         u8         reserved_at_40[0x40];
2251
2252         u8         reserved_at_80[0x4];
2253         u8         lro_timeout_period_usecs[0x10];
2254         u8         lro_enable_mask[0x4];
2255         u8         lro_max_ip_payload_size[0x8];
2256
2257         u8         reserved_at_a0[0x40];
2258
2259         u8         reserved_at_e0[0x8];
2260         u8         inline_rqn[0x18];
2261
2262         u8         rx_hash_symmetric[0x1];
2263         u8         reserved_at_101[0x1];
2264         u8         tunneled_offload_en[0x1];
2265         u8         reserved_at_103[0x5];
2266         u8         indirect_table[0x18];
2267
2268         u8         rx_hash_fn[0x4];
2269         u8         reserved_at_124[0x2];
2270         u8         self_lb_block[0x2];
2271         u8         transport_domain[0x18];
2272
2273         u8         rx_hash_toeplitz_key[10][0x20];
2274
2275         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2276
2277         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2278
2279         u8         reserved_at_2c0[0x4c0];
2280 };
2281
2282 enum {
2283         MLX5_SRQC_STATE_GOOD   = 0x0,
2284         MLX5_SRQC_STATE_ERROR  = 0x1,
2285 };
2286
2287 struct mlx5_ifc_srqc_bits {
2288         u8         state[0x4];
2289         u8         log_srq_size[0x4];
2290         u8         reserved_at_8[0x18];
2291
2292         u8         wq_signature[0x1];
2293         u8         cont_srq[0x1];
2294         u8         reserved_at_22[0x1];
2295         u8         rlky[0x1];
2296         u8         reserved_at_24[0x1];
2297         u8         log_rq_stride[0x3];
2298         u8         xrcd[0x18];
2299
2300         u8         page_offset[0x6];
2301         u8         reserved_at_46[0x2];
2302         u8         cqn[0x18];
2303
2304         u8         reserved_at_60[0x20];
2305
2306         u8         reserved_at_80[0x2];
2307         u8         log_page_size[0x6];
2308         u8         reserved_at_88[0x18];
2309
2310         u8         reserved_at_a0[0x20];
2311
2312         u8         reserved_at_c0[0x8];
2313         u8         pd[0x18];
2314
2315         u8         lwm[0x10];
2316         u8         wqe_cnt[0x10];
2317
2318         u8         reserved_at_100[0x40];
2319
2320         u8         dbr_addr[0x40];
2321
2322         u8         reserved_at_180[0x80];
2323 };
2324
2325 enum {
2326         MLX5_SQC_STATE_RST  = 0x0,
2327         MLX5_SQC_STATE_RDY  = 0x1,
2328         MLX5_SQC_STATE_ERR  = 0x3,
2329 };
2330
2331 struct mlx5_ifc_sqc_bits {
2332         u8         rlky[0x1];
2333         u8         cd_master[0x1];
2334         u8         fre[0x1];
2335         u8         flush_in_error_en[0x1];
2336         u8         reserved_at_4[0x1];
2337         u8         min_wqe_inline_mode[0x3];
2338         u8         state[0x4];
2339         u8         reg_umr[0x1];
2340         u8         reserved_at_d[0x13];
2341
2342         u8         reserved_at_20[0x8];
2343         u8         user_index[0x18];
2344
2345         u8         reserved_at_40[0x8];
2346         u8         cqn[0x18];
2347
2348         u8         reserved_at_60[0x90];
2349
2350         u8         packet_pacing_rate_limit_index[0x10];
2351         u8         tis_lst_sz[0x10];
2352         u8         reserved_at_110[0x10];
2353
2354         u8         reserved_at_120[0x40];
2355
2356         u8         reserved_at_160[0x8];
2357         u8         tis_num_0[0x18];
2358
2359         struct mlx5_ifc_wq_bits wq;
2360 };
2361
2362 enum {
2363         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2364         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2365         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2366         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2367 };
2368
2369 struct mlx5_ifc_scheduling_context_bits {
2370         u8         element_type[0x8];
2371         u8         reserved_at_8[0x18];
2372
2373         u8         element_attributes[0x20];
2374
2375         u8         parent_element_id[0x20];
2376
2377         u8         reserved_at_60[0x40];
2378
2379         u8         bw_share[0x20];
2380
2381         u8         max_average_bw[0x20];
2382
2383         u8         reserved_at_e0[0x120];
2384 };
2385
2386 struct mlx5_ifc_rqtc_bits {
2387         u8         reserved_at_0[0xa0];
2388
2389         u8         reserved_at_a0[0x10];
2390         u8         rqt_max_size[0x10];
2391
2392         u8         reserved_at_c0[0x10];
2393         u8         rqt_actual_size[0x10];
2394
2395         u8         reserved_at_e0[0x6a0];
2396
2397         struct mlx5_ifc_rq_num_bits rq_num[0];
2398 };
2399
2400 enum {
2401         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2402         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2403 };
2404
2405 enum {
2406         MLX5_RQC_STATE_RST  = 0x0,
2407         MLX5_RQC_STATE_RDY  = 0x1,
2408         MLX5_RQC_STATE_ERR  = 0x3,
2409 };
2410
2411 struct mlx5_ifc_rqc_bits {
2412         u8         rlky[0x1];
2413         u8         reserved_at_1[0x1];
2414         u8         scatter_fcs[0x1];
2415         u8         vsd[0x1];
2416         u8         mem_rq_type[0x4];
2417         u8         state[0x4];
2418         u8         reserved_at_c[0x1];
2419         u8         flush_in_error_en[0x1];
2420         u8         reserved_at_e[0x12];
2421
2422         u8         reserved_at_20[0x8];
2423         u8         user_index[0x18];
2424
2425         u8         reserved_at_40[0x8];
2426         u8         cqn[0x18];
2427
2428         u8         counter_set_id[0x8];
2429         u8         reserved_at_68[0x18];
2430
2431         u8         reserved_at_80[0x8];
2432         u8         rmpn[0x18];
2433
2434         u8         reserved_at_a0[0xe0];
2435
2436         struct mlx5_ifc_wq_bits wq;
2437 };
2438
2439 enum {
2440         MLX5_RMPC_STATE_RDY  = 0x1,
2441         MLX5_RMPC_STATE_ERR  = 0x3,
2442 };
2443
2444 struct mlx5_ifc_rmpc_bits {
2445         u8         reserved_at_0[0x8];
2446         u8         state[0x4];
2447         u8         reserved_at_c[0x14];
2448
2449         u8         basic_cyclic_rcv_wqe[0x1];
2450         u8         reserved_at_21[0x1f];
2451
2452         u8         reserved_at_40[0x140];
2453
2454         struct mlx5_ifc_wq_bits wq;
2455 };
2456
2457 struct mlx5_ifc_nic_vport_context_bits {
2458         u8         reserved_at_0[0x5];
2459         u8         min_wqe_inline_mode[0x3];
2460         u8         reserved_at_8[0x17];
2461         u8         roce_en[0x1];
2462
2463         u8         arm_change_event[0x1];
2464         u8         reserved_at_21[0x1a];
2465         u8         event_on_mtu[0x1];
2466         u8         event_on_promisc_change[0x1];
2467         u8         event_on_vlan_change[0x1];
2468         u8         event_on_mc_address_change[0x1];
2469         u8         event_on_uc_address_change[0x1];
2470
2471         u8         reserved_at_40[0xf0];
2472
2473         u8         mtu[0x10];
2474
2475         u8         system_image_guid[0x40];
2476         u8         port_guid[0x40];
2477         u8         node_guid[0x40];
2478
2479         u8         reserved_at_200[0x140];
2480         u8         qkey_violation_counter[0x10];
2481         u8         reserved_at_350[0x430];
2482
2483         u8         promisc_uc[0x1];
2484         u8         promisc_mc[0x1];
2485         u8         promisc_all[0x1];
2486         u8         reserved_at_783[0x2];
2487         u8         allowed_list_type[0x3];
2488         u8         reserved_at_788[0xc];
2489         u8         allowed_list_size[0xc];
2490
2491         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2492
2493         u8         reserved_at_7e0[0x20];
2494
2495         u8         current_uc_mac_address[0][0x40];
2496 };
2497
2498 enum {
2499         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2500         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2501         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2502         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2503 };
2504
2505 struct mlx5_ifc_mkc_bits {
2506         u8         reserved_at_0[0x1];
2507         u8         free[0x1];
2508         u8         reserved_at_2[0xd];
2509         u8         small_fence_on_rdma_read_response[0x1];
2510         u8         umr_en[0x1];
2511         u8         a[0x1];
2512         u8         rw[0x1];
2513         u8         rr[0x1];
2514         u8         lw[0x1];
2515         u8         lr[0x1];
2516         u8         access_mode[0x2];
2517         u8         reserved_at_18[0x8];
2518
2519         u8         qpn[0x18];
2520         u8         mkey_7_0[0x8];
2521
2522         u8         reserved_at_40[0x20];
2523
2524         u8         length64[0x1];
2525         u8         bsf_en[0x1];
2526         u8         sync_umr[0x1];
2527         u8         reserved_at_63[0x2];
2528         u8         expected_sigerr_count[0x1];
2529         u8         reserved_at_66[0x1];
2530         u8         en_rinval[0x1];
2531         u8         pd[0x18];
2532
2533         u8         start_addr[0x40];
2534
2535         u8         len[0x40];
2536
2537         u8         bsf_octword_size[0x20];
2538
2539         u8         reserved_at_120[0x80];
2540
2541         u8         translations_octword_size[0x20];
2542
2543         u8         reserved_at_1c0[0x1b];
2544         u8         log_page_size[0x5];
2545
2546         u8         reserved_at_1e0[0x20];
2547 };
2548
2549 struct mlx5_ifc_pkey_bits {
2550         u8         reserved_at_0[0x10];
2551         u8         pkey[0x10];
2552 };
2553
2554 struct mlx5_ifc_array128_auto_bits {
2555         u8         array128_auto[16][0x8];
2556 };
2557
2558 struct mlx5_ifc_hca_vport_context_bits {
2559         u8         field_select[0x20];
2560
2561         u8         reserved_at_20[0xe0];
2562
2563         u8         sm_virt_aware[0x1];
2564         u8         has_smi[0x1];
2565         u8         has_raw[0x1];
2566         u8         grh_required[0x1];
2567         u8         reserved_at_104[0xc];
2568         u8         port_physical_state[0x4];
2569         u8         vport_state_policy[0x4];
2570         u8         port_state[0x4];
2571         u8         vport_state[0x4];
2572
2573         u8         reserved_at_120[0x20];
2574
2575         u8         system_image_guid[0x40];
2576
2577         u8         port_guid[0x40];
2578
2579         u8         node_guid[0x40];
2580
2581         u8         cap_mask1[0x20];
2582
2583         u8         cap_mask1_field_select[0x20];
2584
2585         u8         cap_mask2[0x20];
2586
2587         u8         cap_mask2_field_select[0x20];
2588
2589         u8         reserved_at_280[0x80];
2590
2591         u8         lid[0x10];
2592         u8         reserved_at_310[0x4];
2593         u8         init_type_reply[0x4];
2594         u8         lmc[0x3];
2595         u8         subnet_timeout[0x5];
2596
2597         u8         sm_lid[0x10];
2598         u8         sm_sl[0x4];
2599         u8         reserved_at_334[0xc];
2600
2601         u8         qkey_violation_counter[0x10];
2602         u8         pkey_violation_counter[0x10];
2603
2604         u8         reserved_at_360[0xca0];
2605 };
2606
2607 struct mlx5_ifc_esw_vport_context_bits {
2608         u8         reserved_at_0[0x3];
2609         u8         vport_svlan_strip[0x1];
2610         u8         vport_cvlan_strip[0x1];
2611         u8         vport_svlan_insert[0x1];
2612         u8         vport_cvlan_insert[0x2];
2613         u8         reserved_at_8[0x18];
2614
2615         u8         reserved_at_20[0x20];
2616
2617         u8         svlan_cfi[0x1];
2618         u8         svlan_pcp[0x3];
2619         u8         svlan_id[0xc];
2620         u8         cvlan_cfi[0x1];
2621         u8         cvlan_pcp[0x3];
2622         u8         cvlan_id[0xc];
2623
2624         u8         reserved_at_60[0x7a0];
2625 };
2626
2627 enum {
2628         MLX5_EQC_STATUS_OK                = 0x0,
2629         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2630 };
2631
2632 enum {
2633         MLX5_EQC_ST_ARMED  = 0x9,
2634         MLX5_EQC_ST_FIRED  = 0xa,
2635 };
2636
2637 struct mlx5_ifc_eqc_bits {
2638         u8         status[0x4];
2639         u8         reserved_at_4[0x9];
2640         u8         ec[0x1];
2641         u8         oi[0x1];
2642         u8         reserved_at_f[0x5];
2643         u8         st[0x4];
2644         u8         reserved_at_18[0x8];
2645
2646         u8         reserved_at_20[0x20];
2647
2648         u8         reserved_at_40[0x14];
2649         u8         page_offset[0x6];
2650         u8         reserved_at_5a[0x6];
2651
2652         u8         reserved_at_60[0x3];
2653         u8         log_eq_size[0x5];
2654         u8         uar_page[0x18];
2655
2656         u8         reserved_at_80[0x20];
2657
2658         u8         reserved_at_a0[0x18];
2659         u8         intr[0x8];
2660
2661         u8         reserved_at_c0[0x3];
2662         u8         log_page_size[0x5];
2663         u8         reserved_at_c8[0x18];
2664
2665         u8         reserved_at_e0[0x60];
2666
2667         u8         reserved_at_140[0x8];
2668         u8         consumer_counter[0x18];
2669
2670         u8         reserved_at_160[0x8];
2671         u8         producer_counter[0x18];
2672
2673         u8         reserved_at_180[0x80];
2674 };
2675
2676 enum {
2677         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2678         MLX5_DCTC_STATE_DRAINING  = 0x1,
2679         MLX5_DCTC_STATE_DRAINED   = 0x2,
2680 };
2681
2682 enum {
2683         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2684         MLX5_DCTC_CS_RES_NA         = 0x1,
2685         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2686 };
2687
2688 enum {
2689         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2690         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2691         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2692         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2693         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2694 };
2695
2696 struct mlx5_ifc_dctc_bits {
2697         u8         reserved_at_0[0x4];
2698         u8         state[0x4];
2699         u8         reserved_at_8[0x18];
2700
2701         u8         reserved_at_20[0x8];
2702         u8         user_index[0x18];
2703
2704         u8         reserved_at_40[0x8];
2705         u8         cqn[0x18];
2706
2707         u8         counter_set_id[0x8];
2708         u8         atomic_mode[0x4];
2709         u8         rre[0x1];
2710         u8         rwe[0x1];
2711         u8         rae[0x1];
2712         u8         atomic_like_write_en[0x1];
2713         u8         latency_sensitive[0x1];
2714         u8         rlky[0x1];
2715         u8         free_ar[0x1];
2716         u8         reserved_at_73[0xd];
2717
2718         u8         reserved_at_80[0x8];
2719         u8         cs_res[0x8];
2720         u8         reserved_at_90[0x3];
2721         u8         min_rnr_nak[0x5];
2722         u8         reserved_at_98[0x8];
2723
2724         u8         reserved_at_a0[0x8];
2725         u8         srqn_xrqn[0x18];
2726
2727         u8         reserved_at_c0[0x8];
2728         u8         pd[0x18];
2729
2730         u8         tclass[0x8];
2731         u8         reserved_at_e8[0x4];
2732         u8         flow_label[0x14];
2733
2734         u8         dc_access_key[0x40];
2735
2736         u8         reserved_at_140[0x5];
2737         u8         mtu[0x3];
2738         u8         port[0x8];
2739         u8         pkey_index[0x10];
2740
2741         u8         reserved_at_160[0x8];
2742         u8         my_addr_index[0x8];
2743         u8         reserved_at_170[0x8];
2744         u8         hop_limit[0x8];
2745
2746         u8         dc_access_key_violation_count[0x20];
2747
2748         u8         reserved_at_1a0[0x14];
2749         u8         dei_cfi[0x1];
2750         u8         eth_prio[0x3];
2751         u8         ecn[0x2];
2752         u8         dscp[0x6];
2753
2754         u8         reserved_at_1c0[0x40];
2755 };
2756
2757 enum {
2758         MLX5_CQC_STATUS_OK             = 0x0,
2759         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2760         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2761 };
2762
2763 enum {
2764         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2765         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2766 };
2767
2768 enum {
2769         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2770         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2771         MLX5_CQC_ST_FIRED                                 = 0xa,
2772 };
2773
2774 enum {
2775         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2776         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2777         MLX5_CQ_PERIOD_NUM_MODES
2778 };
2779
2780 struct mlx5_ifc_cqc_bits {
2781         u8         status[0x4];
2782         u8         reserved_at_4[0x4];
2783         u8         cqe_sz[0x3];
2784         u8         cc[0x1];
2785         u8         reserved_at_c[0x1];
2786         u8         scqe_break_moderation_en[0x1];
2787         u8         oi[0x1];
2788         u8         cq_period_mode[0x2];
2789         u8         cqe_comp_en[0x1];
2790         u8         mini_cqe_res_format[0x2];
2791         u8         st[0x4];
2792         u8         reserved_at_18[0x8];
2793
2794         u8         reserved_at_20[0x20];
2795
2796         u8         reserved_at_40[0x14];
2797         u8         page_offset[0x6];
2798         u8         reserved_at_5a[0x6];
2799
2800         u8         reserved_at_60[0x3];
2801         u8         log_cq_size[0x5];
2802         u8         uar_page[0x18];
2803
2804         u8         reserved_at_80[0x4];
2805         u8         cq_period[0xc];
2806         u8         cq_max_count[0x10];
2807
2808         u8         reserved_at_a0[0x18];
2809         u8         c_eqn[0x8];
2810
2811         u8         reserved_at_c0[0x3];
2812         u8         log_page_size[0x5];
2813         u8         reserved_at_c8[0x18];
2814
2815         u8         reserved_at_e0[0x20];
2816
2817         u8         reserved_at_100[0x8];
2818         u8         last_notified_index[0x18];
2819
2820         u8         reserved_at_120[0x8];
2821         u8         last_solicit_index[0x18];
2822
2823         u8         reserved_at_140[0x8];
2824         u8         consumer_counter[0x18];
2825
2826         u8         reserved_at_160[0x8];
2827         u8         producer_counter[0x18];
2828
2829         u8         reserved_at_180[0x40];
2830
2831         u8         dbr_addr[0x40];
2832 };
2833
2834 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2835         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2836         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2837         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2838         u8         reserved_at_0[0x800];
2839 };
2840
2841 struct mlx5_ifc_query_adapter_param_block_bits {
2842         u8         reserved_at_0[0xc0];
2843
2844         u8         reserved_at_c0[0x8];
2845         u8         ieee_vendor_id[0x18];
2846
2847         u8         reserved_at_e0[0x10];
2848         u8         vsd_vendor_id[0x10];
2849
2850         u8         vsd[208][0x8];
2851
2852         u8         vsd_contd_psid[16][0x8];
2853 };
2854
2855 enum {
2856         MLX5_XRQC_STATE_GOOD   = 0x0,
2857         MLX5_XRQC_STATE_ERROR  = 0x1,
2858 };
2859
2860 enum {
2861         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2862         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2863 };
2864
2865 enum {
2866         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2867 };
2868
2869 struct mlx5_ifc_tag_matching_topology_context_bits {
2870         u8         log_matching_list_sz[0x4];
2871         u8         reserved_at_4[0xc];
2872         u8         append_next_index[0x10];
2873
2874         u8         sw_phase_cnt[0x10];
2875         u8         hw_phase_cnt[0x10];
2876
2877         u8         reserved_at_40[0x40];
2878 };
2879
2880 struct mlx5_ifc_xrqc_bits {
2881         u8         state[0x4];
2882         u8         rlkey[0x1];
2883         u8         reserved_at_5[0xf];
2884         u8         topology[0x4];
2885         u8         reserved_at_18[0x4];
2886         u8         offload[0x4];
2887
2888         u8         reserved_at_20[0x8];
2889         u8         user_index[0x18];
2890
2891         u8         reserved_at_40[0x8];
2892         u8         cqn[0x18];
2893
2894         u8         reserved_at_60[0xa0];
2895
2896         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2897
2898         u8         reserved_at_180[0x880];
2899
2900         struct mlx5_ifc_wq_bits wq;
2901 };
2902
2903 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2904         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2905         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2906         u8         reserved_at_0[0x20];
2907 };
2908
2909 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2910         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2911         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2912         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2913         u8         reserved_at_0[0x20];
2914 };
2915
2916 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2917         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2918         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2919         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2920         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2921         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2922         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2923         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2924         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2925         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2926         u8         reserved_at_0[0x7c0];
2927 };
2928
2929 union mlx5_ifc_event_auto_bits {
2930         struct mlx5_ifc_comp_event_bits comp_event;
2931         struct mlx5_ifc_dct_events_bits dct_events;
2932         struct mlx5_ifc_qp_events_bits qp_events;
2933         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2934         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2935         struct mlx5_ifc_cq_error_bits cq_error;
2936         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2937         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2938         struct mlx5_ifc_gpio_event_bits gpio_event;
2939         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2940         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2941         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2942         u8         reserved_at_0[0xe0];
2943 };
2944
2945 struct mlx5_ifc_health_buffer_bits {
2946         u8         reserved_at_0[0x100];
2947
2948         u8         assert_existptr[0x20];
2949
2950         u8         assert_callra[0x20];
2951
2952         u8         reserved_at_140[0x40];
2953
2954         u8         fw_version[0x20];
2955
2956         u8         hw_id[0x20];
2957
2958         u8         reserved_at_1c0[0x20];
2959
2960         u8         irisc_index[0x8];
2961         u8         synd[0x8];
2962         u8         ext_synd[0x10];
2963 };
2964
2965 struct mlx5_ifc_register_loopback_control_bits {
2966         u8         no_lb[0x1];
2967         u8         reserved_at_1[0x7];
2968         u8         port[0x8];
2969         u8         reserved_at_10[0x10];
2970
2971         u8         reserved_at_20[0x60];
2972 };
2973
2974 struct mlx5_ifc_vport_tc_element_bits {
2975         u8         traffic_class[0x4];
2976         u8         reserved_at_4[0xc];
2977         u8         vport_number[0x10];
2978 };
2979
2980 struct mlx5_ifc_vport_element_bits {
2981         u8         reserved_at_0[0x10];
2982         u8         vport_number[0x10];
2983 };
2984
2985 enum {
2986         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2987         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2988         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2989 };
2990
2991 struct mlx5_ifc_tsar_element_bits {
2992         u8         reserved_at_0[0x8];
2993         u8         tsar_type[0x8];
2994         u8         reserved_at_10[0x10];
2995 };
2996
2997 struct mlx5_ifc_teardown_hca_out_bits {
2998         u8         status[0x8];
2999         u8         reserved_at_8[0x18];
3000
3001         u8         syndrome[0x20];
3002
3003         u8         reserved_at_40[0x40];
3004 };
3005
3006 enum {
3007         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3008         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3009 };
3010
3011 struct mlx5_ifc_teardown_hca_in_bits {
3012         u8         opcode[0x10];
3013         u8         reserved_at_10[0x10];
3014
3015         u8         reserved_at_20[0x10];
3016         u8         op_mod[0x10];
3017
3018         u8         reserved_at_40[0x10];
3019         u8         profile[0x10];
3020
3021         u8         reserved_at_60[0x20];
3022 };
3023
3024 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3025         u8         status[0x8];
3026         u8         reserved_at_8[0x18];
3027
3028         u8         syndrome[0x20];
3029
3030         u8         reserved_at_40[0x40];
3031 };
3032
3033 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3034         u8         opcode[0x10];
3035         u8         reserved_at_10[0x10];
3036
3037         u8         reserved_at_20[0x10];
3038         u8         op_mod[0x10];
3039
3040         u8         reserved_at_40[0x8];
3041         u8         qpn[0x18];
3042
3043         u8         reserved_at_60[0x20];
3044
3045         u8         opt_param_mask[0x20];
3046
3047         u8         reserved_at_a0[0x20];
3048
3049         struct mlx5_ifc_qpc_bits qpc;
3050
3051         u8         reserved_at_800[0x80];
3052 };
3053
3054 struct mlx5_ifc_sqd2rts_qp_out_bits {
3055         u8         status[0x8];
3056         u8         reserved_at_8[0x18];
3057
3058         u8         syndrome[0x20];
3059
3060         u8         reserved_at_40[0x40];
3061 };
3062
3063 struct mlx5_ifc_sqd2rts_qp_in_bits {
3064         u8         opcode[0x10];
3065         u8         reserved_at_10[0x10];
3066
3067         u8         reserved_at_20[0x10];
3068         u8         op_mod[0x10];
3069
3070         u8         reserved_at_40[0x8];
3071         u8         qpn[0x18];
3072
3073         u8         reserved_at_60[0x20];
3074
3075         u8         opt_param_mask[0x20];
3076
3077         u8         reserved_at_a0[0x20];
3078
3079         struct mlx5_ifc_qpc_bits qpc;
3080
3081         u8         reserved_at_800[0x80];
3082 };
3083
3084 struct mlx5_ifc_set_roce_address_out_bits {
3085         u8         status[0x8];
3086         u8         reserved_at_8[0x18];
3087
3088         u8         syndrome[0x20];
3089
3090         u8         reserved_at_40[0x40];
3091 };
3092
3093 struct mlx5_ifc_set_roce_address_in_bits {
3094         u8         opcode[0x10];
3095         u8         reserved_at_10[0x10];
3096
3097         u8         reserved_at_20[0x10];
3098         u8         op_mod[0x10];
3099
3100         u8         roce_address_index[0x10];
3101         u8         reserved_at_50[0x10];
3102
3103         u8         reserved_at_60[0x20];
3104
3105         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3106 };
3107
3108 struct mlx5_ifc_set_mad_demux_out_bits {
3109         u8         status[0x8];
3110         u8         reserved_at_8[0x18];
3111
3112         u8         syndrome[0x20];
3113
3114         u8         reserved_at_40[0x40];
3115 };
3116
3117 enum {
3118         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3119         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3120 };
3121
3122 struct mlx5_ifc_set_mad_demux_in_bits {
3123         u8         opcode[0x10];
3124         u8         reserved_at_10[0x10];
3125
3126         u8         reserved_at_20[0x10];
3127         u8         op_mod[0x10];
3128
3129         u8         reserved_at_40[0x20];
3130
3131         u8         reserved_at_60[0x6];
3132         u8         demux_mode[0x2];
3133         u8         reserved_at_68[0x18];
3134 };
3135
3136 struct mlx5_ifc_set_l2_table_entry_out_bits {
3137         u8         status[0x8];
3138         u8         reserved_at_8[0x18];
3139
3140         u8         syndrome[0x20];
3141
3142         u8         reserved_at_40[0x40];
3143 };
3144
3145 struct mlx5_ifc_set_l2_table_entry_in_bits {
3146         u8         opcode[0x10];
3147         u8         reserved_at_10[0x10];
3148
3149         u8         reserved_at_20[0x10];
3150         u8         op_mod[0x10];
3151
3152         u8         reserved_at_40[0x60];
3153
3154         u8         reserved_at_a0[0x8];
3155         u8         table_index[0x18];
3156
3157         u8         reserved_at_c0[0x20];
3158
3159         u8         reserved_at_e0[0x13];
3160         u8         vlan_valid[0x1];
3161         u8         vlan[0xc];
3162
3163         struct mlx5_ifc_mac_address_layout_bits mac_address;
3164
3165         u8         reserved_at_140[0xc0];
3166 };
3167
3168 struct mlx5_ifc_set_issi_out_bits {
3169         u8         status[0x8];
3170         u8         reserved_at_8[0x18];
3171
3172         u8         syndrome[0x20];
3173
3174         u8         reserved_at_40[0x40];
3175 };
3176
3177 struct mlx5_ifc_set_issi_in_bits {
3178         u8         opcode[0x10];
3179         u8         reserved_at_10[0x10];
3180
3181         u8         reserved_at_20[0x10];
3182         u8         op_mod[0x10];
3183
3184         u8         reserved_at_40[0x10];
3185         u8         current_issi[0x10];
3186
3187         u8         reserved_at_60[0x20];
3188 };
3189
3190 struct mlx5_ifc_set_hca_cap_out_bits {
3191         u8         status[0x8];
3192         u8         reserved_at_8[0x18];
3193
3194         u8         syndrome[0x20];
3195
3196         u8         reserved_at_40[0x40];
3197 };
3198
3199 struct mlx5_ifc_set_hca_cap_in_bits {
3200         u8         opcode[0x10];
3201         u8         reserved_at_10[0x10];
3202
3203         u8         reserved_at_20[0x10];
3204         u8         op_mod[0x10];
3205
3206         u8         reserved_at_40[0x40];
3207
3208         union mlx5_ifc_hca_cap_union_bits capability;
3209 };
3210
3211 enum {
3212         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3213         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3214         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3215         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3216 };
3217
3218 struct mlx5_ifc_set_fte_out_bits {
3219         u8         status[0x8];
3220         u8         reserved_at_8[0x18];
3221
3222         u8         syndrome[0x20];
3223
3224         u8         reserved_at_40[0x40];
3225 };
3226
3227 struct mlx5_ifc_set_fte_in_bits {
3228         u8         opcode[0x10];
3229         u8         reserved_at_10[0x10];
3230
3231         u8         reserved_at_20[0x10];
3232         u8         op_mod[0x10];
3233
3234         u8         other_vport[0x1];
3235         u8         reserved_at_41[0xf];
3236         u8         vport_number[0x10];
3237
3238         u8         reserved_at_60[0x20];
3239
3240         u8         table_type[0x8];
3241         u8         reserved_at_88[0x18];
3242
3243         u8         reserved_at_a0[0x8];
3244         u8         table_id[0x18];
3245
3246         u8         reserved_at_c0[0x18];
3247         u8         modify_enable_mask[0x8];
3248
3249         u8         reserved_at_e0[0x20];
3250
3251         u8         flow_index[0x20];
3252
3253         u8         reserved_at_120[0xe0];
3254
3255         struct mlx5_ifc_flow_context_bits flow_context;
3256 };
3257
3258 struct mlx5_ifc_rts2rts_qp_out_bits {
3259         u8         status[0x8];
3260         u8         reserved_at_8[0x18];
3261
3262         u8         syndrome[0x20];
3263
3264         u8         reserved_at_40[0x40];
3265 };
3266
3267 struct mlx5_ifc_rts2rts_qp_in_bits {
3268         u8         opcode[0x10];
3269         u8         reserved_at_10[0x10];
3270
3271         u8         reserved_at_20[0x10];
3272         u8         op_mod[0x10];
3273
3274         u8         reserved_at_40[0x8];
3275         u8         qpn[0x18];
3276
3277         u8         reserved_at_60[0x20];
3278
3279         u8         opt_param_mask[0x20];
3280
3281         u8         reserved_at_a0[0x20];
3282
3283         struct mlx5_ifc_qpc_bits qpc;
3284
3285         u8         reserved_at_800[0x80];
3286 };
3287
3288 struct mlx5_ifc_rtr2rts_qp_out_bits {
3289         u8         status[0x8];
3290         u8         reserved_at_8[0x18];
3291
3292         u8         syndrome[0x20];
3293
3294         u8         reserved_at_40[0x40];
3295 };
3296
3297 struct mlx5_ifc_rtr2rts_qp_in_bits {
3298         u8         opcode[0x10];
3299         u8         reserved_at_10[0x10];
3300
3301         u8         reserved_at_20[0x10];
3302         u8         op_mod[0x10];
3303
3304         u8         reserved_at_40[0x8];
3305         u8         qpn[0x18];
3306
3307         u8         reserved_at_60[0x20];
3308
3309         u8         opt_param_mask[0x20];
3310
3311         u8         reserved_at_a0[0x20];
3312
3313         struct mlx5_ifc_qpc_bits qpc;
3314
3315         u8         reserved_at_800[0x80];
3316 };
3317
3318 struct mlx5_ifc_rst2init_qp_out_bits {
3319         u8         status[0x8];
3320         u8         reserved_at_8[0x18];
3321
3322         u8         syndrome[0x20];
3323
3324         u8         reserved_at_40[0x40];
3325 };
3326
3327 struct mlx5_ifc_rst2init_qp_in_bits {
3328         u8         opcode[0x10];
3329         u8         reserved_at_10[0x10];
3330
3331         u8         reserved_at_20[0x10];
3332         u8         op_mod[0x10];
3333
3334         u8         reserved_at_40[0x8];
3335         u8         qpn[0x18];
3336
3337         u8         reserved_at_60[0x20];
3338
3339         u8         opt_param_mask[0x20];
3340
3341         u8         reserved_at_a0[0x20];
3342
3343         struct mlx5_ifc_qpc_bits qpc;
3344
3345         u8         reserved_at_800[0x80];
3346 };
3347
3348 struct mlx5_ifc_query_xrq_out_bits {
3349         u8         status[0x8];
3350         u8         reserved_at_8[0x18];
3351
3352         u8         syndrome[0x20];
3353
3354         u8         reserved_at_40[0x40];
3355
3356         struct mlx5_ifc_xrqc_bits xrq_context;
3357 };
3358
3359 struct mlx5_ifc_query_xrq_in_bits {
3360         u8         opcode[0x10];
3361         u8         reserved_at_10[0x10];
3362
3363         u8         reserved_at_20[0x10];
3364         u8         op_mod[0x10];
3365
3366         u8         reserved_at_40[0x8];
3367         u8         xrqn[0x18];
3368
3369         u8         reserved_at_60[0x20];
3370 };
3371
3372 struct mlx5_ifc_query_xrc_srq_out_bits {
3373         u8         status[0x8];
3374         u8         reserved_at_8[0x18];
3375
3376         u8         syndrome[0x20];
3377
3378         u8         reserved_at_40[0x40];
3379
3380         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3381
3382         u8         reserved_at_280[0x600];
3383
3384         u8         pas[0][0x40];
3385 };
3386
3387 struct mlx5_ifc_query_xrc_srq_in_bits {
3388         u8         opcode[0x10];
3389         u8         reserved_at_10[0x10];
3390
3391         u8         reserved_at_20[0x10];
3392         u8         op_mod[0x10];
3393
3394         u8         reserved_at_40[0x8];
3395         u8         xrc_srqn[0x18];
3396
3397         u8         reserved_at_60[0x20];
3398 };
3399
3400 enum {
3401         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3402         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3403 };
3404
3405 struct mlx5_ifc_query_vport_state_out_bits {
3406         u8         status[0x8];
3407         u8         reserved_at_8[0x18];
3408
3409         u8         syndrome[0x20];
3410
3411         u8         reserved_at_40[0x20];
3412
3413         u8         reserved_at_60[0x18];
3414         u8         admin_state[0x4];
3415         u8         state[0x4];
3416 };
3417
3418 enum {
3419         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3420         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3421 };
3422
3423 struct mlx5_ifc_query_vport_state_in_bits {
3424         u8         opcode[0x10];
3425         u8         reserved_at_10[0x10];
3426
3427         u8         reserved_at_20[0x10];
3428         u8         op_mod[0x10];
3429
3430         u8         other_vport[0x1];
3431         u8         reserved_at_41[0xf];
3432         u8         vport_number[0x10];
3433
3434         u8         reserved_at_60[0x20];
3435 };
3436
3437 struct mlx5_ifc_query_vport_counter_out_bits {
3438         u8         status[0x8];
3439         u8         reserved_at_8[0x18];
3440
3441         u8         syndrome[0x20];
3442
3443         u8         reserved_at_40[0x40];
3444
3445         struct mlx5_ifc_traffic_counter_bits received_errors;
3446
3447         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3448
3449         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3450
3451         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3452
3453         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3454
3455         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3456
3457         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3458
3459         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3460
3461         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3462
3463         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3464
3465         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3466
3467         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3468
3469         u8         reserved_at_680[0xa00];
3470 };
3471
3472 enum {
3473         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3474 };
3475
3476 struct mlx5_ifc_query_vport_counter_in_bits {
3477         u8         opcode[0x10];
3478         u8         reserved_at_10[0x10];
3479
3480         u8         reserved_at_20[0x10];
3481         u8         op_mod[0x10];
3482
3483         u8         other_vport[0x1];
3484         u8         reserved_at_41[0xb];
3485         u8         port_num[0x4];
3486         u8         vport_number[0x10];
3487
3488         u8         reserved_at_60[0x60];
3489
3490         u8         clear[0x1];
3491         u8         reserved_at_c1[0x1f];
3492
3493         u8         reserved_at_e0[0x20];
3494 };
3495
3496 struct mlx5_ifc_query_tis_out_bits {
3497         u8         status[0x8];
3498         u8         reserved_at_8[0x18];
3499
3500         u8         syndrome[0x20];
3501
3502         u8         reserved_at_40[0x40];
3503
3504         struct mlx5_ifc_tisc_bits tis_context;
3505 };
3506
3507 struct mlx5_ifc_query_tis_in_bits {
3508         u8         opcode[0x10];
3509         u8         reserved_at_10[0x10];
3510
3511         u8         reserved_at_20[0x10];
3512         u8         op_mod[0x10];
3513
3514         u8         reserved_at_40[0x8];
3515         u8         tisn[0x18];
3516
3517         u8         reserved_at_60[0x20];
3518 };
3519
3520 struct mlx5_ifc_query_tir_out_bits {
3521         u8         status[0x8];
3522         u8         reserved_at_8[0x18];
3523
3524         u8         syndrome[0x20];
3525
3526         u8         reserved_at_40[0xc0];
3527
3528         struct mlx5_ifc_tirc_bits tir_context;
3529 };
3530
3531 struct mlx5_ifc_query_tir_in_bits {
3532         u8         opcode[0x10];
3533         u8         reserved_at_10[0x10];
3534
3535         u8         reserved_at_20[0x10];
3536         u8         op_mod[0x10];
3537
3538         u8         reserved_at_40[0x8];
3539         u8         tirn[0x18];
3540
3541         u8         reserved_at_60[0x20];
3542 };
3543
3544 struct mlx5_ifc_query_srq_out_bits {
3545         u8         status[0x8];
3546         u8         reserved_at_8[0x18];
3547
3548         u8         syndrome[0x20];
3549
3550         u8         reserved_at_40[0x40];
3551
3552         struct mlx5_ifc_srqc_bits srq_context_entry;
3553
3554         u8         reserved_at_280[0x600];
3555
3556         u8         pas[0][0x40];
3557 };
3558
3559 struct mlx5_ifc_query_srq_in_bits {
3560         u8         opcode[0x10];
3561         u8         reserved_at_10[0x10];
3562
3563         u8         reserved_at_20[0x10];
3564         u8         op_mod[0x10];
3565
3566         u8         reserved_at_40[0x8];
3567         u8         srqn[0x18];
3568
3569         u8         reserved_at_60[0x20];
3570 };
3571
3572 struct mlx5_ifc_query_sq_out_bits {
3573         u8         status[0x8];
3574         u8         reserved_at_8[0x18];
3575
3576         u8         syndrome[0x20];
3577
3578         u8         reserved_at_40[0xc0];
3579
3580         struct mlx5_ifc_sqc_bits sq_context;
3581 };
3582
3583 struct mlx5_ifc_query_sq_in_bits {
3584         u8         opcode[0x10];
3585         u8         reserved_at_10[0x10];
3586
3587         u8         reserved_at_20[0x10];
3588         u8         op_mod[0x10];
3589
3590         u8         reserved_at_40[0x8];
3591         u8         sqn[0x18];
3592
3593         u8         reserved_at_60[0x20];
3594 };
3595
3596 struct mlx5_ifc_query_special_contexts_out_bits {
3597         u8         status[0x8];
3598         u8         reserved_at_8[0x18];
3599
3600         u8         syndrome[0x20];
3601
3602         u8         dump_fill_mkey[0x20];
3603
3604         u8         resd_lkey[0x20];
3605
3606         u8         null_mkey[0x20];
3607
3608         u8         reserved_at_a0[0x60];
3609 };
3610
3611 struct mlx5_ifc_query_special_contexts_in_bits {
3612         u8         opcode[0x10];
3613         u8         reserved_at_10[0x10];
3614
3615         u8         reserved_at_20[0x10];
3616         u8         op_mod[0x10];
3617
3618         u8         reserved_at_40[0x40];
3619 };
3620
3621 struct mlx5_ifc_query_scheduling_element_out_bits {
3622         u8         opcode[0x10];
3623         u8         reserved_at_10[0x10];
3624
3625         u8         reserved_at_20[0x10];
3626         u8         op_mod[0x10];
3627
3628         u8         reserved_at_40[0xc0];
3629
3630         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3631
3632         u8         reserved_at_300[0x100];
3633 };
3634
3635 enum {
3636         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3637 };
3638
3639 struct mlx5_ifc_query_scheduling_element_in_bits {
3640         u8         opcode[0x10];
3641         u8         reserved_at_10[0x10];
3642
3643         u8         reserved_at_20[0x10];
3644         u8         op_mod[0x10];
3645
3646         u8         scheduling_hierarchy[0x8];
3647         u8         reserved_at_48[0x18];
3648
3649         u8         scheduling_element_id[0x20];
3650
3651         u8         reserved_at_80[0x180];
3652 };
3653
3654 struct mlx5_ifc_query_rqt_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_at_8[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_at_40[0xc0];
3661
3662         struct mlx5_ifc_rqtc_bits rqt_context;
3663 };
3664
3665 struct mlx5_ifc_query_rqt_in_bits {
3666         u8         opcode[0x10];
3667         u8         reserved_at_10[0x10];
3668
3669         u8         reserved_at_20[0x10];
3670         u8         op_mod[0x10];
3671
3672         u8         reserved_at_40[0x8];
3673         u8         rqtn[0x18];
3674
3675         u8         reserved_at_60[0x20];
3676 };
3677
3678 struct mlx5_ifc_query_rq_out_bits {
3679         u8         status[0x8];
3680         u8         reserved_at_8[0x18];
3681
3682         u8         syndrome[0x20];
3683
3684         u8         reserved_at_40[0xc0];
3685
3686         struct mlx5_ifc_rqc_bits rq_context;
3687 };
3688
3689 struct mlx5_ifc_query_rq_in_bits {
3690         u8         opcode[0x10];
3691         u8         reserved_at_10[0x10];
3692
3693         u8         reserved_at_20[0x10];
3694         u8         op_mod[0x10];
3695
3696         u8         reserved_at_40[0x8];
3697         u8         rqn[0x18];
3698
3699         u8         reserved_at_60[0x20];
3700 };
3701
3702 struct mlx5_ifc_query_roce_address_out_bits {
3703         u8         status[0x8];
3704         u8         reserved_at_8[0x18];
3705
3706         u8         syndrome[0x20];
3707
3708         u8         reserved_at_40[0x40];
3709
3710         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3711 };
3712
3713 struct mlx5_ifc_query_roce_address_in_bits {
3714         u8         opcode[0x10];
3715         u8         reserved_at_10[0x10];
3716
3717         u8         reserved_at_20[0x10];
3718         u8         op_mod[0x10];
3719
3720         u8         roce_address_index[0x10];
3721         u8         reserved_at_50[0x10];
3722
3723         u8         reserved_at_60[0x20];
3724 };
3725
3726 struct mlx5_ifc_query_rmp_out_bits {
3727         u8         status[0x8];
3728         u8         reserved_at_8[0x18];
3729
3730         u8         syndrome[0x20];
3731
3732         u8         reserved_at_40[0xc0];
3733
3734         struct mlx5_ifc_rmpc_bits rmp_context;
3735 };
3736
3737 struct mlx5_ifc_query_rmp_in_bits {
3738         u8         opcode[0x10];
3739         u8         reserved_at_10[0x10];
3740
3741         u8         reserved_at_20[0x10];
3742         u8         op_mod[0x10];
3743
3744         u8         reserved_at_40[0x8];
3745         u8         rmpn[0x18];
3746
3747         u8         reserved_at_60[0x20];
3748 };
3749
3750 struct mlx5_ifc_query_qp_out_bits {
3751         u8         status[0x8];
3752         u8         reserved_at_8[0x18];
3753
3754         u8         syndrome[0x20];
3755
3756         u8         reserved_at_40[0x40];
3757
3758         u8         opt_param_mask[0x20];
3759
3760         u8         reserved_at_a0[0x20];
3761
3762         struct mlx5_ifc_qpc_bits qpc;
3763
3764         u8         reserved_at_800[0x80];
3765
3766         u8         pas[0][0x40];
3767 };
3768
3769 struct mlx5_ifc_query_qp_in_bits {
3770         u8         opcode[0x10];
3771         u8         reserved_at_10[0x10];
3772
3773         u8         reserved_at_20[0x10];
3774         u8         op_mod[0x10];
3775
3776         u8         reserved_at_40[0x8];
3777         u8         qpn[0x18];
3778
3779         u8         reserved_at_60[0x20];
3780 };
3781
3782 struct mlx5_ifc_query_q_counter_out_bits {
3783         u8         status[0x8];
3784         u8         reserved_at_8[0x18];
3785
3786         u8         syndrome[0x20];
3787
3788         u8         reserved_at_40[0x40];
3789
3790         u8         rx_write_requests[0x20];
3791
3792         u8         reserved_at_a0[0x20];
3793
3794         u8         rx_read_requests[0x20];
3795
3796         u8         reserved_at_e0[0x20];
3797
3798         u8         rx_atomic_requests[0x20];
3799
3800         u8         reserved_at_120[0x20];
3801
3802         u8         rx_dct_connect[0x20];
3803
3804         u8         reserved_at_160[0x20];
3805
3806         u8         out_of_buffer[0x20];
3807
3808         u8         reserved_at_1a0[0x20];
3809
3810         u8         out_of_sequence[0x20];
3811
3812         u8         reserved_at_1e0[0x20];
3813
3814         u8         duplicate_request[0x20];
3815
3816         u8         reserved_at_220[0x20];
3817
3818         u8         rnr_nak_retry_err[0x20];
3819
3820         u8         reserved_at_260[0x20];
3821
3822         u8         packet_seq_err[0x20];
3823
3824         u8         reserved_at_2a0[0x20];
3825
3826         u8         implied_nak_seq_err[0x20];
3827
3828         u8         reserved_at_2e0[0x20];
3829
3830         u8         local_ack_timeout_err[0x20];
3831
3832         u8         reserved_at_320[0x4e0];
3833 };
3834
3835 struct mlx5_ifc_query_q_counter_in_bits {
3836         u8         opcode[0x10];
3837         u8         reserved_at_10[0x10];
3838
3839         u8         reserved_at_20[0x10];
3840         u8         op_mod[0x10];
3841
3842         u8         reserved_at_40[0x80];
3843
3844         u8         clear[0x1];
3845         u8         reserved_at_c1[0x1f];
3846
3847         u8         reserved_at_e0[0x18];
3848         u8         counter_set_id[0x8];
3849 };
3850
3851 struct mlx5_ifc_query_pages_out_bits {
3852         u8         status[0x8];
3853         u8         reserved_at_8[0x18];
3854
3855         u8         syndrome[0x20];
3856
3857         u8         reserved_at_40[0x10];
3858         u8         function_id[0x10];
3859
3860         u8         num_pages[0x20];
3861 };
3862
3863 enum {
3864         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3865         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3866         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3867 };
3868
3869 struct mlx5_ifc_query_pages_in_bits {
3870         u8         opcode[0x10];
3871         u8         reserved_at_10[0x10];
3872
3873         u8         reserved_at_20[0x10];
3874         u8         op_mod[0x10];
3875
3876         u8         reserved_at_40[0x10];
3877         u8         function_id[0x10];
3878
3879         u8         reserved_at_60[0x20];
3880 };
3881
3882 struct mlx5_ifc_query_nic_vport_context_out_bits {
3883         u8         status[0x8];
3884         u8         reserved_at_8[0x18];
3885
3886         u8         syndrome[0x20];
3887
3888         u8         reserved_at_40[0x40];
3889
3890         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3891 };
3892
3893 struct mlx5_ifc_query_nic_vport_context_in_bits {
3894         u8         opcode[0x10];
3895         u8         reserved_at_10[0x10];
3896
3897         u8         reserved_at_20[0x10];
3898         u8         op_mod[0x10];
3899
3900         u8         other_vport[0x1];
3901         u8         reserved_at_41[0xf];
3902         u8         vport_number[0x10];
3903
3904         u8         reserved_at_60[0x5];
3905         u8         allowed_list_type[0x3];
3906         u8         reserved_at_68[0x18];
3907 };
3908
3909 struct mlx5_ifc_query_mkey_out_bits {
3910         u8         status[0x8];
3911         u8         reserved_at_8[0x18];
3912
3913         u8         syndrome[0x20];
3914
3915         u8         reserved_at_40[0x40];
3916
3917         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3918
3919         u8         reserved_at_280[0x600];
3920
3921         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3922
3923         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3924 };
3925
3926 struct mlx5_ifc_query_mkey_in_bits {
3927         u8         opcode[0x10];
3928         u8         reserved_at_10[0x10];
3929
3930         u8         reserved_at_20[0x10];
3931         u8         op_mod[0x10];
3932
3933         u8         reserved_at_40[0x8];
3934         u8         mkey_index[0x18];
3935
3936         u8         pg_access[0x1];
3937         u8         reserved_at_61[0x1f];
3938 };
3939
3940 struct mlx5_ifc_query_mad_demux_out_bits {
3941         u8         status[0x8];
3942         u8         reserved_at_8[0x18];
3943
3944         u8         syndrome[0x20];
3945
3946         u8         reserved_at_40[0x40];
3947
3948         u8         mad_dumux_parameters_block[0x20];
3949 };
3950
3951 struct mlx5_ifc_query_mad_demux_in_bits {
3952         u8         opcode[0x10];
3953         u8         reserved_at_10[0x10];
3954
3955         u8         reserved_at_20[0x10];
3956         u8         op_mod[0x10];
3957
3958         u8         reserved_at_40[0x40];
3959 };
3960
3961 struct mlx5_ifc_query_l2_table_entry_out_bits {
3962         u8         status[0x8];
3963         u8         reserved_at_8[0x18];
3964
3965         u8         syndrome[0x20];
3966
3967         u8         reserved_at_40[0xa0];
3968
3969         u8         reserved_at_e0[0x13];
3970         u8         vlan_valid[0x1];
3971         u8         vlan[0xc];
3972
3973         struct mlx5_ifc_mac_address_layout_bits mac_address;
3974
3975         u8         reserved_at_140[0xc0];
3976 };
3977
3978 struct mlx5_ifc_query_l2_table_entry_in_bits {
3979         u8         opcode[0x10];
3980         u8         reserved_at_10[0x10];
3981
3982         u8         reserved_at_20[0x10];
3983         u8         op_mod[0x10];
3984
3985         u8         reserved_at_40[0x60];
3986
3987         u8         reserved_at_a0[0x8];
3988         u8         table_index[0x18];
3989
3990         u8         reserved_at_c0[0x140];
3991 };
3992
3993 struct mlx5_ifc_query_issi_out_bits {
3994         u8         status[0x8];
3995         u8         reserved_at_8[0x18];
3996
3997         u8         syndrome[0x20];
3998
3999         u8         reserved_at_40[0x10];
4000         u8         current_issi[0x10];
4001
4002         u8         reserved_at_60[0xa0];
4003
4004         u8         reserved_at_100[76][0x8];
4005         u8         supported_issi_dw0[0x20];
4006 };
4007
4008 struct mlx5_ifc_query_issi_in_bits {
4009         u8         opcode[0x10];
4010         u8         reserved_at_10[0x10];
4011
4012         u8         reserved_at_20[0x10];
4013         u8         op_mod[0x10];
4014
4015         u8         reserved_at_40[0x40];
4016 };
4017
4018 struct mlx5_ifc_set_driver_version_out_bits {
4019         u8         status[0x8];
4020         u8         reserved_0[0x18];
4021
4022         u8         syndrome[0x20];
4023         u8         reserved_1[0x40];
4024 };
4025
4026 struct mlx5_ifc_set_driver_version_in_bits {
4027         u8         opcode[0x10];
4028         u8         reserved_0[0x10];
4029
4030         u8         reserved_1[0x10];
4031         u8         op_mod[0x10];
4032
4033         u8         reserved_2[0x40];
4034         u8         driver_version[64][0x8];
4035 };
4036
4037 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4038         u8         status[0x8];
4039         u8         reserved_at_8[0x18];
4040
4041         u8         syndrome[0x20];
4042
4043         u8         reserved_at_40[0x40];
4044
4045         struct mlx5_ifc_pkey_bits pkey[0];
4046 };
4047
4048 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4049         u8         opcode[0x10];
4050         u8         reserved_at_10[0x10];
4051
4052         u8         reserved_at_20[0x10];
4053         u8         op_mod[0x10];
4054
4055         u8         other_vport[0x1];
4056         u8         reserved_at_41[0xb];
4057         u8         port_num[0x4];
4058         u8         vport_number[0x10];
4059
4060         u8         reserved_at_60[0x10];
4061         u8         pkey_index[0x10];
4062 };
4063
4064 enum {
4065         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4066         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4067         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4068 };
4069
4070 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4071         u8         status[0x8];
4072         u8         reserved_at_8[0x18];
4073
4074         u8         syndrome[0x20];
4075
4076         u8         reserved_at_40[0x20];
4077
4078         u8         gids_num[0x10];
4079         u8         reserved_at_70[0x10];
4080
4081         struct mlx5_ifc_array128_auto_bits gid[0];
4082 };
4083
4084 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4085         u8         opcode[0x10];
4086         u8         reserved_at_10[0x10];
4087
4088         u8         reserved_at_20[0x10];
4089         u8         op_mod[0x10];
4090
4091         u8         other_vport[0x1];
4092         u8         reserved_at_41[0xb];
4093         u8         port_num[0x4];
4094         u8         vport_number[0x10];
4095
4096         u8         reserved_at_60[0x10];
4097         u8         gid_index[0x10];
4098 };
4099
4100 struct mlx5_ifc_query_hca_vport_context_out_bits {
4101         u8         status[0x8];
4102         u8         reserved_at_8[0x18];
4103
4104         u8         syndrome[0x20];
4105
4106         u8         reserved_at_40[0x40];
4107
4108         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4109 };
4110
4111 struct mlx5_ifc_query_hca_vport_context_in_bits {
4112         u8         opcode[0x10];
4113         u8         reserved_at_10[0x10];
4114
4115         u8         reserved_at_20[0x10];
4116         u8         op_mod[0x10];
4117
4118         u8         other_vport[0x1];
4119         u8         reserved_at_41[0xb];
4120         u8         port_num[0x4];
4121         u8         vport_number[0x10];
4122
4123         u8         reserved_at_60[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_hca_cap_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_at_8[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_at_40[0x40];
4133
4134         union mlx5_ifc_hca_cap_union_bits capability;
4135 };
4136
4137 struct mlx5_ifc_query_hca_cap_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_at_10[0x10];
4140
4141         u8         reserved_at_20[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         reserved_at_40[0x40];
4145 };
4146
4147 struct mlx5_ifc_query_flow_table_out_bits {
4148         u8         status[0x8];
4149         u8         reserved_at_8[0x18];
4150
4151         u8         syndrome[0x20];
4152
4153         u8         reserved_at_40[0x80];
4154
4155         u8         reserved_at_c0[0x8];
4156         u8         level[0x8];
4157         u8         reserved_at_d0[0x8];
4158         u8         log_size[0x8];
4159
4160         u8         reserved_at_e0[0x120];
4161 };
4162
4163 struct mlx5_ifc_query_flow_table_in_bits {
4164         u8         opcode[0x10];
4165         u8         reserved_at_10[0x10];
4166
4167         u8         reserved_at_20[0x10];
4168         u8         op_mod[0x10];
4169
4170         u8         reserved_at_40[0x40];
4171
4172         u8         table_type[0x8];
4173         u8         reserved_at_88[0x18];
4174
4175         u8         reserved_at_a0[0x8];
4176         u8         table_id[0x18];
4177
4178         u8         reserved_at_c0[0x140];
4179 };
4180
4181 struct mlx5_ifc_query_fte_out_bits {
4182         u8         status[0x8];
4183         u8         reserved_at_8[0x18];
4184
4185         u8         syndrome[0x20];
4186
4187         u8         reserved_at_40[0x1c0];
4188
4189         struct mlx5_ifc_flow_context_bits flow_context;
4190 };
4191
4192 struct mlx5_ifc_query_fte_in_bits {
4193         u8         opcode[0x10];
4194         u8         reserved_at_10[0x10];
4195
4196         u8         reserved_at_20[0x10];
4197         u8         op_mod[0x10];
4198
4199         u8         reserved_at_40[0x40];
4200
4201         u8         table_type[0x8];
4202         u8         reserved_at_88[0x18];
4203
4204         u8         reserved_at_a0[0x8];
4205         u8         table_id[0x18];
4206
4207         u8         reserved_at_c0[0x40];
4208
4209         u8         flow_index[0x20];
4210
4211         u8         reserved_at_120[0xe0];
4212 };
4213
4214 enum {
4215         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4216         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4217         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4218 };
4219
4220 struct mlx5_ifc_query_flow_group_out_bits {
4221         u8         status[0x8];
4222         u8         reserved_at_8[0x18];
4223
4224         u8         syndrome[0x20];
4225
4226         u8         reserved_at_40[0xa0];
4227
4228         u8         start_flow_index[0x20];
4229
4230         u8         reserved_at_100[0x20];
4231
4232         u8         end_flow_index[0x20];
4233
4234         u8         reserved_at_140[0xa0];
4235
4236         u8         reserved_at_1e0[0x18];
4237         u8         match_criteria_enable[0x8];
4238
4239         struct mlx5_ifc_fte_match_param_bits match_criteria;
4240
4241         u8         reserved_at_1200[0xe00];
4242 };
4243
4244 struct mlx5_ifc_query_flow_group_in_bits {
4245         u8         opcode[0x10];
4246         u8         reserved_at_10[0x10];
4247
4248         u8         reserved_at_20[0x10];
4249         u8         op_mod[0x10];
4250
4251         u8         reserved_at_40[0x40];
4252
4253         u8         table_type[0x8];
4254         u8         reserved_at_88[0x18];
4255
4256         u8         reserved_at_a0[0x8];
4257         u8         table_id[0x18];
4258
4259         u8         group_id[0x20];
4260
4261         u8         reserved_at_e0[0x120];
4262 };
4263
4264 struct mlx5_ifc_query_flow_counter_out_bits {
4265         u8         status[0x8];
4266         u8         reserved_at_8[0x18];
4267
4268         u8         syndrome[0x20];
4269
4270         u8         reserved_at_40[0x40];
4271
4272         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4273 };
4274
4275 struct mlx5_ifc_query_flow_counter_in_bits {
4276         u8         opcode[0x10];
4277         u8         reserved_at_10[0x10];
4278
4279         u8         reserved_at_20[0x10];
4280         u8         op_mod[0x10];
4281
4282         u8         reserved_at_40[0x80];
4283
4284         u8         clear[0x1];
4285         u8         reserved_at_c1[0xf];
4286         u8         num_of_counters[0x10];
4287
4288         u8         reserved_at_e0[0x10];
4289         u8         flow_counter_id[0x10];
4290 };
4291
4292 struct mlx5_ifc_query_esw_vport_context_out_bits {
4293         u8         status[0x8];
4294         u8         reserved_at_8[0x18];
4295
4296         u8         syndrome[0x20];
4297
4298         u8         reserved_at_40[0x40];
4299
4300         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4301 };
4302
4303 struct mlx5_ifc_query_esw_vport_context_in_bits {
4304         u8         opcode[0x10];
4305         u8         reserved_at_10[0x10];
4306
4307         u8         reserved_at_20[0x10];
4308         u8         op_mod[0x10];
4309
4310         u8         other_vport[0x1];
4311         u8         reserved_at_41[0xf];
4312         u8         vport_number[0x10];
4313
4314         u8         reserved_at_60[0x20];
4315 };
4316
4317 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4318         u8         status[0x8];
4319         u8         reserved_at_8[0x18];
4320
4321         u8         syndrome[0x20];
4322
4323         u8         reserved_at_40[0x40];
4324 };
4325
4326 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4327         u8         reserved_at_0[0x1c];
4328         u8         vport_cvlan_insert[0x1];
4329         u8         vport_svlan_insert[0x1];
4330         u8         vport_cvlan_strip[0x1];
4331         u8         vport_svlan_strip[0x1];
4332 };
4333
4334 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4335         u8         opcode[0x10];
4336         u8         reserved_at_10[0x10];
4337
4338         u8         reserved_at_20[0x10];
4339         u8         op_mod[0x10];
4340
4341         u8         other_vport[0x1];
4342         u8         reserved_at_41[0xf];
4343         u8         vport_number[0x10];
4344
4345         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4346
4347         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4348 };
4349
4350 struct mlx5_ifc_query_eq_out_bits {
4351         u8         status[0x8];
4352         u8         reserved_at_8[0x18];
4353
4354         u8         syndrome[0x20];
4355
4356         u8         reserved_at_40[0x40];
4357
4358         struct mlx5_ifc_eqc_bits eq_context_entry;
4359
4360         u8         reserved_at_280[0x40];
4361
4362         u8         event_bitmask[0x40];
4363
4364         u8         reserved_at_300[0x580];
4365
4366         u8         pas[0][0x40];
4367 };
4368
4369 struct mlx5_ifc_query_eq_in_bits {
4370         u8         opcode[0x10];
4371         u8         reserved_at_10[0x10];
4372
4373         u8         reserved_at_20[0x10];
4374         u8         op_mod[0x10];
4375
4376         u8         reserved_at_40[0x18];
4377         u8         eq_number[0x8];
4378
4379         u8         reserved_at_60[0x20];
4380 };
4381
4382 struct mlx5_ifc_encap_header_in_bits {
4383         u8         reserved_at_0[0x5];
4384         u8         header_type[0x3];
4385         u8         reserved_at_8[0xe];
4386         u8         encap_header_size[0xa];
4387
4388         u8         reserved_at_20[0x10];
4389         u8         encap_header[2][0x8];
4390
4391         u8         more_encap_header[0][0x8];
4392 };
4393
4394 struct mlx5_ifc_query_encap_header_out_bits {
4395         u8         status[0x8];
4396         u8         reserved_at_8[0x18];
4397
4398         u8         syndrome[0x20];
4399
4400         u8         reserved_at_40[0xa0];
4401
4402         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4403 };
4404
4405 struct mlx5_ifc_query_encap_header_in_bits {
4406         u8         opcode[0x10];
4407         u8         reserved_at_10[0x10];
4408
4409         u8         reserved_at_20[0x10];
4410         u8         op_mod[0x10];
4411
4412         u8         encap_id[0x20];
4413
4414         u8         reserved_at_60[0xa0];
4415 };
4416
4417 struct mlx5_ifc_alloc_encap_header_out_bits {
4418         u8         status[0x8];
4419         u8         reserved_at_8[0x18];
4420
4421         u8         syndrome[0x20];
4422
4423         u8         encap_id[0x20];
4424
4425         u8         reserved_at_60[0x20];
4426 };
4427
4428 struct mlx5_ifc_alloc_encap_header_in_bits {
4429         u8         opcode[0x10];
4430         u8         reserved_at_10[0x10];
4431
4432         u8         reserved_at_20[0x10];
4433         u8         op_mod[0x10];
4434
4435         u8         reserved_at_40[0xa0];
4436
4437         struct mlx5_ifc_encap_header_in_bits encap_header;
4438 };
4439
4440 struct mlx5_ifc_dealloc_encap_header_out_bits {
4441         u8         status[0x8];
4442         u8         reserved_at_8[0x18];
4443
4444         u8         syndrome[0x20];
4445
4446         u8         reserved_at_40[0x40];
4447 };
4448
4449 struct mlx5_ifc_dealloc_encap_header_in_bits {
4450         u8         opcode[0x10];
4451         u8         reserved_at_10[0x10];
4452
4453         u8         reserved_20[0x10];
4454         u8         op_mod[0x10];
4455
4456         u8         encap_id[0x20];
4457
4458         u8         reserved_60[0x20];
4459 };
4460
4461 struct mlx5_ifc_query_dct_out_bits {
4462         u8         status[0x8];
4463         u8         reserved_at_8[0x18];
4464
4465         u8         syndrome[0x20];
4466
4467         u8         reserved_at_40[0x40];
4468
4469         struct mlx5_ifc_dctc_bits dct_context_entry;
4470
4471         u8         reserved_at_280[0x180];
4472 };
4473
4474 struct mlx5_ifc_query_dct_in_bits {
4475         u8         opcode[0x10];
4476         u8         reserved_at_10[0x10];
4477
4478         u8         reserved_at_20[0x10];
4479         u8         op_mod[0x10];
4480
4481         u8         reserved_at_40[0x8];
4482         u8         dctn[0x18];
4483
4484         u8         reserved_at_60[0x20];
4485 };
4486
4487 struct mlx5_ifc_query_cq_out_bits {
4488         u8         status[0x8];
4489         u8         reserved_at_8[0x18];
4490
4491         u8         syndrome[0x20];
4492
4493         u8         reserved_at_40[0x40];
4494
4495         struct mlx5_ifc_cqc_bits cq_context;
4496
4497         u8         reserved_at_280[0x600];
4498
4499         u8         pas[0][0x40];
4500 };
4501
4502 struct mlx5_ifc_query_cq_in_bits {
4503         u8         opcode[0x10];
4504         u8         reserved_at_10[0x10];
4505
4506         u8         reserved_at_20[0x10];
4507         u8         op_mod[0x10];
4508
4509         u8         reserved_at_40[0x8];
4510         u8         cqn[0x18];
4511
4512         u8         reserved_at_60[0x20];
4513 };
4514
4515 struct mlx5_ifc_query_cong_status_out_bits {
4516         u8         status[0x8];
4517         u8         reserved_at_8[0x18];
4518
4519         u8         syndrome[0x20];
4520
4521         u8         reserved_at_40[0x20];
4522
4523         u8         enable[0x1];
4524         u8         tag_enable[0x1];
4525         u8         reserved_at_62[0x1e];
4526 };
4527
4528 struct mlx5_ifc_query_cong_status_in_bits {
4529         u8         opcode[0x10];
4530         u8         reserved_at_10[0x10];
4531
4532         u8         reserved_at_20[0x10];
4533         u8         op_mod[0x10];
4534
4535         u8         reserved_at_40[0x18];
4536         u8         priority[0x4];
4537         u8         cong_protocol[0x4];
4538
4539         u8         reserved_at_60[0x20];
4540 };
4541
4542 struct mlx5_ifc_query_cong_statistics_out_bits {
4543         u8         status[0x8];
4544         u8         reserved_at_8[0x18];
4545
4546         u8         syndrome[0x20];
4547
4548         u8         reserved_at_40[0x40];
4549
4550         u8         cur_flows[0x20];
4551
4552         u8         sum_flows[0x20];
4553
4554         u8         cnp_ignored_high[0x20];
4555
4556         u8         cnp_ignored_low[0x20];
4557
4558         u8         cnp_handled_high[0x20];
4559
4560         u8         cnp_handled_low[0x20];
4561
4562         u8         reserved_at_140[0x100];
4563
4564         u8         time_stamp_high[0x20];
4565
4566         u8         time_stamp_low[0x20];
4567
4568         u8         accumulators_period[0x20];
4569
4570         u8         ecn_marked_roce_packets_high[0x20];
4571
4572         u8         ecn_marked_roce_packets_low[0x20];
4573
4574         u8         cnps_sent_high[0x20];
4575
4576         u8         cnps_sent_low[0x20];
4577
4578         u8         reserved_at_320[0x560];
4579 };
4580
4581 struct mlx5_ifc_query_cong_statistics_in_bits {
4582         u8         opcode[0x10];
4583         u8         reserved_at_10[0x10];
4584
4585         u8         reserved_at_20[0x10];
4586         u8         op_mod[0x10];
4587
4588         u8         clear[0x1];
4589         u8         reserved_at_41[0x1f];
4590
4591         u8         reserved_at_60[0x20];
4592 };
4593
4594 struct mlx5_ifc_query_cong_params_out_bits {
4595         u8         status[0x8];
4596         u8         reserved_at_8[0x18];
4597
4598         u8         syndrome[0x20];
4599
4600         u8         reserved_at_40[0x40];
4601
4602         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4603 };
4604
4605 struct mlx5_ifc_query_cong_params_in_bits {
4606         u8         opcode[0x10];
4607         u8         reserved_at_10[0x10];
4608
4609         u8         reserved_at_20[0x10];
4610         u8         op_mod[0x10];
4611
4612         u8         reserved_at_40[0x1c];
4613         u8         cong_protocol[0x4];
4614
4615         u8         reserved_at_60[0x20];
4616 };
4617
4618 struct mlx5_ifc_query_adapter_out_bits {
4619         u8         status[0x8];
4620         u8         reserved_at_8[0x18];
4621
4622         u8         syndrome[0x20];
4623
4624         u8         reserved_at_40[0x40];
4625
4626         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4627 };
4628
4629 struct mlx5_ifc_query_adapter_in_bits {
4630         u8         opcode[0x10];
4631         u8         reserved_at_10[0x10];
4632
4633         u8         reserved_at_20[0x10];
4634         u8         op_mod[0x10];
4635
4636         u8         reserved_at_40[0x40];
4637 };
4638
4639 struct mlx5_ifc_qp_2rst_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0x40];
4646 };
4647
4648 struct mlx5_ifc_qp_2rst_in_bits {
4649         u8         opcode[0x10];
4650         u8         reserved_at_10[0x10];
4651
4652         u8         reserved_at_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         reserved_at_40[0x8];
4656         u8         qpn[0x18];
4657
4658         u8         reserved_at_60[0x20];
4659 };
4660
4661 struct mlx5_ifc_qp_2err_out_bits {
4662         u8         status[0x8];
4663         u8         reserved_at_8[0x18];
4664
4665         u8         syndrome[0x20];
4666
4667         u8         reserved_at_40[0x40];
4668 };
4669
4670 struct mlx5_ifc_qp_2err_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_at_10[0x10];
4673
4674         u8         reserved_at_20[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         reserved_at_40[0x8];
4678         u8         qpn[0x18];
4679
4680         u8         reserved_at_60[0x20];
4681 };
4682
4683 struct mlx5_ifc_page_fault_resume_out_bits {
4684         u8         status[0x8];
4685         u8         reserved_at_8[0x18];
4686
4687         u8         syndrome[0x20];
4688
4689         u8         reserved_at_40[0x40];
4690 };
4691
4692 struct mlx5_ifc_page_fault_resume_in_bits {
4693         u8         opcode[0x10];
4694         u8         reserved_at_10[0x10];
4695
4696         u8         reserved_at_20[0x10];
4697         u8         op_mod[0x10];
4698
4699         u8         error[0x1];
4700         u8         reserved_at_41[0x4];
4701         u8         page_fault_type[0x3];
4702         u8         wq_number[0x18];
4703
4704         u8         reserved_at_60[0x8];
4705         u8         token[0x18];
4706 };
4707
4708 struct mlx5_ifc_nop_out_bits {
4709         u8         status[0x8];
4710         u8         reserved_at_8[0x18];
4711
4712         u8         syndrome[0x20];
4713
4714         u8         reserved_at_40[0x40];
4715 };
4716
4717 struct mlx5_ifc_nop_in_bits {
4718         u8         opcode[0x10];
4719         u8         reserved_at_10[0x10];
4720
4721         u8         reserved_at_20[0x10];
4722         u8         op_mod[0x10];
4723
4724         u8         reserved_at_40[0x40];
4725 };
4726
4727 struct mlx5_ifc_modify_vport_state_out_bits {
4728         u8         status[0x8];
4729         u8         reserved_at_8[0x18];
4730
4731         u8         syndrome[0x20];
4732
4733         u8         reserved_at_40[0x40];
4734 };
4735
4736 struct mlx5_ifc_modify_vport_state_in_bits {
4737         u8         opcode[0x10];
4738         u8         reserved_at_10[0x10];
4739
4740         u8         reserved_at_20[0x10];
4741         u8         op_mod[0x10];
4742
4743         u8         other_vport[0x1];
4744         u8         reserved_at_41[0xf];
4745         u8         vport_number[0x10];
4746
4747         u8         reserved_at_60[0x18];
4748         u8         admin_state[0x4];
4749         u8         reserved_at_7c[0x4];
4750 };
4751
4752 struct mlx5_ifc_modify_tis_out_bits {
4753         u8         status[0x8];
4754         u8         reserved_at_8[0x18];
4755
4756         u8         syndrome[0x20];
4757
4758         u8         reserved_at_40[0x40];
4759 };
4760
4761 struct mlx5_ifc_modify_tis_bitmask_bits {
4762         u8         reserved_at_0[0x20];
4763
4764         u8         reserved_at_20[0x1d];
4765         u8         lag_tx_port_affinity[0x1];
4766         u8         strict_lag_tx_port_affinity[0x1];
4767         u8         prio[0x1];
4768 };
4769
4770 struct mlx5_ifc_modify_tis_in_bits {
4771         u8         opcode[0x10];
4772         u8         reserved_at_10[0x10];
4773
4774         u8         reserved_at_20[0x10];
4775         u8         op_mod[0x10];
4776
4777         u8         reserved_at_40[0x8];
4778         u8         tisn[0x18];
4779
4780         u8         reserved_at_60[0x20];
4781
4782         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4783
4784         u8         reserved_at_c0[0x40];
4785
4786         struct mlx5_ifc_tisc_bits ctx;
4787 };
4788
4789 struct mlx5_ifc_modify_tir_bitmask_bits {
4790         u8         reserved_at_0[0x20];
4791
4792         u8         reserved_at_20[0x1b];
4793         u8         self_lb_en[0x1];
4794         u8         reserved_at_3c[0x1];
4795         u8         hash[0x1];
4796         u8         reserved_at_3e[0x1];
4797         u8         lro[0x1];
4798 };
4799
4800 struct mlx5_ifc_modify_tir_out_bits {
4801         u8         status[0x8];
4802         u8         reserved_at_8[0x18];
4803
4804         u8         syndrome[0x20];
4805
4806         u8         reserved_at_40[0x40];
4807 };
4808
4809 struct mlx5_ifc_modify_tir_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         reserved_at_40[0x8];
4817         u8         tirn[0x18];
4818
4819         u8         reserved_at_60[0x20];
4820
4821         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4822
4823         u8         reserved_at_c0[0x40];
4824
4825         struct mlx5_ifc_tirc_bits ctx;
4826 };
4827
4828 struct mlx5_ifc_modify_sq_out_bits {
4829         u8         status[0x8];
4830         u8         reserved_at_8[0x18];
4831
4832         u8         syndrome[0x20];
4833
4834         u8         reserved_at_40[0x40];
4835 };
4836
4837 struct mlx5_ifc_modify_sq_in_bits {
4838         u8         opcode[0x10];
4839         u8         reserved_at_10[0x10];
4840
4841         u8         reserved_at_20[0x10];
4842         u8         op_mod[0x10];
4843
4844         u8         sq_state[0x4];
4845         u8         reserved_at_44[0x4];
4846         u8         sqn[0x18];
4847
4848         u8         reserved_at_60[0x20];
4849
4850         u8         modify_bitmask[0x40];
4851
4852         u8         reserved_at_c0[0x40];
4853
4854         struct mlx5_ifc_sqc_bits ctx;
4855 };
4856
4857 struct mlx5_ifc_modify_scheduling_element_out_bits {
4858         u8         status[0x8];
4859         u8         reserved_at_8[0x18];
4860
4861         u8         syndrome[0x20];
4862
4863         u8         reserved_at_40[0x1c0];
4864 };
4865
4866 enum {
4867         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4868         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4869 };
4870
4871 struct mlx5_ifc_modify_scheduling_element_in_bits {
4872         u8         opcode[0x10];
4873         u8         reserved_at_10[0x10];
4874
4875         u8         reserved_at_20[0x10];
4876         u8         op_mod[0x10];
4877
4878         u8         scheduling_hierarchy[0x8];
4879         u8         reserved_at_48[0x18];
4880
4881         u8         scheduling_element_id[0x20];
4882
4883         u8         reserved_at_80[0x20];
4884
4885         u8         modify_bitmask[0x20];
4886
4887         u8         reserved_at_c0[0x40];
4888
4889         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4890
4891         u8         reserved_at_300[0x100];
4892 };
4893
4894 struct mlx5_ifc_modify_rqt_out_bits {
4895         u8         status[0x8];
4896         u8         reserved_at_8[0x18];
4897
4898         u8         syndrome[0x20];
4899
4900         u8         reserved_at_40[0x40];
4901 };
4902
4903 struct mlx5_ifc_rqt_bitmask_bits {
4904         u8         reserved_at_0[0x20];
4905
4906         u8         reserved_at_20[0x1f];
4907         u8         rqn_list[0x1];
4908 };
4909
4910 struct mlx5_ifc_modify_rqt_in_bits {
4911         u8         opcode[0x10];
4912         u8         reserved_at_10[0x10];
4913
4914         u8         reserved_at_20[0x10];
4915         u8         op_mod[0x10];
4916
4917         u8         reserved_at_40[0x8];
4918         u8         rqtn[0x18];
4919
4920         u8         reserved_at_60[0x20];
4921
4922         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4923
4924         u8         reserved_at_c0[0x40];
4925
4926         struct mlx5_ifc_rqtc_bits ctx;
4927 };
4928
4929 struct mlx5_ifc_modify_rq_out_bits {
4930         u8         status[0x8];
4931         u8         reserved_at_8[0x18];
4932
4933         u8         syndrome[0x20];
4934
4935         u8         reserved_at_40[0x40];
4936 };
4937
4938 enum {
4939         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4940         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4941 };
4942
4943 struct mlx5_ifc_modify_rq_in_bits {
4944         u8         opcode[0x10];
4945         u8         reserved_at_10[0x10];
4946
4947         u8         reserved_at_20[0x10];
4948         u8         op_mod[0x10];
4949
4950         u8         rq_state[0x4];
4951         u8         reserved_at_44[0x4];
4952         u8         rqn[0x18];
4953
4954         u8         reserved_at_60[0x20];
4955
4956         u8         modify_bitmask[0x40];
4957
4958         u8         reserved_at_c0[0x40];
4959
4960         struct mlx5_ifc_rqc_bits ctx;
4961 };
4962
4963 struct mlx5_ifc_modify_rmp_out_bits {
4964         u8         status[0x8];
4965         u8         reserved_at_8[0x18];
4966
4967         u8         syndrome[0x20];
4968
4969         u8         reserved_at_40[0x40];
4970 };
4971
4972 struct mlx5_ifc_rmp_bitmask_bits {
4973         u8         reserved_at_0[0x20];
4974
4975         u8         reserved_at_20[0x1f];
4976         u8         lwm[0x1];
4977 };
4978
4979 struct mlx5_ifc_modify_rmp_in_bits {
4980         u8         opcode[0x10];
4981         u8         reserved_at_10[0x10];
4982
4983         u8         reserved_at_20[0x10];
4984         u8         op_mod[0x10];
4985
4986         u8         rmp_state[0x4];
4987         u8         reserved_at_44[0x4];
4988         u8         rmpn[0x18];
4989
4990         u8         reserved_at_60[0x20];
4991
4992         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4993
4994         u8         reserved_at_c0[0x40];
4995
4996         struct mlx5_ifc_rmpc_bits ctx;
4997 };
4998
4999 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5000         u8         status[0x8];
5001         u8         reserved_at_8[0x18];
5002
5003         u8         syndrome[0x20];
5004
5005         u8         reserved_at_40[0x40];
5006 };
5007
5008 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5009         u8         reserved_at_0[0x16];
5010         u8         node_guid[0x1];
5011         u8         port_guid[0x1];
5012         u8         min_inline[0x1];
5013         u8         mtu[0x1];
5014         u8         change_event[0x1];
5015         u8         promisc[0x1];
5016         u8         permanent_address[0x1];
5017         u8         addresses_list[0x1];
5018         u8         roce_en[0x1];
5019         u8         reserved_at_1f[0x1];
5020 };
5021
5022 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5023         u8         opcode[0x10];
5024         u8         reserved_at_10[0x10];
5025
5026         u8         reserved_at_20[0x10];
5027         u8         op_mod[0x10];
5028
5029         u8         other_vport[0x1];
5030         u8         reserved_at_41[0xf];
5031         u8         vport_number[0x10];
5032
5033         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5034
5035         u8         reserved_at_80[0x780];
5036
5037         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5038 };
5039
5040 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5041         u8         status[0x8];
5042         u8         reserved_at_8[0x18];
5043
5044         u8         syndrome[0x20];
5045
5046         u8         reserved_at_40[0x40];
5047 };
5048
5049 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5050         u8         opcode[0x10];
5051         u8         reserved_at_10[0x10];
5052
5053         u8         reserved_at_20[0x10];
5054         u8         op_mod[0x10];
5055
5056         u8         other_vport[0x1];
5057         u8         reserved_at_41[0xb];
5058         u8         port_num[0x4];
5059         u8         vport_number[0x10];
5060
5061         u8         reserved_at_60[0x20];
5062
5063         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5064 };
5065
5066 struct mlx5_ifc_modify_cq_out_bits {
5067         u8         status[0x8];
5068         u8         reserved_at_8[0x18];
5069
5070         u8         syndrome[0x20];
5071
5072         u8         reserved_at_40[0x40];
5073 };
5074
5075 enum {
5076         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5077         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5078 };
5079
5080 struct mlx5_ifc_modify_cq_in_bits {
5081         u8         opcode[0x10];
5082         u8         reserved_at_10[0x10];
5083
5084         u8         reserved_at_20[0x10];
5085         u8         op_mod[0x10];
5086
5087         u8         reserved_at_40[0x8];
5088         u8         cqn[0x18];
5089
5090         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5091
5092         struct mlx5_ifc_cqc_bits cq_context;
5093
5094         u8         reserved_at_280[0x600];
5095
5096         u8         pas[0][0x40];
5097 };
5098
5099 struct mlx5_ifc_modify_cong_status_out_bits {
5100         u8         status[0x8];
5101         u8         reserved_at_8[0x18];
5102
5103         u8         syndrome[0x20];
5104
5105         u8         reserved_at_40[0x40];
5106 };
5107
5108 struct mlx5_ifc_modify_cong_status_in_bits {
5109         u8         opcode[0x10];
5110         u8         reserved_at_10[0x10];
5111
5112         u8         reserved_at_20[0x10];
5113         u8         op_mod[0x10];
5114
5115         u8         reserved_at_40[0x18];
5116         u8         priority[0x4];
5117         u8         cong_protocol[0x4];
5118
5119         u8         enable[0x1];
5120         u8         tag_enable[0x1];
5121         u8         reserved_at_62[0x1e];
5122 };
5123
5124 struct mlx5_ifc_modify_cong_params_out_bits {
5125         u8         status[0x8];
5126         u8         reserved_at_8[0x18];
5127
5128         u8         syndrome[0x20];
5129
5130         u8         reserved_at_40[0x40];
5131 };
5132
5133 struct mlx5_ifc_modify_cong_params_in_bits {
5134         u8         opcode[0x10];
5135         u8         reserved_at_10[0x10];
5136
5137         u8         reserved_at_20[0x10];
5138         u8         op_mod[0x10];
5139
5140         u8         reserved_at_40[0x1c];
5141         u8         cong_protocol[0x4];
5142
5143         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5144
5145         u8         reserved_at_80[0x80];
5146
5147         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5148 };
5149
5150 struct mlx5_ifc_manage_pages_out_bits {
5151         u8         status[0x8];
5152         u8         reserved_at_8[0x18];
5153
5154         u8         syndrome[0x20];
5155
5156         u8         output_num_entries[0x20];
5157
5158         u8         reserved_at_60[0x20];
5159
5160         u8         pas[0][0x40];
5161 };
5162
5163 enum {
5164         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5165         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5166         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5167 };
5168
5169 struct mlx5_ifc_manage_pages_in_bits {
5170         u8         opcode[0x10];
5171         u8         reserved_at_10[0x10];
5172
5173         u8         reserved_at_20[0x10];
5174         u8         op_mod[0x10];
5175
5176         u8         reserved_at_40[0x10];
5177         u8         function_id[0x10];
5178
5179         u8         input_num_entries[0x20];
5180
5181         u8         pas[0][0x40];
5182 };
5183
5184 struct mlx5_ifc_mad_ifc_out_bits {
5185         u8         status[0x8];
5186         u8         reserved_at_8[0x18];
5187
5188         u8         syndrome[0x20];
5189
5190         u8         reserved_at_40[0x40];
5191
5192         u8         response_mad_packet[256][0x8];
5193 };
5194
5195 struct mlx5_ifc_mad_ifc_in_bits {
5196         u8         opcode[0x10];
5197         u8         reserved_at_10[0x10];
5198
5199         u8         reserved_at_20[0x10];
5200         u8         op_mod[0x10];
5201
5202         u8         remote_lid[0x10];
5203         u8         reserved_at_50[0x8];
5204         u8         port[0x8];
5205
5206         u8         reserved_at_60[0x20];
5207
5208         u8         mad[256][0x8];
5209 };
5210
5211 struct mlx5_ifc_init_hca_out_bits {
5212         u8         status[0x8];
5213         u8         reserved_at_8[0x18];
5214
5215         u8         syndrome[0x20];
5216
5217         u8         reserved_at_40[0x40];
5218 };
5219
5220 struct mlx5_ifc_init_hca_in_bits {
5221         u8         opcode[0x10];
5222         u8         reserved_at_10[0x10];
5223
5224         u8         reserved_at_20[0x10];
5225         u8         op_mod[0x10];
5226
5227         u8         reserved_at_40[0x40];
5228 };
5229
5230 struct mlx5_ifc_init2rtr_qp_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         reserved_at_40[0x40];
5237 };
5238
5239 struct mlx5_ifc_init2rtr_qp_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x8];
5247         u8         qpn[0x18];
5248
5249         u8         reserved_at_60[0x20];
5250
5251         u8         opt_param_mask[0x20];
5252
5253         u8         reserved_at_a0[0x20];
5254
5255         struct mlx5_ifc_qpc_bits qpc;
5256
5257         u8         reserved_at_800[0x80];
5258 };
5259
5260 struct mlx5_ifc_init2init_qp_out_bits {
5261         u8         status[0x8];
5262         u8         reserved_at_8[0x18];
5263
5264         u8         syndrome[0x20];
5265
5266         u8         reserved_at_40[0x40];
5267 };
5268
5269 struct mlx5_ifc_init2init_qp_in_bits {
5270         u8         opcode[0x10];
5271         u8         reserved_at_10[0x10];
5272
5273         u8         reserved_at_20[0x10];
5274         u8         op_mod[0x10];
5275
5276         u8         reserved_at_40[0x8];
5277         u8         qpn[0x18];
5278
5279         u8         reserved_at_60[0x20];
5280
5281         u8         opt_param_mask[0x20];
5282
5283         u8         reserved_at_a0[0x20];
5284
5285         struct mlx5_ifc_qpc_bits qpc;
5286
5287         u8         reserved_at_800[0x80];
5288 };
5289
5290 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5291         u8         status[0x8];
5292         u8         reserved_at_8[0x18];
5293
5294         u8         syndrome[0x20];
5295
5296         u8         reserved_at_40[0x40];
5297
5298         u8         packet_headers_log[128][0x8];
5299
5300         u8         packet_syndrome[64][0x8];
5301 };
5302
5303 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5304         u8         opcode[0x10];
5305         u8         reserved_at_10[0x10];
5306
5307         u8         reserved_at_20[0x10];
5308         u8         op_mod[0x10];
5309
5310         u8         reserved_at_40[0x40];
5311 };
5312
5313 struct mlx5_ifc_gen_eqe_in_bits {
5314         u8         opcode[0x10];
5315         u8         reserved_at_10[0x10];
5316
5317         u8         reserved_at_20[0x10];
5318         u8         op_mod[0x10];
5319
5320         u8         reserved_at_40[0x18];
5321         u8         eq_number[0x8];
5322
5323         u8         reserved_at_60[0x20];
5324
5325         u8         eqe[64][0x8];
5326 };
5327
5328 struct mlx5_ifc_gen_eq_out_bits {
5329         u8         status[0x8];
5330         u8         reserved_at_8[0x18];
5331
5332         u8         syndrome[0x20];
5333
5334         u8         reserved_at_40[0x40];
5335 };
5336
5337 struct mlx5_ifc_enable_hca_out_bits {
5338         u8         status[0x8];
5339         u8         reserved_at_8[0x18];
5340
5341         u8         syndrome[0x20];
5342
5343         u8         reserved_at_40[0x20];
5344 };
5345
5346 struct mlx5_ifc_enable_hca_in_bits {
5347         u8         opcode[0x10];
5348         u8         reserved_at_10[0x10];
5349
5350         u8         reserved_at_20[0x10];
5351         u8         op_mod[0x10];
5352
5353         u8         reserved_at_40[0x10];
5354         u8         function_id[0x10];
5355
5356         u8         reserved_at_60[0x20];
5357 };
5358
5359 struct mlx5_ifc_drain_dct_out_bits {
5360         u8         status[0x8];
5361         u8         reserved_at_8[0x18];
5362
5363         u8         syndrome[0x20];
5364
5365         u8         reserved_at_40[0x40];
5366 };
5367
5368 struct mlx5_ifc_drain_dct_in_bits {
5369         u8         opcode[0x10];
5370         u8         reserved_at_10[0x10];
5371
5372         u8         reserved_at_20[0x10];
5373         u8         op_mod[0x10];
5374
5375         u8         reserved_at_40[0x8];
5376         u8         dctn[0x18];
5377
5378         u8         reserved_at_60[0x20];
5379 };
5380
5381 struct mlx5_ifc_disable_hca_out_bits {
5382         u8         status[0x8];
5383         u8         reserved_at_8[0x18];
5384
5385         u8         syndrome[0x20];
5386
5387         u8         reserved_at_40[0x20];
5388 };
5389
5390 struct mlx5_ifc_disable_hca_in_bits {
5391         u8         opcode[0x10];
5392         u8         reserved_at_10[0x10];
5393
5394         u8         reserved_at_20[0x10];
5395         u8         op_mod[0x10];
5396
5397         u8         reserved_at_40[0x10];
5398         u8         function_id[0x10];
5399
5400         u8         reserved_at_60[0x20];
5401 };
5402
5403 struct mlx5_ifc_detach_from_mcg_out_bits {
5404         u8         status[0x8];
5405         u8         reserved_at_8[0x18];
5406
5407         u8         syndrome[0x20];
5408
5409         u8         reserved_at_40[0x40];
5410 };
5411
5412 struct mlx5_ifc_detach_from_mcg_in_bits {
5413         u8         opcode[0x10];
5414         u8         reserved_at_10[0x10];
5415
5416         u8         reserved_at_20[0x10];
5417         u8         op_mod[0x10];
5418
5419         u8         reserved_at_40[0x8];
5420         u8         qpn[0x18];
5421
5422         u8         reserved_at_60[0x20];
5423
5424         u8         multicast_gid[16][0x8];
5425 };
5426
5427 struct mlx5_ifc_destroy_xrq_out_bits {
5428         u8         status[0x8];
5429         u8         reserved_at_8[0x18];
5430
5431         u8         syndrome[0x20];
5432
5433         u8         reserved_at_40[0x40];
5434 };
5435
5436 struct mlx5_ifc_destroy_xrq_in_bits {
5437         u8         opcode[0x10];
5438         u8         reserved_at_10[0x10];
5439
5440         u8         reserved_at_20[0x10];
5441         u8         op_mod[0x10];
5442
5443         u8         reserved_at_40[0x8];
5444         u8         xrqn[0x18];
5445
5446         u8         reserved_at_60[0x20];
5447 };
5448
5449 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5450         u8         status[0x8];
5451         u8         reserved_at_8[0x18];
5452
5453         u8         syndrome[0x20];
5454
5455         u8         reserved_at_40[0x40];
5456 };
5457
5458 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5459         u8         opcode[0x10];
5460         u8         reserved_at_10[0x10];
5461
5462         u8         reserved_at_20[0x10];
5463         u8         op_mod[0x10];
5464
5465         u8         reserved_at_40[0x8];
5466         u8         xrc_srqn[0x18];
5467
5468         u8         reserved_at_60[0x20];
5469 };
5470
5471 struct mlx5_ifc_destroy_tis_out_bits {
5472         u8         status[0x8];
5473         u8         reserved_at_8[0x18];
5474
5475         u8         syndrome[0x20];
5476
5477         u8         reserved_at_40[0x40];
5478 };
5479
5480 struct mlx5_ifc_destroy_tis_in_bits {
5481         u8         opcode[0x10];
5482         u8         reserved_at_10[0x10];
5483
5484         u8         reserved_at_20[0x10];
5485         u8         op_mod[0x10];
5486
5487         u8         reserved_at_40[0x8];
5488         u8         tisn[0x18];
5489
5490         u8         reserved_at_60[0x20];
5491 };
5492
5493 struct mlx5_ifc_destroy_tir_out_bits {
5494         u8         status[0x8];
5495         u8         reserved_at_8[0x18];
5496
5497         u8         syndrome[0x20];
5498
5499         u8         reserved_at_40[0x40];
5500 };
5501
5502 struct mlx5_ifc_destroy_tir_in_bits {
5503         u8         opcode[0x10];
5504         u8         reserved_at_10[0x10];
5505
5506         u8         reserved_at_20[0x10];
5507         u8         op_mod[0x10];
5508
5509         u8         reserved_at_40[0x8];
5510         u8         tirn[0x18];
5511
5512         u8         reserved_at_60[0x20];
5513 };
5514
5515 struct mlx5_ifc_destroy_srq_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_at_8[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_at_40[0x40];
5522 };
5523
5524 struct mlx5_ifc_destroy_srq_in_bits {
5525         u8         opcode[0x10];
5526         u8         reserved_at_10[0x10];
5527
5528         u8         reserved_at_20[0x10];
5529         u8         op_mod[0x10];
5530
5531         u8         reserved_at_40[0x8];
5532         u8         srqn[0x18];
5533
5534         u8         reserved_at_60[0x20];
5535 };
5536
5537 struct mlx5_ifc_destroy_sq_out_bits {
5538         u8         status[0x8];
5539         u8         reserved_at_8[0x18];
5540
5541         u8         syndrome[0x20];
5542
5543         u8         reserved_at_40[0x40];
5544 };
5545
5546 struct mlx5_ifc_destroy_sq_in_bits {
5547         u8         opcode[0x10];
5548         u8         reserved_at_10[0x10];
5549
5550         u8         reserved_at_20[0x10];
5551         u8         op_mod[0x10];
5552
5553         u8         reserved_at_40[0x8];
5554         u8         sqn[0x18];
5555
5556         u8         reserved_at_60[0x20];
5557 };
5558
5559 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5560         u8         status[0x8];
5561         u8         reserved_at_8[0x18];
5562
5563         u8         syndrome[0x20];
5564
5565         u8         reserved_at_40[0x1c0];
5566 };
5567
5568 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5569         u8         opcode[0x10];
5570         u8         reserved_at_10[0x10];
5571
5572         u8         reserved_at_20[0x10];
5573         u8         op_mod[0x10];
5574
5575         u8         scheduling_hierarchy[0x8];
5576         u8         reserved_at_48[0x18];
5577
5578         u8         scheduling_element_id[0x20];
5579
5580         u8         reserved_at_80[0x180];
5581 };
5582
5583 struct mlx5_ifc_destroy_rqt_out_bits {
5584         u8         status[0x8];
5585         u8         reserved_at_8[0x18];
5586
5587         u8         syndrome[0x20];
5588
5589         u8         reserved_at_40[0x40];
5590 };
5591
5592 struct mlx5_ifc_destroy_rqt_in_bits {
5593         u8         opcode[0x10];
5594         u8         reserved_at_10[0x10];
5595
5596         u8         reserved_at_20[0x10];
5597         u8         op_mod[0x10];
5598
5599         u8         reserved_at_40[0x8];
5600         u8         rqtn[0x18];
5601
5602         u8         reserved_at_60[0x20];
5603 };
5604
5605 struct mlx5_ifc_destroy_rq_out_bits {
5606         u8         status[0x8];
5607         u8         reserved_at_8[0x18];
5608
5609         u8         syndrome[0x20];
5610
5611         u8         reserved_at_40[0x40];
5612 };
5613
5614 struct mlx5_ifc_destroy_rq_in_bits {
5615         u8         opcode[0x10];
5616         u8         reserved_at_10[0x10];
5617
5618         u8         reserved_at_20[0x10];
5619         u8         op_mod[0x10];
5620
5621         u8         reserved_at_40[0x8];
5622         u8         rqn[0x18];
5623
5624         u8         reserved_at_60[0x20];
5625 };
5626
5627 struct mlx5_ifc_destroy_rmp_out_bits {
5628         u8         status[0x8];
5629         u8         reserved_at_8[0x18];
5630
5631         u8         syndrome[0x20];
5632
5633         u8         reserved_at_40[0x40];
5634 };
5635
5636 struct mlx5_ifc_destroy_rmp_in_bits {
5637         u8         opcode[0x10];
5638         u8         reserved_at_10[0x10];
5639
5640         u8         reserved_at_20[0x10];
5641         u8         op_mod[0x10];
5642
5643         u8         reserved_at_40[0x8];
5644         u8         rmpn[0x18];
5645
5646         u8         reserved_at_60[0x20];
5647 };
5648
5649 struct mlx5_ifc_destroy_qp_out_bits {
5650         u8         status[0x8];
5651         u8         reserved_at_8[0x18];
5652
5653         u8         syndrome[0x20];
5654
5655         u8         reserved_at_40[0x40];
5656 };
5657
5658 struct mlx5_ifc_destroy_qp_in_bits {
5659         u8         opcode[0x10];
5660         u8         reserved_at_10[0x10];
5661
5662         u8         reserved_at_20[0x10];
5663         u8         op_mod[0x10];
5664
5665         u8         reserved_at_40[0x8];
5666         u8         qpn[0x18];
5667
5668         u8         reserved_at_60[0x20];
5669 };
5670
5671 struct mlx5_ifc_destroy_psv_out_bits {
5672         u8         status[0x8];
5673         u8         reserved_at_8[0x18];
5674
5675         u8         syndrome[0x20];
5676
5677         u8         reserved_at_40[0x40];
5678 };
5679
5680 struct mlx5_ifc_destroy_psv_in_bits {
5681         u8         opcode[0x10];
5682         u8         reserved_at_10[0x10];
5683
5684         u8         reserved_at_20[0x10];
5685         u8         op_mod[0x10];
5686
5687         u8         reserved_at_40[0x8];
5688         u8         psvn[0x18];
5689
5690         u8         reserved_at_60[0x20];
5691 };
5692
5693 struct mlx5_ifc_destroy_mkey_out_bits {
5694         u8         status[0x8];
5695         u8         reserved_at_8[0x18];
5696
5697         u8         syndrome[0x20];
5698
5699         u8         reserved_at_40[0x40];
5700 };
5701
5702 struct mlx5_ifc_destroy_mkey_in_bits {
5703         u8         opcode[0x10];
5704         u8         reserved_at_10[0x10];
5705
5706         u8         reserved_at_20[0x10];
5707         u8         op_mod[0x10];
5708
5709         u8         reserved_at_40[0x8];
5710         u8         mkey_index[0x18];
5711
5712         u8         reserved_at_60[0x20];
5713 };
5714
5715 struct mlx5_ifc_destroy_flow_table_out_bits {
5716         u8         status[0x8];
5717         u8         reserved_at_8[0x18];
5718
5719         u8         syndrome[0x20];
5720
5721         u8         reserved_at_40[0x40];
5722 };
5723
5724 struct mlx5_ifc_destroy_flow_table_in_bits {
5725         u8         opcode[0x10];
5726         u8         reserved_at_10[0x10];
5727
5728         u8         reserved_at_20[0x10];
5729         u8         op_mod[0x10];
5730
5731         u8         other_vport[0x1];
5732         u8         reserved_at_41[0xf];
5733         u8         vport_number[0x10];
5734
5735         u8         reserved_at_60[0x20];
5736
5737         u8         table_type[0x8];
5738         u8         reserved_at_88[0x18];
5739
5740         u8         reserved_at_a0[0x8];
5741         u8         table_id[0x18];
5742
5743         u8         reserved_at_c0[0x140];
5744 };
5745
5746 struct mlx5_ifc_destroy_flow_group_out_bits {
5747         u8         status[0x8];
5748         u8         reserved_at_8[0x18];
5749
5750         u8         syndrome[0x20];
5751
5752         u8         reserved_at_40[0x40];
5753 };
5754
5755 struct mlx5_ifc_destroy_flow_group_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         other_vport[0x1];
5763         u8         reserved_at_41[0xf];
5764         u8         vport_number[0x10];
5765
5766         u8         reserved_at_60[0x20];
5767
5768         u8         table_type[0x8];
5769         u8         reserved_at_88[0x18];
5770
5771         u8         reserved_at_a0[0x8];
5772         u8         table_id[0x18];
5773
5774         u8         group_id[0x20];
5775
5776         u8         reserved_at_e0[0x120];
5777 };
5778
5779 struct mlx5_ifc_destroy_eq_out_bits {
5780         u8         status[0x8];
5781         u8         reserved_at_8[0x18];
5782
5783         u8         syndrome[0x20];
5784
5785         u8         reserved_at_40[0x40];
5786 };
5787
5788 struct mlx5_ifc_destroy_eq_in_bits {
5789         u8         opcode[0x10];
5790         u8         reserved_at_10[0x10];
5791
5792         u8         reserved_at_20[0x10];
5793         u8         op_mod[0x10];
5794
5795         u8         reserved_at_40[0x18];
5796         u8         eq_number[0x8];
5797
5798         u8         reserved_at_60[0x20];
5799 };
5800
5801 struct mlx5_ifc_destroy_dct_out_bits {
5802         u8         status[0x8];
5803         u8         reserved_at_8[0x18];
5804
5805         u8         syndrome[0x20];
5806
5807         u8         reserved_at_40[0x40];
5808 };
5809
5810 struct mlx5_ifc_destroy_dct_in_bits {
5811         u8         opcode[0x10];
5812         u8         reserved_at_10[0x10];
5813
5814         u8         reserved_at_20[0x10];
5815         u8         op_mod[0x10];
5816
5817         u8         reserved_at_40[0x8];
5818         u8         dctn[0x18];
5819
5820         u8         reserved_at_60[0x20];
5821 };
5822
5823 struct mlx5_ifc_destroy_cq_out_bits {
5824         u8         status[0x8];
5825         u8         reserved_at_8[0x18];
5826
5827         u8         syndrome[0x20];
5828
5829         u8         reserved_at_40[0x40];
5830 };
5831
5832 struct mlx5_ifc_destroy_cq_in_bits {
5833         u8         opcode[0x10];
5834         u8         reserved_at_10[0x10];
5835
5836         u8         reserved_at_20[0x10];
5837         u8         op_mod[0x10];
5838
5839         u8         reserved_at_40[0x8];
5840         u8         cqn[0x18];
5841
5842         u8         reserved_at_60[0x20];
5843 };
5844
5845 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5846         u8         status[0x8];
5847         u8         reserved_at_8[0x18];
5848
5849         u8         syndrome[0x20];
5850
5851         u8         reserved_at_40[0x40];
5852 };
5853
5854 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5855         u8         opcode[0x10];
5856         u8         reserved_at_10[0x10];
5857
5858         u8         reserved_at_20[0x10];
5859         u8         op_mod[0x10];
5860
5861         u8         reserved_at_40[0x20];
5862
5863         u8         reserved_at_60[0x10];
5864         u8         vxlan_udp_port[0x10];
5865 };
5866
5867 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5868         u8         status[0x8];
5869         u8         reserved_at_8[0x18];
5870
5871         u8         syndrome[0x20];
5872
5873         u8         reserved_at_40[0x40];
5874 };
5875
5876 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5877         u8         opcode[0x10];
5878         u8         reserved_at_10[0x10];
5879
5880         u8         reserved_at_20[0x10];
5881         u8         op_mod[0x10];
5882
5883         u8         reserved_at_40[0x60];
5884
5885         u8         reserved_at_a0[0x8];
5886         u8         table_index[0x18];
5887
5888         u8         reserved_at_c0[0x140];
5889 };
5890
5891 struct mlx5_ifc_delete_fte_out_bits {
5892         u8         status[0x8];
5893         u8         reserved_at_8[0x18];
5894
5895         u8         syndrome[0x20];
5896
5897         u8         reserved_at_40[0x40];
5898 };
5899
5900 struct mlx5_ifc_delete_fte_in_bits {
5901         u8         opcode[0x10];
5902         u8         reserved_at_10[0x10];
5903
5904         u8         reserved_at_20[0x10];
5905         u8         op_mod[0x10];
5906
5907         u8         other_vport[0x1];
5908         u8         reserved_at_41[0xf];
5909         u8         vport_number[0x10];
5910
5911         u8         reserved_at_60[0x20];
5912
5913         u8         table_type[0x8];
5914         u8         reserved_at_88[0x18];
5915
5916         u8         reserved_at_a0[0x8];
5917         u8         table_id[0x18];
5918
5919         u8         reserved_at_c0[0x40];
5920
5921         u8         flow_index[0x20];
5922
5923         u8         reserved_at_120[0xe0];
5924 };
5925
5926 struct mlx5_ifc_dealloc_xrcd_out_bits {
5927         u8         status[0x8];
5928         u8         reserved_at_8[0x18];
5929
5930         u8         syndrome[0x20];
5931
5932         u8         reserved_at_40[0x40];
5933 };
5934
5935 struct mlx5_ifc_dealloc_xrcd_in_bits {
5936         u8         opcode[0x10];
5937         u8         reserved_at_10[0x10];
5938
5939         u8         reserved_at_20[0x10];
5940         u8         op_mod[0x10];
5941
5942         u8         reserved_at_40[0x8];
5943         u8         xrcd[0x18];
5944
5945         u8         reserved_at_60[0x20];
5946 };
5947
5948 struct mlx5_ifc_dealloc_uar_out_bits {
5949         u8         status[0x8];
5950         u8         reserved_at_8[0x18];
5951
5952         u8         syndrome[0x20];
5953
5954         u8         reserved_at_40[0x40];
5955 };
5956
5957 struct mlx5_ifc_dealloc_uar_in_bits {
5958         u8         opcode[0x10];
5959         u8         reserved_at_10[0x10];
5960
5961         u8         reserved_at_20[0x10];
5962         u8         op_mod[0x10];
5963
5964         u8         reserved_at_40[0x8];
5965         u8         uar[0x18];
5966
5967         u8         reserved_at_60[0x20];
5968 };
5969
5970 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5971         u8         status[0x8];
5972         u8         reserved_at_8[0x18];
5973
5974         u8         syndrome[0x20];
5975
5976         u8         reserved_at_40[0x40];
5977 };
5978
5979 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5980         u8         opcode[0x10];
5981         u8         reserved_at_10[0x10];
5982
5983         u8         reserved_at_20[0x10];
5984         u8         op_mod[0x10];
5985
5986         u8         reserved_at_40[0x8];
5987         u8         transport_domain[0x18];
5988
5989         u8         reserved_at_60[0x20];
5990 };
5991
5992 struct mlx5_ifc_dealloc_q_counter_out_bits {
5993         u8         status[0x8];
5994         u8         reserved_at_8[0x18];
5995
5996         u8         syndrome[0x20];
5997
5998         u8         reserved_at_40[0x40];
5999 };
6000
6001 struct mlx5_ifc_dealloc_q_counter_in_bits {
6002         u8         opcode[0x10];
6003         u8         reserved_at_10[0x10];
6004
6005         u8         reserved_at_20[0x10];
6006         u8         op_mod[0x10];
6007
6008         u8         reserved_at_40[0x18];
6009         u8         counter_set_id[0x8];
6010
6011         u8         reserved_at_60[0x20];
6012 };
6013
6014 struct mlx5_ifc_dealloc_pd_out_bits {
6015         u8         status[0x8];
6016         u8         reserved_at_8[0x18];
6017
6018         u8         syndrome[0x20];
6019
6020         u8         reserved_at_40[0x40];
6021 };
6022
6023 struct mlx5_ifc_dealloc_pd_in_bits {
6024         u8         opcode[0x10];
6025         u8         reserved_at_10[0x10];
6026
6027         u8         reserved_at_20[0x10];
6028         u8         op_mod[0x10];
6029
6030         u8         reserved_at_40[0x8];
6031         u8         pd[0x18];
6032
6033         u8         reserved_at_60[0x20];
6034 };
6035
6036 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6037         u8         status[0x8];
6038         u8         reserved_at_8[0x18];
6039
6040         u8         syndrome[0x20];
6041
6042         u8         reserved_at_40[0x40];
6043 };
6044
6045 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6046         u8         opcode[0x10];
6047         u8         reserved_at_10[0x10];
6048
6049         u8         reserved_at_20[0x10];
6050         u8         op_mod[0x10];
6051
6052         u8         reserved_at_40[0x10];
6053         u8         flow_counter_id[0x10];
6054
6055         u8         reserved_at_60[0x20];
6056 };
6057
6058 struct mlx5_ifc_create_xrq_out_bits {
6059         u8         status[0x8];
6060         u8         reserved_at_8[0x18];
6061
6062         u8         syndrome[0x20];
6063
6064         u8         reserved_at_40[0x8];
6065         u8         xrqn[0x18];
6066
6067         u8         reserved_at_60[0x20];
6068 };
6069
6070 struct mlx5_ifc_create_xrq_in_bits {
6071         u8         opcode[0x10];
6072         u8         reserved_at_10[0x10];
6073
6074         u8         reserved_at_20[0x10];
6075         u8         op_mod[0x10];
6076
6077         u8         reserved_at_40[0x40];
6078
6079         struct mlx5_ifc_xrqc_bits xrq_context;
6080 };
6081
6082 struct mlx5_ifc_create_xrc_srq_out_bits {
6083         u8         status[0x8];
6084         u8         reserved_at_8[0x18];
6085
6086         u8         syndrome[0x20];
6087
6088         u8         reserved_at_40[0x8];
6089         u8         xrc_srqn[0x18];
6090
6091         u8         reserved_at_60[0x20];
6092 };
6093
6094 struct mlx5_ifc_create_xrc_srq_in_bits {
6095         u8         opcode[0x10];
6096         u8         reserved_at_10[0x10];
6097
6098         u8         reserved_at_20[0x10];
6099         u8         op_mod[0x10];
6100
6101         u8         reserved_at_40[0x40];
6102
6103         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6104
6105         u8         reserved_at_280[0x600];
6106
6107         u8         pas[0][0x40];
6108 };
6109
6110 struct mlx5_ifc_create_tis_out_bits {
6111         u8         status[0x8];
6112         u8         reserved_at_8[0x18];
6113
6114         u8         syndrome[0x20];
6115
6116         u8         reserved_at_40[0x8];
6117         u8         tisn[0x18];
6118
6119         u8         reserved_at_60[0x20];
6120 };
6121
6122 struct mlx5_ifc_create_tis_in_bits {
6123         u8         opcode[0x10];
6124         u8         reserved_at_10[0x10];
6125
6126         u8         reserved_at_20[0x10];
6127         u8         op_mod[0x10];
6128
6129         u8         reserved_at_40[0xc0];
6130
6131         struct mlx5_ifc_tisc_bits ctx;
6132 };
6133
6134 struct mlx5_ifc_create_tir_out_bits {
6135         u8         status[0x8];
6136         u8         reserved_at_8[0x18];
6137
6138         u8         syndrome[0x20];
6139
6140         u8         reserved_at_40[0x8];
6141         u8         tirn[0x18];
6142
6143         u8         reserved_at_60[0x20];
6144 };
6145
6146 struct mlx5_ifc_create_tir_in_bits {
6147         u8         opcode[0x10];
6148         u8         reserved_at_10[0x10];
6149
6150         u8         reserved_at_20[0x10];
6151         u8         op_mod[0x10];
6152
6153         u8         reserved_at_40[0xc0];
6154
6155         struct mlx5_ifc_tirc_bits ctx;
6156 };
6157
6158 struct mlx5_ifc_create_srq_out_bits {
6159         u8         status[0x8];
6160         u8         reserved_at_8[0x18];
6161
6162         u8         syndrome[0x20];
6163
6164         u8         reserved_at_40[0x8];
6165         u8         srqn[0x18];
6166
6167         u8         reserved_at_60[0x20];
6168 };
6169
6170 struct mlx5_ifc_create_srq_in_bits {
6171         u8         opcode[0x10];
6172         u8         reserved_at_10[0x10];
6173
6174         u8         reserved_at_20[0x10];
6175         u8         op_mod[0x10];
6176
6177         u8         reserved_at_40[0x40];
6178
6179         struct mlx5_ifc_srqc_bits srq_context_entry;
6180
6181         u8         reserved_at_280[0x600];
6182
6183         u8         pas[0][0x40];
6184 };
6185
6186 struct mlx5_ifc_create_sq_out_bits {
6187         u8         status[0x8];
6188         u8         reserved_at_8[0x18];
6189
6190         u8         syndrome[0x20];
6191
6192         u8         reserved_at_40[0x8];
6193         u8         sqn[0x18];
6194
6195         u8         reserved_at_60[0x20];
6196 };
6197
6198 struct mlx5_ifc_create_sq_in_bits {
6199         u8         opcode[0x10];
6200         u8         reserved_at_10[0x10];
6201
6202         u8         reserved_at_20[0x10];
6203         u8         op_mod[0x10];
6204
6205         u8         reserved_at_40[0xc0];
6206
6207         struct mlx5_ifc_sqc_bits ctx;
6208 };
6209
6210 struct mlx5_ifc_create_scheduling_element_out_bits {
6211         u8         status[0x8];
6212         u8         reserved_at_8[0x18];
6213
6214         u8         syndrome[0x20];
6215
6216         u8         reserved_at_40[0x40];
6217
6218         u8         scheduling_element_id[0x20];
6219
6220         u8         reserved_at_a0[0x160];
6221 };
6222
6223 struct mlx5_ifc_create_scheduling_element_in_bits {
6224         u8         opcode[0x10];
6225         u8         reserved_at_10[0x10];
6226
6227         u8         reserved_at_20[0x10];
6228         u8         op_mod[0x10];
6229
6230         u8         scheduling_hierarchy[0x8];
6231         u8         reserved_at_48[0x18];
6232
6233         u8         reserved_at_60[0xa0];
6234
6235         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6236
6237         u8         reserved_at_300[0x100];
6238 };
6239
6240 struct mlx5_ifc_create_rqt_out_bits {
6241         u8         status[0x8];
6242         u8         reserved_at_8[0x18];
6243
6244         u8         syndrome[0x20];
6245
6246         u8         reserved_at_40[0x8];
6247         u8         rqtn[0x18];
6248
6249         u8         reserved_at_60[0x20];
6250 };
6251
6252 struct mlx5_ifc_create_rqt_in_bits {
6253         u8         opcode[0x10];
6254         u8         reserved_at_10[0x10];
6255
6256         u8         reserved_at_20[0x10];
6257         u8         op_mod[0x10];
6258
6259         u8         reserved_at_40[0xc0];
6260
6261         struct mlx5_ifc_rqtc_bits rqt_context;
6262 };
6263
6264 struct mlx5_ifc_create_rq_out_bits {
6265         u8         status[0x8];
6266         u8         reserved_at_8[0x18];
6267
6268         u8         syndrome[0x20];
6269
6270         u8         reserved_at_40[0x8];
6271         u8         rqn[0x18];
6272
6273         u8         reserved_at_60[0x20];
6274 };
6275
6276 struct mlx5_ifc_create_rq_in_bits {
6277         u8         opcode[0x10];
6278         u8         reserved_at_10[0x10];
6279
6280         u8         reserved_at_20[0x10];
6281         u8         op_mod[0x10];
6282
6283         u8         reserved_at_40[0xc0];
6284
6285         struct mlx5_ifc_rqc_bits ctx;
6286 };
6287
6288 struct mlx5_ifc_create_rmp_out_bits {
6289         u8         status[0x8];
6290         u8         reserved_at_8[0x18];
6291
6292         u8         syndrome[0x20];
6293
6294         u8         reserved_at_40[0x8];
6295         u8         rmpn[0x18];
6296
6297         u8         reserved_at_60[0x20];
6298 };
6299
6300 struct mlx5_ifc_create_rmp_in_bits {
6301         u8         opcode[0x10];
6302         u8         reserved_at_10[0x10];
6303
6304         u8         reserved_at_20[0x10];
6305         u8         op_mod[0x10];
6306
6307         u8         reserved_at_40[0xc0];
6308
6309         struct mlx5_ifc_rmpc_bits ctx;
6310 };
6311
6312 struct mlx5_ifc_create_qp_out_bits {
6313         u8         status[0x8];
6314         u8         reserved_at_8[0x18];
6315
6316         u8         syndrome[0x20];
6317
6318         u8         reserved_at_40[0x8];
6319         u8         qpn[0x18];
6320
6321         u8         reserved_at_60[0x20];
6322 };
6323
6324 struct mlx5_ifc_create_qp_in_bits {
6325         u8         opcode[0x10];
6326         u8         reserved_at_10[0x10];
6327
6328         u8         reserved_at_20[0x10];
6329         u8         op_mod[0x10];
6330
6331         u8         reserved_at_40[0x40];
6332
6333         u8         opt_param_mask[0x20];
6334
6335         u8         reserved_at_a0[0x20];
6336
6337         struct mlx5_ifc_qpc_bits qpc;
6338
6339         u8         reserved_at_800[0x80];
6340
6341         u8         pas[0][0x40];
6342 };
6343
6344 struct mlx5_ifc_create_psv_out_bits {
6345         u8         status[0x8];
6346         u8         reserved_at_8[0x18];
6347
6348         u8         syndrome[0x20];
6349
6350         u8         reserved_at_40[0x40];
6351
6352         u8         reserved_at_80[0x8];
6353         u8         psv0_index[0x18];
6354
6355         u8         reserved_at_a0[0x8];
6356         u8         psv1_index[0x18];
6357
6358         u8         reserved_at_c0[0x8];
6359         u8         psv2_index[0x18];
6360
6361         u8         reserved_at_e0[0x8];
6362         u8         psv3_index[0x18];
6363 };
6364
6365 struct mlx5_ifc_create_psv_in_bits {
6366         u8         opcode[0x10];
6367         u8         reserved_at_10[0x10];
6368
6369         u8         reserved_at_20[0x10];
6370         u8         op_mod[0x10];
6371
6372         u8         num_psv[0x4];
6373         u8         reserved_at_44[0x4];
6374         u8         pd[0x18];
6375
6376         u8         reserved_at_60[0x20];
6377 };
6378
6379 struct mlx5_ifc_create_mkey_out_bits {
6380         u8         status[0x8];
6381         u8         reserved_at_8[0x18];
6382
6383         u8         syndrome[0x20];
6384
6385         u8         reserved_at_40[0x8];
6386         u8         mkey_index[0x18];
6387
6388         u8         reserved_at_60[0x20];
6389 };
6390
6391 struct mlx5_ifc_create_mkey_in_bits {
6392         u8         opcode[0x10];
6393         u8         reserved_at_10[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         reserved_at_40[0x20];
6399
6400         u8         pg_access[0x1];
6401         u8         reserved_at_61[0x1f];
6402
6403         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6404
6405         u8         reserved_at_280[0x80];
6406
6407         u8         translations_octword_actual_size[0x20];
6408
6409         u8         reserved_at_320[0x560];
6410
6411         u8         klm_pas_mtt[0][0x20];
6412 };
6413
6414 struct mlx5_ifc_create_flow_table_out_bits {
6415         u8         status[0x8];
6416         u8         reserved_at_8[0x18];
6417
6418         u8         syndrome[0x20];
6419
6420         u8         reserved_at_40[0x8];
6421         u8         table_id[0x18];
6422
6423         u8         reserved_at_60[0x20];
6424 };
6425
6426 struct mlx5_ifc_create_flow_table_in_bits {
6427         u8         opcode[0x10];
6428         u8         reserved_at_10[0x10];
6429
6430         u8         reserved_at_20[0x10];
6431         u8         op_mod[0x10];
6432
6433         u8         other_vport[0x1];
6434         u8         reserved_at_41[0xf];
6435         u8         vport_number[0x10];
6436
6437         u8         reserved_at_60[0x20];
6438
6439         u8         table_type[0x8];
6440         u8         reserved_at_88[0x18];
6441
6442         u8         reserved_at_a0[0x20];
6443
6444         u8         encap_en[0x1];
6445         u8         decap_en[0x1];
6446         u8         reserved_at_c2[0x2];
6447         u8         table_miss_mode[0x4];
6448         u8         level[0x8];
6449         u8         reserved_at_d0[0x8];
6450         u8         log_size[0x8];
6451
6452         u8         reserved_at_e0[0x8];
6453         u8         table_miss_id[0x18];
6454
6455         u8         reserved_at_100[0x8];
6456         u8         lag_master_next_table_id[0x18];
6457
6458         u8         reserved_at_120[0x80];
6459 };
6460
6461 struct mlx5_ifc_create_flow_group_out_bits {
6462         u8         status[0x8];
6463         u8         reserved_at_8[0x18];
6464
6465         u8         syndrome[0x20];
6466
6467         u8         reserved_at_40[0x8];
6468         u8         group_id[0x18];
6469
6470         u8         reserved_at_60[0x20];
6471 };
6472
6473 enum {
6474         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6475         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6476         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6477 };
6478
6479 struct mlx5_ifc_create_flow_group_in_bits {
6480         u8         opcode[0x10];
6481         u8         reserved_at_10[0x10];
6482
6483         u8         reserved_at_20[0x10];
6484         u8         op_mod[0x10];
6485
6486         u8         other_vport[0x1];
6487         u8         reserved_at_41[0xf];
6488         u8         vport_number[0x10];
6489
6490         u8         reserved_at_60[0x20];
6491
6492         u8         table_type[0x8];
6493         u8         reserved_at_88[0x18];
6494
6495         u8         reserved_at_a0[0x8];
6496         u8         table_id[0x18];
6497
6498         u8         reserved_at_c0[0x20];
6499
6500         u8         start_flow_index[0x20];
6501
6502         u8         reserved_at_100[0x20];
6503
6504         u8         end_flow_index[0x20];
6505
6506         u8         reserved_at_140[0xa0];
6507
6508         u8         reserved_at_1e0[0x18];
6509         u8         match_criteria_enable[0x8];
6510
6511         struct mlx5_ifc_fte_match_param_bits match_criteria;
6512
6513         u8         reserved_at_1200[0xe00];
6514 };
6515
6516 struct mlx5_ifc_create_eq_out_bits {
6517         u8         status[0x8];
6518         u8         reserved_at_8[0x18];
6519
6520         u8         syndrome[0x20];
6521
6522         u8         reserved_at_40[0x18];
6523         u8         eq_number[0x8];
6524
6525         u8         reserved_at_60[0x20];
6526 };
6527
6528 struct mlx5_ifc_create_eq_in_bits {
6529         u8         opcode[0x10];
6530         u8         reserved_at_10[0x10];
6531
6532         u8         reserved_at_20[0x10];
6533         u8         op_mod[0x10];
6534
6535         u8         reserved_at_40[0x40];
6536
6537         struct mlx5_ifc_eqc_bits eq_context_entry;
6538
6539         u8         reserved_at_280[0x40];
6540
6541         u8         event_bitmask[0x40];
6542
6543         u8         reserved_at_300[0x580];
6544
6545         u8         pas[0][0x40];
6546 };
6547
6548 struct mlx5_ifc_create_dct_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_at_8[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_at_40[0x8];
6555         u8         dctn[0x18];
6556
6557         u8         reserved_at_60[0x20];
6558 };
6559
6560 struct mlx5_ifc_create_dct_in_bits {
6561         u8         opcode[0x10];
6562         u8         reserved_at_10[0x10];
6563
6564         u8         reserved_at_20[0x10];
6565         u8         op_mod[0x10];
6566
6567         u8         reserved_at_40[0x40];
6568
6569         struct mlx5_ifc_dctc_bits dct_context_entry;
6570
6571         u8         reserved_at_280[0x180];
6572 };
6573
6574 struct mlx5_ifc_create_cq_out_bits {
6575         u8         status[0x8];
6576         u8         reserved_at_8[0x18];
6577
6578         u8         syndrome[0x20];
6579
6580         u8         reserved_at_40[0x8];
6581         u8         cqn[0x18];
6582
6583         u8         reserved_at_60[0x20];
6584 };
6585
6586 struct mlx5_ifc_create_cq_in_bits {
6587         u8         opcode[0x10];
6588         u8         reserved_at_10[0x10];
6589
6590         u8         reserved_at_20[0x10];
6591         u8         op_mod[0x10];
6592
6593         u8         reserved_at_40[0x40];
6594
6595         struct mlx5_ifc_cqc_bits cq_context;
6596
6597         u8         reserved_at_280[0x600];
6598
6599         u8         pas[0][0x40];
6600 };
6601
6602 struct mlx5_ifc_config_int_moderation_out_bits {
6603         u8         status[0x8];
6604         u8         reserved_at_8[0x18];
6605
6606         u8         syndrome[0x20];
6607
6608         u8         reserved_at_40[0x4];
6609         u8         min_delay[0xc];
6610         u8         int_vector[0x10];
6611
6612         u8         reserved_at_60[0x20];
6613 };
6614
6615 enum {
6616         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6617         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6618 };
6619
6620 struct mlx5_ifc_config_int_moderation_in_bits {
6621         u8         opcode[0x10];
6622         u8         reserved_at_10[0x10];
6623
6624         u8         reserved_at_20[0x10];
6625         u8         op_mod[0x10];
6626
6627         u8         reserved_at_40[0x4];
6628         u8         min_delay[0xc];
6629         u8         int_vector[0x10];
6630
6631         u8         reserved_at_60[0x20];
6632 };
6633
6634 struct mlx5_ifc_attach_to_mcg_out_bits {
6635         u8         status[0x8];
6636         u8         reserved_at_8[0x18];
6637
6638         u8         syndrome[0x20];
6639
6640         u8         reserved_at_40[0x40];
6641 };
6642
6643 struct mlx5_ifc_attach_to_mcg_in_bits {
6644         u8         opcode[0x10];
6645         u8         reserved_at_10[0x10];
6646
6647         u8         reserved_at_20[0x10];
6648         u8         op_mod[0x10];
6649
6650         u8         reserved_at_40[0x8];
6651         u8         qpn[0x18];
6652
6653         u8         reserved_at_60[0x20];
6654
6655         u8         multicast_gid[16][0x8];
6656 };
6657
6658 struct mlx5_ifc_arm_xrq_out_bits {
6659         u8         status[0x8];
6660         u8         reserved_at_8[0x18];
6661
6662         u8         syndrome[0x20];
6663
6664         u8         reserved_at_40[0x40];
6665 };
6666
6667 struct mlx5_ifc_arm_xrq_in_bits {
6668         u8         opcode[0x10];
6669         u8         reserved_at_10[0x10];
6670
6671         u8         reserved_at_20[0x10];
6672         u8         op_mod[0x10];
6673
6674         u8         reserved_at_40[0x8];
6675         u8         xrqn[0x18];
6676
6677         u8         reserved_at_60[0x10];
6678         u8         lwm[0x10];
6679 };
6680
6681 struct mlx5_ifc_arm_xrc_srq_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_at_8[0x18];
6684
6685         u8         syndrome[0x20];
6686
6687         u8         reserved_at_40[0x40];
6688 };
6689
6690 enum {
6691         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6692 };
6693
6694 struct mlx5_ifc_arm_xrc_srq_in_bits {
6695         u8         opcode[0x10];
6696         u8         reserved_at_10[0x10];
6697
6698         u8         reserved_at_20[0x10];
6699         u8         op_mod[0x10];
6700
6701         u8         reserved_at_40[0x8];
6702         u8         xrc_srqn[0x18];
6703
6704         u8         reserved_at_60[0x10];
6705         u8         lwm[0x10];
6706 };
6707
6708 struct mlx5_ifc_arm_rq_out_bits {
6709         u8         status[0x8];
6710         u8         reserved_at_8[0x18];
6711
6712         u8         syndrome[0x20];
6713
6714         u8         reserved_at_40[0x40];
6715 };
6716
6717 enum {
6718         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6719         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6720 };
6721
6722 struct mlx5_ifc_arm_rq_in_bits {
6723         u8         opcode[0x10];
6724         u8         reserved_at_10[0x10];
6725
6726         u8         reserved_at_20[0x10];
6727         u8         op_mod[0x10];
6728
6729         u8         reserved_at_40[0x8];
6730         u8         srq_number[0x18];
6731
6732         u8         reserved_at_60[0x10];
6733         u8         lwm[0x10];
6734 };
6735
6736 struct mlx5_ifc_arm_dct_out_bits {
6737         u8         status[0x8];
6738         u8         reserved_at_8[0x18];
6739
6740         u8         syndrome[0x20];
6741
6742         u8         reserved_at_40[0x40];
6743 };
6744
6745 struct mlx5_ifc_arm_dct_in_bits {
6746         u8         opcode[0x10];
6747         u8         reserved_at_10[0x10];
6748
6749         u8         reserved_at_20[0x10];
6750         u8         op_mod[0x10];
6751
6752         u8         reserved_at_40[0x8];
6753         u8         dct_number[0x18];
6754
6755         u8         reserved_at_60[0x20];
6756 };
6757
6758 struct mlx5_ifc_alloc_xrcd_out_bits {
6759         u8         status[0x8];
6760         u8         reserved_at_8[0x18];
6761
6762         u8         syndrome[0x20];
6763
6764         u8         reserved_at_40[0x8];
6765         u8         xrcd[0x18];
6766
6767         u8         reserved_at_60[0x20];
6768 };
6769
6770 struct mlx5_ifc_alloc_xrcd_in_bits {
6771         u8         opcode[0x10];
6772         u8         reserved_at_10[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0x40];
6778 };
6779
6780 struct mlx5_ifc_alloc_uar_out_bits {
6781         u8         status[0x8];
6782         u8         reserved_at_8[0x18];
6783
6784         u8         syndrome[0x20];
6785
6786         u8         reserved_at_40[0x8];
6787         u8         uar[0x18];
6788
6789         u8         reserved_at_60[0x20];
6790 };
6791
6792 struct mlx5_ifc_alloc_uar_in_bits {
6793         u8         opcode[0x10];
6794         u8         reserved_at_10[0x10];
6795
6796         u8         reserved_at_20[0x10];
6797         u8         op_mod[0x10];
6798
6799         u8         reserved_at_40[0x40];
6800 };
6801
6802 struct mlx5_ifc_alloc_transport_domain_out_bits {
6803         u8         status[0x8];
6804         u8         reserved_at_8[0x18];
6805
6806         u8         syndrome[0x20];
6807
6808         u8         reserved_at_40[0x8];
6809         u8         transport_domain[0x18];
6810
6811         u8         reserved_at_60[0x20];
6812 };
6813
6814 struct mlx5_ifc_alloc_transport_domain_in_bits {
6815         u8         opcode[0x10];
6816         u8         reserved_at_10[0x10];
6817
6818         u8         reserved_at_20[0x10];
6819         u8         op_mod[0x10];
6820
6821         u8         reserved_at_40[0x40];
6822 };
6823
6824 struct mlx5_ifc_alloc_q_counter_out_bits {
6825         u8         status[0x8];
6826         u8         reserved_at_8[0x18];
6827
6828         u8         syndrome[0x20];
6829
6830         u8         reserved_at_40[0x18];
6831         u8         counter_set_id[0x8];
6832
6833         u8         reserved_at_60[0x20];
6834 };
6835
6836 struct mlx5_ifc_alloc_q_counter_in_bits {
6837         u8         opcode[0x10];
6838         u8         reserved_at_10[0x10];
6839
6840         u8         reserved_at_20[0x10];
6841         u8         op_mod[0x10];
6842
6843         u8         reserved_at_40[0x40];
6844 };
6845
6846 struct mlx5_ifc_alloc_pd_out_bits {
6847         u8         status[0x8];
6848         u8         reserved_at_8[0x18];
6849
6850         u8         syndrome[0x20];
6851
6852         u8         reserved_at_40[0x8];
6853         u8         pd[0x18];
6854
6855         u8         reserved_at_60[0x20];
6856 };
6857
6858 struct mlx5_ifc_alloc_pd_in_bits {
6859         u8         opcode[0x10];
6860         u8         reserved_at_10[0x10];
6861
6862         u8         reserved_at_20[0x10];
6863         u8         op_mod[0x10];
6864
6865         u8         reserved_at_40[0x40];
6866 };
6867
6868 struct mlx5_ifc_alloc_flow_counter_out_bits {
6869         u8         status[0x8];
6870         u8         reserved_at_8[0x18];
6871
6872         u8         syndrome[0x20];
6873
6874         u8         reserved_at_40[0x10];
6875         u8         flow_counter_id[0x10];
6876
6877         u8         reserved_at_60[0x20];
6878 };
6879
6880 struct mlx5_ifc_alloc_flow_counter_in_bits {
6881         u8         opcode[0x10];
6882         u8         reserved_at_10[0x10];
6883
6884         u8         reserved_at_20[0x10];
6885         u8         op_mod[0x10];
6886
6887         u8         reserved_at_40[0x40];
6888 };
6889
6890 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6891         u8         status[0x8];
6892         u8         reserved_at_8[0x18];
6893
6894         u8         syndrome[0x20];
6895
6896         u8         reserved_at_40[0x40];
6897 };
6898
6899 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6900         u8         opcode[0x10];
6901         u8         reserved_at_10[0x10];
6902
6903         u8         reserved_at_20[0x10];
6904         u8         op_mod[0x10];
6905
6906         u8         reserved_at_40[0x20];
6907
6908         u8         reserved_at_60[0x10];
6909         u8         vxlan_udp_port[0x10];
6910 };
6911
6912 struct mlx5_ifc_set_rate_limit_out_bits {
6913         u8         status[0x8];
6914         u8         reserved_at_8[0x18];
6915
6916         u8         syndrome[0x20];
6917
6918         u8         reserved_at_40[0x40];
6919 };
6920
6921 struct mlx5_ifc_set_rate_limit_in_bits {
6922         u8         opcode[0x10];
6923         u8         reserved_at_10[0x10];
6924
6925         u8         reserved_at_20[0x10];
6926         u8         op_mod[0x10];
6927
6928         u8         reserved_at_40[0x10];
6929         u8         rate_limit_index[0x10];
6930
6931         u8         reserved_at_60[0x20];
6932
6933         u8         rate_limit[0x20];
6934 };
6935
6936 struct mlx5_ifc_access_register_out_bits {
6937         u8         status[0x8];
6938         u8         reserved_at_8[0x18];
6939
6940         u8         syndrome[0x20];
6941
6942         u8         reserved_at_40[0x40];
6943
6944         u8         register_data[0][0x20];
6945 };
6946
6947 enum {
6948         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6949         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6950 };
6951
6952 struct mlx5_ifc_access_register_in_bits {
6953         u8         opcode[0x10];
6954         u8         reserved_at_10[0x10];
6955
6956         u8         reserved_at_20[0x10];
6957         u8         op_mod[0x10];
6958
6959         u8         reserved_at_40[0x10];
6960         u8         register_id[0x10];
6961
6962         u8         argument[0x20];
6963
6964         u8         register_data[0][0x20];
6965 };
6966
6967 struct mlx5_ifc_sltp_reg_bits {
6968         u8         status[0x4];
6969         u8         version[0x4];
6970         u8         local_port[0x8];
6971         u8         pnat[0x2];
6972         u8         reserved_at_12[0x2];
6973         u8         lane[0x4];
6974         u8         reserved_at_18[0x8];
6975
6976         u8         reserved_at_20[0x20];
6977
6978         u8         reserved_at_40[0x7];
6979         u8         polarity[0x1];
6980         u8         ob_tap0[0x8];
6981         u8         ob_tap1[0x8];
6982         u8         ob_tap2[0x8];
6983
6984         u8         reserved_at_60[0xc];
6985         u8         ob_preemp_mode[0x4];
6986         u8         ob_reg[0x8];
6987         u8         ob_bias[0x8];
6988
6989         u8         reserved_at_80[0x20];
6990 };
6991
6992 struct mlx5_ifc_slrg_reg_bits {
6993         u8         status[0x4];
6994         u8         version[0x4];
6995         u8         local_port[0x8];
6996         u8         pnat[0x2];
6997         u8         reserved_at_12[0x2];
6998         u8         lane[0x4];
6999         u8         reserved_at_18[0x8];
7000
7001         u8         time_to_link_up[0x10];
7002         u8         reserved_at_30[0xc];
7003         u8         grade_lane_speed[0x4];
7004
7005         u8         grade_version[0x8];
7006         u8         grade[0x18];
7007
7008         u8         reserved_at_60[0x4];
7009         u8         height_grade_type[0x4];
7010         u8         height_grade[0x18];
7011
7012         u8         height_dz[0x10];
7013         u8         height_dv[0x10];
7014
7015         u8         reserved_at_a0[0x10];
7016         u8         height_sigma[0x10];
7017
7018         u8         reserved_at_c0[0x20];
7019
7020         u8         reserved_at_e0[0x4];
7021         u8         phase_grade_type[0x4];
7022         u8         phase_grade[0x18];
7023
7024         u8         reserved_at_100[0x8];
7025         u8         phase_eo_pos[0x8];
7026         u8         reserved_at_110[0x8];
7027         u8         phase_eo_neg[0x8];
7028
7029         u8         ffe_set_tested[0x10];
7030         u8         test_errors_per_lane[0x10];
7031 };
7032
7033 struct mlx5_ifc_pvlc_reg_bits {
7034         u8         reserved_at_0[0x8];
7035         u8         local_port[0x8];
7036         u8         reserved_at_10[0x10];
7037
7038         u8         reserved_at_20[0x1c];
7039         u8         vl_hw_cap[0x4];
7040
7041         u8         reserved_at_40[0x1c];
7042         u8         vl_admin[0x4];
7043
7044         u8         reserved_at_60[0x1c];
7045         u8         vl_operational[0x4];
7046 };
7047
7048 struct mlx5_ifc_pude_reg_bits {
7049         u8         swid[0x8];
7050         u8         local_port[0x8];
7051         u8         reserved_at_10[0x4];
7052         u8         admin_status[0x4];
7053         u8         reserved_at_18[0x4];
7054         u8         oper_status[0x4];
7055
7056         u8         reserved_at_20[0x60];
7057 };
7058
7059 struct mlx5_ifc_ptys_reg_bits {
7060         u8         reserved_at_0[0x1];
7061         u8         an_disable_admin[0x1];
7062         u8         an_disable_cap[0x1];
7063         u8         reserved_at_3[0x5];
7064         u8         local_port[0x8];
7065         u8         reserved_at_10[0xd];
7066         u8         proto_mask[0x3];
7067
7068         u8         an_status[0x4];
7069         u8         reserved_at_24[0x3c];
7070
7071         u8         eth_proto_capability[0x20];
7072
7073         u8         ib_link_width_capability[0x10];
7074         u8         ib_proto_capability[0x10];
7075
7076         u8         reserved_at_a0[0x20];
7077
7078         u8         eth_proto_admin[0x20];
7079
7080         u8         ib_link_width_admin[0x10];
7081         u8         ib_proto_admin[0x10];
7082
7083         u8         reserved_at_100[0x20];
7084
7085         u8         eth_proto_oper[0x20];
7086
7087         u8         ib_link_width_oper[0x10];
7088         u8         ib_proto_oper[0x10];
7089
7090         u8         reserved_at_160[0x20];
7091
7092         u8         eth_proto_lp_advertise[0x20];
7093
7094         u8         reserved_at_1a0[0x60];
7095 };
7096
7097 struct mlx5_ifc_mlcr_reg_bits {
7098         u8         reserved_at_0[0x8];
7099         u8         local_port[0x8];
7100         u8         reserved_at_10[0x20];
7101
7102         u8         beacon_duration[0x10];
7103         u8         reserved_at_40[0x10];
7104
7105         u8         beacon_remain[0x10];
7106 };
7107
7108 struct mlx5_ifc_ptas_reg_bits {
7109         u8         reserved_at_0[0x20];
7110
7111         u8         algorithm_options[0x10];
7112         u8         reserved_at_30[0x4];
7113         u8         repetitions_mode[0x4];
7114         u8         num_of_repetitions[0x8];
7115
7116         u8         grade_version[0x8];
7117         u8         height_grade_type[0x4];
7118         u8         phase_grade_type[0x4];
7119         u8         height_grade_weight[0x8];
7120         u8         phase_grade_weight[0x8];
7121
7122         u8         gisim_measure_bits[0x10];
7123         u8         adaptive_tap_measure_bits[0x10];
7124
7125         u8         ber_bath_high_error_threshold[0x10];
7126         u8         ber_bath_mid_error_threshold[0x10];
7127
7128         u8         ber_bath_low_error_threshold[0x10];
7129         u8         one_ratio_high_threshold[0x10];
7130
7131         u8         one_ratio_high_mid_threshold[0x10];
7132         u8         one_ratio_low_mid_threshold[0x10];
7133
7134         u8         one_ratio_low_threshold[0x10];
7135         u8         ndeo_error_threshold[0x10];
7136
7137         u8         mixer_offset_step_size[0x10];
7138         u8         reserved_at_110[0x8];
7139         u8         mix90_phase_for_voltage_bath[0x8];
7140
7141         u8         mixer_offset_start[0x10];
7142         u8         mixer_offset_end[0x10];
7143
7144         u8         reserved_at_140[0x15];
7145         u8         ber_test_time[0xb];
7146 };
7147
7148 struct mlx5_ifc_pspa_reg_bits {
7149         u8         swid[0x8];
7150         u8         local_port[0x8];
7151         u8         sub_port[0x8];
7152         u8         reserved_at_18[0x8];
7153
7154         u8         reserved_at_20[0x20];
7155 };
7156
7157 struct mlx5_ifc_pqdr_reg_bits {
7158         u8         reserved_at_0[0x8];
7159         u8         local_port[0x8];
7160         u8         reserved_at_10[0x5];
7161         u8         prio[0x3];
7162         u8         reserved_at_18[0x6];
7163         u8         mode[0x2];
7164
7165         u8         reserved_at_20[0x20];
7166
7167         u8         reserved_at_40[0x10];
7168         u8         min_threshold[0x10];
7169
7170         u8         reserved_at_60[0x10];
7171         u8         max_threshold[0x10];
7172
7173         u8         reserved_at_80[0x10];
7174         u8         mark_probability_denominator[0x10];
7175
7176         u8         reserved_at_a0[0x60];
7177 };
7178
7179 struct mlx5_ifc_ppsc_reg_bits {
7180         u8         reserved_at_0[0x8];
7181         u8         local_port[0x8];
7182         u8         reserved_at_10[0x10];
7183
7184         u8         reserved_at_20[0x60];
7185
7186         u8         reserved_at_80[0x1c];
7187         u8         wrps_admin[0x4];
7188
7189         u8         reserved_at_a0[0x1c];
7190         u8         wrps_status[0x4];
7191
7192         u8         reserved_at_c0[0x8];
7193         u8         up_threshold[0x8];
7194         u8         reserved_at_d0[0x8];
7195         u8         down_threshold[0x8];
7196
7197         u8         reserved_at_e0[0x20];
7198
7199         u8         reserved_at_100[0x1c];
7200         u8         srps_admin[0x4];
7201
7202         u8         reserved_at_120[0x1c];
7203         u8         srps_status[0x4];
7204
7205         u8         reserved_at_140[0x40];
7206 };
7207
7208 struct mlx5_ifc_pplr_reg_bits {
7209         u8         reserved_at_0[0x8];
7210         u8         local_port[0x8];
7211         u8         reserved_at_10[0x10];
7212
7213         u8         reserved_at_20[0x8];
7214         u8         lb_cap[0x8];
7215         u8         reserved_at_30[0x8];
7216         u8         lb_en[0x8];
7217 };
7218
7219 struct mlx5_ifc_pplm_reg_bits {
7220         u8         reserved_at_0[0x8];
7221         u8         local_port[0x8];
7222         u8         reserved_at_10[0x10];
7223
7224         u8         reserved_at_20[0x20];
7225
7226         u8         port_profile_mode[0x8];
7227         u8         static_port_profile[0x8];
7228         u8         active_port_profile[0x8];
7229         u8         reserved_at_58[0x8];
7230
7231         u8         retransmission_active[0x8];
7232         u8         fec_mode_active[0x18];
7233
7234         u8         reserved_at_80[0x20];
7235 };
7236
7237 struct mlx5_ifc_ppcnt_reg_bits {
7238         u8         swid[0x8];
7239         u8         local_port[0x8];
7240         u8         pnat[0x2];
7241         u8         reserved_at_12[0x8];
7242         u8         grp[0x6];
7243
7244         u8         clr[0x1];
7245         u8         reserved_at_21[0x1c];
7246         u8         prio_tc[0x3];
7247
7248         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7249 };
7250
7251 struct mlx5_ifc_ppad_reg_bits {
7252         u8         reserved_at_0[0x3];
7253         u8         single_mac[0x1];
7254         u8         reserved_at_4[0x4];
7255         u8         local_port[0x8];
7256         u8         mac_47_32[0x10];
7257
7258         u8         mac_31_0[0x20];
7259
7260         u8         reserved_at_40[0x40];
7261 };
7262
7263 struct mlx5_ifc_pmtu_reg_bits {
7264         u8         reserved_at_0[0x8];
7265         u8         local_port[0x8];
7266         u8         reserved_at_10[0x10];
7267
7268         u8         max_mtu[0x10];
7269         u8         reserved_at_30[0x10];
7270
7271         u8         admin_mtu[0x10];
7272         u8         reserved_at_50[0x10];
7273
7274         u8         oper_mtu[0x10];
7275         u8         reserved_at_70[0x10];
7276 };
7277
7278 struct mlx5_ifc_pmpr_reg_bits {
7279         u8         reserved_at_0[0x8];
7280         u8         module[0x8];
7281         u8         reserved_at_10[0x10];
7282
7283         u8         reserved_at_20[0x18];
7284         u8         attenuation_5g[0x8];
7285
7286         u8         reserved_at_40[0x18];
7287         u8         attenuation_7g[0x8];
7288
7289         u8         reserved_at_60[0x18];
7290         u8         attenuation_12g[0x8];
7291 };
7292
7293 struct mlx5_ifc_pmpe_reg_bits {
7294         u8         reserved_at_0[0x8];
7295         u8         module[0x8];
7296         u8         reserved_at_10[0xc];
7297         u8         module_status[0x4];
7298
7299         u8         reserved_at_20[0x60];
7300 };
7301
7302 struct mlx5_ifc_pmpc_reg_bits {
7303         u8         module_state_updated[32][0x8];
7304 };
7305
7306 struct mlx5_ifc_pmlpn_reg_bits {
7307         u8         reserved_at_0[0x4];
7308         u8         mlpn_status[0x4];
7309         u8         local_port[0x8];
7310         u8         reserved_at_10[0x10];
7311
7312         u8         e[0x1];
7313         u8         reserved_at_21[0x1f];
7314 };
7315
7316 struct mlx5_ifc_pmlp_reg_bits {
7317         u8         rxtx[0x1];
7318         u8         reserved_at_1[0x7];
7319         u8         local_port[0x8];
7320         u8         reserved_at_10[0x8];
7321         u8         width[0x8];
7322
7323         u8         lane0_module_mapping[0x20];
7324
7325         u8         lane1_module_mapping[0x20];
7326
7327         u8         lane2_module_mapping[0x20];
7328
7329         u8         lane3_module_mapping[0x20];
7330
7331         u8         reserved_at_a0[0x160];
7332 };
7333
7334 struct mlx5_ifc_pmaos_reg_bits {
7335         u8         reserved_at_0[0x8];
7336         u8         module[0x8];
7337         u8         reserved_at_10[0x4];
7338         u8         admin_status[0x4];
7339         u8         reserved_at_18[0x4];
7340         u8         oper_status[0x4];
7341
7342         u8         ase[0x1];
7343         u8         ee[0x1];
7344         u8         reserved_at_22[0x1c];
7345         u8         e[0x2];
7346
7347         u8         reserved_at_40[0x40];
7348 };
7349
7350 struct mlx5_ifc_plpc_reg_bits {
7351         u8         reserved_at_0[0x4];
7352         u8         profile_id[0xc];
7353         u8         reserved_at_10[0x4];
7354         u8         proto_mask[0x4];
7355         u8         reserved_at_18[0x8];
7356
7357         u8         reserved_at_20[0x10];
7358         u8         lane_speed[0x10];
7359
7360         u8         reserved_at_40[0x17];
7361         u8         lpbf[0x1];
7362         u8         fec_mode_policy[0x8];
7363
7364         u8         retransmission_capability[0x8];
7365         u8         fec_mode_capability[0x18];
7366
7367         u8         retransmission_support_admin[0x8];
7368         u8         fec_mode_support_admin[0x18];
7369
7370         u8         retransmission_request_admin[0x8];
7371         u8         fec_mode_request_admin[0x18];
7372
7373         u8         reserved_at_c0[0x80];
7374 };
7375
7376 struct mlx5_ifc_plib_reg_bits {
7377         u8         reserved_at_0[0x8];
7378         u8         local_port[0x8];
7379         u8         reserved_at_10[0x8];
7380         u8         ib_port[0x8];
7381
7382         u8         reserved_at_20[0x60];
7383 };
7384
7385 struct mlx5_ifc_plbf_reg_bits {
7386         u8         reserved_at_0[0x8];
7387         u8         local_port[0x8];
7388         u8         reserved_at_10[0xd];
7389         u8         lbf_mode[0x3];
7390
7391         u8         reserved_at_20[0x20];
7392 };
7393
7394 struct mlx5_ifc_pipg_reg_bits {
7395         u8         reserved_at_0[0x8];
7396         u8         local_port[0x8];
7397         u8         reserved_at_10[0x10];
7398
7399         u8         dic[0x1];
7400         u8         reserved_at_21[0x19];
7401         u8         ipg[0x4];
7402         u8         reserved_at_3e[0x2];
7403 };
7404
7405 struct mlx5_ifc_pifr_reg_bits {
7406         u8         reserved_at_0[0x8];
7407         u8         local_port[0x8];
7408         u8         reserved_at_10[0x10];
7409
7410         u8         reserved_at_20[0xe0];
7411
7412         u8         port_filter[8][0x20];
7413
7414         u8         port_filter_update_en[8][0x20];
7415 };
7416
7417 struct mlx5_ifc_pfcc_reg_bits {
7418         u8         reserved_at_0[0x8];
7419         u8         local_port[0x8];
7420         u8         reserved_at_10[0x10];
7421
7422         u8         ppan[0x4];
7423         u8         reserved_at_24[0x4];
7424         u8         prio_mask_tx[0x8];
7425         u8         reserved_at_30[0x8];
7426         u8         prio_mask_rx[0x8];
7427
7428         u8         pptx[0x1];
7429         u8         aptx[0x1];
7430         u8         reserved_at_42[0x6];
7431         u8         pfctx[0x8];
7432         u8         reserved_at_50[0x10];
7433
7434         u8         pprx[0x1];
7435         u8         aprx[0x1];
7436         u8         reserved_at_62[0x6];
7437         u8         pfcrx[0x8];
7438         u8         reserved_at_70[0x10];
7439
7440         u8         reserved_at_80[0x80];
7441 };
7442
7443 struct mlx5_ifc_pelc_reg_bits {
7444         u8         op[0x4];
7445         u8         reserved_at_4[0x4];
7446         u8         local_port[0x8];
7447         u8         reserved_at_10[0x10];
7448
7449         u8         op_admin[0x8];
7450         u8         op_capability[0x8];
7451         u8         op_request[0x8];
7452         u8         op_active[0x8];
7453
7454         u8         admin[0x40];
7455
7456         u8         capability[0x40];
7457
7458         u8         request[0x40];
7459
7460         u8         active[0x40];
7461
7462         u8         reserved_at_140[0x80];
7463 };
7464
7465 struct mlx5_ifc_peir_reg_bits {
7466         u8         reserved_at_0[0x8];
7467         u8         local_port[0x8];
7468         u8         reserved_at_10[0x10];
7469
7470         u8         reserved_at_20[0xc];
7471         u8         error_count[0x4];
7472         u8         reserved_at_30[0x10];
7473
7474         u8         reserved_at_40[0xc];
7475         u8         lane[0x4];
7476         u8         reserved_at_50[0x8];
7477         u8         error_type[0x8];
7478 };
7479
7480 struct mlx5_ifc_pcap_reg_bits {
7481         u8         reserved_at_0[0x8];
7482         u8         local_port[0x8];
7483         u8         reserved_at_10[0x10];
7484
7485         u8         port_capability_mask[4][0x20];
7486 };
7487
7488 struct mlx5_ifc_paos_reg_bits {
7489         u8         swid[0x8];
7490         u8         local_port[0x8];
7491         u8         reserved_at_10[0x4];
7492         u8         admin_status[0x4];
7493         u8         reserved_at_18[0x4];
7494         u8         oper_status[0x4];
7495
7496         u8         ase[0x1];
7497         u8         ee[0x1];
7498         u8         reserved_at_22[0x1c];
7499         u8         e[0x2];
7500
7501         u8         reserved_at_40[0x40];
7502 };
7503
7504 struct mlx5_ifc_pamp_reg_bits {
7505         u8         reserved_at_0[0x8];
7506         u8         opamp_group[0x8];
7507         u8         reserved_at_10[0xc];
7508         u8         opamp_group_type[0x4];
7509
7510         u8         start_index[0x10];
7511         u8         reserved_at_30[0x4];
7512         u8         num_of_indices[0xc];
7513
7514         u8         index_data[18][0x10];
7515 };
7516
7517 struct mlx5_ifc_pcmr_reg_bits {
7518         u8         reserved_at_0[0x8];
7519         u8         local_port[0x8];
7520         u8         reserved_at_10[0x2e];
7521         u8         fcs_cap[0x1];
7522         u8         reserved_at_3f[0x1f];
7523         u8         fcs_chk[0x1];
7524         u8         reserved_at_5f[0x1];
7525 };
7526
7527 struct mlx5_ifc_lane_2_module_mapping_bits {
7528         u8         reserved_at_0[0x6];
7529         u8         rx_lane[0x2];
7530         u8         reserved_at_8[0x6];
7531         u8         tx_lane[0x2];
7532         u8         reserved_at_10[0x8];
7533         u8         module[0x8];
7534 };
7535
7536 struct mlx5_ifc_bufferx_reg_bits {
7537         u8         reserved_at_0[0x6];
7538         u8         lossy[0x1];
7539         u8         epsb[0x1];
7540         u8         reserved_at_8[0xc];
7541         u8         size[0xc];
7542
7543         u8         xoff_threshold[0x10];
7544         u8         xon_threshold[0x10];
7545 };
7546
7547 struct mlx5_ifc_set_node_in_bits {
7548         u8         node_description[64][0x8];
7549 };
7550
7551 struct mlx5_ifc_register_power_settings_bits {
7552         u8         reserved_at_0[0x18];
7553         u8         power_settings_level[0x8];
7554
7555         u8         reserved_at_20[0x60];
7556 };
7557
7558 struct mlx5_ifc_register_host_endianness_bits {
7559         u8         he[0x1];
7560         u8         reserved_at_1[0x1f];
7561
7562         u8         reserved_at_20[0x60];
7563 };
7564
7565 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7566         u8         reserved_at_0[0x20];
7567
7568         u8         mkey[0x20];
7569
7570         u8         addressh_63_32[0x20];
7571
7572         u8         addressl_31_0[0x20];
7573 };
7574
7575 struct mlx5_ifc_ud_adrs_vector_bits {
7576         u8         dc_key[0x40];
7577
7578         u8         ext[0x1];
7579         u8         reserved_at_41[0x7];
7580         u8         destination_qp_dct[0x18];
7581
7582         u8         static_rate[0x4];
7583         u8         sl_eth_prio[0x4];
7584         u8         fl[0x1];
7585         u8         mlid[0x7];
7586         u8         rlid_udp_sport[0x10];
7587
7588         u8         reserved_at_80[0x20];
7589
7590         u8         rmac_47_16[0x20];
7591
7592         u8         rmac_15_0[0x10];
7593         u8         tclass[0x8];
7594         u8         hop_limit[0x8];
7595
7596         u8         reserved_at_e0[0x1];
7597         u8         grh[0x1];
7598         u8         reserved_at_e2[0x2];
7599         u8         src_addr_index[0x8];
7600         u8         flow_label[0x14];
7601
7602         u8         rgid_rip[16][0x8];
7603 };
7604
7605 struct mlx5_ifc_pages_req_event_bits {
7606         u8         reserved_at_0[0x10];
7607         u8         function_id[0x10];
7608
7609         u8         num_pages[0x20];
7610
7611         u8         reserved_at_40[0xa0];
7612 };
7613
7614 struct mlx5_ifc_eqe_bits {
7615         u8         reserved_at_0[0x8];
7616         u8         event_type[0x8];
7617         u8         reserved_at_10[0x8];
7618         u8         event_sub_type[0x8];
7619
7620         u8         reserved_at_20[0xe0];
7621
7622         union mlx5_ifc_event_auto_bits event_data;
7623
7624         u8         reserved_at_1e0[0x10];
7625         u8         signature[0x8];
7626         u8         reserved_at_1f8[0x7];
7627         u8         owner[0x1];
7628 };
7629
7630 enum {
7631         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7632 };
7633
7634 struct mlx5_ifc_cmd_queue_entry_bits {
7635         u8         type[0x8];
7636         u8         reserved_at_8[0x18];
7637
7638         u8         input_length[0x20];
7639
7640         u8         input_mailbox_pointer_63_32[0x20];
7641
7642         u8         input_mailbox_pointer_31_9[0x17];
7643         u8         reserved_at_77[0x9];
7644
7645         u8         command_input_inline_data[16][0x8];
7646
7647         u8         command_output_inline_data[16][0x8];
7648
7649         u8         output_mailbox_pointer_63_32[0x20];
7650
7651         u8         output_mailbox_pointer_31_9[0x17];
7652         u8         reserved_at_1b7[0x9];
7653
7654         u8         output_length[0x20];
7655
7656         u8         token[0x8];
7657         u8         signature[0x8];
7658         u8         reserved_at_1f0[0x8];
7659         u8         status[0x7];
7660         u8         ownership[0x1];
7661 };
7662
7663 struct mlx5_ifc_cmd_out_bits {
7664         u8         status[0x8];
7665         u8         reserved_at_8[0x18];
7666
7667         u8         syndrome[0x20];
7668
7669         u8         command_output[0x20];
7670 };
7671
7672 struct mlx5_ifc_cmd_in_bits {
7673         u8         opcode[0x10];
7674         u8         reserved_at_10[0x10];
7675
7676         u8         reserved_at_20[0x10];
7677         u8         op_mod[0x10];
7678
7679         u8         command[0][0x20];
7680 };
7681
7682 struct mlx5_ifc_cmd_if_box_bits {
7683         u8         mailbox_data[512][0x8];
7684
7685         u8         reserved_at_1000[0x180];
7686
7687         u8         next_pointer_63_32[0x20];
7688
7689         u8         next_pointer_31_10[0x16];
7690         u8         reserved_at_11b6[0xa];
7691
7692         u8         block_number[0x20];
7693
7694         u8         reserved_at_11e0[0x8];
7695         u8         token[0x8];
7696         u8         ctrl_signature[0x8];
7697         u8         signature[0x8];
7698 };
7699
7700 struct mlx5_ifc_mtt_bits {
7701         u8         ptag_63_32[0x20];
7702
7703         u8         ptag_31_8[0x18];
7704         u8         reserved_at_38[0x6];
7705         u8         wr_en[0x1];
7706         u8         rd_en[0x1];
7707 };
7708
7709 struct mlx5_ifc_query_wol_rol_out_bits {
7710         u8         status[0x8];
7711         u8         reserved_at_8[0x18];
7712
7713         u8         syndrome[0x20];
7714
7715         u8         reserved_at_40[0x10];
7716         u8         rol_mode[0x8];
7717         u8         wol_mode[0x8];
7718
7719         u8         reserved_at_60[0x20];
7720 };
7721
7722 struct mlx5_ifc_query_wol_rol_in_bits {
7723         u8         opcode[0x10];
7724         u8         reserved_at_10[0x10];
7725
7726         u8         reserved_at_20[0x10];
7727         u8         op_mod[0x10];
7728
7729         u8         reserved_at_40[0x40];
7730 };
7731
7732 struct mlx5_ifc_set_wol_rol_out_bits {
7733         u8         status[0x8];
7734         u8         reserved_at_8[0x18];
7735
7736         u8         syndrome[0x20];
7737
7738         u8         reserved_at_40[0x40];
7739 };
7740
7741 struct mlx5_ifc_set_wol_rol_in_bits {
7742         u8         opcode[0x10];
7743         u8         reserved_at_10[0x10];
7744
7745         u8         reserved_at_20[0x10];
7746         u8         op_mod[0x10];
7747
7748         u8         rol_mode_valid[0x1];
7749         u8         wol_mode_valid[0x1];
7750         u8         reserved_at_42[0xe];
7751         u8         rol_mode[0x8];
7752         u8         wol_mode[0x8];
7753
7754         u8         reserved_at_60[0x20];
7755 };
7756
7757 enum {
7758         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7759         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7760         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7761 };
7762
7763 enum {
7764         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7765         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7766         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7767 };
7768
7769 enum {
7770         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7771         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7772         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7773         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7774         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7775         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7776         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7777         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7778         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7779         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7780         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7781 };
7782
7783 struct mlx5_ifc_initial_seg_bits {
7784         u8         fw_rev_minor[0x10];
7785         u8         fw_rev_major[0x10];
7786
7787         u8         cmd_interface_rev[0x10];
7788         u8         fw_rev_subminor[0x10];
7789
7790         u8         reserved_at_40[0x40];
7791
7792         u8         cmdq_phy_addr_63_32[0x20];
7793
7794         u8         cmdq_phy_addr_31_12[0x14];
7795         u8         reserved_at_b4[0x2];
7796         u8         nic_interface[0x2];
7797         u8         log_cmdq_size[0x4];
7798         u8         log_cmdq_stride[0x4];
7799
7800         u8         command_doorbell_vector[0x20];
7801
7802         u8         reserved_at_e0[0xf00];
7803
7804         u8         initializing[0x1];
7805         u8         reserved_at_fe1[0x4];
7806         u8         nic_interface_supported[0x3];
7807         u8         reserved_at_fe8[0x18];
7808
7809         struct mlx5_ifc_health_buffer_bits health_buffer;
7810
7811         u8         no_dram_nic_offset[0x20];
7812
7813         u8         reserved_at_1220[0x6e40];
7814
7815         u8         reserved_at_8060[0x1f];
7816         u8         clear_int[0x1];
7817
7818         u8         health_syndrome[0x8];
7819         u8         health_counter[0x18];
7820
7821         u8         reserved_at_80a0[0x17fc0];
7822 };
7823
7824 union mlx5_ifc_ports_control_registers_document_bits {
7825         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7826         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7827         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7828         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7829         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7830         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7831         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7832         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7833         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7834         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7835         struct mlx5_ifc_paos_reg_bits paos_reg;
7836         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7837         struct mlx5_ifc_peir_reg_bits peir_reg;
7838         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7839         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7840         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7841         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7842         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7843         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7844         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7845         struct mlx5_ifc_plib_reg_bits plib_reg;
7846         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7847         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7848         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7849         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7850         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7851         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7852         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7853         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7854         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7855         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7856         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7857         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7858         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7859         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7860         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7861         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7862         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7863         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7864         struct mlx5_ifc_pude_reg_bits pude_reg;
7865         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7866         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7867         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7868         u8         reserved_at_0[0x60e0];
7869 };
7870
7871 union mlx5_ifc_debug_enhancements_document_bits {
7872         struct mlx5_ifc_health_buffer_bits health_buffer;
7873         u8         reserved_at_0[0x200];
7874 };
7875
7876 union mlx5_ifc_uplink_pci_interface_document_bits {
7877         struct mlx5_ifc_initial_seg_bits initial_seg;
7878         u8         reserved_at_0[0x20060];
7879 };
7880
7881 struct mlx5_ifc_set_flow_table_root_out_bits {
7882         u8         status[0x8];
7883         u8         reserved_at_8[0x18];
7884
7885         u8         syndrome[0x20];
7886
7887         u8         reserved_at_40[0x40];
7888 };
7889
7890 struct mlx5_ifc_set_flow_table_root_in_bits {
7891         u8         opcode[0x10];
7892         u8         reserved_at_10[0x10];
7893
7894         u8         reserved_at_20[0x10];
7895         u8         op_mod[0x10];
7896
7897         u8         other_vport[0x1];
7898         u8         reserved_at_41[0xf];
7899         u8         vport_number[0x10];
7900
7901         u8         reserved_at_60[0x20];
7902
7903         u8         table_type[0x8];
7904         u8         reserved_at_88[0x18];
7905
7906         u8         reserved_at_a0[0x8];
7907         u8         table_id[0x18];
7908
7909         u8         reserved_at_c0[0x140];
7910 };
7911
7912 enum {
7913         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
7914         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7915 };
7916
7917 struct mlx5_ifc_modify_flow_table_out_bits {
7918         u8         status[0x8];
7919         u8         reserved_at_8[0x18];
7920
7921         u8         syndrome[0x20];
7922
7923         u8         reserved_at_40[0x40];
7924 };
7925
7926 struct mlx5_ifc_modify_flow_table_in_bits {
7927         u8         opcode[0x10];
7928         u8         reserved_at_10[0x10];
7929
7930         u8         reserved_at_20[0x10];
7931         u8         op_mod[0x10];
7932
7933         u8         other_vport[0x1];
7934         u8         reserved_at_41[0xf];
7935         u8         vport_number[0x10];
7936
7937         u8         reserved_at_60[0x10];
7938         u8         modify_field_select[0x10];
7939
7940         u8         table_type[0x8];
7941         u8         reserved_at_88[0x18];
7942
7943         u8         reserved_at_a0[0x8];
7944         u8         table_id[0x18];
7945
7946         u8         reserved_at_c0[0x4];
7947         u8         table_miss_mode[0x4];
7948         u8         reserved_at_c8[0x18];
7949
7950         u8         reserved_at_e0[0x8];
7951         u8         table_miss_id[0x18];
7952
7953         u8         reserved_at_100[0x8];
7954         u8         lag_master_next_table_id[0x18];
7955
7956         u8         reserved_at_120[0x80];
7957 };
7958
7959 struct mlx5_ifc_ets_tcn_config_reg_bits {
7960         u8         g[0x1];
7961         u8         b[0x1];
7962         u8         r[0x1];
7963         u8         reserved_at_3[0x9];
7964         u8         group[0x4];
7965         u8         reserved_at_10[0x9];
7966         u8         bw_allocation[0x7];
7967
7968         u8         reserved_at_20[0xc];
7969         u8         max_bw_units[0x4];
7970         u8         reserved_at_30[0x8];
7971         u8         max_bw_value[0x8];
7972 };
7973
7974 struct mlx5_ifc_ets_global_config_reg_bits {
7975         u8         reserved_at_0[0x2];
7976         u8         r[0x1];
7977         u8         reserved_at_3[0x1d];
7978
7979         u8         reserved_at_20[0xc];
7980         u8         max_bw_units[0x4];
7981         u8         reserved_at_30[0x8];
7982         u8         max_bw_value[0x8];
7983 };
7984
7985 struct mlx5_ifc_qetc_reg_bits {
7986         u8                                         reserved_at_0[0x8];
7987         u8                                         port_number[0x8];
7988         u8                                         reserved_at_10[0x30];
7989
7990         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7991         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7992 };
7993
7994 struct mlx5_ifc_qtct_reg_bits {
7995         u8         reserved_at_0[0x8];
7996         u8         port_number[0x8];
7997         u8         reserved_at_10[0xd];
7998         u8         prio[0x3];
7999
8000         u8         reserved_at_20[0x1d];
8001         u8         tclass[0x3];
8002 };
8003
8004 struct mlx5_ifc_mcia_reg_bits {
8005         u8         l[0x1];
8006         u8         reserved_at_1[0x7];
8007         u8         module[0x8];
8008         u8         reserved_at_10[0x8];
8009         u8         status[0x8];
8010
8011         u8         i2c_device_address[0x8];
8012         u8         page_number[0x8];
8013         u8         device_address[0x10];
8014
8015         u8         reserved_at_40[0x10];
8016         u8         size[0x10];
8017
8018         u8         reserved_at_60[0x20];
8019
8020         u8         dword_0[0x20];
8021         u8         dword_1[0x20];
8022         u8         dword_2[0x20];
8023         u8         dword_3[0x20];
8024         u8         dword_4[0x20];
8025         u8         dword_5[0x20];
8026         u8         dword_6[0x20];
8027         u8         dword_7[0x20];
8028         u8         dword_8[0x20];
8029         u8         dword_9[0x20];
8030         u8         dword_10[0x20];
8031         u8         dword_11[0x20];
8032 };
8033
8034 struct mlx5_ifc_dcbx_param_bits {
8035         u8         dcbx_cee_cap[0x1];
8036         u8         dcbx_ieee_cap[0x1];
8037         u8         dcbx_standby_cap[0x1];
8038         u8         reserved_at_0[0x5];
8039         u8         port_number[0x8];
8040         u8         reserved_at_10[0xa];
8041         u8         max_application_table_size[6];
8042         u8         reserved_at_20[0x15];
8043         u8         version_oper[0x3];
8044         u8         reserved_at_38[5];
8045         u8         version_admin[0x3];
8046         u8         willing_admin[0x1];
8047         u8         reserved_at_41[0x3];
8048         u8         pfc_cap_oper[0x4];
8049         u8         reserved_at_48[0x4];
8050         u8         pfc_cap_admin[0x4];
8051         u8         reserved_at_50[0x4];
8052         u8         num_of_tc_oper[0x4];
8053         u8         reserved_at_58[0x4];
8054         u8         num_of_tc_admin[0x4];
8055         u8         remote_willing[0x1];
8056         u8         reserved_at_61[3];
8057         u8         remote_pfc_cap[4];
8058         u8         reserved_at_68[0x14];
8059         u8         remote_num_of_tc[0x4];
8060         u8         reserved_at_80[0x18];
8061         u8         error[0x8];
8062         u8         reserved_at_a0[0x160];
8063 };
8064
8065 struct mlx5_ifc_lagc_bits {
8066         u8         reserved_at_0[0x1d];
8067         u8         lag_state[0x3];
8068
8069         u8         reserved_at_20[0x14];
8070         u8         tx_remap_affinity_2[0x4];
8071         u8         reserved_at_38[0x4];
8072         u8         tx_remap_affinity_1[0x4];
8073 };
8074
8075 struct mlx5_ifc_create_lag_out_bits {
8076         u8         status[0x8];
8077         u8         reserved_at_8[0x18];
8078
8079         u8         syndrome[0x20];
8080
8081         u8         reserved_at_40[0x40];
8082 };
8083
8084 struct mlx5_ifc_create_lag_in_bits {
8085         u8         opcode[0x10];
8086         u8         reserved_at_10[0x10];
8087
8088         u8         reserved_at_20[0x10];
8089         u8         op_mod[0x10];
8090
8091         struct mlx5_ifc_lagc_bits ctx;
8092 };
8093
8094 struct mlx5_ifc_modify_lag_out_bits {
8095         u8         status[0x8];
8096         u8         reserved_at_8[0x18];
8097
8098         u8         syndrome[0x20];
8099
8100         u8         reserved_at_40[0x40];
8101 };
8102
8103 struct mlx5_ifc_modify_lag_in_bits {
8104         u8         opcode[0x10];
8105         u8         reserved_at_10[0x10];
8106
8107         u8         reserved_at_20[0x10];
8108         u8         op_mod[0x10];
8109
8110         u8         reserved_at_40[0x20];
8111         u8         field_select[0x20];
8112
8113         struct mlx5_ifc_lagc_bits ctx;
8114 };
8115
8116 struct mlx5_ifc_query_lag_out_bits {
8117         u8         status[0x8];
8118         u8         reserved_at_8[0x18];
8119
8120         u8         syndrome[0x20];
8121
8122         u8         reserved_at_40[0x40];
8123
8124         struct mlx5_ifc_lagc_bits ctx;
8125 };
8126
8127 struct mlx5_ifc_query_lag_in_bits {
8128         u8         opcode[0x10];
8129         u8         reserved_at_10[0x10];
8130
8131         u8         reserved_at_20[0x10];
8132         u8         op_mod[0x10];
8133
8134         u8         reserved_at_40[0x40];
8135 };
8136
8137 struct mlx5_ifc_destroy_lag_out_bits {
8138         u8         status[0x8];
8139         u8         reserved_at_8[0x18];
8140
8141         u8         syndrome[0x20];
8142
8143         u8         reserved_at_40[0x40];
8144 };
8145
8146 struct mlx5_ifc_destroy_lag_in_bits {
8147         u8         opcode[0x10];
8148         u8         reserved_at_10[0x10];
8149
8150         u8         reserved_at_20[0x10];
8151         u8         op_mod[0x10];
8152
8153         u8         reserved_at_40[0x40];
8154 };
8155
8156 struct mlx5_ifc_create_vport_lag_out_bits {
8157         u8         status[0x8];
8158         u8         reserved_at_8[0x18];
8159
8160         u8         syndrome[0x20];
8161
8162         u8         reserved_at_40[0x40];
8163 };
8164
8165 struct mlx5_ifc_create_vport_lag_in_bits {
8166         u8         opcode[0x10];
8167         u8         reserved_at_10[0x10];
8168
8169         u8         reserved_at_20[0x10];
8170         u8         op_mod[0x10];
8171
8172         u8         reserved_at_40[0x40];
8173 };
8174
8175 struct mlx5_ifc_destroy_vport_lag_out_bits {
8176         u8         status[0x8];
8177         u8         reserved_at_8[0x18];
8178
8179         u8         syndrome[0x20];
8180
8181         u8         reserved_at_40[0x40];
8182 };
8183
8184 struct mlx5_ifc_destroy_vport_lag_in_bits {
8185         u8         opcode[0x10];
8186         u8         reserved_at_10[0x10];
8187
8188         u8         reserved_at_20[0x10];
8189         u8         op_mod[0x10];
8190
8191         u8         reserved_at_40[0x40];
8192 };
8193
8194 #endif /* MLX5_IFC_H */