include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         reserved_at_4[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         vlan_tag[0x1];
 369         u8         reserved_at_91[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_vlan_tag[0x1];
 402         u8         inner_second_vlan_tag[0x1];
 403         u8         reserved_at_62[0xe];
 404         u8         gre_protocol[0x10];
 405
 406         u8         gre_key_h[0x18];
 407         u8         gre_key_l[0x8];
 408
 409         u8         vxlan_vni[0x18];
 410         u8         reserved_at_b8[0x8];
 411
 412         u8         reserved_at_c0[0x20];
 413
 414         u8         reserved_at_e0[0xc];
 415         u8         outer_ipv6_flow_label[0x14];
 416
 417         u8         reserved_at_100[0xc];
 418         u8         inner_ipv6_flow_label[0x14];
 419
 420         u8         reserved_at_120[0xe0];
 421 };
 422
 423 struct mlx5_ifc_cmd_pas_bits {
 424         u8         pa_h[0x20];
 425
 426         u8         pa_l[0x14];
 427         u8         reserved_at_34[0xc];
 428 };
 429
 430 struct mlx5_ifc_uint64_bits {
 431         u8         hi[0x20];
 432
 433         u8         lo[0x20];
 434 };
 435
 436 enum {
 437         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 438         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 439         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 440         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 441         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 442         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 443         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 444         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 445         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 446         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 447 };
 448
 449 struct mlx5_ifc_ads_bits {
 450         u8         fl[0x1];
 451         u8         free_ar[0x1];
 452         u8         reserved_at_2[0xe];
 453         u8         pkey_index[0x10];
 454
 455         u8         reserved_at_20[0x8];
 456         u8         grh[0x1];
 457         u8         mlid[0x7];
 458         u8         rlid[0x10];
 459
 460         u8         ack_timeout[0x5];
 461         u8         reserved_at_45[0x3];
 462         u8         src_addr_index[0x8];
 463         u8         reserved_at_50[0x4];
 464         u8         stat_rate[0x4];
 465         u8         hop_limit[0x8];
 466
 467         u8         reserved_at_60[0x4];
 468         u8         tclass[0x8];
 469         u8         flow_label[0x14];
 470
 471         u8         rgid_rip[16][0x8];
 472
 473         u8         reserved_at_100[0x4];
 474         u8         f_dscp[0x1];
 475         u8         f_ecn[0x1];
 476         u8         reserved_at_106[0x1];
 477         u8         f_eth_prio[0x1];
 478         u8         ecn[0x2];
 479         u8         dscp[0x6];
 480         u8         udp_sport[0x10];
 481
 482         u8         dei_cfi[0x1];
 483         u8         eth_prio[0x3];
 484         u8         sl[0x4];
 485         u8         port[0x8];
 486         u8         rmac_47_32[0x10];
 487
 488         u8         rmac_31_0[0x20];
 489 };
 490
 491 struct mlx5_ifc_flow_table_nic_cap_bits {
 492         u8         nic_rx_multi_path_tirs[0x1];
 493         u8         nic_rx_multi_path_tirs_fts[0x1];
 494         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 495         u8         reserved_at_3[0x1fd];
 496
 497         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 498
 499         u8         reserved_at_400[0x200];
 500
 501         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 504
 505         u8         reserved_at_a00[0x200];
 506
 507         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 508
 509         u8         reserved_at_e00[0x7200];
 510 };
 511
 512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 513         u8     reserved_at_0[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 520
 521         u8      reserved_at_800[0x7800];
 522 };
 523
 524 struct mlx5_ifc_e_switch_cap_bits {
 525         u8         vport_svlan_strip[0x1];
 526         u8         vport_cvlan_strip[0x1];
 527         u8         vport_svlan_insert[0x1];
 528         u8         vport_cvlan_insert_if_not_exist[0x1];
 529         u8         vport_cvlan_insert_overwrite[0x1];
 530         u8         reserved_at_5[0x19];
 531         u8         nic_vport_node_guid_modify[0x1];
 532         u8         nic_vport_port_guid_modify[0x1];
 533
 534         u8         vxlan_encap_decap[0x1];
 535         u8         nvgre_encap_decap[0x1];
 536         u8         reserved_at_22[0x9];
 537         u8         log_max_encap_headers[0x5];
 538         u8         reserved_2b[0x6];
 539         u8         max_encap_header_size[0xa];
 540
 541         u8         reserved_40[0x7c0];
 542
 543 };
 544
 545 struct mlx5_ifc_qos_cap_bits {
 546         u8         packet_pacing[0x1];
 547         u8         esw_scheduling[0x1];
 548         u8         reserved_at_2[0x1e];
 549
 550         u8         reserved_at_20[0x20];
 551
 552         u8         packet_pacing_max_rate[0x20];
 553
 554         u8         packet_pacing_min_rate[0x20];
 555
 556         u8         reserved_at_80[0x10];
 557         u8         packet_pacing_rate_table_size[0x10];
 558
 559         u8         esw_element_type[0x10];
 560         u8         esw_tsar_type[0x10];
 561
 562         u8         reserved_at_c0[0x10];
 563         u8         max_qos_para_vport[0x10];
 564
 565         u8         max_tsar_bw_share[0x20];
 566
 567         u8         reserved_at_100[0x700];
 568 };
 569
 570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 571         u8         csum_cap[0x1];
 572         u8         vlan_cap[0x1];
 573         u8         lro_cap[0x1];
 574         u8         lro_psh_flag[0x1];
 575         u8         lro_time_stamp[0x1];
 576         u8         reserved_at_5[0x3];
 577         u8         self_lb_en_modifiable[0x1];
 578         u8         reserved_at_9[0x2];
 579         u8         max_lso_cap[0x5];
 580         u8         multi_pkt_send_wqe[0x2];
 581         u8         wqe_inline_mode[0x2];
 582         u8         rss_ind_tbl_cap[0x4];
 583         u8         reg_umr_sq[0x1];
 584         u8         scatter_fcs[0x1];
 585         u8         reserved_at_1a[0x1];
 586         u8         tunnel_lso_const_out_ip_id[0x1];
 587         u8         reserved_at_1c[0x2];
 588         u8         tunnel_statless_gre[0x1];
 589         u8         tunnel_stateless_vxlan[0x1];
 590
 591         u8         reserved_at_20[0x20];
 592
 593         u8         reserved_at_40[0x10];
 594         u8         lro_min_mss_size[0x10];
 595
 596         u8         reserved_at_60[0x120];
 597
 598         u8         lro_timer_supported_periods[4][0x20];
 599
 600         u8         reserved_at_200[0x600];
 601 };
 602
 603 struct mlx5_ifc_roce_cap_bits {
 604         u8         roce_apm[0x1];
 605         u8         reserved_at_1[0x1f];
 606
 607         u8         reserved_at_20[0x60];
 608
 609         u8         reserved_at_80[0xc];
 610         u8         l3_type[0x4];
 611         u8         reserved_at_90[0x8];
 612         u8         roce_version[0x8];
 613
 614         u8         reserved_at_a0[0x10];
 615         u8         r_roce_dest_udp_port[0x10];
 616
 617         u8         r_roce_max_src_udp_port[0x10];
 618         u8         r_roce_min_src_udp_port[0x10];
 619
 620         u8         reserved_at_e0[0x10];
 621         u8         roce_address_table_size[0x10];
 622
 623         u8         reserved_at_100[0x700];
 624 };
 625
 626 enum {
 627         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 628         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 636 };
 637
 638 enum {
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 648 };
 649
 650 struct mlx5_ifc_atomic_caps_bits {
 651         u8         reserved_at_0[0x40];
 652
 653         u8         atomic_req_8B_endianess_mode[0x2];
 654         u8         reserved_at_42[0x4];
 655         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 656
 657         u8         reserved_at_47[0x19];
 658
 659         u8         reserved_at_60[0x20];
 660
 661         u8         reserved_at_80[0x10];
 662         u8         atomic_operations[0x10];
 663
 664         u8         reserved_at_a0[0x10];
 665         u8         atomic_size_qp[0x10];
 666
 667         u8         reserved_at_c0[0x10];
 668         u8         atomic_size_dc[0x10];
 669
 670         u8         reserved_at_e0[0x720];
 671 };
 672
 673 struct mlx5_ifc_odp_cap_bits {
 674         u8         reserved_at_0[0x40];
 675
 676         u8         sig[0x1];
 677         u8         reserved_at_41[0x1f];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 682
 683         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 686
 687         u8         reserved_at_e0[0x720];
 688 };
 689
 690 struct mlx5_ifc_calc_op {
 691         u8        reserved_at_0[0x10];
 692         u8        reserved_at_10[0x9];
 693         u8        op_swap_endianness[0x1];
 694         u8        op_min[0x1];
 695         u8        op_xor[0x1];
 696         u8        op_or[0x1];
 697         u8        op_and[0x1];
 698         u8        op_max[0x1];
 699         u8        op_add[0x1];
 700 };
 701
 702 struct mlx5_ifc_vector_calc_cap_bits {
 703         u8         calc_matrix[0x1];
 704         u8         reserved_at_1[0x1f];
 705         u8         reserved_at_20[0x8];
 706         u8         max_vec_count[0x8];
 707         u8         reserved_at_30[0xd];
 708         u8         max_chunk_size[0x3];
 709         struct mlx5_ifc_calc_op calc0;
 710         struct mlx5_ifc_calc_op calc1;
 711         struct mlx5_ifc_calc_op calc2;
 712         struct mlx5_ifc_calc_op calc3;
 713
 714         u8         reserved_at_e0[0x720];
 715 };
 716
 717 enum {
 718         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 719         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 720         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 721 };
 722
 723 enum {
 724         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 725         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 726 };
 727
 728 enum {
 729         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 730         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 734 };
 735
 736 enum {
 737         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 738         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 743 };
 744
 745 enum {
 746         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 747         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 748 };
 749
 750 enum {
 751         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 752         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 754 };
 755
 756 enum {
 757         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 758         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 759 };
 760
 761 struct mlx5_ifc_cmd_hca_cap_bits {
 762         u8         reserved_at_0[0x80];
 763
 764         u8         log_max_srq_sz[0x8];
 765         u8         log_max_qp_sz[0x8];
 766         u8         reserved_at_90[0xb];
 767         u8         log_max_qp[0x5];
 768
 769         u8         reserved_at_a0[0xb];
 770         u8         log_max_srq[0x5];
 771         u8         reserved_at_b0[0x10];
 772
 773         u8         reserved_at_c0[0x8];
 774         u8         log_max_cq_sz[0x8];
 775         u8         reserved_at_d0[0xb];
 776         u8         log_max_cq[0x5];
 777
 778         u8         log_max_eq_sz[0x8];
 779         u8         reserved_at_e8[0x2];
 780         u8         log_max_mkey[0x6];
 781         u8         reserved_at_f0[0xc];
 782         u8         log_max_eq[0x4];
 783
 784         u8         max_indirection[0x8];
 785         u8         reserved_at_108[0x1];
 786         u8         log_max_mrw_sz[0x7];
 787         u8         reserved_at_110[0x2];
 788         u8         log_max_bsf_list_size[0x6];
 789         u8         reserved_at_118[0x2];
 790         u8         log_max_klm_list_size[0x6];
 791
 792         u8         reserved_at_120[0xa];
 793         u8         log_max_ra_req_dc[0x6];
 794         u8         reserved_at_130[0xa];
 795         u8         log_max_ra_res_dc[0x6];
 796
 797         u8         reserved_at_140[0xa];
 798         u8         log_max_ra_req_qp[0x6];
 799         u8         reserved_at_150[0xa];
 800         u8         log_max_ra_res_qp[0x6];
 801
 802         u8         pad_cap[0x1];
 803         u8         cc_query_allowed[0x1];
 804         u8         cc_modify_allowed[0x1];
 805         u8         reserved_at_163[0xd];
 806         u8         gid_table_size[0x10];
 807
 808         u8         out_of_seq_cnt[0x1];
 809         u8         vport_counters[0x1];
 810         u8         retransmission_q_counters[0x1];
 811         u8         reserved_at_183[0x1];
 812         u8         modify_rq_counter_set_id[0x1];
 813         u8         reserved_at_185[0x1];
 814         u8         max_qp_cnt[0xa];
 815         u8         pkey_table_size[0x10];
 816
 817         u8         vport_group_manager[0x1];
 818         u8         vhca_group_manager[0x1];
 819         u8         ib_virt[0x1];
 820         u8         eth_virt[0x1];
 821         u8         reserved_at_1a4[0x1];
 822         u8         ets[0x1];
 823         u8         nic_flow_table[0x1];
 824         u8         eswitch_flow_table[0x1];
 825         u8         early_vf_enable[0x1];
 826         u8         reserved_at_1a9[0x2];
 827         u8         local_ca_ack_delay[0x5];
 828         u8         port_module_event[0x1];
 829         u8         reserved_at_1b0[0x1];
 830         u8         ports_check[0x1];
 831         u8         reserved_at_1b2[0x1];
 832         u8         disable_link_up[0x1];
 833         u8         beacon_led[0x1];
 834         u8         port_type[0x2];
 835         u8         num_ports[0x8];
 836
 837         u8         reserved_at_1c0[0x3];
 838         u8         log_max_msg[0x5];
 839         u8         reserved_at_1c8[0x4];
 840         u8         max_tc[0x4];
 841         u8         reserved_at_1d0[0x1];
 842         u8         dcbx[0x1];
 843         u8         reserved_at_1d2[0x4];
 844         u8         rol_s[0x1];
 845         u8         rol_g[0x1];
 846         u8         reserved_at_1d8[0x1];
 847         u8         wol_s[0x1];
 848         u8         wol_g[0x1];
 849         u8         wol_a[0x1];
 850         u8         wol_b[0x1];
 851         u8         wol_m[0x1];
 852         u8         wol_u[0x1];
 853         u8         wol_p[0x1];
 854
 855         u8         stat_rate_support[0x10];
 856         u8         reserved_at_1f0[0xc];
 857         u8         cqe_version[0x4];
 858
 859         u8         compact_address_vector[0x1];
 860         u8         striding_rq[0x1];
 861         u8         reserved_at_201[0x2];
 862         u8         ipoib_basic_offloads[0x1];
 863         u8         reserved_at_205[0xa];
 864         u8         drain_sigerr[0x1];
 865         u8         cmdif_checksum[0x2];
 866         u8         sigerr_cqe[0x1];
 867         u8         reserved_at_213[0x1];
 868         u8         wq_signature[0x1];
 869         u8         sctr_data_cqe[0x1];
 870         u8         reserved_at_216[0x1];
 871         u8         sho[0x1];
 872         u8         tph[0x1];
 873         u8         rf[0x1];
 874         u8         dct[0x1];
 875         u8         qos[0x1];
 876         u8         eth_net_offloads[0x1];
 877         u8         roce[0x1];
 878         u8         atomic[0x1];
 879         u8         reserved_at_21f[0x1];
 880
 881         u8         cq_oi[0x1];
 882         u8         cq_resize[0x1];
 883         u8         cq_moderation[0x1];
 884         u8         reserved_at_223[0x3];
 885         u8         cq_eq_remap[0x1];
 886         u8         pg[0x1];
 887         u8         block_lb_mc[0x1];
 888         u8         reserved_at_229[0x1];
 889         u8         scqe_break_moderation[0x1];
 890         u8         cq_period_start_from_cqe[0x1];
 891         u8         cd[0x1];
 892         u8         reserved_at_22d[0x1];
 893         u8         apm[0x1];
 894         u8         vector_calc[0x1];
 895         u8         umr_ptr_rlky[0x1];
 896         u8         imaicl[0x1];
 897         u8         reserved_at_232[0x4];
 898         u8         qkv[0x1];
 899         u8         pkv[0x1];
 900         u8         set_deth_sqpn[0x1];
 901         u8         reserved_at_239[0x3];
 902         u8         xrc[0x1];
 903         u8         ud[0x1];
 904         u8         uc[0x1];
 905         u8         rc[0x1];
 906
 907         u8         reserved_at_240[0xa];
 908         u8         uar_sz[0x6];
 909         u8         reserved_at_250[0x8];
 910         u8         log_pg_sz[0x8];
 911
 912         u8         bf[0x1];
 913         u8         driver_version[0x1];
 914         u8         pad_tx_eth_packet[0x1];
 915         u8         reserved_at_263[0x8];
 916         u8         log_bf_reg_size[0x5];
 917
 918         u8         reserved_at_270[0xb];
 919         u8         lag_master[0x1];
 920         u8         num_lag_ports[0x4];
 921
 922         u8         reserved_at_280[0x10];
 923         u8         max_wqe_sz_sq[0x10];
 924
 925         u8         reserved_at_2a0[0x10];
 926         u8         max_wqe_sz_rq[0x10];
 927
 928         u8         reserved_at_2c0[0x10];
 929         u8         max_wqe_sz_sq_dc[0x10];
 930
 931         u8         reserved_at_2e0[0x7];
 932         u8         max_qp_mcg[0x19];
 933
 934         u8         reserved_at_300[0x18];
 935         u8         log_max_mcg[0x8];
 936
 937         u8         reserved_at_320[0x3];
 938         u8         log_max_transport_domain[0x5];
 939         u8         reserved_at_328[0x3];
 940         u8         log_max_pd[0x5];
 941         u8         reserved_at_330[0xb];
 942         u8         log_max_xrcd[0x5];
 943
 944         u8         reserved_at_340[0x8];
 945         u8         log_max_flow_counter_bulk[0x8];
 946         u8         max_flow_counter[0x10];
 947
 948
 949         u8         reserved_at_360[0x3];
 950         u8         log_max_rq[0x5];
 951         u8         reserved_at_368[0x3];
 952         u8         log_max_sq[0x5];
 953         u8         reserved_at_370[0x3];
 954         u8         log_max_tir[0x5];
 955         u8         reserved_at_378[0x3];
 956         u8         log_max_tis[0x5];
 957
 958         u8         basic_cyclic_rcv_wqe[0x1];
 959         u8         reserved_at_381[0x2];
 960         u8         log_max_rmp[0x5];
 961         u8         reserved_at_388[0x3];
 962         u8         log_max_rqt[0x5];
 963         u8         reserved_at_390[0x3];
 964         u8         log_max_rqt_size[0x5];
 965         u8         reserved_at_398[0x3];
 966         u8         log_max_tis_per_sq[0x5];
 967
 968         u8         reserved_at_3a0[0x3];
 969         u8         log_max_stride_sz_rq[0x5];
 970         u8         reserved_at_3a8[0x3];
 971         u8         log_min_stride_sz_rq[0x5];
 972         u8         reserved_at_3b0[0x3];
 973         u8         log_max_stride_sz_sq[0x5];
 974         u8         reserved_at_3b8[0x3];
 975         u8         log_min_stride_sz_sq[0x5];
 976
 977         u8         reserved_at_3c0[0x1b];
 978         u8         log_max_wq_sz[0x5];
 979
 980         u8         nic_vport_change_event[0x1];
 981         u8         reserved_at_3e1[0xa];
 982         u8         log_max_vlan_list[0x5];
 983         u8         reserved_at_3f0[0x3];
 984         u8         log_max_current_mc_list[0x5];
 985         u8         reserved_at_3f8[0x3];
 986         u8         log_max_current_uc_list[0x5];
 987
 988         u8         reserved_at_400[0x80];
 989
 990         u8         reserved_at_480[0x3];
 991         u8         log_max_l2_table[0x5];
 992         u8         reserved_at_488[0x8];
 993         u8         log_uar_page_sz[0x10];
 994
 995         u8         reserved_at_4a0[0x20];
 996         u8         device_frequency_mhz[0x20];
 997         u8         device_frequency_khz[0x20];
 998
 999         u8         reserved_at_500[0x80];
1000
1001         u8         reserved_at_580[0x3f];
1002         u8         cqe_compression[0x1];
1003
1004         u8         cqe_compression_timeout[0x10];
1005         u8         cqe_compression_max_num[0x10];
1006
1007         u8         reserved_at_5e0[0x10];
1008         u8         tag_matching[0x1];
1009         u8         rndv_offload_rc[0x1];
1010         u8         rndv_offload_dc[0x1];
1011         u8         log_tag_matching_list_sz[0x5];
1012         u8         reserved_at_5e8[0x3];
1013         u8         log_max_xrq[0x5];
1014
1015         u8         reserved_at_5f0[0x200];
1016 };
1017
1018 enum mlx5_flow_destination_type {
1019         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1020         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1021         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1022
1023         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1024 };
1025
1026 struct mlx5_ifc_dest_format_struct_bits {
1027         u8         destination_type[0x8];
1028         u8         destination_id[0x18];
1029
1030         u8         reserved_at_20[0x20];
1031 };
1032
1033 struct mlx5_ifc_flow_counter_list_bits {
1034         u8         clear[0x1];
1035         u8         num_of_counters[0xf];
1036         u8         flow_counter_id[0x10];
1037
1038         u8         reserved_at_20[0x20];
1039 };
1040
1041 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1042         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1043         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1044         u8         reserved_at_0[0x40];
1045 };
1046
1047 struct mlx5_ifc_fte_match_param_bits {
1048         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1049
1050         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1051
1052         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1053
1054         u8         reserved_at_600[0xa00];
1055 };
1056
1057 enum {
1058         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1059         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1060         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1061         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1062         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1063 };
1064
1065 struct mlx5_ifc_rx_hash_field_select_bits {
1066         u8         l3_prot_type[0x1];
1067         u8         l4_prot_type[0x1];
1068         u8         selected_fields[0x1e];
1069 };
1070
1071 enum {
1072         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1073         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1074 };
1075
1076 enum {
1077         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1078         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1079 };
1080
1081 struct mlx5_ifc_wq_bits {
1082         u8         wq_type[0x4];
1083         u8         wq_signature[0x1];
1084         u8         end_padding_mode[0x2];
1085         u8         cd_slave[0x1];
1086         u8         reserved_at_8[0x18];
1087
1088         u8         hds_skip_first_sge[0x1];
1089         u8         log2_hds_buf_size[0x3];
1090         u8         reserved_at_24[0x7];
1091         u8         page_offset[0x5];
1092         u8         lwm[0x10];
1093
1094         u8         reserved_at_40[0x8];
1095         u8         pd[0x18];
1096
1097         u8         reserved_at_60[0x8];
1098         u8         uar_page[0x18];
1099
1100         u8         dbr_addr[0x40];
1101
1102         u8         hw_counter[0x20];
1103
1104         u8         sw_counter[0x20];
1105
1106         u8         reserved_at_100[0xc];
1107         u8         log_wq_stride[0x4];
1108         u8         reserved_at_110[0x3];
1109         u8         log_wq_pg_sz[0x5];
1110         u8         reserved_at_118[0x3];
1111         u8         log_wq_sz[0x5];
1112
1113         u8         reserved_at_120[0x15];
1114         u8         log_wqe_num_of_strides[0x3];
1115         u8         two_byte_shift_en[0x1];
1116         u8         reserved_at_139[0x4];
1117         u8         log_wqe_stride_size[0x3];
1118
1119         u8         reserved_at_140[0x4c0];
1120
1121         struct mlx5_ifc_cmd_pas_bits pas[0];
1122 };
1123
1124 struct mlx5_ifc_rq_num_bits {
1125         u8         reserved_at_0[0x8];
1126         u8         rq_num[0x18];
1127 };
1128
1129 struct mlx5_ifc_mac_address_layout_bits {
1130         u8         reserved_at_0[0x10];
1131         u8         mac_addr_47_32[0x10];
1132
1133         u8         mac_addr_31_0[0x20];
1134 };
1135
1136 struct mlx5_ifc_vlan_layout_bits {
1137         u8         reserved_at_0[0x14];
1138         u8         vlan[0x0c];
1139
1140         u8         reserved_at_20[0x20];
1141 };
1142
1143 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1144         u8         reserved_at_0[0xa0];
1145
1146         u8         min_time_between_cnps[0x20];
1147
1148         u8         reserved_at_c0[0x12];
1149         u8         cnp_dscp[0x6];
1150         u8         reserved_at_d8[0x5];
1151         u8         cnp_802p_prio[0x3];
1152
1153         u8         reserved_at_e0[0x720];
1154 };
1155
1156 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1157         u8         reserved_at_0[0x60];
1158
1159         u8         reserved_at_60[0x4];
1160         u8         clamp_tgt_rate[0x1];
1161         u8         reserved_at_65[0x3];
1162         u8         clamp_tgt_rate_after_time_inc[0x1];
1163         u8         reserved_at_69[0x17];
1164
1165         u8         reserved_at_80[0x20];
1166
1167         u8         rpg_time_reset[0x20];
1168
1169         u8         rpg_byte_reset[0x20];
1170
1171         u8         rpg_threshold[0x20];
1172
1173         u8         rpg_max_rate[0x20];
1174
1175         u8         rpg_ai_rate[0x20];
1176
1177         u8         rpg_hai_rate[0x20];
1178
1179         u8         rpg_gd[0x20];
1180
1181         u8         rpg_min_dec_fac[0x20];
1182
1183         u8         rpg_min_rate[0x20];
1184
1185         u8         reserved_at_1c0[0xe0];
1186
1187         u8         rate_to_set_on_first_cnp[0x20];
1188
1189         u8         dce_tcp_g[0x20];
1190
1191         u8         dce_tcp_rtt[0x20];
1192
1193         u8         rate_reduce_monitor_period[0x20];
1194
1195         u8         reserved_at_320[0x20];
1196
1197         u8         initial_alpha_value[0x20];
1198
1199         u8         reserved_at_360[0x4a0];
1200 };
1201
1202 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1203         u8         reserved_at_0[0x80];
1204
1205         u8         rppp_max_rps[0x20];
1206
1207         u8         rpg_time_reset[0x20];
1208
1209         u8         rpg_byte_reset[0x20];
1210
1211         u8         rpg_threshold[0x20];
1212
1213         u8         rpg_max_rate[0x20];
1214
1215         u8         rpg_ai_rate[0x20];
1216
1217         u8         rpg_hai_rate[0x20];
1218
1219         u8         rpg_gd[0x20];
1220
1221         u8         rpg_min_dec_fac[0x20];
1222
1223         u8         rpg_min_rate[0x20];
1224
1225         u8         reserved_at_1c0[0x640];
1226 };
1227
1228 enum {
1229         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1230         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1231         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1232 };
1233
1234 struct mlx5_ifc_resize_field_select_bits {
1235         u8         resize_field_select[0x20];
1236 };
1237
1238 enum {
1239         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1240         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1241         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1242         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1243 };
1244
1245 struct mlx5_ifc_modify_field_select_bits {
1246         u8         modify_field_select[0x20];
1247 };
1248
1249 struct mlx5_ifc_field_select_r_roce_np_bits {
1250         u8         field_select_r_roce_np[0x20];
1251 };
1252
1253 struct mlx5_ifc_field_select_r_roce_rp_bits {
1254         u8         field_select_r_roce_rp[0x20];
1255 };
1256
1257 enum {
1258         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1259         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1260         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1261         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1262         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1268 };
1269
1270 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1271         u8         field_select_8021qaurp[0x20];
1272 };
1273
1274 struct mlx5_ifc_phys_layer_cntrs_bits {
1275         u8         time_since_last_clear_high[0x20];
1276
1277         u8         time_since_last_clear_low[0x20];
1278
1279         u8         symbol_errors_high[0x20];
1280
1281         u8         symbol_errors_low[0x20];
1282
1283         u8         sync_headers_errors_high[0x20];
1284
1285         u8         sync_headers_errors_low[0x20];
1286
1287         u8         edpl_bip_errors_lane0_high[0x20];
1288
1289         u8         edpl_bip_errors_lane0_low[0x20];
1290
1291         u8         edpl_bip_errors_lane1_high[0x20];
1292
1293         u8         edpl_bip_errors_lane1_low[0x20];
1294
1295         u8         edpl_bip_errors_lane2_high[0x20];
1296
1297         u8         edpl_bip_errors_lane2_low[0x20];
1298
1299         u8         edpl_bip_errors_lane3_high[0x20];
1300
1301         u8         edpl_bip_errors_lane3_low[0x20];
1302
1303         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1304
1305         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1306
1307         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1308
1309         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1310
1311         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1312
1313         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1314
1315         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1316
1317         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1318
1319         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1320
1321         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1322
1323         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1324
1325         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1326
1327         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1328
1329         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1330
1331         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1332
1333         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1334
1335         u8         rs_fec_corrected_blocks_high[0x20];
1336
1337         u8         rs_fec_corrected_blocks_low[0x20];
1338
1339         u8         rs_fec_uncorrectable_blocks_high[0x20];
1340
1341         u8         rs_fec_uncorrectable_blocks_low[0x20];
1342
1343         u8         rs_fec_no_errors_blocks_high[0x20];
1344
1345         u8         rs_fec_no_errors_blocks_low[0x20];
1346
1347         u8         rs_fec_single_error_blocks_high[0x20];
1348
1349         u8         rs_fec_single_error_blocks_low[0x20];
1350
1351         u8         rs_fec_corrected_symbols_total_high[0x20];
1352
1353         u8         rs_fec_corrected_symbols_total_low[0x20];
1354
1355         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1356
1357         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1358
1359         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1360
1361         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1362
1363         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1364
1365         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1366
1367         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1368
1369         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1370
1371         u8         link_down_events[0x20];
1372
1373         u8         successful_recovery_events[0x20];
1374
1375         u8         reserved_at_640[0x180];
1376 };
1377
1378 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1379         u8         symbol_error_counter[0x10];
1380
1381         u8         link_error_recovery_counter[0x8];
1382
1383         u8         link_downed_counter[0x8];
1384
1385         u8         port_rcv_errors[0x10];
1386
1387         u8         port_rcv_remote_physical_errors[0x10];
1388
1389         u8         port_rcv_switch_relay_errors[0x10];
1390
1391         u8         port_xmit_discards[0x10];
1392
1393         u8         port_xmit_constraint_errors[0x8];
1394
1395         u8         port_rcv_constraint_errors[0x8];
1396
1397         u8         reserved_at_70[0x8];
1398
1399         u8         link_overrun_errors[0x8];
1400
1401         u8         reserved_at_80[0x10];
1402
1403         u8         vl_15_dropped[0x10];
1404
1405         u8         reserved_at_a0[0xa0];
1406 };
1407
1408 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1409         u8         transmit_queue_high[0x20];
1410
1411         u8         transmit_queue_low[0x20];
1412
1413         u8         reserved_at_40[0x780];
1414 };
1415
1416 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1417         u8         rx_octets_high[0x20];
1418
1419         u8         rx_octets_low[0x20];
1420
1421         u8         reserved_at_40[0xc0];
1422
1423         u8         rx_frames_high[0x20];
1424
1425         u8         rx_frames_low[0x20];
1426
1427         u8         tx_octets_high[0x20];
1428
1429         u8         tx_octets_low[0x20];
1430
1431         u8         reserved_at_180[0xc0];
1432
1433         u8         tx_frames_high[0x20];
1434
1435         u8         tx_frames_low[0x20];
1436
1437         u8         rx_pause_high[0x20];
1438
1439         u8         rx_pause_low[0x20];
1440
1441         u8         rx_pause_duration_high[0x20];
1442
1443         u8         rx_pause_duration_low[0x20];
1444
1445         u8         tx_pause_high[0x20];
1446
1447         u8         tx_pause_low[0x20];
1448
1449         u8         tx_pause_duration_high[0x20];
1450
1451         u8         tx_pause_duration_low[0x20];
1452
1453         u8         rx_pause_transition_high[0x20];
1454
1455         u8         rx_pause_transition_low[0x20];
1456
1457         u8         reserved_at_3c0[0x400];
1458 };
1459
1460 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1461         u8         port_transmit_wait_high[0x20];
1462
1463         u8         port_transmit_wait_low[0x20];
1464
1465         u8         reserved_at_40[0x780];
1466 };
1467
1468 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1469         u8         dot3stats_alignment_errors_high[0x20];
1470
1471         u8         dot3stats_alignment_errors_low[0x20];
1472
1473         u8         dot3stats_fcs_errors_high[0x20];
1474
1475         u8         dot3stats_fcs_errors_low[0x20];
1476
1477         u8         dot3stats_single_collision_frames_high[0x20];
1478
1479         u8         dot3stats_single_collision_frames_low[0x20];
1480
1481         u8         dot3stats_multiple_collision_frames_high[0x20];
1482
1483         u8         dot3stats_multiple_collision_frames_low[0x20];
1484
1485         u8         dot3stats_sqe_test_errors_high[0x20];
1486
1487         u8         dot3stats_sqe_test_errors_low[0x20];
1488
1489         u8         dot3stats_deferred_transmissions_high[0x20];
1490
1491         u8         dot3stats_deferred_transmissions_low[0x20];
1492
1493         u8         dot3stats_late_collisions_high[0x20];
1494
1495         u8         dot3stats_late_collisions_low[0x20];
1496
1497         u8         dot3stats_excessive_collisions_high[0x20];
1498
1499         u8         dot3stats_excessive_collisions_low[0x20];
1500
1501         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1502
1503         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1504
1505         u8         dot3stats_carrier_sense_errors_high[0x20];
1506
1507         u8         dot3stats_carrier_sense_errors_low[0x20];
1508
1509         u8         dot3stats_frame_too_longs_high[0x20];
1510
1511         u8         dot3stats_frame_too_longs_low[0x20];
1512
1513         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1514
1515         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1516
1517         u8         dot3stats_symbol_errors_high[0x20];
1518
1519         u8         dot3stats_symbol_errors_low[0x20];
1520
1521         u8         dot3control_in_unknown_opcodes_high[0x20];
1522
1523         u8         dot3control_in_unknown_opcodes_low[0x20];
1524
1525         u8         dot3in_pause_frames_high[0x20];
1526
1527         u8         dot3in_pause_frames_low[0x20];
1528
1529         u8         dot3out_pause_frames_high[0x20];
1530
1531         u8         dot3out_pause_frames_low[0x20];
1532
1533         u8         reserved_at_400[0x3c0];
1534 };
1535
1536 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1537         u8         ether_stats_drop_events_high[0x20];
1538
1539         u8         ether_stats_drop_events_low[0x20];
1540
1541         u8         ether_stats_octets_high[0x20];
1542
1543         u8         ether_stats_octets_low[0x20];
1544
1545         u8         ether_stats_pkts_high[0x20];
1546
1547         u8         ether_stats_pkts_low[0x20];
1548
1549         u8         ether_stats_broadcast_pkts_high[0x20];
1550
1551         u8         ether_stats_broadcast_pkts_low[0x20];
1552
1553         u8         ether_stats_multicast_pkts_high[0x20];
1554
1555         u8         ether_stats_multicast_pkts_low[0x20];
1556
1557         u8         ether_stats_crc_align_errors_high[0x20];
1558
1559         u8         ether_stats_crc_align_errors_low[0x20];
1560
1561         u8         ether_stats_undersize_pkts_high[0x20];
1562
1563         u8         ether_stats_undersize_pkts_low[0x20];
1564
1565         u8         ether_stats_oversize_pkts_high[0x20];
1566
1567         u8         ether_stats_oversize_pkts_low[0x20];
1568
1569         u8         ether_stats_fragments_high[0x20];
1570
1571         u8         ether_stats_fragments_low[0x20];
1572
1573         u8         ether_stats_jabbers_high[0x20];
1574
1575         u8         ether_stats_jabbers_low[0x20];
1576
1577         u8         ether_stats_collisions_high[0x20];
1578
1579         u8         ether_stats_collisions_low[0x20];
1580
1581         u8         ether_stats_pkts64octets_high[0x20];
1582
1583         u8         ether_stats_pkts64octets_low[0x20];
1584
1585         u8         ether_stats_pkts65to127octets_high[0x20];
1586
1587         u8         ether_stats_pkts65to127octets_low[0x20];
1588
1589         u8         ether_stats_pkts128to255octets_high[0x20];
1590
1591         u8         ether_stats_pkts128to255octets_low[0x20];
1592
1593         u8         ether_stats_pkts256to511octets_high[0x20];
1594
1595         u8         ether_stats_pkts256to511octets_low[0x20];
1596
1597         u8         ether_stats_pkts512to1023octets_high[0x20];
1598
1599         u8         ether_stats_pkts512to1023octets_low[0x20];
1600
1601         u8         ether_stats_pkts1024to1518octets_high[0x20];
1602
1603         u8         ether_stats_pkts1024to1518octets_low[0x20];
1604
1605         u8         ether_stats_pkts1519to2047octets_high[0x20];
1606
1607         u8         ether_stats_pkts1519to2047octets_low[0x20];
1608
1609         u8         ether_stats_pkts2048to4095octets_high[0x20];
1610
1611         u8         ether_stats_pkts2048to4095octets_low[0x20];
1612
1613         u8         ether_stats_pkts4096to8191octets_high[0x20];
1614
1615         u8         ether_stats_pkts4096to8191octets_low[0x20];
1616
1617         u8         ether_stats_pkts8192to10239octets_high[0x20];
1618
1619         u8         ether_stats_pkts8192to10239octets_low[0x20];
1620
1621         u8         reserved_at_540[0x280];
1622 };
1623
1624 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1625         u8         if_in_octets_high[0x20];
1626
1627         u8         if_in_octets_low[0x20];
1628
1629         u8         if_in_ucast_pkts_high[0x20];
1630
1631         u8         if_in_ucast_pkts_low[0x20];
1632
1633         u8         if_in_discards_high[0x20];
1634
1635         u8         if_in_discards_low[0x20];
1636
1637         u8         if_in_errors_high[0x20];
1638
1639         u8         if_in_errors_low[0x20];
1640
1641         u8         if_in_unknown_protos_high[0x20];
1642
1643         u8         if_in_unknown_protos_low[0x20];
1644
1645         u8         if_out_octets_high[0x20];
1646
1647         u8         if_out_octets_low[0x20];
1648
1649         u8         if_out_ucast_pkts_high[0x20];
1650
1651         u8         if_out_ucast_pkts_low[0x20];
1652
1653         u8         if_out_discards_high[0x20];
1654
1655         u8         if_out_discards_low[0x20];
1656
1657         u8         if_out_errors_high[0x20];
1658
1659         u8         if_out_errors_low[0x20];
1660
1661         u8         if_in_multicast_pkts_high[0x20];
1662
1663         u8         if_in_multicast_pkts_low[0x20];
1664
1665         u8         if_in_broadcast_pkts_high[0x20];
1666
1667         u8         if_in_broadcast_pkts_low[0x20];
1668
1669         u8         if_out_multicast_pkts_high[0x20];
1670
1671         u8         if_out_multicast_pkts_low[0x20];
1672
1673         u8         if_out_broadcast_pkts_high[0x20];
1674
1675         u8         if_out_broadcast_pkts_low[0x20];
1676
1677         u8         reserved_at_340[0x480];
1678 };
1679
1680 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1681         u8         a_frames_transmitted_ok_high[0x20];
1682
1683         u8         a_frames_transmitted_ok_low[0x20];
1684
1685         u8         a_frames_received_ok_high[0x20];
1686
1687         u8         a_frames_received_ok_low[0x20];
1688
1689         u8         a_frame_check_sequence_errors_high[0x20];
1690
1691         u8         a_frame_check_sequence_errors_low[0x20];
1692
1693         u8         a_alignment_errors_high[0x20];
1694
1695         u8         a_alignment_errors_low[0x20];
1696
1697         u8         a_octets_transmitted_ok_high[0x20];
1698
1699         u8         a_octets_transmitted_ok_low[0x20];
1700
1701         u8         a_octets_received_ok_high[0x20];
1702
1703         u8         a_octets_received_ok_low[0x20];
1704
1705         u8         a_multicast_frames_xmitted_ok_high[0x20];
1706
1707         u8         a_multicast_frames_xmitted_ok_low[0x20];
1708
1709         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1710
1711         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1712
1713         u8         a_multicast_frames_received_ok_high[0x20];
1714
1715         u8         a_multicast_frames_received_ok_low[0x20];
1716
1717         u8         a_broadcast_frames_received_ok_high[0x20];
1718
1719         u8         a_broadcast_frames_received_ok_low[0x20];
1720
1721         u8         a_in_range_length_errors_high[0x20];
1722
1723         u8         a_in_range_length_errors_low[0x20];
1724
1725         u8         a_out_of_range_length_field_high[0x20];
1726
1727         u8         a_out_of_range_length_field_low[0x20];
1728
1729         u8         a_frame_too_long_errors_high[0x20];
1730
1731         u8         a_frame_too_long_errors_low[0x20];
1732
1733         u8         a_symbol_error_during_carrier_high[0x20];
1734
1735         u8         a_symbol_error_during_carrier_low[0x20];
1736
1737         u8         a_mac_control_frames_transmitted_high[0x20];
1738
1739         u8         a_mac_control_frames_transmitted_low[0x20];
1740
1741         u8         a_mac_control_frames_received_high[0x20];
1742
1743         u8         a_mac_control_frames_received_low[0x20];
1744
1745         u8         a_unsupported_opcodes_received_high[0x20];
1746
1747         u8         a_unsupported_opcodes_received_low[0x20];
1748
1749         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1750
1751         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1752
1753         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1754
1755         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1756
1757         u8         reserved_at_4c0[0x300];
1758 };
1759
1760 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1761         u8         life_time_counter_high[0x20];
1762
1763         u8         life_time_counter_low[0x20];
1764
1765         u8         rx_errors[0x20];
1766
1767         u8         tx_errors[0x20];
1768
1769         u8         l0_to_recovery_eieos[0x20];
1770
1771         u8         l0_to_recovery_ts[0x20];
1772
1773         u8         l0_to_recovery_framing[0x20];
1774
1775         u8         l0_to_recovery_retrain[0x20];
1776
1777         u8         crc_error_dllp[0x20];
1778
1779         u8         crc_error_tlp[0x20];
1780
1781         u8         reserved_at_140[0x680];
1782 };
1783
1784 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
1785         u8         life_time_counter_high[0x20];
1786
1787         u8         life_time_counter_low[0x20];
1788
1789         u8         time_to_boot_image_start[0x20];
1790
1791         u8         time_to_link_image[0x20];
1792
1793         u8         calibration_time[0x20];
1794
1795         u8         time_to_first_perst[0x20];
1796
1797         u8         time_to_detect_state[0x20];
1798
1799         u8         time_to_l0[0x20];
1800
1801         u8         time_to_crs_en[0x20];
1802
1803         u8         time_to_plastic_image_start[0x20];
1804
1805         u8         time_to_iron_image_start[0x20];
1806
1807         u8         perst_handler[0x20];
1808
1809         u8         times_in_l1[0x20];
1810
1811         u8         times_in_l23[0x20];
1812
1813         u8         dl_down[0x20];
1814
1815         u8         config_cycle1usec[0x20];
1816
1817         u8         config_cycle2to7usec[0x20];
1818
1819         u8         config_cycle_8to15usec[0x20];
1820
1821         u8         config_cycle_16_to_63usec[0x20];
1822
1823         u8         config_cycle_64usec[0x20];
1824
1825         u8         correctable_err_msg_sent[0x20];
1826
1827         u8         non_fatal_err_msg_sent[0x20];
1828
1829         u8         fatal_err_msg_sent[0x20];
1830
1831         u8         reserved_at_2e0[0x4e0];
1832 };
1833
1834 struct mlx5_ifc_cmd_inter_comp_event_bits {
1835         u8         command_completion_vector[0x20];
1836
1837         u8         reserved_at_20[0xc0];
1838 };
1839
1840 struct mlx5_ifc_stall_vl_event_bits {
1841         u8         reserved_at_0[0x18];
1842         u8         port_num[0x1];
1843         u8         reserved_at_19[0x3];
1844         u8         vl[0x4];
1845
1846         u8         reserved_at_20[0xa0];
1847 };
1848
1849 struct mlx5_ifc_db_bf_congestion_event_bits {
1850         u8         event_subtype[0x8];
1851         u8         reserved_at_8[0x8];
1852         u8         congestion_level[0x8];
1853         u8         reserved_at_18[0x8];
1854
1855         u8         reserved_at_20[0xa0];
1856 };
1857
1858 struct mlx5_ifc_gpio_event_bits {
1859         u8         reserved_at_0[0x60];
1860
1861         u8         gpio_event_hi[0x20];
1862
1863         u8         gpio_event_lo[0x20];
1864
1865         u8         reserved_at_a0[0x40];
1866 };
1867
1868 struct mlx5_ifc_port_state_change_event_bits {
1869         u8         reserved_at_0[0x40];
1870
1871         u8         port_num[0x4];
1872         u8         reserved_at_44[0x1c];
1873
1874         u8         reserved_at_60[0x80];
1875 };
1876
1877 struct mlx5_ifc_dropped_packet_logged_bits {
1878         u8         reserved_at_0[0xe0];
1879 };
1880
1881 enum {
1882         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1883         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1884 };
1885
1886 struct mlx5_ifc_cq_error_bits {
1887         u8         reserved_at_0[0x8];
1888         u8         cqn[0x18];
1889
1890         u8         reserved_at_20[0x20];
1891
1892         u8         reserved_at_40[0x18];
1893         u8         syndrome[0x8];
1894
1895         u8         reserved_at_60[0x80];
1896 };
1897
1898 struct mlx5_ifc_rdma_page_fault_event_bits {
1899         u8         bytes_committed[0x20];
1900
1901         u8         r_key[0x20];
1902
1903         u8         reserved_at_40[0x10];
1904         u8         packet_len[0x10];
1905
1906         u8         rdma_op_len[0x20];
1907
1908         u8         rdma_va[0x40];
1909
1910         u8         reserved_at_c0[0x5];
1911         u8         rdma[0x1];
1912         u8         write[0x1];
1913         u8         requestor[0x1];
1914         u8         qp_number[0x18];
1915 };
1916
1917 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1918         u8         bytes_committed[0x20];
1919
1920         u8         reserved_at_20[0x10];
1921         u8         wqe_index[0x10];
1922
1923         u8         reserved_at_40[0x10];
1924         u8         len[0x10];
1925
1926         u8         reserved_at_60[0x60];
1927
1928         u8         reserved_at_c0[0x5];
1929         u8         rdma[0x1];
1930         u8         write_read[0x1];
1931         u8         requestor[0x1];
1932         u8         qpn[0x18];
1933 };
1934
1935 struct mlx5_ifc_qp_events_bits {
1936         u8         reserved_at_0[0xa0];
1937
1938         u8         type[0x8];
1939         u8         reserved_at_a8[0x18];
1940
1941         u8         reserved_at_c0[0x8];
1942         u8         qpn_rqn_sqn[0x18];
1943 };
1944
1945 struct mlx5_ifc_dct_events_bits {
1946         u8         reserved_at_0[0xc0];
1947
1948         u8         reserved_at_c0[0x8];
1949         u8         dct_number[0x18];
1950 };
1951
1952 struct mlx5_ifc_comp_event_bits {
1953         u8         reserved_at_0[0xc0];
1954
1955         u8         reserved_at_c0[0x8];
1956         u8         cq_number[0x18];
1957 };
1958
1959 enum {
1960         MLX5_QPC_STATE_RST        = 0x0,
1961         MLX5_QPC_STATE_INIT       = 0x1,
1962         MLX5_QPC_STATE_RTR        = 0x2,
1963         MLX5_QPC_STATE_RTS        = 0x3,
1964         MLX5_QPC_STATE_SQER       = 0x4,
1965         MLX5_QPC_STATE_ERR        = 0x6,
1966         MLX5_QPC_STATE_SQD        = 0x7,
1967         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1968 };
1969
1970 enum {
1971         MLX5_QPC_ST_RC            = 0x0,
1972         MLX5_QPC_ST_UC            = 0x1,
1973         MLX5_QPC_ST_UD            = 0x2,
1974         MLX5_QPC_ST_XRC           = 0x3,
1975         MLX5_QPC_ST_DCI           = 0x5,
1976         MLX5_QPC_ST_QP0           = 0x7,
1977         MLX5_QPC_ST_QP1           = 0x8,
1978         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1979         MLX5_QPC_ST_REG_UMR       = 0xc,
1980 };
1981
1982 enum {
1983         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1984         MLX5_QPC_PM_STATE_REARM     = 0x1,
1985         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1986         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1987 };
1988
1989 enum {
1990         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1991         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1992 };
1993
1994 enum {
1995         MLX5_QPC_MTU_256_BYTES        = 0x1,
1996         MLX5_QPC_MTU_512_BYTES        = 0x2,
1997         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1998         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1999         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2000         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2001 };
2002
2003 enum {
2004         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2005         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2006         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2007         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2008         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2009         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2010         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2011         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2012 };
2013
2014 enum {
2015         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2016         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2017         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2018 };
2019
2020 enum {
2021         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2022         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2023         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2024 };
2025
2026 struct mlx5_ifc_qpc_bits {
2027         u8         state[0x4];
2028         u8         lag_tx_port_affinity[0x4];
2029         u8         st[0x8];
2030         u8         reserved_at_10[0x3];
2031         u8         pm_state[0x2];
2032         u8         reserved_at_15[0x7];
2033         u8         end_padding_mode[0x2];
2034         u8         reserved_at_1e[0x2];
2035
2036         u8         wq_signature[0x1];
2037         u8         block_lb_mc[0x1];
2038         u8         atomic_like_write_en[0x1];
2039         u8         latency_sensitive[0x1];
2040         u8         reserved_at_24[0x1];
2041         u8         drain_sigerr[0x1];
2042         u8         reserved_at_26[0x2];
2043         u8         pd[0x18];
2044
2045         u8         mtu[0x3];
2046         u8         log_msg_max[0x5];
2047         u8         reserved_at_48[0x1];
2048         u8         log_rq_size[0x4];
2049         u8         log_rq_stride[0x3];
2050         u8         no_sq[0x1];
2051         u8         log_sq_size[0x4];
2052         u8         reserved_at_55[0x6];
2053         u8         rlky[0x1];
2054         u8         ulp_stateless_offload_mode[0x4];
2055
2056         u8         counter_set_id[0x8];
2057         u8         uar_page[0x18];
2058
2059         u8         reserved_at_80[0x8];
2060         u8         user_index[0x18];
2061
2062         u8         reserved_at_a0[0x3];
2063         u8         log_page_size[0x5];
2064         u8         remote_qpn[0x18];
2065
2066         struct mlx5_ifc_ads_bits primary_address_path;
2067
2068         struct mlx5_ifc_ads_bits secondary_address_path;
2069
2070         u8         log_ack_req_freq[0x4];
2071         u8         reserved_at_384[0x4];
2072         u8         log_sra_max[0x3];
2073         u8         reserved_at_38b[0x2];
2074         u8         retry_count[0x3];
2075         u8         rnr_retry[0x3];
2076         u8         reserved_at_393[0x1];
2077         u8         fre[0x1];
2078         u8         cur_rnr_retry[0x3];
2079         u8         cur_retry_count[0x3];
2080         u8         reserved_at_39b[0x5];
2081
2082         u8         reserved_at_3a0[0x20];
2083
2084         u8         reserved_at_3c0[0x8];
2085         u8         next_send_psn[0x18];
2086
2087         u8         reserved_at_3e0[0x8];
2088         u8         cqn_snd[0x18];
2089
2090         u8         reserved_at_400[0x8];
2091         u8         deth_sqpn[0x18];
2092
2093         u8         reserved_at_420[0x20];
2094
2095         u8         reserved_at_440[0x8];
2096         u8         last_acked_psn[0x18];
2097
2098         u8         reserved_at_460[0x8];
2099         u8         ssn[0x18];
2100
2101         u8         reserved_at_480[0x8];
2102         u8         log_rra_max[0x3];
2103         u8         reserved_at_48b[0x1];
2104         u8         atomic_mode[0x4];
2105         u8         rre[0x1];
2106         u8         rwe[0x1];
2107         u8         rae[0x1];
2108         u8         reserved_at_493[0x1];
2109         u8         page_offset[0x6];
2110         u8         reserved_at_49a[0x3];
2111         u8         cd_slave_receive[0x1];
2112         u8         cd_slave_send[0x1];
2113         u8         cd_master[0x1];
2114
2115         u8         reserved_at_4a0[0x3];
2116         u8         min_rnr_nak[0x5];
2117         u8         next_rcv_psn[0x18];
2118
2119         u8         reserved_at_4c0[0x8];
2120         u8         xrcd[0x18];
2121
2122         u8         reserved_at_4e0[0x8];
2123         u8         cqn_rcv[0x18];
2124
2125         u8         dbr_addr[0x40];
2126
2127         u8         q_key[0x20];
2128
2129         u8         reserved_at_560[0x5];
2130         u8         rq_type[0x3];
2131         u8         srqn_rmpn_xrqn[0x18];
2132
2133         u8         reserved_at_580[0x8];
2134         u8         rmsn[0x18];
2135
2136         u8         hw_sq_wqebb_counter[0x10];
2137         u8         sw_sq_wqebb_counter[0x10];
2138
2139         u8         hw_rq_counter[0x20];
2140
2141         u8         sw_rq_counter[0x20];
2142
2143         u8         reserved_at_600[0x20];
2144
2145         u8         reserved_at_620[0xf];
2146         u8         cgs[0x1];
2147         u8         cs_req[0x8];
2148         u8         cs_res[0x8];
2149
2150         u8         dc_access_key[0x40];
2151
2152         u8         reserved_at_680[0xc0];
2153 };
2154
2155 struct mlx5_ifc_roce_addr_layout_bits {
2156         u8         source_l3_address[16][0x8];
2157
2158         u8         reserved_at_80[0x3];
2159         u8         vlan_valid[0x1];
2160         u8         vlan_id[0xc];
2161         u8         source_mac_47_32[0x10];
2162
2163         u8         source_mac_31_0[0x20];
2164
2165         u8         reserved_at_c0[0x14];
2166         u8         roce_l3_type[0x4];
2167         u8         roce_version[0x8];
2168
2169         u8         reserved_at_e0[0x20];
2170 };
2171
2172 union mlx5_ifc_hca_cap_union_bits {
2173         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2174         struct mlx5_ifc_odp_cap_bits odp_cap;
2175         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2176         struct mlx5_ifc_roce_cap_bits roce_cap;
2177         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2178         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2179         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2180         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2181         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2182         struct mlx5_ifc_qos_cap_bits qos_cap;
2183         u8         reserved_at_0[0x8000];
2184 };
2185
2186 enum {
2187         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2188         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2189         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2190         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2191         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2192         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2193 };
2194
2195 struct mlx5_ifc_flow_context_bits {
2196         u8         reserved_at_0[0x20];
2197
2198         u8         group_id[0x20];
2199
2200         u8         reserved_at_40[0x8];
2201         u8         flow_tag[0x18];
2202
2203         u8         reserved_at_60[0x10];
2204         u8         action[0x10];
2205
2206         u8         reserved_at_80[0x8];
2207         u8         destination_list_size[0x18];
2208
2209         u8         reserved_at_a0[0x8];
2210         u8         flow_counter_list_size[0x18];
2211
2212         u8         encap_id[0x20];
2213
2214         u8         reserved_at_e0[0x120];
2215
2216         struct mlx5_ifc_fte_match_param_bits match_value;
2217
2218         u8         reserved_at_1200[0x600];
2219
2220         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2221 };
2222
2223 enum {
2224         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2225         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2226 };
2227
2228 struct mlx5_ifc_xrc_srqc_bits {
2229         u8         state[0x4];
2230         u8         log_xrc_srq_size[0x4];
2231         u8         reserved_at_8[0x18];
2232
2233         u8         wq_signature[0x1];
2234         u8         cont_srq[0x1];
2235         u8         reserved_at_22[0x1];
2236         u8         rlky[0x1];
2237         u8         basic_cyclic_rcv_wqe[0x1];
2238         u8         log_rq_stride[0x3];
2239         u8         xrcd[0x18];
2240
2241         u8         page_offset[0x6];
2242         u8         reserved_at_46[0x2];
2243         u8         cqn[0x18];
2244
2245         u8         reserved_at_60[0x20];
2246
2247         u8         user_index_equal_xrc_srqn[0x1];
2248         u8         reserved_at_81[0x1];
2249         u8         log_page_size[0x6];
2250         u8         user_index[0x18];
2251
2252         u8         reserved_at_a0[0x20];
2253
2254         u8         reserved_at_c0[0x8];
2255         u8         pd[0x18];
2256
2257         u8         lwm[0x10];
2258         u8         wqe_cnt[0x10];
2259
2260         u8         reserved_at_100[0x40];
2261
2262         u8         db_record_addr_h[0x20];
2263
2264         u8         db_record_addr_l[0x1e];
2265         u8         reserved_at_17e[0x2];
2266
2267         u8         reserved_at_180[0x80];
2268 };
2269
2270 struct mlx5_ifc_traffic_counter_bits {
2271         u8         packets[0x40];
2272
2273         u8         octets[0x40];
2274 };
2275
2276 struct mlx5_ifc_tisc_bits {
2277         u8         strict_lag_tx_port_affinity[0x1];
2278         u8         reserved_at_1[0x3];
2279         u8         lag_tx_port_affinity[0x04];
2280
2281         u8         reserved_at_8[0x4];
2282         u8         prio[0x4];
2283         u8         reserved_at_10[0x10];
2284
2285         u8         reserved_at_20[0x100];
2286
2287         u8         reserved_at_120[0x8];
2288         u8         transport_domain[0x18];
2289
2290         u8         reserved_at_140[0x3c0];
2291 };
2292
2293 enum {
2294         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2295         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2296 };
2297
2298 enum {
2299         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2300         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2301 };
2302
2303 enum {
2304         MLX5_RX_HASH_FN_NONE           = 0x0,
2305         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2306         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2307 };
2308
2309 enum {
2310         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2311         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2312 };
2313
2314 struct mlx5_ifc_tirc_bits {
2315         u8         reserved_at_0[0x20];
2316
2317         u8         disp_type[0x4];
2318         u8         reserved_at_24[0x1c];
2319
2320         u8         reserved_at_40[0x40];
2321
2322         u8         reserved_at_80[0x4];
2323         u8         lro_timeout_period_usecs[0x10];
2324         u8         lro_enable_mask[0x4];
2325         u8         lro_max_ip_payload_size[0x8];
2326
2327         u8         reserved_at_a0[0x40];
2328
2329         u8         reserved_at_e0[0x8];
2330         u8         inline_rqn[0x18];
2331
2332         u8         rx_hash_symmetric[0x1];
2333         u8         reserved_at_101[0x1];
2334         u8         tunneled_offload_en[0x1];
2335         u8         reserved_at_103[0x5];
2336         u8         indirect_table[0x18];
2337
2338         u8         rx_hash_fn[0x4];
2339         u8         reserved_at_124[0x2];
2340         u8         self_lb_block[0x2];
2341         u8         transport_domain[0x18];
2342
2343         u8         rx_hash_toeplitz_key[10][0x20];
2344
2345         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2346
2347         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2348
2349         u8         reserved_at_2c0[0x4c0];
2350 };
2351
2352 enum {
2353         MLX5_SRQC_STATE_GOOD   = 0x0,
2354         MLX5_SRQC_STATE_ERROR  = 0x1,
2355 };
2356
2357 struct mlx5_ifc_srqc_bits {
2358         u8         state[0x4];
2359         u8         log_srq_size[0x4];
2360         u8         reserved_at_8[0x18];
2361
2362         u8         wq_signature[0x1];
2363         u8         cont_srq[0x1];
2364         u8         reserved_at_22[0x1];
2365         u8         rlky[0x1];
2366         u8         reserved_at_24[0x1];
2367         u8         log_rq_stride[0x3];
2368         u8         xrcd[0x18];
2369
2370         u8         page_offset[0x6];
2371         u8         reserved_at_46[0x2];
2372         u8         cqn[0x18];
2373
2374         u8         reserved_at_60[0x20];
2375
2376         u8         reserved_at_80[0x2];
2377         u8         log_page_size[0x6];
2378         u8         reserved_at_88[0x18];
2379
2380         u8         reserved_at_a0[0x20];
2381
2382         u8         reserved_at_c0[0x8];
2383         u8         pd[0x18];
2384
2385         u8         lwm[0x10];
2386         u8         wqe_cnt[0x10];
2387
2388         u8         reserved_at_100[0x40];
2389
2390         u8         dbr_addr[0x40];
2391
2392         u8         reserved_at_180[0x80];
2393 };
2394
2395 enum {
2396         MLX5_SQC_STATE_RST  = 0x0,
2397         MLX5_SQC_STATE_RDY  = 0x1,
2398         MLX5_SQC_STATE_ERR  = 0x3,
2399 };
2400
2401 struct mlx5_ifc_sqc_bits {
2402         u8         rlky[0x1];
2403         u8         cd_master[0x1];
2404         u8         fre[0x1];
2405         u8         flush_in_error_en[0x1];
2406         u8         reserved_at_4[0x1];
2407         u8         min_wqe_inline_mode[0x3];
2408         u8         state[0x4];
2409         u8         reg_umr[0x1];
2410         u8         reserved_at_d[0x13];
2411
2412         u8         reserved_at_20[0x8];
2413         u8         user_index[0x18];
2414
2415         u8         reserved_at_40[0x8];
2416         u8         cqn[0x18];
2417
2418         u8         reserved_at_60[0x90];
2419
2420         u8         packet_pacing_rate_limit_index[0x10];
2421         u8         tis_lst_sz[0x10];
2422         u8         reserved_at_110[0x10];
2423
2424         u8         reserved_at_120[0x40];
2425
2426         u8         reserved_at_160[0x8];
2427         u8         tis_num_0[0x18];
2428
2429         struct mlx5_ifc_wq_bits wq;
2430 };
2431
2432 enum {
2433         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2434         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2435         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2436         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2437 };
2438
2439 struct mlx5_ifc_scheduling_context_bits {
2440         u8         element_type[0x8];
2441         u8         reserved_at_8[0x18];
2442
2443         u8         element_attributes[0x20];
2444
2445         u8         parent_element_id[0x20];
2446
2447         u8         reserved_at_60[0x40];
2448
2449         u8         bw_share[0x20];
2450
2451         u8         max_average_bw[0x20];
2452
2453         u8         reserved_at_e0[0x120];
2454 };
2455
2456 struct mlx5_ifc_rqtc_bits {
2457         u8         reserved_at_0[0xa0];
2458
2459         u8         reserved_at_a0[0x10];
2460         u8         rqt_max_size[0x10];
2461
2462         u8         reserved_at_c0[0x10];
2463         u8         rqt_actual_size[0x10];
2464
2465         u8         reserved_at_e0[0x6a0];
2466
2467         struct mlx5_ifc_rq_num_bits rq_num[0];
2468 };
2469
2470 enum {
2471         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2472         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2473 };
2474
2475 enum {
2476         MLX5_RQC_STATE_RST  = 0x0,
2477         MLX5_RQC_STATE_RDY  = 0x1,
2478         MLX5_RQC_STATE_ERR  = 0x3,
2479 };
2480
2481 struct mlx5_ifc_rqc_bits {
2482         u8         rlky[0x1];
2483         u8         reserved_at_1[0x1];
2484         u8         scatter_fcs[0x1];
2485         u8         vsd[0x1];
2486         u8         mem_rq_type[0x4];
2487         u8         state[0x4];
2488         u8         reserved_at_c[0x1];
2489         u8         flush_in_error_en[0x1];
2490         u8         reserved_at_e[0x12];
2491
2492         u8         reserved_at_20[0x8];
2493         u8         user_index[0x18];
2494
2495         u8         reserved_at_40[0x8];
2496         u8         cqn[0x18];
2497
2498         u8         counter_set_id[0x8];
2499         u8         reserved_at_68[0x18];
2500
2501         u8         reserved_at_80[0x8];
2502         u8         rmpn[0x18];
2503
2504         u8         reserved_at_a0[0xe0];
2505
2506         struct mlx5_ifc_wq_bits wq;
2507 };
2508
2509 enum {
2510         MLX5_RMPC_STATE_RDY  = 0x1,
2511         MLX5_RMPC_STATE_ERR  = 0x3,
2512 };
2513
2514 struct mlx5_ifc_rmpc_bits {
2515         u8         reserved_at_0[0x8];
2516         u8         state[0x4];
2517         u8         reserved_at_c[0x14];
2518
2519         u8         basic_cyclic_rcv_wqe[0x1];
2520         u8         reserved_at_21[0x1f];
2521
2522         u8         reserved_at_40[0x140];
2523
2524         struct mlx5_ifc_wq_bits wq;
2525 };
2526
2527 struct mlx5_ifc_nic_vport_context_bits {
2528         u8         reserved_at_0[0x5];
2529         u8         min_wqe_inline_mode[0x3];
2530         u8         reserved_at_8[0x17];
2531         u8         roce_en[0x1];
2532
2533         u8         arm_change_event[0x1];
2534         u8         reserved_at_21[0x1a];
2535         u8         event_on_mtu[0x1];
2536         u8         event_on_promisc_change[0x1];
2537         u8         event_on_vlan_change[0x1];
2538         u8         event_on_mc_address_change[0x1];
2539         u8         event_on_uc_address_change[0x1];
2540
2541         u8         reserved_at_40[0xf0];
2542
2543         u8         mtu[0x10];
2544
2545         u8         system_image_guid[0x40];
2546         u8         port_guid[0x40];
2547         u8         node_guid[0x40];
2548
2549         u8         reserved_at_200[0x140];
2550         u8         qkey_violation_counter[0x10];
2551         u8         reserved_at_350[0x430];
2552
2553         u8         promisc_uc[0x1];
2554         u8         promisc_mc[0x1];
2555         u8         promisc_all[0x1];
2556         u8         reserved_at_783[0x2];
2557         u8         allowed_list_type[0x3];
2558         u8         reserved_at_788[0xc];
2559         u8         allowed_list_size[0xc];
2560
2561         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2562
2563         u8         reserved_at_7e0[0x20];
2564
2565         u8         current_uc_mac_address[0][0x40];
2566 };
2567
2568 enum {
2569         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2570         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2571         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2572 };
2573
2574 struct mlx5_ifc_mkc_bits {
2575         u8         reserved_at_0[0x1];
2576         u8         free[0x1];
2577         u8         reserved_at_2[0xd];
2578         u8         small_fence_on_rdma_read_response[0x1];
2579         u8         umr_en[0x1];
2580         u8         a[0x1];
2581         u8         rw[0x1];
2582         u8         rr[0x1];
2583         u8         lw[0x1];
2584         u8         lr[0x1];
2585         u8         access_mode[0x2];
2586         u8         reserved_at_18[0x8];
2587
2588         u8         qpn[0x18];
2589         u8         mkey_7_0[0x8];
2590
2591         u8         reserved_at_40[0x20];
2592
2593         u8         length64[0x1];
2594         u8         bsf_en[0x1];
2595         u8         sync_umr[0x1];
2596         u8         reserved_at_63[0x2];
2597         u8         expected_sigerr_count[0x1];
2598         u8         reserved_at_66[0x1];
2599         u8         en_rinval[0x1];
2600         u8         pd[0x18];
2601
2602         u8         start_addr[0x40];
2603
2604         u8         len[0x40];
2605
2606         u8         bsf_octword_size[0x20];
2607
2608         u8         reserved_at_120[0x80];
2609
2610         u8         translations_octword_size[0x20];
2611
2612         u8         reserved_at_1c0[0x1b];
2613         u8         log_page_size[0x5];
2614
2615         u8         reserved_at_1e0[0x20];
2616 };
2617
2618 struct mlx5_ifc_pkey_bits {
2619         u8         reserved_at_0[0x10];
2620         u8         pkey[0x10];
2621 };
2622
2623 struct mlx5_ifc_array128_auto_bits {
2624         u8         array128_auto[16][0x8];
2625 };
2626
2627 struct mlx5_ifc_hca_vport_context_bits {
2628         u8         field_select[0x20];
2629
2630         u8         reserved_at_20[0xe0];
2631
2632         u8         sm_virt_aware[0x1];
2633         u8         has_smi[0x1];
2634         u8         has_raw[0x1];
2635         u8         grh_required[0x1];
2636         u8         reserved_at_104[0xc];
2637         u8         port_physical_state[0x4];
2638         u8         vport_state_policy[0x4];
2639         u8         port_state[0x4];
2640         u8         vport_state[0x4];
2641
2642         u8         reserved_at_120[0x20];
2643
2644         u8         system_image_guid[0x40];
2645
2646         u8         port_guid[0x40];
2647
2648         u8         node_guid[0x40];
2649
2650         u8         cap_mask1[0x20];
2651
2652         u8         cap_mask1_field_select[0x20];
2653
2654         u8         cap_mask2[0x20];
2655
2656         u8         cap_mask2_field_select[0x20];
2657
2658         u8         reserved_at_280[0x80];
2659
2660         u8         lid[0x10];
2661         u8         reserved_at_310[0x4];
2662         u8         init_type_reply[0x4];
2663         u8         lmc[0x3];
2664         u8         subnet_timeout[0x5];
2665
2666         u8         sm_lid[0x10];
2667         u8         sm_sl[0x4];
2668         u8         reserved_at_334[0xc];
2669
2670         u8         qkey_violation_counter[0x10];
2671         u8         pkey_violation_counter[0x10];
2672
2673         u8         reserved_at_360[0xca0];
2674 };
2675
2676 struct mlx5_ifc_esw_vport_context_bits {
2677         u8         reserved_at_0[0x3];
2678         u8         vport_svlan_strip[0x1];
2679         u8         vport_cvlan_strip[0x1];
2680         u8         vport_svlan_insert[0x1];
2681         u8         vport_cvlan_insert[0x2];
2682         u8         reserved_at_8[0x18];
2683
2684         u8         reserved_at_20[0x20];
2685
2686         u8         svlan_cfi[0x1];
2687         u8         svlan_pcp[0x3];
2688         u8         svlan_id[0xc];
2689         u8         cvlan_cfi[0x1];
2690         u8         cvlan_pcp[0x3];
2691         u8         cvlan_id[0xc];
2692
2693         u8         reserved_at_60[0x7a0];
2694 };
2695
2696 enum {
2697         MLX5_EQC_STATUS_OK                = 0x0,
2698         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2699 };
2700
2701 enum {
2702         MLX5_EQC_ST_ARMED  = 0x9,
2703         MLX5_EQC_ST_FIRED  = 0xa,
2704 };
2705
2706 struct mlx5_ifc_eqc_bits {
2707         u8         status[0x4];
2708         u8         reserved_at_4[0x9];
2709         u8         ec[0x1];
2710         u8         oi[0x1];
2711         u8         reserved_at_f[0x5];
2712         u8         st[0x4];
2713         u8         reserved_at_18[0x8];
2714
2715         u8         reserved_at_20[0x20];
2716
2717         u8         reserved_at_40[0x14];
2718         u8         page_offset[0x6];
2719         u8         reserved_at_5a[0x6];
2720
2721         u8         reserved_at_60[0x3];
2722         u8         log_eq_size[0x5];
2723         u8         uar_page[0x18];
2724
2725         u8         reserved_at_80[0x20];
2726
2727         u8         reserved_at_a0[0x18];
2728         u8         intr[0x8];
2729
2730         u8         reserved_at_c0[0x3];
2731         u8         log_page_size[0x5];
2732         u8         reserved_at_c8[0x18];
2733
2734         u8         reserved_at_e0[0x60];
2735
2736         u8         reserved_at_140[0x8];
2737         u8         consumer_counter[0x18];
2738
2739         u8         reserved_at_160[0x8];
2740         u8         producer_counter[0x18];
2741
2742         u8         reserved_at_180[0x80];
2743 };
2744
2745 enum {
2746         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2747         MLX5_DCTC_STATE_DRAINING  = 0x1,
2748         MLX5_DCTC_STATE_DRAINED   = 0x2,
2749 };
2750
2751 enum {
2752         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2753         MLX5_DCTC_CS_RES_NA         = 0x1,
2754         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2755 };
2756
2757 enum {
2758         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2759         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2760         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2761         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2762         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2763 };
2764
2765 struct mlx5_ifc_dctc_bits {
2766         u8         reserved_at_0[0x4];
2767         u8         state[0x4];
2768         u8         reserved_at_8[0x18];
2769
2770         u8         reserved_at_20[0x8];
2771         u8         user_index[0x18];
2772
2773         u8         reserved_at_40[0x8];
2774         u8         cqn[0x18];
2775
2776         u8         counter_set_id[0x8];
2777         u8         atomic_mode[0x4];
2778         u8         rre[0x1];
2779         u8         rwe[0x1];
2780         u8         rae[0x1];
2781         u8         atomic_like_write_en[0x1];
2782         u8         latency_sensitive[0x1];
2783         u8         rlky[0x1];
2784         u8         free_ar[0x1];
2785         u8         reserved_at_73[0xd];
2786
2787         u8         reserved_at_80[0x8];
2788         u8         cs_res[0x8];
2789         u8         reserved_at_90[0x3];
2790         u8         min_rnr_nak[0x5];
2791         u8         reserved_at_98[0x8];
2792
2793         u8         reserved_at_a0[0x8];
2794         u8         srqn_xrqn[0x18];
2795
2796         u8         reserved_at_c0[0x8];
2797         u8         pd[0x18];
2798
2799         u8         tclass[0x8];
2800         u8         reserved_at_e8[0x4];
2801         u8         flow_label[0x14];
2802
2803         u8         dc_access_key[0x40];
2804
2805         u8         reserved_at_140[0x5];
2806         u8         mtu[0x3];
2807         u8         port[0x8];
2808         u8         pkey_index[0x10];
2809
2810         u8         reserved_at_160[0x8];
2811         u8         my_addr_index[0x8];
2812         u8         reserved_at_170[0x8];
2813         u8         hop_limit[0x8];
2814
2815         u8         dc_access_key_violation_count[0x20];
2816
2817         u8         reserved_at_1a0[0x14];
2818         u8         dei_cfi[0x1];
2819         u8         eth_prio[0x3];
2820         u8         ecn[0x2];
2821         u8         dscp[0x6];
2822
2823         u8         reserved_at_1c0[0x40];
2824 };
2825
2826 enum {
2827         MLX5_CQC_STATUS_OK             = 0x0,
2828         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2829         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2830 };
2831
2832 enum {
2833         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2834         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2835 };
2836
2837 enum {
2838         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2839         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2840         MLX5_CQC_ST_FIRED                                 = 0xa,
2841 };
2842
2843 enum {
2844         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2845         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2846         MLX5_CQ_PERIOD_NUM_MODES
2847 };
2848
2849 struct mlx5_ifc_cqc_bits {
2850         u8         status[0x4];
2851         u8         reserved_at_4[0x4];
2852         u8         cqe_sz[0x3];
2853         u8         cc[0x1];
2854         u8         reserved_at_c[0x1];
2855         u8         scqe_break_moderation_en[0x1];
2856         u8         oi[0x1];
2857         u8         cq_period_mode[0x2];
2858         u8         cqe_comp_en[0x1];
2859         u8         mini_cqe_res_format[0x2];
2860         u8         st[0x4];
2861         u8         reserved_at_18[0x8];
2862
2863         u8         reserved_at_20[0x20];
2864
2865         u8         reserved_at_40[0x14];
2866         u8         page_offset[0x6];
2867         u8         reserved_at_5a[0x6];
2868
2869         u8         reserved_at_60[0x3];
2870         u8         log_cq_size[0x5];
2871         u8         uar_page[0x18];
2872
2873         u8         reserved_at_80[0x4];
2874         u8         cq_period[0xc];
2875         u8         cq_max_count[0x10];
2876
2877         u8         reserved_at_a0[0x18];
2878         u8         c_eqn[0x8];
2879
2880         u8         reserved_at_c0[0x3];
2881         u8         log_page_size[0x5];
2882         u8         reserved_at_c8[0x18];
2883
2884         u8         reserved_at_e0[0x20];
2885
2886         u8         reserved_at_100[0x8];
2887         u8         last_notified_index[0x18];
2888
2889         u8         reserved_at_120[0x8];
2890         u8         last_solicit_index[0x18];
2891
2892         u8         reserved_at_140[0x8];
2893         u8         consumer_counter[0x18];
2894
2895         u8         reserved_at_160[0x8];
2896         u8         producer_counter[0x18];
2897
2898         u8         reserved_at_180[0x40];
2899
2900         u8         dbr_addr[0x40];
2901 };
2902
2903 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2904         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2905         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2906         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2907         u8         reserved_at_0[0x800];
2908 };
2909
2910 struct mlx5_ifc_query_adapter_param_block_bits {
2911         u8         reserved_at_0[0xc0];
2912
2913         u8         reserved_at_c0[0x8];
2914         u8         ieee_vendor_id[0x18];
2915
2916         u8         reserved_at_e0[0x10];
2917         u8         vsd_vendor_id[0x10];
2918
2919         u8         vsd[208][0x8];
2920
2921         u8         vsd_contd_psid[16][0x8];
2922 };
2923
2924 enum {
2925         MLX5_XRQC_STATE_GOOD   = 0x0,
2926         MLX5_XRQC_STATE_ERROR  = 0x1,
2927 };
2928
2929 enum {
2930         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2931         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2932 };
2933
2934 enum {
2935         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2936 };
2937
2938 struct mlx5_ifc_tag_matching_topology_context_bits {
2939         u8         log_matching_list_sz[0x4];
2940         u8         reserved_at_4[0xc];
2941         u8         append_next_index[0x10];
2942
2943         u8         sw_phase_cnt[0x10];
2944         u8         hw_phase_cnt[0x10];
2945
2946         u8         reserved_at_40[0x40];
2947 };
2948
2949 struct mlx5_ifc_xrqc_bits {
2950         u8         state[0x4];
2951         u8         rlkey[0x1];
2952         u8         reserved_at_5[0xf];
2953         u8         topology[0x4];
2954         u8         reserved_at_18[0x4];
2955         u8         offload[0x4];
2956
2957         u8         reserved_at_20[0x8];
2958         u8         user_index[0x18];
2959
2960         u8         reserved_at_40[0x8];
2961         u8         cqn[0x18];
2962
2963         u8         reserved_at_60[0xa0];
2964
2965         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2966
2967         u8         reserved_at_180[0x880];
2968
2969         struct mlx5_ifc_wq_bits wq;
2970 };
2971
2972 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2973         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2974         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2975         u8         reserved_at_0[0x20];
2976 };
2977
2978 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2979         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2980         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2981         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2982         u8         reserved_at_0[0x20];
2983 };
2984
2985 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2986         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2987         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2988         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2989         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2990         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2991         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2992         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2993         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2994         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2995         u8         reserved_at_0[0x7c0];
2996 };
2997
2998 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2999         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3000         struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
3001         u8         reserved_at_0[0x7c0];
3002 };
3003
3004 union mlx5_ifc_event_auto_bits {
3005         struct mlx5_ifc_comp_event_bits comp_event;
3006         struct mlx5_ifc_dct_events_bits dct_events;
3007         struct mlx5_ifc_qp_events_bits qp_events;
3008         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3009         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3010         struct mlx5_ifc_cq_error_bits cq_error;
3011         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3012         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3013         struct mlx5_ifc_gpio_event_bits gpio_event;
3014         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3015         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3016         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3017         u8         reserved_at_0[0xe0];
3018 };
3019
3020 struct mlx5_ifc_health_buffer_bits {
3021         u8         reserved_at_0[0x100];
3022
3023         u8         assert_existptr[0x20];
3024
3025         u8         assert_callra[0x20];
3026
3027         u8         reserved_at_140[0x40];
3028
3029         u8         fw_version[0x20];
3030
3031         u8         hw_id[0x20];
3032
3033         u8         reserved_at_1c0[0x20];
3034
3035         u8         irisc_index[0x8];
3036         u8         synd[0x8];
3037         u8         ext_synd[0x10];
3038 };
3039
3040 struct mlx5_ifc_register_loopback_control_bits {
3041         u8         no_lb[0x1];
3042         u8         reserved_at_1[0x7];
3043         u8         port[0x8];
3044         u8         reserved_at_10[0x10];
3045
3046         u8         reserved_at_20[0x60];
3047 };
3048
3049 struct mlx5_ifc_vport_tc_element_bits {
3050         u8         traffic_class[0x4];
3051         u8         reserved_at_4[0xc];
3052         u8         vport_number[0x10];
3053 };
3054
3055 struct mlx5_ifc_vport_element_bits {
3056         u8         reserved_at_0[0x10];
3057         u8         vport_number[0x10];
3058 };
3059
3060 enum {
3061         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3062         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3063         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3064 };
3065
3066 struct mlx5_ifc_tsar_element_bits {
3067         u8         reserved_at_0[0x8];
3068         u8         tsar_type[0x8];
3069         u8         reserved_at_10[0x10];
3070 };
3071
3072 struct mlx5_ifc_teardown_hca_out_bits {
3073         u8         status[0x8];
3074         u8         reserved_at_8[0x18];
3075
3076         u8         syndrome[0x20];
3077
3078         u8         reserved_at_40[0x40];
3079 };
3080
3081 enum {
3082         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3083         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3084 };
3085
3086 struct mlx5_ifc_teardown_hca_in_bits {
3087         u8         opcode[0x10];
3088         u8         reserved_at_10[0x10];
3089
3090         u8         reserved_at_20[0x10];
3091         u8         op_mod[0x10];
3092
3093         u8         reserved_at_40[0x10];
3094         u8         profile[0x10];
3095
3096         u8         reserved_at_60[0x20];
3097 };
3098
3099 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3100         u8         status[0x8];
3101         u8         reserved_at_8[0x18];
3102
3103         u8         syndrome[0x20];
3104
3105         u8         reserved_at_40[0x40];
3106 };
3107
3108 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3109         u8         opcode[0x10];
3110         u8         reserved_at_10[0x10];
3111
3112         u8         reserved_at_20[0x10];
3113         u8         op_mod[0x10];
3114
3115         u8         reserved_at_40[0x8];
3116         u8         qpn[0x18];
3117
3118         u8         reserved_at_60[0x20];
3119
3120         u8         opt_param_mask[0x20];
3121
3122         u8         reserved_at_a0[0x20];
3123
3124         struct mlx5_ifc_qpc_bits qpc;
3125
3126         u8         reserved_at_800[0x80];
3127 };
3128
3129 struct mlx5_ifc_sqd2rts_qp_out_bits {
3130         u8         status[0x8];
3131         u8         reserved_at_8[0x18];
3132
3133         u8         syndrome[0x20];
3134
3135         u8         reserved_at_40[0x40];
3136 };
3137
3138 struct mlx5_ifc_sqd2rts_qp_in_bits {
3139         u8         opcode[0x10];
3140         u8         reserved_at_10[0x10];
3141
3142         u8         reserved_at_20[0x10];
3143         u8         op_mod[0x10];
3144
3145         u8         reserved_at_40[0x8];
3146         u8         qpn[0x18];
3147
3148         u8         reserved_at_60[0x20];
3149
3150         u8         opt_param_mask[0x20];
3151
3152         u8         reserved_at_a0[0x20];
3153
3154         struct mlx5_ifc_qpc_bits qpc;
3155
3156         u8         reserved_at_800[0x80];
3157 };
3158
3159 struct mlx5_ifc_set_roce_address_out_bits {
3160         u8         status[0x8];
3161         u8         reserved_at_8[0x18];
3162
3163         u8         syndrome[0x20];
3164
3165         u8         reserved_at_40[0x40];
3166 };
3167
3168 struct mlx5_ifc_set_roce_address_in_bits {
3169         u8         opcode[0x10];
3170         u8         reserved_at_10[0x10];
3171
3172         u8         reserved_at_20[0x10];
3173         u8         op_mod[0x10];
3174
3175         u8         roce_address_index[0x10];
3176         u8         reserved_at_50[0x10];
3177
3178         u8         reserved_at_60[0x20];
3179
3180         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3181 };
3182
3183 struct mlx5_ifc_set_mad_demux_out_bits {
3184         u8         status[0x8];
3185         u8         reserved_at_8[0x18];
3186
3187         u8         syndrome[0x20];
3188
3189         u8         reserved_at_40[0x40];
3190 };
3191
3192 enum {
3193         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3194         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3195 };
3196
3197 struct mlx5_ifc_set_mad_demux_in_bits {
3198         u8         opcode[0x10];
3199         u8         reserved_at_10[0x10];
3200
3201         u8         reserved_at_20[0x10];
3202         u8         op_mod[0x10];
3203
3204         u8         reserved_at_40[0x20];
3205
3206         u8         reserved_at_60[0x6];
3207         u8         demux_mode[0x2];
3208         u8         reserved_at_68[0x18];
3209 };
3210
3211 struct mlx5_ifc_set_l2_table_entry_out_bits {
3212         u8         status[0x8];
3213         u8         reserved_at_8[0x18];
3214
3215         u8         syndrome[0x20];
3216
3217         u8         reserved_at_40[0x40];
3218 };
3219
3220 struct mlx5_ifc_set_l2_table_entry_in_bits {
3221         u8         opcode[0x10];
3222         u8         reserved_at_10[0x10];
3223
3224         u8         reserved_at_20[0x10];
3225         u8         op_mod[0x10];
3226
3227         u8         reserved_at_40[0x60];
3228
3229         u8         reserved_at_a0[0x8];
3230         u8         table_index[0x18];
3231
3232         u8         reserved_at_c0[0x20];
3233
3234         u8         reserved_at_e0[0x13];
3235         u8         vlan_valid[0x1];
3236         u8         vlan[0xc];
3237
3238         struct mlx5_ifc_mac_address_layout_bits mac_address;
3239
3240         u8         reserved_at_140[0xc0];
3241 };
3242
3243 struct mlx5_ifc_set_issi_out_bits {
3244         u8         status[0x8];
3245         u8         reserved_at_8[0x18];
3246
3247         u8         syndrome[0x20];
3248
3249         u8         reserved_at_40[0x40];
3250 };
3251
3252 struct mlx5_ifc_set_issi_in_bits {
3253         u8         opcode[0x10];
3254         u8         reserved_at_10[0x10];
3255
3256         u8         reserved_at_20[0x10];
3257         u8         op_mod[0x10];
3258
3259         u8         reserved_at_40[0x10];
3260         u8         current_issi[0x10];
3261
3262         u8         reserved_at_60[0x20];
3263 };
3264
3265 struct mlx5_ifc_set_hca_cap_out_bits {
3266         u8         status[0x8];
3267         u8         reserved_at_8[0x18];
3268
3269         u8         syndrome[0x20];
3270
3271         u8         reserved_at_40[0x40];
3272 };
3273
3274 struct mlx5_ifc_set_hca_cap_in_bits {
3275         u8         opcode[0x10];
3276         u8         reserved_at_10[0x10];
3277
3278         u8         reserved_at_20[0x10];
3279         u8         op_mod[0x10];
3280
3281         u8         reserved_at_40[0x40];
3282
3283         union mlx5_ifc_hca_cap_union_bits capability;
3284 };
3285
3286 enum {
3287         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3288         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3289         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3290         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3291 };
3292
3293 struct mlx5_ifc_set_fte_out_bits {
3294         u8         status[0x8];
3295         u8         reserved_at_8[0x18];
3296
3297         u8         syndrome[0x20];
3298
3299         u8         reserved_at_40[0x40];
3300 };
3301
3302 struct mlx5_ifc_set_fte_in_bits {
3303         u8         opcode[0x10];
3304         u8         reserved_at_10[0x10];
3305
3306         u8         reserved_at_20[0x10];
3307         u8         op_mod[0x10];
3308
3309         u8         other_vport[0x1];
3310         u8         reserved_at_41[0xf];
3311         u8         vport_number[0x10];
3312
3313         u8         reserved_at_60[0x20];
3314
3315         u8         table_type[0x8];
3316         u8         reserved_at_88[0x18];
3317
3318         u8         reserved_at_a0[0x8];
3319         u8         table_id[0x18];
3320
3321         u8         reserved_at_c0[0x18];
3322         u8         modify_enable_mask[0x8];
3323
3324         u8         reserved_at_e0[0x20];
3325
3326         u8         flow_index[0x20];
3327
3328         u8         reserved_at_120[0xe0];
3329
3330         struct mlx5_ifc_flow_context_bits flow_context;
3331 };
3332
3333 struct mlx5_ifc_rts2rts_qp_out_bits {
3334         u8         status[0x8];
3335         u8         reserved_at_8[0x18];
3336
3337         u8         syndrome[0x20];
3338
3339         u8         reserved_at_40[0x40];
3340 };
3341
3342 struct mlx5_ifc_rts2rts_qp_in_bits {
3343         u8         opcode[0x10];
3344         u8         reserved_at_10[0x10];
3345
3346         u8         reserved_at_20[0x10];
3347         u8         op_mod[0x10];
3348
3349         u8         reserved_at_40[0x8];
3350         u8         qpn[0x18];
3351
3352         u8         reserved_at_60[0x20];
3353
3354         u8         opt_param_mask[0x20];
3355
3356         u8         reserved_at_a0[0x20];
3357
3358         struct mlx5_ifc_qpc_bits qpc;
3359
3360         u8         reserved_at_800[0x80];
3361 };
3362
3363 struct mlx5_ifc_rtr2rts_qp_out_bits {
3364         u8         status[0x8];
3365         u8         reserved_at_8[0x18];
3366
3367         u8         syndrome[0x20];
3368
3369         u8         reserved_at_40[0x40];
3370 };
3371
3372 struct mlx5_ifc_rtr2rts_qp_in_bits {
3373         u8         opcode[0x10];
3374         u8         reserved_at_10[0x10];
3375
3376         u8         reserved_at_20[0x10];
3377         u8         op_mod[0x10];
3378
3379         u8         reserved_at_40[0x8];
3380         u8         qpn[0x18];
3381
3382         u8         reserved_at_60[0x20];
3383
3384         u8         opt_param_mask[0x20];
3385
3386         u8         reserved_at_a0[0x20];
3387
3388         struct mlx5_ifc_qpc_bits qpc;
3389
3390         u8         reserved_at_800[0x80];
3391 };
3392
3393 struct mlx5_ifc_rst2init_qp_out_bits {
3394         u8         status[0x8];
3395         u8         reserved_at_8[0x18];
3396
3397         u8         syndrome[0x20];
3398
3399         u8         reserved_at_40[0x40];
3400 };
3401
3402 struct mlx5_ifc_rst2init_qp_in_bits {
3403         u8         opcode[0x10];
3404         u8         reserved_at_10[0x10];
3405
3406         u8         reserved_at_20[0x10];
3407         u8         op_mod[0x10];
3408
3409         u8         reserved_at_40[0x8];
3410         u8         qpn[0x18];
3411
3412         u8         reserved_at_60[0x20];
3413
3414         u8         opt_param_mask[0x20];
3415
3416         u8         reserved_at_a0[0x20];
3417
3418         struct mlx5_ifc_qpc_bits qpc;
3419
3420         u8         reserved_at_800[0x80];
3421 };
3422
3423 struct mlx5_ifc_query_xrq_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_at_40[0x40];
3430
3431         struct mlx5_ifc_xrqc_bits xrq_context;
3432 };
3433
3434 struct mlx5_ifc_query_xrq_in_bits {
3435         u8         opcode[0x10];
3436         u8         reserved_at_10[0x10];
3437
3438         u8         reserved_at_20[0x10];
3439         u8         op_mod[0x10];
3440
3441         u8         reserved_at_40[0x8];
3442         u8         xrqn[0x18];
3443
3444         u8         reserved_at_60[0x20];
3445 };
3446
3447 struct mlx5_ifc_query_xrc_srq_out_bits {
3448         u8         status[0x8];
3449         u8         reserved_at_8[0x18];
3450
3451         u8         syndrome[0x20];
3452
3453         u8         reserved_at_40[0x40];
3454
3455         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3456
3457         u8         reserved_at_280[0x600];
3458
3459         u8         pas[0][0x40];
3460 };
3461
3462 struct mlx5_ifc_query_xrc_srq_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_at_40[0x8];
3470         u8         xrc_srqn[0x18];
3471
3472         u8         reserved_at_60[0x20];
3473 };
3474
3475 enum {
3476         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3477         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3478 };
3479
3480 struct mlx5_ifc_query_vport_state_out_bits {
3481         u8         status[0x8];
3482         u8         reserved_at_8[0x18];
3483
3484         u8         syndrome[0x20];
3485
3486         u8         reserved_at_40[0x20];
3487
3488         u8         reserved_at_60[0x18];
3489         u8         admin_state[0x4];
3490         u8         state[0x4];
3491 };
3492
3493 enum {
3494         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3495         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3496 };
3497
3498 struct mlx5_ifc_query_vport_state_in_bits {
3499         u8         opcode[0x10];
3500         u8         reserved_at_10[0x10];
3501
3502         u8         reserved_at_20[0x10];
3503         u8         op_mod[0x10];
3504
3505         u8         other_vport[0x1];
3506         u8         reserved_at_41[0xf];
3507         u8         vport_number[0x10];
3508
3509         u8         reserved_at_60[0x20];
3510 };
3511
3512 struct mlx5_ifc_query_vport_counter_out_bits {
3513         u8         status[0x8];
3514         u8         reserved_at_8[0x18];
3515
3516         u8         syndrome[0x20];
3517
3518         u8         reserved_at_40[0x40];
3519
3520         struct mlx5_ifc_traffic_counter_bits received_errors;
3521
3522         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3523
3524         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3525
3526         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3527
3528         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3529
3530         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3531
3532         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3533
3534         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3535
3536         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3537
3538         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3539
3540         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3541
3542         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3543
3544         u8         reserved_at_680[0xa00];
3545 };
3546
3547 enum {
3548         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3549 };
3550
3551 struct mlx5_ifc_query_vport_counter_in_bits {
3552         u8         opcode[0x10];
3553         u8         reserved_at_10[0x10];
3554
3555         u8         reserved_at_20[0x10];
3556         u8         op_mod[0x10];
3557
3558         u8         other_vport[0x1];
3559         u8         reserved_at_41[0xb];
3560         u8         port_num[0x4];
3561         u8         vport_number[0x10];
3562
3563         u8         reserved_at_60[0x60];
3564
3565         u8         clear[0x1];
3566         u8         reserved_at_c1[0x1f];
3567
3568         u8         reserved_at_e0[0x20];
3569 };
3570
3571 struct mlx5_ifc_query_tis_out_bits {
3572         u8         status[0x8];
3573         u8         reserved_at_8[0x18];
3574
3575         u8         syndrome[0x20];
3576
3577         u8         reserved_at_40[0x40];
3578
3579         struct mlx5_ifc_tisc_bits tis_context;
3580 };
3581
3582 struct mlx5_ifc_query_tis_in_bits {
3583         u8         opcode[0x10];
3584         u8         reserved_at_10[0x10];
3585
3586         u8         reserved_at_20[0x10];
3587         u8         op_mod[0x10];
3588
3589         u8         reserved_at_40[0x8];
3590         u8         tisn[0x18];
3591
3592         u8         reserved_at_60[0x20];
3593 };
3594
3595 struct mlx5_ifc_query_tir_out_bits {
3596         u8         status[0x8];
3597         u8         reserved_at_8[0x18];
3598
3599         u8         syndrome[0x20];
3600
3601         u8         reserved_at_40[0xc0];
3602
3603         struct mlx5_ifc_tirc_bits tir_context;
3604 };
3605
3606 struct mlx5_ifc_query_tir_in_bits {
3607         u8         opcode[0x10];
3608         u8         reserved_at_10[0x10];
3609
3610         u8         reserved_at_20[0x10];
3611         u8         op_mod[0x10];
3612
3613         u8         reserved_at_40[0x8];
3614         u8         tirn[0x18];
3615
3616         u8         reserved_at_60[0x20];
3617 };
3618
3619 struct mlx5_ifc_query_srq_out_bits {
3620         u8         status[0x8];
3621         u8         reserved_at_8[0x18];
3622
3623         u8         syndrome[0x20];
3624
3625         u8         reserved_at_40[0x40];
3626
3627         struct mlx5_ifc_srqc_bits srq_context_entry;
3628
3629         u8         reserved_at_280[0x600];
3630
3631         u8         pas[0][0x40];
3632 };
3633
3634 struct mlx5_ifc_query_srq_in_bits {
3635         u8         opcode[0x10];
3636         u8         reserved_at_10[0x10];
3637
3638         u8         reserved_at_20[0x10];
3639         u8         op_mod[0x10];
3640
3641         u8         reserved_at_40[0x8];
3642         u8         srqn[0x18];
3643
3644         u8         reserved_at_60[0x20];
3645 };
3646
3647 struct mlx5_ifc_query_sq_out_bits {
3648         u8         status[0x8];
3649         u8         reserved_at_8[0x18];
3650
3651         u8         syndrome[0x20];
3652
3653         u8         reserved_at_40[0xc0];
3654
3655         struct mlx5_ifc_sqc_bits sq_context;
3656 };
3657
3658 struct mlx5_ifc_query_sq_in_bits {
3659         u8         opcode[0x10];
3660         u8         reserved_at_10[0x10];
3661
3662         u8         reserved_at_20[0x10];
3663         u8         op_mod[0x10];
3664
3665         u8         reserved_at_40[0x8];
3666         u8         sqn[0x18];
3667
3668         u8         reserved_at_60[0x20];
3669 };
3670
3671 struct mlx5_ifc_query_special_contexts_out_bits {
3672         u8         status[0x8];
3673         u8         reserved_at_8[0x18];
3674
3675         u8         syndrome[0x20];
3676
3677         u8         dump_fill_mkey[0x20];
3678
3679         u8         resd_lkey[0x20];
3680 };
3681
3682 struct mlx5_ifc_query_special_contexts_in_bits {
3683         u8         opcode[0x10];
3684         u8         reserved_at_10[0x10];
3685
3686         u8         reserved_at_20[0x10];
3687         u8         op_mod[0x10];
3688
3689         u8         reserved_at_40[0x40];
3690 };
3691
3692 struct mlx5_ifc_query_scheduling_element_out_bits {
3693         u8         opcode[0x10];
3694         u8         reserved_at_10[0x10];
3695
3696         u8         reserved_at_20[0x10];
3697         u8         op_mod[0x10];
3698
3699         u8         reserved_at_40[0xc0];
3700
3701         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3702
3703         u8         reserved_at_300[0x100];
3704 };
3705
3706 enum {
3707         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3708 };
3709
3710 struct mlx5_ifc_query_scheduling_element_in_bits {
3711         u8         opcode[0x10];
3712         u8         reserved_at_10[0x10];
3713
3714         u8         reserved_at_20[0x10];
3715         u8         op_mod[0x10];
3716
3717         u8         scheduling_hierarchy[0x8];
3718         u8         reserved_at_48[0x18];
3719
3720         u8         scheduling_element_id[0x20];
3721
3722         u8         reserved_at_80[0x180];
3723 };
3724
3725 struct mlx5_ifc_query_rqt_out_bits {
3726         u8         status[0x8];
3727         u8         reserved_at_8[0x18];
3728
3729         u8         syndrome[0x20];
3730
3731         u8         reserved_at_40[0xc0];
3732
3733         struct mlx5_ifc_rqtc_bits rqt_context;
3734 };
3735
3736 struct mlx5_ifc_query_rqt_in_bits {
3737         u8         opcode[0x10];
3738         u8         reserved_at_10[0x10];
3739
3740         u8         reserved_at_20[0x10];
3741         u8         op_mod[0x10];
3742
3743         u8         reserved_at_40[0x8];
3744         u8         rqtn[0x18];
3745
3746         u8         reserved_at_60[0x20];
3747 };
3748
3749 struct mlx5_ifc_query_rq_out_bits {
3750         u8         status[0x8];
3751         u8         reserved_at_8[0x18];
3752
3753         u8         syndrome[0x20];
3754
3755         u8         reserved_at_40[0xc0];
3756
3757         struct mlx5_ifc_rqc_bits rq_context;
3758 };
3759
3760 struct mlx5_ifc_query_rq_in_bits {
3761         u8         opcode[0x10];
3762         u8         reserved_at_10[0x10];
3763
3764         u8         reserved_at_20[0x10];
3765         u8         op_mod[0x10];
3766
3767         u8         reserved_at_40[0x8];
3768         u8         rqn[0x18];
3769
3770         u8         reserved_at_60[0x20];
3771 };
3772
3773 struct mlx5_ifc_query_roce_address_out_bits {
3774         u8         status[0x8];
3775         u8         reserved_at_8[0x18];
3776
3777         u8         syndrome[0x20];
3778
3779         u8         reserved_at_40[0x40];
3780
3781         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3782 };
3783
3784 struct mlx5_ifc_query_roce_address_in_bits {
3785         u8         opcode[0x10];
3786         u8         reserved_at_10[0x10];
3787
3788         u8         reserved_at_20[0x10];
3789         u8         op_mod[0x10];
3790
3791         u8         roce_address_index[0x10];
3792         u8         reserved_at_50[0x10];
3793
3794         u8         reserved_at_60[0x20];
3795 };
3796
3797 struct mlx5_ifc_query_rmp_out_bits {
3798         u8         status[0x8];
3799         u8         reserved_at_8[0x18];
3800
3801         u8         syndrome[0x20];
3802
3803         u8         reserved_at_40[0xc0];
3804
3805         struct mlx5_ifc_rmpc_bits rmp_context;
3806 };
3807
3808 struct mlx5_ifc_query_rmp_in_bits {
3809         u8         opcode[0x10];
3810         u8         reserved_at_10[0x10];
3811
3812         u8         reserved_at_20[0x10];
3813         u8         op_mod[0x10];
3814
3815         u8         reserved_at_40[0x8];
3816         u8         rmpn[0x18];
3817
3818         u8         reserved_at_60[0x20];
3819 };
3820
3821 struct mlx5_ifc_query_qp_out_bits {
3822         u8         status[0x8];
3823         u8         reserved_at_8[0x18];
3824
3825         u8         syndrome[0x20];
3826
3827         u8         reserved_at_40[0x40];
3828
3829         u8         opt_param_mask[0x20];
3830
3831         u8         reserved_at_a0[0x20];
3832
3833         struct mlx5_ifc_qpc_bits qpc;
3834
3835         u8         reserved_at_800[0x80];
3836
3837         u8         pas[0][0x40];
3838 };
3839
3840 struct mlx5_ifc_query_qp_in_bits {
3841         u8         opcode[0x10];
3842         u8         reserved_at_10[0x10];
3843
3844         u8         reserved_at_20[0x10];
3845         u8         op_mod[0x10];
3846
3847         u8         reserved_at_40[0x8];
3848         u8         qpn[0x18];
3849
3850         u8         reserved_at_60[0x20];
3851 };
3852
3853 struct mlx5_ifc_query_q_counter_out_bits {
3854         u8         status[0x8];
3855         u8         reserved_at_8[0x18];
3856
3857         u8         syndrome[0x20];
3858
3859         u8         reserved_at_40[0x40];
3860
3861         u8         rx_write_requests[0x20];
3862
3863         u8         reserved_at_a0[0x20];
3864
3865         u8         rx_read_requests[0x20];
3866
3867         u8         reserved_at_e0[0x20];
3868
3869         u8         rx_atomic_requests[0x20];
3870
3871         u8         reserved_at_120[0x20];
3872
3873         u8         rx_dct_connect[0x20];
3874
3875         u8         reserved_at_160[0x20];
3876
3877         u8         out_of_buffer[0x20];
3878
3879         u8         reserved_at_1a0[0x20];
3880
3881         u8         out_of_sequence[0x20];
3882
3883         u8         reserved_at_1e0[0x20];
3884
3885         u8         duplicate_request[0x20];
3886
3887         u8         reserved_at_220[0x20];
3888
3889         u8         rnr_nak_retry_err[0x20];
3890
3891         u8         reserved_at_260[0x20];
3892
3893         u8         packet_seq_err[0x20];
3894
3895         u8         reserved_at_2a0[0x20];
3896
3897         u8         implied_nak_seq_err[0x20];
3898
3899         u8         reserved_at_2e0[0x20];
3900
3901         u8         local_ack_timeout_err[0x20];
3902
3903         u8         reserved_at_320[0x4e0];
3904 };
3905
3906 struct mlx5_ifc_query_q_counter_in_bits {
3907         u8         opcode[0x10];
3908         u8         reserved_at_10[0x10];
3909
3910         u8         reserved_at_20[0x10];
3911         u8         op_mod[0x10];
3912
3913         u8         reserved_at_40[0x80];
3914
3915         u8         clear[0x1];
3916         u8         reserved_at_c1[0x1f];
3917
3918         u8         reserved_at_e0[0x18];
3919         u8         counter_set_id[0x8];
3920 };
3921
3922 struct mlx5_ifc_query_pages_out_bits {
3923         u8         status[0x8];
3924         u8         reserved_at_8[0x18];
3925
3926         u8         syndrome[0x20];
3927
3928         u8         reserved_at_40[0x10];
3929         u8         function_id[0x10];
3930
3931         u8         num_pages[0x20];
3932 };
3933
3934 enum {
3935         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3936         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3937         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3938 };
3939
3940 struct mlx5_ifc_query_pages_in_bits {
3941         u8         opcode[0x10];
3942         u8         reserved_at_10[0x10];
3943
3944         u8         reserved_at_20[0x10];
3945         u8         op_mod[0x10];
3946
3947         u8         reserved_at_40[0x10];
3948         u8         function_id[0x10];
3949
3950         u8         reserved_at_60[0x20];
3951 };
3952
3953 struct mlx5_ifc_query_nic_vport_context_out_bits {
3954         u8         status[0x8];
3955         u8         reserved_at_8[0x18];
3956
3957         u8         syndrome[0x20];
3958
3959         u8         reserved_at_40[0x40];
3960
3961         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3962 };
3963
3964 struct mlx5_ifc_query_nic_vport_context_in_bits {
3965         u8         opcode[0x10];
3966         u8         reserved_at_10[0x10];
3967
3968         u8         reserved_at_20[0x10];
3969         u8         op_mod[0x10];
3970
3971         u8         other_vport[0x1];
3972         u8         reserved_at_41[0xf];
3973         u8         vport_number[0x10];
3974
3975         u8         reserved_at_60[0x5];
3976         u8         allowed_list_type[0x3];
3977         u8         reserved_at_68[0x18];
3978 };
3979
3980 struct mlx5_ifc_query_mkey_out_bits {
3981         u8         status[0x8];
3982         u8         reserved_at_8[0x18];
3983
3984         u8         syndrome[0x20];
3985
3986         u8         reserved_at_40[0x40];
3987
3988         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3989
3990         u8         reserved_at_280[0x600];
3991
3992         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3993
3994         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3995 };
3996
3997 struct mlx5_ifc_query_mkey_in_bits {
3998         u8         opcode[0x10];
3999         u8         reserved_at_10[0x10];
4000
4001         u8         reserved_at_20[0x10];
4002         u8         op_mod[0x10];
4003
4004         u8         reserved_at_40[0x8];
4005         u8         mkey_index[0x18];
4006
4007         u8         pg_access[0x1];
4008         u8         reserved_at_61[0x1f];
4009 };
4010
4011 struct mlx5_ifc_query_mad_demux_out_bits {
4012         u8         status[0x8];
4013         u8         reserved_at_8[0x18];
4014
4015         u8         syndrome[0x20];
4016
4017         u8         reserved_at_40[0x40];
4018
4019         u8         mad_dumux_parameters_block[0x20];
4020 };
4021
4022 struct mlx5_ifc_query_mad_demux_in_bits {
4023         u8         opcode[0x10];
4024         u8         reserved_at_10[0x10];
4025
4026         u8         reserved_at_20[0x10];
4027         u8         op_mod[0x10];
4028
4029         u8         reserved_at_40[0x40];
4030 };
4031
4032 struct mlx5_ifc_query_l2_table_entry_out_bits {
4033         u8         status[0x8];
4034         u8         reserved_at_8[0x18];
4035
4036         u8         syndrome[0x20];
4037
4038         u8         reserved_at_40[0xa0];
4039
4040         u8         reserved_at_e0[0x13];
4041         u8         vlan_valid[0x1];
4042         u8         vlan[0xc];
4043
4044         struct mlx5_ifc_mac_address_layout_bits mac_address;
4045
4046         u8         reserved_at_140[0xc0];
4047 };
4048
4049 struct mlx5_ifc_query_l2_table_entry_in_bits {
4050         u8         opcode[0x10];
4051         u8         reserved_at_10[0x10];
4052
4053         u8         reserved_at_20[0x10];
4054         u8         op_mod[0x10];
4055
4056         u8         reserved_at_40[0x60];
4057
4058         u8         reserved_at_a0[0x8];
4059         u8         table_index[0x18];
4060
4061         u8         reserved_at_c0[0x140];
4062 };
4063
4064 struct mlx5_ifc_query_issi_out_bits {
4065         u8         status[0x8];
4066         u8         reserved_at_8[0x18];
4067
4068         u8         syndrome[0x20];
4069
4070         u8         reserved_at_40[0x10];
4071         u8         current_issi[0x10];
4072
4073         u8         reserved_at_60[0xa0];
4074
4075         u8         reserved_at_100[76][0x8];
4076         u8         supported_issi_dw0[0x20];
4077 };
4078
4079 struct mlx5_ifc_query_issi_in_bits {
4080         u8         opcode[0x10];
4081         u8         reserved_at_10[0x10];
4082
4083         u8         reserved_at_20[0x10];
4084         u8         op_mod[0x10];
4085
4086         u8         reserved_at_40[0x40];
4087 };
4088
4089 struct mlx5_ifc_set_driver_version_out_bits {
4090         u8         status[0x8];
4091         u8         reserved_0[0x18];
4092
4093         u8         syndrome[0x20];
4094         u8         reserved_1[0x40];
4095 };
4096
4097 struct mlx5_ifc_set_driver_version_in_bits {
4098         u8         opcode[0x10];
4099         u8         reserved_0[0x10];
4100
4101         u8         reserved_1[0x10];
4102         u8         op_mod[0x10];
4103
4104         u8         reserved_2[0x40];
4105         u8         driver_version[64][0x8];
4106 };
4107
4108 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4109         u8         status[0x8];
4110         u8         reserved_at_8[0x18];
4111
4112         u8         syndrome[0x20];
4113
4114         u8         reserved_at_40[0x40];
4115
4116         struct mlx5_ifc_pkey_bits pkey[0];
4117 };
4118
4119 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4120         u8         opcode[0x10];
4121         u8         reserved_at_10[0x10];
4122
4123         u8         reserved_at_20[0x10];
4124         u8         op_mod[0x10];
4125
4126         u8         other_vport[0x1];
4127         u8         reserved_at_41[0xb];
4128         u8         port_num[0x4];
4129         u8         vport_number[0x10];
4130
4131         u8         reserved_at_60[0x10];
4132         u8         pkey_index[0x10];
4133 };
4134
4135 enum {
4136         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4137         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4138         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4139 };
4140
4141 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4142         u8         status[0x8];
4143         u8         reserved_at_8[0x18];
4144
4145         u8         syndrome[0x20];
4146
4147         u8         reserved_at_40[0x20];
4148
4149         u8         gids_num[0x10];
4150         u8         reserved_at_70[0x10];
4151
4152         struct mlx5_ifc_array128_auto_bits gid[0];
4153 };
4154
4155 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4156         u8         opcode[0x10];
4157         u8         reserved_at_10[0x10];
4158
4159         u8         reserved_at_20[0x10];
4160         u8         op_mod[0x10];
4161
4162         u8         other_vport[0x1];
4163         u8         reserved_at_41[0xb];
4164         u8         port_num[0x4];
4165         u8         vport_number[0x10];
4166
4167         u8         reserved_at_60[0x10];
4168         u8         gid_index[0x10];
4169 };
4170
4171 struct mlx5_ifc_query_hca_vport_context_out_bits {
4172         u8         status[0x8];
4173         u8         reserved_at_8[0x18];
4174
4175         u8         syndrome[0x20];
4176
4177         u8         reserved_at_40[0x40];
4178
4179         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4180 };
4181
4182 struct mlx5_ifc_query_hca_vport_context_in_bits {
4183         u8         opcode[0x10];
4184         u8         reserved_at_10[0x10];
4185
4186         u8         reserved_at_20[0x10];
4187         u8         op_mod[0x10];
4188
4189         u8         other_vport[0x1];
4190         u8         reserved_at_41[0xb];
4191         u8         port_num[0x4];
4192         u8         vport_number[0x10];
4193
4194         u8         reserved_at_60[0x20];
4195 };
4196
4197 struct mlx5_ifc_query_hca_cap_out_bits {
4198         u8         status[0x8];
4199         u8         reserved_at_8[0x18];
4200
4201         u8         syndrome[0x20];
4202
4203         u8         reserved_at_40[0x40];
4204
4205         union mlx5_ifc_hca_cap_union_bits capability;
4206 };
4207
4208 struct mlx5_ifc_query_hca_cap_in_bits {
4209         u8         opcode[0x10];
4210         u8         reserved_at_10[0x10];
4211
4212         u8         reserved_at_20[0x10];
4213         u8         op_mod[0x10];
4214
4215         u8         reserved_at_40[0x40];
4216 };
4217
4218 struct mlx5_ifc_query_flow_table_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_at_8[0x18];
4221
4222         u8         syndrome[0x20];
4223
4224         u8         reserved_at_40[0x80];
4225
4226         u8         reserved_at_c0[0x8];
4227         u8         level[0x8];
4228         u8         reserved_at_d0[0x8];
4229         u8         log_size[0x8];
4230
4231         u8         reserved_at_e0[0x120];
4232 };
4233
4234 struct mlx5_ifc_query_flow_table_in_bits {
4235         u8         opcode[0x10];
4236         u8         reserved_at_10[0x10];
4237
4238         u8         reserved_at_20[0x10];
4239         u8         op_mod[0x10];
4240
4241         u8         reserved_at_40[0x40];
4242
4243         u8         table_type[0x8];
4244         u8         reserved_at_88[0x18];
4245
4246         u8         reserved_at_a0[0x8];
4247         u8         table_id[0x18];
4248
4249         u8         reserved_at_c0[0x140];
4250 };
4251
4252 struct mlx5_ifc_query_fte_out_bits {
4253         u8         status[0x8];
4254         u8         reserved_at_8[0x18];
4255
4256         u8         syndrome[0x20];
4257
4258         u8         reserved_at_40[0x1c0];
4259
4260         struct mlx5_ifc_flow_context_bits flow_context;
4261 };
4262
4263 struct mlx5_ifc_query_fte_in_bits {
4264         u8         opcode[0x10];
4265         u8         reserved_at_10[0x10];
4266
4267         u8         reserved_at_20[0x10];
4268         u8         op_mod[0x10];
4269
4270         u8         reserved_at_40[0x40];
4271
4272         u8         table_type[0x8];
4273         u8         reserved_at_88[0x18];
4274
4275         u8         reserved_at_a0[0x8];
4276         u8         table_id[0x18];
4277
4278         u8         reserved_at_c0[0x40];
4279
4280         u8         flow_index[0x20];
4281
4282         u8         reserved_at_120[0xe0];
4283 };
4284
4285 enum {
4286         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4287         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4288         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4289 };
4290
4291 struct mlx5_ifc_query_flow_group_out_bits {
4292         u8         status[0x8];
4293         u8         reserved_at_8[0x18];
4294
4295         u8         syndrome[0x20];
4296
4297         u8         reserved_at_40[0xa0];
4298
4299         u8         start_flow_index[0x20];
4300
4301         u8         reserved_at_100[0x20];
4302
4303         u8         end_flow_index[0x20];
4304
4305         u8         reserved_at_140[0xa0];
4306
4307         u8         reserved_at_1e0[0x18];
4308         u8         match_criteria_enable[0x8];
4309
4310         struct mlx5_ifc_fte_match_param_bits match_criteria;
4311
4312         u8         reserved_at_1200[0xe00];
4313 };
4314
4315 struct mlx5_ifc_query_flow_group_in_bits {
4316         u8         opcode[0x10];
4317         u8         reserved_at_10[0x10];
4318
4319         u8         reserved_at_20[0x10];
4320         u8         op_mod[0x10];
4321
4322         u8         reserved_at_40[0x40];
4323
4324         u8         table_type[0x8];
4325         u8         reserved_at_88[0x18];
4326
4327         u8         reserved_at_a0[0x8];
4328         u8         table_id[0x18];
4329
4330         u8         group_id[0x20];
4331
4332         u8         reserved_at_e0[0x120];
4333 };
4334
4335 struct mlx5_ifc_query_flow_counter_out_bits {
4336         u8         status[0x8];
4337         u8         reserved_at_8[0x18];
4338
4339         u8         syndrome[0x20];
4340
4341         u8         reserved_at_40[0x40];
4342
4343         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4344 };
4345
4346 struct mlx5_ifc_query_flow_counter_in_bits {
4347         u8         opcode[0x10];
4348         u8         reserved_at_10[0x10];
4349
4350         u8         reserved_at_20[0x10];
4351         u8         op_mod[0x10];
4352
4353         u8         reserved_at_40[0x80];
4354
4355         u8         clear[0x1];
4356         u8         reserved_at_c1[0xf];
4357         u8         num_of_counters[0x10];
4358
4359         u8         reserved_at_e0[0x10];
4360         u8         flow_counter_id[0x10];
4361 };
4362
4363 struct mlx5_ifc_query_esw_vport_context_out_bits {
4364         u8         status[0x8];
4365         u8         reserved_at_8[0x18];
4366
4367         u8         syndrome[0x20];
4368
4369         u8         reserved_at_40[0x40];
4370
4371         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4372 };
4373
4374 struct mlx5_ifc_query_esw_vport_context_in_bits {
4375         u8         opcode[0x10];
4376         u8         reserved_at_10[0x10];
4377
4378         u8         reserved_at_20[0x10];
4379         u8         op_mod[0x10];
4380
4381         u8         other_vport[0x1];
4382         u8         reserved_at_41[0xf];
4383         u8         vport_number[0x10];
4384
4385         u8         reserved_at_60[0x20];
4386 };
4387
4388 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4389         u8         status[0x8];
4390         u8         reserved_at_8[0x18];
4391
4392         u8         syndrome[0x20];
4393
4394         u8         reserved_at_40[0x40];
4395 };
4396
4397 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4398         u8         reserved_at_0[0x1c];
4399         u8         vport_cvlan_insert[0x1];
4400         u8         vport_svlan_insert[0x1];
4401         u8         vport_cvlan_strip[0x1];
4402         u8         vport_svlan_strip[0x1];
4403 };
4404
4405 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4406         u8         opcode[0x10];
4407         u8         reserved_at_10[0x10];
4408
4409         u8         reserved_at_20[0x10];
4410         u8         op_mod[0x10];
4411
4412         u8         other_vport[0x1];
4413         u8         reserved_at_41[0xf];
4414         u8         vport_number[0x10];
4415
4416         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4417
4418         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4419 };
4420
4421 struct mlx5_ifc_query_eq_out_bits {
4422         u8         status[0x8];
4423         u8         reserved_at_8[0x18];
4424
4425         u8         syndrome[0x20];
4426
4427         u8         reserved_at_40[0x40];
4428
4429         struct mlx5_ifc_eqc_bits eq_context_entry;
4430
4431         u8         reserved_at_280[0x40];
4432
4433         u8         event_bitmask[0x40];
4434
4435         u8         reserved_at_300[0x580];
4436
4437         u8         pas[0][0x40];
4438 };
4439
4440 struct mlx5_ifc_query_eq_in_bits {
4441         u8         opcode[0x10];
4442         u8         reserved_at_10[0x10];
4443
4444         u8         reserved_at_20[0x10];
4445         u8         op_mod[0x10];
4446
4447         u8         reserved_at_40[0x18];
4448         u8         eq_number[0x8];
4449
4450         u8         reserved_at_60[0x20];
4451 };
4452
4453 struct mlx5_ifc_encap_header_in_bits {
4454         u8         reserved_at_0[0x5];
4455         u8         header_type[0x3];
4456         u8         reserved_at_8[0xe];
4457         u8         encap_header_size[0xa];
4458
4459         u8         reserved_at_20[0x10];
4460         u8         encap_header[2][0x8];
4461
4462         u8         more_encap_header[0][0x8];
4463 };
4464
4465 struct mlx5_ifc_query_encap_header_out_bits {
4466         u8         status[0x8];
4467         u8         reserved_at_8[0x18];
4468
4469         u8         syndrome[0x20];
4470
4471         u8         reserved_at_40[0xa0];
4472
4473         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4474 };
4475
4476 struct mlx5_ifc_query_encap_header_in_bits {
4477         u8         opcode[0x10];
4478         u8         reserved_at_10[0x10];
4479
4480         u8         reserved_at_20[0x10];
4481         u8         op_mod[0x10];
4482
4483         u8         encap_id[0x20];
4484
4485         u8         reserved_at_60[0xa0];
4486 };
4487
4488 struct mlx5_ifc_alloc_encap_header_out_bits {
4489         u8         status[0x8];
4490         u8         reserved_at_8[0x18];
4491
4492         u8         syndrome[0x20];
4493
4494         u8         encap_id[0x20];
4495
4496         u8         reserved_at_60[0x20];
4497 };
4498
4499 struct mlx5_ifc_alloc_encap_header_in_bits {
4500         u8         opcode[0x10];
4501         u8         reserved_at_10[0x10];
4502
4503         u8         reserved_at_20[0x10];
4504         u8         op_mod[0x10];
4505
4506         u8         reserved_at_40[0xa0];
4507
4508         struct mlx5_ifc_encap_header_in_bits encap_header;
4509 };
4510
4511 struct mlx5_ifc_dealloc_encap_header_out_bits {
4512         u8         status[0x8];
4513         u8         reserved_at_8[0x18];
4514
4515         u8         syndrome[0x20];
4516
4517         u8         reserved_at_40[0x40];
4518 };
4519
4520 struct mlx5_ifc_dealloc_encap_header_in_bits {
4521         u8         opcode[0x10];
4522         u8         reserved_at_10[0x10];
4523
4524         u8         reserved_20[0x10];
4525         u8         op_mod[0x10];
4526
4527         u8         encap_id[0x20];
4528
4529         u8         reserved_60[0x20];
4530 };
4531
4532 struct mlx5_ifc_query_dct_out_bits {
4533         u8         status[0x8];
4534         u8         reserved_at_8[0x18];
4535
4536         u8         syndrome[0x20];
4537
4538         u8         reserved_at_40[0x40];
4539
4540         struct mlx5_ifc_dctc_bits dct_context_entry;
4541
4542         u8         reserved_at_280[0x180];
4543 };
4544
4545 struct mlx5_ifc_query_dct_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_at_10[0x10];
4548
4549         u8         reserved_at_20[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         reserved_at_40[0x8];
4553         u8         dctn[0x18];
4554
4555         u8         reserved_at_60[0x20];
4556 };
4557
4558 struct mlx5_ifc_query_cq_out_bits {
4559         u8         status[0x8];
4560         u8         reserved_at_8[0x18];
4561
4562         u8         syndrome[0x20];
4563
4564         u8         reserved_at_40[0x40];
4565
4566         struct mlx5_ifc_cqc_bits cq_context;
4567
4568         u8         reserved_at_280[0x600];
4569
4570         u8         pas[0][0x40];
4571 };
4572
4573 struct mlx5_ifc_query_cq_in_bits {
4574         u8         opcode[0x10];
4575         u8         reserved_at_10[0x10];
4576
4577         u8         reserved_at_20[0x10];
4578         u8         op_mod[0x10];
4579
4580         u8         reserved_at_40[0x8];
4581         u8         cqn[0x18];
4582
4583         u8         reserved_at_60[0x20];
4584 };
4585
4586 struct mlx5_ifc_query_cong_status_out_bits {
4587         u8         status[0x8];
4588         u8         reserved_at_8[0x18];
4589
4590         u8         syndrome[0x20];
4591
4592         u8         reserved_at_40[0x20];
4593
4594         u8         enable[0x1];
4595         u8         tag_enable[0x1];
4596         u8         reserved_at_62[0x1e];
4597 };
4598
4599 struct mlx5_ifc_query_cong_status_in_bits {
4600         u8         opcode[0x10];
4601         u8         reserved_at_10[0x10];
4602
4603         u8         reserved_at_20[0x10];
4604         u8         op_mod[0x10];
4605
4606         u8         reserved_at_40[0x18];
4607         u8         priority[0x4];
4608         u8         cong_protocol[0x4];
4609
4610         u8         reserved_at_60[0x20];
4611 };
4612
4613 struct mlx5_ifc_query_cong_statistics_out_bits {
4614         u8         status[0x8];
4615         u8         reserved_at_8[0x18];
4616
4617         u8         syndrome[0x20];
4618
4619         u8         reserved_at_40[0x40];
4620
4621         u8         cur_flows[0x20];
4622
4623         u8         sum_flows[0x20];
4624
4625         u8         cnp_ignored_high[0x20];
4626
4627         u8         cnp_ignored_low[0x20];
4628
4629         u8         cnp_handled_high[0x20];
4630
4631         u8         cnp_handled_low[0x20];
4632
4633         u8         reserved_at_140[0x100];
4634
4635         u8         time_stamp_high[0x20];
4636
4637         u8         time_stamp_low[0x20];
4638
4639         u8         accumulators_period[0x20];
4640
4641         u8         ecn_marked_roce_packets_high[0x20];
4642
4643         u8         ecn_marked_roce_packets_low[0x20];
4644
4645         u8         cnps_sent_high[0x20];
4646
4647         u8         cnps_sent_low[0x20];
4648
4649         u8         reserved_at_320[0x560];
4650 };
4651
4652 struct mlx5_ifc_query_cong_statistics_in_bits {
4653         u8         opcode[0x10];
4654         u8         reserved_at_10[0x10];
4655
4656         u8         reserved_at_20[0x10];
4657         u8         op_mod[0x10];
4658
4659         u8         clear[0x1];
4660         u8         reserved_at_41[0x1f];
4661
4662         u8         reserved_at_60[0x20];
4663 };
4664
4665 struct mlx5_ifc_query_cong_params_out_bits {
4666         u8         status[0x8];
4667         u8         reserved_at_8[0x18];
4668
4669         u8         syndrome[0x20];
4670
4671         u8         reserved_at_40[0x40];
4672
4673         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4674 };
4675
4676 struct mlx5_ifc_query_cong_params_in_bits {
4677         u8         opcode[0x10];
4678         u8         reserved_at_10[0x10];
4679
4680         u8         reserved_at_20[0x10];
4681         u8         op_mod[0x10];
4682
4683         u8         reserved_at_40[0x1c];
4684         u8         cong_protocol[0x4];
4685
4686         u8         reserved_at_60[0x20];
4687 };
4688
4689 struct mlx5_ifc_query_adapter_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_at_8[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_at_40[0x40];
4696
4697         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4698 };
4699
4700 struct mlx5_ifc_query_adapter_in_bits {
4701         u8         opcode[0x10];
4702         u8         reserved_at_10[0x10];
4703
4704         u8         reserved_at_20[0x10];
4705         u8         op_mod[0x10];
4706
4707         u8         reserved_at_40[0x40];
4708 };
4709
4710 struct mlx5_ifc_qp_2rst_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_at_8[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         reserved_at_40[0x40];
4717 };
4718
4719 struct mlx5_ifc_qp_2rst_in_bits {
4720         u8         opcode[0x10];
4721         u8         reserved_at_10[0x10];
4722
4723         u8         reserved_at_20[0x10];
4724         u8         op_mod[0x10];
4725
4726         u8         reserved_at_40[0x8];
4727         u8         qpn[0x18];
4728
4729         u8         reserved_at_60[0x20];
4730 };
4731
4732 struct mlx5_ifc_qp_2err_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_at_8[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_at_40[0x40];
4739 };
4740
4741 struct mlx5_ifc_qp_2err_in_bits {
4742         u8         opcode[0x10];
4743         u8         reserved_at_10[0x10];
4744
4745         u8         reserved_at_20[0x10];
4746         u8         op_mod[0x10];
4747
4748         u8         reserved_at_40[0x8];
4749         u8         qpn[0x18];
4750
4751         u8         reserved_at_60[0x20];
4752 };
4753
4754 struct mlx5_ifc_page_fault_resume_out_bits {
4755         u8         status[0x8];
4756         u8         reserved_at_8[0x18];
4757
4758         u8         syndrome[0x20];
4759
4760         u8         reserved_at_40[0x40];
4761 };
4762
4763 struct mlx5_ifc_page_fault_resume_in_bits {
4764         u8         opcode[0x10];
4765         u8         reserved_at_10[0x10];
4766
4767         u8         reserved_at_20[0x10];
4768         u8         op_mod[0x10];
4769
4770         u8         error[0x1];
4771         u8         reserved_at_41[0x4];
4772         u8         rdma[0x1];
4773         u8         read_write[0x1];
4774         u8         req_res[0x1];
4775         u8         qpn[0x18];
4776
4777         u8         reserved_at_60[0x20];
4778 };
4779
4780 struct mlx5_ifc_nop_out_bits {
4781         u8         status[0x8];
4782         u8         reserved_at_8[0x18];
4783
4784         u8         syndrome[0x20];
4785
4786         u8         reserved_at_40[0x40];
4787 };
4788
4789 struct mlx5_ifc_nop_in_bits {
4790         u8         opcode[0x10];
4791         u8         reserved_at_10[0x10];
4792
4793         u8         reserved_at_20[0x10];
4794         u8         op_mod[0x10];
4795
4796         u8         reserved_at_40[0x40];
4797 };
4798
4799 struct mlx5_ifc_modify_vport_state_out_bits {
4800         u8         status[0x8];
4801         u8         reserved_at_8[0x18];
4802
4803         u8         syndrome[0x20];
4804
4805         u8         reserved_at_40[0x40];
4806 };
4807
4808 struct mlx5_ifc_modify_vport_state_in_bits {
4809         u8         opcode[0x10];
4810         u8         reserved_at_10[0x10];
4811
4812         u8         reserved_at_20[0x10];
4813         u8         op_mod[0x10];
4814
4815         u8         other_vport[0x1];
4816         u8         reserved_at_41[0xf];
4817         u8         vport_number[0x10];
4818
4819         u8         reserved_at_60[0x18];
4820         u8         admin_state[0x4];
4821         u8         reserved_at_7c[0x4];
4822 };
4823
4824 struct mlx5_ifc_modify_tis_out_bits {
4825         u8         status[0x8];
4826         u8         reserved_at_8[0x18];
4827
4828         u8         syndrome[0x20];
4829
4830         u8         reserved_at_40[0x40];
4831 };
4832
4833 struct mlx5_ifc_modify_tis_bitmask_bits {
4834         u8         reserved_at_0[0x20];
4835
4836         u8         reserved_at_20[0x1d];
4837         u8         lag_tx_port_affinity[0x1];
4838         u8         strict_lag_tx_port_affinity[0x1];
4839         u8         prio[0x1];
4840 };
4841
4842 struct mlx5_ifc_modify_tis_in_bits {
4843         u8         opcode[0x10];
4844         u8         reserved_at_10[0x10];
4845
4846         u8         reserved_at_20[0x10];
4847         u8         op_mod[0x10];
4848
4849         u8         reserved_at_40[0x8];
4850         u8         tisn[0x18];
4851
4852         u8         reserved_at_60[0x20];
4853
4854         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4855
4856         u8         reserved_at_c0[0x40];
4857
4858         struct mlx5_ifc_tisc_bits ctx;
4859 };
4860
4861 struct mlx5_ifc_modify_tir_bitmask_bits {
4862         u8         reserved_at_0[0x20];
4863
4864         u8         reserved_at_20[0x1b];
4865         u8         self_lb_en[0x1];
4866         u8         reserved_at_3c[0x1];
4867         u8         hash[0x1];
4868         u8         reserved_at_3e[0x1];
4869         u8         lro[0x1];
4870 };
4871
4872 struct mlx5_ifc_modify_tir_out_bits {
4873         u8         status[0x8];
4874         u8         reserved_at_8[0x18];
4875
4876         u8         syndrome[0x20];
4877
4878         u8         reserved_at_40[0x40];
4879 };
4880
4881 struct mlx5_ifc_modify_tir_in_bits {
4882         u8         opcode[0x10];
4883         u8         reserved_at_10[0x10];
4884
4885         u8         reserved_at_20[0x10];
4886         u8         op_mod[0x10];
4887
4888         u8         reserved_at_40[0x8];
4889         u8         tirn[0x18];
4890
4891         u8         reserved_at_60[0x20];
4892
4893         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4894
4895         u8         reserved_at_c0[0x40];
4896
4897         struct mlx5_ifc_tirc_bits ctx;
4898 };
4899
4900 struct mlx5_ifc_modify_sq_out_bits {
4901         u8         status[0x8];
4902         u8         reserved_at_8[0x18];
4903
4904         u8         syndrome[0x20];
4905
4906         u8         reserved_at_40[0x40];
4907 };
4908
4909 struct mlx5_ifc_modify_sq_in_bits {
4910         u8         opcode[0x10];
4911         u8         reserved_at_10[0x10];
4912
4913         u8         reserved_at_20[0x10];
4914         u8         op_mod[0x10];
4915
4916         u8         sq_state[0x4];
4917         u8         reserved_at_44[0x4];
4918         u8         sqn[0x18];
4919
4920         u8         reserved_at_60[0x20];
4921
4922         u8         modify_bitmask[0x40];
4923
4924         u8         reserved_at_c0[0x40];
4925
4926         struct mlx5_ifc_sqc_bits ctx;
4927 };
4928
4929 struct mlx5_ifc_modify_scheduling_element_out_bits {
4930         u8         status[0x8];
4931         u8         reserved_at_8[0x18];
4932
4933         u8         syndrome[0x20];
4934
4935         u8         reserved_at_40[0x1c0];
4936 };
4937
4938 enum {
4939         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4940         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4941 };
4942
4943 struct mlx5_ifc_modify_scheduling_element_in_bits {
4944         u8         opcode[0x10];
4945         u8         reserved_at_10[0x10];
4946
4947         u8         reserved_at_20[0x10];
4948         u8         op_mod[0x10];
4949
4950         u8         scheduling_hierarchy[0x8];
4951         u8         reserved_at_48[0x18];
4952
4953         u8         scheduling_element_id[0x20];
4954
4955         u8         reserved_at_80[0x20];
4956
4957         u8         modify_bitmask[0x20];
4958
4959         u8         reserved_at_c0[0x40];
4960
4961         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4962
4963         u8         reserved_at_300[0x100];
4964 };
4965
4966 struct mlx5_ifc_modify_rqt_out_bits {
4967         u8         status[0x8];
4968         u8         reserved_at_8[0x18];
4969
4970         u8         syndrome[0x20];
4971
4972         u8         reserved_at_40[0x40];
4973 };
4974
4975 struct mlx5_ifc_rqt_bitmask_bits {
4976         u8         reserved_at_0[0x20];
4977
4978         u8         reserved_at_20[0x1f];
4979         u8         rqn_list[0x1];
4980 };
4981
4982 struct mlx5_ifc_modify_rqt_in_bits {
4983         u8         opcode[0x10];
4984         u8         reserved_at_10[0x10];
4985
4986         u8         reserved_at_20[0x10];
4987         u8         op_mod[0x10];
4988
4989         u8         reserved_at_40[0x8];
4990         u8         rqtn[0x18];
4991
4992         u8         reserved_at_60[0x20];
4993
4994         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4995
4996         u8         reserved_at_c0[0x40];
4997
4998         struct mlx5_ifc_rqtc_bits ctx;
4999 };
5000
5001 struct mlx5_ifc_modify_rq_out_bits {
5002         u8         status[0x8];
5003         u8         reserved_at_8[0x18];
5004
5005         u8         syndrome[0x20];
5006
5007         u8         reserved_at_40[0x40];
5008 };
5009
5010 enum {
5011         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5012         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5013 };
5014
5015 struct mlx5_ifc_modify_rq_in_bits {
5016         u8         opcode[0x10];
5017         u8         reserved_at_10[0x10];
5018
5019         u8         reserved_at_20[0x10];
5020         u8         op_mod[0x10];
5021
5022         u8         rq_state[0x4];
5023         u8         reserved_at_44[0x4];
5024         u8         rqn[0x18];
5025
5026         u8         reserved_at_60[0x20];
5027
5028         u8         modify_bitmask[0x40];
5029
5030         u8         reserved_at_c0[0x40];
5031
5032         struct mlx5_ifc_rqc_bits ctx;
5033 };
5034
5035 struct mlx5_ifc_modify_rmp_out_bits {
5036         u8         status[0x8];
5037         u8         reserved_at_8[0x18];
5038
5039         u8         syndrome[0x20];
5040
5041         u8         reserved_at_40[0x40];
5042 };
5043
5044 struct mlx5_ifc_rmp_bitmask_bits {
5045         u8         reserved_at_0[0x20];
5046
5047         u8         reserved_at_20[0x1f];
5048         u8         lwm[0x1];
5049 };
5050
5051 struct mlx5_ifc_modify_rmp_in_bits {
5052         u8         opcode[0x10];
5053         u8         reserved_at_10[0x10];
5054
5055         u8         reserved_at_20[0x10];
5056         u8         op_mod[0x10];
5057
5058         u8         rmp_state[0x4];
5059         u8         reserved_at_44[0x4];
5060         u8         rmpn[0x18];
5061
5062         u8         reserved_at_60[0x20];
5063
5064         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5065
5066         u8         reserved_at_c0[0x40];
5067
5068         struct mlx5_ifc_rmpc_bits ctx;
5069 };
5070
5071 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5072         u8         status[0x8];
5073         u8         reserved_at_8[0x18];
5074
5075         u8         syndrome[0x20];
5076
5077         u8         reserved_at_40[0x40];
5078 };
5079
5080 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5081         u8         reserved_at_0[0x16];
5082         u8         node_guid[0x1];
5083         u8         port_guid[0x1];
5084         u8         min_inline[0x1];
5085         u8         mtu[0x1];
5086         u8         change_event[0x1];
5087         u8         promisc[0x1];
5088         u8         permanent_address[0x1];
5089         u8         addresses_list[0x1];
5090         u8         roce_en[0x1];
5091         u8         reserved_at_1f[0x1];
5092 };
5093
5094 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5095         u8         opcode[0x10];
5096         u8         reserved_at_10[0x10];
5097
5098         u8         reserved_at_20[0x10];
5099         u8         op_mod[0x10];
5100
5101         u8         other_vport[0x1];
5102         u8         reserved_at_41[0xf];
5103         u8         vport_number[0x10];
5104
5105         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5106
5107         u8         reserved_at_80[0x780];
5108
5109         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5110 };
5111
5112 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5113         u8         status[0x8];
5114         u8         reserved_at_8[0x18];
5115
5116         u8         syndrome[0x20];
5117
5118         u8         reserved_at_40[0x40];
5119 };
5120
5121 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5122         u8         opcode[0x10];
5123         u8         reserved_at_10[0x10];
5124
5125         u8         reserved_at_20[0x10];
5126         u8         op_mod[0x10];
5127
5128         u8         other_vport[0x1];
5129         u8         reserved_at_41[0xb];
5130         u8         port_num[0x4];
5131         u8         vport_number[0x10];
5132
5133         u8         reserved_at_60[0x20];
5134
5135         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5136 };
5137
5138 struct mlx5_ifc_modify_cq_out_bits {
5139         u8         status[0x8];
5140         u8         reserved_at_8[0x18];
5141
5142         u8         syndrome[0x20];
5143
5144         u8         reserved_at_40[0x40];
5145 };
5146
5147 enum {
5148         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5149         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5150 };
5151
5152 struct mlx5_ifc_modify_cq_in_bits {
5153         u8         opcode[0x10];
5154         u8         reserved_at_10[0x10];
5155
5156         u8         reserved_at_20[0x10];
5157         u8         op_mod[0x10];
5158
5159         u8         reserved_at_40[0x8];
5160         u8         cqn[0x18];
5161
5162         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5163
5164         struct mlx5_ifc_cqc_bits cq_context;
5165
5166         u8         reserved_at_280[0x600];
5167
5168         u8         pas[0][0x40];
5169 };
5170
5171 struct mlx5_ifc_modify_cong_status_out_bits {
5172         u8         status[0x8];
5173         u8         reserved_at_8[0x18];
5174
5175         u8         syndrome[0x20];
5176
5177         u8         reserved_at_40[0x40];
5178 };
5179
5180 struct mlx5_ifc_modify_cong_status_in_bits {
5181         u8         opcode[0x10];
5182         u8         reserved_at_10[0x10];
5183
5184         u8         reserved_at_20[0x10];
5185         u8         op_mod[0x10];
5186
5187         u8         reserved_at_40[0x18];
5188         u8         priority[0x4];
5189         u8         cong_protocol[0x4];
5190
5191         u8         enable[0x1];
5192         u8         tag_enable[0x1];
5193         u8         reserved_at_62[0x1e];
5194 };
5195
5196 struct mlx5_ifc_modify_cong_params_out_bits {
5197         u8         status[0x8];
5198         u8         reserved_at_8[0x18];
5199
5200         u8         syndrome[0x20];
5201
5202         u8         reserved_at_40[0x40];
5203 };
5204
5205 struct mlx5_ifc_modify_cong_params_in_bits {
5206         u8         opcode[0x10];
5207         u8         reserved_at_10[0x10];
5208
5209         u8         reserved_at_20[0x10];
5210         u8         op_mod[0x10];
5211
5212         u8         reserved_at_40[0x1c];
5213         u8         cong_protocol[0x4];
5214
5215         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5216
5217         u8         reserved_at_80[0x80];
5218
5219         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5220 };
5221
5222 struct mlx5_ifc_manage_pages_out_bits {
5223         u8         status[0x8];
5224         u8         reserved_at_8[0x18];
5225
5226         u8         syndrome[0x20];
5227
5228         u8         output_num_entries[0x20];
5229
5230         u8         reserved_at_60[0x20];
5231
5232         u8         pas[0][0x40];
5233 };
5234
5235 enum {
5236         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5237         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5238         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5239 };
5240
5241 struct mlx5_ifc_manage_pages_in_bits {
5242         u8         opcode[0x10];
5243         u8         reserved_at_10[0x10];
5244
5245         u8         reserved_at_20[0x10];
5246         u8         op_mod[0x10];
5247
5248         u8         reserved_at_40[0x10];
5249         u8         function_id[0x10];
5250
5251         u8         input_num_entries[0x20];
5252
5253         u8         pas[0][0x40];
5254 };
5255
5256 struct mlx5_ifc_mad_ifc_out_bits {
5257         u8         status[0x8];
5258         u8         reserved_at_8[0x18];
5259
5260         u8         syndrome[0x20];
5261
5262         u8         reserved_at_40[0x40];
5263
5264         u8         response_mad_packet[256][0x8];
5265 };
5266
5267 struct mlx5_ifc_mad_ifc_in_bits {
5268         u8         opcode[0x10];
5269         u8         reserved_at_10[0x10];
5270
5271         u8         reserved_at_20[0x10];
5272         u8         op_mod[0x10];
5273
5274         u8         remote_lid[0x10];
5275         u8         reserved_at_50[0x8];
5276         u8         port[0x8];
5277
5278         u8         reserved_at_60[0x20];
5279
5280         u8         mad[256][0x8];
5281 };
5282
5283 struct mlx5_ifc_init_hca_out_bits {
5284         u8         status[0x8];
5285         u8         reserved_at_8[0x18];
5286
5287         u8         syndrome[0x20];
5288
5289         u8         reserved_at_40[0x40];
5290 };
5291
5292 struct mlx5_ifc_init_hca_in_bits {
5293         u8         opcode[0x10];
5294         u8         reserved_at_10[0x10];
5295
5296         u8         reserved_at_20[0x10];
5297         u8         op_mod[0x10];
5298
5299         u8         reserved_at_40[0x40];
5300 };
5301
5302 struct mlx5_ifc_init2rtr_qp_out_bits {
5303         u8         status[0x8];
5304         u8         reserved_at_8[0x18];
5305
5306         u8         syndrome[0x20];
5307
5308         u8         reserved_at_40[0x40];
5309 };
5310
5311 struct mlx5_ifc_init2rtr_qp_in_bits {
5312         u8         opcode[0x10];
5313         u8         reserved_at_10[0x10];
5314
5315         u8         reserved_at_20[0x10];
5316         u8         op_mod[0x10];
5317
5318         u8         reserved_at_40[0x8];
5319         u8         qpn[0x18];
5320
5321         u8         reserved_at_60[0x20];
5322
5323         u8         opt_param_mask[0x20];
5324
5325         u8         reserved_at_a0[0x20];
5326
5327         struct mlx5_ifc_qpc_bits qpc;
5328
5329         u8         reserved_at_800[0x80];
5330 };
5331
5332 struct mlx5_ifc_init2init_qp_out_bits {
5333         u8         status[0x8];
5334         u8         reserved_at_8[0x18];
5335
5336         u8         syndrome[0x20];
5337
5338         u8         reserved_at_40[0x40];
5339 };
5340
5341 struct mlx5_ifc_init2init_qp_in_bits {
5342         u8         opcode[0x10];
5343         u8         reserved_at_10[0x10];
5344
5345         u8         reserved_at_20[0x10];
5346         u8         op_mod[0x10];
5347
5348         u8         reserved_at_40[0x8];
5349         u8         qpn[0x18];
5350
5351         u8         reserved_at_60[0x20];
5352
5353         u8         opt_param_mask[0x20];
5354
5355         u8         reserved_at_a0[0x20];
5356
5357         struct mlx5_ifc_qpc_bits qpc;
5358
5359         u8         reserved_at_800[0x80];
5360 };
5361
5362 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5363         u8         status[0x8];
5364         u8         reserved_at_8[0x18];
5365
5366         u8         syndrome[0x20];
5367
5368         u8         reserved_at_40[0x40];
5369
5370         u8         packet_headers_log[128][0x8];
5371
5372         u8         packet_syndrome[64][0x8];
5373 };
5374
5375 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5376         u8         opcode[0x10];
5377         u8         reserved_at_10[0x10];
5378
5379         u8         reserved_at_20[0x10];
5380         u8         op_mod[0x10];
5381
5382         u8         reserved_at_40[0x40];
5383 };
5384
5385 struct mlx5_ifc_gen_eqe_in_bits {
5386         u8         opcode[0x10];
5387         u8         reserved_at_10[0x10];
5388
5389         u8         reserved_at_20[0x10];
5390         u8         op_mod[0x10];
5391
5392         u8         reserved_at_40[0x18];
5393         u8         eq_number[0x8];
5394
5395         u8         reserved_at_60[0x20];
5396
5397         u8         eqe[64][0x8];
5398 };
5399
5400 struct mlx5_ifc_gen_eq_out_bits {
5401         u8         status[0x8];
5402         u8         reserved_at_8[0x18];
5403
5404         u8         syndrome[0x20];
5405
5406         u8         reserved_at_40[0x40];
5407 };
5408
5409 struct mlx5_ifc_enable_hca_out_bits {
5410         u8         status[0x8];
5411         u8         reserved_at_8[0x18];
5412
5413         u8         syndrome[0x20];
5414
5415         u8         reserved_at_40[0x20];
5416 };
5417
5418 struct mlx5_ifc_enable_hca_in_bits {
5419         u8         opcode[0x10];
5420         u8         reserved_at_10[0x10];
5421
5422         u8         reserved_at_20[0x10];
5423         u8         op_mod[0x10];
5424
5425         u8         reserved_at_40[0x10];
5426         u8         function_id[0x10];
5427
5428         u8         reserved_at_60[0x20];
5429 };
5430
5431 struct mlx5_ifc_drain_dct_out_bits {
5432         u8         status[0x8];
5433         u8         reserved_at_8[0x18];
5434
5435         u8         syndrome[0x20];
5436
5437         u8         reserved_at_40[0x40];
5438 };
5439
5440 struct mlx5_ifc_drain_dct_in_bits {
5441         u8         opcode[0x10];
5442         u8         reserved_at_10[0x10];
5443
5444         u8         reserved_at_20[0x10];
5445         u8         op_mod[0x10];
5446
5447         u8         reserved_at_40[0x8];
5448         u8         dctn[0x18];
5449
5450         u8         reserved_at_60[0x20];
5451 };
5452
5453 struct mlx5_ifc_disable_hca_out_bits {
5454         u8         status[0x8];
5455         u8         reserved_at_8[0x18];
5456
5457         u8         syndrome[0x20];
5458
5459         u8         reserved_at_40[0x20];
5460 };
5461
5462 struct mlx5_ifc_disable_hca_in_bits {
5463         u8         opcode[0x10];
5464         u8         reserved_at_10[0x10];
5465
5466         u8         reserved_at_20[0x10];
5467         u8         op_mod[0x10];
5468
5469         u8         reserved_at_40[0x10];
5470         u8         function_id[0x10];
5471
5472         u8         reserved_at_60[0x20];
5473 };
5474
5475 struct mlx5_ifc_detach_from_mcg_out_bits {
5476         u8         status[0x8];
5477         u8         reserved_at_8[0x18];
5478
5479         u8         syndrome[0x20];
5480
5481         u8         reserved_at_40[0x40];
5482 };
5483
5484 struct mlx5_ifc_detach_from_mcg_in_bits {
5485         u8         opcode[0x10];
5486         u8         reserved_at_10[0x10];
5487
5488         u8         reserved_at_20[0x10];
5489         u8         op_mod[0x10];
5490
5491         u8         reserved_at_40[0x8];
5492         u8         qpn[0x18];
5493
5494         u8         reserved_at_60[0x20];
5495
5496         u8         multicast_gid[16][0x8];
5497 };
5498
5499 struct mlx5_ifc_destroy_xrq_out_bits {
5500         u8         status[0x8];
5501         u8         reserved_at_8[0x18];
5502
5503         u8         syndrome[0x20];
5504
5505         u8         reserved_at_40[0x40];
5506 };
5507
5508 struct mlx5_ifc_destroy_xrq_in_bits {
5509         u8         opcode[0x10];
5510         u8         reserved_at_10[0x10];
5511
5512         u8         reserved_at_20[0x10];
5513         u8         op_mod[0x10];
5514
5515         u8         reserved_at_40[0x8];
5516         u8         xrqn[0x18];
5517
5518         u8         reserved_at_60[0x20];
5519 };
5520
5521 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524
5525         u8         syndrome[0x20];
5526
5527         u8         reserved_at_40[0x40];
5528 };
5529
5530 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5531         u8         opcode[0x10];
5532         u8         reserved_at_10[0x10];
5533
5534         u8         reserved_at_20[0x10];
5535         u8         op_mod[0x10];
5536
5537         u8         reserved_at_40[0x8];
5538         u8         xrc_srqn[0x18];
5539
5540         u8         reserved_at_60[0x20];
5541 };
5542
5543 struct mlx5_ifc_destroy_tis_out_bits {
5544         u8         status[0x8];
5545         u8         reserved_at_8[0x18];
5546
5547         u8         syndrome[0x20];
5548
5549         u8         reserved_at_40[0x40];
5550 };
5551
5552 struct mlx5_ifc_destroy_tis_in_bits {
5553         u8         opcode[0x10];
5554         u8         reserved_at_10[0x10];
5555
5556         u8         reserved_at_20[0x10];
5557         u8         op_mod[0x10];
5558
5559         u8         reserved_at_40[0x8];
5560         u8         tisn[0x18];
5561
5562         u8         reserved_at_60[0x20];
5563 };
5564
5565 struct mlx5_ifc_destroy_tir_out_bits {
5566         u8         status[0x8];
5567         u8         reserved_at_8[0x18];
5568
5569         u8         syndrome[0x20];
5570
5571         u8         reserved_at_40[0x40];
5572 };
5573
5574 struct mlx5_ifc_destroy_tir_in_bits {
5575         u8         opcode[0x10];
5576         u8         reserved_at_10[0x10];
5577
5578         u8         reserved_at_20[0x10];
5579         u8         op_mod[0x10];
5580
5581         u8         reserved_at_40[0x8];
5582         u8         tirn[0x18];
5583
5584         u8         reserved_at_60[0x20];
5585 };
5586
5587 struct mlx5_ifc_destroy_srq_out_bits {
5588         u8         status[0x8];
5589         u8         reserved_at_8[0x18];
5590
5591         u8         syndrome[0x20];
5592
5593         u8         reserved_at_40[0x40];
5594 };
5595
5596 struct mlx5_ifc_destroy_srq_in_bits {
5597         u8         opcode[0x10];
5598         u8         reserved_at_10[0x10];
5599
5600         u8         reserved_at_20[0x10];
5601         u8         op_mod[0x10];
5602
5603         u8         reserved_at_40[0x8];
5604         u8         srqn[0x18];
5605
5606         u8         reserved_at_60[0x20];
5607 };
5608
5609 struct mlx5_ifc_destroy_sq_out_bits {
5610         u8         status[0x8];
5611         u8         reserved_at_8[0x18];
5612
5613         u8         syndrome[0x20];
5614
5615         u8         reserved_at_40[0x40];
5616 };
5617
5618 struct mlx5_ifc_destroy_sq_in_bits {
5619         u8         opcode[0x10];
5620         u8         reserved_at_10[0x10];
5621
5622         u8         reserved_at_20[0x10];
5623         u8         op_mod[0x10];
5624
5625         u8         reserved_at_40[0x8];
5626         u8         sqn[0x18];
5627
5628         u8         reserved_at_60[0x20];
5629 };
5630
5631 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5632         u8         status[0x8];
5633         u8         reserved_at_8[0x18];
5634
5635         u8         syndrome[0x20];
5636
5637         u8         reserved_at_40[0x1c0];
5638 };
5639
5640 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5641         u8         opcode[0x10];
5642         u8         reserved_at_10[0x10];
5643
5644         u8         reserved_at_20[0x10];
5645         u8         op_mod[0x10];
5646
5647         u8         scheduling_hierarchy[0x8];
5648         u8         reserved_at_48[0x18];
5649
5650         u8         scheduling_element_id[0x20];
5651
5652         u8         reserved_at_80[0x180];
5653 };
5654
5655 struct mlx5_ifc_destroy_rqt_out_bits {
5656         u8         status[0x8];
5657         u8         reserved_at_8[0x18];
5658
5659         u8         syndrome[0x20];
5660
5661         u8         reserved_at_40[0x40];
5662 };
5663
5664 struct mlx5_ifc_destroy_rqt_in_bits {
5665         u8         opcode[0x10];
5666         u8         reserved_at_10[0x10];
5667
5668         u8         reserved_at_20[0x10];
5669         u8         op_mod[0x10];
5670
5671         u8         reserved_at_40[0x8];
5672         u8         rqtn[0x18];
5673
5674         u8         reserved_at_60[0x20];
5675 };
5676
5677 struct mlx5_ifc_destroy_rq_out_bits {
5678         u8         status[0x8];
5679         u8         reserved_at_8[0x18];
5680
5681         u8         syndrome[0x20];
5682
5683         u8         reserved_at_40[0x40];
5684 };
5685
5686 struct mlx5_ifc_destroy_rq_in_bits {
5687         u8         opcode[0x10];
5688         u8         reserved_at_10[0x10];
5689
5690         u8         reserved_at_20[0x10];
5691         u8         op_mod[0x10];
5692
5693         u8         reserved_at_40[0x8];
5694         u8         rqn[0x18];
5695
5696         u8         reserved_at_60[0x20];
5697 };
5698
5699 struct mlx5_ifc_destroy_rmp_out_bits {
5700         u8         status[0x8];
5701         u8         reserved_at_8[0x18];
5702
5703         u8         syndrome[0x20];
5704
5705         u8         reserved_at_40[0x40];
5706 };
5707
5708 struct mlx5_ifc_destroy_rmp_in_bits {
5709         u8         opcode[0x10];
5710         u8         reserved_at_10[0x10];
5711
5712         u8         reserved_at_20[0x10];
5713         u8         op_mod[0x10];
5714
5715         u8         reserved_at_40[0x8];
5716         u8         rmpn[0x18];
5717
5718         u8         reserved_at_60[0x20];
5719 };
5720
5721 struct mlx5_ifc_destroy_qp_out_bits {
5722         u8         status[0x8];
5723         u8         reserved_at_8[0x18];
5724
5725         u8         syndrome[0x20];
5726
5727         u8         reserved_at_40[0x40];
5728 };
5729
5730 struct mlx5_ifc_destroy_qp_in_bits {
5731         u8         opcode[0x10];
5732         u8         reserved_at_10[0x10];
5733
5734         u8         reserved_at_20[0x10];
5735         u8         op_mod[0x10];
5736
5737         u8         reserved_at_40[0x8];
5738         u8         qpn[0x18];
5739
5740         u8         reserved_at_60[0x20];
5741 };
5742
5743 struct mlx5_ifc_destroy_psv_out_bits {
5744         u8         status[0x8];
5745         u8         reserved_at_8[0x18];
5746
5747         u8         syndrome[0x20];
5748
5749         u8         reserved_at_40[0x40];
5750 };
5751
5752 struct mlx5_ifc_destroy_psv_in_bits {
5753         u8         opcode[0x10];
5754         u8         reserved_at_10[0x10];
5755
5756         u8         reserved_at_20[0x10];
5757         u8         op_mod[0x10];
5758
5759         u8         reserved_at_40[0x8];
5760         u8         psvn[0x18];
5761
5762         u8         reserved_at_60[0x20];
5763 };
5764
5765 struct mlx5_ifc_destroy_mkey_out_bits {
5766         u8         status[0x8];
5767         u8         reserved_at_8[0x18];
5768
5769         u8         syndrome[0x20];
5770
5771         u8         reserved_at_40[0x40];
5772 };
5773
5774 struct mlx5_ifc_destroy_mkey_in_bits {
5775         u8         opcode[0x10];
5776         u8         reserved_at_10[0x10];
5777
5778         u8         reserved_at_20[0x10];
5779         u8         op_mod[0x10];
5780
5781         u8         reserved_at_40[0x8];
5782         u8         mkey_index[0x18];
5783
5784         u8         reserved_at_60[0x20];
5785 };
5786
5787 struct mlx5_ifc_destroy_flow_table_out_bits {
5788         u8         status[0x8];
5789         u8         reserved_at_8[0x18];
5790
5791         u8         syndrome[0x20];
5792
5793         u8         reserved_at_40[0x40];
5794 };
5795
5796 struct mlx5_ifc_destroy_flow_table_in_bits {
5797         u8         opcode[0x10];
5798         u8         reserved_at_10[0x10];
5799
5800         u8         reserved_at_20[0x10];
5801         u8         op_mod[0x10];
5802
5803         u8         other_vport[0x1];
5804         u8         reserved_at_41[0xf];
5805         u8         vport_number[0x10];
5806
5807         u8         reserved_at_60[0x20];
5808
5809         u8         table_type[0x8];
5810         u8         reserved_at_88[0x18];
5811
5812         u8         reserved_at_a0[0x8];
5813         u8         table_id[0x18];
5814
5815         u8         reserved_at_c0[0x140];
5816 };
5817
5818 struct mlx5_ifc_destroy_flow_group_out_bits {
5819         u8         status[0x8];
5820         u8         reserved_at_8[0x18];
5821
5822         u8         syndrome[0x20];
5823
5824         u8         reserved_at_40[0x40];
5825 };
5826
5827 struct mlx5_ifc_destroy_flow_group_in_bits {
5828         u8         opcode[0x10];
5829         u8         reserved_at_10[0x10];
5830
5831         u8         reserved_at_20[0x10];
5832         u8         op_mod[0x10];
5833
5834         u8         other_vport[0x1];
5835         u8         reserved_at_41[0xf];
5836         u8         vport_number[0x10];
5837
5838         u8         reserved_at_60[0x20];
5839
5840         u8         table_type[0x8];
5841         u8         reserved_at_88[0x18];
5842
5843         u8         reserved_at_a0[0x8];
5844         u8         table_id[0x18];
5845
5846         u8         group_id[0x20];
5847
5848         u8         reserved_at_e0[0x120];
5849 };
5850
5851 struct mlx5_ifc_destroy_eq_out_bits {
5852         u8         status[0x8];
5853         u8         reserved_at_8[0x18];
5854
5855         u8         syndrome[0x20];
5856
5857         u8         reserved_at_40[0x40];
5858 };
5859
5860 struct mlx5_ifc_destroy_eq_in_bits {
5861         u8         opcode[0x10];
5862         u8         reserved_at_10[0x10];
5863
5864         u8         reserved_at_20[0x10];
5865         u8         op_mod[0x10];
5866
5867         u8         reserved_at_40[0x18];
5868         u8         eq_number[0x8];
5869
5870         u8         reserved_at_60[0x20];
5871 };
5872
5873 struct mlx5_ifc_destroy_dct_out_bits {
5874         u8         status[0x8];
5875         u8         reserved_at_8[0x18];
5876
5877         u8         syndrome[0x20];
5878
5879         u8         reserved_at_40[0x40];
5880 };
5881
5882 struct mlx5_ifc_destroy_dct_in_bits {
5883         u8         opcode[0x10];
5884         u8         reserved_at_10[0x10];
5885
5886         u8         reserved_at_20[0x10];
5887         u8         op_mod[0x10];
5888
5889         u8         reserved_at_40[0x8];
5890         u8         dctn[0x18];
5891
5892         u8         reserved_at_60[0x20];
5893 };
5894
5895 struct mlx5_ifc_destroy_cq_out_bits {
5896         u8         status[0x8];
5897         u8         reserved_at_8[0x18];
5898
5899         u8         syndrome[0x20];
5900
5901         u8         reserved_at_40[0x40];
5902 };
5903
5904 struct mlx5_ifc_destroy_cq_in_bits {
5905         u8         opcode[0x10];
5906         u8         reserved_at_10[0x10];
5907
5908         u8         reserved_at_20[0x10];
5909         u8         op_mod[0x10];
5910
5911         u8         reserved_at_40[0x8];
5912         u8         cqn[0x18];
5913
5914         u8         reserved_at_60[0x20];
5915 };
5916
5917 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5918         u8         status[0x8];
5919         u8         reserved_at_8[0x18];
5920
5921         u8         syndrome[0x20];
5922
5923         u8         reserved_at_40[0x40];
5924 };
5925
5926 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5927         u8         opcode[0x10];
5928         u8         reserved_at_10[0x10];
5929
5930         u8         reserved_at_20[0x10];
5931         u8         op_mod[0x10];
5932
5933         u8         reserved_at_40[0x20];
5934
5935         u8         reserved_at_60[0x10];
5936         u8         vxlan_udp_port[0x10];
5937 };
5938
5939 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5940         u8         status[0x8];
5941         u8         reserved_at_8[0x18];
5942
5943         u8         syndrome[0x20];
5944
5945         u8         reserved_at_40[0x40];
5946 };
5947
5948 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5949         u8         opcode[0x10];
5950         u8         reserved_at_10[0x10];
5951
5952         u8         reserved_at_20[0x10];
5953         u8         op_mod[0x10];
5954
5955         u8         reserved_at_40[0x60];
5956
5957         u8         reserved_at_a0[0x8];
5958         u8         table_index[0x18];
5959
5960         u8         reserved_at_c0[0x140];
5961 };
5962
5963 struct mlx5_ifc_delete_fte_out_bits {
5964         u8         status[0x8];
5965         u8         reserved_at_8[0x18];
5966
5967         u8         syndrome[0x20];
5968
5969         u8         reserved_at_40[0x40];
5970 };
5971
5972 struct mlx5_ifc_delete_fte_in_bits {
5973         u8         opcode[0x10];
5974         u8         reserved_at_10[0x10];
5975
5976         u8         reserved_at_20[0x10];
5977         u8         op_mod[0x10];
5978
5979         u8         other_vport[0x1];
5980         u8         reserved_at_41[0xf];
5981         u8         vport_number[0x10];
5982
5983         u8         reserved_at_60[0x20];
5984
5985         u8         table_type[0x8];
5986         u8         reserved_at_88[0x18];
5987
5988         u8         reserved_at_a0[0x8];
5989         u8         table_id[0x18];
5990
5991         u8         reserved_at_c0[0x40];
5992
5993         u8         flow_index[0x20];
5994
5995         u8         reserved_at_120[0xe0];
5996 };
5997
5998 struct mlx5_ifc_dealloc_xrcd_out_bits {
5999         u8         status[0x8];
6000         u8         reserved_at_8[0x18];
6001
6002         u8         syndrome[0x20];
6003
6004         u8         reserved_at_40[0x40];
6005 };
6006
6007 struct mlx5_ifc_dealloc_xrcd_in_bits {
6008         u8         opcode[0x10];
6009         u8         reserved_at_10[0x10];
6010
6011         u8         reserved_at_20[0x10];
6012         u8         op_mod[0x10];
6013
6014         u8         reserved_at_40[0x8];
6015         u8         xrcd[0x18];
6016
6017         u8         reserved_at_60[0x20];
6018 };
6019
6020 struct mlx5_ifc_dealloc_uar_out_bits {
6021         u8         status[0x8];
6022         u8         reserved_at_8[0x18];
6023
6024         u8         syndrome[0x20];
6025
6026         u8         reserved_at_40[0x40];
6027 };
6028
6029 struct mlx5_ifc_dealloc_uar_in_bits {
6030         u8         opcode[0x10];
6031         u8         reserved_at_10[0x10];
6032
6033         u8         reserved_at_20[0x10];
6034         u8         op_mod[0x10];
6035
6036         u8         reserved_at_40[0x8];
6037         u8         uar[0x18];
6038
6039         u8         reserved_at_60[0x20];
6040 };
6041
6042 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6043         u8         status[0x8];
6044         u8         reserved_at_8[0x18];
6045
6046         u8         syndrome[0x20];
6047
6048         u8         reserved_at_40[0x40];
6049 };
6050
6051 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6052         u8         opcode[0x10];
6053         u8         reserved_at_10[0x10];
6054
6055         u8         reserved_at_20[0x10];
6056         u8         op_mod[0x10];
6057
6058         u8         reserved_at_40[0x8];
6059         u8         transport_domain[0x18];
6060
6061         u8         reserved_at_60[0x20];
6062 };
6063
6064 struct mlx5_ifc_dealloc_q_counter_out_bits {
6065         u8         status[0x8];
6066         u8         reserved_at_8[0x18];
6067
6068         u8         syndrome[0x20];
6069
6070         u8         reserved_at_40[0x40];
6071 };
6072
6073 struct mlx5_ifc_dealloc_q_counter_in_bits {
6074         u8         opcode[0x10];
6075         u8         reserved_at_10[0x10];
6076
6077         u8         reserved_at_20[0x10];
6078         u8         op_mod[0x10];
6079
6080         u8         reserved_at_40[0x18];
6081         u8         counter_set_id[0x8];
6082
6083         u8         reserved_at_60[0x20];
6084 };
6085
6086 struct mlx5_ifc_dealloc_pd_out_bits {
6087         u8         status[0x8];
6088         u8         reserved_at_8[0x18];
6089
6090         u8         syndrome[0x20];
6091
6092         u8         reserved_at_40[0x40];
6093 };
6094
6095 struct mlx5_ifc_dealloc_pd_in_bits {
6096         u8         opcode[0x10];
6097         u8         reserved_at_10[0x10];
6098
6099         u8         reserved_at_20[0x10];
6100         u8         op_mod[0x10];
6101
6102         u8         reserved_at_40[0x8];
6103         u8         pd[0x18];
6104
6105         u8         reserved_at_60[0x20];
6106 };
6107
6108 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6109         u8         status[0x8];
6110         u8         reserved_at_8[0x18];
6111
6112         u8         syndrome[0x20];
6113
6114         u8         reserved_at_40[0x40];
6115 };
6116
6117 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6118         u8         opcode[0x10];
6119         u8         reserved_at_10[0x10];
6120
6121         u8         reserved_at_20[0x10];
6122         u8         op_mod[0x10];
6123
6124         u8         reserved_at_40[0x10];
6125         u8         flow_counter_id[0x10];
6126
6127         u8         reserved_at_60[0x20];
6128 };
6129
6130 struct mlx5_ifc_create_xrq_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_at_8[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_at_40[0x8];
6137         u8         xrqn[0x18];
6138
6139         u8         reserved_at_60[0x20];
6140 };
6141
6142 struct mlx5_ifc_create_xrq_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0x40];
6150
6151         struct mlx5_ifc_xrqc_bits xrq_context;
6152 };
6153
6154 struct mlx5_ifc_create_xrc_srq_out_bits {
6155         u8         status[0x8];
6156         u8         reserved_at_8[0x18];
6157
6158         u8         syndrome[0x20];
6159
6160         u8         reserved_at_40[0x8];
6161         u8         xrc_srqn[0x18];
6162
6163         u8         reserved_at_60[0x20];
6164 };
6165
6166 struct mlx5_ifc_create_xrc_srq_in_bits {
6167         u8         opcode[0x10];
6168         u8         reserved_at_10[0x10];
6169
6170         u8         reserved_at_20[0x10];
6171         u8         op_mod[0x10];
6172
6173         u8         reserved_at_40[0x40];
6174
6175         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6176
6177         u8         reserved_at_280[0x600];
6178
6179         u8         pas[0][0x40];
6180 };
6181
6182 struct mlx5_ifc_create_tis_out_bits {
6183         u8         status[0x8];
6184         u8         reserved_at_8[0x18];
6185
6186         u8         syndrome[0x20];
6187
6188         u8         reserved_at_40[0x8];
6189         u8         tisn[0x18];
6190
6191         u8         reserved_at_60[0x20];
6192 };
6193
6194 struct mlx5_ifc_create_tis_in_bits {
6195         u8         opcode[0x10];
6196         u8         reserved_at_10[0x10];
6197
6198         u8         reserved_at_20[0x10];
6199         u8         op_mod[0x10];
6200
6201         u8         reserved_at_40[0xc0];
6202
6203         struct mlx5_ifc_tisc_bits ctx;
6204 };
6205
6206 struct mlx5_ifc_create_tir_out_bits {
6207         u8         status[0x8];
6208         u8         reserved_at_8[0x18];
6209
6210         u8         syndrome[0x20];
6211
6212         u8         reserved_at_40[0x8];
6213         u8         tirn[0x18];
6214
6215         u8         reserved_at_60[0x20];
6216 };
6217
6218 struct mlx5_ifc_create_tir_in_bits {
6219         u8         opcode[0x10];
6220         u8         reserved_at_10[0x10];
6221
6222         u8         reserved_at_20[0x10];
6223         u8         op_mod[0x10];
6224
6225         u8         reserved_at_40[0xc0];
6226
6227         struct mlx5_ifc_tirc_bits ctx;
6228 };
6229
6230 struct mlx5_ifc_create_srq_out_bits {
6231         u8         status[0x8];
6232         u8         reserved_at_8[0x18];
6233
6234         u8         syndrome[0x20];
6235
6236         u8         reserved_at_40[0x8];
6237         u8         srqn[0x18];
6238
6239         u8         reserved_at_60[0x20];
6240 };
6241
6242 struct mlx5_ifc_create_srq_in_bits {
6243         u8         opcode[0x10];
6244         u8         reserved_at_10[0x10];
6245
6246         u8         reserved_at_20[0x10];
6247         u8         op_mod[0x10];
6248
6249         u8         reserved_at_40[0x40];
6250
6251         struct mlx5_ifc_srqc_bits srq_context_entry;
6252
6253         u8         reserved_at_280[0x600];
6254
6255         u8         pas[0][0x40];
6256 };
6257
6258 struct mlx5_ifc_create_sq_out_bits {
6259         u8         status[0x8];
6260         u8         reserved_at_8[0x18];
6261
6262         u8         syndrome[0x20];
6263
6264         u8         reserved_at_40[0x8];
6265         u8         sqn[0x18];
6266
6267         u8         reserved_at_60[0x20];
6268 };
6269
6270 struct mlx5_ifc_create_sq_in_bits {
6271         u8         opcode[0x10];
6272         u8         reserved_at_10[0x10];
6273
6274         u8         reserved_at_20[0x10];
6275         u8         op_mod[0x10];
6276
6277         u8         reserved_at_40[0xc0];
6278
6279         struct mlx5_ifc_sqc_bits ctx;
6280 };
6281
6282 struct mlx5_ifc_create_scheduling_element_out_bits {
6283         u8         status[0x8];
6284         u8         reserved_at_8[0x18];
6285
6286         u8         syndrome[0x20];
6287
6288         u8         reserved_at_40[0x40];
6289
6290         u8         scheduling_element_id[0x20];
6291
6292         u8         reserved_at_a0[0x160];
6293 };
6294
6295 struct mlx5_ifc_create_scheduling_element_in_bits {
6296         u8         opcode[0x10];
6297         u8         reserved_at_10[0x10];
6298
6299         u8         reserved_at_20[0x10];
6300         u8         op_mod[0x10];
6301
6302         u8         scheduling_hierarchy[0x8];
6303         u8         reserved_at_48[0x18];
6304
6305         u8         reserved_at_60[0xa0];
6306
6307         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6308
6309         u8         reserved_at_300[0x100];
6310 };
6311
6312 struct mlx5_ifc_create_rqt_out_bits {
6313         u8         status[0x8];
6314         u8         reserved_at_8[0x18];
6315
6316         u8         syndrome[0x20];
6317
6318         u8         reserved_at_40[0x8];
6319         u8         rqtn[0x18];
6320
6321         u8         reserved_at_60[0x20];
6322 };
6323
6324 struct mlx5_ifc_create_rqt_in_bits {
6325         u8         opcode[0x10];
6326         u8         reserved_at_10[0x10];
6327
6328         u8         reserved_at_20[0x10];
6329         u8         op_mod[0x10];
6330
6331         u8         reserved_at_40[0xc0];
6332
6333         struct mlx5_ifc_rqtc_bits rqt_context;
6334 };
6335
6336 struct mlx5_ifc_create_rq_out_bits {
6337         u8         status[0x8];
6338         u8         reserved_at_8[0x18];
6339
6340         u8         syndrome[0x20];
6341
6342         u8         reserved_at_40[0x8];
6343         u8         rqn[0x18];
6344
6345         u8         reserved_at_60[0x20];
6346 };
6347
6348 struct mlx5_ifc_create_rq_in_bits {
6349         u8         opcode[0x10];
6350         u8         reserved_at_10[0x10];
6351
6352         u8         reserved_at_20[0x10];
6353         u8         op_mod[0x10];
6354
6355         u8         reserved_at_40[0xc0];
6356
6357         struct mlx5_ifc_rqc_bits ctx;
6358 };
6359
6360 struct mlx5_ifc_create_rmp_out_bits {
6361         u8         status[0x8];
6362         u8         reserved_at_8[0x18];
6363
6364         u8         syndrome[0x20];
6365
6366         u8         reserved_at_40[0x8];
6367         u8         rmpn[0x18];
6368
6369         u8         reserved_at_60[0x20];
6370 };
6371
6372 struct mlx5_ifc_create_rmp_in_bits {
6373         u8         opcode[0x10];
6374         u8         reserved_at_10[0x10];
6375
6376         u8         reserved_at_20[0x10];
6377         u8         op_mod[0x10];
6378
6379         u8         reserved_at_40[0xc0];
6380
6381         struct mlx5_ifc_rmpc_bits ctx;
6382 };
6383
6384 struct mlx5_ifc_create_qp_out_bits {
6385         u8         status[0x8];
6386         u8         reserved_at_8[0x18];
6387
6388         u8         syndrome[0x20];
6389
6390         u8         reserved_at_40[0x8];
6391         u8         qpn[0x18];
6392
6393         u8         reserved_at_60[0x20];
6394 };
6395
6396 struct mlx5_ifc_create_qp_in_bits {
6397         u8         opcode[0x10];
6398         u8         reserved_at_10[0x10];
6399
6400         u8         reserved_at_20[0x10];
6401         u8         op_mod[0x10];
6402
6403         u8         reserved_at_40[0x40];
6404
6405         u8         opt_param_mask[0x20];
6406
6407         u8         reserved_at_a0[0x20];
6408
6409         struct mlx5_ifc_qpc_bits qpc;
6410
6411         u8         reserved_at_800[0x80];
6412
6413         u8         pas[0][0x40];
6414 };
6415
6416 struct mlx5_ifc_create_psv_out_bits {
6417         u8         status[0x8];
6418         u8         reserved_at_8[0x18];
6419
6420         u8         syndrome[0x20];
6421
6422         u8         reserved_at_40[0x40];
6423
6424         u8         reserved_at_80[0x8];
6425         u8         psv0_index[0x18];
6426
6427         u8         reserved_at_a0[0x8];
6428         u8         psv1_index[0x18];
6429
6430         u8         reserved_at_c0[0x8];
6431         u8         psv2_index[0x18];
6432
6433         u8         reserved_at_e0[0x8];
6434         u8         psv3_index[0x18];
6435 };
6436
6437 struct mlx5_ifc_create_psv_in_bits {
6438         u8         opcode[0x10];
6439         u8         reserved_at_10[0x10];
6440
6441         u8         reserved_at_20[0x10];
6442         u8         op_mod[0x10];
6443
6444         u8         num_psv[0x4];
6445         u8         reserved_at_44[0x4];
6446         u8         pd[0x18];
6447
6448         u8         reserved_at_60[0x20];
6449 };
6450
6451 struct mlx5_ifc_create_mkey_out_bits {
6452         u8         status[0x8];
6453         u8         reserved_at_8[0x18];
6454
6455         u8         syndrome[0x20];
6456
6457         u8         reserved_at_40[0x8];
6458         u8         mkey_index[0x18];
6459
6460         u8         reserved_at_60[0x20];
6461 };
6462
6463 struct mlx5_ifc_create_mkey_in_bits {
6464         u8         opcode[0x10];
6465         u8         reserved_at_10[0x10];
6466
6467         u8         reserved_at_20[0x10];
6468         u8         op_mod[0x10];
6469
6470         u8         reserved_at_40[0x20];
6471
6472         u8         pg_access[0x1];
6473         u8         reserved_at_61[0x1f];
6474
6475         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6476
6477         u8         reserved_at_280[0x80];
6478
6479         u8         translations_octword_actual_size[0x20];
6480
6481         u8         reserved_at_320[0x560];
6482
6483         u8         klm_pas_mtt[0][0x20];
6484 };
6485
6486 struct mlx5_ifc_create_flow_table_out_bits {
6487         u8         status[0x8];
6488         u8         reserved_at_8[0x18];
6489
6490         u8         syndrome[0x20];
6491
6492         u8         reserved_at_40[0x8];
6493         u8         table_id[0x18];
6494
6495         u8         reserved_at_60[0x20];
6496 };
6497
6498 struct mlx5_ifc_create_flow_table_in_bits {
6499         u8         opcode[0x10];
6500         u8         reserved_at_10[0x10];
6501
6502         u8         reserved_at_20[0x10];
6503         u8         op_mod[0x10];
6504
6505         u8         other_vport[0x1];
6506         u8         reserved_at_41[0xf];
6507         u8         vport_number[0x10];
6508
6509         u8         reserved_at_60[0x20];
6510
6511         u8         table_type[0x8];
6512         u8         reserved_at_88[0x18];
6513
6514         u8         reserved_at_a0[0x20];
6515
6516         u8         encap_en[0x1];
6517         u8         decap_en[0x1];
6518         u8         reserved_at_c2[0x2];
6519         u8         table_miss_mode[0x4];
6520         u8         level[0x8];
6521         u8         reserved_at_d0[0x8];
6522         u8         log_size[0x8];
6523
6524         u8         reserved_at_e0[0x8];
6525         u8         table_miss_id[0x18];
6526
6527         u8         reserved_at_100[0x8];
6528         u8         lag_master_next_table_id[0x18];
6529
6530         u8         reserved_at_120[0x80];
6531 };
6532
6533 struct mlx5_ifc_create_flow_group_out_bits {
6534         u8         status[0x8];
6535         u8         reserved_at_8[0x18];
6536
6537         u8         syndrome[0x20];
6538
6539         u8         reserved_at_40[0x8];
6540         u8         group_id[0x18];
6541
6542         u8         reserved_at_60[0x20];
6543 };
6544
6545 enum {
6546         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6547         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6548         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6549 };
6550
6551 struct mlx5_ifc_create_flow_group_in_bits {
6552         u8         opcode[0x10];
6553         u8         reserved_at_10[0x10];
6554
6555         u8         reserved_at_20[0x10];
6556         u8         op_mod[0x10];
6557
6558         u8         other_vport[0x1];
6559         u8         reserved_at_41[0xf];
6560         u8         vport_number[0x10];
6561
6562         u8         reserved_at_60[0x20];
6563
6564         u8         table_type[0x8];
6565         u8         reserved_at_88[0x18];
6566
6567         u8         reserved_at_a0[0x8];
6568         u8         table_id[0x18];
6569
6570         u8         reserved_at_c0[0x20];
6571
6572         u8         start_flow_index[0x20];
6573
6574         u8         reserved_at_100[0x20];
6575
6576         u8         end_flow_index[0x20];
6577
6578         u8         reserved_at_140[0xa0];
6579
6580         u8         reserved_at_1e0[0x18];
6581         u8         match_criteria_enable[0x8];
6582
6583         struct mlx5_ifc_fte_match_param_bits match_criteria;
6584
6585         u8         reserved_at_1200[0xe00];
6586 };
6587
6588 struct mlx5_ifc_create_eq_out_bits {
6589         u8         status[0x8];
6590         u8         reserved_at_8[0x18];
6591
6592         u8         syndrome[0x20];
6593
6594         u8         reserved_at_40[0x18];
6595         u8         eq_number[0x8];
6596
6597         u8         reserved_at_60[0x20];
6598 };
6599
6600 struct mlx5_ifc_create_eq_in_bits {
6601         u8         opcode[0x10];
6602         u8         reserved_at_10[0x10];
6603
6604         u8         reserved_at_20[0x10];
6605         u8         op_mod[0x10];
6606
6607         u8         reserved_at_40[0x40];
6608
6609         struct mlx5_ifc_eqc_bits eq_context_entry;
6610
6611         u8         reserved_at_280[0x40];
6612
6613         u8         event_bitmask[0x40];
6614
6615         u8         reserved_at_300[0x580];
6616
6617         u8         pas[0][0x40];
6618 };
6619
6620 struct mlx5_ifc_create_dct_out_bits {
6621         u8         status[0x8];
6622         u8         reserved_at_8[0x18];
6623
6624         u8         syndrome[0x20];
6625
6626         u8         reserved_at_40[0x8];
6627         u8         dctn[0x18];
6628
6629         u8         reserved_at_60[0x20];
6630 };
6631
6632 struct mlx5_ifc_create_dct_in_bits {
6633         u8         opcode[0x10];
6634         u8         reserved_at_10[0x10];
6635
6636         u8         reserved_at_20[0x10];
6637         u8         op_mod[0x10];
6638
6639         u8         reserved_at_40[0x40];
6640
6641         struct mlx5_ifc_dctc_bits dct_context_entry;
6642
6643         u8         reserved_at_280[0x180];
6644 };
6645
6646 struct mlx5_ifc_create_cq_out_bits {
6647         u8         status[0x8];
6648         u8         reserved_at_8[0x18];
6649
6650         u8         syndrome[0x20];
6651
6652         u8         reserved_at_40[0x8];
6653         u8         cqn[0x18];
6654
6655         u8         reserved_at_60[0x20];
6656 };
6657
6658 struct mlx5_ifc_create_cq_in_bits {
6659         u8         opcode[0x10];
6660         u8         reserved_at_10[0x10];
6661
6662         u8         reserved_at_20[0x10];
6663         u8         op_mod[0x10];
6664
6665         u8         reserved_at_40[0x40];
6666
6667         struct mlx5_ifc_cqc_bits cq_context;
6668
6669         u8         reserved_at_280[0x600];
6670
6671         u8         pas[0][0x40];
6672 };
6673
6674 struct mlx5_ifc_config_int_moderation_out_bits {
6675         u8         status[0x8];
6676         u8         reserved_at_8[0x18];
6677
6678         u8         syndrome[0x20];
6679
6680         u8         reserved_at_40[0x4];
6681         u8         min_delay[0xc];
6682         u8         int_vector[0x10];
6683
6684         u8         reserved_at_60[0x20];
6685 };
6686
6687 enum {
6688         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6689         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6690 };
6691
6692 struct mlx5_ifc_config_int_moderation_in_bits {
6693         u8         opcode[0x10];
6694         u8         reserved_at_10[0x10];
6695
6696         u8         reserved_at_20[0x10];
6697         u8         op_mod[0x10];
6698
6699         u8         reserved_at_40[0x4];
6700         u8         min_delay[0xc];
6701         u8         int_vector[0x10];
6702
6703         u8         reserved_at_60[0x20];
6704 };
6705
6706 struct mlx5_ifc_attach_to_mcg_out_bits {
6707         u8         status[0x8];
6708         u8         reserved_at_8[0x18];
6709
6710         u8         syndrome[0x20];
6711
6712         u8         reserved_at_40[0x40];
6713 };
6714
6715 struct mlx5_ifc_attach_to_mcg_in_bits {
6716         u8         opcode[0x10];
6717         u8         reserved_at_10[0x10];
6718
6719         u8         reserved_at_20[0x10];
6720         u8         op_mod[0x10];
6721
6722         u8         reserved_at_40[0x8];
6723         u8         qpn[0x18];
6724
6725         u8         reserved_at_60[0x20];
6726
6727         u8         multicast_gid[16][0x8];
6728 };
6729
6730 struct mlx5_ifc_arm_xrq_out_bits {
6731         u8         status[0x8];
6732         u8         reserved_at_8[0x18];
6733
6734         u8         syndrome[0x20];
6735
6736         u8         reserved_at_40[0x40];
6737 };
6738
6739 struct mlx5_ifc_arm_xrq_in_bits {
6740         u8         opcode[0x10];
6741         u8         reserved_at_10[0x10];
6742
6743         u8         reserved_at_20[0x10];
6744         u8         op_mod[0x10];
6745
6746         u8         reserved_at_40[0x8];
6747         u8         xrqn[0x18];
6748
6749         u8         reserved_at_60[0x10];
6750         u8         lwm[0x10];
6751 };
6752
6753 struct mlx5_ifc_arm_xrc_srq_out_bits {
6754         u8         status[0x8];
6755         u8         reserved_at_8[0x18];
6756
6757         u8         syndrome[0x20];
6758
6759         u8         reserved_at_40[0x40];
6760 };
6761
6762 enum {
6763         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6764 };
6765
6766 struct mlx5_ifc_arm_xrc_srq_in_bits {
6767         u8         opcode[0x10];
6768         u8         reserved_at_10[0x10];
6769
6770         u8         reserved_at_20[0x10];
6771         u8         op_mod[0x10];
6772
6773         u8         reserved_at_40[0x8];
6774         u8         xrc_srqn[0x18];
6775
6776         u8         reserved_at_60[0x10];
6777         u8         lwm[0x10];
6778 };
6779
6780 struct mlx5_ifc_arm_rq_out_bits {
6781         u8         status[0x8];
6782         u8         reserved_at_8[0x18];
6783
6784         u8         syndrome[0x20];
6785
6786         u8         reserved_at_40[0x40];
6787 };
6788
6789 enum {
6790         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6791         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6792 };
6793
6794 struct mlx5_ifc_arm_rq_in_bits {
6795         u8         opcode[0x10];
6796         u8         reserved_at_10[0x10];
6797
6798         u8         reserved_at_20[0x10];
6799         u8         op_mod[0x10];
6800
6801         u8         reserved_at_40[0x8];
6802         u8         srq_number[0x18];
6803
6804         u8         reserved_at_60[0x10];
6805         u8         lwm[0x10];
6806 };
6807
6808 struct mlx5_ifc_arm_dct_out_bits {
6809         u8         status[0x8];
6810         u8         reserved_at_8[0x18];
6811
6812         u8         syndrome[0x20];
6813
6814         u8         reserved_at_40[0x40];
6815 };
6816
6817 struct mlx5_ifc_arm_dct_in_bits {
6818         u8         opcode[0x10];
6819         u8         reserved_at_10[0x10];
6820
6821         u8         reserved_at_20[0x10];
6822         u8         op_mod[0x10];
6823
6824         u8         reserved_at_40[0x8];
6825         u8         dct_number[0x18];
6826
6827         u8         reserved_at_60[0x20];
6828 };
6829
6830 struct mlx5_ifc_alloc_xrcd_out_bits {
6831         u8         status[0x8];
6832         u8         reserved_at_8[0x18];
6833
6834         u8         syndrome[0x20];
6835
6836         u8         reserved_at_40[0x8];
6837         u8         xrcd[0x18];
6838
6839         u8         reserved_at_60[0x20];
6840 };
6841
6842 struct mlx5_ifc_alloc_xrcd_in_bits {
6843         u8         opcode[0x10];
6844         u8         reserved_at_10[0x10];
6845
6846         u8         reserved_at_20[0x10];
6847         u8         op_mod[0x10];
6848
6849         u8         reserved_at_40[0x40];
6850 };
6851
6852 struct mlx5_ifc_alloc_uar_out_bits {
6853         u8         status[0x8];
6854         u8         reserved_at_8[0x18];
6855
6856         u8         syndrome[0x20];
6857
6858         u8         reserved_at_40[0x8];
6859         u8         uar[0x18];
6860
6861         u8         reserved_at_60[0x20];
6862 };
6863
6864 struct mlx5_ifc_alloc_uar_in_bits {
6865         u8         opcode[0x10];
6866         u8         reserved_at_10[0x10];
6867
6868         u8         reserved_at_20[0x10];
6869         u8         op_mod[0x10];
6870
6871         u8         reserved_at_40[0x40];
6872 };
6873
6874 struct mlx5_ifc_alloc_transport_domain_out_bits {
6875         u8         status[0x8];
6876         u8         reserved_at_8[0x18];
6877
6878         u8         syndrome[0x20];
6879
6880         u8         reserved_at_40[0x8];
6881         u8         transport_domain[0x18];
6882
6883         u8         reserved_at_60[0x20];
6884 };
6885
6886 struct mlx5_ifc_alloc_transport_domain_in_bits {
6887         u8         opcode[0x10];
6888         u8         reserved_at_10[0x10];
6889
6890         u8         reserved_at_20[0x10];
6891         u8         op_mod[0x10];
6892
6893         u8         reserved_at_40[0x40];
6894 };
6895
6896 struct mlx5_ifc_alloc_q_counter_out_bits {
6897         u8         status[0x8];
6898         u8         reserved_at_8[0x18];
6899
6900         u8         syndrome[0x20];
6901
6902         u8         reserved_at_40[0x18];
6903         u8         counter_set_id[0x8];
6904
6905         u8         reserved_at_60[0x20];
6906 };
6907
6908 struct mlx5_ifc_alloc_q_counter_in_bits {
6909         u8         opcode[0x10];
6910         u8         reserved_at_10[0x10];
6911
6912         u8         reserved_at_20[0x10];
6913         u8         op_mod[0x10];
6914
6915         u8         reserved_at_40[0x40];
6916 };
6917
6918 struct mlx5_ifc_alloc_pd_out_bits {
6919         u8         status[0x8];
6920         u8         reserved_at_8[0x18];
6921
6922         u8         syndrome[0x20];
6923
6924         u8         reserved_at_40[0x8];
6925         u8         pd[0x18];
6926
6927         u8         reserved_at_60[0x20];
6928 };
6929
6930 struct mlx5_ifc_alloc_pd_in_bits {
6931         u8         opcode[0x10];
6932         u8         reserved_at_10[0x10];
6933
6934         u8         reserved_at_20[0x10];
6935         u8         op_mod[0x10];
6936
6937         u8         reserved_at_40[0x40];
6938 };
6939
6940 struct mlx5_ifc_alloc_flow_counter_out_bits {
6941         u8         status[0x8];
6942         u8         reserved_at_8[0x18];
6943
6944         u8         syndrome[0x20];
6945
6946         u8         reserved_at_40[0x10];
6947         u8         flow_counter_id[0x10];
6948
6949         u8         reserved_at_60[0x20];
6950 };
6951
6952 struct mlx5_ifc_alloc_flow_counter_in_bits {
6953         u8         opcode[0x10];
6954         u8         reserved_at_10[0x10];
6955
6956         u8         reserved_at_20[0x10];
6957         u8         op_mod[0x10];
6958
6959         u8         reserved_at_40[0x40];
6960 };
6961
6962 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6963         u8         status[0x8];
6964         u8         reserved_at_8[0x18];
6965
6966         u8         syndrome[0x20];
6967
6968         u8         reserved_at_40[0x40];
6969 };
6970
6971 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6972         u8         opcode[0x10];
6973         u8         reserved_at_10[0x10];
6974
6975         u8         reserved_at_20[0x10];
6976         u8         op_mod[0x10];
6977
6978         u8         reserved_at_40[0x20];
6979
6980         u8         reserved_at_60[0x10];
6981         u8         vxlan_udp_port[0x10];
6982 };
6983
6984 struct mlx5_ifc_set_rate_limit_out_bits {
6985         u8         status[0x8];
6986         u8         reserved_at_8[0x18];
6987
6988         u8         syndrome[0x20];
6989
6990         u8         reserved_at_40[0x40];
6991 };
6992
6993 struct mlx5_ifc_set_rate_limit_in_bits {
6994         u8         opcode[0x10];
6995         u8         reserved_at_10[0x10];
6996
6997         u8         reserved_at_20[0x10];
6998         u8         op_mod[0x10];
6999
7000         u8         reserved_at_40[0x10];
7001         u8         rate_limit_index[0x10];
7002
7003         u8         reserved_at_60[0x20];
7004
7005         u8         rate_limit[0x20];
7006 };
7007
7008 struct mlx5_ifc_access_register_out_bits {
7009         u8         status[0x8];
7010         u8         reserved_at_8[0x18];
7011
7012         u8         syndrome[0x20];
7013
7014         u8         reserved_at_40[0x40];
7015
7016         u8         register_data[0][0x20];
7017 };
7018
7019 enum {
7020         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7021         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7022 };
7023
7024 struct mlx5_ifc_access_register_in_bits {
7025         u8         opcode[0x10];
7026         u8         reserved_at_10[0x10];
7027
7028         u8         reserved_at_20[0x10];
7029         u8         op_mod[0x10];
7030
7031         u8         reserved_at_40[0x10];
7032         u8         register_id[0x10];
7033
7034         u8         argument[0x20];
7035
7036         u8         register_data[0][0x20];
7037 };
7038
7039 struct mlx5_ifc_sltp_reg_bits {
7040         u8         status[0x4];
7041         u8         version[0x4];
7042         u8         local_port[0x8];
7043         u8         pnat[0x2];
7044         u8         reserved_at_12[0x2];
7045         u8         lane[0x4];
7046         u8         reserved_at_18[0x8];
7047
7048         u8         reserved_at_20[0x20];
7049
7050         u8         reserved_at_40[0x7];
7051         u8         polarity[0x1];
7052         u8         ob_tap0[0x8];
7053         u8         ob_tap1[0x8];
7054         u8         ob_tap2[0x8];
7055
7056         u8         reserved_at_60[0xc];
7057         u8         ob_preemp_mode[0x4];
7058         u8         ob_reg[0x8];
7059         u8         ob_bias[0x8];
7060
7061         u8         reserved_at_80[0x20];
7062 };
7063
7064 struct mlx5_ifc_slrg_reg_bits {
7065         u8         status[0x4];
7066         u8         version[0x4];
7067         u8         local_port[0x8];
7068         u8         pnat[0x2];
7069         u8         reserved_at_12[0x2];
7070         u8         lane[0x4];
7071         u8         reserved_at_18[0x8];
7072
7073         u8         time_to_link_up[0x10];
7074         u8         reserved_at_30[0xc];
7075         u8         grade_lane_speed[0x4];
7076
7077         u8         grade_version[0x8];
7078         u8         grade[0x18];
7079
7080         u8         reserved_at_60[0x4];
7081         u8         height_grade_type[0x4];
7082         u8         height_grade[0x18];
7083
7084         u8         height_dz[0x10];
7085         u8         height_dv[0x10];
7086
7087         u8         reserved_at_a0[0x10];
7088         u8         height_sigma[0x10];
7089
7090         u8         reserved_at_c0[0x20];
7091
7092         u8         reserved_at_e0[0x4];
7093         u8         phase_grade_type[0x4];
7094         u8         phase_grade[0x18];
7095
7096         u8         reserved_at_100[0x8];
7097         u8         phase_eo_pos[0x8];
7098         u8         reserved_at_110[0x8];
7099         u8         phase_eo_neg[0x8];
7100
7101         u8         ffe_set_tested[0x10];
7102         u8         test_errors_per_lane[0x10];
7103 };
7104
7105 struct mlx5_ifc_pvlc_reg_bits {
7106         u8         reserved_at_0[0x8];
7107         u8         local_port[0x8];
7108         u8         reserved_at_10[0x10];
7109
7110         u8         reserved_at_20[0x1c];
7111         u8         vl_hw_cap[0x4];
7112
7113         u8         reserved_at_40[0x1c];
7114         u8         vl_admin[0x4];
7115
7116         u8         reserved_at_60[0x1c];
7117         u8         vl_operational[0x4];
7118 };
7119
7120 struct mlx5_ifc_pude_reg_bits {
7121         u8         swid[0x8];
7122         u8         local_port[0x8];
7123         u8         reserved_at_10[0x4];
7124         u8         admin_status[0x4];
7125         u8         reserved_at_18[0x4];
7126         u8         oper_status[0x4];
7127
7128         u8         reserved_at_20[0x60];
7129 };
7130
7131 struct mlx5_ifc_ptys_reg_bits {
7132         u8         reserved_at_0[0x1];
7133         u8         an_disable_admin[0x1];
7134         u8         an_disable_cap[0x1];
7135         u8         reserved_at_3[0x5];
7136         u8         local_port[0x8];
7137         u8         reserved_at_10[0xd];
7138         u8         proto_mask[0x3];
7139
7140         u8         an_status[0x4];
7141         u8         reserved_at_24[0x3c];
7142
7143         u8         eth_proto_capability[0x20];
7144
7145         u8         ib_link_width_capability[0x10];
7146         u8         ib_proto_capability[0x10];
7147
7148         u8         reserved_at_a0[0x20];
7149
7150         u8         eth_proto_admin[0x20];
7151
7152         u8         ib_link_width_admin[0x10];
7153         u8         ib_proto_admin[0x10];
7154
7155         u8         reserved_at_100[0x20];
7156
7157         u8         eth_proto_oper[0x20];
7158
7159         u8         ib_link_width_oper[0x10];
7160         u8         ib_proto_oper[0x10];
7161
7162         u8         reserved_at_160[0x20];
7163
7164         u8         eth_proto_lp_advertise[0x20];
7165
7166         u8         reserved_at_1a0[0x60];
7167 };
7168
7169 struct mlx5_ifc_mlcr_reg_bits {
7170         u8         reserved_at_0[0x8];
7171         u8         local_port[0x8];
7172         u8         reserved_at_10[0x20];
7173
7174         u8         beacon_duration[0x10];
7175         u8         reserved_at_40[0x10];
7176
7177         u8         beacon_remain[0x10];
7178 };
7179
7180 struct mlx5_ifc_ptas_reg_bits {
7181         u8         reserved_at_0[0x20];
7182
7183         u8         algorithm_options[0x10];
7184         u8         reserved_at_30[0x4];
7185         u8         repetitions_mode[0x4];
7186         u8         num_of_repetitions[0x8];
7187
7188         u8         grade_version[0x8];
7189         u8         height_grade_type[0x4];
7190         u8         phase_grade_type[0x4];
7191         u8         height_grade_weight[0x8];
7192         u8         phase_grade_weight[0x8];
7193
7194         u8         gisim_measure_bits[0x10];
7195         u8         adaptive_tap_measure_bits[0x10];
7196
7197         u8         ber_bath_high_error_threshold[0x10];
7198         u8         ber_bath_mid_error_threshold[0x10];
7199
7200         u8         ber_bath_low_error_threshold[0x10];
7201         u8         one_ratio_high_threshold[0x10];
7202
7203         u8         one_ratio_high_mid_threshold[0x10];
7204         u8         one_ratio_low_mid_threshold[0x10];
7205
7206         u8         one_ratio_low_threshold[0x10];
7207         u8         ndeo_error_threshold[0x10];
7208
7209         u8         mixer_offset_step_size[0x10];
7210         u8         reserved_at_110[0x8];
7211         u8         mix90_phase_for_voltage_bath[0x8];
7212
7213         u8         mixer_offset_start[0x10];
7214         u8         mixer_offset_end[0x10];
7215
7216         u8         reserved_at_140[0x15];
7217         u8         ber_test_time[0xb];
7218 };
7219
7220 struct mlx5_ifc_pspa_reg_bits {
7221         u8         swid[0x8];
7222         u8         local_port[0x8];
7223         u8         sub_port[0x8];
7224         u8         reserved_at_18[0x8];
7225
7226         u8         reserved_at_20[0x20];
7227 };
7228
7229 struct mlx5_ifc_pqdr_reg_bits {
7230         u8         reserved_at_0[0x8];
7231         u8         local_port[0x8];
7232         u8         reserved_at_10[0x5];
7233         u8         prio[0x3];
7234         u8         reserved_at_18[0x6];
7235         u8         mode[0x2];
7236
7237         u8         reserved_at_20[0x20];
7238
7239         u8         reserved_at_40[0x10];
7240         u8         min_threshold[0x10];
7241
7242         u8         reserved_at_60[0x10];
7243         u8         max_threshold[0x10];
7244
7245         u8         reserved_at_80[0x10];
7246         u8         mark_probability_denominator[0x10];
7247
7248         u8         reserved_at_a0[0x60];
7249 };
7250
7251 struct mlx5_ifc_ppsc_reg_bits {
7252         u8         reserved_at_0[0x8];
7253         u8         local_port[0x8];
7254         u8         reserved_at_10[0x10];
7255
7256         u8         reserved_at_20[0x60];
7257
7258         u8         reserved_at_80[0x1c];
7259         u8         wrps_admin[0x4];
7260
7261         u8         reserved_at_a0[0x1c];
7262         u8         wrps_status[0x4];
7263
7264         u8         reserved_at_c0[0x8];
7265         u8         up_threshold[0x8];
7266         u8         reserved_at_d0[0x8];
7267         u8         down_threshold[0x8];
7268
7269         u8         reserved_at_e0[0x20];
7270
7271         u8         reserved_at_100[0x1c];
7272         u8         srps_admin[0x4];
7273
7274         u8         reserved_at_120[0x1c];
7275         u8         srps_status[0x4];
7276
7277         u8         reserved_at_140[0x40];
7278 };
7279
7280 struct mlx5_ifc_pplr_reg_bits {
7281         u8         reserved_at_0[0x8];
7282         u8         local_port[0x8];
7283         u8         reserved_at_10[0x10];
7284
7285         u8         reserved_at_20[0x8];
7286         u8         lb_cap[0x8];
7287         u8         reserved_at_30[0x8];
7288         u8         lb_en[0x8];
7289 };
7290
7291 struct mlx5_ifc_pplm_reg_bits {
7292         u8         reserved_at_0[0x8];
7293         u8         local_port[0x8];
7294         u8         reserved_at_10[0x10];
7295
7296         u8         reserved_at_20[0x20];
7297
7298         u8         port_profile_mode[0x8];
7299         u8         static_port_profile[0x8];
7300         u8         active_port_profile[0x8];
7301         u8         reserved_at_58[0x8];
7302
7303         u8         retransmission_active[0x8];
7304         u8         fec_mode_active[0x18];
7305
7306         u8         reserved_at_80[0x20];
7307 };
7308
7309 struct mlx5_ifc_ppcnt_reg_bits {
7310         u8         swid[0x8];
7311         u8         local_port[0x8];
7312         u8         pnat[0x2];
7313         u8         reserved_at_12[0x8];
7314         u8         grp[0x6];
7315
7316         u8         clr[0x1];
7317         u8         reserved_at_21[0x1c];
7318         u8         prio_tc[0x3];
7319
7320         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7321 };
7322
7323 struct mlx5_ifc_mpcnt_reg_bits {
7324         u8         reserved_at_0[0x8];
7325         u8         pcie_index[0x8];
7326         u8         reserved_at_10[0xa];
7327         u8         grp[0x6];
7328
7329         u8         clr[0x1];
7330         u8         reserved_at_21[0x1f];
7331
7332         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7333 };
7334
7335 struct mlx5_ifc_ppad_reg_bits {
7336         u8         reserved_at_0[0x3];
7337         u8         single_mac[0x1];
7338         u8         reserved_at_4[0x4];
7339         u8         local_port[0x8];
7340         u8         mac_47_32[0x10];
7341
7342         u8         mac_31_0[0x20];
7343
7344         u8         reserved_at_40[0x40];
7345 };
7346
7347 struct mlx5_ifc_pmtu_reg_bits {
7348         u8         reserved_at_0[0x8];
7349         u8         local_port[0x8];
7350         u8         reserved_at_10[0x10];
7351
7352         u8         max_mtu[0x10];
7353         u8         reserved_at_30[0x10];
7354
7355         u8         admin_mtu[0x10];
7356         u8         reserved_at_50[0x10];
7357
7358         u8         oper_mtu[0x10];
7359         u8         reserved_at_70[0x10];
7360 };
7361
7362 struct mlx5_ifc_pmpr_reg_bits {
7363         u8         reserved_at_0[0x8];
7364         u8         module[0x8];
7365         u8         reserved_at_10[0x10];
7366
7367         u8         reserved_at_20[0x18];
7368         u8         attenuation_5g[0x8];
7369
7370         u8         reserved_at_40[0x18];
7371         u8         attenuation_7g[0x8];
7372
7373         u8         reserved_at_60[0x18];
7374         u8         attenuation_12g[0x8];
7375 };
7376
7377 struct mlx5_ifc_pmpe_reg_bits {
7378         u8         reserved_at_0[0x8];
7379         u8         module[0x8];
7380         u8         reserved_at_10[0xc];
7381         u8         module_status[0x4];
7382
7383         u8         reserved_at_20[0x60];
7384 };
7385
7386 struct mlx5_ifc_pmpc_reg_bits {
7387         u8         module_state_updated[32][0x8];
7388 };
7389
7390 struct mlx5_ifc_pmlpn_reg_bits {
7391         u8         reserved_at_0[0x4];
7392         u8         mlpn_status[0x4];
7393         u8         local_port[0x8];
7394         u8         reserved_at_10[0x10];
7395
7396         u8         e[0x1];
7397         u8         reserved_at_21[0x1f];
7398 };
7399
7400 struct mlx5_ifc_pmlp_reg_bits {
7401         u8         rxtx[0x1];
7402         u8         reserved_at_1[0x7];
7403         u8         local_port[0x8];
7404         u8         reserved_at_10[0x8];
7405         u8         width[0x8];
7406
7407         u8         lane0_module_mapping[0x20];
7408
7409         u8         lane1_module_mapping[0x20];
7410
7411         u8         lane2_module_mapping[0x20];
7412
7413         u8         lane3_module_mapping[0x20];
7414
7415         u8         reserved_at_a0[0x160];
7416 };
7417
7418 struct mlx5_ifc_pmaos_reg_bits {
7419         u8         reserved_at_0[0x8];
7420         u8         module[0x8];
7421         u8         reserved_at_10[0x4];
7422         u8         admin_status[0x4];
7423         u8         reserved_at_18[0x4];
7424         u8         oper_status[0x4];
7425
7426         u8         ase[0x1];
7427         u8         ee[0x1];
7428         u8         reserved_at_22[0x1c];
7429         u8         e[0x2];
7430
7431         u8         reserved_at_40[0x40];
7432 };
7433
7434 struct mlx5_ifc_plpc_reg_bits {
7435         u8         reserved_at_0[0x4];
7436         u8         profile_id[0xc];
7437         u8         reserved_at_10[0x4];
7438         u8         proto_mask[0x4];
7439         u8         reserved_at_18[0x8];
7440
7441         u8         reserved_at_20[0x10];
7442         u8         lane_speed[0x10];
7443
7444         u8         reserved_at_40[0x17];
7445         u8         lpbf[0x1];
7446         u8         fec_mode_policy[0x8];
7447
7448         u8         retransmission_capability[0x8];
7449         u8         fec_mode_capability[0x18];
7450
7451         u8         retransmission_support_admin[0x8];
7452         u8         fec_mode_support_admin[0x18];
7453
7454         u8         retransmission_request_admin[0x8];
7455         u8         fec_mode_request_admin[0x18];
7456
7457         u8         reserved_at_c0[0x80];
7458 };
7459
7460 struct mlx5_ifc_plib_reg_bits {
7461         u8         reserved_at_0[0x8];
7462         u8         local_port[0x8];
7463         u8         reserved_at_10[0x8];
7464         u8         ib_port[0x8];
7465
7466         u8         reserved_at_20[0x60];
7467 };
7468
7469 struct mlx5_ifc_plbf_reg_bits {
7470         u8         reserved_at_0[0x8];
7471         u8         local_port[0x8];
7472         u8         reserved_at_10[0xd];
7473         u8         lbf_mode[0x3];
7474
7475         u8         reserved_at_20[0x20];
7476 };
7477
7478 struct mlx5_ifc_pipg_reg_bits {
7479         u8         reserved_at_0[0x8];
7480         u8         local_port[0x8];
7481         u8         reserved_at_10[0x10];
7482
7483         u8         dic[0x1];
7484         u8         reserved_at_21[0x19];
7485         u8         ipg[0x4];
7486         u8         reserved_at_3e[0x2];
7487 };
7488
7489 struct mlx5_ifc_pifr_reg_bits {
7490         u8         reserved_at_0[0x8];
7491         u8         local_port[0x8];
7492         u8         reserved_at_10[0x10];
7493
7494         u8         reserved_at_20[0xe0];
7495
7496         u8         port_filter[8][0x20];
7497
7498         u8         port_filter_update_en[8][0x20];
7499 };
7500
7501 struct mlx5_ifc_pfcc_reg_bits {
7502         u8         reserved_at_0[0x8];
7503         u8         local_port[0x8];
7504         u8         reserved_at_10[0x10];
7505
7506         u8         ppan[0x4];
7507         u8         reserved_at_24[0x4];
7508         u8         prio_mask_tx[0x8];
7509         u8         reserved_at_30[0x8];
7510         u8         prio_mask_rx[0x8];
7511
7512         u8         pptx[0x1];
7513         u8         aptx[0x1];
7514         u8         reserved_at_42[0x6];
7515         u8         pfctx[0x8];
7516         u8         reserved_at_50[0x10];
7517
7518         u8         pprx[0x1];
7519         u8         aprx[0x1];
7520         u8         reserved_at_62[0x6];
7521         u8         pfcrx[0x8];
7522         u8         reserved_at_70[0x10];
7523
7524         u8         reserved_at_80[0x80];
7525 };
7526
7527 struct mlx5_ifc_pelc_reg_bits {
7528         u8         op[0x4];
7529         u8         reserved_at_4[0x4];
7530         u8         local_port[0x8];
7531         u8         reserved_at_10[0x10];
7532
7533         u8         op_admin[0x8];
7534         u8         op_capability[0x8];
7535         u8         op_request[0x8];
7536         u8         op_active[0x8];
7537
7538         u8         admin[0x40];
7539
7540         u8         capability[0x40];
7541
7542         u8         request[0x40];
7543
7544         u8         active[0x40];
7545
7546         u8         reserved_at_140[0x80];
7547 };
7548
7549 struct mlx5_ifc_peir_reg_bits {
7550         u8         reserved_at_0[0x8];
7551         u8         local_port[0x8];
7552         u8         reserved_at_10[0x10];
7553
7554         u8         reserved_at_20[0xc];
7555         u8         error_count[0x4];
7556         u8         reserved_at_30[0x10];
7557
7558         u8         reserved_at_40[0xc];
7559         u8         lane[0x4];
7560         u8         reserved_at_50[0x8];
7561         u8         error_type[0x8];
7562 };
7563
7564 struct mlx5_ifc_pcap_reg_bits {
7565         u8         reserved_at_0[0x8];
7566         u8         local_port[0x8];
7567         u8         reserved_at_10[0x10];
7568
7569         u8         port_capability_mask[4][0x20];
7570 };
7571
7572 struct mlx5_ifc_paos_reg_bits {
7573         u8         swid[0x8];
7574         u8         local_port[0x8];
7575         u8         reserved_at_10[0x4];
7576         u8         admin_status[0x4];
7577         u8         reserved_at_18[0x4];
7578         u8         oper_status[0x4];
7579
7580         u8         ase[0x1];
7581         u8         ee[0x1];
7582         u8         reserved_at_22[0x1c];
7583         u8         e[0x2];
7584
7585         u8         reserved_at_40[0x40];
7586 };
7587
7588 struct mlx5_ifc_pamp_reg_bits {
7589         u8         reserved_at_0[0x8];
7590         u8         opamp_group[0x8];
7591         u8         reserved_at_10[0xc];
7592         u8         opamp_group_type[0x4];
7593
7594         u8         start_index[0x10];
7595         u8         reserved_at_30[0x4];
7596         u8         num_of_indices[0xc];
7597
7598         u8         index_data[18][0x10];
7599 };
7600
7601 struct mlx5_ifc_pcmr_reg_bits {
7602         u8         reserved_at_0[0x8];
7603         u8         local_port[0x8];
7604         u8         reserved_at_10[0x2e];
7605         u8         fcs_cap[0x1];
7606         u8         reserved_at_3f[0x1f];
7607         u8         fcs_chk[0x1];
7608         u8         reserved_at_5f[0x1];
7609 };
7610
7611 struct mlx5_ifc_lane_2_module_mapping_bits {
7612         u8         reserved_at_0[0x6];
7613         u8         rx_lane[0x2];
7614         u8         reserved_at_8[0x6];
7615         u8         tx_lane[0x2];
7616         u8         reserved_at_10[0x8];
7617         u8         module[0x8];
7618 };
7619
7620 struct mlx5_ifc_bufferx_reg_bits {
7621         u8         reserved_at_0[0x6];
7622         u8         lossy[0x1];
7623         u8         epsb[0x1];
7624         u8         reserved_at_8[0xc];
7625         u8         size[0xc];
7626
7627         u8         xoff_threshold[0x10];
7628         u8         xon_threshold[0x10];
7629 };
7630
7631 struct mlx5_ifc_set_node_in_bits {
7632         u8         node_description[64][0x8];
7633 };
7634
7635 struct mlx5_ifc_register_power_settings_bits {
7636         u8         reserved_at_0[0x18];
7637         u8         power_settings_level[0x8];
7638
7639         u8         reserved_at_20[0x60];
7640 };
7641
7642 struct mlx5_ifc_register_host_endianness_bits {
7643         u8         he[0x1];
7644         u8         reserved_at_1[0x1f];
7645
7646         u8         reserved_at_20[0x60];
7647 };
7648
7649 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7650         u8         reserved_at_0[0x20];
7651
7652         u8         mkey[0x20];
7653
7654         u8         addressh_63_32[0x20];
7655
7656         u8         addressl_31_0[0x20];
7657 };
7658
7659 struct mlx5_ifc_ud_adrs_vector_bits {
7660         u8         dc_key[0x40];
7661
7662         u8         ext[0x1];
7663         u8         reserved_at_41[0x7];
7664         u8         destination_qp_dct[0x18];
7665
7666         u8         static_rate[0x4];
7667         u8         sl_eth_prio[0x4];
7668         u8         fl[0x1];
7669         u8         mlid[0x7];
7670         u8         rlid_udp_sport[0x10];
7671
7672         u8         reserved_at_80[0x20];
7673
7674         u8         rmac_47_16[0x20];
7675
7676         u8         rmac_15_0[0x10];
7677         u8         tclass[0x8];
7678         u8         hop_limit[0x8];
7679
7680         u8         reserved_at_e0[0x1];
7681         u8         grh[0x1];
7682         u8         reserved_at_e2[0x2];
7683         u8         src_addr_index[0x8];
7684         u8         flow_label[0x14];
7685
7686         u8         rgid_rip[16][0x8];
7687 };
7688
7689 struct mlx5_ifc_pages_req_event_bits {
7690         u8         reserved_at_0[0x10];
7691         u8         function_id[0x10];
7692
7693         u8         num_pages[0x20];
7694
7695         u8         reserved_at_40[0xa0];
7696 };
7697
7698 struct mlx5_ifc_eqe_bits {
7699         u8         reserved_at_0[0x8];
7700         u8         event_type[0x8];
7701         u8         reserved_at_10[0x8];
7702         u8         event_sub_type[0x8];
7703
7704         u8         reserved_at_20[0xe0];
7705
7706         union mlx5_ifc_event_auto_bits event_data;
7707
7708         u8         reserved_at_1e0[0x10];
7709         u8         signature[0x8];
7710         u8         reserved_at_1f8[0x7];
7711         u8         owner[0x1];
7712 };
7713
7714 enum {
7715         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7716 };
7717
7718 struct mlx5_ifc_cmd_queue_entry_bits {
7719         u8         type[0x8];
7720         u8         reserved_at_8[0x18];
7721
7722         u8         input_length[0x20];
7723
7724         u8         input_mailbox_pointer_63_32[0x20];
7725
7726         u8         input_mailbox_pointer_31_9[0x17];
7727         u8         reserved_at_77[0x9];
7728
7729         u8         command_input_inline_data[16][0x8];
7730
7731         u8         command_output_inline_data[16][0x8];
7732
7733         u8         output_mailbox_pointer_63_32[0x20];
7734
7735         u8         output_mailbox_pointer_31_9[0x17];
7736         u8         reserved_at_1b7[0x9];
7737
7738         u8         output_length[0x20];
7739
7740         u8         token[0x8];
7741         u8         signature[0x8];
7742         u8         reserved_at_1f0[0x8];
7743         u8         status[0x7];
7744         u8         ownership[0x1];
7745 };
7746
7747 struct mlx5_ifc_cmd_out_bits {
7748         u8         status[0x8];
7749         u8         reserved_at_8[0x18];
7750
7751         u8         syndrome[0x20];
7752
7753         u8         command_output[0x20];
7754 };
7755
7756 struct mlx5_ifc_cmd_in_bits {
7757         u8         opcode[0x10];
7758         u8         reserved_at_10[0x10];
7759
7760         u8         reserved_at_20[0x10];
7761         u8         op_mod[0x10];
7762
7763         u8         command[0][0x20];
7764 };
7765
7766 struct mlx5_ifc_cmd_if_box_bits {
7767         u8         mailbox_data[512][0x8];
7768
7769         u8         reserved_at_1000[0x180];
7770
7771         u8         next_pointer_63_32[0x20];
7772
7773         u8         next_pointer_31_10[0x16];
7774         u8         reserved_at_11b6[0xa];
7775
7776         u8         block_number[0x20];
7777
7778         u8         reserved_at_11e0[0x8];
7779         u8         token[0x8];
7780         u8         ctrl_signature[0x8];
7781         u8         signature[0x8];
7782 };
7783
7784 struct mlx5_ifc_mtt_bits {
7785         u8         ptag_63_32[0x20];
7786
7787         u8         ptag_31_8[0x18];
7788         u8         reserved_at_38[0x6];
7789         u8         wr_en[0x1];
7790         u8         rd_en[0x1];
7791 };
7792
7793 struct mlx5_ifc_query_wol_rol_out_bits {
7794         u8         status[0x8];
7795         u8         reserved_at_8[0x18];
7796
7797         u8         syndrome[0x20];
7798
7799         u8         reserved_at_40[0x10];
7800         u8         rol_mode[0x8];
7801         u8         wol_mode[0x8];
7802
7803         u8         reserved_at_60[0x20];
7804 };
7805
7806 struct mlx5_ifc_query_wol_rol_in_bits {
7807         u8         opcode[0x10];
7808         u8         reserved_at_10[0x10];
7809
7810         u8         reserved_at_20[0x10];
7811         u8         op_mod[0x10];
7812
7813         u8         reserved_at_40[0x40];
7814 };
7815
7816 struct mlx5_ifc_set_wol_rol_out_bits {
7817         u8         status[0x8];
7818         u8         reserved_at_8[0x18];
7819
7820         u8         syndrome[0x20];
7821
7822         u8         reserved_at_40[0x40];
7823 };
7824
7825 struct mlx5_ifc_set_wol_rol_in_bits {
7826         u8         opcode[0x10];
7827         u8         reserved_at_10[0x10];
7828
7829         u8         reserved_at_20[0x10];
7830         u8         op_mod[0x10];
7831
7832         u8         rol_mode_valid[0x1];
7833         u8         wol_mode_valid[0x1];
7834         u8         reserved_at_42[0xe];
7835         u8         rol_mode[0x8];
7836         u8         wol_mode[0x8];
7837
7838         u8         reserved_at_60[0x20];
7839 };
7840
7841 enum {
7842         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7843         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7844         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7845 };
7846
7847 enum {
7848         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7849         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7850         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7851 };
7852
7853 enum {
7854         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7855         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7856         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7857         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7858         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7859         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7860         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7861         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7862         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7863         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7864         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7865 };
7866
7867 struct mlx5_ifc_initial_seg_bits {
7868         u8         fw_rev_minor[0x10];
7869         u8         fw_rev_major[0x10];
7870
7871         u8         cmd_interface_rev[0x10];
7872         u8         fw_rev_subminor[0x10];
7873
7874         u8         reserved_at_40[0x40];
7875
7876         u8         cmdq_phy_addr_63_32[0x20];
7877
7878         u8         cmdq_phy_addr_31_12[0x14];
7879         u8         reserved_at_b4[0x2];
7880         u8         nic_interface[0x2];
7881         u8         log_cmdq_size[0x4];
7882         u8         log_cmdq_stride[0x4];
7883
7884         u8         command_doorbell_vector[0x20];
7885
7886         u8         reserved_at_e0[0xf00];
7887
7888         u8         initializing[0x1];
7889         u8         reserved_at_fe1[0x4];
7890         u8         nic_interface_supported[0x3];
7891         u8         reserved_at_fe8[0x18];
7892
7893         struct mlx5_ifc_health_buffer_bits health_buffer;
7894
7895         u8         no_dram_nic_offset[0x20];
7896
7897         u8         reserved_at_1220[0x6e40];
7898
7899         u8         reserved_at_8060[0x1f];
7900         u8         clear_int[0x1];
7901
7902         u8         health_syndrome[0x8];
7903         u8         health_counter[0x18];
7904
7905         u8         reserved_at_80a0[0x17fc0];
7906 };
7907
7908 union mlx5_ifc_ports_control_registers_document_bits {
7909         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7910         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7911         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7912         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7913         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7914         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7915         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7916         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7917         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7918         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7919         struct mlx5_ifc_paos_reg_bits paos_reg;
7920         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7921         struct mlx5_ifc_peir_reg_bits peir_reg;
7922         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7923         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7924         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7925         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7926         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7927         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7928         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7929         struct mlx5_ifc_plib_reg_bits plib_reg;
7930         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7931         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7932         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7933         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7934         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7935         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7936         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7937         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7938         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7939         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7940         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
7941         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7942         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7943         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7944         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7945         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7946         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7947         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7948         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7949         struct mlx5_ifc_pude_reg_bits pude_reg;
7950         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7951         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7952         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7953         u8         reserved_at_0[0x60e0];
7954 };
7955
7956 union mlx5_ifc_debug_enhancements_document_bits {
7957         struct mlx5_ifc_health_buffer_bits health_buffer;
7958         u8         reserved_at_0[0x200];
7959 };
7960
7961 union mlx5_ifc_uplink_pci_interface_document_bits {
7962         struct mlx5_ifc_initial_seg_bits initial_seg;
7963         u8         reserved_at_0[0x20060];
7964 };
7965
7966 struct mlx5_ifc_set_flow_table_root_out_bits {
7967         u8         status[0x8];
7968         u8         reserved_at_8[0x18];
7969
7970         u8         syndrome[0x20];
7971
7972         u8         reserved_at_40[0x40];
7973 };
7974
7975 struct mlx5_ifc_set_flow_table_root_in_bits {
7976         u8         opcode[0x10];
7977         u8         reserved_at_10[0x10];
7978
7979         u8         reserved_at_20[0x10];
7980         u8         op_mod[0x10];
7981
7982         u8         other_vport[0x1];
7983         u8         reserved_at_41[0xf];
7984         u8         vport_number[0x10];
7985
7986         u8         reserved_at_60[0x20];
7987
7988         u8         table_type[0x8];
7989         u8         reserved_at_88[0x18];
7990
7991         u8         reserved_at_a0[0x8];
7992         u8         table_id[0x18];
7993
7994         u8         reserved_at_c0[0x140];
7995 };
7996
7997 enum {
7998         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
7999         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8000 };
8001
8002 struct mlx5_ifc_modify_flow_table_out_bits {
8003         u8         status[0x8];
8004         u8         reserved_at_8[0x18];
8005
8006         u8         syndrome[0x20];
8007
8008         u8         reserved_at_40[0x40];
8009 };
8010
8011 struct mlx5_ifc_modify_flow_table_in_bits {
8012         u8         opcode[0x10];
8013         u8         reserved_at_10[0x10];
8014
8015         u8         reserved_at_20[0x10];
8016         u8         op_mod[0x10];
8017
8018         u8         other_vport[0x1];
8019         u8         reserved_at_41[0xf];
8020         u8         vport_number[0x10];
8021
8022         u8         reserved_at_60[0x10];
8023         u8         modify_field_select[0x10];
8024
8025         u8         table_type[0x8];
8026         u8         reserved_at_88[0x18];
8027
8028         u8         reserved_at_a0[0x8];
8029         u8         table_id[0x18];
8030
8031         u8         reserved_at_c0[0x4];
8032         u8         table_miss_mode[0x4];
8033         u8         reserved_at_c8[0x18];
8034
8035         u8         reserved_at_e0[0x8];
8036         u8         table_miss_id[0x18];
8037
8038         u8         reserved_at_100[0x8];
8039         u8         lag_master_next_table_id[0x18];
8040
8041         u8         reserved_at_120[0x80];
8042 };
8043
8044 struct mlx5_ifc_ets_tcn_config_reg_bits {
8045         u8         g[0x1];
8046         u8         b[0x1];
8047         u8         r[0x1];
8048         u8         reserved_at_3[0x9];
8049         u8         group[0x4];
8050         u8         reserved_at_10[0x9];
8051         u8         bw_allocation[0x7];
8052
8053         u8         reserved_at_20[0xc];
8054         u8         max_bw_units[0x4];
8055         u8         reserved_at_30[0x8];
8056         u8         max_bw_value[0x8];
8057 };
8058
8059 struct mlx5_ifc_ets_global_config_reg_bits {
8060         u8         reserved_at_0[0x2];
8061         u8         r[0x1];
8062         u8         reserved_at_3[0x1d];
8063
8064         u8         reserved_at_20[0xc];
8065         u8         max_bw_units[0x4];
8066         u8         reserved_at_30[0x8];
8067         u8         max_bw_value[0x8];
8068 };
8069
8070 struct mlx5_ifc_qetc_reg_bits {
8071         u8                                         reserved_at_0[0x8];
8072         u8                                         port_number[0x8];
8073         u8                                         reserved_at_10[0x30];
8074
8075         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8076         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8077 };
8078
8079 struct mlx5_ifc_qtct_reg_bits {
8080         u8         reserved_at_0[0x8];
8081         u8         port_number[0x8];
8082         u8         reserved_at_10[0xd];
8083         u8         prio[0x3];
8084
8085         u8         reserved_at_20[0x1d];
8086         u8         tclass[0x3];
8087 };
8088
8089 struct mlx5_ifc_mcia_reg_bits {
8090         u8         l[0x1];
8091         u8         reserved_at_1[0x7];
8092         u8         module[0x8];
8093         u8         reserved_at_10[0x8];
8094         u8         status[0x8];
8095
8096         u8         i2c_device_address[0x8];
8097         u8         page_number[0x8];
8098         u8         device_address[0x10];
8099
8100         u8         reserved_at_40[0x10];
8101         u8         size[0x10];
8102
8103         u8         reserved_at_60[0x20];
8104
8105         u8         dword_0[0x20];
8106         u8         dword_1[0x20];
8107         u8         dword_2[0x20];
8108         u8         dword_3[0x20];
8109         u8         dword_4[0x20];
8110         u8         dword_5[0x20];
8111         u8         dword_6[0x20];
8112         u8         dword_7[0x20];
8113         u8         dword_8[0x20];
8114         u8         dword_9[0x20];
8115         u8         dword_10[0x20];
8116         u8         dword_11[0x20];
8117 };
8118
8119 struct mlx5_ifc_dcbx_param_bits {
8120         u8         dcbx_cee_cap[0x1];
8121         u8         dcbx_ieee_cap[0x1];
8122         u8         dcbx_standby_cap[0x1];
8123         u8         reserved_at_0[0x5];
8124         u8         port_number[0x8];
8125         u8         reserved_at_10[0xa];
8126         u8         max_application_table_size[6];
8127         u8         reserved_at_20[0x15];
8128         u8         version_oper[0x3];
8129         u8         reserved_at_38[5];
8130         u8         version_admin[0x3];
8131         u8         willing_admin[0x1];
8132         u8         reserved_at_41[0x3];
8133         u8         pfc_cap_oper[0x4];
8134         u8         reserved_at_48[0x4];
8135         u8         pfc_cap_admin[0x4];
8136         u8         reserved_at_50[0x4];
8137         u8         num_of_tc_oper[0x4];
8138         u8         reserved_at_58[0x4];
8139         u8         num_of_tc_admin[0x4];
8140         u8         remote_willing[0x1];
8141         u8         reserved_at_61[3];
8142         u8         remote_pfc_cap[4];
8143         u8         reserved_at_68[0x14];
8144         u8         remote_num_of_tc[0x4];
8145         u8         reserved_at_80[0x18];
8146         u8         error[0x8];
8147         u8         reserved_at_a0[0x160];
8148 };
8149
8150 struct mlx5_ifc_lagc_bits {
8151         u8         reserved_at_0[0x1d];
8152         u8         lag_state[0x3];
8153
8154         u8         reserved_at_20[0x14];
8155         u8         tx_remap_affinity_2[0x4];
8156         u8         reserved_at_38[0x4];
8157         u8         tx_remap_affinity_1[0x4];
8158 };
8159
8160 struct mlx5_ifc_create_lag_out_bits {
8161         u8         status[0x8];
8162         u8         reserved_at_8[0x18];
8163
8164         u8         syndrome[0x20];
8165
8166         u8         reserved_at_40[0x40];
8167 };
8168
8169 struct mlx5_ifc_create_lag_in_bits {
8170         u8         opcode[0x10];
8171         u8         reserved_at_10[0x10];
8172
8173         u8         reserved_at_20[0x10];
8174         u8         op_mod[0x10];
8175
8176         struct mlx5_ifc_lagc_bits ctx;
8177 };
8178
8179 struct mlx5_ifc_modify_lag_out_bits {
8180         u8         status[0x8];
8181         u8         reserved_at_8[0x18];
8182
8183         u8         syndrome[0x20];
8184
8185         u8         reserved_at_40[0x40];
8186 };
8187
8188 struct mlx5_ifc_modify_lag_in_bits {
8189         u8         opcode[0x10];
8190         u8         reserved_at_10[0x10];
8191
8192         u8         reserved_at_20[0x10];
8193         u8         op_mod[0x10];
8194
8195         u8         reserved_at_40[0x20];
8196         u8         field_select[0x20];
8197
8198         struct mlx5_ifc_lagc_bits ctx;
8199 };
8200
8201 struct mlx5_ifc_query_lag_out_bits {
8202         u8         status[0x8];
8203         u8         reserved_at_8[0x18];
8204
8205         u8         syndrome[0x20];
8206
8207         u8         reserved_at_40[0x40];
8208
8209         struct mlx5_ifc_lagc_bits ctx;
8210 };
8211
8212 struct mlx5_ifc_query_lag_in_bits {
8213         u8         opcode[0x10];
8214         u8         reserved_at_10[0x10];
8215
8216         u8         reserved_at_20[0x10];
8217         u8         op_mod[0x10];
8218
8219         u8         reserved_at_40[0x40];
8220 };
8221
8222 struct mlx5_ifc_destroy_lag_out_bits {
8223         u8         status[0x8];
8224         u8         reserved_at_8[0x18];
8225
8226         u8         syndrome[0x20];
8227
8228         u8         reserved_at_40[0x40];
8229 };
8230
8231 struct mlx5_ifc_destroy_lag_in_bits {
8232         u8         opcode[0x10];
8233         u8         reserved_at_10[0x10];
8234
8235         u8         reserved_at_20[0x10];
8236         u8         op_mod[0x10];
8237
8238         u8         reserved_at_40[0x40];
8239 };
8240
8241 struct mlx5_ifc_create_vport_lag_out_bits {
8242         u8         status[0x8];
8243         u8         reserved_at_8[0x18];
8244
8245         u8         syndrome[0x20];
8246
8247         u8         reserved_at_40[0x40];
8248 };
8249
8250 struct mlx5_ifc_create_vport_lag_in_bits {
8251         u8         opcode[0x10];
8252         u8         reserved_at_10[0x10];
8253
8254         u8         reserved_at_20[0x10];
8255         u8         op_mod[0x10];
8256
8257         u8         reserved_at_40[0x40];
8258 };
8259
8260 struct mlx5_ifc_destroy_vport_lag_out_bits {
8261         u8         status[0x8];
8262         u8         reserved_at_8[0x18];
8263
8264         u8         syndrome[0x20];
8265
8266         u8         reserved_at_40[0x40];
8267 };
8268
8269 struct mlx5_ifc_destroy_vport_lag_in_bits {
8270         u8         opcode[0x10];
8271         u8         reserved_at_10[0x10];
8272
8273         u8         reserved_at_20[0x10];
8274         u8         op_mod[0x10];
8275
8276         u8         reserved_at_40[0x40];
8277 };
8278
8279 #endif /* MLX5_IFC_H */