net/mlx5: Fix counter list hardware structure
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64
65 enum {
66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71
72 enum {
73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76
77 enum {
78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
170         MLX5_CMD_OP_NOP                           = 0x80d,
171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
203         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
204         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
205         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
206         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
207         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
208         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
209         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
210         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
211         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
212         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
213         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
214         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
215         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
216         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
217         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
218         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
219         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
220         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
221         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
222         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
223         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
224         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
225         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
226         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
227         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
228         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
229         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
230         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
231         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
232         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
233         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
234         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
235         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
236         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
237         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
238         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
239         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
240         MLX5_CMD_OP_MAX
241 };
242
243 struct mlx5_ifc_flow_table_fields_supported_bits {
244         u8         outer_dmac[0x1];
245         u8         outer_smac[0x1];
246         u8         outer_ether_type[0x1];
247         u8         outer_ip_version[0x1];
248         u8         outer_first_prio[0x1];
249         u8         outer_first_cfi[0x1];
250         u8         outer_first_vid[0x1];
251         u8         outer_ipv4_ttl[0x1];
252         u8         outer_second_prio[0x1];
253         u8         outer_second_cfi[0x1];
254         u8         outer_second_vid[0x1];
255         u8         reserved_at_b[0x1];
256         u8         outer_sip[0x1];
257         u8         outer_dip[0x1];
258         u8         outer_frag[0x1];
259         u8         outer_ip_protocol[0x1];
260         u8         outer_ip_ecn[0x1];
261         u8         outer_ip_dscp[0x1];
262         u8         outer_udp_sport[0x1];
263         u8         outer_udp_dport[0x1];
264         u8         outer_tcp_sport[0x1];
265         u8         outer_tcp_dport[0x1];
266         u8         outer_tcp_flags[0x1];
267         u8         outer_gre_protocol[0x1];
268         u8         outer_gre_key[0x1];
269         u8         outer_vxlan_vni[0x1];
270         u8         reserved_at_1a[0x5];
271         u8         source_eswitch_port[0x1];
272
273         u8         inner_dmac[0x1];
274         u8         inner_smac[0x1];
275         u8         inner_ether_type[0x1];
276         u8         inner_ip_version[0x1];
277         u8         inner_first_prio[0x1];
278         u8         inner_first_cfi[0x1];
279         u8         inner_first_vid[0x1];
280         u8         reserved_at_27[0x1];
281         u8         inner_second_prio[0x1];
282         u8         inner_second_cfi[0x1];
283         u8         inner_second_vid[0x1];
284         u8         reserved_at_2b[0x1];
285         u8         inner_sip[0x1];
286         u8         inner_dip[0x1];
287         u8         inner_frag[0x1];
288         u8         inner_ip_protocol[0x1];
289         u8         inner_ip_ecn[0x1];
290         u8         inner_ip_dscp[0x1];
291         u8         inner_udp_sport[0x1];
292         u8         inner_udp_dport[0x1];
293         u8         inner_tcp_sport[0x1];
294         u8         inner_tcp_dport[0x1];
295         u8         inner_tcp_flags[0x1];
296         u8         reserved_at_37[0x9];
297
298         u8         reserved_at_40[0x40];
299 };
300
301 struct mlx5_ifc_flow_table_prop_layout_bits {
302         u8         ft_support[0x1];
303         u8         reserved_at_1[0x1];
304         u8         flow_counter[0x1];
305         u8         flow_modify_en[0x1];
306         u8         modify_root[0x1];
307         u8         identified_miss_table_mode[0x1];
308         u8         flow_table_modify[0x1];
309         u8         encap[0x1];
310         u8         decap[0x1];
311         u8         reserved_at_9[0x17];
312
313         u8         reserved_at_20[0x2];
314         u8         log_max_ft_size[0x6];
315         u8         log_max_modify_header_context[0x8];
316         u8         max_modify_header_actions[0x8];
317         u8         max_ft_level[0x8];
318
319         u8         reserved_at_40[0x20];
320
321         u8         reserved_at_60[0x18];
322         u8         log_max_ft_num[0x8];
323
324         u8         reserved_at_80[0x18];
325         u8         log_max_destination[0x8];
326
327         u8         reserved_at_a0[0x18];
328         u8         log_max_flow[0x8];
329
330         u8         reserved_at_c0[0x40];
331
332         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
333
334         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
335 };
336
337 struct mlx5_ifc_odp_per_transport_service_cap_bits {
338         u8         send[0x1];
339         u8         receive[0x1];
340         u8         write[0x1];
341         u8         read[0x1];
342         u8         atomic[0x1];
343         u8         srq_receive[0x1];
344         u8         reserved_at_6[0x1a];
345 };
346
347 struct mlx5_ifc_ipv4_layout_bits {
348         u8         reserved_at_0[0x60];
349
350         u8         ipv4[0x20];
351 };
352
353 struct mlx5_ifc_ipv6_layout_bits {
354         u8         ipv6[16][0x8];
355 };
356
357 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
358         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
359         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
360         u8         reserved_at_0[0x80];
361 };
362
363 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
364         u8         smac_47_16[0x20];
365
366         u8         smac_15_0[0x10];
367         u8         ethertype[0x10];
368
369         u8         dmac_47_16[0x20];
370
371         u8         dmac_15_0[0x10];
372         u8         first_prio[0x3];
373         u8         first_cfi[0x1];
374         u8         first_vid[0xc];
375
376         u8         ip_protocol[0x8];
377         u8         ip_dscp[0x6];
378         u8         ip_ecn[0x2];
379         u8         cvlan_tag[0x1];
380         u8         svlan_tag[0x1];
381         u8         frag[0x1];
382         u8         ip_version[0x4];
383         u8         tcp_flags[0x9];
384
385         u8         tcp_sport[0x10];
386         u8         tcp_dport[0x10];
387
388         u8         reserved_at_c0[0x18];
389         u8         ttl_hoplimit[0x8];
390
391         u8         udp_sport[0x10];
392         u8         udp_dport[0x10];
393
394         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
395
396         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
397 };
398
399 struct mlx5_ifc_fte_match_set_misc_bits {
400         u8         reserved_at_0[0x8];
401         u8         source_sqn[0x18];
402
403         u8         reserved_at_20[0x10];
404         u8         source_port[0x10];
405
406         u8         outer_second_prio[0x3];
407         u8         outer_second_cfi[0x1];
408         u8         outer_second_vid[0xc];
409         u8         inner_second_prio[0x3];
410         u8         inner_second_cfi[0x1];
411         u8         inner_second_vid[0xc];
412
413         u8         outer_second_cvlan_tag[0x1];
414         u8         inner_second_cvlan_tag[0x1];
415         u8         outer_second_svlan_tag[0x1];
416         u8         inner_second_svlan_tag[0x1];
417         u8         reserved_at_64[0xc];
418         u8         gre_protocol[0x10];
419
420         u8         gre_key_h[0x18];
421         u8         gre_key_l[0x8];
422
423         u8         vxlan_vni[0x18];
424         u8         reserved_at_b8[0x8];
425
426         u8         reserved_at_c0[0x20];
427
428         u8         reserved_at_e0[0xc];
429         u8         outer_ipv6_flow_label[0x14];
430
431         u8         reserved_at_100[0xc];
432         u8         inner_ipv6_flow_label[0x14];
433
434         u8         reserved_at_120[0xe0];
435 };
436
437 struct mlx5_ifc_cmd_pas_bits {
438         u8         pa_h[0x20];
439
440         u8         pa_l[0x14];
441         u8         reserved_at_34[0xc];
442 };
443
444 struct mlx5_ifc_uint64_bits {
445         u8         hi[0x20];
446
447         u8         lo[0x20];
448 };
449
450 enum {
451         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
452         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
453         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
454         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
455         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
456         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
457         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
458         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
459         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
460         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
461 };
462
463 struct mlx5_ifc_ads_bits {
464         u8         fl[0x1];
465         u8         free_ar[0x1];
466         u8         reserved_at_2[0xe];
467         u8         pkey_index[0x10];
468
469         u8         reserved_at_20[0x8];
470         u8         grh[0x1];
471         u8         mlid[0x7];
472         u8         rlid[0x10];
473
474         u8         ack_timeout[0x5];
475         u8         reserved_at_45[0x3];
476         u8         src_addr_index[0x8];
477         u8         reserved_at_50[0x4];
478         u8         stat_rate[0x4];
479         u8         hop_limit[0x8];
480
481         u8         reserved_at_60[0x4];
482         u8         tclass[0x8];
483         u8         flow_label[0x14];
484
485         u8         rgid_rip[16][0x8];
486
487         u8         reserved_at_100[0x4];
488         u8         f_dscp[0x1];
489         u8         f_ecn[0x1];
490         u8         reserved_at_106[0x1];
491         u8         f_eth_prio[0x1];
492         u8         ecn[0x2];
493         u8         dscp[0x6];
494         u8         udp_sport[0x10];
495
496         u8         dei_cfi[0x1];
497         u8         eth_prio[0x3];
498         u8         sl[0x4];
499         u8         port[0x8];
500         u8         rmac_47_32[0x10];
501
502         u8         rmac_31_0[0x20];
503 };
504
505 struct mlx5_ifc_flow_table_nic_cap_bits {
506         u8         nic_rx_multi_path_tirs[0x1];
507         u8         nic_rx_multi_path_tirs_fts[0x1];
508         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
509         u8         reserved_at_3[0x1fd];
510
511         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
512
513         u8         reserved_at_400[0x200];
514
515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
516
517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
518
519         u8         reserved_at_a00[0x200];
520
521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
522
523         u8         reserved_at_e00[0x7200];
524 };
525
526 struct mlx5_ifc_flow_table_eswitch_cap_bits {
527         u8     reserved_at_0[0x200];
528
529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
530
531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
532
533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
534
535         u8      reserved_at_800[0x7800];
536 };
537
538 struct mlx5_ifc_e_switch_cap_bits {
539         u8         vport_svlan_strip[0x1];
540         u8         vport_cvlan_strip[0x1];
541         u8         vport_svlan_insert[0x1];
542         u8         vport_cvlan_insert_if_not_exist[0x1];
543         u8         vport_cvlan_insert_overwrite[0x1];
544         u8         reserved_at_5[0x19];
545         u8         nic_vport_node_guid_modify[0x1];
546         u8         nic_vport_port_guid_modify[0x1];
547
548         u8         vxlan_encap_decap[0x1];
549         u8         nvgre_encap_decap[0x1];
550         u8         reserved_at_22[0x9];
551         u8         log_max_encap_headers[0x5];
552         u8         reserved_2b[0x6];
553         u8         max_encap_header_size[0xa];
554
555         u8         reserved_40[0x7c0];
556
557 };
558
559 struct mlx5_ifc_qos_cap_bits {
560         u8         packet_pacing[0x1];
561         u8         esw_scheduling[0x1];
562         u8         esw_bw_share[0x1];
563         u8         esw_rate_limit[0x1];
564         u8         reserved_at_4[0x1c];
565
566         u8         reserved_at_20[0x20];
567
568         u8         packet_pacing_max_rate[0x20];
569
570         u8         packet_pacing_min_rate[0x20];
571
572         u8         reserved_at_80[0x10];
573         u8         packet_pacing_rate_table_size[0x10];
574
575         u8         esw_element_type[0x10];
576         u8         esw_tsar_type[0x10];
577
578         u8         reserved_at_c0[0x10];
579         u8         max_qos_para_vport[0x10];
580
581         u8         max_tsar_bw_share[0x20];
582
583         u8         reserved_at_100[0x700];
584 };
585
586 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
587         u8         csum_cap[0x1];
588         u8         vlan_cap[0x1];
589         u8         lro_cap[0x1];
590         u8         lro_psh_flag[0x1];
591         u8         lro_time_stamp[0x1];
592         u8         reserved_at_5[0x2];
593         u8         wqe_vlan_insert[0x1];
594         u8         self_lb_en_modifiable[0x1];
595         u8         reserved_at_9[0x2];
596         u8         max_lso_cap[0x5];
597         u8         multi_pkt_send_wqe[0x2];
598         u8         wqe_inline_mode[0x2];
599         u8         rss_ind_tbl_cap[0x4];
600         u8         reg_umr_sq[0x1];
601         u8         scatter_fcs[0x1];
602         u8         reserved_at_1a[0x1];
603         u8         tunnel_lso_const_out_ip_id[0x1];
604         u8         reserved_at_1c[0x2];
605         u8         tunnel_statless_gre[0x1];
606         u8         tunnel_stateless_vxlan[0x1];
607
608         u8         swp[0x1];
609         u8         swp_csum[0x1];
610         u8         swp_lso[0x1];
611         u8         reserved_at_23[0x1d];
612
613         u8         reserved_at_40[0x10];
614         u8         lro_min_mss_size[0x10];
615
616         u8         reserved_at_60[0x120];
617
618         u8         lro_timer_supported_periods[4][0x20];
619
620         u8         reserved_at_200[0x600];
621 };
622
623 struct mlx5_ifc_roce_cap_bits {
624         u8         roce_apm[0x1];
625         u8         reserved_at_1[0x1f];
626
627         u8         reserved_at_20[0x60];
628
629         u8         reserved_at_80[0xc];
630         u8         l3_type[0x4];
631         u8         reserved_at_90[0x8];
632         u8         roce_version[0x8];
633
634         u8         reserved_at_a0[0x10];
635         u8         r_roce_dest_udp_port[0x10];
636
637         u8         r_roce_max_src_udp_port[0x10];
638         u8         r_roce_min_src_udp_port[0x10];
639
640         u8         reserved_at_e0[0x10];
641         u8         roce_address_table_size[0x10];
642
643         u8         reserved_at_100[0x700];
644 };
645
646 enum {
647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
650         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
656 };
657
658 enum {
659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
664         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
665         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
666         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
668 };
669
670 struct mlx5_ifc_atomic_caps_bits {
671         u8         reserved_at_0[0x40];
672
673         u8         atomic_req_8B_endianness_mode[0x2];
674         u8         reserved_at_42[0x4];
675         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
676
677         u8         reserved_at_47[0x19];
678
679         u8         reserved_at_60[0x20];
680
681         u8         reserved_at_80[0x10];
682         u8         atomic_operations[0x10];
683
684         u8         reserved_at_a0[0x10];
685         u8         atomic_size_qp[0x10];
686
687         u8         reserved_at_c0[0x10];
688         u8         atomic_size_dc[0x10];
689
690         u8         reserved_at_e0[0x720];
691 };
692
693 struct mlx5_ifc_odp_cap_bits {
694         u8         reserved_at_0[0x40];
695
696         u8         sig[0x1];
697         u8         reserved_at_41[0x1f];
698
699         u8         reserved_at_60[0x20];
700
701         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
702
703         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
704
705         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
706
707         u8         reserved_at_e0[0x720];
708 };
709
710 struct mlx5_ifc_calc_op {
711         u8        reserved_at_0[0x10];
712         u8        reserved_at_10[0x9];
713         u8        op_swap_endianness[0x1];
714         u8        op_min[0x1];
715         u8        op_xor[0x1];
716         u8        op_or[0x1];
717         u8        op_and[0x1];
718         u8        op_max[0x1];
719         u8        op_add[0x1];
720 };
721
722 struct mlx5_ifc_vector_calc_cap_bits {
723         u8         calc_matrix[0x1];
724         u8         reserved_at_1[0x1f];
725         u8         reserved_at_20[0x8];
726         u8         max_vec_count[0x8];
727         u8         reserved_at_30[0xd];
728         u8         max_chunk_size[0x3];
729         struct mlx5_ifc_calc_op calc0;
730         struct mlx5_ifc_calc_op calc1;
731         struct mlx5_ifc_calc_op calc2;
732         struct mlx5_ifc_calc_op calc3;
733
734         u8         reserved_at_e0[0x720];
735 };
736
737 enum {
738         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
739         MLX5_WQ_TYPE_CYCLIC       = 0x1,
740         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
741 };
742
743 enum {
744         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
745         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
746 };
747
748 enum {
749         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
750         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
751         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
752         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
753         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
754 };
755
756 enum {
757         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
758         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
759         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
760         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
761         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
762         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
763 };
764
765 enum {
766         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
767         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
768 };
769
770 enum {
771         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
772         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
773         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
774 };
775
776 enum {
777         MLX5_CAP_PORT_TYPE_IB  = 0x0,
778         MLX5_CAP_PORT_TYPE_ETH = 0x1,
779 };
780
781 enum {
782         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
783         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
784         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
785 };
786
787 struct mlx5_ifc_cmd_hca_cap_bits {
788         u8         reserved_at_0[0x80];
789
790         u8         log_max_srq_sz[0x8];
791         u8         log_max_qp_sz[0x8];
792         u8         reserved_at_90[0xb];
793         u8         log_max_qp[0x5];
794
795         u8         reserved_at_a0[0xb];
796         u8         log_max_srq[0x5];
797         u8         reserved_at_b0[0x10];
798
799         u8         reserved_at_c0[0x8];
800         u8         log_max_cq_sz[0x8];
801         u8         reserved_at_d0[0xb];
802         u8         log_max_cq[0x5];
803
804         u8         log_max_eq_sz[0x8];
805         u8         reserved_at_e8[0x2];
806         u8         log_max_mkey[0x6];
807         u8         reserved_at_f0[0xc];
808         u8         log_max_eq[0x4];
809
810         u8         max_indirection[0x8];
811         u8         fixed_buffer_size[0x1];
812         u8         log_max_mrw_sz[0x7];
813         u8         force_teardown[0x1];
814         u8         reserved_at_111[0x1];
815         u8         log_max_bsf_list_size[0x6];
816         u8         umr_extended_translation_offset[0x1];
817         u8         null_mkey[0x1];
818         u8         log_max_klm_list_size[0x6];
819
820         u8         reserved_at_120[0xa];
821         u8         log_max_ra_req_dc[0x6];
822         u8         reserved_at_130[0xa];
823         u8         log_max_ra_res_dc[0x6];
824
825         u8         reserved_at_140[0xa];
826         u8         log_max_ra_req_qp[0x6];
827         u8         reserved_at_150[0xa];
828         u8         log_max_ra_res_qp[0x6];
829
830         u8         end_pad[0x1];
831         u8         cc_query_allowed[0x1];
832         u8         cc_modify_allowed[0x1];
833         u8         start_pad[0x1];
834         u8         cache_line_128byte[0x1];
835         u8         reserved_at_165[0xb];
836         u8         gid_table_size[0x10];
837
838         u8         out_of_seq_cnt[0x1];
839         u8         vport_counters[0x1];
840         u8         retransmission_q_counters[0x1];
841         u8         reserved_at_183[0x1];
842         u8         modify_rq_counter_set_id[0x1];
843         u8         reserved_at_185[0x1];
844         u8         max_qp_cnt[0xa];
845         u8         pkey_table_size[0x10];
846
847         u8         vport_group_manager[0x1];
848         u8         vhca_group_manager[0x1];
849         u8         ib_virt[0x1];
850         u8         eth_virt[0x1];
851         u8         reserved_at_1a4[0x1];
852         u8         ets[0x1];
853         u8         nic_flow_table[0x1];
854         u8         eswitch_flow_table[0x1];
855         u8         early_vf_enable[0x1];
856         u8         mcam_reg[0x1];
857         u8         pcam_reg[0x1];
858         u8         local_ca_ack_delay[0x5];
859         u8         port_module_event[0x1];
860         u8         reserved_at_1b1[0x1];
861         u8         ports_check[0x1];
862         u8         reserved_at_1b3[0x1];
863         u8         disable_link_up[0x1];
864         u8         beacon_led[0x1];
865         u8         port_type[0x2];
866         u8         num_ports[0x8];
867
868         u8         reserved_at_1c0[0x1];
869         u8         pps[0x1];
870         u8         pps_modify[0x1];
871         u8         log_max_msg[0x5];
872         u8         reserved_at_1c8[0x4];
873         u8         max_tc[0x4];
874         u8         reserved_at_1d0[0x1];
875         u8         dcbx[0x1];
876         u8         reserved_at_1d2[0x3];
877         u8         fpga[0x1];
878         u8         rol_s[0x1];
879         u8         rol_g[0x1];
880         u8         reserved_at_1d8[0x1];
881         u8         wol_s[0x1];
882         u8         wol_g[0x1];
883         u8         wol_a[0x1];
884         u8         wol_b[0x1];
885         u8         wol_m[0x1];
886         u8         wol_u[0x1];
887         u8         wol_p[0x1];
888
889         u8         stat_rate_support[0x10];
890         u8         reserved_at_1f0[0xc];
891         u8         cqe_version[0x4];
892
893         u8         compact_address_vector[0x1];
894         u8         striding_rq[0x1];
895         u8         reserved_at_202[0x1];
896         u8         ipoib_enhanced_offloads[0x1];
897         u8         ipoib_basic_offloads[0x1];
898         u8         reserved_at_205[0x5];
899         u8         umr_fence[0x2];
900         u8         reserved_at_20c[0x3];
901         u8         drain_sigerr[0x1];
902         u8         cmdif_checksum[0x2];
903         u8         sigerr_cqe[0x1];
904         u8         reserved_at_213[0x1];
905         u8         wq_signature[0x1];
906         u8         sctr_data_cqe[0x1];
907         u8         reserved_at_216[0x1];
908         u8         sho[0x1];
909         u8         tph[0x1];
910         u8         rf[0x1];
911         u8         dct[0x1];
912         u8         qos[0x1];
913         u8         eth_net_offloads[0x1];
914         u8         roce[0x1];
915         u8         atomic[0x1];
916         u8         reserved_at_21f[0x1];
917
918         u8         cq_oi[0x1];
919         u8         cq_resize[0x1];
920         u8         cq_moderation[0x1];
921         u8         reserved_at_223[0x3];
922         u8         cq_eq_remap[0x1];
923         u8         pg[0x1];
924         u8         block_lb_mc[0x1];
925         u8         reserved_at_229[0x1];
926         u8         scqe_break_moderation[0x1];
927         u8         cq_period_start_from_cqe[0x1];
928         u8         cd[0x1];
929         u8         reserved_at_22d[0x1];
930         u8         apm[0x1];
931         u8         vector_calc[0x1];
932         u8         umr_ptr_rlky[0x1];
933         u8         imaicl[0x1];
934         u8         reserved_at_232[0x4];
935         u8         qkv[0x1];
936         u8         pkv[0x1];
937         u8         set_deth_sqpn[0x1];
938         u8         reserved_at_239[0x3];
939         u8         xrc[0x1];
940         u8         ud[0x1];
941         u8         uc[0x1];
942         u8         rc[0x1];
943
944         u8         uar_4k[0x1];
945         u8         reserved_at_241[0x9];
946         u8         uar_sz[0x6];
947         u8         reserved_at_250[0x8];
948         u8         log_pg_sz[0x8];
949
950         u8         bf[0x1];
951         u8         driver_version[0x1];
952         u8         pad_tx_eth_packet[0x1];
953         u8         reserved_at_263[0x8];
954         u8         log_bf_reg_size[0x5];
955
956         u8         reserved_at_270[0xb];
957         u8         lag_master[0x1];
958         u8         num_lag_ports[0x4];
959
960         u8         reserved_at_280[0x10];
961         u8         max_wqe_sz_sq[0x10];
962
963         u8         reserved_at_2a0[0x10];
964         u8         max_wqe_sz_rq[0x10];
965
966         u8         reserved_at_2c0[0x10];
967         u8         max_wqe_sz_sq_dc[0x10];
968
969         u8         reserved_at_2e0[0x7];
970         u8         max_qp_mcg[0x19];
971
972         u8         reserved_at_300[0x18];
973         u8         log_max_mcg[0x8];
974
975         u8         reserved_at_320[0x3];
976         u8         log_max_transport_domain[0x5];
977         u8         reserved_at_328[0x3];
978         u8         log_max_pd[0x5];
979         u8         reserved_at_330[0xb];
980         u8         log_max_xrcd[0x5];
981
982         u8         reserved_at_340[0x8];
983         u8         log_max_flow_counter_bulk[0x8];
984         u8         max_flow_counter[0x10];
985
986
987         u8         reserved_at_360[0x3];
988         u8         log_max_rq[0x5];
989         u8         reserved_at_368[0x3];
990         u8         log_max_sq[0x5];
991         u8         reserved_at_370[0x3];
992         u8         log_max_tir[0x5];
993         u8         reserved_at_378[0x3];
994         u8         log_max_tis[0x5];
995
996         u8         basic_cyclic_rcv_wqe[0x1];
997         u8         reserved_at_381[0x2];
998         u8         log_max_rmp[0x5];
999         u8         reserved_at_388[0x3];
1000         u8         log_max_rqt[0x5];
1001         u8         reserved_at_390[0x3];
1002         u8         log_max_rqt_size[0x5];
1003         u8         reserved_at_398[0x3];
1004         u8         log_max_tis_per_sq[0x5];
1005
1006         u8         reserved_at_3a0[0x3];
1007         u8         log_max_stride_sz_rq[0x5];
1008         u8         reserved_at_3a8[0x3];
1009         u8         log_min_stride_sz_rq[0x5];
1010         u8         reserved_at_3b0[0x3];
1011         u8         log_max_stride_sz_sq[0x5];
1012         u8         reserved_at_3b8[0x3];
1013         u8         log_min_stride_sz_sq[0x5];
1014
1015         u8         reserved_at_3c0[0x1b];
1016         u8         log_max_wq_sz[0x5];
1017
1018         u8         nic_vport_change_event[0x1];
1019         u8         reserved_at_3e1[0xa];
1020         u8         log_max_vlan_list[0x5];
1021         u8         reserved_at_3f0[0x3];
1022         u8         log_max_current_mc_list[0x5];
1023         u8         reserved_at_3f8[0x3];
1024         u8         log_max_current_uc_list[0x5];
1025
1026         u8         reserved_at_400[0x80];
1027
1028         u8         reserved_at_480[0x3];
1029         u8         log_max_l2_table[0x5];
1030         u8         reserved_at_488[0x8];
1031         u8         log_uar_page_sz[0x10];
1032
1033         u8         reserved_at_4a0[0x20];
1034         u8         device_frequency_mhz[0x20];
1035         u8         device_frequency_khz[0x20];
1036
1037         u8         reserved_at_500[0x20];
1038         u8         num_of_uars_per_page[0x20];
1039         u8         reserved_at_540[0x40];
1040
1041         u8         reserved_at_580[0x3f];
1042         u8         cqe_compression[0x1];
1043
1044         u8         cqe_compression_timeout[0x10];
1045         u8         cqe_compression_max_num[0x10];
1046
1047         u8         reserved_at_5e0[0x10];
1048         u8         tag_matching[0x1];
1049         u8         rndv_offload_rc[0x1];
1050         u8         rndv_offload_dc[0x1];
1051         u8         log_tag_matching_list_sz[0x5];
1052         u8         reserved_at_5f8[0x3];
1053         u8         log_max_xrq[0x5];
1054
1055         u8         reserved_at_600[0x200];
1056 };
1057
1058 enum mlx5_flow_destination_type {
1059         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1060         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1061         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1062
1063         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1064 };
1065
1066 struct mlx5_ifc_dest_format_struct_bits {
1067         u8         destination_type[0x8];
1068         u8         destination_id[0x18];
1069
1070         u8         reserved_at_20[0x20];
1071 };
1072
1073 struct mlx5_ifc_flow_counter_list_bits {
1074         u8         reserved_at_0[0x10];
1075         u8         flow_counter_id[0x10];
1076
1077         u8         reserved_at_20[0x20];
1078 };
1079
1080 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1081         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1082         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1083         u8         reserved_at_0[0x40];
1084 };
1085
1086 struct mlx5_ifc_fte_match_param_bits {
1087         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1088
1089         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1090
1091         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1092
1093         u8         reserved_at_600[0xa00];
1094 };
1095
1096 enum {
1097         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1098         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1099         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1100         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1101         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1102 };
1103
1104 struct mlx5_ifc_rx_hash_field_select_bits {
1105         u8         l3_prot_type[0x1];
1106         u8         l4_prot_type[0x1];
1107         u8         selected_fields[0x1e];
1108 };
1109
1110 enum {
1111         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1112         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1113 };
1114
1115 enum {
1116         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1117         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1118 };
1119
1120 struct mlx5_ifc_wq_bits {
1121         u8         wq_type[0x4];
1122         u8         wq_signature[0x1];
1123         u8         end_padding_mode[0x2];
1124         u8         cd_slave[0x1];
1125         u8         reserved_at_8[0x18];
1126
1127         u8         hds_skip_first_sge[0x1];
1128         u8         log2_hds_buf_size[0x3];
1129         u8         reserved_at_24[0x7];
1130         u8         page_offset[0x5];
1131         u8         lwm[0x10];
1132
1133         u8         reserved_at_40[0x8];
1134         u8         pd[0x18];
1135
1136         u8         reserved_at_60[0x8];
1137         u8         uar_page[0x18];
1138
1139         u8         dbr_addr[0x40];
1140
1141         u8         hw_counter[0x20];
1142
1143         u8         sw_counter[0x20];
1144
1145         u8         reserved_at_100[0xc];
1146         u8         log_wq_stride[0x4];
1147         u8         reserved_at_110[0x3];
1148         u8         log_wq_pg_sz[0x5];
1149         u8         reserved_at_118[0x3];
1150         u8         log_wq_sz[0x5];
1151
1152         u8         reserved_at_120[0x15];
1153         u8         log_wqe_num_of_strides[0x3];
1154         u8         two_byte_shift_en[0x1];
1155         u8         reserved_at_139[0x4];
1156         u8         log_wqe_stride_size[0x3];
1157
1158         u8         reserved_at_140[0x4c0];
1159
1160         struct mlx5_ifc_cmd_pas_bits pas[0];
1161 };
1162
1163 struct mlx5_ifc_rq_num_bits {
1164         u8         reserved_at_0[0x8];
1165         u8         rq_num[0x18];
1166 };
1167
1168 struct mlx5_ifc_mac_address_layout_bits {
1169         u8         reserved_at_0[0x10];
1170         u8         mac_addr_47_32[0x10];
1171
1172         u8         mac_addr_31_0[0x20];
1173 };
1174
1175 struct mlx5_ifc_vlan_layout_bits {
1176         u8         reserved_at_0[0x14];
1177         u8         vlan[0x0c];
1178
1179         u8         reserved_at_20[0x20];
1180 };
1181
1182 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1183         u8         reserved_at_0[0xa0];
1184
1185         u8         min_time_between_cnps[0x20];
1186
1187         u8         reserved_at_c0[0x12];
1188         u8         cnp_dscp[0x6];
1189         u8         reserved_at_d8[0x5];
1190         u8         cnp_802p_prio[0x3];
1191
1192         u8         reserved_at_e0[0x720];
1193 };
1194
1195 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1196         u8         reserved_at_0[0x60];
1197
1198         u8         reserved_at_60[0x4];
1199         u8         clamp_tgt_rate[0x1];
1200         u8         reserved_at_65[0x3];
1201         u8         clamp_tgt_rate_after_time_inc[0x1];
1202         u8         reserved_at_69[0x17];
1203
1204         u8         reserved_at_80[0x20];
1205
1206         u8         rpg_time_reset[0x20];
1207
1208         u8         rpg_byte_reset[0x20];
1209
1210         u8         rpg_threshold[0x20];
1211
1212         u8         rpg_max_rate[0x20];
1213
1214         u8         rpg_ai_rate[0x20];
1215
1216         u8         rpg_hai_rate[0x20];
1217
1218         u8         rpg_gd[0x20];
1219
1220         u8         rpg_min_dec_fac[0x20];
1221
1222         u8         rpg_min_rate[0x20];
1223
1224         u8         reserved_at_1c0[0xe0];
1225
1226         u8         rate_to_set_on_first_cnp[0x20];
1227
1228         u8         dce_tcp_g[0x20];
1229
1230         u8         dce_tcp_rtt[0x20];
1231
1232         u8         rate_reduce_monitor_period[0x20];
1233
1234         u8         reserved_at_320[0x20];
1235
1236         u8         initial_alpha_value[0x20];
1237
1238         u8         reserved_at_360[0x4a0];
1239 };
1240
1241 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1242         u8         reserved_at_0[0x80];
1243
1244         u8         rppp_max_rps[0x20];
1245
1246         u8         rpg_time_reset[0x20];
1247
1248         u8         rpg_byte_reset[0x20];
1249
1250         u8         rpg_threshold[0x20];
1251
1252         u8         rpg_max_rate[0x20];
1253
1254         u8         rpg_ai_rate[0x20];
1255
1256         u8         rpg_hai_rate[0x20];
1257
1258         u8         rpg_gd[0x20];
1259
1260         u8         rpg_min_dec_fac[0x20];
1261
1262         u8         rpg_min_rate[0x20];
1263
1264         u8         reserved_at_1c0[0x640];
1265 };
1266
1267 enum {
1268         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1269         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1270         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1271 };
1272
1273 struct mlx5_ifc_resize_field_select_bits {
1274         u8         resize_field_select[0x20];
1275 };
1276
1277 enum {
1278         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1279         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1280         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1281         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1282 };
1283
1284 struct mlx5_ifc_modify_field_select_bits {
1285         u8         modify_field_select[0x20];
1286 };
1287
1288 struct mlx5_ifc_field_select_r_roce_np_bits {
1289         u8         field_select_r_roce_np[0x20];
1290 };
1291
1292 struct mlx5_ifc_field_select_r_roce_rp_bits {
1293         u8         field_select_r_roce_rp[0x20];
1294 };
1295
1296 enum {
1297         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1298         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1299         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1300         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1301         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1302         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1303         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1304         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1305         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1306         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1307 };
1308
1309 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1310         u8         field_select_8021qaurp[0x20];
1311 };
1312
1313 struct mlx5_ifc_phys_layer_cntrs_bits {
1314         u8         time_since_last_clear_high[0x20];
1315
1316         u8         time_since_last_clear_low[0x20];
1317
1318         u8         symbol_errors_high[0x20];
1319
1320         u8         symbol_errors_low[0x20];
1321
1322         u8         sync_headers_errors_high[0x20];
1323
1324         u8         sync_headers_errors_low[0x20];
1325
1326         u8         edpl_bip_errors_lane0_high[0x20];
1327
1328         u8         edpl_bip_errors_lane0_low[0x20];
1329
1330         u8         edpl_bip_errors_lane1_high[0x20];
1331
1332         u8         edpl_bip_errors_lane1_low[0x20];
1333
1334         u8         edpl_bip_errors_lane2_high[0x20];
1335
1336         u8         edpl_bip_errors_lane2_low[0x20];
1337
1338         u8         edpl_bip_errors_lane3_high[0x20];
1339
1340         u8         edpl_bip_errors_lane3_low[0x20];
1341
1342         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1343
1344         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1345
1346         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1347
1348         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1349
1350         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1351
1352         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1353
1354         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1355
1356         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1357
1358         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1359
1360         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1361
1362         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1363
1364         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1365
1366         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1367
1368         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1369
1370         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1371
1372         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1373
1374         u8         rs_fec_corrected_blocks_high[0x20];
1375
1376         u8         rs_fec_corrected_blocks_low[0x20];
1377
1378         u8         rs_fec_uncorrectable_blocks_high[0x20];
1379
1380         u8         rs_fec_uncorrectable_blocks_low[0x20];
1381
1382         u8         rs_fec_no_errors_blocks_high[0x20];
1383
1384         u8         rs_fec_no_errors_blocks_low[0x20];
1385
1386         u8         rs_fec_single_error_blocks_high[0x20];
1387
1388         u8         rs_fec_single_error_blocks_low[0x20];
1389
1390         u8         rs_fec_corrected_symbols_total_high[0x20];
1391
1392         u8         rs_fec_corrected_symbols_total_low[0x20];
1393
1394         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1395
1396         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1397
1398         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1399
1400         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1401
1402         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1403
1404         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1405
1406         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1407
1408         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1409
1410         u8         link_down_events[0x20];
1411
1412         u8         successful_recovery_events[0x20];
1413
1414         u8         reserved_at_640[0x180];
1415 };
1416
1417 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1418         u8         time_since_last_clear_high[0x20];
1419
1420         u8         time_since_last_clear_low[0x20];
1421
1422         u8         phy_received_bits_high[0x20];
1423
1424         u8         phy_received_bits_low[0x20];
1425
1426         u8         phy_symbol_errors_high[0x20];
1427
1428         u8         phy_symbol_errors_low[0x20];
1429
1430         u8         phy_corrected_bits_high[0x20];
1431
1432         u8         phy_corrected_bits_low[0x20];
1433
1434         u8         phy_corrected_bits_lane0_high[0x20];
1435
1436         u8         phy_corrected_bits_lane0_low[0x20];
1437
1438         u8         phy_corrected_bits_lane1_high[0x20];
1439
1440         u8         phy_corrected_bits_lane1_low[0x20];
1441
1442         u8         phy_corrected_bits_lane2_high[0x20];
1443
1444         u8         phy_corrected_bits_lane2_low[0x20];
1445
1446         u8         phy_corrected_bits_lane3_high[0x20];
1447
1448         u8         phy_corrected_bits_lane3_low[0x20];
1449
1450         u8         reserved_at_200[0x5c0];
1451 };
1452
1453 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1454         u8         symbol_error_counter[0x10];
1455
1456         u8         link_error_recovery_counter[0x8];
1457
1458         u8         link_downed_counter[0x8];
1459
1460         u8         port_rcv_errors[0x10];
1461
1462         u8         port_rcv_remote_physical_errors[0x10];
1463
1464         u8         port_rcv_switch_relay_errors[0x10];
1465
1466         u8         port_xmit_discards[0x10];
1467
1468         u8         port_xmit_constraint_errors[0x8];
1469
1470         u8         port_rcv_constraint_errors[0x8];
1471
1472         u8         reserved_at_70[0x8];
1473
1474         u8         link_overrun_errors[0x8];
1475
1476         u8         reserved_at_80[0x10];
1477
1478         u8         vl_15_dropped[0x10];
1479
1480         u8         reserved_at_a0[0x80];
1481
1482         u8         port_xmit_wait[0x20];
1483 };
1484
1485 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1486         u8         transmit_queue_high[0x20];
1487
1488         u8         transmit_queue_low[0x20];
1489
1490         u8         reserved_at_40[0x780];
1491 };
1492
1493 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1494         u8         rx_octets_high[0x20];
1495
1496         u8         rx_octets_low[0x20];
1497
1498         u8         reserved_at_40[0xc0];
1499
1500         u8         rx_frames_high[0x20];
1501
1502         u8         rx_frames_low[0x20];
1503
1504         u8         tx_octets_high[0x20];
1505
1506         u8         tx_octets_low[0x20];
1507
1508         u8         reserved_at_180[0xc0];
1509
1510         u8         tx_frames_high[0x20];
1511
1512         u8         tx_frames_low[0x20];
1513
1514         u8         rx_pause_high[0x20];
1515
1516         u8         rx_pause_low[0x20];
1517
1518         u8         rx_pause_duration_high[0x20];
1519
1520         u8         rx_pause_duration_low[0x20];
1521
1522         u8         tx_pause_high[0x20];
1523
1524         u8         tx_pause_low[0x20];
1525
1526         u8         tx_pause_duration_high[0x20];
1527
1528         u8         tx_pause_duration_low[0x20];
1529
1530         u8         rx_pause_transition_high[0x20];
1531
1532         u8         rx_pause_transition_low[0x20];
1533
1534         u8         reserved_at_3c0[0x400];
1535 };
1536
1537 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1538         u8         port_transmit_wait_high[0x20];
1539
1540         u8         port_transmit_wait_low[0x20];
1541
1542         u8         reserved_at_40[0x780];
1543 };
1544
1545 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1546         u8         dot3stats_alignment_errors_high[0x20];
1547
1548         u8         dot3stats_alignment_errors_low[0x20];
1549
1550         u8         dot3stats_fcs_errors_high[0x20];
1551
1552         u8         dot3stats_fcs_errors_low[0x20];
1553
1554         u8         dot3stats_single_collision_frames_high[0x20];
1555
1556         u8         dot3stats_single_collision_frames_low[0x20];
1557
1558         u8         dot3stats_multiple_collision_frames_high[0x20];
1559
1560         u8         dot3stats_multiple_collision_frames_low[0x20];
1561
1562         u8         dot3stats_sqe_test_errors_high[0x20];
1563
1564         u8         dot3stats_sqe_test_errors_low[0x20];
1565
1566         u8         dot3stats_deferred_transmissions_high[0x20];
1567
1568         u8         dot3stats_deferred_transmissions_low[0x20];
1569
1570         u8         dot3stats_late_collisions_high[0x20];
1571
1572         u8         dot3stats_late_collisions_low[0x20];
1573
1574         u8         dot3stats_excessive_collisions_high[0x20];
1575
1576         u8         dot3stats_excessive_collisions_low[0x20];
1577
1578         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1579
1580         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1581
1582         u8         dot3stats_carrier_sense_errors_high[0x20];
1583
1584         u8         dot3stats_carrier_sense_errors_low[0x20];
1585
1586         u8         dot3stats_frame_too_longs_high[0x20];
1587
1588         u8         dot3stats_frame_too_longs_low[0x20];
1589
1590         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1591
1592         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1593
1594         u8         dot3stats_symbol_errors_high[0x20];
1595
1596         u8         dot3stats_symbol_errors_low[0x20];
1597
1598         u8         dot3control_in_unknown_opcodes_high[0x20];
1599
1600         u8         dot3control_in_unknown_opcodes_low[0x20];
1601
1602         u8         dot3in_pause_frames_high[0x20];
1603
1604         u8         dot3in_pause_frames_low[0x20];
1605
1606         u8         dot3out_pause_frames_high[0x20];
1607
1608         u8         dot3out_pause_frames_low[0x20];
1609
1610         u8         reserved_at_400[0x3c0];
1611 };
1612
1613 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1614         u8         ether_stats_drop_events_high[0x20];
1615
1616         u8         ether_stats_drop_events_low[0x20];
1617
1618         u8         ether_stats_octets_high[0x20];
1619
1620         u8         ether_stats_octets_low[0x20];
1621
1622         u8         ether_stats_pkts_high[0x20];
1623
1624         u8         ether_stats_pkts_low[0x20];
1625
1626         u8         ether_stats_broadcast_pkts_high[0x20];
1627
1628         u8         ether_stats_broadcast_pkts_low[0x20];
1629
1630         u8         ether_stats_multicast_pkts_high[0x20];
1631
1632         u8         ether_stats_multicast_pkts_low[0x20];
1633
1634         u8         ether_stats_crc_align_errors_high[0x20];
1635
1636         u8         ether_stats_crc_align_errors_low[0x20];
1637
1638         u8         ether_stats_undersize_pkts_high[0x20];
1639
1640         u8         ether_stats_undersize_pkts_low[0x20];
1641
1642         u8         ether_stats_oversize_pkts_high[0x20];
1643
1644         u8         ether_stats_oversize_pkts_low[0x20];
1645
1646         u8         ether_stats_fragments_high[0x20];
1647
1648         u8         ether_stats_fragments_low[0x20];
1649
1650         u8         ether_stats_jabbers_high[0x20];
1651
1652         u8         ether_stats_jabbers_low[0x20];
1653
1654         u8         ether_stats_collisions_high[0x20];
1655
1656         u8         ether_stats_collisions_low[0x20];
1657
1658         u8         ether_stats_pkts64octets_high[0x20];
1659
1660         u8         ether_stats_pkts64octets_low[0x20];
1661
1662         u8         ether_stats_pkts65to127octets_high[0x20];
1663
1664         u8         ether_stats_pkts65to127octets_low[0x20];
1665
1666         u8         ether_stats_pkts128to255octets_high[0x20];
1667
1668         u8         ether_stats_pkts128to255octets_low[0x20];
1669
1670         u8         ether_stats_pkts256to511octets_high[0x20];
1671
1672         u8         ether_stats_pkts256to511octets_low[0x20];
1673
1674         u8         ether_stats_pkts512to1023octets_high[0x20];
1675
1676         u8         ether_stats_pkts512to1023octets_low[0x20];
1677
1678         u8         ether_stats_pkts1024to1518octets_high[0x20];
1679
1680         u8         ether_stats_pkts1024to1518octets_low[0x20];
1681
1682         u8         ether_stats_pkts1519to2047octets_high[0x20];
1683
1684         u8         ether_stats_pkts1519to2047octets_low[0x20];
1685
1686         u8         ether_stats_pkts2048to4095octets_high[0x20];
1687
1688         u8         ether_stats_pkts2048to4095octets_low[0x20];
1689
1690         u8         ether_stats_pkts4096to8191octets_high[0x20];
1691
1692         u8         ether_stats_pkts4096to8191octets_low[0x20];
1693
1694         u8         ether_stats_pkts8192to10239octets_high[0x20];
1695
1696         u8         ether_stats_pkts8192to10239octets_low[0x20];
1697
1698         u8         reserved_at_540[0x280];
1699 };
1700
1701 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1702         u8         if_in_octets_high[0x20];
1703
1704         u8         if_in_octets_low[0x20];
1705
1706         u8         if_in_ucast_pkts_high[0x20];
1707
1708         u8         if_in_ucast_pkts_low[0x20];
1709
1710         u8         if_in_discards_high[0x20];
1711
1712         u8         if_in_discards_low[0x20];
1713
1714         u8         if_in_errors_high[0x20];
1715
1716         u8         if_in_errors_low[0x20];
1717
1718         u8         if_in_unknown_protos_high[0x20];
1719
1720         u8         if_in_unknown_protos_low[0x20];
1721
1722         u8         if_out_octets_high[0x20];
1723
1724         u8         if_out_octets_low[0x20];
1725
1726         u8         if_out_ucast_pkts_high[0x20];
1727
1728         u8         if_out_ucast_pkts_low[0x20];
1729
1730         u8         if_out_discards_high[0x20];
1731
1732         u8         if_out_discards_low[0x20];
1733
1734         u8         if_out_errors_high[0x20];
1735
1736         u8         if_out_errors_low[0x20];
1737
1738         u8         if_in_multicast_pkts_high[0x20];
1739
1740         u8         if_in_multicast_pkts_low[0x20];
1741
1742         u8         if_in_broadcast_pkts_high[0x20];
1743
1744         u8         if_in_broadcast_pkts_low[0x20];
1745
1746         u8         if_out_multicast_pkts_high[0x20];
1747
1748         u8         if_out_multicast_pkts_low[0x20];
1749
1750         u8         if_out_broadcast_pkts_high[0x20];
1751
1752         u8         if_out_broadcast_pkts_low[0x20];
1753
1754         u8         reserved_at_340[0x480];
1755 };
1756
1757 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1758         u8         a_frames_transmitted_ok_high[0x20];
1759
1760         u8         a_frames_transmitted_ok_low[0x20];
1761
1762         u8         a_frames_received_ok_high[0x20];
1763
1764         u8         a_frames_received_ok_low[0x20];
1765
1766         u8         a_frame_check_sequence_errors_high[0x20];
1767
1768         u8         a_frame_check_sequence_errors_low[0x20];
1769
1770         u8         a_alignment_errors_high[0x20];
1771
1772         u8         a_alignment_errors_low[0x20];
1773
1774         u8         a_octets_transmitted_ok_high[0x20];
1775
1776         u8         a_octets_transmitted_ok_low[0x20];
1777
1778         u8         a_octets_received_ok_high[0x20];
1779
1780         u8         a_octets_received_ok_low[0x20];
1781
1782         u8         a_multicast_frames_xmitted_ok_high[0x20];
1783
1784         u8         a_multicast_frames_xmitted_ok_low[0x20];
1785
1786         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1787
1788         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1789
1790         u8         a_multicast_frames_received_ok_high[0x20];
1791
1792         u8         a_multicast_frames_received_ok_low[0x20];
1793
1794         u8         a_broadcast_frames_received_ok_high[0x20];
1795
1796         u8         a_broadcast_frames_received_ok_low[0x20];
1797
1798         u8         a_in_range_length_errors_high[0x20];
1799
1800         u8         a_in_range_length_errors_low[0x20];
1801
1802         u8         a_out_of_range_length_field_high[0x20];
1803
1804         u8         a_out_of_range_length_field_low[0x20];
1805
1806         u8         a_frame_too_long_errors_high[0x20];
1807
1808         u8         a_frame_too_long_errors_low[0x20];
1809
1810         u8         a_symbol_error_during_carrier_high[0x20];
1811
1812         u8         a_symbol_error_during_carrier_low[0x20];
1813
1814         u8         a_mac_control_frames_transmitted_high[0x20];
1815
1816         u8         a_mac_control_frames_transmitted_low[0x20];
1817
1818         u8         a_mac_control_frames_received_high[0x20];
1819
1820         u8         a_mac_control_frames_received_low[0x20];
1821
1822         u8         a_unsupported_opcodes_received_high[0x20];
1823
1824         u8         a_unsupported_opcodes_received_low[0x20];
1825
1826         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1827
1828         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1829
1830         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1831
1832         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1833
1834         u8         reserved_at_4c0[0x300];
1835 };
1836
1837 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1838         u8         life_time_counter_high[0x20];
1839
1840         u8         life_time_counter_low[0x20];
1841
1842         u8         rx_errors[0x20];
1843
1844         u8         tx_errors[0x20];
1845
1846         u8         l0_to_recovery_eieos[0x20];
1847
1848         u8         l0_to_recovery_ts[0x20];
1849
1850         u8         l0_to_recovery_framing[0x20];
1851
1852         u8         l0_to_recovery_retrain[0x20];
1853
1854         u8         crc_error_dllp[0x20];
1855
1856         u8         crc_error_tlp[0x20];
1857
1858         u8         reserved_at_140[0x680];
1859 };
1860
1861 struct mlx5_ifc_cmd_inter_comp_event_bits {
1862         u8         command_completion_vector[0x20];
1863
1864         u8         reserved_at_20[0xc0];
1865 };
1866
1867 struct mlx5_ifc_stall_vl_event_bits {
1868         u8         reserved_at_0[0x18];
1869         u8         port_num[0x1];
1870         u8         reserved_at_19[0x3];
1871         u8         vl[0x4];
1872
1873         u8         reserved_at_20[0xa0];
1874 };
1875
1876 struct mlx5_ifc_db_bf_congestion_event_bits {
1877         u8         event_subtype[0x8];
1878         u8         reserved_at_8[0x8];
1879         u8         congestion_level[0x8];
1880         u8         reserved_at_18[0x8];
1881
1882         u8         reserved_at_20[0xa0];
1883 };
1884
1885 struct mlx5_ifc_gpio_event_bits {
1886         u8         reserved_at_0[0x60];
1887
1888         u8         gpio_event_hi[0x20];
1889
1890         u8         gpio_event_lo[0x20];
1891
1892         u8         reserved_at_a0[0x40];
1893 };
1894
1895 struct mlx5_ifc_port_state_change_event_bits {
1896         u8         reserved_at_0[0x40];
1897
1898         u8         port_num[0x4];
1899         u8         reserved_at_44[0x1c];
1900
1901         u8         reserved_at_60[0x80];
1902 };
1903
1904 struct mlx5_ifc_dropped_packet_logged_bits {
1905         u8         reserved_at_0[0xe0];
1906 };
1907
1908 enum {
1909         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1910         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1911 };
1912
1913 struct mlx5_ifc_cq_error_bits {
1914         u8         reserved_at_0[0x8];
1915         u8         cqn[0x18];
1916
1917         u8         reserved_at_20[0x20];
1918
1919         u8         reserved_at_40[0x18];
1920         u8         syndrome[0x8];
1921
1922         u8         reserved_at_60[0x80];
1923 };
1924
1925 struct mlx5_ifc_rdma_page_fault_event_bits {
1926         u8         bytes_committed[0x20];
1927
1928         u8         r_key[0x20];
1929
1930         u8         reserved_at_40[0x10];
1931         u8         packet_len[0x10];
1932
1933         u8         rdma_op_len[0x20];
1934
1935         u8         rdma_va[0x40];
1936
1937         u8         reserved_at_c0[0x5];
1938         u8         rdma[0x1];
1939         u8         write[0x1];
1940         u8         requestor[0x1];
1941         u8         qp_number[0x18];
1942 };
1943
1944 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1945         u8         bytes_committed[0x20];
1946
1947         u8         reserved_at_20[0x10];
1948         u8         wqe_index[0x10];
1949
1950         u8         reserved_at_40[0x10];
1951         u8         len[0x10];
1952
1953         u8         reserved_at_60[0x60];
1954
1955         u8         reserved_at_c0[0x5];
1956         u8         rdma[0x1];
1957         u8         write_read[0x1];
1958         u8         requestor[0x1];
1959         u8         qpn[0x18];
1960 };
1961
1962 struct mlx5_ifc_qp_events_bits {
1963         u8         reserved_at_0[0xa0];
1964
1965         u8         type[0x8];
1966         u8         reserved_at_a8[0x18];
1967
1968         u8         reserved_at_c0[0x8];
1969         u8         qpn_rqn_sqn[0x18];
1970 };
1971
1972 struct mlx5_ifc_dct_events_bits {
1973         u8         reserved_at_0[0xc0];
1974
1975         u8         reserved_at_c0[0x8];
1976         u8         dct_number[0x18];
1977 };
1978
1979 struct mlx5_ifc_comp_event_bits {
1980         u8         reserved_at_0[0xc0];
1981
1982         u8         reserved_at_c0[0x8];
1983         u8         cq_number[0x18];
1984 };
1985
1986 enum {
1987         MLX5_QPC_STATE_RST        = 0x0,
1988         MLX5_QPC_STATE_INIT       = 0x1,
1989         MLX5_QPC_STATE_RTR        = 0x2,
1990         MLX5_QPC_STATE_RTS        = 0x3,
1991         MLX5_QPC_STATE_SQER       = 0x4,
1992         MLX5_QPC_STATE_ERR        = 0x6,
1993         MLX5_QPC_STATE_SQD        = 0x7,
1994         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1995 };
1996
1997 enum {
1998         MLX5_QPC_ST_RC            = 0x0,
1999         MLX5_QPC_ST_UC            = 0x1,
2000         MLX5_QPC_ST_UD            = 0x2,
2001         MLX5_QPC_ST_XRC           = 0x3,
2002         MLX5_QPC_ST_DCI           = 0x5,
2003         MLX5_QPC_ST_QP0           = 0x7,
2004         MLX5_QPC_ST_QP1           = 0x8,
2005         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2006         MLX5_QPC_ST_REG_UMR       = 0xc,
2007 };
2008
2009 enum {
2010         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2011         MLX5_QPC_PM_STATE_REARM     = 0x1,
2012         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2013         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2014 };
2015
2016 enum {
2017         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2018         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2019 };
2020
2021 enum {
2022         MLX5_QPC_MTU_256_BYTES        = 0x1,
2023         MLX5_QPC_MTU_512_BYTES        = 0x2,
2024         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2025         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2026         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2027         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2028 };
2029
2030 enum {
2031         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2032         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2033         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2034         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2035         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2036         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2037         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2038         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2039 };
2040
2041 enum {
2042         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2043         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2044         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2045 };
2046
2047 enum {
2048         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2049         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2050         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2051 };
2052
2053 struct mlx5_ifc_qpc_bits {
2054         u8         state[0x4];
2055         u8         lag_tx_port_affinity[0x4];
2056         u8         st[0x8];
2057         u8         reserved_at_10[0x3];
2058         u8         pm_state[0x2];
2059         u8         reserved_at_15[0x7];
2060         u8         end_padding_mode[0x2];
2061         u8         reserved_at_1e[0x2];
2062
2063         u8         wq_signature[0x1];
2064         u8         block_lb_mc[0x1];
2065         u8         atomic_like_write_en[0x1];
2066         u8         latency_sensitive[0x1];
2067         u8         reserved_at_24[0x1];
2068         u8         drain_sigerr[0x1];
2069         u8         reserved_at_26[0x2];
2070         u8         pd[0x18];
2071
2072         u8         mtu[0x3];
2073         u8         log_msg_max[0x5];
2074         u8         reserved_at_48[0x1];
2075         u8         log_rq_size[0x4];
2076         u8         log_rq_stride[0x3];
2077         u8         no_sq[0x1];
2078         u8         log_sq_size[0x4];
2079         u8         reserved_at_55[0x6];
2080         u8         rlky[0x1];
2081         u8         ulp_stateless_offload_mode[0x4];
2082
2083         u8         counter_set_id[0x8];
2084         u8         uar_page[0x18];
2085
2086         u8         reserved_at_80[0x8];
2087         u8         user_index[0x18];
2088
2089         u8         reserved_at_a0[0x3];
2090         u8         log_page_size[0x5];
2091         u8         remote_qpn[0x18];
2092
2093         struct mlx5_ifc_ads_bits primary_address_path;
2094
2095         struct mlx5_ifc_ads_bits secondary_address_path;
2096
2097         u8         log_ack_req_freq[0x4];
2098         u8         reserved_at_384[0x4];
2099         u8         log_sra_max[0x3];
2100         u8         reserved_at_38b[0x2];
2101         u8         retry_count[0x3];
2102         u8         rnr_retry[0x3];
2103         u8         reserved_at_393[0x1];
2104         u8         fre[0x1];
2105         u8         cur_rnr_retry[0x3];
2106         u8         cur_retry_count[0x3];
2107         u8         reserved_at_39b[0x5];
2108
2109         u8         reserved_at_3a0[0x20];
2110
2111         u8         reserved_at_3c0[0x8];
2112         u8         next_send_psn[0x18];
2113
2114         u8         reserved_at_3e0[0x8];
2115         u8         cqn_snd[0x18];
2116
2117         u8         reserved_at_400[0x8];
2118         u8         deth_sqpn[0x18];
2119
2120         u8         reserved_at_420[0x20];
2121
2122         u8         reserved_at_440[0x8];
2123         u8         last_acked_psn[0x18];
2124
2125         u8         reserved_at_460[0x8];
2126         u8         ssn[0x18];
2127
2128         u8         reserved_at_480[0x8];
2129         u8         log_rra_max[0x3];
2130         u8         reserved_at_48b[0x1];
2131         u8         atomic_mode[0x4];
2132         u8         rre[0x1];
2133         u8         rwe[0x1];
2134         u8         rae[0x1];
2135         u8         reserved_at_493[0x1];
2136         u8         page_offset[0x6];
2137         u8         reserved_at_49a[0x3];
2138         u8         cd_slave_receive[0x1];
2139         u8         cd_slave_send[0x1];
2140         u8         cd_master[0x1];
2141
2142         u8         reserved_at_4a0[0x3];
2143         u8         min_rnr_nak[0x5];
2144         u8         next_rcv_psn[0x18];
2145
2146         u8         reserved_at_4c0[0x8];
2147         u8         xrcd[0x18];
2148
2149         u8         reserved_at_4e0[0x8];
2150         u8         cqn_rcv[0x18];
2151
2152         u8         dbr_addr[0x40];
2153
2154         u8         q_key[0x20];
2155
2156         u8         reserved_at_560[0x5];
2157         u8         rq_type[0x3];
2158         u8         srqn_rmpn_xrqn[0x18];
2159
2160         u8         reserved_at_580[0x8];
2161         u8         rmsn[0x18];
2162
2163         u8         hw_sq_wqebb_counter[0x10];
2164         u8         sw_sq_wqebb_counter[0x10];
2165
2166         u8         hw_rq_counter[0x20];
2167
2168         u8         sw_rq_counter[0x20];
2169
2170         u8         reserved_at_600[0x20];
2171
2172         u8         reserved_at_620[0xf];
2173         u8         cgs[0x1];
2174         u8         cs_req[0x8];
2175         u8         cs_res[0x8];
2176
2177         u8         dc_access_key[0x40];
2178
2179         u8         reserved_at_680[0xc0];
2180 };
2181
2182 struct mlx5_ifc_roce_addr_layout_bits {
2183         u8         source_l3_address[16][0x8];
2184
2185         u8         reserved_at_80[0x3];
2186         u8         vlan_valid[0x1];
2187         u8         vlan_id[0xc];
2188         u8         source_mac_47_32[0x10];
2189
2190         u8         source_mac_31_0[0x20];
2191
2192         u8         reserved_at_c0[0x14];
2193         u8         roce_l3_type[0x4];
2194         u8         roce_version[0x8];
2195
2196         u8         reserved_at_e0[0x20];
2197 };
2198
2199 union mlx5_ifc_hca_cap_union_bits {
2200         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2201         struct mlx5_ifc_odp_cap_bits odp_cap;
2202         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2203         struct mlx5_ifc_roce_cap_bits roce_cap;
2204         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2205         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2206         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2207         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2208         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2209         struct mlx5_ifc_qos_cap_bits qos_cap;
2210         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2211         u8         reserved_at_0[0x8000];
2212 };
2213
2214 enum {
2215         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2216         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2217         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2218         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2219         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2220         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2221         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2222 };
2223
2224 struct mlx5_ifc_flow_context_bits {
2225         u8         reserved_at_0[0x20];
2226
2227         u8         group_id[0x20];
2228
2229         u8         reserved_at_40[0x8];
2230         u8         flow_tag[0x18];
2231
2232         u8         reserved_at_60[0x10];
2233         u8         action[0x10];
2234
2235         u8         reserved_at_80[0x8];
2236         u8         destination_list_size[0x18];
2237
2238         u8         reserved_at_a0[0x8];
2239         u8         flow_counter_list_size[0x18];
2240
2241         u8         encap_id[0x20];
2242
2243         u8         modify_header_id[0x20];
2244
2245         u8         reserved_at_100[0x100];
2246
2247         struct mlx5_ifc_fte_match_param_bits match_value;
2248
2249         u8         reserved_at_1200[0x600];
2250
2251         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2252 };
2253
2254 enum {
2255         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2256         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2257 };
2258
2259 struct mlx5_ifc_xrc_srqc_bits {
2260         u8         state[0x4];
2261         u8         log_xrc_srq_size[0x4];
2262         u8         reserved_at_8[0x18];
2263
2264         u8         wq_signature[0x1];
2265         u8         cont_srq[0x1];
2266         u8         reserved_at_22[0x1];
2267         u8         rlky[0x1];
2268         u8         basic_cyclic_rcv_wqe[0x1];
2269         u8         log_rq_stride[0x3];
2270         u8         xrcd[0x18];
2271
2272         u8         page_offset[0x6];
2273         u8         reserved_at_46[0x2];
2274         u8         cqn[0x18];
2275
2276         u8         reserved_at_60[0x20];
2277
2278         u8         user_index_equal_xrc_srqn[0x1];
2279         u8         reserved_at_81[0x1];
2280         u8         log_page_size[0x6];
2281         u8         user_index[0x18];
2282
2283         u8         reserved_at_a0[0x20];
2284
2285         u8         reserved_at_c0[0x8];
2286         u8         pd[0x18];
2287
2288         u8         lwm[0x10];
2289         u8         wqe_cnt[0x10];
2290
2291         u8         reserved_at_100[0x40];
2292
2293         u8         db_record_addr_h[0x20];
2294
2295         u8         db_record_addr_l[0x1e];
2296         u8         reserved_at_17e[0x2];
2297
2298         u8         reserved_at_180[0x80];
2299 };
2300
2301 struct mlx5_ifc_traffic_counter_bits {
2302         u8         packets[0x40];
2303
2304         u8         octets[0x40];
2305 };
2306
2307 struct mlx5_ifc_tisc_bits {
2308         u8         strict_lag_tx_port_affinity[0x1];
2309         u8         reserved_at_1[0x3];
2310         u8         lag_tx_port_affinity[0x04];
2311
2312         u8         reserved_at_8[0x4];
2313         u8         prio[0x4];
2314         u8         reserved_at_10[0x10];
2315
2316         u8         reserved_at_20[0x100];
2317
2318         u8         reserved_at_120[0x8];
2319         u8         transport_domain[0x18];
2320
2321         u8         reserved_at_140[0x8];
2322         u8         underlay_qpn[0x18];
2323         u8         reserved_at_160[0x3a0];
2324 };
2325
2326 enum {
2327         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2328         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2329 };
2330
2331 enum {
2332         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2333         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2334 };
2335
2336 enum {
2337         MLX5_RX_HASH_FN_NONE           = 0x0,
2338         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2339         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2340 };
2341
2342 enum {
2343         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2344         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2345 };
2346
2347 struct mlx5_ifc_tirc_bits {
2348         u8         reserved_at_0[0x20];
2349
2350         u8         disp_type[0x4];
2351         u8         reserved_at_24[0x1c];
2352
2353         u8         reserved_at_40[0x40];
2354
2355         u8         reserved_at_80[0x4];
2356         u8         lro_timeout_period_usecs[0x10];
2357         u8         lro_enable_mask[0x4];
2358         u8         lro_max_ip_payload_size[0x8];
2359
2360         u8         reserved_at_a0[0x40];
2361
2362         u8         reserved_at_e0[0x8];
2363         u8         inline_rqn[0x18];
2364
2365         u8         rx_hash_symmetric[0x1];
2366         u8         reserved_at_101[0x1];
2367         u8         tunneled_offload_en[0x1];
2368         u8         reserved_at_103[0x5];
2369         u8         indirect_table[0x18];
2370
2371         u8         rx_hash_fn[0x4];
2372         u8         reserved_at_124[0x2];
2373         u8         self_lb_block[0x2];
2374         u8         transport_domain[0x18];
2375
2376         u8         rx_hash_toeplitz_key[10][0x20];
2377
2378         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2379
2380         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2381
2382         u8         reserved_at_2c0[0x4c0];
2383 };
2384
2385 enum {
2386         MLX5_SRQC_STATE_GOOD   = 0x0,
2387         MLX5_SRQC_STATE_ERROR  = 0x1,
2388 };
2389
2390 struct mlx5_ifc_srqc_bits {
2391         u8         state[0x4];
2392         u8         log_srq_size[0x4];
2393         u8         reserved_at_8[0x18];
2394
2395         u8         wq_signature[0x1];
2396         u8         cont_srq[0x1];
2397         u8         reserved_at_22[0x1];
2398         u8         rlky[0x1];
2399         u8         reserved_at_24[0x1];
2400         u8         log_rq_stride[0x3];
2401         u8         xrcd[0x18];
2402
2403         u8         page_offset[0x6];
2404         u8         reserved_at_46[0x2];
2405         u8         cqn[0x18];
2406
2407         u8         reserved_at_60[0x20];
2408
2409         u8         reserved_at_80[0x2];
2410         u8         log_page_size[0x6];
2411         u8         reserved_at_88[0x18];
2412
2413         u8         reserved_at_a0[0x20];
2414
2415         u8         reserved_at_c0[0x8];
2416         u8         pd[0x18];
2417
2418         u8         lwm[0x10];
2419         u8         wqe_cnt[0x10];
2420
2421         u8         reserved_at_100[0x40];
2422
2423         u8         dbr_addr[0x40];
2424
2425         u8         reserved_at_180[0x80];
2426 };
2427
2428 enum {
2429         MLX5_SQC_STATE_RST  = 0x0,
2430         MLX5_SQC_STATE_RDY  = 0x1,
2431         MLX5_SQC_STATE_ERR  = 0x3,
2432 };
2433
2434 struct mlx5_ifc_sqc_bits {
2435         u8         rlky[0x1];
2436         u8         cd_master[0x1];
2437         u8         fre[0x1];
2438         u8         flush_in_error_en[0x1];
2439         u8         reserved_at_4[0x1];
2440         u8         min_wqe_inline_mode[0x3];
2441         u8         state[0x4];
2442         u8         reg_umr[0x1];
2443         u8         allow_swp[0x1];
2444         u8         reserved_at_e[0x12];
2445
2446         u8         reserved_at_20[0x8];
2447         u8         user_index[0x18];
2448
2449         u8         reserved_at_40[0x8];
2450         u8         cqn[0x18];
2451
2452         u8         reserved_at_60[0x90];
2453
2454         u8         packet_pacing_rate_limit_index[0x10];
2455         u8         tis_lst_sz[0x10];
2456         u8         reserved_at_110[0x10];
2457
2458         u8         reserved_at_120[0x40];
2459
2460         u8         reserved_at_160[0x8];
2461         u8         tis_num_0[0x18];
2462
2463         struct mlx5_ifc_wq_bits wq;
2464 };
2465
2466 enum {
2467         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2468         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2469         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2470         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2471 };
2472
2473 struct mlx5_ifc_scheduling_context_bits {
2474         u8         element_type[0x8];
2475         u8         reserved_at_8[0x18];
2476
2477         u8         element_attributes[0x20];
2478
2479         u8         parent_element_id[0x20];
2480
2481         u8         reserved_at_60[0x40];
2482
2483         u8         bw_share[0x20];
2484
2485         u8         max_average_bw[0x20];
2486
2487         u8         reserved_at_e0[0x120];
2488 };
2489
2490 struct mlx5_ifc_rqtc_bits {
2491         u8         reserved_at_0[0xa0];
2492
2493         u8         reserved_at_a0[0x10];
2494         u8         rqt_max_size[0x10];
2495
2496         u8         reserved_at_c0[0x10];
2497         u8         rqt_actual_size[0x10];
2498
2499         u8         reserved_at_e0[0x6a0];
2500
2501         struct mlx5_ifc_rq_num_bits rq_num[0];
2502 };
2503
2504 enum {
2505         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2506         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2507 };
2508
2509 enum {
2510         MLX5_RQC_STATE_RST  = 0x0,
2511         MLX5_RQC_STATE_RDY  = 0x1,
2512         MLX5_RQC_STATE_ERR  = 0x3,
2513 };
2514
2515 struct mlx5_ifc_rqc_bits {
2516         u8         rlky[0x1];
2517         u8         reserved_at_1[0x1];
2518         u8         scatter_fcs[0x1];
2519         u8         vsd[0x1];
2520         u8         mem_rq_type[0x4];
2521         u8         state[0x4];
2522         u8         reserved_at_c[0x1];
2523         u8         flush_in_error_en[0x1];
2524         u8         reserved_at_e[0x12];
2525
2526         u8         reserved_at_20[0x8];
2527         u8         user_index[0x18];
2528
2529         u8         reserved_at_40[0x8];
2530         u8         cqn[0x18];
2531
2532         u8         counter_set_id[0x8];
2533         u8         reserved_at_68[0x18];
2534
2535         u8         reserved_at_80[0x8];
2536         u8         rmpn[0x18];
2537
2538         u8         reserved_at_a0[0xe0];
2539
2540         struct mlx5_ifc_wq_bits wq;
2541 };
2542
2543 enum {
2544         MLX5_RMPC_STATE_RDY  = 0x1,
2545         MLX5_RMPC_STATE_ERR  = 0x3,
2546 };
2547
2548 struct mlx5_ifc_rmpc_bits {
2549         u8         reserved_at_0[0x8];
2550         u8         state[0x4];
2551         u8         reserved_at_c[0x14];
2552
2553         u8         basic_cyclic_rcv_wqe[0x1];
2554         u8         reserved_at_21[0x1f];
2555
2556         u8         reserved_at_40[0x140];
2557
2558         struct mlx5_ifc_wq_bits wq;
2559 };
2560
2561 struct mlx5_ifc_nic_vport_context_bits {
2562         u8         reserved_at_0[0x5];
2563         u8         min_wqe_inline_mode[0x3];
2564         u8         reserved_at_8[0x17];
2565         u8         roce_en[0x1];
2566
2567         u8         arm_change_event[0x1];
2568         u8         reserved_at_21[0x1a];
2569         u8         event_on_mtu[0x1];
2570         u8         event_on_promisc_change[0x1];
2571         u8         event_on_vlan_change[0x1];
2572         u8         event_on_mc_address_change[0x1];
2573         u8         event_on_uc_address_change[0x1];
2574
2575         u8         reserved_at_40[0xf0];
2576
2577         u8         mtu[0x10];
2578
2579         u8         system_image_guid[0x40];
2580         u8         port_guid[0x40];
2581         u8         node_guid[0x40];
2582
2583         u8         reserved_at_200[0x140];
2584         u8         qkey_violation_counter[0x10];
2585         u8         reserved_at_350[0x430];
2586
2587         u8         promisc_uc[0x1];
2588         u8         promisc_mc[0x1];
2589         u8         promisc_all[0x1];
2590         u8         reserved_at_783[0x2];
2591         u8         allowed_list_type[0x3];
2592         u8         reserved_at_788[0xc];
2593         u8         allowed_list_size[0xc];
2594
2595         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2596
2597         u8         reserved_at_7e0[0x20];
2598
2599         u8         current_uc_mac_address[0][0x40];
2600 };
2601
2602 enum {
2603         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2604         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2605         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2606         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2607 };
2608
2609 struct mlx5_ifc_mkc_bits {
2610         u8         reserved_at_0[0x1];
2611         u8         free[0x1];
2612         u8         reserved_at_2[0xd];
2613         u8         small_fence_on_rdma_read_response[0x1];
2614         u8         umr_en[0x1];
2615         u8         a[0x1];
2616         u8         rw[0x1];
2617         u8         rr[0x1];
2618         u8         lw[0x1];
2619         u8         lr[0x1];
2620         u8         access_mode[0x2];
2621         u8         reserved_at_18[0x8];
2622
2623         u8         qpn[0x18];
2624         u8         mkey_7_0[0x8];
2625
2626         u8         reserved_at_40[0x20];
2627
2628         u8         length64[0x1];
2629         u8         bsf_en[0x1];
2630         u8         sync_umr[0x1];
2631         u8         reserved_at_63[0x2];
2632         u8         expected_sigerr_count[0x1];
2633         u8         reserved_at_66[0x1];
2634         u8         en_rinval[0x1];
2635         u8         pd[0x18];
2636
2637         u8         start_addr[0x40];
2638
2639         u8         len[0x40];
2640
2641         u8         bsf_octword_size[0x20];
2642
2643         u8         reserved_at_120[0x80];
2644
2645         u8         translations_octword_size[0x20];
2646
2647         u8         reserved_at_1c0[0x1b];
2648         u8         log_page_size[0x5];
2649
2650         u8         reserved_at_1e0[0x20];
2651 };
2652
2653 struct mlx5_ifc_pkey_bits {
2654         u8         reserved_at_0[0x10];
2655         u8         pkey[0x10];
2656 };
2657
2658 struct mlx5_ifc_array128_auto_bits {
2659         u8         array128_auto[16][0x8];
2660 };
2661
2662 struct mlx5_ifc_hca_vport_context_bits {
2663         u8         field_select[0x20];
2664
2665         u8         reserved_at_20[0xe0];
2666
2667         u8         sm_virt_aware[0x1];
2668         u8         has_smi[0x1];
2669         u8         has_raw[0x1];
2670         u8         grh_required[0x1];
2671         u8         reserved_at_104[0xc];
2672         u8         port_physical_state[0x4];
2673         u8         vport_state_policy[0x4];
2674         u8         port_state[0x4];
2675         u8         vport_state[0x4];
2676
2677         u8         reserved_at_120[0x20];
2678
2679         u8         system_image_guid[0x40];
2680
2681         u8         port_guid[0x40];
2682
2683         u8         node_guid[0x40];
2684
2685         u8         cap_mask1[0x20];
2686
2687         u8         cap_mask1_field_select[0x20];
2688
2689         u8         cap_mask2[0x20];
2690
2691         u8         cap_mask2_field_select[0x20];
2692
2693         u8         reserved_at_280[0x80];
2694
2695         u8         lid[0x10];
2696         u8         reserved_at_310[0x4];
2697         u8         init_type_reply[0x4];
2698         u8         lmc[0x3];
2699         u8         subnet_timeout[0x5];
2700
2701         u8         sm_lid[0x10];
2702         u8         sm_sl[0x4];
2703         u8         reserved_at_334[0xc];
2704
2705         u8         qkey_violation_counter[0x10];
2706         u8         pkey_violation_counter[0x10];
2707
2708         u8         reserved_at_360[0xca0];
2709 };
2710
2711 struct mlx5_ifc_esw_vport_context_bits {
2712         u8         reserved_at_0[0x3];
2713         u8         vport_svlan_strip[0x1];
2714         u8         vport_cvlan_strip[0x1];
2715         u8         vport_svlan_insert[0x1];
2716         u8         vport_cvlan_insert[0x2];
2717         u8         reserved_at_8[0x18];
2718
2719         u8         reserved_at_20[0x20];
2720
2721         u8         svlan_cfi[0x1];
2722         u8         svlan_pcp[0x3];
2723         u8         svlan_id[0xc];
2724         u8         cvlan_cfi[0x1];
2725         u8         cvlan_pcp[0x3];
2726         u8         cvlan_id[0xc];
2727
2728         u8         reserved_at_60[0x7a0];
2729 };
2730
2731 enum {
2732         MLX5_EQC_STATUS_OK                = 0x0,
2733         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2734 };
2735
2736 enum {
2737         MLX5_EQC_ST_ARMED  = 0x9,
2738         MLX5_EQC_ST_FIRED  = 0xa,
2739 };
2740
2741 struct mlx5_ifc_eqc_bits {
2742         u8         status[0x4];
2743         u8         reserved_at_4[0x9];
2744         u8         ec[0x1];
2745         u8         oi[0x1];
2746         u8         reserved_at_f[0x5];
2747         u8         st[0x4];
2748         u8         reserved_at_18[0x8];
2749
2750         u8         reserved_at_20[0x20];
2751
2752         u8         reserved_at_40[0x14];
2753         u8         page_offset[0x6];
2754         u8         reserved_at_5a[0x6];
2755
2756         u8         reserved_at_60[0x3];
2757         u8         log_eq_size[0x5];
2758         u8         uar_page[0x18];
2759
2760         u8         reserved_at_80[0x20];
2761
2762         u8         reserved_at_a0[0x18];
2763         u8         intr[0x8];
2764
2765         u8         reserved_at_c0[0x3];
2766         u8         log_page_size[0x5];
2767         u8         reserved_at_c8[0x18];
2768
2769         u8         reserved_at_e0[0x60];
2770
2771         u8         reserved_at_140[0x8];
2772         u8         consumer_counter[0x18];
2773
2774         u8         reserved_at_160[0x8];
2775         u8         producer_counter[0x18];
2776
2777         u8         reserved_at_180[0x80];
2778 };
2779
2780 enum {
2781         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2782         MLX5_DCTC_STATE_DRAINING  = 0x1,
2783         MLX5_DCTC_STATE_DRAINED   = 0x2,
2784 };
2785
2786 enum {
2787         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2788         MLX5_DCTC_CS_RES_NA         = 0x1,
2789         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2790 };
2791
2792 enum {
2793         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2794         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2795         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2796         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2797         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2798 };
2799
2800 struct mlx5_ifc_dctc_bits {
2801         u8         reserved_at_0[0x4];
2802         u8         state[0x4];
2803         u8         reserved_at_8[0x18];
2804
2805         u8         reserved_at_20[0x8];
2806         u8         user_index[0x18];
2807
2808         u8         reserved_at_40[0x8];
2809         u8         cqn[0x18];
2810
2811         u8         counter_set_id[0x8];
2812         u8         atomic_mode[0x4];
2813         u8         rre[0x1];
2814         u8         rwe[0x1];
2815         u8         rae[0x1];
2816         u8         atomic_like_write_en[0x1];
2817         u8         latency_sensitive[0x1];
2818         u8         rlky[0x1];
2819         u8         free_ar[0x1];
2820         u8         reserved_at_73[0xd];
2821
2822         u8         reserved_at_80[0x8];
2823         u8         cs_res[0x8];
2824         u8         reserved_at_90[0x3];
2825         u8         min_rnr_nak[0x5];
2826         u8         reserved_at_98[0x8];
2827
2828         u8         reserved_at_a0[0x8];
2829         u8         srqn_xrqn[0x18];
2830
2831         u8         reserved_at_c0[0x8];
2832         u8         pd[0x18];
2833
2834         u8         tclass[0x8];
2835         u8         reserved_at_e8[0x4];
2836         u8         flow_label[0x14];
2837
2838         u8         dc_access_key[0x40];
2839
2840         u8         reserved_at_140[0x5];
2841         u8         mtu[0x3];
2842         u8         port[0x8];
2843         u8         pkey_index[0x10];
2844
2845         u8         reserved_at_160[0x8];
2846         u8         my_addr_index[0x8];
2847         u8         reserved_at_170[0x8];
2848         u8         hop_limit[0x8];
2849
2850         u8         dc_access_key_violation_count[0x20];
2851
2852         u8         reserved_at_1a0[0x14];
2853         u8         dei_cfi[0x1];
2854         u8         eth_prio[0x3];
2855         u8         ecn[0x2];
2856         u8         dscp[0x6];
2857
2858         u8         reserved_at_1c0[0x40];
2859 };
2860
2861 enum {
2862         MLX5_CQC_STATUS_OK             = 0x0,
2863         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2864         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2865 };
2866
2867 enum {
2868         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2869         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2870 };
2871
2872 enum {
2873         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2874         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2875         MLX5_CQC_ST_FIRED                                 = 0xa,
2876 };
2877
2878 enum {
2879         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2880         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2881         MLX5_CQ_PERIOD_NUM_MODES
2882 };
2883
2884 struct mlx5_ifc_cqc_bits {
2885         u8         status[0x4];
2886         u8         reserved_at_4[0x4];
2887         u8         cqe_sz[0x3];
2888         u8         cc[0x1];
2889         u8         reserved_at_c[0x1];
2890         u8         scqe_break_moderation_en[0x1];
2891         u8         oi[0x1];
2892         u8         cq_period_mode[0x2];
2893         u8         cqe_comp_en[0x1];
2894         u8         mini_cqe_res_format[0x2];
2895         u8         st[0x4];
2896         u8         reserved_at_18[0x8];
2897
2898         u8         reserved_at_20[0x20];
2899
2900         u8         reserved_at_40[0x14];
2901         u8         page_offset[0x6];
2902         u8         reserved_at_5a[0x6];
2903
2904         u8         reserved_at_60[0x3];
2905         u8         log_cq_size[0x5];
2906         u8         uar_page[0x18];
2907
2908         u8         reserved_at_80[0x4];
2909         u8         cq_period[0xc];
2910         u8         cq_max_count[0x10];
2911
2912         u8         reserved_at_a0[0x18];
2913         u8         c_eqn[0x8];
2914
2915         u8         reserved_at_c0[0x3];
2916         u8         log_page_size[0x5];
2917         u8         reserved_at_c8[0x18];
2918
2919         u8         reserved_at_e0[0x20];
2920
2921         u8         reserved_at_100[0x8];
2922         u8         last_notified_index[0x18];
2923
2924         u8         reserved_at_120[0x8];
2925         u8         last_solicit_index[0x18];
2926
2927         u8         reserved_at_140[0x8];
2928         u8         consumer_counter[0x18];
2929
2930         u8         reserved_at_160[0x8];
2931         u8         producer_counter[0x18];
2932
2933         u8         reserved_at_180[0x40];
2934
2935         u8         dbr_addr[0x40];
2936 };
2937
2938 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2939         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2940         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2941         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2942         u8         reserved_at_0[0x800];
2943 };
2944
2945 struct mlx5_ifc_query_adapter_param_block_bits {
2946         u8         reserved_at_0[0xc0];
2947
2948         u8         reserved_at_c0[0x8];
2949         u8         ieee_vendor_id[0x18];
2950
2951         u8         reserved_at_e0[0x10];
2952         u8         vsd_vendor_id[0x10];
2953
2954         u8         vsd[208][0x8];
2955
2956         u8         vsd_contd_psid[16][0x8];
2957 };
2958
2959 enum {
2960         MLX5_XRQC_STATE_GOOD   = 0x0,
2961         MLX5_XRQC_STATE_ERROR  = 0x1,
2962 };
2963
2964 enum {
2965         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2966         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2967 };
2968
2969 enum {
2970         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2971 };
2972
2973 struct mlx5_ifc_tag_matching_topology_context_bits {
2974         u8         log_matching_list_sz[0x4];
2975         u8         reserved_at_4[0xc];
2976         u8         append_next_index[0x10];
2977
2978         u8         sw_phase_cnt[0x10];
2979         u8         hw_phase_cnt[0x10];
2980
2981         u8         reserved_at_40[0x40];
2982 };
2983
2984 struct mlx5_ifc_xrqc_bits {
2985         u8         state[0x4];
2986         u8         rlkey[0x1];
2987         u8         reserved_at_5[0xf];
2988         u8         topology[0x4];
2989         u8         reserved_at_18[0x4];
2990         u8         offload[0x4];
2991
2992         u8         reserved_at_20[0x8];
2993         u8         user_index[0x18];
2994
2995         u8         reserved_at_40[0x8];
2996         u8         cqn[0x18];
2997
2998         u8         reserved_at_60[0xa0];
2999
3000         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3001
3002         u8         reserved_at_180[0x880];
3003
3004         struct mlx5_ifc_wq_bits wq;
3005 };
3006
3007 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3008         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3009         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3010         u8         reserved_at_0[0x20];
3011 };
3012
3013 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3014         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3015         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3016         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3017         u8         reserved_at_0[0x20];
3018 };
3019
3020 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3021         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3022         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3023         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3024         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3025         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3026         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3027         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3028         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3029         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3030         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3031         u8         reserved_at_0[0x7c0];
3032 };
3033
3034 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3035         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3036         u8         reserved_at_0[0x7c0];
3037 };
3038
3039 union mlx5_ifc_event_auto_bits {
3040         struct mlx5_ifc_comp_event_bits comp_event;
3041         struct mlx5_ifc_dct_events_bits dct_events;
3042         struct mlx5_ifc_qp_events_bits qp_events;
3043         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3044         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3045         struct mlx5_ifc_cq_error_bits cq_error;
3046         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3047         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3048         struct mlx5_ifc_gpio_event_bits gpio_event;
3049         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3050         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3051         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3052         u8         reserved_at_0[0xe0];
3053 };
3054
3055 struct mlx5_ifc_health_buffer_bits {
3056         u8         reserved_at_0[0x100];
3057
3058         u8         assert_existptr[0x20];
3059
3060         u8         assert_callra[0x20];
3061
3062         u8         reserved_at_140[0x40];
3063
3064         u8         fw_version[0x20];
3065
3066         u8         hw_id[0x20];
3067
3068         u8         reserved_at_1c0[0x20];
3069
3070         u8         irisc_index[0x8];
3071         u8         synd[0x8];
3072         u8         ext_synd[0x10];
3073 };
3074
3075 struct mlx5_ifc_register_loopback_control_bits {
3076         u8         no_lb[0x1];
3077         u8         reserved_at_1[0x7];
3078         u8         port[0x8];
3079         u8         reserved_at_10[0x10];
3080
3081         u8         reserved_at_20[0x60];
3082 };
3083
3084 struct mlx5_ifc_vport_tc_element_bits {
3085         u8         traffic_class[0x4];
3086         u8         reserved_at_4[0xc];
3087         u8         vport_number[0x10];
3088 };
3089
3090 struct mlx5_ifc_vport_element_bits {
3091         u8         reserved_at_0[0x10];
3092         u8         vport_number[0x10];
3093 };
3094
3095 enum {
3096         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3097         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3098         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3099 };
3100
3101 struct mlx5_ifc_tsar_element_bits {
3102         u8         reserved_at_0[0x8];
3103         u8         tsar_type[0x8];
3104         u8         reserved_at_10[0x10];
3105 };
3106
3107 enum {
3108         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3109         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3110 };
3111
3112 struct mlx5_ifc_teardown_hca_out_bits {
3113         u8         status[0x8];
3114         u8         reserved_at_8[0x18];
3115
3116         u8         syndrome[0x20];
3117
3118         u8         reserved_at_40[0x3f];
3119
3120         u8         force_state[0x1];
3121 };
3122
3123 enum {
3124         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3125         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3126 };
3127
3128 struct mlx5_ifc_teardown_hca_in_bits {
3129         u8         opcode[0x10];
3130         u8         reserved_at_10[0x10];
3131
3132         u8         reserved_at_20[0x10];
3133         u8         op_mod[0x10];
3134
3135         u8         reserved_at_40[0x10];
3136         u8         profile[0x10];
3137
3138         u8         reserved_at_60[0x20];
3139 };
3140
3141 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3142         u8         status[0x8];
3143         u8         reserved_at_8[0x18];
3144
3145         u8         syndrome[0x20];
3146
3147         u8         reserved_at_40[0x40];
3148 };
3149
3150 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3151         u8         opcode[0x10];
3152         u8         reserved_at_10[0x10];
3153
3154         u8         reserved_at_20[0x10];
3155         u8         op_mod[0x10];
3156
3157         u8         reserved_at_40[0x8];
3158         u8         qpn[0x18];
3159
3160         u8         reserved_at_60[0x20];
3161
3162         u8         opt_param_mask[0x20];
3163
3164         u8         reserved_at_a0[0x20];
3165
3166         struct mlx5_ifc_qpc_bits qpc;
3167
3168         u8         reserved_at_800[0x80];
3169 };
3170
3171 struct mlx5_ifc_sqd2rts_qp_out_bits {
3172         u8         status[0x8];
3173         u8         reserved_at_8[0x18];
3174
3175         u8         syndrome[0x20];
3176
3177         u8         reserved_at_40[0x40];
3178 };
3179
3180 struct mlx5_ifc_sqd2rts_qp_in_bits {
3181         u8         opcode[0x10];
3182         u8         reserved_at_10[0x10];
3183
3184         u8         reserved_at_20[0x10];
3185         u8         op_mod[0x10];
3186
3187         u8         reserved_at_40[0x8];
3188         u8         qpn[0x18];
3189
3190         u8         reserved_at_60[0x20];
3191
3192         u8         opt_param_mask[0x20];
3193
3194         u8         reserved_at_a0[0x20];
3195
3196         struct mlx5_ifc_qpc_bits qpc;
3197
3198         u8         reserved_at_800[0x80];
3199 };
3200
3201 struct mlx5_ifc_set_roce_address_out_bits {
3202         u8         status[0x8];
3203         u8         reserved_at_8[0x18];
3204
3205         u8         syndrome[0x20];
3206
3207         u8         reserved_at_40[0x40];
3208 };
3209
3210 struct mlx5_ifc_set_roce_address_in_bits {
3211         u8         opcode[0x10];
3212         u8         reserved_at_10[0x10];
3213
3214         u8         reserved_at_20[0x10];
3215         u8         op_mod[0x10];
3216
3217         u8         roce_address_index[0x10];
3218         u8         reserved_at_50[0x10];
3219
3220         u8         reserved_at_60[0x20];
3221
3222         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3223 };
3224
3225 struct mlx5_ifc_set_mad_demux_out_bits {
3226         u8         status[0x8];
3227         u8         reserved_at_8[0x18];
3228
3229         u8         syndrome[0x20];
3230
3231         u8         reserved_at_40[0x40];
3232 };
3233
3234 enum {
3235         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3236         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3237 };
3238
3239 struct mlx5_ifc_set_mad_demux_in_bits {
3240         u8         opcode[0x10];
3241         u8         reserved_at_10[0x10];
3242
3243         u8         reserved_at_20[0x10];
3244         u8         op_mod[0x10];
3245
3246         u8         reserved_at_40[0x20];
3247
3248         u8         reserved_at_60[0x6];
3249         u8         demux_mode[0x2];
3250         u8         reserved_at_68[0x18];
3251 };
3252
3253 struct mlx5_ifc_set_l2_table_entry_out_bits {
3254         u8         status[0x8];
3255         u8         reserved_at_8[0x18];
3256
3257         u8         syndrome[0x20];
3258
3259         u8         reserved_at_40[0x40];
3260 };
3261
3262 struct mlx5_ifc_set_l2_table_entry_in_bits {
3263         u8         opcode[0x10];
3264         u8         reserved_at_10[0x10];
3265
3266         u8         reserved_at_20[0x10];
3267         u8         op_mod[0x10];
3268
3269         u8         reserved_at_40[0x60];
3270
3271         u8         reserved_at_a0[0x8];