net/mlx5: Expose PCAM, MCAM registers infrastructure
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 enum {
36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
60 };
61
62 enum {
63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
67 };
68
69 enum {
70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
72 };
73
74 enum {
75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
167         MLX5_CMD_OP_NOP                           = 0x80d,
168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
230         MLX5_CMD_OP_MAX
231 };
232
233 struct mlx5_ifc_flow_table_fields_supported_bits {
234         u8         outer_dmac[0x1];
235         u8         outer_smac[0x1];
236         u8         outer_ether_type[0x1];
237         u8         reserved_at_3[0x1];
238         u8         outer_first_prio[0x1];
239         u8         outer_first_cfi[0x1];
240         u8         outer_first_vid[0x1];
241         u8         reserved_at_7[0x1];
242         u8         outer_second_prio[0x1];
243         u8         outer_second_cfi[0x1];
244         u8         outer_second_vid[0x1];
245         u8         reserved_at_b[0x1];
246         u8         outer_sip[0x1];
247         u8         outer_dip[0x1];
248         u8         outer_frag[0x1];
249         u8         outer_ip_protocol[0x1];
250         u8         outer_ip_ecn[0x1];
251         u8         outer_ip_dscp[0x1];
252         u8         outer_udp_sport[0x1];
253         u8         outer_udp_dport[0x1];
254         u8         outer_tcp_sport[0x1];
255         u8         outer_tcp_dport[0x1];
256         u8         outer_tcp_flags[0x1];
257         u8         outer_gre_protocol[0x1];
258         u8         outer_gre_key[0x1];
259         u8         outer_vxlan_vni[0x1];
260         u8         reserved_at_1a[0x5];
261         u8         source_eswitch_port[0x1];
262
263         u8         inner_dmac[0x1];
264         u8         inner_smac[0x1];
265         u8         inner_ether_type[0x1];
266         u8         reserved_at_23[0x1];
267         u8         inner_first_prio[0x1];
268         u8         inner_first_cfi[0x1];
269         u8         inner_first_vid[0x1];
270         u8         reserved_at_27[0x1];
271         u8         inner_second_prio[0x1];
272         u8         inner_second_cfi[0x1];
273         u8         inner_second_vid[0x1];
274         u8         reserved_at_2b[0x1];
275         u8         inner_sip[0x1];
276         u8         inner_dip[0x1];
277         u8         inner_frag[0x1];
278         u8         inner_ip_protocol[0x1];
279         u8         inner_ip_ecn[0x1];
280         u8         inner_ip_dscp[0x1];
281         u8         inner_udp_sport[0x1];
282         u8         inner_udp_dport[0x1];
283         u8         inner_tcp_sport[0x1];
284         u8         inner_tcp_dport[0x1];
285         u8         inner_tcp_flags[0x1];
286         u8         reserved_at_37[0x9];
287
288         u8         reserved_at_40[0x40];
289 };
290
291 struct mlx5_ifc_flow_table_prop_layout_bits {
292         u8         ft_support[0x1];
293         u8         reserved_at_1[0x1];
294         u8         flow_counter[0x1];
295         u8         flow_modify_en[0x1];
296         u8         modify_root[0x1];
297         u8         identified_miss_table_mode[0x1];
298         u8         flow_table_modify[0x1];
299         u8         encap[0x1];
300         u8         decap[0x1];
301         u8         reserved_at_9[0x17];
302
303         u8         reserved_at_20[0x2];
304         u8         log_max_ft_size[0x6];
305         u8         reserved_at_28[0x10];
306         u8         max_ft_level[0x8];
307
308         u8         reserved_at_40[0x20];
309
310         u8         reserved_at_60[0x18];
311         u8         log_max_ft_num[0x8];
312
313         u8         reserved_at_80[0x18];
314         u8         log_max_destination[0x8];
315
316         u8         reserved_at_a0[0x18];
317         u8         log_max_flow[0x8];
318
319         u8         reserved_at_c0[0x40];
320
321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324 };
325
326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
327         u8         send[0x1];
328         u8         receive[0x1];
329         u8         write[0x1];
330         u8         read[0x1];
331         u8         atomic[0x1];
332         u8         srq_receive[0x1];
333         u8         reserved_at_6[0x1a];
334 };
335
336 struct mlx5_ifc_ipv4_layout_bits {
337         u8         reserved_at_0[0x60];
338
339         u8         ipv4[0x20];
340 };
341
342 struct mlx5_ifc_ipv6_layout_bits {
343         u8         ipv6[16][0x8];
344 };
345
346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
349         u8         reserved_at_0[0x80];
350 };
351
352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353         u8         smac_47_16[0x20];
354
355         u8         smac_15_0[0x10];
356         u8         ethertype[0x10];
357
358         u8         dmac_47_16[0x20];
359
360         u8         dmac_15_0[0x10];
361         u8         first_prio[0x3];
362         u8         first_cfi[0x1];
363         u8         first_vid[0xc];
364
365         u8         ip_protocol[0x8];
366         u8         ip_dscp[0x6];
367         u8         ip_ecn[0x2];
368         u8         cvlan_tag[0x1];
369         u8         svlan_tag[0x1];
370         u8         frag[0x1];
371         u8         reserved_at_93[0x4];
372         u8         tcp_flags[0x9];
373
374         u8         tcp_sport[0x10];
375         u8         tcp_dport[0x10];
376
377         u8         reserved_at_c0[0x20];
378
379         u8         udp_sport[0x10];
380         u8         udp_dport[0x10];
381
382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
383
384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
385 };
386
387 struct mlx5_ifc_fte_match_set_misc_bits {
388         u8         reserved_at_0[0x8];
389         u8         source_sqn[0x18];
390
391         u8         reserved_at_20[0x10];
392         u8         source_port[0x10];
393
394         u8         outer_second_prio[0x3];
395         u8         outer_second_cfi[0x1];
396         u8         outer_second_vid[0xc];
397         u8         inner_second_prio[0x3];
398         u8         inner_second_cfi[0x1];
399         u8         inner_second_vid[0xc];
400
401         u8         outer_second_cvlan_tag[0x1];
402         u8         inner_second_cvlan_tag[0x1];
403         u8         outer_second_svlan_tag[0x1];
404         u8         inner_second_svlan_tag[0x1];
405         u8         reserved_at_64[0xc];
406         u8         gre_protocol[0x10];
407
408         u8         gre_key_h[0x18];
409         u8         gre_key_l[0x8];
410
411         u8         vxlan_vni[0x18];
412         u8         reserved_at_b8[0x8];
413
414         u8         reserved_at_c0[0x20];
415
416         u8         reserved_at_e0[0xc];
417         u8         outer_ipv6_flow_label[0x14];
418
419         u8         reserved_at_100[0xc];
420         u8         inner_ipv6_flow_label[0x14];
421
422         u8         reserved_at_120[0xe0];
423 };
424
425 struct mlx5_ifc_cmd_pas_bits {
426         u8         pa_h[0x20];
427
428         u8         pa_l[0x14];
429         u8         reserved_at_34[0xc];
430 };
431
432 struct mlx5_ifc_uint64_bits {
433         u8         hi[0x20];
434
435         u8         lo[0x20];
436 };
437
438 enum {
439         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
440         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
441         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
442         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
443         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
444         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
445         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
446         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
447         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
448         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
449 };
450
451 struct mlx5_ifc_ads_bits {
452         u8         fl[0x1];
453         u8         free_ar[0x1];
454         u8         reserved_at_2[0xe];
455         u8         pkey_index[0x10];
456
457         u8         reserved_at_20[0x8];
458         u8         grh[0x1];
459         u8         mlid[0x7];
460         u8         rlid[0x10];
461
462         u8         ack_timeout[0x5];
463         u8         reserved_at_45[0x3];
464         u8         src_addr_index[0x8];
465         u8         reserved_at_50[0x4];
466         u8         stat_rate[0x4];
467         u8         hop_limit[0x8];
468
469         u8         reserved_at_60[0x4];
470         u8         tclass[0x8];
471         u8         flow_label[0x14];
472
473         u8         rgid_rip[16][0x8];
474
475         u8         reserved_at_100[0x4];
476         u8         f_dscp[0x1];
477         u8         f_ecn[0x1];
478         u8         reserved_at_106[0x1];
479         u8         f_eth_prio[0x1];
480         u8         ecn[0x2];
481         u8         dscp[0x6];
482         u8         udp_sport[0x10];
483
484         u8         dei_cfi[0x1];
485         u8         eth_prio[0x3];
486         u8         sl[0x4];
487         u8         port[0x8];
488         u8         rmac_47_32[0x10];
489
490         u8         rmac_31_0[0x20];
491 };
492
493 struct mlx5_ifc_flow_table_nic_cap_bits {
494         u8         nic_rx_multi_path_tirs[0x1];
495         u8         nic_rx_multi_path_tirs_fts[0x1];
496         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
497         u8         reserved_at_3[0x1fd];
498
499         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
500
501         u8         reserved_at_400[0x200];
502
503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
504
505         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
506
507         u8         reserved_at_a00[0x200];
508
509         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
510
511         u8         reserved_at_e00[0x7200];
512 };
513
514 struct mlx5_ifc_flow_table_eswitch_cap_bits {
515         u8     reserved_at_0[0x200];
516
517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
518
519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
520
521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
522
523         u8      reserved_at_800[0x7800];
524 };
525
526 struct mlx5_ifc_e_switch_cap_bits {
527         u8         vport_svlan_strip[0x1];
528         u8         vport_cvlan_strip[0x1];
529         u8         vport_svlan_insert[0x1];
530         u8         vport_cvlan_insert_if_not_exist[0x1];
531         u8         vport_cvlan_insert_overwrite[0x1];
532         u8         reserved_at_5[0x19];
533         u8         nic_vport_node_guid_modify[0x1];
534         u8         nic_vport_port_guid_modify[0x1];
535
536         u8         vxlan_encap_decap[0x1];
537         u8         nvgre_encap_decap[0x1];
538         u8         reserved_at_22[0x9];
539         u8         log_max_encap_headers[0x5];
540         u8         reserved_2b[0x6];
541         u8         max_encap_header_size[0xa];
542
543         u8         reserved_40[0x7c0];
544
545 };
546
547 struct mlx5_ifc_qos_cap_bits {
548         u8         packet_pacing[0x1];
549         u8         esw_scheduling[0x1];
550         u8         reserved_at_2[0x1e];
551
552         u8         reserved_at_20[0x20];
553
554         u8         packet_pacing_max_rate[0x20];
555
556         u8         packet_pacing_min_rate[0x20];
557
558         u8         reserved_at_80[0x10];
559         u8         packet_pacing_rate_table_size[0x10];
560
561         u8         esw_element_type[0x10];
562         u8         esw_tsar_type[0x10];
563
564         u8         reserved_at_c0[0x10];
565         u8         max_qos_para_vport[0x10];
566
567         u8         max_tsar_bw_share[0x20];
568
569         u8         reserved_at_100[0x700];
570 };
571
572 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
573         u8         csum_cap[0x1];
574         u8         vlan_cap[0x1];
575         u8         lro_cap[0x1];
576         u8         lro_psh_flag[0x1];
577         u8         lro_time_stamp[0x1];
578         u8         reserved_at_5[0x3];
579         u8         self_lb_en_modifiable[0x1];
580         u8         reserved_at_9[0x2];
581         u8         max_lso_cap[0x5];
582         u8         multi_pkt_send_wqe[0x2];
583         u8         wqe_inline_mode[0x2];
584         u8         rss_ind_tbl_cap[0x4];
585         u8         reg_umr_sq[0x1];
586         u8         scatter_fcs[0x1];
587         u8         reserved_at_1a[0x1];
588         u8         tunnel_lso_const_out_ip_id[0x1];
589         u8         reserved_at_1c[0x2];
590         u8         tunnel_statless_gre[0x1];
591         u8         tunnel_stateless_vxlan[0x1];
592
593         u8         reserved_at_20[0x20];
594
595         u8         reserved_at_40[0x10];
596         u8         lro_min_mss_size[0x10];
597
598         u8         reserved_at_60[0x120];
599
600         u8         lro_timer_supported_periods[4][0x20];
601
602         u8         reserved_at_200[0x600];
603 };
604
605 struct mlx5_ifc_roce_cap_bits {
606         u8         roce_apm[0x1];
607         u8         reserved_at_1[0x1f];
608
609         u8         reserved_at_20[0x60];
610
611         u8         reserved_at_80[0xc];
612         u8         l3_type[0x4];
613         u8         reserved_at_90[0x8];
614         u8         roce_version[0x8];
615
616         u8         reserved_at_a0[0x10];
617         u8         r_roce_dest_udp_port[0x10];
618
619         u8         r_roce_max_src_udp_port[0x10];
620         u8         r_roce_min_src_udp_port[0x10];
621
622         u8         reserved_at_e0[0x10];
623         u8         roce_address_table_size[0x10];
624
625         u8         reserved_at_100[0x700];
626 };
627
628 enum {
629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
636         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
637         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
638 };
639
640 enum {
641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
650 };
651
652 struct mlx5_ifc_atomic_caps_bits {
653         u8         reserved_at_0[0x40];
654
655         u8         atomic_req_8B_endianess_mode[0x2];
656         u8         reserved_at_42[0x4];
657         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
658
659         u8         reserved_at_47[0x19];
660
661         u8         reserved_at_60[0x20];
662
663         u8         reserved_at_80[0x10];
664         u8         atomic_operations[0x10];
665
666         u8         reserved_at_a0[0x10];
667         u8         atomic_size_qp[0x10];
668
669         u8         reserved_at_c0[0x10];
670         u8         atomic_size_dc[0x10];
671
672         u8         reserved_at_e0[0x720];
673 };
674
675 struct mlx5_ifc_odp_cap_bits {
676         u8         reserved_at_0[0x40];
677
678         u8         sig[0x1];
679         u8         reserved_at_41[0x1f];
680
681         u8         reserved_at_60[0x20];
682
683         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
684
685         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
686
687         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
688
689         u8         reserved_at_e0[0x720];
690 };
691
692 struct mlx5_ifc_calc_op {
693         u8        reserved_at_0[0x10];
694         u8        reserved_at_10[0x9];
695         u8        op_swap_endianness[0x1];
696         u8        op_min[0x1];
697         u8        op_xor[0x1];
698         u8        op_or[0x1];
699         u8        op_and[0x1];
700         u8        op_max[0x1];
701         u8        op_add[0x1];
702 };
703
704 struct mlx5_ifc_vector_calc_cap_bits {
705         u8         calc_matrix[0x1];
706         u8         reserved_at_1[0x1f];
707         u8         reserved_at_20[0x8];
708         u8         max_vec_count[0x8];
709         u8         reserved_at_30[0xd];
710         u8         max_chunk_size[0x3];
711         struct mlx5_ifc_calc_op calc0;
712         struct mlx5_ifc_calc_op calc1;
713         struct mlx5_ifc_calc_op calc2;
714         struct mlx5_ifc_calc_op calc3;
715
716         u8         reserved_at_e0[0x720];
717 };
718
719 enum {
720         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
721         MLX5_WQ_TYPE_CYCLIC       = 0x1,
722         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
723 };
724
725 enum {
726         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
727         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
728 };
729
730 enum {
731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
734         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
735         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
736 };
737
738 enum {
739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
743         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
744         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
745 };
746
747 enum {
748         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
749         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
750 };
751
752 enum {
753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
754         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
755         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
756 };
757
758 enum {
759         MLX5_CAP_PORT_TYPE_IB  = 0x0,
760         MLX5_CAP_PORT_TYPE_ETH = 0x1,
761 };
762
763 struct mlx5_ifc_cmd_hca_cap_bits {
764         u8         reserved_at_0[0x80];
765
766         u8         log_max_srq_sz[0x8];
767         u8         log_max_qp_sz[0x8];
768         u8         reserved_at_90[0xb];
769         u8         log_max_qp[0x5];
770
771         u8         reserved_at_a0[0xb];
772         u8         log_max_srq[0x5];
773         u8         reserved_at_b0[0x10];
774
775         u8         reserved_at_c0[0x8];
776         u8         log_max_cq_sz[0x8];
777         u8         reserved_at_d0[0xb];
778         u8         log_max_cq[0x5];
779
780         u8         log_max_eq_sz[0x8];
781         u8         reserved_at_e8[0x2];
782         u8         log_max_mkey[0x6];
783         u8         reserved_at_f0[0xc];
784         u8         log_max_eq[0x4];
785
786         u8         max_indirection[0x8];
787         u8         fixed_buffer_size[0x1];
788         u8         log_max_mrw_sz[0x7];
789         u8         reserved_at_110[0x2];
790         u8         log_max_bsf_list_size[0x6];
791         u8         umr_extended_translation_offset[0x1];
792         u8         null_mkey[0x1];
793         u8         log_max_klm_list_size[0x6];
794
795         u8         reserved_at_120[0xa];
796         u8         log_max_ra_req_dc[0x6];
797         u8         reserved_at_130[0xa];
798         u8         log_max_ra_res_dc[0x6];
799
800         u8         reserved_at_140[0xa];
801         u8         log_max_ra_req_qp[0x6];
802         u8         reserved_at_150[0xa];
803         u8         log_max_ra_res_qp[0x6];
804
805         u8         pad_cap[0x1];
806         u8         cc_query_allowed[0x1];
807         u8         cc_modify_allowed[0x1];
808         u8         reserved_at_163[0xd];
809         u8         gid_table_size[0x10];
810
811         u8         out_of_seq_cnt[0x1];
812         u8         vport_counters[0x1];
813         u8         retransmission_q_counters[0x1];
814         u8         reserved_at_183[0x1];
815         u8         modify_rq_counter_set_id[0x1];
816         u8         reserved_at_185[0x1];
817         u8         max_qp_cnt[0xa];
818         u8         pkey_table_size[0x10];
819
820         u8         vport_group_manager[0x1];
821         u8         vhca_group_manager[0x1];
822         u8         ib_virt[0x1];
823         u8         eth_virt[0x1];
824         u8         reserved_at_1a4[0x1];
825         u8         ets[0x1];
826         u8         nic_flow_table[0x1];
827         u8         eswitch_flow_table[0x1];
828         u8         early_vf_enable[0x1];
829         u8         mcam_reg[0x1];
830         u8         pcam_reg[0x1];
831         u8         local_ca_ack_delay[0x5];
832         u8         port_module_event[0x1];
833         u8         reserved_at_1b1[0x1];
834         u8         ports_check[0x1];
835         u8         reserved_at_1b3[0x1];
836         u8         disable_link_up[0x1];
837         u8         beacon_led[0x1];
838         u8         port_type[0x2];
839         u8         num_ports[0x8];
840
841         u8         reserved_at_1c0[0x1];
842         u8         pps[0x1];
843         u8         pps_modify[0x1];
844         u8         log_max_msg[0x5];
845         u8         reserved_at_1c8[0x4];
846         u8         max_tc[0x4];
847         u8         reserved_at_1d0[0x1];
848         u8         dcbx[0x1];
849         u8         reserved_at_1d2[0x4];
850         u8         rol_s[0x1];
851         u8         rol_g[0x1];
852         u8         reserved_at_1d8[0x1];
853         u8         wol_s[0x1];
854         u8         wol_g[0x1];
855         u8         wol_a[0x1];
856         u8         wol_b[0x1];
857         u8         wol_m[0x1];
858         u8         wol_u[0x1];
859         u8         wol_p[0x1];
860
861         u8         stat_rate_support[0x10];
862         u8         reserved_at_1f0[0xc];
863         u8         cqe_version[0x4];
864
865         u8         compact_address_vector[0x1];
866         u8         striding_rq[0x1];
867         u8         reserved_at_202[0x2];
868         u8         ipoib_basic_offloads[0x1];
869         u8         reserved_at_205[0xa];
870         u8         drain_sigerr[0x1];
871         u8         cmdif_checksum[0x2];
872         u8         sigerr_cqe[0x1];
873         u8         reserved_at_213[0x1];
874         u8         wq_signature[0x1];
875         u8         sctr_data_cqe[0x1];
876         u8         reserved_at_216[0x1];
877         u8         sho[0x1];
878         u8         tph[0x1];
879         u8         rf[0x1];
880         u8         dct[0x1];
881         u8         qos[0x1];
882         u8         eth_net_offloads[0x1];
883         u8         roce[0x1];
884         u8         atomic[0x1];
885         u8         reserved_at_21f[0x1];
886
887         u8         cq_oi[0x1];
888         u8         cq_resize[0x1];
889         u8         cq_moderation[0x1];
890         u8         reserved_at_223[0x3];
891         u8         cq_eq_remap[0x1];
892         u8         pg[0x1];
893         u8         block_lb_mc[0x1];
894         u8         reserved_at_229[0x1];
895         u8         scqe_break_moderation[0x1];
896         u8         cq_period_start_from_cqe[0x1];
897         u8         cd[0x1];
898         u8         reserved_at_22d[0x1];
899         u8         apm[0x1];
900         u8         vector_calc[0x1];
901         u8         umr_ptr_rlky[0x1];
902         u8         imaicl[0x1];
903         u8         reserved_at_232[0x4];
904         u8         qkv[0x1];
905         u8         pkv[0x1];
906         u8         set_deth_sqpn[0x1];
907         u8         reserved_at_239[0x3];
908         u8         xrc[0x1];
909         u8         ud[0x1];
910         u8         uc[0x1];
911         u8         rc[0x1];
912
913         u8         uar_4k[0x1];
914         u8         reserved_at_241[0x9];
915         u8         uar_sz[0x6];
916         u8         reserved_at_250[0x8];
917         u8         log_pg_sz[0x8];
918
919         u8         bf[0x1];
920         u8         driver_version[0x1];
921         u8         pad_tx_eth_packet[0x1];
922         u8         reserved_at_263[0x8];
923         u8         log_bf_reg_size[0x5];
924
925         u8         reserved_at_270[0xb];
926         u8         lag_master[0x1];
927         u8         num_lag_ports[0x4];
928
929         u8         reserved_at_280[0x10];
930         u8         max_wqe_sz_sq[0x10];
931
932         u8         reserved_at_2a0[0x10];
933         u8         max_wqe_sz_rq[0x10];
934
935         u8         reserved_at_2c0[0x10];
936         u8         max_wqe_sz_sq_dc[0x10];
937
938         u8         reserved_at_2e0[0x7];
939         u8         max_qp_mcg[0x19];
940
941         u8         reserved_at_300[0x18];
942         u8         log_max_mcg[0x8];
943
944         u8         reserved_at_320[0x3];
945         u8         log_max_transport_domain[0x5];
946         u8         reserved_at_328[0x3];
947         u8         log_max_pd[0x5];
948         u8         reserved_at_330[0xb];
949         u8         log_max_xrcd[0x5];
950
951         u8         reserved_at_340[0x8];
952         u8         log_max_flow_counter_bulk[0x8];
953         u8         max_flow_counter[0x10];
954
955
956         u8         reserved_at_360[0x3];
957         u8         log_max_rq[0x5];
958         u8         reserved_at_368[0x3];
959         u8         log_max_sq[0x5];
960         u8         reserved_at_370[0x3];
961         u8         log_max_tir[0x5];
962         u8         reserved_at_378[0x3];
963         u8         log_max_tis[0x5];
964
965         u8         basic_cyclic_rcv_wqe[0x1];
966         u8         reserved_at_381[0x2];
967         u8         log_max_rmp[0x5];
968         u8         reserved_at_388[0x3];
969         u8         log_max_rqt[0x5];
970         u8         reserved_at_390[0x3];
971         u8         log_max_rqt_size[0x5];
972         u8         reserved_at_398[0x3];
973         u8         log_max_tis_per_sq[0x5];
974
975         u8         reserved_at_3a0[0x3];
976         u8         log_max_stride_sz_rq[0x5];
977         u8         reserved_at_3a8[0x3];
978         u8         log_min_stride_sz_rq[0x5];
979         u8         reserved_at_3b0[0x3];
980         u8         log_max_stride_sz_sq[0x5];
981         u8         reserved_at_3b8[0x3];
982         u8         log_min_stride_sz_sq[0x5];
983
984         u8         reserved_at_3c0[0x1b];
985         u8         log_max_wq_sz[0x5];
986
987         u8         nic_vport_change_event[0x1];
988         u8         reserved_at_3e1[0xa];
989         u8         log_max_vlan_list[0x5];
990         u8         reserved_at_3f0[0x3];
991         u8         log_max_current_mc_list[0x5];
992         u8         reserved_at_3f8[0x3];
993         u8         log_max_current_uc_list[0x5];
994
995         u8         reserved_at_400[0x80];
996
997         u8         reserved_at_480[0x3];
998         u8         log_max_l2_table[0x5];
999         u8         reserved_at_488[0x8];
1000         u8         log_uar_page_sz[0x10];
1001
1002         u8         reserved_at_4a0[0x20];
1003         u8         device_frequency_mhz[0x20];
1004         u8         device_frequency_khz[0x20];
1005
1006         u8         reserved_at_500[0x20];
1007         u8         num_of_uars_per_page[0x20];
1008         u8         reserved_at_540[0x40];
1009
1010         u8         reserved_at_580[0x3f];
1011         u8         cqe_compression[0x1];
1012
1013         u8         cqe_compression_timeout[0x10];
1014         u8         cqe_compression_max_num[0x10];
1015
1016         u8         reserved_at_5e0[0x10];
1017         u8         tag_matching[0x1];
1018         u8         rndv_offload_rc[0x1];
1019         u8         rndv_offload_dc[0x1];
1020         u8         log_tag_matching_list_sz[0x5];
1021         u8         reserved_at_5f8[0x3];
1022         u8         log_max_xrq[0x5];
1023
1024         u8         reserved_at_600[0x200];
1025 };
1026
1027 enum mlx5_flow_destination_type {
1028         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1029         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1030         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1031
1032         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1033 };
1034
1035 struct mlx5_ifc_dest_format_struct_bits {
1036         u8         destination_type[0x8];
1037         u8         destination_id[0x18];
1038
1039         u8         reserved_at_20[0x20];
1040 };
1041
1042 struct mlx5_ifc_flow_counter_list_bits {
1043         u8         clear[0x1];
1044         u8         num_of_counters[0xf];
1045         u8         flow_counter_id[0x10];
1046
1047         u8         reserved_at_20[0x20];
1048 };
1049
1050 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1051         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1052         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1053         u8         reserved_at_0[0x40];
1054 };
1055
1056 struct mlx5_ifc_fte_match_param_bits {
1057         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1058
1059         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1060
1061         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1062
1063         u8         reserved_at_600[0xa00];
1064 };
1065
1066 enum {
1067         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1068         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1069         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1070         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1071         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1072 };
1073
1074 struct mlx5_ifc_rx_hash_field_select_bits {
1075         u8         l3_prot_type[0x1];
1076         u8         l4_prot_type[0x1];
1077         u8         selected_fields[0x1e];
1078 };
1079
1080 enum {
1081         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1082         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1083 };
1084
1085 enum {
1086         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1087         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1088 };
1089
1090 struct mlx5_ifc_wq_bits {
1091         u8         wq_type[0x4];
1092         u8         wq_signature[0x1];
1093         u8         end_padding_mode[0x2];
1094         u8         cd_slave[0x1];
1095         u8         reserved_at_8[0x18];
1096
1097         u8         hds_skip_first_sge[0x1];
1098         u8         log2_hds_buf_size[0x3];
1099         u8         reserved_at_24[0x7];
1100         u8         page_offset[0x5];
1101         u8         lwm[0x10];
1102
1103         u8         reserved_at_40[0x8];
1104         u8         pd[0x18];
1105
1106         u8         reserved_at_60[0x8];
1107         u8         uar_page[0x18];
1108
1109         u8         dbr_addr[0x40];
1110
1111         u8         hw_counter[0x20];
1112
1113         u8         sw_counter[0x20];
1114
1115         u8         reserved_at_100[0xc];
1116         u8         log_wq_stride[0x4];
1117         u8         reserved_at_110[0x3];
1118         u8         log_wq_pg_sz[0x5];
1119         u8         reserved_at_118[0x3];
1120         u8         log_wq_sz[0x5];
1121
1122         u8         reserved_at_120[0x15];
1123         u8         log_wqe_num_of_strides[0x3];
1124         u8         two_byte_shift_en[0x1];
1125         u8         reserved_at_139[0x4];
1126         u8         log_wqe_stride_size[0x3];
1127
1128         u8         reserved_at_140[0x4c0];
1129
1130         struct mlx5_ifc_cmd_pas_bits pas[0];
1131 };
1132
1133 struct mlx5_ifc_rq_num_bits {
1134         u8         reserved_at_0[0x8];
1135         u8         rq_num[0x18];
1136 };
1137
1138 struct mlx5_ifc_mac_address_layout_bits {
1139         u8         reserved_at_0[0x10];
1140         u8         mac_addr_47_32[0x10];
1141
1142         u8         mac_addr_31_0[0x20];
1143 };
1144
1145 struct mlx5_ifc_vlan_layout_bits {
1146         u8         reserved_at_0[0x14];
1147         u8         vlan[0x0c];
1148
1149         u8         reserved_at_20[0x20];
1150 };
1151
1152 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1153         u8         reserved_at_0[0xa0];
1154
1155         u8         min_time_between_cnps[0x20];
1156
1157         u8         reserved_at_c0[0x12];
1158         u8         cnp_dscp[0x6];
1159         u8         reserved_at_d8[0x5];
1160         u8         cnp_802p_prio[0x3];
1161
1162         u8         reserved_at_e0[0x720];
1163 };
1164
1165 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1166         u8         reserved_at_0[0x60];
1167
1168         u8         reserved_at_60[0x4];
1169         u8         clamp_tgt_rate[0x1];
1170         u8         reserved_at_65[0x3];
1171         u8         clamp_tgt_rate_after_time_inc[0x1];
1172         u8         reserved_at_69[0x17];
1173
1174         u8         reserved_at_80[0x20];
1175
1176         u8         rpg_time_reset[0x20];
1177
1178         u8         rpg_byte_reset[0x20];
1179
1180         u8         rpg_threshold[0x20];
1181
1182         u8         rpg_max_rate[0x20];
1183
1184         u8         rpg_ai_rate[0x20];
1185
1186         u8         rpg_hai_rate[0x20];
1187
1188         u8         rpg_gd[0x20];
1189
1190         u8         rpg_min_dec_fac[0x20];
1191
1192         u8         rpg_min_rate[0x20];
1193
1194         u8         reserved_at_1c0[0xe0];
1195
1196         u8         rate_to_set_on_first_cnp[0x20];
1197
1198         u8         dce_tcp_g[0x20];
1199
1200         u8         dce_tcp_rtt[0x20];
1201
1202         u8         rate_reduce_monitor_period[0x20];
1203
1204         u8         reserved_at_320[0x20];
1205
1206         u8         initial_alpha_value[0x20];
1207
1208         u8         reserved_at_360[0x4a0];
1209 };
1210
1211 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1212         u8         reserved_at_0[0x80];
1213
1214         u8         rppp_max_rps[0x20];
1215
1216         u8         rpg_time_reset[0x20];
1217
1218         u8         rpg_byte_reset[0x20];
1219
1220         u8         rpg_threshold[0x20];
1221
1222         u8         rpg_max_rate[0x20];
1223
1224         u8         rpg_ai_rate[0x20];
1225
1226         u8         rpg_hai_rate[0x20];
1227
1228         u8         rpg_gd[0x20];
1229
1230         u8         rpg_min_dec_fac[0x20];
1231
1232         u8         rpg_min_rate[0x20];
1233
1234         u8         reserved_at_1c0[0x640];
1235 };
1236
1237 enum {
1238         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1239         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1240         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1241 };
1242
1243 struct mlx5_ifc_resize_field_select_bits {
1244         u8         resize_field_select[0x20];
1245 };
1246
1247 enum {
1248         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1249         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1250         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1251         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1252 };
1253
1254 struct mlx5_ifc_modify_field_select_bits {
1255         u8         modify_field_select[0x20];
1256 };
1257
1258 struct mlx5_ifc_field_select_r_roce_np_bits {
1259         u8         field_select_r_roce_np[0x20];
1260 };
1261
1262 struct mlx5_ifc_field_select_r_roce_rp_bits {
1263         u8         field_select_r_roce_rp[0x20];
1264 };
1265
1266 enum {
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1268         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1269         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1270         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1272         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1273         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1274         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1275         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1276         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1277 };
1278
1279 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1280         u8         field_select_8021qaurp[0x20];
1281 };
1282
1283 struct mlx5_ifc_phys_layer_cntrs_bits {
1284         u8         time_since_last_clear_high[0x20];
1285
1286         u8         time_since_last_clear_low[0x20];
1287
1288         u8         symbol_errors_high[0x20];
1289
1290         u8         symbol_errors_low[0x20];
1291
1292         u8         sync_headers_errors_high[0x20];
1293
1294         u8         sync_headers_errors_low[0x20];
1295
1296         u8         edpl_bip_errors_lane0_high[0x20];
1297
1298         u8         edpl_bip_errors_lane0_low[0x20];
1299
1300         u8         edpl_bip_errors_lane1_high[0x20];
1301
1302         u8         edpl_bip_errors_lane1_low[0x20];
1303
1304         u8         edpl_bip_errors_lane2_high[0x20];
1305
1306         u8         edpl_bip_errors_lane2_low[0x20];
1307
1308         u8         edpl_bip_errors_lane3_high[0x20];
1309
1310         u8         edpl_bip_errors_lane3_low[0x20];
1311
1312         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1313
1314         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1315
1316         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1317
1318         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1319
1320         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1321
1322         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1323
1324         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1325
1326         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1327
1328         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1329
1330         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1331
1332         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1333
1334         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1335
1336         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1337
1338         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1339
1340         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1341
1342         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1343
1344         u8         rs_fec_corrected_blocks_high[0x20];
1345
1346         u8         rs_fec_corrected_blocks_low[0x20];
1347
1348         u8         rs_fec_uncorrectable_blocks_high[0x20];
1349
1350         u8         rs_fec_uncorrectable_blocks_low[0x20];
1351
1352         u8         rs_fec_no_errors_blocks_high[0x20];
1353
1354         u8         rs_fec_no_errors_blocks_low[0x20];
1355
1356         u8         rs_fec_single_error_blocks_high[0x20];
1357
1358         u8         rs_fec_single_error_blocks_low[0x20];
1359
1360         u8         rs_fec_corrected_symbols_total_high[0x20];
1361
1362         u8         rs_fec_corrected_symbols_total_low[0x20];
1363
1364         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1365
1366         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1367
1368         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1369
1370         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1371
1372         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1373
1374         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1375
1376         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1377
1378         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1379
1380         u8         link_down_events[0x20];
1381
1382         u8         successful_recovery_events[0x20];
1383
1384         u8         reserved_at_640[0x180];
1385 };
1386
1387 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1388         u8         symbol_error_counter[0x10];
1389
1390         u8         link_error_recovery_counter[0x8];
1391
1392         u8         link_downed_counter[0x8];
1393
1394         u8         port_rcv_errors[0x10];
1395
1396         u8         port_rcv_remote_physical_errors[0x10];
1397
1398         u8         port_rcv_switch_relay_errors[0x10];
1399
1400         u8         port_xmit_discards[0x10];
1401
1402         u8         port_xmit_constraint_errors[0x8];
1403
1404         u8         port_rcv_constraint_errors[0x8];
1405
1406         u8         reserved_at_70[0x8];
1407
1408         u8         link_overrun_errors[0x8];
1409
1410         u8         reserved_at_80[0x10];
1411
1412         u8         vl_15_dropped[0x10];
1413
1414         u8         reserved_at_a0[0xa0];
1415 };
1416
1417 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1418         u8         transmit_queue_high[0x20];
1419
1420         u8         transmit_queue_low[0x20];
1421
1422         u8         reserved_at_40[0x780];
1423 };
1424
1425 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1426         u8         rx_octets_high[0x20];
1427
1428         u8         rx_octets_low[0x20];
1429
1430         u8         reserved_at_40[0xc0];
1431
1432         u8         rx_frames_high[0x20];
1433
1434         u8         rx_frames_low[0x20];
1435
1436         u8         tx_octets_high[0x20];
1437
1438         u8         tx_octets_low[0x20];
1439
1440         u8         reserved_at_180[0xc0];
1441
1442         u8         tx_frames_high[0x20];
1443
1444         u8         tx_frames_low[0x20];
1445
1446         u8         rx_pause_high[0x20];
1447
1448         u8         rx_pause_low[0x20];
1449
1450         u8         rx_pause_duration_high[0x20];
1451
1452         u8         rx_pause_duration_low[0x20];
1453
1454         u8         tx_pause_high[0x20];
1455
1456         u8         tx_pause_low[0x20];
1457
1458         u8         tx_pause_duration_high[0x20];
1459
1460         u8         tx_pause_duration_low[0x20];
1461
1462         u8         rx_pause_transition_high[0x20];
1463
1464         u8         rx_pause_transition_low[0x20];
1465
1466         u8         reserved_at_3c0[0x400];
1467 };
1468
1469 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1470         u8         port_transmit_wait_high[0x20];
1471
1472         u8         port_transmit_wait_low[0x20];
1473
1474         u8         reserved_at_40[0x780];
1475 };
1476
1477 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1478         u8         dot3stats_alignment_errors_high[0x20];
1479
1480         u8         dot3stats_alignment_errors_low[0x20];
1481
1482         u8         dot3stats_fcs_errors_high[0x20];
1483
1484         u8         dot3stats_fcs_errors_low[0x20];
1485
1486         u8         dot3stats_single_collision_frames_high[0x20];
1487
1488         u8         dot3stats_single_collision_frames_low[0x20];
1489
1490         u8         dot3stats_multiple_collision_frames_high[0x20];
1491
1492         u8         dot3stats_multiple_collision_frames_low[0x20];
1493
1494         u8         dot3stats_sqe_test_errors_high[0x20];
1495
1496         u8         dot3stats_sqe_test_errors_low[0x20];
1497
1498         u8         dot3stats_deferred_transmissions_high[0x20];
1499
1500         u8         dot3stats_deferred_transmissions_low[0x20];
1501
1502         u8         dot3stats_late_collisions_high[0x20];
1503
1504         u8         dot3stats_late_collisions_low[0x20];
1505
1506         u8         dot3stats_excessive_collisions_high[0x20];
1507
1508         u8         dot3stats_excessive_collisions_low[0x20];
1509
1510         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1511
1512         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1513
1514         u8         dot3stats_carrier_sense_errors_high[0x20];
1515
1516         u8         dot3stats_carrier_sense_errors_low[0x20];
1517
1518         u8         dot3stats_frame_too_longs_high[0x20];
1519
1520         u8         dot3stats_frame_too_longs_low[0x20];
1521
1522         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1523
1524         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1525
1526         u8         dot3stats_symbol_errors_high[0x20];
1527
1528         u8         dot3stats_symbol_errors_low[0x20];
1529
1530         u8         dot3control_in_unknown_opcodes_high[0x20];
1531
1532         u8         dot3control_in_unknown_opcodes_low[0x20];
1533
1534         u8         dot3in_pause_frames_high[0x20];
1535
1536         u8         dot3in_pause_frames_low[0x20];
1537
1538         u8         dot3out_pause_frames_high[0x20];
1539
1540         u8         dot3out_pause_frames_low[0x20];
1541
1542         u8         reserved_at_400[0x3c0];
1543 };
1544
1545 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1546         u8         ether_stats_drop_events_high[0x20];
1547
1548         u8         ether_stats_drop_events_low[0x20];
1549
1550         u8         ether_stats_octets_high[0x20];
1551
1552         u8         ether_stats_octets_low[0x20];
1553
1554         u8         ether_stats_pkts_high[0x20];
1555
1556         u8         ether_stats_pkts_low[0x20];
1557
1558         u8         ether_stats_broadcast_pkts_high[0x20];
1559
1560         u8         ether_stats_broadcast_pkts_low[0x20];
1561
1562         u8         ether_stats_multicast_pkts_high[0x20];
1563
1564         u8         ether_stats_multicast_pkts_low[0x20];
1565
1566         u8         ether_stats_crc_align_errors_high[0x20];
1567
1568         u8         ether_stats_crc_align_errors_low[0x20];
1569
1570         u8         ether_stats_undersize_pkts_high[0x20];
1571
1572         u8         ether_stats_undersize_pkts_low[0x20];
1573
1574         u8         ether_stats_oversize_pkts_high[0x20];
1575
1576         u8         ether_stats_oversize_pkts_low[0x20];
1577
1578         u8         ether_stats_fragments_high[0x20];
1579
1580         u8         ether_stats_fragments_low[0x20];
1581
1582         u8         ether_stats_jabbers_high[0x20];
1583
1584         u8         ether_stats_jabbers_low[0x20];
1585
1586         u8         ether_stats_collisions_high[0x20];
1587
1588         u8         ether_stats_collisions_low[0x20];
1589
1590         u8         ether_stats_pkts64octets_high[0x20];
1591
1592         u8         ether_stats_pkts64octets_low[0x20];
1593
1594         u8         ether_stats_pkts65to127octets_high[0x20];
1595
1596         u8         ether_stats_pkts65to127octets_low[0x20];
1597
1598         u8         ether_stats_pkts128to255octets_high[0x20];
1599
1600         u8         ether_stats_pkts128to255octets_low[0x20];
1601
1602         u8         ether_stats_pkts256to511octets_high[0x20];
1603
1604         u8         ether_stats_pkts256to511octets_low[0x20];
1605
1606         u8         ether_stats_pkts512to1023octets_high[0x20];
1607
1608         u8         ether_stats_pkts512to1023octets_low[0x20];
1609
1610         u8         ether_stats_pkts1024to1518octets_high[0x20];
1611
1612         u8         ether_stats_pkts1024to1518octets_low[0x20];
1613
1614         u8         ether_stats_pkts1519to2047octets_high[0x20];
1615
1616         u8         ether_stats_pkts1519to2047octets_low[0x20];
1617
1618         u8         ether_stats_pkts2048to4095octets_high[0x20];
1619
1620         u8         ether_stats_pkts2048to4095octets_low[0x20];
1621
1622         u8         ether_stats_pkts4096to8191octets_high[0x20];
1623
1624         u8         ether_stats_pkts4096to8191octets_low[0x20];
1625
1626         u8         ether_stats_pkts8192to10239octets_high[0x20];
1627
1628         u8         ether_stats_pkts8192to10239octets_low[0x20];
1629
1630         u8         reserved_at_540[0x280];
1631 };
1632
1633 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1634         u8         if_in_octets_high[0x20];
1635
1636         u8         if_in_octets_low[0x20];
1637
1638         u8         if_in_ucast_pkts_high[0x20];
1639
1640         u8         if_in_ucast_pkts_low[0x20];
1641
1642         u8         if_in_discards_high[0x20];
1643
1644         u8         if_in_discards_low[0x20];
1645
1646         u8         if_in_errors_high[0x20];
1647
1648         u8         if_in_errors_low[0x20];
1649
1650         u8         if_in_unknown_protos_high[0x20];
1651
1652         u8         if_in_unknown_protos_low[0x20];
1653
1654         u8         if_out_octets_high[0x20];
1655
1656         u8         if_out_octets_low[0x20];
1657
1658         u8         if_out_ucast_pkts_high[0x20];
1659
1660         u8         if_out_ucast_pkts_low[0x20];
1661
1662         u8         if_out_discards_high[0x20];
1663
1664         u8         if_out_discards_low[0x20];
1665
1666         u8         if_out_errors_high[0x20];
1667
1668         u8         if_out_errors_low[0x20];
1669
1670         u8         if_in_multicast_pkts_high[0x20];
1671
1672         u8         if_in_multicast_pkts_low[0x20];
1673
1674         u8         if_in_broadcast_pkts_high[0x20];
1675
1676         u8         if_in_broadcast_pkts_low[0x20];
1677
1678         u8         if_out_multicast_pkts_high[0x20];
1679
1680         u8         if_out_multicast_pkts_low[0x20];
1681
1682         u8         if_out_broadcast_pkts_high[0x20];
1683
1684         u8         if_out_broadcast_pkts_low[0x20];
1685
1686         u8         reserved_at_340[0x480];
1687 };
1688
1689 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1690         u8         a_frames_transmitted_ok_high[0x20];
1691
1692         u8         a_frames_transmitted_ok_low[0x20];
1693
1694         u8         a_frames_received_ok_high[0x20];
1695
1696         u8         a_frames_received_ok_low[0x20];
1697
1698         u8         a_frame_check_sequence_errors_high[0x20];
1699
1700         u8         a_frame_check_sequence_errors_low[0x20];
1701
1702         u8         a_alignment_errors_high[0x20];
1703
1704         u8         a_alignment_errors_low[0x20];
1705
1706         u8         a_octets_transmitted_ok_high[0x20];
1707
1708         u8         a_octets_transmitted_ok_low[0x20];
1709
1710         u8         a_octets_received_ok_high[0x20];
1711
1712         u8         a_octets_received_ok_low[0x20];
1713
1714         u8         a_multicast_frames_xmitted_ok_high[0x20];
1715
1716         u8         a_multicast_frames_xmitted_ok_low[0x20];
1717
1718         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1719
1720         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1721
1722         u8         a_multicast_frames_received_ok_high[0x20];
1723
1724         u8         a_multicast_frames_received_ok_low[0x20];
1725
1726         u8         a_broadcast_frames_received_ok_high[0x20];
1727
1728         u8         a_broadcast_frames_received_ok_low[0x20];
1729
1730         u8         a_in_range_length_errors_high[0x20];
1731
1732         u8         a_in_range_length_errors_low[0x20];
1733
1734         u8         a_out_of_range_length_field_high[0x20];
1735
1736         u8         a_out_of_range_length_field_low[0x20];
1737
1738         u8         a_frame_too_long_errors_high[0x20];
1739
1740         u8         a_frame_too_long_errors_low[0x20];
1741
1742         u8         a_symbol_error_during_carrier_high[0x20];
1743
1744         u8         a_symbol_error_during_carrier_low[0x20];
1745
1746         u8         a_mac_control_frames_transmitted_high[0x20];
1747
1748         u8         a_mac_control_frames_transmitted_low[0x20];
1749
1750         u8         a_mac_control_frames_received_high[0x20];
1751
1752         u8         a_mac_control_frames_received_low[0x20];
1753
1754         u8         a_unsupported_opcodes_received_high[0x20];
1755
1756         u8         a_unsupported_opcodes_received_low[0x20];
1757
1758         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1759
1760         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1761
1762         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1763
1764         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1765
1766         u8         reserved_at_4c0[0x300];
1767 };
1768
1769 struct mlx5_ifc_cmd_inter_comp_event_bits {
1770         u8         command_completion_vector[0x20];
1771
1772         u8         reserved_at_20[0xc0];
1773 };
1774
1775 struct mlx5_ifc_stall_vl_event_bits {
1776         u8         reserved_at_0[0x18];
1777         u8         port_num[0x1];
1778         u8         reserved_at_19[0x3];
1779         u8         vl[0x4];
1780
1781         u8         reserved_at_20[0xa0];
1782 };
1783
1784 struct mlx5_ifc_db_bf_congestion_event_bits {
1785         u8         event_subtype[0x8];
1786         u8         reserved_at_8[0x8];
1787         u8         congestion_level[0x8];
1788         u8         reserved_at_18[0x8];
1789
1790         u8         reserved_at_20[0xa0];
1791 };
1792
1793 struct mlx5_ifc_gpio_event_bits {
1794         u8         reserved_at_0[0x60];
1795
1796         u8         gpio_event_hi[0x20];
1797
1798         u8         gpio_event_lo[0x20];
1799
1800         u8         reserved_at_a0[0x40];
1801 };
1802
1803 struct mlx5_ifc_port_state_change_event_bits {
1804         u8         reserved_at_0[0x40];
1805
1806         u8         port_num[0x4];
1807         u8         reserved_at_44[0x1c];
1808
1809         u8         reserved_at_60[0x80];
1810 };
1811
1812 struct mlx5_ifc_dropped_packet_logged_bits {
1813         u8         reserved_at_0[0xe0];
1814 };
1815
1816 enum {
1817         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1818         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1819 };
1820
1821 struct mlx5_ifc_cq_error_bits {
1822         u8         reserved_at_0[0x8];
1823         u8         cqn[0x18];
1824
1825         u8         reserved_at_20[0x20];
1826
1827         u8         reserved_at_40[0x18];
1828         u8         syndrome[0x8];
1829
1830         u8         reserved_at_60[0x80];
1831 };
1832
1833 struct mlx5_ifc_rdma_page_fault_event_bits {
1834         u8         bytes_committed[0x20];
1835
1836         u8         r_key[0x20];
1837
1838         u8         reserved_at_40[0x10];
1839         u8         packet_len[0x10];
1840
1841         u8         rdma_op_len[0x20];
1842
1843         u8         rdma_va[0x40];
1844
1845         u8         reserved_at_c0[0x5];
1846         u8         rdma[0x1];
1847         u8         write[0x1];
1848         u8         requestor[0x1];
1849         u8         qp_number[0x18];
1850 };
1851
1852 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1853         u8         bytes_committed[0x20];
1854
1855         u8         reserved_at_20[0x10];
1856         u8         wqe_index[0x10];
1857
1858         u8         reserved_at_40[0x10];
1859         u8         len[0x10];
1860
1861         u8         reserved_at_60[0x60];
1862
1863         u8         reserved_at_c0[0x5];
1864         u8         rdma[0x1];
1865         u8         write_read[0x1];
1866         u8         requestor[0x1];
1867         u8         qpn[0x18];
1868 };
1869
1870 struct mlx5_ifc_qp_events_bits {
1871         u8         reserved_at_0[0xa0];
1872
1873         u8         type[0x8];
1874         u8         reserved_at_a8[0x18];
1875
1876         u8         reserved_at_c0[0x8];
1877         u8         qpn_rqn_sqn[0x18];
1878 };
1879
1880 struct mlx5_ifc_dct_events_bits {
1881         u8         reserved_at_0[0xc0];
1882
1883         u8         reserved_at_c0[0x8];
1884         u8         dct_number[0x18];
1885 };
1886
1887 struct mlx5_ifc_comp_event_bits {
1888         u8         reserved_at_0[0xc0];
1889
1890         u8         reserved_at_c0[0x8];
1891         u8         cq_number[0x18];
1892 };
1893
1894 enum {
1895         MLX5_QPC_STATE_RST        = 0x0,
1896         MLX5_QPC_STATE_INIT       = 0x1,
1897         MLX5_QPC_STATE_RTR        = 0x2,
1898         MLX5_QPC_STATE_RTS        = 0x3,
1899         MLX5_QPC_STATE_SQER       = 0x4,
1900         MLX5_QPC_STATE_ERR        = 0x6,
1901         MLX5_QPC_STATE_SQD        = 0x7,
1902         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1903 };
1904
1905 enum {
1906         MLX5_QPC_ST_RC            = 0x0,
1907         MLX5_QPC_ST_UC            = 0x1,
1908         MLX5_QPC_ST_UD            = 0x2,
1909         MLX5_QPC_ST_XRC           = 0x3,
1910         MLX5_QPC_ST_DCI           = 0x5,
1911         MLX5_QPC_ST_QP0           = 0x7,
1912         MLX5_QPC_ST_QP1           = 0x8,
1913         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1914         MLX5_QPC_ST_REG_UMR       = 0xc,
1915 };
1916
1917 enum {
1918         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1919         MLX5_QPC_PM_STATE_REARM     = 0x1,
1920         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1921         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1922 };
1923
1924 enum {
1925         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1926         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1927 };
1928
1929 enum {
1930         MLX5_QPC_MTU_256_BYTES        = 0x1,
1931         MLX5_QPC_MTU_512_BYTES        = 0x2,
1932         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1933         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1934         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1935         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1936 };
1937
1938 enum {
1939         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1940         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1941         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1942         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1943         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1944         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1945         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1946         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1947 };
1948
1949 enum {
1950         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1951         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1952         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1953 };
1954
1955 enum {
1956         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1957         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1958         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1959 };
1960
1961 struct mlx5_ifc_qpc_bits {
1962         u8         state[0x4];
1963         u8         lag_tx_port_affinity[0x4];
1964         u8         st[0x8];
1965         u8         reserved_at_10[0x3];
1966         u8         pm_state[0x2];
1967         u8         reserved_at_15[0x7];
1968         u8         end_padding_mode[0x2];
1969         u8         reserved_at_1e[0x2];
1970
1971         u8         wq_signature[0x1];
1972         u8         block_lb_mc[0x1];
1973         u8         atomic_like_write_en[0x1];
1974         u8         latency_sensitive[0x1];
1975         u8         reserved_at_24[0x1];
1976         u8         drain_sigerr[0x1];
1977         u8         reserved_at_26[0x2];
1978         u8         pd[0x18];
1979
1980         u8         mtu[0x3];
1981         u8         log_msg_max[0x5];
1982         u8         reserved_at_48[0x1];
1983         u8         log_rq_size[0x4];
1984         u8         log_rq_stride[0x3];
1985         u8         no_sq[0x1];
1986         u8         log_sq_size[0x4];
1987         u8         reserved_at_55[0x6];
1988         u8         rlky[0x1];
1989         u8         ulp_stateless_offload_mode[0x4];
1990
1991         u8         counter_set_id[0x8];
1992         u8         uar_page[0x18];
1993
1994         u8         reserved_at_80[0x8];
1995         u8         user_index[0x18];
1996
1997         u8         reserved_at_a0[0x3];
1998         u8         log_page_size[0x5];
1999         u8         remote_qpn[0x18];
2000
2001         struct mlx5_ifc_ads_bits primary_address_path;
2002
2003         struct mlx5_ifc_ads_bits secondary_address_path;
2004
2005         u8         log_ack_req_freq[0x4];
2006         u8         reserved_at_384[0x4];
2007         u8         log_sra_max[0x3];
2008         u8         reserved_at_38b[0x2];
2009         u8         retry_count[0x3];
2010         u8         rnr_retry[0x3];
2011         u8         reserved_at_393[0x1];
2012         u8         fre[0x1];
2013         u8         cur_rnr_retry[0x3];
2014         u8         cur_retry_count[0x3];
2015         u8         reserved_at_39b[0x5];
2016
2017         u8         reserved_at_3a0[0x20];
2018
2019         u8         reserved_at_3c0[0x8];
2020         u8         next_send_psn[0x18];
2021
2022         u8         reserved_at_3e0[0x8];
2023         u8         cqn_snd[0x18];
2024
2025         u8         reserved_at_400[0x8];
2026         u8         deth_sqpn[0x18];
2027
2028         u8         reserved_at_420[0x20];
2029
2030         u8         reserved_at_440[0x8];
2031         u8         last_acked_psn[0x18];
2032
2033         u8         reserved_at_460[0x8];
2034         u8         ssn[0x18];
2035
2036         u8         reserved_at_480[0x8];
2037         u8         log_rra_max[0x3];
2038         u8         reserved_at_48b[0x1];
2039         u8         atomic_mode[0x4];
2040         u8         rre[0x1];
2041         u8         rwe[0x1];
2042         u8         rae[0x1];
2043         u8         reserved_at_493[0x1];
2044         u8         page_offset[0x6];
2045         u8         reserved_at_49a[0x3];
2046         u8         cd_slave_receive[0x1];
2047         u8         cd_slave_send[0x1];
2048         u8         cd_master[0x1];
2049
2050         u8         reserved_at_4a0[0x3];
2051         u8         min_rnr_nak[0x5];
2052         u8         next_rcv_psn[0x18];
2053
2054         u8         reserved_at_4c0[0x8];
2055         u8         xrcd[0x18];
2056
2057         u8         reserved_at_4e0[0x8];
2058         u8         cqn_rcv[0x18];
2059
2060         u8         dbr_addr[0x40];
2061
2062         u8         q_key[0x20];
2063
2064         u8         reserved_at_560[0x5];
2065         u8         rq_type[0x3];
2066         u8         srqn_rmpn_xrqn[0x18];
2067
2068         u8         reserved_at_580[0x8];
2069         u8         rmsn[0x18];
2070
2071         u8         hw_sq_wqebb_counter[0x10];
2072         u8         sw_sq_wqebb_counter[0x10];
2073
2074         u8         hw_rq_counter[0x20];
2075
2076         u8         sw_rq_counter[0x20];
2077
2078         u8         reserved_at_600[0x20];
2079
2080         u8         reserved_at_620[0xf];
2081         u8         cgs[0x1];
2082         u8         cs_req[0x8];
2083         u8         cs_res[0x8];
2084
2085         u8         dc_access_key[0x40];
2086
2087         u8         reserved_at_680[0xc0];
2088 };
2089
2090 struct mlx5_ifc_roce_addr_layout_bits {
2091         u8         source_l3_address[16][0x8];
2092
2093         u8         reserved_at_80[0x3];
2094         u8         vlan_valid[0x1];
2095         u8         vlan_id[0xc];
2096         u8         source_mac_47_32[0x10];
2097
2098         u8         source_mac_31_0[0x20];
2099
2100         u8         reserved_at_c0[0x14];
2101         u8         roce_l3_type[0x4];
2102         u8         roce_version[0x8];
2103
2104         u8         reserved_at_e0[0x20];
2105 };
2106
2107 union mlx5_ifc_hca_cap_union_bits {
2108         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2109         struct mlx5_ifc_odp_cap_bits odp_cap;
2110         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2111         struct mlx5_ifc_roce_cap_bits roce_cap;
2112         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2113         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2114         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2115         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2116         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2117         struct mlx5_ifc_qos_cap_bits qos_cap;
2118         u8         reserved_at_0[0x8000];
2119 };
2120
2121 enum {
2122         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2123         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2124         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2125         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2126         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2127         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2128 };
2129
2130 struct mlx5_ifc_flow_context_bits {
2131         u8         reserved_at_0[0x20];
2132
2133         u8         group_id[0x20];
2134
2135         u8         reserved_at_40[0x8];
2136         u8         flow_tag[0x18];
2137
2138         u8         reserved_at_60[0x10];
2139         u8         action[0x10];
2140
2141         u8         reserved_at_80[0x8];
2142         u8         destination_list_size[0x18];
2143
2144         u8         reserved_at_a0[0x8];
2145         u8         flow_counter_list_size[0x18];
2146
2147         u8         encap_id[0x20];
2148
2149         u8         reserved_at_e0[0x120];
2150
2151         struct mlx5_ifc_fte_match_param_bits match_value;
2152
2153         u8         reserved_at_1200[0x600];
2154
2155         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2156 };
2157
2158 enum {
2159         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2160         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2161 };
2162
2163 struct mlx5_ifc_xrc_srqc_bits {
2164         u8         state[0x4];
2165         u8         log_xrc_srq_size[0x4];
2166         u8         reserved_at_8[0x18];
2167
2168         u8         wq_signature[0x1];
2169         u8         cont_srq[0x1];
2170         u8         reserved_at_22[0x1];
2171         u8         rlky[0x1];
2172         u8         basic_cyclic_rcv_wqe[0x1];
2173         u8         log_rq_stride[0x3];
2174         u8         xrcd[0x18];
2175
2176         u8         page_offset[0x6];
2177         u8         reserved_at_46[0x2];
2178         u8         cqn[0x18];
2179
2180         u8         reserved_at_60[0x20];
2181
2182         u8         user_index_equal_xrc_srqn[0x1];
2183         u8         reserved_at_81[0x1];
2184         u8         log_page_size[0x6];
2185         u8         user_index[0x18];
2186
2187         u8         reserved_at_a0[0x20];
2188
2189         u8         reserved_at_c0[0x8];
2190         u8         pd[0x18];
2191
2192         u8         lwm[0x10];
2193         u8         wqe_cnt[0x10];
2194
2195         u8         reserved_at_100[0x40];
2196
2197         u8         db_record_addr_h[0x20];
2198
2199         u8         db_record_addr_l[0x1e];
2200         u8         reserved_at_17e[0x2];
2201
2202         u8         reserved_at_180[0x80];
2203 };
2204
2205 struct mlx5_ifc_traffic_counter_bits {
2206         u8         packets[0x40];
2207
2208         u8         octets[0x40];
2209 };
2210
2211 struct mlx5_ifc_tisc_bits {
2212         u8         strict_lag_tx_port_affinity[0x1];
2213         u8         reserved_at_1[0x3];
2214         u8         lag_tx_port_affinity[0x04];
2215
2216         u8         reserved_at_8[0x4];
2217         u8         prio[0x4];
2218         u8         reserved_at_10[0x10];
2219
2220         u8         reserved_at_20[0x100];
2221
2222         u8         reserved_at_120[0x8];
2223         u8         transport_domain[0x18];
2224
2225         u8         reserved_at_140[0x3c0];
2226 };
2227
2228 enum {
2229         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2230         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2231 };
2232
2233 enum {
2234         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2235         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2236 };
2237
2238 enum {
2239         MLX5_RX_HASH_FN_NONE           = 0x0,
2240         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2241         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2242 };
2243
2244 enum {
2245         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2246         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2247 };
2248
2249 struct mlx5_ifc_tirc_bits {
2250         u8         reserved_at_0[0x20];
2251
2252         u8         disp_type[0x4];
2253         u8         reserved_at_24[0x1c];
2254
2255         u8         reserved_at_40[0x40];
2256
2257         u8         reserved_at_80[0x4];
2258         u8         lro_timeout_period_usecs[0x10];
2259         u8         lro_enable_mask[0x4];
2260         u8         lro_max_ip_payload_size[0x8];
2261
2262         u8         reserved_at_a0[0x40];
2263
2264         u8         reserved_at_e0[0x8];
2265         u8         inline_rqn[0x18];
2266
2267         u8         rx_hash_symmetric[0x1];
2268         u8         reserved_at_101[0x1];
2269         u8         tunneled_offload_en[0x1];
2270         u8         reserved_at_103[0x5];
2271         u8         indirect_table[0x18];
2272
2273         u8         rx_hash_fn[0x4];
2274         u8         reserved_at_124[0x2];
2275         u8         self_lb_block[0x2];
2276         u8         transport_domain[0x18];
2277
2278         u8         rx_hash_toeplitz_key[10][0x20];
2279
2280         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2281
2282         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2283
2284         u8         reserved_at_2c0[0x4c0];
2285 };
2286
2287 enum {
2288         MLX5_SRQC_STATE_GOOD   = 0x0,
2289         MLX5_SRQC_STATE_ERROR  = 0x1,
2290 };
2291
2292 struct mlx5_ifc_srqc_bits {
2293         u8         state[0x4];
2294         u8         log_srq_size[0x4];
2295         u8         reserved_at_8[0x18];
2296
2297         u8         wq_signature[0x1];
2298         u8         cont_srq[0x1];
2299         u8         reserved_at_22[0x1];
2300         u8         rlky[0x1];
2301         u8         reserved_at_24[0x1];
2302         u8         log_rq_stride[0x3];
2303         u8         xrcd[0x18];
2304
2305         u8         page_offset[0x6];
2306         u8         reserved_at_46[0x2];
2307         u8         cqn[0x18];
2308
2309         u8         reserved_at_60[0x20];
2310
2311         u8         reserved_at_80[0x2];
2312         u8         log_page_size[0x6];
2313         u8         reserved_at_88[0x18];
2314
2315         u8         reserved_at_a0[0x20];
2316
2317         u8         reserved_at_c0[0x8];
2318         u8         pd[0x18];
2319
2320         u8         lwm[0x10];
2321         u8         wqe_cnt[0x10];
2322
2323         u8         reserved_at_100[0x40];
2324
2325         u8         dbr_addr[0x40];
2326
2327         u8         reserved_at_180[0x80];
2328 };
2329
2330 enum {
2331         MLX5_SQC_STATE_RST  = 0x0,
2332         MLX5_SQC_STATE_RDY  = 0x1,
2333         MLX5_SQC_STATE_ERR  = 0x3,
2334 };
2335
2336 struct mlx5_ifc_sqc_bits {
2337         u8         rlky[0x1];
2338         u8         cd_master[0x1];
2339         u8         fre[0x1];
2340         u8         flush_in_error_en[0x1];
2341         u8         reserved_at_4[0x1];
2342         u8         min_wqe_inline_mode[0x3];
2343         u8         state[0x4];
2344         u8         reg_umr[0x1];
2345         u8         reserved_at_d[0x13];
2346
2347         u8         reserved_at_20[0x8];
2348         u8         user_index[0x18];
2349
2350         u8         reserved_at_40[0x8];
2351         u8         cqn[0x18];
2352
2353         u8         reserved_at_60[0x90];
2354
2355         u8         packet_pacing_rate_limit_index[0x10];
2356         u8         tis_lst_sz[0x10];
2357         u8         reserved_at_110[0x10];
2358
2359         u8         reserved_at_120[0x40];
2360
2361         u8         reserved_at_160[0x8];
2362         u8         tis_num_0[0x18];
2363
2364         struct mlx5_ifc_wq_bits wq;
2365 };
2366
2367 enum {
2368         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2369         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2370         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2371         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2372 };
2373
2374 struct mlx5_ifc_scheduling_context_bits {
2375         u8         element_type[0x8];
2376         u8         reserved_at_8[0x18];
2377
2378         u8         element_attributes[0x20];
2379
2380         u8         parent_element_id[0x20];
2381
2382         u8         reserved_at_60[0x40];
2383
2384         u8         bw_share[0x20];
2385
2386         u8         max_average_bw[0x20];
2387
2388         u8         reserved_at_e0[0x120];
2389 };
2390
2391 struct mlx5_ifc_rqtc_bits {
2392         u8         reserved_at_0[0xa0];
2393
2394         u8         reserved_at_a0[0x10];
2395         u8         rqt_max_size[0x10];
2396
2397         u8         reserved_at_c0[0x10];
2398         u8         rqt_actual_size[0x10];
2399
2400         u8         reserved_at_e0[0x6a0];
2401
2402         struct mlx5_ifc_rq_num_bits rq_num[0];
2403 };
2404
2405 enum {
2406         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2407         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2408 };
2409
2410 enum {
2411         MLX5_RQC_STATE_RST  = 0x0,
2412         MLX5_RQC_STATE_RDY  = 0x1,
2413         MLX5_RQC_STATE_ERR  = 0x3,
2414 };
2415
2416 struct mlx5_ifc_rqc_bits {
2417         u8         rlky[0x1];
2418         u8         reserved_at_1[0x1];
2419         u8         scatter_fcs[0x1];
2420         u8         vsd[0x1];
2421         u8         mem_rq_type[0x4];
2422         u8         state[0x4];
2423         u8         reserved_at_c[0x1];
2424         u8         flush_in_error_en[0x1];
2425         u8         reserved_at_e[0x12];
2426
2427         u8         reserved_at_20[0x8];
2428         u8         user_index[0x18];
2429
2430         u8         reserved_at_40[0x8];
2431         u8         cqn[0x18];
2432
2433         u8         counter_set_id[0x8];
2434         u8         reserved_at_68[0x18];
2435
2436         u8         reserved_at_80[0x8];
2437         u8         rmpn[0x18];
2438
2439         u8         reserved_at_a0[0xe0];
2440
2441         struct mlx5_ifc_wq_bits wq;
2442 };
2443
2444 enum {
2445         MLX5_RMPC_STATE_RDY  = 0x1,
2446         MLX5_RMPC_STATE_ERR  = 0x3,
2447 };
2448
2449 struct mlx5_ifc_rmpc_bits {
2450         u8         reserved_at_0[0x8];
2451         u8         state[0x4];
2452         u8         reserved_at_c[0x14];
2453
2454         u8         basic_cyclic_rcv_wqe[0x1];
2455         u8         reserved_at_21[0x1f];
2456
2457         u8         reserved_at_40[0x140];
2458
2459         struct mlx5_ifc_wq_bits wq;
2460 };
2461
2462 struct mlx5_ifc_nic_vport_context_bits {
2463         u8         reserved_at_0[0x5];
2464         u8         min_wqe_inline_mode[0x3];
2465         u8         reserved_at_8[0x17];
2466         u8         roce_en[0x1];
2467
2468         u8         arm_change_event[0x1];
2469         u8         reserved_at_21[0x1a];
2470         u8         event_on_mtu[0x1];
2471         u8         event_on_promisc_change[0x1];
2472         u8         event_on_vlan_change[0x1];
2473         u8         event_on_mc_address_change[0x1];
2474         u8         event_on_uc_address_change[0x1];
2475
2476         u8         reserved_at_40[0xf0];
2477
2478         u8         mtu[0x10];
2479
2480         u8         system_image_guid[0x40];
2481         u8         port_guid[0x40];
2482         u8         node_guid[0x40];
2483
2484         u8         reserved_at_200[0x140];
2485         u8         qkey_violation_counter[0x10];
2486         u8         reserved_at_350[0x430];
2487
2488         u8         promisc_uc[0x1];
2489         u8         promisc_mc[0x1];
2490         u8         promisc_all[0x1];
2491         u8         reserved_at_783[0x2];
2492         u8         allowed_list_type[0x3];
2493         u8         reserved_at_788[0xc];
2494         u8         allowed_list_size[0xc];
2495
2496         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2497
2498         u8         reserved_at_7e0[0x20];
2499
2500         u8         current_uc_mac_address[0][0x40];
2501 };
2502
2503 enum {
2504         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2505         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2506         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2507         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2508 };
2509
2510 struct mlx5_ifc_mkc_bits {
2511         u8         reserved_at_0[0x1];
2512         u8         free[0x1];
2513         u8         reserved_at_2[0xd];
2514         u8         small_fence_on_rdma_read_response[0x1];
2515         u8         umr_en[0x1];
2516         u8         a[0x1];
2517         u8         rw[0x1];
2518         u8         rr[0x1];
2519         u8         lw[0x1];
2520         u8         lr[0x1];
2521         u8         access_mode[0x2];
2522         u8         reserved_at_18[0x8];
2523
2524         u8         qpn[0x18];
2525         u8         mkey_7_0[0x8];
2526
2527         u8         reserved_at_40[0x20];
2528
2529         u8         length64[0x1];
2530         u8         bsf_en[0x1];
2531         u8         sync_umr[0x1];
2532         u8         reserved_at_63[0x2];
2533         u8         expected_sigerr_count[0x1];
2534         u8         reserved_at_66[0x1];
2535         u8         en_rinval[0x1];
2536         u8         pd[0x18];
2537
2538         u8         start_addr[0x40];
2539
2540         u8         len[0x40];
2541
2542         u8         bsf_octword_size[0x20];
2543
2544         u8         reserved_at_120[0x80];
2545
2546         u8         translations_octword_size[0x20];
2547
2548         u8         reserved_at_1c0[0x1b];
2549         u8         log_page_size[0x5];
2550
2551         u8         reserved_at_1e0[0x20];
2552 };
2553
2554 struct mlx5_ifc_pkey_bits {
2555         u8         reserved_at_0[0x10];
2556         u8         pkey[0x10];
2557 };
2558
2559 struct mlx5_ifc_array128_auto_bits {
2560         u8         array128_auto[16][0x8];
2561 };
2562
2563 struct mlx5_ifc_hca_vport_context_bits {
2564         u8         field_select[0x20];
2565
2566         u8         reserved_at_20[0xe0];
2567
2568         u8         sm_virt_aware[0x1];
2569         u8         has_smi[0x1];
2570         u8         has_raw[0x1];
2571         u8         grh_required[0x1];
2572         u8         reserved_at_104[0xc];
2573         u8         port_physical_state[0x4];
2574         u8         vport_state_policy[0x4];
2575         u8         port_state[0x4];
2576         u8         vport_state[0x4];
2577
2578         u8         reserved_at_120[0x20];
2579
2580         u8         system_image_guid[0x40];
2581
2582         u8         port_guid[0x40];
2583
2584         u8         node_guid[0x40];
2585
2586         u8         cap_mask1[0x20];
2587
2588         u8         cap_mask1_field_select[0x20];
2589
2590         u8         cap_mask2[0x20];
2591
2592         u8         cap_mask2_field_select[0x20];
2593
2594         u8         reserved_at_280[0x80];
2595
2596         u8         lid[0x10];
2597         u8         reserved_at_310[0x4];
2598         u8         init_type_reply[0x4];
2599         u8         lmc[0x3];
2600         u8         subnet_timeout[0x5];
2601
2602         u8         sm_lid[0x10];
2603         u8         sm_sl[0x4];
2604         u8         reserved_at_334[0xc];
2605
2606         u8         qkey_violation_counter[0x10];
2607         u8         pkey_violation_counter[0x10];
2608
2609         u8         reserved_at_360[0xca0];
2610 };
2611
2612 struct mlx5_ifc_esw_vport_context_bits {
2613         u8         reserved_at_0[0x3];
2614         u8         vport_svlan_strip[0x1];
2615         u8         vport_cvlan_strip[0x1];
2616         u8         vport_svlan_insert[0x1];
2617         u8         vport_cvlan_insert[0x2];
2618         u8         reserved_at_8[0x18];
2619
2620         u8         reserved_at_20[0x20];
2621
2622         u8         svlan_cfi[0x1];
2623         u8         svlan_pcp[0x3];
2624         u8         svlan_id[0xc];
2625         u8         cvlan_cfi[0x1];
2626         u8         cvlan_pcp[0x3];
2627         u8         cvlan_id[0xc];
2628
2629         u8         reserved_at_60[0x7a0];
2630 };
2631
2632 enum {
2633         MLX5_EQC_STATUS_OK                = 0x0,
2634         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2635 };
2636
2637 enum {
2638         MLX5_EQC_ST_ARMED  = 0x9,
2639         MLX5_EQC_ST_FIRED  = 0xa,
2640 };
2641
2642 struct mlx5_ifc_eqc_bits {
2643         u8         status[0x4];
2644         u8         reserved_at_4[0x9];
2645         u8         ec[0x1];
2646         u8         oi[0x1];
2647         u8         reserved_at_f[0x5];
2648         u8         st[0x4];
2649         u8         reserved_at_18[0x8];
2650
2651         u8         reserved_at_20[0x20];
2652
2653         u8         reserved_at_40[0x14];
2654         u8         page_offset[0x6];
2655         u8         reserved_at_5a[0x6];
2656
2657         u8         reserved_at_60[0x3];
2658         u8         log_eq_size[0x5];
2659         u8         uar_page[0x18];
2660
2661         u8         reserved_at_80[0x20];
2662
2663         u8         reserved_at_a0[0x18];
2664         u8         intr[0x8];
2665
2666         u8         reserved_at_c0[0x3];
2667         u8         log_page_size[0x5];
2668         u8         reserved_at_c8[0x18];
2669
2670         u8         reserved_at_e0[0x60];
2671
2672         u8         reserved_at_140[0x8];
2673         u8         consumer_counter[0x18];
2674
2675         u8         reserved_at_160[0x8];
2676         u8         producer_counter[0x18];
2677
2678         u8         reserved_at_180[0x80];
2679 };
2680
2681 enum {
2682         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2683         MLX5_DCTC_STATE_DRAINING  = 0x1,
2684         MLX5_DCTC_STATE_DRAINED   = 0x2,
2685 };
2686
2687 enum {
2688         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2689         MLX5_DCTC_CS_RES_NA         = 0x1,
2690         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2691 };
2692
2693 enum {
2694         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2695         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2696         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2697         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2698         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2699 };
2700
2701 struct mlx5_ifc_dctc_bits {
2702         u8         reserved_at_0[0x4];
2703         u8         state[0x4];
2704         u8         reserved_at_8[0x18];
2705
2706         u8         reserved_at_20[0x8];
2707         u8         user_index[0x18];
2708
2709         u8         reserved_at_40[0x8];
2710         u8         cqn[0x18];
2711
2712         u8         counter_set_id[0x8];
2713         u8         atomic_mode[0x4];
2714         u8         rre[0x1];
2715         u8         rwe[0x1];
2716         u8         rae[0x1];
2717         u8         atomic_like_write_en[0x1];
2718         u8         latency_sensitive[0x1];
2719         u8         rlky[0x1];
2720         u8         free_ar[0x1];
2721         u8         reserved_at_73[0xd];
2722
2723         u8         reserved_at_80[0x8];
2724         u8         cs_res[0x8];
2725         u8         reserved_at_90[0x3];
2726         u8         min_rnr_nak[0x5];
2727         u8         reserved_at_98[0x8];
2728
2729         u8         reserved_at_a0[0x8];
2730         u8         srqn_xrqn[0x18];
2731
2732         u8         reserved_at_c0[0x8];
2733         u8         pd[0x18];
2734
2735         u8         tclass[0x8];
2736         u8         reserved_at_e8[0x4];
2737         u8         flow_label[0x14];
2738
2739         u8         dc_access_key[0x40];
2740
2741         u8         reserved_at_140[0x5];
2742         u8         mtu[0x3];
2743         u8         port[0x8];
2744         u8         pkey_index[0x10];
2745
2746         u8         reserved_at_160[0x8];
2747         u8         my_addr_index[0x8];
2748         u8         reserved_at_170[0x8];
2749         u8         hop_limit[0x8];
2750
2751         u8         dc_access_key_violation_count[0x20];
2752
2753         u8         reserved_at_1a0[0x14];
2754         u8         dei_cfi[0x1];
2755         u8         eth_prio[0x3];
2756         u8         ecn[0x2];
2757         u8         dscp[0x6];
2758
2759         u8         reserved_at_1c0[0x40];
2760 };
2761
2762 enum {
2763         MLX5_CQC_STATUS_OK             = 0x0,
2764         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2765         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2766 };
2767
2768 enum {
2769         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2770         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2771 };
2772
2773 enum {
2774         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2775         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2776         MLX5_CQC_ST_FIRED                                 = 0xa,
2777 };
2778
2779 enum {
2780         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2781         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2782         MLX5_CQ_PERIOD_NUM_MODES
2783 };
2784
2785 struct mlx5_ifc_cqc_bits {
2786         u8         status[0x4];
2787         u8         reserved_at_4[0x4];
2788         u8         cqe_sz[0x3];
2789         u8         cc[0x1];
2790         u8         reserved_at_c[0x1];
2791         u8         scqe_break_moderation_en[0x1];
2792         u8         oi[0x1];
2793         u8         cq_period_mode[0x2];
2794         u8         cqe_comp_en[0x1];
2795         u8         mini_cqe_res_format[0x2];
2796         u8         st[0x4];
2797         u8         reserved_at_18[0x8];
2798
2799         u8         reserved_at_20[0x20];
2800
2801         u8         reserved_at_40[0x14];
2802         u8         page_offset[0x6];
2803         u8         reserved_at_5a[0x6];
2804
2805         u8         reserved_at_60[0x3];
2806         u8         log_cq_size[0x5];
2807         u8         uar_page[0x18];
2808
2809         u8         reserved_at_80[0x4];
2810         u8         cq_period[0xc];
2811         u8         cq_max_count[0x10];
2812
2813         u8         reserved_at_a0[0x18];
2814         u8         c_eqn[0x8];
2815
2816         u8         reserved_at_c0[0x3];
2817         u8         log_page_size[0x5];
2818         u8         reserved_at_c8[0x18];
2819
2820         u8         reserved_at_e0[0x20];
2821
2822         u8         reserved_at_100[0x8];
2823         u8         last_notified_index[0x18];
2824
2825         u8         reserved_at_120[0x8];
2826         u8         last_solicit_index[0x18];
2827
2828         u8         reserved_at_140[0x8];
2829         u8         consumer_counter[0x18];
2830
2831         u8         reserved_at_160[0x8];
2832         u8         producer_counter[0x18];
2833
2834         u8         reserved_at_180[0x40];
2835
2836         u8         dbr_addr[0x40];
2837 };
2838
2839 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2840         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2841         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2842         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2843         u8         reserved_at_0[0x800];
2844 };
2845
2846 struct mlx5_ifc_query_adapter_param_block_bits {
2847         u8         reserved_at_0[0xc0];
2848
2849         u8         reserved_at_c0[0x8];
2850         u8         ieee_vendor_id[0x18];
2851
2852         u8         reserved_at_e0[0x10];
2853         u8         vsd_vendor_id[0x10];
2854
2855         u8         vsd[208][0x8];
2856
2857         u8         vsd_contd_psid[16][0x8];
2858 };
2859
2860 enum {
2861         MLX5_XRQC_STATE_GOOD   = 0x0,
2862         MLX5_XRQC_STATE_ERROR  = 0x1,
2863 };
2864
2865 enum {
2866         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2867         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2868 };
2869
2870 enum {
2871         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2872 };
2873
2874 struct mlx5_ifc_tag_matching_topology_context_bits {
2875         u8         log_matching_list_sz[0x4];
2876         u8         reserved_at_4[0xc];
2877         u8         append_next_index[0x10];
2878
2879         u8         sw_phase_cnt[0x10];
2880         u8         hw_phase_cnt[0x10];
2881
2882         u8         reserved_at_40[0x40];
2883 };
2884
2885 struct mlx5_ifc_xrqc_bits {
2886         u8         state[0x4];
2887         u8         rlkey[0x1];
2888         u8         reserved_at_5[0xf];
2889         u8         topology[0x4];
2890         u8         reserved_at_18[0x4];
2891         u8         offload[0x4];
2892
2893         u8         reserved_at_20[0x8];
2894         u8         user_index[0x18];
2895
2896         u8         reserved_at_40[0x8];
2897         u8         cqn[0x18];
2898
2899         u8         reserved_at_60[0xa0];
2900
2901         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2902
2903         u8         reserved_at_180[0x880];
2904
2905         struct mlx5_ifc_wq_bits wq;
2906 };
2907
2908 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2909         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2910         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2911         u8         reserved_at_0[0x20];
2912 };
2913
2914 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2915         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2916         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2917         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2918         u8         reserved_at_0[0x20];
2919 };
2920
2921 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2922         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2923         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2924         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2925         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2926         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2927         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2928         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2929         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2930         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2931         u8         reserved_at_0[0x7c0];
2932 };
2933
2934 union mlx5_ifc_event_auto_bits {
2935         struct mlx5_ifc_comp_event_bits comp_event;
2936         struct mlx5_ifc_dct_events_bits dct_events;
2937         struct mlx5_ifc_qp_events_bits qp_events;
2938         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2939         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2940         struct mlx5_ifc_cq_error_bits cq_error;
2941         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2942         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2943         struct mlx5_ifc_gpio_event_bits gpio_event;
2944         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2945         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2946         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2947         u8         reserved_at_0[0xe0];
2948 };
2949
2950 struct mlx5_ifc_health_buffer_bits {
2951         u8         reserved_at_0[0x100];
2952
2953         u8         assert_existptr[0x20];
2954
2955         u8         assert_callra[0x20];
2956
2957         u8         reserved_at_140[0x40];
2958
2959         u8         fw_version[0x20];
2960
2961         u8         hw_id[0x20];
2962
2963         u8         reserved_at_1c0[0x20];
2964
2965         u8         irisc_index[0x8];
2966         u8         synd[0x8];
2967         u8         ext_synd[0x10];
2968 };
2969
2970 struct mlx5_ifc_register_loopback_control_bits {
2971         u8         no_lb[0x1];
2972         u8         reserved_at_1[0x7];
2973         u8         port[0x8];
2974         u8         reserved_at_10[0x10];
2975
2976         u8         reserved_at_20[0x60];
2977 };
2978
2979 struct mlx5_ifc_vport_tc_element_bits {
2980         u8         traffic_class[0x4];
2981         u8         reserved_at_4[0xc];
2982         u8         vport_number[0x10];
2983 };
2984
2985 struct mlx5_ifc_vport_element_bits {
2986         u8         reserved_at_0[0x10];
2987         u8         vport_number[0x10];
2988 };
2989
2990 enum {
2991         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2992         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2993         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2994 };
2995
2996 struct mlx5_ifc_tsar_element_bits {
2997         u8         reserved_at_0[0x8];
2998         u8         tsar_type[0x8];
2999         u8         reserved_at_10[0x10];
3000 };
3001
3002 struct mlx5_ifc_teardown_hca_out_bits {
3003         u8         status[0x8];
3004         u8         reserved_at_8[0x18];
3005
3006         u8         syndrome[0x20];
3007
3008         u8         reserved_at_40[0x40];
3009 };
3010
3011 enum {
3012         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3013         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3014 };
3015
3016 struct mlx5_ifc_teardown_hca_in_bits {
3017         u8         opcode[0x10];
3018         u8         reserved_at_10[0x10];
3019
3020         u8         reserved_at_20[0x10];
3021         u8         op_mod[0x10];
3022
3023         u8         reserved_at_40[0x10];
3024         u8         profile[0x10];
3025
3026         u8         reserved_at_60[0x20];
3027 };
3028
3029 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3030         u8         status[0x8];
3031         u8         reserved_at_8[0x18];
3032
3033         u8         syndrome[0x20];
3034
3035         u8         reserved_at_40[0x40];
3036 };
3037
3038 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3039         u8         opcode[0x10];
3040         u8         reserved_at_10[0x10];
3041
3042         u8         reserved_at_20[0x10];
3043         u8         op_mod[0x10];
3044
3045         u8         reserved_at_40[0x8];
3046         u8         qpn[0x18];
3047
3048         u8         reserved_at_60[0x20];
3049
3050         u8         opt_param_mask[0x20];
3051
3052         u8         reserved_at_a0[0x20];
3053
3054         struct mlx5_ifc_qpc_bits qpc;
3055
3056         u8         reserved_at_800[0x80];
3057 };
3058
3059 struct mlx5_ifc_sqd2rts_qp_out_bits {
3060         u8         status[0x8];
3061         u8         reserved_at_8[0x18];
3062
3063         u8         syndrome[0x20];
3064
3065         u8         reserved_at_40[0x40];
3066 };
3067
3068 struct mlx5_ifc_sqd2rts_qp_in_bits {
3069         u8         opcode[0x10];
3070         u8         reserved_at_10[0x10];
3071
3072         u8         reserved_at_20[0x10];
3073         u8         op_mod[0x10];
3074
3075         u8         reserved_at_40[0x8];
3076         u8         qpn[0x18];
3077
3078         u8         reserved_at_60[0x20];
3079
3080         u8         opt_param_mask[0x20];
3081
3082         u8         reserved_at_a0[0x20];
3083
3084         struct mlx5_ifc_qpc_bits qpc;
3085
3086         u8         reserved_at_800[0x80];
3087 };
3088
3089 struct mlx5_ifc_set_roce_address_out_bits {
3090         u8         status[0x8];
3091         u8         reserved_at_8[0x18];
3092
3093         u8         syndrome[0x20];
3094
3095         u8         reserved_at_40[0x40];
3096 };
3097
3098 struct mlx5_ifc_set_roce_address_in_bits {
3099         u8         opcode[0x10];
3100         u8         reserved_at_10[0x10];
3101
3102         u8         reserved_at_20[0x10];
3103         u8         op_mod[0x10];
3104
3105         u8         roce_address_index[0x10];
3106         u8         reserved_at_50[0x10];
3107
3108         u8         reserved_at_60[0x20];
3109
3110         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3111 };
3112
3113 struct mlx5_ifc_set_mad_demux_out_bits {
3114         u8         status[0x8];
3115         u8         reserved_at_8[0x18];
3116
3117         u8         syndrome[0x20];
3118
3119         u8         reserved_at_40[0x40];
3120 };
3121
3122 enum {
3123         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3124         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3125 };
3126
3127 struct mlx5_ifc_set_mad_demux_in_bits {
3128         u8         opcode[0x10];
3129         u8         reserved_at_10[0x10];
3130
3131         u8         reserved_at_20[0x10];
3132         u8         op_mod[0x10];
3133
3134         u8         reserved_at_40[0x20];
3135
3136         u8         reserved_at_60[0x6];
3137         u8         demux_mode[0x2];
3138         u8         reserved_at_68[0x18];
3139 };
3140
3141 struct mlx5_ifc_set_l2_table_entry_out_bits {
3142         u8         status[0x8];
3143         u8         reserved_at_8[0x18];
3144
3145         u8         syndrome[0x20];
3146
3147         u8         reserved_at_40[0x40];
3148 };
3149
3150 struct mlx5_ifc_set_l2_table_entry_in_bits {
3151         u8         opcode[0x10];
3152         u8         reserved_at_10[0x10];
3153
3154         u8         reserved_at_20[0x10];
3155         u8         op_mod[0x10];
3156
3157         u8         reserved_at_40[0x60];
3158
3159         u8         reserved_at_a0[0x8];
3160         u8         table_index[0x18];
3161
3162         u8         reserved_at_c0[0x20];
3163
3164         u8         reserved_at_e0[0x13];
3165         u8         vlan_valid[0x1];
3166         u8         vlan[0xc];
3167
3168         struct mlx5_ifc_mac_address_layout_bits mac_address;
3169
3170         u8         reserved_at_140[0xc0];
3171 };
3172
3173 struct mlx5_ifc_set_issi_out_bits {
3174         u8         status[0x8];
3175         u8         reserved_at_8[0x18];
3176
3177         u8         syndrome[0x20];
3178
3179         u8         reserved_at_40[0x40];
3180 };
3181
3182 struct mlx5_ifc_set_issi_in_bits {
3183         u8         opcode[0x10];
3184         u8         reserved_at_10[0x10];
3185
3186         u8         reserved_at_20[0x10];
3187         u8         op_mod[0x10];
3188
3189         u8         reserved_at_40[0x10];
3190         u8         current_issi[0x10];
3191
3192         u8         reserved_at_60[0x20];
3193 };
3194
3195 struct mlx5_ifc_set_hca_cap_out_bits {
3196         u8         status[0x8];
3197         u8         reserved_at_8[0x18];
3198
3199         u8         syndrome[0x20];
3200
3201         u8         reserved_at_40[0x40];
3202 };
3203
3204 struct mlx5_ifc_set_hca_cap_in_bits {
3205         u8         opcode[0x10];
3206         u8         reserved_at_10[0x10];
3207
3208         u8         reserved_at_20[0x10];
3209         u8         op_mod[0x10];
3210
3211         u8         reserved_at_40[0x40];
3212
3213         union mlx5_ifc_hca_cap_union_bits capability;
3214 };
3215
3216 enum {
3217         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3218         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3219         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3220         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3221 };
3222
3223 struct mlx5_ifc_set_fte_out_bits {
3224         u8         status[0x8];
3225         u8         reserved_at_8[0x18];
3226
3227         u8         syndrome[0x20];
3228
3229         u8         reserved_at_40[0x40];
3230 };
3231
3232 struct mlx5_ifc_set_fte_in_bits {
3233         u8         opcode[0x10];
3234         u8         reserved_at_10[0x10];
3235
3236         u8         reserved_at_20[0x10];
3237         u8         op_mod[0x10];
3238
3239         u8         other_vport[0x1];
3240         u8         reserved_at_41[0xf];
3241         u8         vport_number[0x10];
3242
3243         u8         reserved_at_60[0x20];
3244
3245         u8         table_type[0x8];
3246         u8         reserved_at_88[0x18];
3247
3248         u8         reserved_at_a0[0x8];
3249         u8         table_id[0x18];
3250
3251         u8         reserved_at_c0[0x18];
3252         u8         modify_enable_mask[0x8];
3253
3254         u8         reserved_at_e0[0x20];
3255
3256         u8         flow_index[0x20];
3257
3258         u8         reserved_at_120[0xe0];
3259
3260         struct mlx5_ifc_flow_context_bits flow_context;
3261 };
3262
3263 struct mlx5_ifc_rts2rts_qp_out_bits {
3264         u8         status[0x8];
3265         u8         reserved_at_8[0x18];
3266
3267         u8         syndrome[0x20];
3268
3269         u8         reserved_at_40[0x40];
3270 };
3271
3272 struct mlx5_ifc_rts2rts_qp_in_bits {
3273         u8         opcode[0x10];
3274         u8         reserved_at_10[0x10];
3275
3276         u8         reserved_at_20[0x10];