include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         atomic[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         cvlan_tag[0x1];
 369         u8         svlan_tag[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_cvlan_tag[0x1];
 402         u8         inner_second_cvlan_tag[0x1];
 403         u8         outer_second_svlan_tag[0x1];
 404         u8         inner_second_svlan_tag[0x1];
 405         u8         reserved_at_64[0xc];
 406         u8         gre_protocol[0x10];
 407
 408         u8         gre_key_h[0x18];
 409         u8         gre_key_l[0x8];
 410
 411         u8         vxlan_vni[0x18];
 412         u8         reserved_at_b8[0x8];
 413
 414         u8         reserved_at_c0[0x20];
 415
 416         u8         reserved_at_e0[0xc];
 417         u8         outer_ipv6_flow_label[0x14];
 418
 419         u8         reserved_at_100[0xc];
 420         u8         inner_ipv6_flow_label[0x14];
 421
 422         u8         reserved_at_120[0xe0];
 423 };
 424
 425 struct mlx5_ifc_cmd_pas_bits {
 426         u8         pa_h[0x20];
 427
 428         u8         pa_l[0x14];
 429         u8         reserved_at_34[0xc];
 430 };
 431
 432 struct mlx5_ifc_uint64_bits {
 433         u8         hi[0x20];
 434
 435         u8         lo[0x20];
 436 };
 437
 438 enum {
 439         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 440         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 441         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 442         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 443         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 444         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 445         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 446         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 447         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 448         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 449 };
 450
 451 struct mlx5_ifc_ads_bits {
 452         u8         fl[0x1];
 453         u8         free_ar[0x1];
 454         u8         reserved_at_2[0xe];
 455         u8         pkey_index[0x10];
 456
 457         u8         reserved_at_20[0x8];
 458         u8         grh[0x1];
 459         u8         mlid[0x7];
 460         u8         rlid[0x10];
 461
 462         u8         ack_timeout[0x5];
 463         u8         reserved_at_45[0x3];
 464         u8         src_addr_index[0x8];
 465         u8         reserved_at_50[0x4];
 466         u8         stat_rate[0x4];
 467         u8         hop_limit[0x8];
 468
 469         u8         reserved_at_60[0x4];
 470         u8         tclass[0x8];
 471         u8         flow_label[0x14];
 472
 473         u8         rgid_rip[16][0x8];
 474
 475         u8         reserved_at_100[0x4];
 476         u8         f_dscp[0x1];
 477         u8         f_ecn[0x1];
 478         u8         reserved_at_106[0x1];
 479         u8         f_eth_prio[0x1];
 480         u8         ecn[0x2];
 481         u8         dscp[0x6];
 482         u8         udp_sport[0x10];
 483
 484         u8         dei_cfi[0x1];
 485         u8         eth_prio[0x3];
 486         u8         sl[0x4];
 487         u8         port[0x8];
 488         u8         rmac_47_32[0x10];
 489
 490         u8         rmac_31_0[0x20];
 491 };
 492
 493 struct mlx5_ifc_flow_table_nic_cap_bits {
 494         u8         nic_rx_multi_path_tirs[0x1];
 495         u8         nic_rx_multi_path_tirs_fts[0x1];
 496         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 497         u8         reserved_at_3[0x1fd];
 498
 499         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 500
 501         u8         reserved_at_400[0x200];
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 504
 505         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 506
 507         u8         reserved_at_a00[0x200];
 508
 509         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 510
 511         u8         reserved_at_e00[0x7200];
 512 };
 513
 514 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 515         u8     reserved_at_0[0x200];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 522
 523         u8      reserved_at_800[0x7800];
 524 };
 525
 526 struct mlx5_ifc_e_switch_cap_bits {
 527         u8         vport_svlan_strip[0x1];
 528         u8         vport_cvlan_strip[0x1];
 529         u8         vport_svlan_insert[0x1];
 530         u8         vport_cvlan_insert_if_not_exist[0x1];
 531         u8         vport_cvlan_insert_overwrite[0x1];
 532         u8         reserved_at_5[0x19];
 533         u8         nic_vport_node_guid_modify[0x1];
 534         u8         nic_vport_port_guid_modify[0x1];
 535
 536         u8         vxlan_encap_decap[0x1];
 537         u8         nvgre_encap_decap[0x1];
 538         u8         reserved_at_22[0x9];
 539         u8         log_max_encap_headers[0x5];
 540         u8         reserved_2b[0x6];
 541         u8         max_encap_header_size[0xa];
 542
 543         u8         reserved_40[0x7c0];
 544
 545 };
 546
 547 struct mlx5_ifc_qos_cap_bits {
 548         u8         packet_pacing[0x1];
 549         u8         esw_scheduling[0x1];
 550         u8         reserved_at_2[0x1e];
 551
 552         u8         reserved_at_20[0x20];
 553
 554         u8         packet_pacing_max_rate[0x20];
 555
 556         u8         packet_pacing_min_rate[0x20];
 557
 558         u8         reserved_at_80[0x10];
 559         u8         packet_pacing_rate_table_size[0x10];
 560
 561         u8         esw_element_type[0x10];
 562         u8         esw_tsar_type[0x10];
 563
 564         u8         reserved_at_c0[0x10];
 565         u8         max_qos_para_vport[0x10];
 566
 567         u8         max_tsar_bw_share[0x20];
 568
 569         u8         reserved_at_100[0x700];
 570 };
 571
 572 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 573         u8         csum_cap[0x1];
 574         u8         vlan_cap[0x1];
 575         u8         lro_cap[0x1];
 576         u8         lro_psh_flag[0x1];
 577         u8         lro_time_stamp[0x1];
 578         u8         reserved_at_5[0x3];
 579         u8         self_lb_en_modifiable[0x1];
 580         u8         reserved_at_9[0x2];
 581         u8         max_lso_cap[0x5];
 582         u8         multi_pkt_send_wqe[0x2];
 583         u8         wqe_inline_mode[0x2];
 584         u8         rss_ind_tbl_cap[0x4];
 585         u8         reg_umr_sq[0x1];
 586         u8         scatter_fcs[0x1];
 587         u8         reserved_at_1a[0x1];
 588         u8         tunnel_lso_const_out_ip_id[0x1];
 589         u8         reserved_at_1c[0x2];
 590         u8         tunnel_statless_gre[0x1];
 591         u8         tunnel_stateless_vxlan[0x1];
 592
 593         u8         reserved_at_20[0x20];
 594
 595         u8         reserved_at_40[0x10];
 596         u8         lro_min_mss_size[0x10];
 597
 598         u8         reserved_at_60[0x120];
 599
 600         u8         lro_timer_supported_periods[4][0x20];
 601
 602         u8         reserved_at_200[0x600];
 603 };
 604
 605 struct mlx5_ifc_roce_cap_bits {
 606         u8         roce_apm[0x1];
 607         u8         reserved_at_1[0x1f];
 608
 609         u8         reserved_at_20[0x60];
 610
 611         u8         reserved_at_80[0xc];
 612         u8         l3_type[0x4];
 613         u8         reserved_at_90[0x8];
 614         u8         roce_version[0x8];
 615
 616         u8         reserved_at_a0[0x10];
 617         u8         r_roce_dest_udp_port[0x10];
 618
 619         u8         r_roce_max_src_udp_port[0x10];
 620         u8         r_roce_min_src_udp_port[0x10];
 621
 622         u8         reserved_at_e0[0x10];
 623         u8         roce_address_table_size[0x10];
 624
 625         u8         reserved_at_100[0x700];
 626 };
 627
 628 enum {
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 636         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 637         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 638 };
 639
 640 enum {
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 650 };
 651
 652 struct mlx5_ifc_atomic_caps_bits {
 653         u8         reserved_at_0[0x40];
 654
 655         u8         atomic_req_8B_endianess_mode[0x2];
 656         u8         reserved_at_42[0x4];
 657         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 658
 659         u8         reserved_at_47[0x19];
 660
 661         u8         reserved_at_60[0x20];
 662
 663         u8         reserved_at_80[0x10];
 664         u8         atomic_operations[0x10];
 665
 666         u8         reserved_at_a0[0x10];
 667         u8         atomic_size_qp[0x10];
 668
 669         u8         reserved_at_c0[0x10];
 670         u8         atomic_size_dc[0x10];
 671
 672         u8         reserved_at_e0[0x720];
 673 };
 674
 675 struct mlx5_ifc_odp_cap_bits {
 676         u8         reserved_at_0[0x40];
 677
 678         u8         sig[0x1];
 679         u8         reserved_at_41[0x1f];
 680
 681         u8         reserved_at_60[0x20];
 682
 683         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 686
 687         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 688
 689         u8         reserved_at_e0[0x720];
 690 };
 691
 692 struct mlx5_ifc_calc_op {
 693         u8        reserved_at_0[0x10];
 694         u8        reserved_at_10[0x9];
 695         u8        op_swap_endianness[0x1];
 696         u8        op_min[0x1];
 697         u8        op_xor[0x1];
 698         u8        op_or[0x1];
 699         u8        op_and[0x1];
 700         u8        op_max[0x1];
 701         u8        op_add[0x1];
 702 };
 703
 704 struct mlx5_ifc_vector_calc_cap_bits {
 705         u8         calc_matrix[0x1];
 706         u8         reserved_at_1[0x1f];
 707         u8         reserved_at_20[0x8];
 708         u8         max_vec_count[0x8];
 709         u8         reserved_at_30[0xd];
 710         u8         max_chunk_size[0x3];
 711         struct mlx5_ifc_calc_op calc0;
 712         struct mlx5_ifc_calc_op calc1;
 713         struct mlx5_ifc_calc_op calc2;
 714         struct mlx5_ifc_calc_op calc3;
 715
 716         u8         reserved_at_e0[0x720];
 717 };
 718
 719 enum {
 720         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 721         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 722         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 723 };
 724
 725 enum {
 726         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 727         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 728 };
 729
 730 enum {
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 734         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 735         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 736 };
 737
 738 enum {
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 743         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 744         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 745 };
 746
 747 enum {
 748         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 749         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 750 };
 751
 752 enum {
 753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 754         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 755         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 756 };
 757
 758 enum {
 759         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 760         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 761 };
 762
 763 struct mlx5_ifc_cmd_hca_cap_bits {
 764         u8         reserved_at_0[0x80];
 765
 766         u8         log_max_srq_sz[0x8];
 767         u8         log_max_qp_sz[0x8];
 768         u8         reserved_at_90[0xb];
 769         u8         log_max_qp[0x5];
 770
 771         u8         reserved_at_a0[0xb];
 772         u8         log_max_srq[0x5];
 773         u8         reserved_at_b0[0x10];
 774
 775         u8         reserved_at_c0[0x8];
 776         u8         log_max_cq_sz[0x8];
 777         u8         reserved_at_d0[0xb];
 778         u8         log_max_cq[0x5];
 779
 780         u8         log_max_eq_sz[0x8];
 781         u8         reserved_at_e8[0x2];
 782         u8         log_max_mkey[0x6];
 783         u8         reserved_at_f0[0xc];
 784         u8         log_max_eq[0x4];
 785
 786         u8         max_indirection[0x8];
 787         u8         fixed_buffer_size[0x1];
 788         u8         log_max_mrw_sz[0x7];
 789         u8         reserved_at_110[0x2];
 790         u8         log_max_bsf_list_size[0x6];
 791         u8         umr_extended_translation_offset[0x1];
 792         u8         null_mkey[0x1];
 793         u8         log_max_klm_list_size[0x6];
 794
 795         u8         reserved_at_120[0xa];
 796         u8         log_max_ra_req_dc[0x6];
 797         u8         reserved_at_130[0xa];
 798         u8         log_max_ra_res_dc[0x6];
 799
 800         u8         reserved_at_140[0xa];
 801         u8         log_max_ra_req_qp[0x6];
 802         u8         reserved_at_150[0xa];
 803         u8         log_max_ra_res_qp[0x6];
 804
 805         u8         pad_cap[0x1];
 806         u8         cc_query_allowed[0x1];
 807         u8         cc_modify_allowed[0x1];
 808         u8         reserved_at_163[0xd];
 809         u8         gid_table_size[0x10];
 810
 811         u8         out_of_seq_cnt[0x1];
 812         u8         vport_counters[0x1];
 813         u8         retransmission_q_counters[0x1];
 814         u8         reserved_at_183[0x1];
 815         u8         modify_rq_counter_set_id[0x1];
 816         u8         reserved_at_185[0x1];
 817         u8         max_qp_cnt[0xa];
 818         u8         pkey_table_size[0x10];
 819
 820         u8         vport_group_manager[0x1];
 821         u8         vhca_group_manager[0x1];
 822         u8         ib_virt[0x1];
 823         u8         eth_virt[0x1];
 824         u8         reserved_at_1a4[0x1];
 825         u8         ets[0x1];
 826         u8         nic_flow_table[0x1];
 827         u8         eswitch_flow_table[0x1];
 828         u8         early_vf_enable[0x1];
 829         u8         mcam_reg[0x1];
 830         u8         pcam_reg[0x1];
 831         u8         local_ca_ack_delay[0x5];
 832         u8         port_module_event[0x1];
 833         u8         reserved_at_1b1[0x1];
 834         u8         ports_check[0x1];
 835         u8         reserved_at_1b3[0x1];
 836         u8         disable_link_up[0x1];
 837         u8         beacon_led[0x1];
 838         u8         port_type[0x2];
 839         u8         num_ports[0x8];
 840
 841         u8         reserved_at_1c0[0x1];
 842         u8         pps[0x1];
 843         u8         pps_modify[0x1];
 844         u8         log_max_msg[0x5];
 845         u8         reserved_at_1c8[0x4];
 846         u8         max_tc[0x4];
 847         u8         reserved_at_1d0[0x1];
 848         u8         dcbx[0x1];
 849         u8         reserved_at_1d2[0x4];
 850         u8         rol_s[0x1];
 851         u8         rol_g[0x1];
 852         u8         reserved_at_1d8[0x1];
 853         u8         wol_s[0x1];
 854         u8         wol_g[0x1];
 855         u8         wol_a[0x1];
 856         u8         wol_b[0x1];
 857         u8         wol_m[0x1];
 858         u8         wol_u[0x1];
 859         u8         wol_p[0x1];
 860
 861         u8         stat_rate_support[0x10];
 862         u8         reserved_at_1f0[0xc];
 863         u8         cqe_version[0x4];
 864
 865         u8         compact_address_vector[0x1];
 866         u8         striding_rq[0x1];
 867         u8         reserved_at_202[0x2];
 868         u8         ipoib_basic_offloads[0x1];
 869         u8         reserved_at_205[0xa];
 870         u8         drain_sigerr[0x1];
 871         u8         cmdif_checksum[0x2];
 872         u8         sigerr_cqe[0x1];
 873         u8         reserved_at_213[0x1];
 874         u8         wq_signature[0x1];
 875         u8         sctr_data_cqe[0x1];
 876         u8         reserved_at_216[0x1];
 877         u8         sho[0x1];
 878         u8         tph[0x1];
 879         u8         rf[0x1];
 880         u8         dct[0x1];
 881         u8         qos[0x1];
 882         u8         eth_net_offloads[0x1];
 883         u8         roce[0x1];
 884         u8         atomic[0x1];
 885         u8         reserved_at_21f[0x1];
 886
 887         u8         cq_oi[0x1];
 888         u8         cq_resize[0x1];
 889         u8         cq_moderation[0x1];
 890         u8         reserved_at_223[0x3];
 891         u8         cq_eq_remap[0x1];
 892         u8         pg[0x1];
 893         u8         block_lb_mc[0x1];
 894         u8         reserved_at_229[0x1];
 895         u8         scqe_break_moderation[0x1];
 896         u8         cq_period_start_from_cqe[0x1];
 897         u8         cd[0x1];
 898         u8         reserved_at_22d[0x1];
 899         u8         apm[0x1];
 900         u8         vector_calc[0x1];
 901         u8         umr_ptr_rlky[0x1];
 902         u8         imaicl[0x1];
 903         u8         reserved_at_232[0x4];
 904         u8         qkv[0x1];
 905         u8         pkv[0x1];
 906         u8         set_deth_sqpn[0x1];
 907         u8         reserved_at_239[0x3];
 908         u8         xrc[0x1];
 909         u8         ud[0x1];
 910         u8         uc[0x1];
 911         u8         rc[0x1];
 912
 913         u8         uar_4k[0x1];
 914         u8         reserved_at_241[0x9];
 915         u8         uar_sz[0x6];
 916         u8         reserved_at_250[0x8];
 917         u8         log_pg_sz[0x8];
 918
 919         u8         bf[0x1];
 920         u8         driver_version[0x1];
 921         u8         pad_tx_eth_packet[0x1];
 922         u8         reserved_at_263[0x8];
 923         u8         log_bf_reg_size[0x5];
 924
 925         u8         reserved_at_270[0xb];
 926         u8         lag_master[0x1];
 927         u8         num_lag_ports[0x4];
 928
 929         u8         reserved_at_280[0x10];
 930         u8         max_wqe_sz_sq[0x10];
 931
 932         u8         reserved_at_2a0[0x10];
 933         u8         max_wqe_sz_rq[0x10];
 934
 935         u8         reserved_at_2c0[0x10];
 936         u8         max_wqe_sz_sq_dc[0x10];
 937
 938         u8         reserved_at_2e0[0x7];
 939         u8         max_qp_mcg[0x19];
 940
 941         u8         reserved_at_300[0x18];
 942         u8         log_max_mcg[0x8];
 943
 944         u8         reserved_at_320[0x3];
 945         u8         log_max_transport_domain[0x5];
 946         u8         reserved_at_328[0x3];
 947         u8         log_max_pd[0x5];
 948         u8         reserved_at_330[0xb];
 949         u8         log_max_xrcd[0x5];
 950
 951         u8         reserved_at_340[0x8];
 952         u8         log_max_flow_counter_bulk[0x8];
 953         u8         max_flow_counter[0x10];
 954
 955
 956         u8         reserved_at_360[0x3];
 957         u8         log_max_rq[0x5];
 958         u8         reserved_at_368[0x3];
 959         u8         log_max_sq[0x5];
 960         u8         reserved_at_370[0x3];
 961         u8         log_max_tir[0x5];
 962         u8         reserved_at_378[0x3];
 963         u8         log_max_tis[0x5];
 964
 965         u8         basic_cyclic_rcv_wqe[0x1];
 966         u8         reserved_at_381[0x2];
 967         u8         log_max_rmp[0x5];
 968         u8         reserved_at_388[0x3];
 969         u8         log_max_rqt[0x5];
 970         u8         reserved_at_390[0x3];
 971         u8         log_max_rqt_size[0x5];
 972         u8         reserved_at_398[0x3];
 973         u8         log_max_tis_per_sq[0x5];
 974
 975         u8         reserved_at_3a0[0x3];
 976         u8         log_max_stride_sz_rq[0x5];
 977         u8         reserved_at_3a8[0x3];
 978         u8         log_min_stride_sz_rq[0x5];
 979         u8         reserved_at_3b0[0x3];
 980         u8         log_max_stride_sz_sq[0x5];
 981         u8         reserved_at_3b8[0x3];
 982         u8         log_min_stride_sz_sq[0x5];
 983
 984         u8         reserved_at_3c0[0x1b];
 985         u8         log_max_wq_sz[0x5];
 986
 987         u8         nic_vport_change_event[0x1];
 988         u8         reserved_at_3e1[0xa];
 989         u8         log_max_vlan_list[0x5];
 990         u8         reserved_at_3f0[0x3];
 991         u8         log_max_current_mc_list[0x5];
 992         u8         reserved_at_3f8[0x3];
 993         u8         log_max_current_uc_list[0x5];
 994
 995         u8         reserved_at_400[0x80];
 996
 997         u8         reserved_at_480[0x3];
 998         u8         log_max_l2_table[0x5];
 999         u8         reserved_at_488[0x8];
1000         u8         log_uar_page_sz[0x10];
1001
1002         u8         reserved_at_4a0[0x20];
1003         u8         device_frequency_mhz[0x20];
1004         u8         device_frequency_khz[0x20];
1005
1006         u8         reserved_at_500[0x20];
1007         u8         num_of_uars_per_page[0x20];
1008         u8         reserved_at_540[0x40];
1009
1010         u8         reserved_at_580[0x3f];
1011         u8         cqe_compression[0x1];
1012
1013         u8         cqe_compression_timeout[0x10];
1014         u8         cqe_compression_max_num[0x10];
1015
1016         u8         reserved_at_5e0[0x10];
1017         u8         tag_matching[0x1];
1018         u8         rndv_offload_rc[0x1];
1019         u8         rndv_offload_dc[0x1];
1020         u8         log_tag_matching_list_sz[0x5];
1021         u8         reserved_at_5f8[0x3];
1022         u8         log_max_xrq[0x5];
1023
1024         u8         reserved_at_600[0x200];
1025 };
1026
1027 enum mlx5_flow_destination_type {
1028         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1029         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1030         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1031
1032         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1033 };
1034
1035 struct mlx5_ifc_dest_format_struct_bits {
1036         u8         destination_type[0x8];
1037         u8         destination_id[0x18];
1038
1039         u8         reserved_at_20[0x20];
1040 };
1041
1042 struct mlx5_ifc_flow_counter_list_bits {
1043         u8         clear[0x1];
1044         u8         num_of_counters[0xf];
1045         u8         flow_counter_id[0x10];
1046
1047         u8         reserved_at_20[0x20];
1048 };
1049
1050 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1051         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1052         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1053         u8         reserved_at_0[0x40];
1054 };
1055
1056 struct mlx5_ifc_fte_match_param_bits {
1057         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1058
1059         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1060
1061         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1062
1063         u8         reserved_at_600[0xa00];
1064 };
1065
1066 enum {
1067         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1068         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1069         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1070         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1071         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1072 };
1073
1074 struct mlx5_ifc_rx_hash_field_select_bits {
1075         u8         l3_prot_type[0x1];
1076         u8         l4_prot_type[0x1];
1077         u8         selected_fields[0x1e];
1078 };
1079
1080 enum {
1081         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1082         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1083 };
1084
1085 enum {
1086         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1087         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1088 };
1089
1090 struct mlx5_ifc_wq_bits {
1091         u8         wq_type[0x4];
1092         u8         wq_signature[0x1];
1093         u8         end_padding_mode[0x2];
1094         u8         cd_slave[0x1];
1095         u8         reserved_at_8[0x18];
1096
1097         u8         hds_skip_first_sge[0x1];
1098         u8         log2_hds_buf_size[0x3];
1099         u8         reserved_at_24[0x7];
1100         u8         page_offset[0x5];
1101         u8         lwm[0x10];
1102
1103         u8         reserved_at_40[0x8];
1104         u8         pd[0x18];
1105
1106         u8         reserved_at_60[0x8];
1107         u8         uar_page[0x18];
1108
1109         u8         dbr_addr[0x40];
1110
1111         u8         hw_counter[0x20];
1112
1113         u8         sw_counter[0x20];
1114
1115         u8         reserved_at_100[0xc];
1116         u8         log_wq_stride[0x4];
1117         u8         reserved_at_110[0x3];
1118         u8         log_wq_pg_sz[0x5];
1119         u8         reserved_at_118[0x3];
1120         u8         log_wq_sz[0x5];
1121
1122         u8         reserved_at_120[0x15];
1123         u8         log_wqe_num_of_strides[0x3];
1124         u8         two_byte_shift_en[0x1];
1125         u8         reserved_at_139[0x4];
1126         u8         log_wqe_stride_size[0x3];
1127
1128         u8         reserved_at_140[0x4c0];
1129
1130         struct mlx5_ifc_cmd_pas_bits pas[0];
1131 };
1132
1133 struct mlx5_ifc_rq_num_bits {
1134         u8         reserved_at_0[0x8];
1135         u8         rq_num[0x18];
1136 };
1137
1138 struct mlx5_ifc_mac_address_layout_bits {
1139         u8         reserved_at_0[0x10];
1140         u8         mac_addr_47_32[0x10];
1141
1142         u8         mac_addr_31_0[0x20];
1143 };
1144
1145 struct mlx5_ifc_vlan_layout_bits {
1146         u8         reserved_at_0[0x14];
1147         u8         vlan[0x0c];
1148
1149         u8         reserved_at_20[0x20];
1150 };
1151
1152 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1153         u8         reserved_at_0[0xa0];
1154
1155         u8         min_time_between_cnps[0x20];
1156
1157         u8         reserved_at_c0[0x12];
1158         u8         cnp_dscp[0x6];
1159         u8         reserved_at_d8[0x5];
1160         u8         cnp_802p_prio[0x3];
1161
1162         u8         reserved_at_e0[0x720];
1163 };
1164
1165 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1166         u8         reserved_at_0[0x60];
1167
1168         u8         reserved_at_60[0x4];
1169         u8         clamp_tgt_rate[0x1];
1170         u8         reserved_at_65[0x3];
1171         u8         clamp_tgt_rate_after_time_inc[0x1];
1172         u8         reserved_at_69[0x17];
1173
1174         u8         reserved_at_80[0x20];
1175
1176         u8         rpg_time_reset[0x20];
1177
1178         u8         rpg_byte_reset[0x20];
1179
1180         u8         rpg_threshold[0x20];
1181
1182         u8         rpg_max_rate[0x20];
1183
1184         u8         rpg_ai_rate[0x20];
1185
1186         u8         rpg_hai_rate[0x20];
1187
1188         u8         rpg_gd[0x20];
1189
1190         u8         rpg_min_dec_fac[0x20];
1191
1192         u8         rpg_min_rate[0x20];
1193
1194         u8         reserved_at_1c0[0xe0];
1195
1196         u8         rate_to_set_on_first_cnp[0x20];
1197
1198         u8         dce_tcp_g[0x20];
1199
1200         u8         dce_tcp_rtt[0x20];
1201
1202         u8         rate_reduce_monitor_period[0x20];
1203
1204         u8         reserved_at_320[0x20];
1205
1206         u8         initial_alpha_value[0x20];
1207
1208         u8         reserved_at_360[0x4a0];
1209 };
1210
1211 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1212         u8         reserved_at_0[0x80];
1213
1214         u8         rppp_max_rps[0x20];
1215
1216         u8         rpg_time_reset[0x20];
1217
1218         u8         rpg_byte_reset[0x20];
1219
1220         u8         rpg_threshold[0x20];
1221
1222         u8         rpg_max_rate[0x20];
1223
1224         u8         rpg_ai_rate[0x20];
1225
1226         u8         rpg_hai_rate[0x20];
1227
1228         u8         rpg_gd[0x20];
1229
1230         u8         rpg_min_dec_fac[0x20];
1231
1232         u8         rpg_min_rate[0x20];
1233
1234         u8         reserved_at_1c0[0x640];
1235 };
1236
1237 enum {
1238         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1239         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1240         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1241 };
1242
1243 struct mlx5_ifc_resize_field_select_bits {
1244         u8         resize_field_select[0x20];
1245 };
1246
1247 enum {
1248         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1249         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1250         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1251         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1252 };
1253
1254 struct mlx5_ifc_modify_field_select_bits {
1255         u8         modify_field_select[0x20];
1256 };
1257
1258 struct mlx5_ifc_field_select_r_roce_np_bits {
1259         u8         field_select_r_roce_np[0x20];
1260 };
1261
1262 struct mlx5_ifc_field_select_r_roce_rp_bits {
1263         u8         field_select_r_roce_rp[0x20];
1264 };
1265
1266 enum {
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1268         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1269         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1270         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1272         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1273         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1274         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1275         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1276         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1277 };
1278
1279 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1280         u8         field_select_8021qaurp[0x20];
1281 };
1282
1283 struct mlx5_ifc_phys_layer_cntrs_bits {
1284         u8         time_since_last_clear_high[0x20];
1285
1286         u8         time_since_last_clear_low[0x20];
1287
1288         u8         symbol_errors_high[0x20];
1289
1290         u8         symbol_errors_low[0x20];
1291
1292         u8         sync_headers_errors_high[0x20];
1293
1294         u8         sync_headers_errors_low[0x20];
1295
1296         u8         edpl_bip_errors_lane0_high[0x20];
1297
1298         u8         edpl_bip_errors_lane0_low[0x20];
1299
1300         u8         edpl_bip_errors_lane1_high[0x20];
1301
1302         u8         edpl_bip_errors_lane1_low[0x20];
1303
1304         u8         edpl_bip_errors_lane2_high[0x20];
1305
1306         u8         edpl_bip_errors_lane2_low[0x20];
1307
1308         u8         edpl_bip_errors_lane3_high[0x20];
1309
1310         u8         edpl_bip_errors_lane3_low[0x20];
1311
1312         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1313
1314         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1315
1316         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1317
1318         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1319
1320         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1321
1322         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1323
1324         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1325
1326         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1327
1328         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1329
1330         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1331
1332         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1333
1334         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1335
1336         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1337
1338         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1339
1340         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1341
1342         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1343
1344         u8         rs_fec_corrected_blocks_high[0x20];
1345
1346         u8         rs_fec_corrected_blocks_low[0x20];
1347
1348         u8         rs_fec_uncorrectable_blocks_high[0x20];
1349
1350         u8         rs_fec_uncorrectable_blocks_low[0x20];
1351
1352         u8         rs_fec_no_errors_blocks_high[0x20];
1353
1354         u8         rs_fec_no_errors_blocks_low[0x20];
1355
1356         u8         rs_fec_single_error_blocks_high[0x20];
1357
1358         u8         rs_fec_single_error_blocks_low[0x20];
1359
1360         u8         rs_fec_corrected_symbols_total_high[0x20];
1361
1362         u8         rs_fec_corrected_symbols_total_low[0x20];
1363
1364         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1365
1366         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1367
1368         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1369
1370         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1371
1372         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1373
1374         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1375
1376         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1377
1378         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1379
1380         u8         link_down_events[0x20];
1381
1382         u8         successful_recovery_events[0x20];
1383
1384         u8         reserved_at_640[0x180];
1385 };
1386
1387 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1388         u8         time_since_last_clear_high[0x20];
1389
1390         u8         time_since_last_clear_low[0x20];
1391
1392         u8         phy_received_bits_high[0x20];
1393
1394         u8         phy_received_bits_low[0x20];
1395
1396         u8         phy_symbol_errors_high[0x20];
1397
1398         u8         phy_symbol_errors_low[0x20];
1399
1400         u8         phy_corrected_bits_high[0x20];
1401
1402         u8         phy_corrected_bits_low[0x20];
1403
1404         u8         phy_corrected_bits_lane0_high[0x20];
1405
1406         u8         phy_corrected_bits_lane0_low[0x20];
1407
1408         u8         phy_corrected_bits_lane1_high[0x20];
1409
1410         u8         phy_corrected_bits_lane1_low[0x20];
1411
1412         u8         phy_corrected_bits_lane2_high[0x20];
1413
1414         u8         phy_corrected_bits_lane2_low[0x20];
1415
1416         u8         phy_corrected_bits_lane3_high[0x20];
1417
1418         u8         phy_corrected_bits_lane3_low[0x20];
1419
1420         u8         reserved_at_200[0x5c0];
1421 };
1422
1423 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1424         u8         symbol_error_counter[0x10];
1425
1426         u8         link_error_recovery_counter[0x8];
1427
1428         u8         link_downed_counter[0x8];
1429
1430         u8         port_rcv_errors[0x10];
1431
1432         u8         port_rcv_remote_physical_errors[0x10];
1433
1434         u8         port_rcv_switch_relay_errors[0x10];
1435
1436         u8         port_xmit_discards[0x10];
1437
1438         u8         port_xmit_constraint_errors[0x8];
1439
1440         u8         port_rcv_constraint_errors[0x8];
1441
1442         u8         reserved_at_70[0x8];
1443
1444         u8         link_overrun_errors[0x8];
1445
1446         u8         reserved_at_80[0x10];
1447
1448         u8         vl_15_dropped[0x10];
1449
1450         u8         reserved_at_a0[0xa0];
1451 };
1452
1453 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1454         u8         transmit_queue_high[0x20];
1455
1456         u8         transmit_queue_low[0x20];
1457
1458         u8         reserved_at_40[0x780];
1459 };
1460
1461 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1462         u8         rx_octets_high[0x20];
1463
1464         u8         rx_octets_low[0x20];
1465
1466         u8         reserved_at_40[0xc0];
1467
1468         u8         rx_frames_high[0x20];
1469
1470         u8         rx_frames_low[0x20];
1471
1472         u8         tx_octets_high[0x20];
1473
1474         u8         tx_octets_low[0x20];
1475
1476         u8         reserved_at_180[0xc0];
1477
1478         u8         tx_frames_high[0x20];
1479
1480         u8         tx_frames_low[0x20];
1481
1482         u8         rx_pause_high[0x20];
1483
1484         u8         rx_pause_low[0x20];
1485
1486         u8         rx_pause_duration_high[0x20];
1487
1488         u8         rx_pause_duration_low[0x20];
1489
1490         u8         tx_pause_high[0x20];
1491
1492         u8         tx_pause_low[0x20];
1493
1494         u8         tx_pause_duration_high[0x20];
1495
1496         u8         tx_pause_duration_low[0x20];
1497
1498         u8         rx_pause_transition_high[0x20];
1499
1500         u8         rx_pause_transition_low[0x20];
1501
1502         u8         reserved_at_3c0[0x400];
1503 };
1504
1505 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1506         u8         port_transmit_wait_high[0x20];
1507
1508         u8         port_transmit_wait_low[0x20];
1509
1510         u8         reserved_at_40[0x780];
1511 };
1512
1513 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1514         u8         dot3stats_alignment_errors_high[0x20];
1515
1516         u8         dot3stats_alignment_errors_low[0x20];
1517
1518         u8         dot3stats_fcs_errors_high[0x20];
1519
1520         u8         dot3stats_fcs_errors_low[0x20];
1521
1522         u8         dot3stats_single_collision_frames_high[0x20];
1523
1524         u8         dot3stats_single_collision_frames_low[0x20];
1525
1526         u8         dot3stats_multiple_collision_frames_high[0x20];
1527
1528         u8         dot3stats_multiple_collision_frames_low[0x20];
1529
1530         u8         dot3stats_sqe_test_errors_high[0x20];
1531
1532         u8         dot3stats_sqe_test_errors_low[0x20];
1533
1534         u8         dot3stats_deferred_transmissions_high[0x20];
1535
1536         u8         dot3stats_deferred_transmissions_low[0x20];
1537
1538         u8         dot3stats_late_collisions_high[0x20];
1539
1540         u8         dot3stats_late_collisions_low[0x20];
1541
1542         u8         dot3stats_excessive_collisions_high[0x20];
1543
1544         u8         dot3stats_excessive_collisions_low[0x20];
1545
1546         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1547
1548         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1549
1550         u8         dot3stats_carrier_sense_errors_high[0x20];
1551
1552         u8         dot3stats_carrier_sense_errors_low[0x20];
1553
1554         u8         dot3stats_frame_too_longs_high[0x20];
1555
1556         u8         dot3stats_frame_too_longs_low[0x20];
1557
1558         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1559
1560         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1561
1562         u8         dot3stats_symbol_errors_high[0x20];
1563
1564         u8         dot3stats_symbol_errors_low[0x20];
1565
1566         u8         dot3control_in_unknown_opcodes_high[0x20];
1567
1568         u8         dot3control_in_unknown_opcodes_low[0x20];
1569
1570         u8         dot3in_pause_frames_high[0x20];
1571
1572         u8         dot3in_pause_frames_low[0x20];
1573
1574         u8         dot3out_pause_frames_high[0x20];
1575
1576         u8         dot3out_pause_frames_low[0x20];
1577
1578         u8         reserved_at_400[0x3c0];
1579 };
1580
1581 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1582         u8         ether_stats_drop_events_high[0x20];
1583
1584         u8         ether_stats_drop_events_low[0x20];
1585
1586         u8         ether_stats_octets_high[0x20];
1587
1588         u8         ether_stats_octets_low[0x20];
1589
1590         u8         ether_stats_pkts_high[0x20];
1591
1592         u8         ether_stats_pkts_low[0x20];
1593
1594         u8         ether_stats_broadcast_pkts_high[0x20];
1595
1596         u8         ether_stats_broadcast_pkts_low[0x20];
1597
1598         u8         ether_stats_multicast_pkts_high[0x20];
1599
1600         u8         ether_stats_multicast_pkts_low[0x20];
1601
1602         u8         ether_stats_crc_align_errors_high[0x20];
1603
1604         u8         ether_stats_crc_align_errors_low[0x20];
1605
1606         u8         ether_stats_undersize_pkts_high[0x20];
1607
1608         u8         ether_stats_undersize_pkts_low[0x20];
1609
1610         u8         ether_stats_oversize_pkts_high[0x20];
1611
1612         u8         ether_stats_oversize_pkts_low[0x20];
1613
1614         u8         ether_stats_fragments_high[0x20];
1615
1616         u8         ether_stats_fragments_low[0x20];
1617
1618         u8         ether_stats_jabbers_high[0x20];
1619
1620         u8         ether_stats_jabbers_low[0x20];
1621
1622         u8         ether_stats_collisions_high[0x20];
1623
1624         u8         ether_stats_collisions_low[0x20];
1625
1626         u8         ether_stats_pkts64octets_high[0x20];
1627
1628         u8         ether_stats_pkts64octets_low[0x20];
1629
1630         u8         ether_stats_pkts65to127octets_high[0x20];
1631
1632         u8         ether_stats_pkts65to127octets_low[0x20];
1633
1634         u8         ether_stats_pkts128to255octets_high[0x20];
1635
1636         u8         ether_stats_pkts128to255octets_low[0x20];
1637
1638         u8         ether_stats_pkts256to511octets_high[0x20];
1639
1640         u8         ether_stats_pkts256to511octets_low[0x20];
1641
1642         u8         ether_stats_pkts512to1023octets_high[0x20];
1643
1644         u8         ether_stats_pkts512to1023octets_low[0x20];
1645
1646         u8         ether_stats_pkts1024to1518octets_high[0x20];
1647
1648         u8         ether_stats_pkts1024to1518octets_low[0x20];
1649
1650         u8         ether_stats_pkts1519to2047octets_high[0x20];
1651
1652         u8         ether_stats_pkts1519to2047octets_low[0x20];
1653
1654         u8         ether_stats_pkts2048to4095octets_high[0x20];
1655
1656         u8         ether_stats_pkts2048to4095octets_low[0x20];
1657
1658         u8         ether_stats_pkts4096to8191octets_high[0x20];
1659
1660         u8         ether_stats_pkts4096to8191octets_low[0x20];
1661
1662         u8         ether_stats_pkts8192to10239octets_high[0x20];
1663
1664         u8         ether_stats_pkts8192to10239octets_low[0x20];
1665
1666         u8         reserved_at_540[0x280];
1667 };
1668
1669 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1670         u8         if_in_octets_high[0x20];
1671
1672         u8         if_in_octets_low[0x20];
1673
1674         u8         if_in_ucast_pkts_high[0x20];
1675
1676         u8         if_in_ucast_pkts_low[0x20];
1677
1678         u8         if_in_discards_high[0x20];
1679
1680         u8         if_in_discards_low[0x20];
1681
1682         u8         if_in_errors_high[0x20];
1683
1684         u8         if_in_errors_low[0x20];
1685
1686         u8         if_in_unknown_protos_high[0x20];
1687
1688         u8         if_in_unknown_protos_low[0x20];
1689
1690         u8         if_out_octets_high[0x20];
1691
1692         u8         if_out_octets_low[0x20];
1693
1694         u8         if_out_ucast_pkts_high[0x20];
1695
1696         u8         if_out_ucast_pkts_low[0x20];
1697
1698         u8         if_out_discards_high[0x20];
1699
1700         u8         if_out_discards_low[0x20];
1701
1702         u8         if_out_errors_high[0x20];
1703
1704         u8         if_out_errors_low[0x20];
1705
1706         u8         if_in_multicast_pkts_high[0x20];
1707
1708         u8         if_in_multicast_pkts_low[0x20];
1709
1710         u8         if_in_broadcast_pkts_high[0x20];
1711
1712         u8         if_in_broadcast_pkts_low[0x20];
1713
1714         u8         if_out_multicast_pkts_high[0x20];
1715
1716         u8         if_out_multicast_pkts_low[0x20];
1717
1718         u8         if_out_broadcast_pkts_high[0x20];
1719
1720         u8         if_out_broadcast_pkts_low[0x20];
1721
1722         u8         reserved_at_340[0x480];
1723 };
1724
1725 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1726         u8         a_frames_transmitted_ok_high[0x20];
1727
1728         u8         a_frames_transmitted_ok_low[0x20];
1729
1730         u8         a_frames_received_ok_high[0x20];
1731
1732         u8         a_frames_received_ok_low[0x20];
1733
1734         u8         a_frame_check_sequence_errors_high[0x20];
1735
1736         u8         a_frame_check_sequence_errors_low[0x20];
1737
1738         u8         a_alignment_errors_high[0x20];
1739
1740         u8         a_alignment_errors_low[0x20];
1741
1742         u8         a_octets_transmitted_ok_high[0x20];
1743
1744         u8         a_octets_transmitted_ok_low[0x20];
1745
1746         u8         a_octets_received_ok_high[0x20];
1747
1748         u8         a_octets_received_ok_low[0x20];
1749
1750         u8         a_multicast_frames_xmitted_ok_high[0x20];
1751
1752         u8         a_multicast_frames_xmitted_ok_low[0x20];
1753
1754         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1755
1756         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1757
1758         u8         a_multicast_frames_received_ok_high[0x20];
1759
1760         u8         a_multicast_frames_received_ok_low[0x20];
1761
1762         u8         a_broadcast_frames_received_ok_high[0x20];
1763
1764         u8         a_broadcast_frames_received_ok_low[0x20];
1765
1766         u8         a_in_range_length_errors_high[0x20];
1767
1768         u8         a_in_range_length_errors_low[0x20];
1769
1770         u8         a_out_of_range_length_field_high[0x20];
1771
1772         u8         a_out_of_range_length_field_low[0x20];
1773
1774         u8         a_frame_too_long_errors_high[0x20];
1775
1776         u8         a_frame_too_long_errors_low[0x20];
1777
1778         u8         a_symbol_error_during_carrier_high[0x20];
1779
1780         u8         a_symbol_error_during_carrier_low[0x20];
1781
1782         u8         a_mac_control_frames_transmitted_high[0x20];
1783
1784         u8         a_mac_control_frames_transmitted_low[0x20];
1785
1786         u8         a_mac_control_frames_received_high[0x20];
1787
1788         u8         a_mac_control_frames_received_low[0x20];
1789
1790         u8         a_unsupported_opcodes_received_high[0x20];
1791
1792         u8         a_unsupported_opcodes_received_low[0x20];
1793
1794         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1795
1796         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1797
1798         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1799
1800         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1801
1802         u8         reserved_at_4c0[0x300];
1803 };
1804
1805 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1806         u8         life_time_counter_high[0x20];
1807
1808         u8         life_time_counter_low[0x20];
1809
1810         u8         rx_errors[0x20];
1811
1812         u8         tx_errors[0x20];
1813
1814         u8         l0_to_recovery_eieos[0x20];
1815
1816         u8         l0_to_recovery_ts[0x20];
1817
1818         u8         l0_to_recovery_framing[0x20];
1819
1820         u8         l0_to_recovery_retrain[0x20];
1821
1822         u8         crc_error_dllp[0x20];
1823
1824         u8         crc_error_tlp[0x20];
1825
1826         u8         reserved_at_140[0x680];
1827 };
1828
1829 struct mlx5_ifc_cmd_inter_comp_event_bits {
1830         u8         command_completion_vector[0x20];
1831
1832         u8         reserved_at_20[0xc0];
1833 };
1834
1835 struct mlx5_ifc_stall_vl_event_bits {
1836         u8         reserved_at_0[0x18];
1837         u8         port_num[0x1];
1838         u8         reserved_at_19[0x3];
1839         u8         vl[0x4];
1840
1841         u8         reserved_at_20[0xa0];
1842 };
1843
1844 struct mlx5_ifc_db_bf_congestion_event_bits {
1845         u8         event_subtype[0x8];
1846         u8         reserved_at_8[0x8];
1847         u8         congestion_level[0x8];
1848         u8         reserved_at_18[0x8];
1849
1850         u8         reserved_at_20[0xa0];
1851 };
1852
1853 struct mlx5_ifc_gpio_event_bits {
1854         u8         reserved_at_0[0x60];
1855
1856         u8         gpio_event_hi[0x20];
1857
1858         u8         gpio_event_lo[0x20];
1859
1860         u8         reserved_at_a0[0x40];
1861 };
1862
1863 struct mlx5_ifc_port_state_change_event_bits {
1864         u8         reserved_at_0[0x40];
1865
1866         u8         port_num[0x4];
1867         u8         reserved_at_44[0x1c];
1868
1869         u8         reserved_at_60[0x80];
1870 };
1871
1872 struct mlx5_ifc_dropped_packet_logged_bits {
1873         u8         reserved_at_0[0xe0];
1874 };
1875
1876 enum {
1877         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1878         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1879 };
1880
1881 struct mlx5_ifc_cq_error_bits {
1882         u8         reserved_at_0[0x8];
1883         u8         cqn[0x18];
1884
1885         u8         reserved_at_20[0x20];
1886
1887         u8         reserved_at_40[0x18];
1888         u8         syndrome[0x8];
1889
1890         u8         reserved_at_60[0x80];
1891 };
1892
1893 struct mlx5_ifc_rdma_page_fault_event_bits {
1894         u8         bytes_committed[0x20];
1895
1896         u8         r_key[0x20];
1897
1898         u8         reserved_at_40[0x10];
1899         u8         packet_len[0x10];
1900
1901         u8         rdma_op_len[0x20];
1902
1903         u8         rdma_va[0x40];
1904
1905         u8         reserved_at_c0[0x5];
1906         u8         rdma[0x1];
1907         u8         write[0x1];
1908         u8         requestor[0x1];
1909         u8         qp_number[0x18];
1910 };
1911
1912 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1913         u8         bytes_committed[0x20];
1914
1915         u8         reserved_at_20[0x10];
1916         u8         wqe_index[0x10];
1917
1918         u8         reserved_at_40[0x10];
1919         u8         len[0x10];
1920
1921         u8         reserved_at_60[0x60];
1922
1923         u8         reserved_at_c0[0x5];
1924         u8         rdma[0x1];
1925         u8         write_read[0x1];
1926         u8         requestor[0x1];
1927         u8         qpn[0x18];
1928 };
1929
1930 struct mlx5_ifc_qp_events_bits {
1931         u8         reserved_at_0[0xa0];
1932
1933         u8         type[0x8];
1934         u8         reserved_at_a8[0x18];
1935
1936         u8         reserved_at_c0[0x8];
1937         u8         qpn_rqn_sqn[0x18];
1938 };
1939
1940 struct mlx5_ifc_dct_events_bits {
1941         u8         reserved_at_0[0xc0];
1942
1943         u8         reserved_at_c0[0x8];
1944         u8         dct_number[0x18];
1945 };
1946
1947 struct mlx5_ifc_comp_event_bits {
1948         u8         reserved_at_0[0xc0];
1949
1950         u8         reserved_at_c0[0x8];
1951         u8         cq_number[0x18];
1952 };
1953
1954 enum {
1955         MLX5_QPC_STATE_RST        = 0x0,
1956         MLX5_QPC_STATE_INIT       = 0x1,
1957         MLX5_QPC_STATE_RTR        = 0x2,
1958         MLX5_QPC_STATE_RTS        = 0x3,
1959         MLX5_QPC_STATE_SQER       = 0x4,
1960         MLX5_QPC_STATE_ERR        = 0x6,
1961         MLX5_QPC_STATE_SQD        = 0x7,
1962         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1963 };
1964
1965 enum {
1966         MLX5_QPC_ST_RC            = 0x0,
1967         MLX5_QPC_ST_UC            = 0x1,
1968         MLX5_QPC_ST_UD            = 0x2,
1969         MLX5_QPC_ST_XRC           = 0x3,
1970         MLX5_QPC_ST_DCI           = 0x5,
1971         MLX5_QPC_ST_QP0           = 0x7,
1972         MLX5_QPC_ST_QP1           = 0x8,
1973         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1974         MLX5_QPC_ST_REG_UMR       = 0xc,
1975 };
1976
1977 enum {
1978         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1979         MLX5_QPC_PM_STATE_REARM     = 0x1,
1980         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1981         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1982 };
1983
1984 enum {
1985         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1986         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1987 };
1988
1989 enum {
1990         MLX5_QPC_MTU_256_BYTES        = 0x1,
1991         MLX5_QPC_MTU_512_BYTES        = 0x2,
1992         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1993         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1994         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1995         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1996 };
1997
1998 enum {
1999         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2000         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2001         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2002         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2003         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2004         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2005         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2006         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2007 };
2008
2009 enum {
2010         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2011         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2012         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2013 };
2014
2015 enum {
2016         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2017         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2018         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2019 };
2020
2021 struct mlx5_ifc_qpc_bits {
2022         u8         state[0x4];
2023         u8         lag_tx_port_affinity[0x4];
2024         u8         st[0x8];
2025         u8         reserved_at_10[0x3];
2026         u8         pm_state[0x2];
2027         u8         reserved_at_15[0x7];
2028         u8         end_padding_mode[0x2];
2029         u8         reserved_at_1e[0x2];
2030
2031         u8         wq_signature[0x1];
2032         u8         block_lb_mc[0x1];
2033         u8         atomic_like_write_en[0x1];
2034         u8         latency_sensitive[0x1];
2035         u8         reserved_at_24[0x1];
2036         u8         drain_sigerr[0x1];
2037         u8         reserved_at_26[0x2];
2038         u8         pd[0x18];
2039
2040         u8         mtu[0x3];
2041         u8         log_msg_max[0x5];
2042         u8         reserved_at_48[0x1];
2043         u8         log_rq_size[0x4];
2044         u8         log_rq_stride[0x3];
2045         u8         no_sq[0x1];
2046         u8         log_sq_size[0x4];
2047         u8         reserved_at_55[0x6];
2048         u8         rlky[0x1];
2049         u8         ulp_stateless_offload_mode[0x4];
2050
2051         u8         counter_set_id[0x8];
2052         u8         uar_page[0x18];
2053
2054         u8         reserved_at_80[0x8];
2055         u8         user_index[0x18];
2056
2057         u8         reserved_at_a0[0x3];
2058         u8         log_page_size[0x5];
2059         u8         remote_qpn[0x18];
2060
2061         struct mlx5_ifc_ads_bits primary_address_path;
2062
2063         struct mlx5_ifc_ads_bits secondary_address_path;
2064
2065         u8         log_ack_req_freq[0x4];
2066         u8         reserved_at_384[0x4];
2067         u8         log_sra_max[0x3];
2068         u8         reserved_at_38b[0x2];
2069         u8         retry_count[0x3];
2070         u8         rnr_retry[0x3];
2071         u8         reserved_at_393[0x1];
2072         u8         fre[0x1];
2073         u8         cur_rnr_retry[0x3];
2074         u8         cur_retry_count[0x3];
2075         u8         reserved_at_39b[0x5];
2076
2077         u8         reserved_at_3a0[0x20];
2078
2079         u8         reserved_at_3c0[0x8];
2080         u8         next_send_psn[0x18];
2081
2082         u8         reserved_at_3e0[0x8];
2083         u8         cqn_snd[0x18];
2084
2085         u8         reserved_at_400[0x8];
2086         u8         deth_sqpn[0x18];
2087
2088         u8         reserved_at_420[0x20];
2089
2090         u8         reserved_at_440[0x8];
2091         u8         last_acked_psn[0x18];
2092
2093         u8         reserved_at_460[0x8];
2094         u8         ssn[0x18];
2095
2096         u8         reserved_at_480[0x8];
2097         u8         log_rra_max[0x3];
2098         u8         reserved_at_48b[0x1];
2099         u8         atomic_mode[0x4];
2100         u8         rre[0x1];
2101         u8         rwe[0x1];
2102         u8         rae[0x1];
2103         u8         reserved_at_493[0x1];
2104         u8         page_offset[0x6];
2105         u8         reserved_at_49a[0x3];
2106         u8         cd_slave_receive[0x1];
2107         u8         cd_slave_send[0x1];
2108         u8         cd_master[0x1];
2109
2110         u8         reserved_at_4a0[0x3];
2111         u8         min_rnr_nak[0x5];
2112         u8         next_rcv_psn[0x18];
2113
2114         u8         reserved_at_4c0[0x8];
2115         u8         xrcd[0x18];
2116
2117         u8         reserved_at_4e0[0x8];
2118         u8         cqn_rcv[0x18];
2119
2120         u8         dbr_addr[0x40];
2121
2122         u8         q_key[0x20];
2123
2124         u8         reserved_at_560[0x5];
2125         u8         rq_type[0x3];
2126         u8         srqn_rmpn_xrqn[0x18];
2127
2128         u8         reserved_at_580[0x8];
2129         u8         rmsn[0x18];
2130
2131         u8         hw_sq_wqebb_counter[0x10];
2132         u8         sw_sq_wqebb_counter[0x10];
2133
2134         u8         hw_rq_counter[0x20];
2135
2136         u8         sw_rq_counter[0x20];
2137
2138         u8         reserved_at_600[0x20];
2139
2140         u8         reserved_at_620[0xf];
2141         u8         cgs[0x1];
2142         u8         cs_req[0x8];
2143         u8         cs_res[0x8];
2144
2145         u8         dc_access_key[0x40];
2146
2147         u8         reserved_at_680[0xc0];
2148 };
2149
2150 struct mlx5_ifc_roce_addr_layout_bits {
2151         u8         source_l3_address[16][0x8];
2152
2153         u8         reserved_at_80[0x3];
2154         u8         vlan_valid[0x1];
2155         u8         vlan_id[0xc];
2156         u8         source_mac_47_32[0x10];
2157
2158         u8         source_mac_31_0[0x20];
2159
2160         u8         reserved_at_c0[0x14];
2161         u8         roce_l3_type[0x4];
2162         u8         roce_version[0x8];
2163
2164         u8         reserved_at_e0[0x20];
2165 };
2166
2167 union mlx5_ifc_hca_cap_union_bits {
2168         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2169         struct mlx5_ifc_odp_cap_bits odp_cap;
2170         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2171         struct mlx5_ifc_roce_cap_bits roce_cap;
2172         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2173         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2174         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2175         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2176         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2177         struct mlx5_ifc_qos_cap_bits qos_cap;
2178         u8         reserved_at_0[0x8000];
2179 };
2180
2181 enum {
2182         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2183         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2184         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2185         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2186         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2187         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2188 };
2189
2190 struct mlx5_ifc_flow_context_bits {
2191         u8         reserved_at_0[0x20];
2192
2193         u8         group_id[0x20];
2194
2195         u8         reserved_at_40[0x8];
2196         u8         flow_tag[0x18];
2197
2198         u8         reserved_at_60[0x10];
2199         u8         action[0x10];
2200
2201         u8         reserved_at_80[0x8];
2202         u8         destination_list_size[0x18];
2203
2204         u8         reserved_at_a0[0x8];
2205         u8         flow_counter_list_size[0x18];
2206
2207         u8         encap_id[0x20];
2208
2209         u8         reserved_at_e0[0x120];
2210
2211         struct mlx5_ifc_fte_match_param_bits match_value;
2212
2213         u8         reserved_at_1200[0x600];
2214
2215         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2216 };
2217
2218 enum {
2219         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2220         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2221 };
2222
2223 struct mlx5_ifc_xrc_srqc_bits {
2224         u8         state[0x4];
2225         u8         log_xrc_srq_size[0x4];
2226         u8         reserved_at_8[0x18];
2227
2228         u8         wq_signature[0x1];
2229         u8         cont_srq[0x1];
2230         u8         reserved_at_22[0x1];
2231         u8         rlky[0x1];
2232         u8         basic_cyclic_rcv_wqe[0x1];
2233         u8         log_rq_stride[0x3];
2234         u8         xrcd[0x18];
2235
2236         u8         page_offset[0x6];
2237         u8         reserved_at_46[0x2];
2238         u8         cqn[0x18];
2239
2240         u8         reserved_at_60[0x20];
2241
2242         u8         user_index_equal_xrc_srqn[0x1];
2243         u8         reserved_at_81[0x1];
2244         u8         log_page_size[0x6];
2245         u8         user_index[0x18];
2246
2247         u8         reserved_at_a0[0x20];
2248
2249         u8         reserved_at_c0[0x8];
2250         u8         pd[0x18];
2251
2252         u8         lwm[0x10];
2253         u8         wqe_cnt[0x10];
2254
2255         u8         reserved_at_100[0x40];
2256
2257         u8         db_record_addr_h[0x20];
2258
2259         u8         db_record_addr_l[0x1e];
2260         u8         reserved_at_17e[0x2];
2261
2262         u8         reserved_at_180[0x80];
2263 };
2264
2265 struct mlx5_ifc_traffic_counter_bits {
2266         u8         packets[0x40];
2267
2268         u8         octets[0x40];
2269 };
2270
2271 struct mlx5_ifc_tisc_bits {
2272         u8         strict_lag_tx_port_affinity[0x1];
2273         u8         reserved_at_1[0x3];
2274         u8         lag_tx_port_affinity[0x04];
2275
2276         u8         reserved_at_8[0x4];
2277         u8         prio[0x4];
2278         u8         reserved_at_10[0x10];
2279
2280         u8         reserved_at_20[0x100];
2281
2282         u8         reserved_at_120[0x8];
2283         u8         transport_domain[0x18];
2284
2285         u8         reserved_at_140[0x3c0];
2286 };
2287
2288 enum {
2289         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2290         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2291 };
2292
2293 enum {
2294         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2295         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2296 };
2297
2298 enum {
2299         MLX5_RX_HASH_FN_NONE           = 0x0,
2300         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2301         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2302 };
2303
2304 enum {
2305         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2306         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2307 };
2308
2309 struct mlx5_ifc_tirc_bits {
2310         u8         reserved_at_0[0x20];
2311
2312         u8         disp_type[0x4];
2313         u8         reserved_at_24[0x1c];
2314
2315         u8         reserved_at_40[0x40];
2316
2317         u8         reserved_at_80[0x4];
2318         u8         lro_timeout_period_usecs[0x10];
2319         u8         lro_enable_mask[0x4];
2320         u8         lro_max_ip_payload_size[0x8];
2321
2322         u8         reserved_at_a0[0x40];
2323
2324         u8         reserved_at_e0[0x8];
2325         u8         inline_rqn[0x18];
2326
2327         u8         rx_hash_symmetric[0x1];
2328         u8         reserved_at_101[0x1];
2329         u8         tunneled_offload_en[0x1];
2330         u8         reserved_at_103[0x5];
2331         u8         indirect_table[0x18];
2332
2333         u8         rx_hash_fn[0x4];
2334         u8         reserved_at_124[0x2];
2335         u8         self_lb_block[0x2];
2336         u8         transport_domain[0x18];
2337
2338         u8         rx_hash_toeplitz_key[10][0x20];
2339
2340         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2341
2342         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2343
2344         u8         reserved_at_2c0[0x4c0];
2345 };
2346
2347 enum {
2348         MLX5_SRQC_STATE_GOOD   = 0x0,
2349         MLX5_SRQC_STATE_ERROR  = 0x1,
2350 };
2351
2352 struct mlx5_ifc_srqc_bits {
2353         u8         state[0x4];
2354         u8         log_srq_size[0x4];
2355         u8         reserved_at_8[0x18];
2356
2357         u8         wq_signature[0x1];
2358         u8         cont_srq[0x1];
2359         u8         reserved_at_22[0x1];
2360         u8         rlky[0x1];
2361         u8         reserved_at_24[0x1];
2362         u8         log_rq_stride[0x3];
2363         u8         xrcd[0x18];
2364
2365         u8         page_offset[0x6];
2366         u8         reserved_at_46[0x2];
2367         u8         cqn[0x18];
2368
2369         u8         reserved_at_60[0x20];
2370
2371         u8         reserved_at_80[0x2];
2372         u8         log_page_size[0x6];
2373         u8         reserved_at_88[0x18];
2374
2375         u8         reserved_at_a0[0x20];
2376
2377         u8         reserved_at_c0[0x8];
2378         u8         pd[0x18];
2379
2380         u8         lwm[0x10];
2381         u8         wqe_cnt[0x10];
2382
2383         u8         reserved_at_100[0x40];
2384
2385         u8         dbr_addr[0x40];
2386
2387         u8         reserved_at_180[0x80];
2388 };
2389
2390 enum {
2391         MLX5_SQC_STATE_RST  = 0x0,
2392         MLX5_SQC_STATE_RDY  = 0x1,
2393         MLX5_SQC_STATE_ERR  = 0x3,
2394 };
2395
2396 struct mlx5_ifc_sqc_bits {
2397         u8         rlky[0x1];
2398         u8         cd_master[0x1];
2399         u8         fre[0x1];
2400         u8         flush_in_error_en[0x1];
2401         u8         reserved_at_4[0x1];
2402         u8         min_wqe_inline_mode[0x3];
2403         u8         state[0x4];
2404         u8         reg_umr[0x1];
2405         u8         reserved_at_d[0x13];
2406
2407         u8         reserved_at_20[0x8];
2408         u8         user_index[0x18];
2409
2410         u8         reserved_at_40[0x8];
2411         u8         cqn[0x18];
2412
2413         u8         reserved_at_60[0x90];
2414
2415         u8         packet_pacing_rate_limit_index[0x10];
2416         u8         tis_lst_sz[0x10];
2417         u8         reserved_at_110[0x10];
2418
2419         u8         reserved_at_120[0x40];
2420
2421         u8         reserved_at_160[0x8];
2422         u8         tis_num_0[0x18];
2423
2424         struct mlx5_ifc_wq_bits wq;
2425 };
2426
2427 enum {
2428         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2429         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2430         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2431         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2432 };
2433
2434 struct mlx5_ifc_scheduling_context_bits {
2435         u8         element_type[0x8];
2436         u8         reserved_at_8[0x18];
2437
2438         u8         element_attributes[0x20];
2439
2440         u8         parent_element_id[0x20];
2441
2442         u8         reserved_at_60[0x40];
2443
2444         u8         bw_share[0x20];
2445
2446         u8         max_average_bw[0x20];
2447
2448         u8         reserved_at_e0[0x120];
2449 };
2450
2451 struct mlx5_ifc_rqtc_bits {
2452         u8         reserved_at_0[0xa0];
2453
2454         u8         reserved_at_a0[0x10];
2455         u8         rqt_max_size[0x10];
2456
2457         u8         reserved_at_c0[0x10];
2458         u8         rqt_actual_size[0x10];
2459
2460         u8         reserved_at_e0[0x6a0];
2461
2462         struct mlx5_ifc_rq_num_bits rq_num[0];
2463 };
2464
2465 enum {
2466         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2467         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2468 };
2469
2470 enum {
2471         MLX5_RQC_STATE_RST  = 0x0,
2472         MLX5_RQC_STATE_RDY  = 0x1,
2473         MLX5_RQC_STATE_ERR  = 0x3,
2474 };
2475
2476 struct mlx5_ifc_rqc_bits {
2477         u8         rlky[0x1];
2478         u8         reserved_at_1[0x1];
2479         u8         scatter_fcs[0x1];
2480         u8         vsd[0x1];
2481         u8         mem_rq_type[0x4];
2482         u8         state[0x4];
2483         u8         reserved_at_c[0x1];
2484         u8         flush_in_error_en[0x1];
2485         u8         reserved_at_e[0x12];
2486
2487         u8         reserved_at_20[0x8];
2488         u8         user_index[0x18];
2489
2490         u8         reserved_at_40[0x8];
2491         u8         cqn[0x18];
2492
2493         u8         counter_set_id[0x8];
2494         u8         reserved_at_68[0x18];
2495
2496         u8         reserved_at_80[0x8];
2497         u8         rmpn[0x18];
2498
2499         u8         reserved_at_a0[0xe0];
2500
2501         struct mlx5_ifc_wq_bits wq;
2502 };
2503
2504 enum {
2505         MLX5_RMPC_STATE_RDY  = 0x1,
2506         MLX5_RMPC_STATE_ERR  = 0x3,
2507 };
2508
2509 struct mlx5_ifc_rmpc_bits {
2510         u8         reserved_at_0[0x8];
2511         u8         state[0x4];
2512         u8         reserved_at_c[0x14];
2513
2514         u8         basic_cyclic_rcv_wqe[0x1];
2515         u8         reserved_at_21[0x1f];
2516
2517         u8         reserved_at_40[0x140];
2518
2519         struct mlx5_ifc_wq_bits wq;
2520 };
2521
2522 struct mlx5_ifc_nic_vport_context_bits {
2523         u8         reserved_at_0[0x5];
2524         u8         min_wqe_inline_mode[0x3];
2525         u8         reserved_at_8[0x17];
2526         u8         roce_en[0x1];
2527
2528         u8         arm_change_event[0x1];
2529         u8         reserved_at_21[0x1a];
2530         u8         event_on_mtu[0x1];
2531         u8         event_on_promisc_change[0x1];
2532         u8         event_on_vlan_change[0x1];
2533         u8         event_on_mc_address_change[0x1];
2534         u8         event_on_uc_address_change[0x1];
2535
2536         u8         reserved_at_40[0xf0];
2537
2538         u8         mtu[0x10];
2539
2540         u8         system_image_guid[0x40];
2541         u8         port_guid[0x40];
2542         u8         node_guid[0x40];
2543
2544         u8         reserved_at_200[0x140];
2545         u8         qkey_violation_counter[0x10];
2546         u8         reserved_at_350[0x430];
2547
2548         u8         promisc_uc[0x1];
2549         u8         promisc_mc[0x1];
2550         u8         promisc_all[0x1];
2551         u8         reserved_at_783[0x2];
2552         u8         allowed_list_type[0x3];
2553         u8         reserved_at_788[0xc];
2554         u8         allowed_list_size[0xc];
2555
2556         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2557
2558         u8         reserved_at_7e0[0x20];
2559
2560         u8         current_uc_mac_address[0][0x40];
2561 };
2562
2563 enum {
2564         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2565         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2566         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2567         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2568 };
2569
2570 struct mlx5_ifc_mkc_bits {
2571         u8         reserved_at_0[0x1];
2572         u8         free[0x1];
2573         u8         reserved_at_2[0xd];
2574         u8         small_fence_on_rdma_read_response[0x1];
2575         u8         umr_en[0x1];
2576         u8         a[0x1];
2577         u8         rw[0x1];
2578         u8         rr[0x1];
2579         u8         lw[0x1];
2580         u8         lr[0x1];
2581         u8         access_mode[0x2];
2582         u8         reserved_at_18[0x8];
2583
2584         u8         qpn[0x18];
2585         u8         mkey_7_0[0x8];
2586
2587         u8         reserved_at_40[0x20];
2588
2589         u8         length64[0x1];
2590         u8         bsf_en[0x1];
2591         u8         sync_umr[0x1];
2592         u8         reserved_at_63[0x2];
2593         u8         expected_sigerr_count[0x1];
2594         u8         reserved_at_66[0x1];
2595         u8         en_rinval[0x1];
2596         u8         pd[0x18];
2597
2598         u8         start_addr[0x40];
2599
2600         u8         len[0x40];
2601
2602         u8         bsf_octword_size[0x20];
2603
2604         u8         reserved_at_120[0x80];
2605
2606         u8         translations_octword_size[0x20];
2607
2608         u8         reserved_at_1c0[0x1b];
2609         u8         log_page_size[0x5];
2610
2611         u8         reserved_at_1e0[0x20];
2612 };
2613
2614 struct mlx5_ifc_pkey_bits {
2615         u8         reserved_at_0[0x10];
2616         u8         pkey[0x10];
2617 };
2618
2619 struct mlx5_ifc_array128_auto_bits {
2620         u8         array128_auto[16][0x8];
2621 };
2622
2623 struct mlx5_ifc_hca_vport_context_bits {
2624         u8         field_select[0x20];
2625
2626         u8         reserved_at_20[0xe0];
2627
2628         u8         sm_virt_aware[0x1];
2629         u8         has_smi[0x1];
2630         u8         has_raw[0x1];
2631         u8         grh_required[0x1];
2632         u8         reserved_at_104[0xc];
2633         u8         port_physical_state[0x4];
2634         u8         vport_state_policy[0x4];
2635         u8         port_state[0x4];
2636         u8         vport_state[0x4];
2637
2638         u8         reserved_at_120[0x20];
2639
2640         u8         system_image_guid[0x40];
2641
2642         u8         port_guid[0x40];
2643
2644         u8         node_guid[0x40];
2645
2646         u8         cap_mask1[0x20];
2647
2648         u8         cap_mask1_field_select[0x20];
2649
2650         u8         cap_mask2[0x20];
2651
2652         u8         cap_mask2_field_select[0x20];
2653
2654         u8         reserved_at_280[0x80];
2655
2656         u8         lid[0x10];
2657         u8         reserved_at_310[0x4];
2658         u8         init_type_reply[0x4];
2659         u8         lmc[0x3];
2660         u8         subnet_timeout[0x5];
2661
2662         u8         sm_lid[0x10];
2663         u8         sm_sl[0x4];
2664         u8         reserved_at_334[0xc];
2665
2666         u8         qkey_violation_counter[0x10];
2667         u8         pkey_violation_counter[0x10];
2668
2669         u8         reserved_at_360[0xca0];
2670 };
2671
2672 struct mlx5_ifc_esw_vport_context_bits {
2673         u8         reserved_at_0[0x3];
2674         u8         vport_svlan_strip[0x1];
2675         u8         vport_cvlan_strip[0x1];
2676         u8         vport_svlan_insert[0x1];
2677         u8         vport_cvlan_insert[0x2];
2678         u8         reserved_at_8[0x18];
2679
2680         u8         reserved_at_20[0x20];
2681
2682         u8         svlan_cfi[0x1];
2683         u8         svlan_pcp[0x3];
2684         u8         svlan_id[0xc];
2685         u8         cvlan_cfi[0x1];
2686         u8         cvlan_pcp[0x3];
2687         u8         cvlan_id[0xc];
2688
2689         u8         reserved_at_60[0x7a0];
2690 };
2691
2692 enum {
2693         MLX5_EQC_STATUS_OK                = 0x0,
2694         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2695 };
2696
2697 enum {
2698         MLX5_EQC_ST_ARMED  = 0x9,
2699         MLX5_EQC_ST_FIRED  = 0xa,
2700 };
2701
2702 struct mlx5_ifc_eqc_bits {
2703         u8         status[0x4];
2704         u8         reserved_at_4[0x9];
2705         u8         ec[0x1];
2706         u8         oi[0x1];
2707         u8         reserved_at_f[0x5];
2708         u8         st[0x4];
2709         u8         reserved_at_18[0x8];
2710
2711         u8         reserved_at_20[0x20];
2712
2713         u8         reserved_at_40[0x14];
2714         u8         page_offset[0x6];
2715         u8         reserved_at_5a[0x6];
2716
2717         u8         reserved_at_60[0x3];
2718         u8         log_eq_size[0x5];
2719         u8         uar_page[0x18];
2720
2721         u8         reserved_at_80[0x20];
2722
2723         u8         reserved_at_a0[0x18];
2724         u8         intr[0x8];
2725
2726         u8         reserved_at_c0[0x3];
2727         u8         log_page_size[0x5];
2728         u8         reserved_at_c8[0x18];
2729
2730         u8         reserved_at_e0[0x60];
2731
2732         u8         reserved_at_140[0x8];
2733         u8         consumer_counter[0x18];
2734
2735         u8         reserved_at_160[0x8];
2736         u8         producer_counter[0x18];
2737
2738         u8         reserved_at_180[0x80];
2739 };
2740
2741 enum {
2742         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2743         MLX5_DCTC_STATE_DRAINING  = 0x1,
2744         MLX5_DCTC_STATE_DRAINED   = 0x2,
2745 };
2746
2747 enum {
2748         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2749         MLX5_DCTC_CS_RES_NA         = 0x1,
2750         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2751 };
2752
2753 enum {
2754         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2755         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2756         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2757         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2758         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2759 };
2760
2761 struct mlx5_ifc_dctc_bits {
2762         u8         reserved_at_0[0x4];
2763         u8         state[0x4];
2764         u8         reserved_at_8[0x18];
2765
2766         u8         reserved_at_20[0x8];
2767         u8         user_index[0x18];
2768
2769         u8         reserved_at_40[0x8];
2770         u8         cqn[0x18];
2771
2772         u8         counter_set_id[0x8];
2773         u8         atomic_mode[0x4];
2774         u8         rre[0x1];
2775         u8         rwe[0x1];
2776         u8         rae[0x1];
2777         u8         atomic_like_write_en[0x1];
2778         u8         latency_sensitive[0x1];
2779         u8         rlky[0x1];
2780         u8         free_ar[0x1];
2781         u8         reserved_at_73[0xd];
2782
2783         u8         reserved_at_80[0x8];
2784         u8         cs_res[0x8];
2785         u8         reserved_at_90[0x3];
2786         u8         min_rnr_nak[0x5];
2787         u8         reserved_at_98[0x8];
2788
2789         u8         reserved_at_a0[0x8];
2790         u8         srqn_xrqn[0x18];
2791
2792         u8         reserved_at_c0[0x8];
2793         u8         pd[0x18];
2794
2795         u8         tclass[0x8];
2796         u8         reserved_at_e8[0x4];
2797         u8         flow_label[0x14];
2798
2799         u8         dc_access_key[0x40];
2800
2801         u8         reserved_at_140[0x5];
2802         u8         mtu[0x3];
2803         u8         port[0x8];
2804         u8         pkey_index[0x10];
2805
2806         u8         reserved_at_160[0x8];
2807         u8         my_addr_index[0x8];
2808         u8         reserved_at_170[0x8];
2809         u8         hop_limit[0x8];
2810
2811         u8         dc_access_key_violation_count[0x20];
2812
2813         u8         reserved_at_1a0[0x14];
2814         u8         dei_cfi[0x1];
2815         u8         eth_prio[0x3];
2816         u8         ecn[0x2];
2817         u8         dscp[0x6];
2818
2819         u8         reserved_at_1c0[0x40];
2820 };
2821
2822 enum {
2823         MLX5_CQC_STATUS_OK             = 0x0,
2824         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2825         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2826 };
2827
2828 enum {
2829         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2830         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2831 };
2832
2833 enum {
2834         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2835         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2836         MLX5_CQC_ST_FIRED                                 = 0xa,
2837 };
2838
2839 enum {
2840         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2841         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2842         MLX5_CQ_PERIOD_NUM_MODES
2843 };
2844
2845 struct mlx5_ifc_cqc_bits {
2846         u8         status[0x4];
2847         u8         reserved_at_4[0x4];
2848         u8         cqe_sz[0x3];
2849         u8         cc[0x1];
2850         u8         reserved_at_c[0x1];
2851         u8         scqe_break_moderation_en[0x1];
2852         u8         oi[0x1];
2853         u8         cq_period_mode[0x2];
2854         u8         cqe_comp_en[0x1];
2855         u8         mini_cqe_res_format[0x2];
2856         u8         st[0x4];
2857         u8         reserved_at_18[0x8];
2858
2859         u8         reserved_at_20[0x20];
2860
2861         u8         reserved_at_40[0x14];
2862         u8         page_offset[0x6];
2863         u8         reserved_at_5a[0x6];
2864
2865         u8         reserved_at_60[0x3];
2866         u8         log_cq_size[0x5];
2867         u8         uar_page[0x18];
2868
2869         u8         reserved_at_80[0x4];
2870         u8         cq_period[0xc];
2871         u8         cq_max_count[0x10];
2872
2873         u8         reserved_at_a0[0x18];
2874         u8         c_eqn[0x8];
2875
2876         u8         reserved_at_c0[0x3];
2877         u8         log_page_size[0x5];
2878         u8         reserved_at_c8[0x18];
2879
2880         u8         reserved_at_e0[0x20];
2881
2882         u8         reserved_at_100[0x8];
2883         u8         last_notified_index[0x18];
2884
2885         u8         reserved_at_120[0x8];
2886         u8         last_solicit_index[0x18];
2887
2888         u8         reserved_at_140[0x8];
2889         u8         consumer_counter[0x18];
2890
2891         u8         reserved_at_160[0x8];
2892         u8         producer_counter[0x18];
2893
2894         u8         reserved_at_180[0x40];
2895
2896         u8         dbr_addr[0x40];
2897 };
2898
2899 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2900         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2901         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2902         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2903         u8         reserved_at_0[0x800];
2904 };
2905
2906 struct mlx5_ifc_query_adapter_param_block_bits {
2907         u8         reserved_at_0[0xc0];
2908
2909         u8         reserved_at_c0[0x8];
2910         u8         ieee_vendor_id[0x18];
2911
2912         u8         reserved_at_e0[0x10];
2913         u8         vsd_vendor_id[0x10];
2914
2915         u8         vsd[208][0x8];
2916
2917         u8         vsd_contd_psid[16][0x8];
2918 };
2919
2920 enum {
2921         MLX5_XRQC_STATE_GOOD   = 0x0,
2922         MLX5_XRQC_STATE_ERROR  = 0x1,
2923 };
2924
2925 enum {
2926         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2927         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2928 };
2929
2930 enum {
2931         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2932 };
2933
2934 struct mlx5_ifc_tag_matching_topology_context_bits {
2935         u8         log_matching_list_sz[0x4];
2936         u8         reserved_at_4[0xc];
2937         u8         append_next_index[0x10];
2938
2939         u8         sw_phase_cnt[0x10];
2940         u8         hw_phase_cnt[0x10];
2941
2942         u8         reserved_at_40[0x40];
2943 };
2944
2945 struct mlx5_ifc_xrqc_bits {
2946         u8         state[0x4];
2947         u8         rlkey[0x1];
2948         u8         reserved_at_5[0xf];
2949         u8         topology[0x4];
2950         u8         reserved_at_18[0x4];
2951         u8         offload[0x4];
2952
2953         u8         reserved_at_20[0x8];
2954         u8         user_index[0x18];
2955
2956         u8         reserved_at_40[0x8];
2957         u8         cqn[0x18];
2958
2959         u8         reserved_at_60[0xa0];
2960
2961         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2962
2963         u8         reserved_at_180[0x880];
2964
2965         struct mlx5_ifc_wq_bits wq;
2966 };
2967
2968 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2969         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2970         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2971         u8         reserved_at_0[0x20];
2972 };
2973
2974 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2975         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2976         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2977         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2978         u8         reserved_at_0[0x20];
2979 };
2980
2981 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2982         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2983         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2984         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2985         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2986         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2987         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2988         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2989         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2990         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2991         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
2992         u8         reserved_at_0[0x7c0];
2993 };
2994
2995 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2996         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
2997         u8         reserved_at_0[0x7c0];
2998 };
2999
3000 union mlx5_ifc_event_auto_bits {
3001         struct mlx5_ifc_comp_event_bits comp_event;
3002         struct mlx5_ifc_dct_events_bits dct_events;
3003         struct mlx5_ifc_qp_events_bits qp_events;
3004         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3005         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3006         struct mlx5_ifc_cq_error_bits cq_error;
3007         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3008         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3009         struct mlx5_ifc_gpio_event_bits gpio_event;
3010         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3011         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3012         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3013         u8         reserved_at_0[0xe0];
3014 };
3015
3016 struct mlx5_ifc_health_buffer_bits {
3017         u8         reserved_at_0[0x100];
3018
3019         u8         assert_existptr[0x20];
3020
3021         u8         assert_callra[0x20];
3022
3023         u8         reserved_at_140[0x40];
3024
3025         u8         fw_version[0x20];
3026
3027         u8         hw_id[0x20];
3028
3029         u8         reserved_at_1c0[0x20];
3030
3031         u8         irisc_index[0x8];
3032         u8         synd[0x8];
3033         u8         ext_synd[0x10];
3034 };
3035
3036 struct mlx5_ifc_register_loopback_control_bits {
3037         u8         no_lb[0x1];
3038         u8         reserved_at_1[0x7];
3039         u8         port[0x8];
3040         u8         reserved_at_10[0x10];
3041
3042         u8         reserved_at_20[0x60];
3043 };
3044
3045 struct mlx5_ifc_vport_tc_element_bits {
3046         u8         traffic_class[0x4];
3047         u8         reserved_at_4[0xc];
3048         u8         vport_number[0x10];
3049 };
3050
3051 struct mlx5_ifc_vport_element_bits {
3052         u8         reserved_at_0[0x10];
3053         u8         vport_number[0x10];
3054 };
3055
3056 enum {
3057         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3058         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3059         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3060 };
3061
3062 struct mlx5_ifc_tsar_element_bits {
3063         u8         reserved_at_0[0x8];
3064         u8         tsar_type[0x8];
3065         u8         reserved_at_10[0x10];
3066 };
3067
3068 struct mlx5_ifc_teardown_hca_out_bits {
3069         u8         status[0x8];
3070         u8         reserved_at_8[0x18];
3071
3072         u8         syndrome[0x20];
3073
3074         u8         reserved_at_40[0x40];
3075 };
3076
3077 enum {
3078         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3079         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3080 };
3081
3082 struct mlx5_ifc_teardown_hca_in_bits {
3083         u8         opcode[0x10];
3084         u8         reserved_at_10[0x10];
3085
3086         u8         reserved_at_20[0x10];
3087         u8         op_mod[0x10];
3088
3089         u8         reserved_at_40[0x10];
3090         u8         profile[0x10];
3091
3092         u8         reserved_at_60[0x20];
3093 };
3094
3095 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3096         u8         status[0x8];
3097         u8         reserved_at_8[0x18];
3098
3099         u8         syndrome[0x20];
3100
3101         u8         reserved_at_40[0x40];
3102 };
3103
3104 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3105         u8         opcode[0x10];
3106         u8         reserved_at_10[0x10];
3107
3108         u8         reserved_at_20[0x10];
3109         u8         op_mod[0x10];
3110
3111         u8         reserved_at_40[0x8];
3112         u8         qpn[0x18];
3113
3114         u8         reserved_at_60[0x20];
3115
3116         u8         opt_param_mask[0x20];
3117
3118         u8         reserved_at_a0[0x20];
3119
3120         struct mlx5_ifc_qpc_bits qpc;
3121
3122         u8         reserved_at_800[0x80];
3123 };
3124
3125 struct mlx5_ifc_sqd2rts_qp_out_bits {
3126         u8         status[0x8];
3127         u8         reserved_at_8[0x18];
3128
3129         u8         syndrome[0x20];
3130
3131         u8         reserved_at_40[0x40];
3132 };
3133
3134 struct mlx5_ifc_sqd2rts_qp_in_bits {
3135         u8         opcode[0x10];
3136         u8         reserved_at_10[0x10];
3137
3138         u8         reserved_at_20[0x10];
3139         u8         op_mod[0x10];
3140
3141         u8         reserved_at_40[0x8];
3142         u8         qpn[0x18];
3143
3144         u8         reserved_at_60[0x20];
3145
3146         u8         opt_param_mask[0x20];
3147
3148         u8         reserved_at_a0[0x20];
3149
3150         struct mlx5_ifc_qpc_bits qpc;
3151
3152         u8         reserved_at_800[0x80];
3153 };
3154
3155 struct mlx5_ifc_set_roce_address_out_bits {
3156         u8         status[0x8];
3157         u8         reserved_at_8[0x18];
3158
3159         u8         syndrome[0x20];
3160
3161         u8         reserved_at_40[0x40];
3162 };
3163
3164 struct mlx5_ifc_set_roce_address_in_bits {
3165         u8         opcode[0x10];
3166         u8         reserved_at_10[0x10];
3167
3168         u8         reserved_at_20[0x10];
3169         u8         op_mod[0x10];
3170
3171         u8         roce_address_index[0x10];
3172         u8         reserved_at_50[0x10];
3173
3174         u8         reserved_at_60[0x20];
3175
3176         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3177 };
3178
3179 struct mlx5_ifc_set_mad_demux_out_bits {
3180         u8         status[0x8];
3181         u8         reserved_at_8[0x18];
3182
3183         u8         syndrome[0x20];
3184
3185         u8         reserved_at_40[0x40];
3186 };
3187
3188 enum {
3189         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3190         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3191 };
3192
3193 struct mlx5_ifc_set_mad_demux_in_bits {
3194         u8         opcode[0x10];
3195         u8         reserved_at_10[0x10];
3196
3197         u8         reserved_at_20[0x10];
3198         u8         op_mod[0x10];
3199
3200         u8         reserved_at_40[0x20];
3201
3202         u8         reserved_at_60[0x6];
3203         u8         demux_mode[0x2];
3204         u8         reserved_at_68[0x18];
3205 };
3206
3207 struct mlx5_ifc_set_l2_table_entry_out_bits {
3208         u8         status[0x8];
3209         u8         reserved_at_8[0x18];
3210
3211         u8         syndrome[0x20];
3212
3213         u8         reserved_at_40[0x40];
3214 };
3215
3216 struct mlx5_ifc_set_l2_table_entry_in_bits {
3217         u8         opcode[0x10];
3218         u8         reserved_at_10[0x10];
3219
3220         u8         reserved_at_20[0x10];
3221         u8         op_mod[0x10];
3222
3223         u8         reserved_at_40[0x60];
3224
3225         u8         reserved_at_a0[0x8];
3226         u8         table_index[0x18];
3227
3228         u8         reserved_at_c0[0x20];
3229
3230         u8         reserved_at_e0[0x13];
3231         u8         vlan_valid[0x1];
3232         u8         vlan[0xc];
3233
3234         struct mlx5_ifc_mac_address_layout_bits mac_address;
3235
3236         u8         reserved_at_140[0xc0];
3237 };
3238
3239 struct mlx5_ifc_set_issi_out_bits {
3240         u8         status[0x8];
3241         u8         reserved_at_8[0x18];
3242
3243         u8         syndrome[0x20];
3244
3245         u8         reserved_at_40[0x40];
3246 };
3247
3248 struct mlx5_ifc_set_issi_in_bits {
3249         u8         opcode[0x10];
3250         u8         reserved_at_10[0x10];
3251
3252         u8         reserved_at_20[0x10];
3253         u8         op_mod[0x10];
3254
3255         u8         reserved_at_40[0x10];
3256         u8         current_issi[0x10];
3257
3258         u8         reserved_at_60[0x20];
3259 };
3260
3261 struct mlx5_ifc_set_hca_cap_out_bits {
3262         u8         status[0x8];
3263         u8         reserved_at_8[0x18];
3264
3265         u8         syndrome[0x20];
3266
3267         u8         reserved_at_40[0x40];
3268 };
3269
3270 struct mlx5_ifc_set_hca_cap_in_bits {
3271         u8         opcode[0x10];
3272         u8         reserved_at_10[0x10];
3273
3274         u8         reserved_at_20[0x10];
3275         u8         op_mod[0x10];
3276
3277         u8         reserved_at_40[0x40];
3278
3279         union mlx5_ifc_hca_cap_union_bits capability;
3280 };
3281
3282 enum {
3283         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3284         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3285         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3286         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3287 };
3288
3289 struct mlx5_ifc_set_fte_out_bits {
3290         u8         status[0x8];
3291         u8         reserved_at_8[0x18];
3292
3293         u8         syndrome[0x20];
3294
3295         u8         reserved_at_40[0x40];
3296 };
3297
3298 struct mlx5_ifc_set_fte_in_bits {
3299         u8         opcode[0x10];
3300         u8         reserved_at_10[0x10];
3301
3302         u8         reserved_at_20[0x10];
3303         u8         op_mod[0x10];
3304
3305         u8         other_vport[0x1];
3306         u8         reserved_at_41[0xf];
3307         u8         vport_number[0x10];
3308
3309         u8         reserved_at_60[0x20];
3310
3311         u8         table_type[0x8];
3312         u8         reserved_at_88[0x18];
3313
3314         u8         reserved_at_a0[0x8];
3315         u8         table_id[0x18];
3316
3317         u8         reserved_at_c0[0x18];
3318         u8         modify_enable_mask[0x8];
3319
3320         u8         reserved_at_e0[0x20];
3321
3322         u8         flow_index[0x20];
3323
3324         u8         reserved_at_120[0xe0];
3325
3326         struct mlx5_ifc_flow_context_bits flow_context;
3327 };
3328
3329 struct mlx5_ifc_rts2rts_qp_out_bits {
3330         u8         status[0x8];
3331         u8         reserved_at_8[0x18];
3332
3333         u8         syndrome[0x20];
3334
3335         u8         reserved_at_40[0x40];
3336 };
3337
3338 struct mlx5_ifc_rts2rts_qp_in_bits {
3339         u8         opcode[0x10];
3340         u8         reserved_at_10[0x10];
3341
3342         u8         reserved_at_20[0x10];
3343         u8         op_mod[0x10];
3344
3345         u8         reserved_at_40[0x8];
3346         u8         qpn[0x18];
3347
3348         u8         reserved_at_60[0x20];
3349
3350         u8         opt_param_mask[0x20];
3351
3352         u8         reserved_at_a0[0x20];
3353
3354         struct mlx5_ifc_qpc_bits qpc;
3355
3356         u8         reserved_at_800[0x80];
3357 };
3358
3359 struct mlx5_ifc_rtr2rts_qp_out_bits {
3360         u8         status[0x8];
3361         u8         reserved_at_8[0x18];
3362
3363         u8         syndrome[0x20];
3364
3365         u8         reserved_at_40[0x40];
3366 };
3367
3368 struct mlx5_ifc_rtr2rts_qp_in_bits {
3369         u8         opcode[0x10];
3370         u8         reserved_at_10[0x10];
3371
3372         u8         reserved_at_20[0x10];
3373         u8         op_mod[0x10];
3374
3375         u8         reserved_at_40[0x8];
3376         u8         qpn[0x18];
3377
3378         u8         reserved_at_60[0x20];
3379
3380         u8         opt_param_mask[0x20];
3381
3382         u8         reserved_at_a0[0x20];
3383
3384         struct mlx5_ifc_qpc_bits qpc;
3385
3386         u8         reserved_at_800[0x80];
3387 };
3388
3389 struct mlx5_ifc_rst2init_qp_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_at_8[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_at_40[0x40];
3396 };
3397
3398 struct mlx5_ifc_rst2init_qp_in_bits {
3399         u8         opcode[0x10];
3400         u8         reserved_at_10[0x10];
3401
3402         u8         reserved_at_20[0x10];
3403         u8         op_mod[0x10];
3404
3405         u8         reserved_at_40[0x8];
3406         u8         qpn[0x18];
3407
3408         u8         reserved_at_60[0x20];
3409
3410         u8         opt_param_mask[0x20];
3411
3412         u8         reserved_at_a0[0x20];
3413
3414         struct mlx5_ifc_qpc_bits qpc;
3415
3416         u8         reserved_at_800[0x80];
3417 };
3418
3419 struct mlx5_ifc_query_xrq_out_bits {
3420         u8         status[0x8];
3421         u8         reserved_at_8[0x18];
3422
3423         u8         syndrome[0x20];
3424
3425         u8         reserved_at_40[0x40];
3426
3427         struct mlx5_ifc_xrqc_bits xrq_context;
3428 };
3429
3430 struct mlx5_ifc_query_xrq_in_bits {
3431         u8         opcode[0x10];
3432         u8         reserved_at_10[0x10];
3433
3434         u8         reserved_at_20[0x10];
3435         u8         op_mod[0x10];
3436
3437         u8         reserved_at_40[0x8];
3438         u8         xrqn[0x18];
3439
3440         u8         reserved_at_60[0x20];
3441 };
3442
3443 struct mlx5_ifc_query_xrc_srq_out_bits {
3444         u8         status[0x8];
3445         u8         reserved_at_8[0x18];
3446
3447         u8         syndrome[0x20];
3448
3449         u8         reserved_at_40[0x40];
3450
3451         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3452
3453         u8         reserved_at_280[0x600];
3454
3455         u8         pas[0][0x40];
3456 };
3457
3458 struct mlx5_ifc_query_xrc_srq_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_at_10[0x10];
3461
3462         u8         reserved_at_20[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_at_40[0x8];
3466         u8         xrc_srqn[0x18];
3467
3468         u8         reserved_at_60[0x20];
3469 };
3470
3471 enum {
3472         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3473         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3474 };
3475
3476 struct mlx5_ifc_query_vport_state_out_bits {
3477         u8         status[0x8];
3478         u8         reserved_at_8[0x18];
3479
3480         u8         syndrome[0x20];
3481
3482         u8         reserved_at_40[0x20];
3483
3484         u8         reserved_at_60[0x18];
3485         u8         admin_state[0x4];
3486         u8         state[0x4];
3487 };
3488
3489 enum {
3490         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3491         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3492 };
3493
3494 struct mlx5_ifc_query_vport_state_in_bits {
3495         u8         opcode[0x10];
3496         u8         reserved_at_10[0x10];
3497
3498         u8         reserved_at_20[0x10];
3499         u8         op_mod[0x10];
3500
3501         u8         other_vport[0x1];
3502         u8         reserved_at_41[0xf];
3503         u8         vport_number[0x10];
3504
3505         u8         reserved_at_60[0x20];
3506 };
3507
3508 struct mlx5_ifc_query_vport_counter_out_bits {
3509         u8         status[0x8];
3510         u8         reserved_at_8[0x18];
3511
3512         u8         syndrome[0x20];
3513
3514         u8         reserved_at_40[0x40];
3515
3516         struct mlx5_ifc_traffic_counter_bits received_errors;
3517
3518         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3519
3520         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3521
3522         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3523
3524         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3525
3526         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3527
3528         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3529
3530         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3531
3532         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3533
3534         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3535
3536         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3537
3538         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3539
3540         u8         reserved_at_680[0xa00];
3541 };
3542
3543 enum {
3544         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3545 };
3546
3547 struct mlx5_ifc_query_vport_counter_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         other_vport[0x1];
3555         u8         reserved_at_41[0xb];
3556         u8         port_num[0x4];
3557         u8         vport_number[0x10];
3558
3559         u8         reserved_at_60[0x60];
3560
3561         u8         clear[0x1];
3562         u8         reserved_at_c1[0x1f];
3563
3564         u8         reserved_at_e0[0x20];
3565 };
3566
3567 struct mlx5_ifc_query_tis_out_bits {
3568         u8         status[0x8];
3569         u8         reserved_at_8[0x18];
3570
3571         u8         syndrome[0x20];
3572
3573         u8         reserved_at_40[0x40];
3574
3575         struct mlx5_ifc_tisc_bits tis_context;
3576 };
3577
3578 struct mlx5_ifc_query_tis_in_bits {
3579         u8         opcode[0x10];
3580         u8         reserved_at_10[0x10];
3581
3582         u8         reserved_at_20[0x10];
3583         u8         op_mod[0x10];
3584
3585         u8         reserved_at_40[0x8];
3586         u8         tisn[0x18];
3587
3588         u8         reserved_at_60[0x20];
3589 };
3590
3591 struct mlx5_ifc_query_tir_out_bits {
3592         u8         status[0x8];
3593         u8         reserved_at_8[0x18];
3594
3595         u8         syndrome[0x20];
3596
3597         u8         reserved_at_40[0xc0];
3598
3599         struct mlx5_ifc_tirc_bits tir_context;
3600 };
3601
3602 struct mlx5_ifc_query_tir_in_bits {
3603         u8         opcode[0x10];
3604         u8         reserved_at_10[0x10];
3605
3606         u8         reserved_at_20[0x10];
3607         u8         op_mod[0x10];
3608
3609         u8         reserved_at_40[0x8];
3610         u8         tirn[0x18];
3611
3612         u8         reserved_at_60[0x20];
3613 };
3614
3615 struct mlx5_ifc_query_srq_out_bits {
3616         u8         status[0x8];
3617         u8         reserved_at_8[0x18];
3618
3619         u8         syndrome[0x20];
3620
3621         u8         reserved_at_40[0x40];
3622
3623         struct mlx5_ifc_srqc_bits srq_context_entry;
3624
3625         u8         reserved_at_280[0x600];
3626
3627         u8         pas[0][0x40];
3628 };
3629
3630 struct mlx5_ifc_query_srq_in_bits {
3631         u8         opcode[0x10];
3632         u8         reserved_at_10[0x10];
3633
3634         u8         reserved_at_20[0x10];
3635         u8         op_mod[0x10];
3636
3637         u8         reserved_at_40[0x8];
3638         u8         srqn[0x18];
3639
3640         u8         reserved_at_60[0x20];
3641 };
3642
3643 struct mlx5_ifc_query_sq_out_bits {
3644         u8         status[0x8];
3645         u8         reserved_at_8[0x18];
3646
3647         u8         syndrome[0x20];
3648
3649         u8         reserved_at_40[0xc0];
3650
3651         struct mlx5_ifc_sqc_bits sq_context;
3652 };
3653
3654 struct mlx5_ifc_query_sq_in_bits {
3655         u8         opcode[0x10];
3656         u8         reserved_at_10[0x10];
3657
3658         u8         reserved_at_20[0x10];
3659         u8         op_mod[0x10];
3660
3661         u8         reserved_at_40[0x8];
3662         u8         sqn[0x18];
3663
3664         u8         reserved_at_60[0x20];
3665 };
3666
3667 struct mlx5_ifc_query_special_contexts_out_bits {
3668         u8         status[0x8];
3669         u8         reserved_at_8[0x18];
3670
3671         u8         syndrome[0x20];
3672
3673         u8         dump_fill_mkey[0x20];
3674
3675         u8         resd_lkey[0x20];
3676
3677         u8         null_mkey[0x20];
3678
3679         u8         reserved_at_a0[0x60];
3680 };
3681
3682 struct mlx5_ifc_query_special_contexts_in_bits {
3683         u8         opcode[0x10];
3684         u8         reserved_at_10[0x10];
3685
3686         u8         reserved_at_20[0x10];
3687         u8         op_mod[0x10];
3688
3689         u8         reserved_at_40[0x40];
3690 };
3691
3692 struct mlx5_ifc_query_scheduling_element_out_bits {
3693         u8         opcode[0x10];
3694         u8         reserved_at_10[0x10];
3695
3696         u8         reserved_at_20[0x10];
3697         u8         op_mod[0x10];
3698
3699         u8         reserved_at_40[0xc0];
3700
3701         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3702
3703         u8         reserved_at_300[0x100];
3704 };
3705
3706 enum {
3707         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3708 };
3709
3710 struct mlx5_ifc_query_scheduling_element_in_bits {
3711         u8         opcode[0x10];
3712         u8         reserved_at_10[0x10];
3713
3714         u8         reserved_at_20[0x10];
3715         u8         op_mod[0x10];
3716
3717         u8         scheduling_hierarchy[0x8];
3718         u8         reserved_at_48[0x18];
3719
3720         u8         scheduling_element_id[0x20];
3721
3722         u8         reserved_at_80[0x180];
3723 };
3724
3725 struct mlx5_ifc_query_rqt_out_bits {
3726         u8         status[0x8];
3727         u8         reserved_at_8[0x18];
3728
3729         u8         syndrome[0x20];
3730
3731         u8         reserved_at_40[0xc0];
3732
3733         struct mlx5_ifc_rqtc_bits rqt_context;
3734 };
3735
3736 struct mlx5_ifc_query_rqt_in_bits {
3737         u8         opcode[0x10];
3738         u8         reserved_at_10[0x10];
3739
3740         u8         reserved_at_20[0x10];
3741         u8         op_mod[0x10];
3742
3743         u8         reserved_at_40[0x8];
3744         u8         rqtn[0x18];
3745
3746         u8         reserved_at_60[0x20];
3747 };
3748
3749 struct mlx5_ifc_query_rq_out_bits {
3750         u8         status[0x8];
3751         u8         reserved_at_8[0x18];
3752
3753         u8         syndrome[0x20];
3754
3755         u8         reserved_at_40[0xc0];
3756
3757         struct mlx5_ifc_rqc_bits rq_context;
3758 };
3759
3760 struct mlx5_ifc_query_rq_in_bits {
3761         u8         opcode[0x10];
3762         u8         reserved_at_10[0x10];
3763
3764         u8         reserved_at_20[0x10];
3765         u8         op_mod[0x10];
3766
3767         u8         reserved_at_40[0x8];
3768         u8         rqn[0x18];
3769
3770         u8         reserved_at_60[0x20];
3771 };
3772
3773 struct mlx5_ifc_query_roce_address_out_bits {
3774         u8         status[0x8];
3775         u8         reserved_at_8[0x18];
3776
3777         u8         syndrome[0x20];
3778
3779         u8         reserved_at_40[0x40];
3780
3781         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3782 };
3783
3784 struct mlx5_ifc_query_roce_address_in_bits {
3785         u8         opcode[0x10];
3786         u8         reserved_at_10[0x10];
3787
3788         u8         reserved_at_20[0x10];
3789         u8         op_mod[0x10];
3790
3791         u8         roce_address_index[0x10];
3792         u8         reserved_at_50[0x10];
3793
3794         u8         reserved_at_60[0x20];
3795 };
3796
3797 struct mlx5_ifc_query_rmp_out_bits {
3798         u8         status[0x8];
3799         u8         reserved_at_8[0x18];
3800
3801         u8         syndrome[0x20];
3802
3803         u8         reserved_at_40[0xc0];
3804
3805         struct mlx5_ifc_rmpc_bits rmp_context;
3806 };
3807
3808 struct mlx5_ifc_query_rmp_in_bits {
3809         u8         opcode[0x10];
3810         u8         reserved_at_10[0x10];
3811
3812         u8         reserved_at_20[0x10];
3813         u8         op_mod[0x10];
3814
3815         u8         reserved_at_40[0x8];
3816         u8         rmpn[0x18];
3817
3818         u8         reserved_at_60[0x20];
3819 };
3820
3821 struct mlx5_ifc_query_qp_out_bits {
3822         u8         status[0x8];
3823         u8         reserved_at_8[0x18];
3824
3825         u8         syndrome[0x20];
3826
3827         u8         reserved_at_40[0x40];
3828
3829         u8         opt_param_mask[0x20];
3830
3831         u8         reserved_at_a0[0x20];
3832
3833         struct mlx5_ifc_qpc_bits qpc;
3834
3835         u8         reserved_at_800[0x80];
3836
3837         u8         pas[0][0x40];
3838 };
3839
3840 struct mlx5_ifc_query_qp_in_bits {
3841         u8         opcode[0x10];
3842         u8         reserved_at_10[0x10];
3843
3844         u8         reserved_at_20[0x10];
3845         u8         op_mod[0x10];
3846
3847         u8         reserved_at_40[0x8];
3848         u8         qpn[0x18];
3849
3850         u8         reserved_at_60[0x20];
3851 };
3852
3853 struct mlx5_ifc_query_q_counter_out_bits {
3854         u8         status[0x8];
3855         u8         reserved_at_8[0x18];
3856
3857         u8         syndrome[0x20];
3858
3859         u8         reserved_at_40[0x40];
3860
3861         u8         rx_write_requests[0x20];
3862
3863         u8         reserved_at_a0[0x20];
3864
3865         u8         rx_read_requests[0x20];
3866
3867         u8         reserved_at_e0[0x20];
3868
3869         u8         rx_atomic_requests[0x20];
3870
3871         u8         reserved_at_120[0x20];
3872
3873         u8         rx_dct_connect[0x20];
3874
3875         u8         reserved_at_160[0x20];
3876
3877         u8         out_of_buffer[0x20];
3878
3879         u8         reserved_at_1a0[0x20];
3880
3881         u8         out_of_sequence[0x20];
3882
3883         u8         reserved_at_1e0[0x20];
3884
3885         u8         duplicate_request[0x20];
3886
3887         u8         reserved_at_220[0x20];
3888
3889         u8         rnr_nak_retry_err[0x20];
3890
3891         u8         reserved_at_260[0x20];
3892
3893         u8         packet_seq_err[0x20];
3894
3895         u8         reserved_at_2a0[0x20];
3896
3897         u8         implied_nak_seq_err[0x20];
3898
3899         u8         reserved_at_2e0[0x20];
3900
3901         u8         local_ack_timeout_err[0x20];
3902
3903         u8         reserved_at_320[0x4e0];
3904 };
3905
3906 struct mlx5_ifc_query_q_counter_in_bits {
3907         u8         opcode[0x10];
3908         u8         reserved_at_10[0x10];
3909
3910         u8         reserved_at_20[0x10];
3911         u8         op_mod[0x10];
3912
3913         u8         reserved_at_40[0x80];
3914
3915         u8         clear[0x1];
3916         u8         reserved_at_c1[0x1f];
3917
3918         u8         reserved_at_e0[0x18];
3919         u8         counter_set_id[0x8];
3920 };
3921
3922 struct mlx5_ifc_query_pages_out_bits {
3923         u8         status[0x8];
3924         u8         reserved_at_8[0x18];
3925
3926         u8         syndrome[0x20];
3927
3928         u8         reserved_at_40[0x10];
3929         u8         function_id[0x10];
3930
3931         u8         num_pages[0x20];
3932 };
3933
3934 enum {
3935         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3936         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3937         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3938 };
3939
3940 struct mlx5_ifc_query_pages_in_bits {
3941         u8         opcode[0x10];
3942         u8         reserved_at_10[0x10];
3943
3944         u8         reserved_at_20[0x10];
3945         u8         op_mod[0x10];
3946
3947         u8         reserved_at_40[0x10];
3948         u8         function_id[0x10];
3949
3950         u8         reserved_at_60[0x20];
3951 };
3952
3953 struct mlx5_ifc_query_nic_vport_context_out_bits {
3954         u8         status[0x8];
3955         u8         reserved_at_8[0x18];
3956
3957         u8         syndrome[0x20];
3958
3959         u8         reserved_at_40[0x40];
3960
3961         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3962 };
3963
3964 struct mlx5_ifc_query_nic_vport_context_in_bits {
3965         u8         opcode[0x10];
3966         u8         reserved_at_10[0x10];
3967
3968         u8         reserved_at_20[0x10];
3969         u8         op_mod[0x10];
3970
3971         u8         other_vport[0x1];
3972         u8         reserved_at_41[0xf];
3973         u8         vport_number[0x10];
3974
3975         u8         reserved_at_60[0x5];
3976         u8         allowed_list_type[0x3];
3977         u8         reserved_at_68[0x18];
3978 };
3979
3980 struct mlx5_ifc_query_mkey_out_bits {
3981         u8         status[0x8];
3982         u8         reserved_at_8[0x18];
3983
3984         u8         syndrome[0x20];
3985
3986         u8         reserved_at_40[0x40];
3987
3988         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3989
3990         u8         reserved_at_280[0x600];
3991
3992         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3993
3994         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3995 };
3996
3997 struct mlx5_ifc_query_mkey_in_bits {
3998         u8         opcode[0x10];
3999         u8         reserved_at_10[0x10];
4000
4001         u8         reserved_at_20[0x10];
4002         u8         op_mod[0x10];
4003
4004         u8         reserved_at_40[0x8];
4005         u8         mkey_index[0x18];
4006
4007         u8         pg_access[0x1];
4008         u8         reserved_at_61[0x1f];
4009 };
4010
4011 struct mlx5_ifc_query_mad_demux_out_bits {
4012         u8         status[0x8];
4013         u8         reserved_at_8[0x18];
4014
4015         u8         syndrome[0x20];
4016
4017         u8         reserved_at_40[0x40];
4018
4019         u8         mad_dumux_parameters_block[0x20];
4020 };
4021
4022 struct mlx5_ifc_query_mad_demux_in_bits {
4023         u8         opcode[0x10];
4024         u8         reserved_at_10[0x10];
4025
4026         u8         reserved_at_20[0x10];
4027         u8         op_mod[0x10];
4028
4029         u8         reserved_at_40[0x40];
4030 };
4031
4032 struct mlx5_ifc_query_l2_table_entry_out_bits {
4033         u8         status[0x8];
4034         u8         reserved_at_8[0x18];
4035
4036         u8         syndrome[0x20];
4037
4038         u8         reserved_at_40[0xa0];
4039
4040         u8         reserved_at_e0[0x13];
4041         u8         vlan_valid[0x1];
4042         u8         vlan[0xc];
4043
4044         struct mlx5_ifc_mac_address_layout_bits mac_address;
4045
4046         u8         reserved_at_140[0xc0];
4047 };
4048
4049 struct mlx5_ifc_query_l2_table_entry_in_bits {
4050         u8         opcode[0x10];
4051         u8         reserved_at_10[0x10];
4052
4053         u8         reserved_at_20[0x10];
4054         u8         op_mod[0x10];
4055
4056         u8         reserved_at_40[0x60];
4057
4058         u8         reserved_at_a0[0x8];
4059         u8         table_index[0x18];
4060
4061         u8         reserved_at_c0[0x140];
4062 };
4063
4064 struct mlx5_ifc_query_issi_out_bits {
4065         u8         status[0x8];
4066         u8         reserved_at_8[0x18];
4067
4068         u8         syndrome[0x20];
4069
4070         u8         reserved_at_40[0x10];
4071         u8         current_issi[0x10];
4072
4073         u8         reserved_at_60[0xa0];
4074
4075         u8         reserved_at_100[76][0x8];
4076         u8         supported_issi_dw0[0x20];
4077 };
4078
4079 struct mlx5_ifc_query_issi_in_bits {
4080         u8         opcode[0x10];
4081         u8         reserved_at_10[0x10];
4082
4083         u8         reserved_at_20[0x10];
4084         u8         op_mod[0x10];
4085
4086         u8         reserved_at_40[0x40];
4087 };
4088
4089 struct mlx5_ifc_set_driver_version_out_bits {
4090         u8         status[0x8];
4091         u8         reserved_0[0x18];
4092
4093         u8         syndrome[0x20];
4094         u8         reserved_1[0x40];
4095 };
4096
4097 struct mlx5_ifc_set_driver_version_in_bits {
4098         u8         opcode[0x10];
4099         u8         reserved_0[0x10];
4100
4101         u8         reserved_1[0x10];
4102         u8         op_mod[0x10];
4103
4104         u8         reserved_2[0x40];
4105         u8         driver_version[64][0x8];
4106 };
4107
4108 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4109         u8         status[0x8];
4110         u8         reserved_at_8[0x18];
4111
4112         u8         syndrome[0x20];
4113
4114         u8         reserved_at_40[0x40];
4115
4116         struct mlx5_ifc_pkey_bits pkey[0];
4117 };
4118
4119 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4120         u8         opcode[0x10];
4121         u8         reserved_at_10[0x10];
4122
4123         u8         reserved_at_20[0x10];
4124         u8         op_mod[0x10];
4125
4126         u8         other_vport[0x1];
4127         u8         reserved_at_41[0xb];
4128         u8         port_num[0x4];
4129         u8         vport_number[0x10];
4130
4131         u8         reserved_at_60[0x10];
4132         u8         pkey_index[0x10];
4133 };
4134
4135 enum {
4136         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4137         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4138         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4139 };
4140
4141 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4142         u8         status[0x8];
4143         u8         reserved_at_8[0x18];
4144
4145         u8         syndrome[0x20];
4146
4147         u8         reserved_at_40[0x20];
4148
4149         u8         gids_num[0x10];
4150         u8         reserved_at_70[0x10];
4151
4152         struct mlx5_ifc_array128_auto_bits gid[0];
4153 };
4154
4155 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4156         u8         opcode[0x10];
4157         u8         reserved_at_10[0x10];
4158
4159         u8         reserved_at_20[0x10];
4160         u8         op_mod[0x10];
4161
4162         u8         other_vport[0x1];
4163         u8         reserved_at_41[0xb];
4164         u8         port_num[0x4];
4165         u8         vport_number[0x10];
4166
4167         u8         reserved_at_60[0x10];
4168         u8         gid_index[0x10];
4169 };
4170
4171 struct mlx5_ifc_query_hca_vport_context_out_bits {
4172         u8         status[0x8];
4173         u8         reserved_at_8[0x18];
4174
4175         u8         syndrome[0x20];
4176
4177         u8         reserved_at_40[0x40];
4178
4179         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4180 };
4181
4182 struct mlx5_ifc_query_hca_vport_context_in_bits {
4183         u8         opcode[0x10];
4184         u8         reserved_at_10[0x10];
4185
4186         u8         reserved_at_20[0x10];
4187         u8         op_mod[0x10];
4188
4189         u8         other_vport[0x1];
4190         u8         reserved_at_41[0xb];
4191         u8         port_num[0x4];
4192         u8         vport_number[0x10];
4193
4194         u8         reserved_at_60[0x20];
4195 };
4196
4197 struct mlx5_ifc_query_hca_cap_out_bits {
4198         u8         status[0x8];
4199         u8         reserved_at_8[0x18];
4200
4201         u8         syndrome[0x20];
4202
4203         u8         reserved_at_40[0x40];
4204
4205         union mlx5_ifc_hca_cap_union_bits capability;
4206 };
4207
4208 struct mlx5_ifc_query_hca_cap_in_bits {
4209         u8         opcode[0x10];
4210         u8         reserved_at_10[0x10];
4211
4212         u8         reserved_at_20[0x10];
4213         u8         op_mod[0x10];
4214
4215         u8         reserved_at_40[0x40];
4216 };
4217
4218 struct mlx5_ifc_query_flow_table_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_at_8[0x18];
4221
4222         u8         syndrome[0x20];
4223
4224         u8         reserved_at_40[0x80];
4225
4226         u8         reserved_at_c0[0x8];
4227         u8         level[0x8];
4228         u8         reserved_at_d0[0x8];
4229         u8         log_size[0x8];
4230
4231         u8         reserved_at_e0[0x120];
4232 };
4233
4234 struct mlx5_ifc_query_flow_table_in_bits {
4235         u8         opcode[0x10];
4236         u8         reserved_at_10[0x10];
4237
4238         u8         reserved_at_20[0x10];
4239         u8         op_mod[0x10];
4240
4241         u8         reserved_at_40[0x40];
4242
4243         u8         table_type[0x8];
4244         u8         reserved_at_88[0x18];
4245
4246         u8         reserved_at_a0[0x8];
4247         u8         table_id[0x18];
4248
4249         u8         reserved_at_c0[0x140];
4250 };
4251
4252 struct mlx5_ifc_query_fte_out_bits {
4253         u8         status[0x8];
4254         u8         reserved_at_8[0x18];
4255
4256         u8         syndrome[0x20];
4257
4258         u8         reserved_at_40[0x1c0];
4259
4260         struct mlx5_ifc_flow_context_bits flow_context;
4261 };
4262
4263 struct mlx5_ifc_query_fte_in_bits {
4264         u8         opcode[0x10];
4265         u8         reserved_at_10[0x10];
4266
4267         u8         reserved_at_20[0x10];
4268         u8         op_mod[0x10];
4269
4270         u8         reserved_at_40[0x40];
4271
4272         u8         table_type[0x8];
4273         u8         reserved_at_88[0x18];
4274
4275         u8         reserved_at_a0[0x8];
4276         u8         table_id[0x18];
4277
4278         u8         reserved_at_c0[0x40];
4279
4280         u8         flow_index[0x20];
4281
4282         u8         reserved_at_120[0xe0];
4283 };
4284
4285 enum {
4286         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4287         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4288         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4289 };
4290
4291 struct mlx5_ifc_query_flow_group_out_bits {
4292         u8         status[0x8];
4293         u8         reserved_at_8[0x18];
4294
4295         u8         syndrome[0x20];
4296
4297         u8         reserved_at_40[0xa0];
4298
4299         u8         start_flow_index[0x20];
4300
4301         u8         reserved_at_100[0x20];
4302
4303         u8         end_flow_index[0x20];
4304
4305         u8         reserved_at_140[0xa0];
4306
4307         u8         reserved_at_1e0[0x18];
4308         u8         match_criteria_enable[0x8];
4309
4310         struct mlx5_ifc_fte_match_param_bits match_criteria;
4311
4312         u8         reserved_at_1200[0xe00];
4313 };
4314
4315 struct mlx5_ifc_query_flow_group_in_bits {
4316         u8         opcode[0x10];
4317         u8         reserved_at_10[0x10];
4318
4319         u8         reserved_at_20[0x10];
4320         u8         op_mod[0x10];
4321
4322         u8         reserved_at_40[0x40];
4323
4324         u8         table_type[0x8];
4325         u8         reserved_at_88[0x18];
4326
4327         u8         reserved_at_a0[0x8];
4328         u8         table_id[0x18];
4329
4330         u8         group_id[0x20];
4331
4332         u8         reserved_at_e0[0x120];
4333 };
4334
4335 struct mlx5_ifc_query_flow_counter_out_bits {
4336         u8         status[0x8];
4337         u8         reserved_at_8[0x18];
4338
4339         u8         syndrome[0x20];
4340
4341         u8         reserved_at_40[0x40];
4342
4343         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4344 };
4345
4346 struct mlx5_ifc_query_flow_counter_in_bits {
4347         u8         opcode[0x10];
4348         u8         reserved_at_10[0x10];
4349
4350         u8         reserved_at_20[0x10];
4351         u8         op_mod[0x10];
4352
4353         u8         reserved_at_40[0x80];
4354
4355         u8         clear[0x1];
4356         u8         reserved_at_c1[0xf];
4357         u8         num_of_counters[0x10];
4358
4359         u8         reserved_at_e0[0x10];
4360         u8         flow_counter_id[0x10];
4361 };
4362
4363 struct mlx5_ifc_query_esw_vport_context_out_bits {
4364         u8         status[0x8];
4365         u8         reserved_at_8[0x18];
4366
4367         u8         syndrome[0x20];
4368
4369         u8         reserved_at_40[0x40];
4370
4371         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4372 };
4373
4374 struct mlx5_ifc_query_esw_vport_context_in_bits {
4375         u8         opcode[0x10];
4376         u8         reserved_at_10[0x10];
4377
4378         u8         reserved_at_20[0x10];
4379         u8         op_mod[0x10];
4380
4381         u8         other_vport[0x1];
4382         u8         reserved_at_41[0xf];
4383         u8         vport_number[0x10];
4384
4385         u8         reserved_at_60[0x20];
4386 };
4387
4388 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4389         u8         status[0x8];
4390         u8         reserved_at_8[0x18];
4391
4392         u8         syndrome[0x20];
4393
4394         u8         reserved_at_40[0x40];
4395 };
4396
4397 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4398         u8         reserved_at_0[0x1c];
4399         u8         vport_cvlan_insert[0x1];
4400         u8         vport_svlan_insert[0x1];
4401         u8         vport_cvlan_strip[0x1];
4402         u8         vport_svlan_strip[0x1];
4403 };
4404
4405 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4406         u8         opcode[0x10];
4407         u8         reserved_at_10[0x10];
4408
4409         u8         reserved_at_20[0x10];
4410         u8         op_mod[0x10];
4411
4412         u8         other_vport[0x1];
4413         u8         reserved_at_41[0xf];
4414         u8         vport_number[0x10];
4415
4416         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4417
4418         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4419 };
4420
4421 struct mlx5_ifc_query_eq_out_bits {
4422         u8         status[0x8];
4423         u8         reserved_at_8[0x18];
4424
4425         u8         syndrome[0x20];
4426
4427         u8         reserved_at_40[0x40];
4428
4429         struct mlx5_ifc_eqc_bits eq_context_entry;
4430
4431         u8         reserved_at_280[0x40];
4432
4433         u8         event_bitmask[0x40];
4434
4435         u8         reserved_at_300[0x580];
4436
4437         u8         pas[0][0x40];
4438 };
4439
4440 struct mlx5_ifc_query_eq_in_bits {
4441         u8         opcode[0x10];
4442         u8         reserved_at_10[0x10];
4443
4444         u8         reserved_at_20[0x10];
4445         u8         op_mod[0x10];
4446
4447         u8         reserved_at_40[0x18];
4448         u8         eq_number[0x8];
4449
4450         u8         reserved_at_60[0x20];
4451 };
4452
4453 struct mlx5_ifc_encap_header_in_bits {
4454         u8         reserved_at_0[0x5];
4455         u8         header_type[0x3];
4456         u8         reserved_at_8[0xe];
4457         u8         encap_header_size[0xa];
4458
4459         u8         reserved_at_20[0x10];
4460         u8         encap_header[2][0x8];
4461
4462         u8         more_encap_header[0][0x8];
4463 };
4464
4465 struct mlx5_ifc_query_encap_header_out_bits {
4466         u8         status[0x8];
4467         u8         reserved_at_8[0x18];
4468
4469         u8         syndrome[0x20];
4470
4471         u8         reserved_at_40[0xa0];
4472
4473         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4474 };
4475
4476 struct mlx5_ifc_query_encap_header_in_bits {
4477         u8         opcode[0x10];
4478         u8         reserved_at_10[0x10];
4479
4480         u8         reserved_at_20[0x10];
4481         u8         op_mod[0x10];
4482
4483         u8         encap_id[0x20];
4484
4485         u8         reserved_at_60[0xa0];
4486 };
4487
4488 struct mlx5_ifc_alloc_encap_header_out_bits {
4489         u8         status[0x8];
4490         u8         reserved_at_8[0x18];
4491
4492         u8         syndrome[0x20];
4493
4494         u8         encap_id[0x20];
4495
4496         u8         reserved_at_60[0x20];
4497 };
4498
4499 struct mlx5_ifc_alloc_encap_header_in_bits {
4500         u8         opcode[0x10];
4501         u8         reserved_at_10[0x10];
4502
4503         u8         reserved_at_20[0x10];
4504         u8         op_mod[0x10];
4505
4506         u8         reserved_at_40[0xa0];
4507
4508         struct mlx5_ifc_encap_header_in_bits encap_header;
4509 };
4510
4511 struct mlx5_ifc_dealloc_encap_header_out_bits {
4512         u8         status[0x8];
4513         u8         reserved_at_8[0x18];
4514
4515         u8         syndrome[0x20];
4516
4517         u8         reserved_at_40[0x40];
4518 };
4519
4520 struct mlx5_ifc_dealloc_encap_header_in_bits {
4521         u8         opcode[0x10];
4522         u8         reserved_at_10[0x10];
4523
4524         u8         reserved_20[0x10];
4525         u8         op_mod[0x10];
4526
4527         u8         encap_id[0x20];
4528
4529         u8         reserved_60[0x20];
4530 };
4531
4532 struct mlx5_ifc_query_dct_out_bits {
4533         u8         status[0x8];
4534         u8         reserved_at_8[0x18];
4535
4536         u8         syndrome[0x20];
4537
4538         u8         reserved_at_40[0x40];
4539
4540         struct mlx5_ifc_dctc_bits dct_context_entry;
4541
4542         u8         reserved_at_280[0x180];
4543 };
4544
4545 struct mlx5_ifc_query_dct_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_at_10[0x10];
4548
4549         u8         reserved_at_20[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         reserved_at_40[0x8];
4553         u8         dctn[0x18];
4554
4555         u8         reserved_at_60[0x20];
4556 };
4557
4558 struct mlx5_ifc_query_cq_out_bits {
4559         u8         status[0x8];
4560         u8         reserved_at_8[0x18];
4561
4562         u8         syndrome[0x20];
4563
4564         u8         reserved_at_40[0x40];
4565
4566         struct mlx5_ifc_cqc_bits cq_context;
4567
4568         u8         reserved_at_280[0x600];
4569
4570         u8         pas[0][0x40];
4571 };
4572
4573 struct mlx5_ifc_query_cq_in_bits {
4574         u8         opcode[0x10];
4575         u8         reserved_at_10[0x10];
4576
4577         u8         reserved_at_20[0x10];
4578         u8         op_mod[0x10];
4579
4580         u8         reserved_at_40[0x8];
4581         u8         cqn[0x18];
4582
4583         u8         reserved_at_60[0x20];
4584 };
4585
4586 struct mlx5_ifc_query_cong_status_out_bits {
4587         u8         status[0x8];
4588         u8         reserved_at_8[0x18];
4589
4590         u8         syndrome[0x20];
4591
4592         u8         reserved_at_40[0x20];
4593
4594         u8         enable[0x1];
4595         u8         tag_enable[0x1];
4596         u8         reserved_at_62[0x1e];
4597 };
4598
4599 struct mlx5_ifc_query_cong_status_in_bits {
4600         u8         opcode[0x10];
4601         u8         reserved_at_10[0x10];
4602
4603         u8         reserved_at_20[0x10];
4604         u8         op_mod[0x10];
4605
4606         u8         reserved_at_40[0x18];
4607         u8         priority[0x4];
4608         u8         cong_protocol[0x4];
4609
4610         u8         reserved_at_60[0x20];
4611 };
4612
4613 struct mlx5_ifc_query_cong_statistics_out_bits {
4614         u8         status[0x8];
4615         u8         reserved_at_8[0x18];
4616
4617         u8         syndrome[0x20];
4618
4619         u8         reserved_at_40[0x40];
4620
4621         u8         cur_flows[0x20];
4622
4623         u8         sum_flows[0x20];
4624
4625         u8         cnp_ignored_high[0x20];
4626
4627         u8         cnp_ignored_low[0x20];
4628
4629         u8         cnp_handled_high[0x20];
4630
4631         u8         cnp_handled_low[0x20];
4632
4633         u8         reserved_at_140[0x100];
4634
4635         u8         time_stamp_high[0x20];
4636
4637         u8         time_stamp_low[0x20];
4638
4639         u8         accumulators_period[0x20];
4640
4641         u8         ecn_marked_roce_packets_high[0x20];
4642
4643         u8         ecn_marked_roce_packets_low[0x20];
4644
4645         u8         cnps_sent_high[0x20];
4646
4647         u8         cnps_sent_low[0x20];
4648
4649         u8         reserved_at_320[0x560];
4650 };
4651
4652 struct mlx5_ifc_query_cong_statistics_in_bits {
4653         u8         opcode[0x10];
4654         u8         reserved_at_10[0x10];
4655
4656         u8         reserved_at_20[0x10];
4657         u8         op_mod[0x10];
4658
4659         u8         clear[0x1];
4660         u8         reserved_at_41[0x1f];
4661
4662         u8         reserved_at_60[0x20];
4663 };
4664
4665 struct mlx5_ifc_query_cong_params_out_bits {
4666         u8         status[0x8];
4667         u8         reserved_at_8[0x18];
4668
4669         u8         syndrome[0x20];
4670
4671         u8         reserved_at_40[0x40];
4672
4673         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4674 };
4675
4676 struct mlx5_ifc_query_cong_params_in_bits {
4677         u8         opcode[0x10];
4678         u8         reserved_at_10[0x10];
4679
4680         u8         reserved_at_20[0x10];
4681         u8         op_mod[0x10];
4682
4683         u8         reserved_at_40[0x1c];
4684         u8         cong_protocol[0x4];
4685
4686         u8         reserved_at_60[0x20];
4687 };
4688
4689 struct mlx5_ifc_query_adapter_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_at_8[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_at_40[0x40];
4696
4697         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4698 };
4699
4700 struct mlx5_ifc_query_adapter_in_bits {
4701         u8         opcode[0x10];
4702         u8         reserved_at_10[0x10];
4703
4704         u8         reserved_at_20[0x10];
4705         u8         op_mod[0x10];
4706
4707         u8         reserved_at_40[0x40];
4708 };
4709
4710 struct mlx5_ifc_qp_2rst_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_at_8[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         reserved_at_40[0x40];
4717 };
4718
4719 struct mlx5_ifc_qp_2rst_in_bits {
4720         u8         opcode[0x10];
4721         u8         reserved_at_10[0x10];
4722
4723         u8         reserved_at_20[0x10];
4724         u8         op_mod[0x10];
4725
4726         u8         reserved_at_40[0x8];
4727         u8         qpn[0x18];
4728
4729         u8         reserved_at_60[0x20];
4730 };
4731
4732 struct mlx5_ifc_qp_2err_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_at_8[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_at_40[0x40];
4739 };
4740
4741 struct mlx5_ifc_qp_2err_in_bits {
4742         u8         opcode[0x10];
4743         u8         reserved_at_10[0x10];
4744
4745         u8         reserved_at_20[0x10];
4746         u8         op_mod[0x10];
4747
4748         u8         reserved_at_40[0x8];
4749         u8         qpn[0x18];
4750
4751         u8         reserved_at_60[0x20];
4752 };
4753
4754 struct mlx5_ifc_page_fault_resume_out_bits {
4755         u8         status[0x8];
4756         u8         reserved_at_8[0x18];
4757
4758         u8         syndrome[0x20];
4759
4760         u8         reserved_at_40[0x40];
4761 };
4762
4763 struct mlx5_ifc_page_fault_resume_in_bits {
4764         u8         opcode[0x10];
4765         u8         reserved_at_10[0x10];
4766
4767         u8         reserved_at_20[0x10];
4768         u8         op_mod[0x10];
4769
4770         u8         error[0x1];
4771         u8         reserved_at_41[0x4];
4772         u8         page_fault_type[0x3];
4773         u8         wq_number[0x18];
4774
4775         u8         reserved_at_60[0x8];
4776         u8         token[0x18];
4777 };
4778
4779 struct mlx5_ifc_nop_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_at_8[0x18];
4782
4783         u8         syndrome[0x20];
4784
4785         u8         reserved_at_40[0x40];
4786 };
4787
4788 struct mlx5_ifc_nop_in_bits {
4789         u8         opcode[0x10];
4790         u8         reserved_at_10[0x10];
4791
4792         u8         reserved_at_20[0x10];
4793         u8         op_mod[0x10];
4794
4795         u8         reserved_at_40[0x40];
4796 };
4797
4798 struct mlx5_ifc_modify_vport_state_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_at_8[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_at_40[0x40];
4805 };
4806
4807 struct mlx5_ifc_modify_vport_state_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_at_10[0x10];
4810
4811         u8         reserved_at_20[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         other_vport[0x1];
4815         u8         reserved_at_41[0xf];
4816         u8         vport_number[0x10];
4817
4818         u8         reserved_at_60[0x18];
4819         u8         admin_state[0x4];
4820         u8         reserved_at_7c[0x4];
4821 };
4822
4823 struct mlx5_ifc_modify_tis_out_bits {
4824         u8         status[0x8];
4825         u8         reserved_at_8[0x18];
4826
4827         u8         syndrome[0x20];
4828
4829         u8         reserved_at_40[0x40];
4830 };
4831
4832 struct mlx5_ifc_modify_tis_bitmask_bits {
4833         u8         reserved_at_0[0x20];
4834
4835         u8         reserved_at_20[0x1d];
4836         u8         lag_tx_port_affinity[0x1];
4837         u8         strict_lag_tx_port_affinity[0x1];
4838         u8         prio[0x1];
4839 };
4840
4841 struct mlx5_ifc_modify_tis_in_bits {
4842         u8         opcode[0x10];
4843         u8         reserved_at_10[0x10];
4844
4845         u8         reserved_at_20[0x10];
4846         u8         op_mod[0x10];
4847
4848         u8         reserved_at_40[0x8];
4849         u8         tisn[0x18];
4850
4851         u8         reserved_at_60[0x20];
4852
4853         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4854
4855         u8         reserved_at_c0[0x40];
4856
4857         struct mlx5_ifc_tisc_bits ctx;
4858 };
4859
4860 struct mlx5_ifc_modify_tir_bitmask_bits {
4861         u8         reserved_at_0[0x20];
4862
4863         u8         reserved_at_20[0x1b];
4864         u8         self_lb_en[0x1];
4865         u8         reserved_at_3c[0x1];
4866         u8         hash[0x1];
4867         u8         reserved_at_3e[0x1];
4868         u8         lro[0x1];
4869 };
4870
4871 struct mlx5_ifc_modify_tir_out_bits {
4872         u8         status[0x8];
4873         u8         reserved_at_8[0x18];
4874
4875         u8         syndrome[0x20];
4876
4877         u8         reserved_at_40[0x40];
4878 };
4879
4880 struct mlx5_ifc_modify_tir_in_bits {
4881         u8         opcode[0x10];
4882         u8         reserved_at_10[0x10];
4883
4884         u8         reserved_at_20[0x10];
4885         u8         op_mod[0x10];
4886
4887         u8         reserved_at_40[0x8];
4888         u8         tirn[0x18];
4889
4890         u8         reserved_at_60[0x20];
4891
4892         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4893
4894         u8         reserved_at_c0[0x40];
4895
4896         struct mlx5_ifc_tirc_bits ctx;
4897 };
4898
4899 struct mlx5_ifc_modify_sq_out_bits {
4900         u8         status[0x8];
4901         u8         reserved_at_8[0x18];
4902
4903         u8         syndrome[0x20];
4904
4905         u8         reserved_at_40[0x40];
4906 };
4907
4908 struct mlx5_ifc_modify_sq_in_bits {
4909         u8         opcode[0x10];
4910         u8         reserved_at_10[0x10];
4911
4912         u8         reserved_at_20[0x10];
4913         u8         op_mod[0x10];
4914
4915         u8         sq_state[0x4];
4916         u8         reserved_at_44[0x4];
4917         u8         sqn[0x18];
4918
4919         u8         reserved_at_60[0x20];
4920
4921         u8         modify_bitmask[0x40];
4922
4923         u8         reserved_at_c0[0x40];
4924
4925         struct mlx5_ifc_sqc_bits ctx;
4926 };
4927
4928 struct mlx5_ifc_modify_scheduling_element_out_bits {
4929         u8         status[0x8];
4930         u8         reserved_at_8[0x18];
4931
4932         u8         syndrome[0x20];
4933
4934         u8         reserved_at_40[0x1c0];
4935 };
4936
4937 enum {
4938         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4939         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4940 };
4941
4942 struct mlx5_ifc_modify_scheduling_element_in_bits {
4943         u8         opcode[0x10];
4944         u8         reserved_at_10[0x10];
4945
4946         u8         reserved_at_20[0x10];
4947         u8         op_mod[0x10];
4948
4949         u8         scheduling_hierarchy[0x8];
4950         u8         reserved_at_48[0x18];
4951
4952         u8         scheduling_element_id[0x20];
4953
4954         u8         reserved_at_80[0x20];
4955
4956         u8         modify_bitmask[0x20];
4957
4958         u8         reserved_at_c0[0x40];
4959
4960         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4961
4962         u8         reserved_at_300[0x100];
4963 };
4964
4965 struct mlx5_ifc_modify_rqt_out_bits {
4966         u8         status[0x8];
4967         u8         reserved_at_8[0x18];
4968
4969         u8         syndrome[0x20];
4970
4971         u8         reserved_at_40[0x40];
4972 };
4973
4974 struct mlx5_ifc_rqt_bitmask_bits {
4975         u8         reserved_at_0[0x20];
4976
4977         u8         reserved_at_20[0x1f];
4978         u8         rqn_list[0x1];
4979 };
4980
4981 struct mlx5_ifc_modify_rqt_in_bits {
4982         u8         opcode[0x10];
4983         u8         reserved_at_10[0x10];
4984
4985         u8         reserved_at_20[0x10];
4986         u8         op_mod[0x10];
4987
4988         u8         reserved_at_40[0x8];
4989         u8         rqtn[0x18];
4990
4991         u8         reserved_at_60[0x20];
4992
4993         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4994
4995         u8         reserved_at_c0[0x40];
4996
4997         struct mlx5_ifc_rqtc_bits ctx;
4998 };
4999
5000 struct mlx5_ifc_modify_rq_out_bits {
5001         u8         status[0x8];
5002         u8         reserved_at_8[0x18];
5003
5004         u8         syndrome[0x20];
5005
5006         u8         reserved_at_40[0x40];
5007 };
5008
5009 enum {
5010         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5011         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5012 };
5013
5014 struct mlx5_ifc_modify_rq_in_bits {
5015         u8         opcode[0x10];
5016         u8         reserved_at_10[0x10];
5017
5018         u8         reserved_at_20[0x10];
5019         u8         op_mod[0x10];
5020
5021         u8         rq_state[0x4];
5022         u8         reserved_at_44[0x4];
5023         u8         rqn[0x18];
5024
5025         u8         reserved_at_60[0x20];
5026
5027         u8         modify_bitmask[0x40];
5028
5029         u8         reserved_at_c0[0x40];
5030
5031         struct mlx5_ifc_rqc_bits ctx;
5032 };
5033
5034 struct mlx5_ifc_modify_rmp_out_bits {
5035         u8         status[0x8];
5036         u8         reserved_at_8[0x18];
5037
5038         u8         syndrome[0x20];
5039
5040         u8         reserved_at_40[0x40];
5041 };
5042
5043 struct mlx5_ifc_rmp_bitmask_bits {
5044         u8         reserved_at_0[0x20];
5045
5046         u8         reserved_at_20[0x1f];
5047         u8         lwm[0x1];
5048 };
5049
5050 struct mlx5_ifc_modify_rmp_in_bits {
5051         u8         opcode[0x10];
5052         u8         reserved_at_10[0x10];
5053
5054         u8         reserved_at_20[0x10];
5055         u8         op_mod[0x10];
5056
5057         u8         rmp_state[0x4];
5058         u8         reserved_at_44[0x4];
5059         u8         rmpn[0x18];
5060
5061         u8         reserved_at_60[0x20];
5062
5063         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5064
5065         u8         reserved_at_c0[0x40];
5066
5067         struct mlx5_ifc_rmpc_bits ctx;
5068 };
5069
5070 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5071         u8         status[0x8];
5072         u8         reserved_at_8[0x18];
5073
5074         u8         syndrome[0x20];
5075
5076         u8         reserved_at_40[0x40];
5077 };
5078
5079 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5080         u8         reserved_at_0[0x16];
5081         u8         node_guid[0x1];
5082         u8         port_guid[0x1];
5083         u8         min_inline[0x1];
5084         u8         mtu[0x1];
5085         u8         change_event[0x1];
5086         u8         promisc[0x1];
5087         u8         permanent_address[0x1];
5088         u8         addresses_list[0x1];
5089         u8         roce_en[0x1];
5090         u8         reserved_at_1f[0x1];
5091 };
5092
5093 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5094         u8         opcode[0x10];
5095         u8         reserved_at_10[0x10];
5096
5097         u8         reserved_at_20[0x10];
5098         u8         op_mod[0x10];
5099
5100         u8         other_vport[0x1];
5101         u8         reserved_at_41[0xf];
5102         u8         vport_number[0x10];
5103
5104         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5105
5106         u8         reserved_at_80[0x780];
5107
5108         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5109 };
5110
5111 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5112         u8         status[0x8];
5113         u8         reserved_at_8[0x18];
5114
5115         u8         syndrome[0x20];
5116
5117         u8         reserved_at_40[0x40];
5118 };
5119
5120 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5121         u8         opcode[0x10];
5122         u8         reserved_at_10[0x10];
5123
5124         u8         reserved_at_20[0x10];
5125         u8         op_mod[0x10];
5126
5127         u8         other_vport[0x1];
5128         u8         reserved_at_41[0xb];
5129         u8         port_num[0x4];
5130         u8         vport_number[0x10];
5131
5132         u8         reserved_at_60[0x20];
5133
5134         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5135 };
5136
5137 struct mlx5_ifc_modify_cq_out_bits {
5138         u8         status[0x8];
5139         u8         reserved_at_8[0x18];
5140
5141         u8         syndrome[0x20];
5142
5143         u8         reserved_at_40[0x40];
5144 };
5145
5146 enum {
5147         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5148         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5149 };
5150
5151 struct mlx5_ifc_modify_cq_in_bits {
5152         u8         opcode[0x10];
5153         u8         reserved_at_10[0x10];
5154
5155         u8         reserved_at_20[0x10];
5156         u8         op_mod[0x10];
5157
5158         u8         reserved_at_40[0x8];
5159         u8         cqn[0x18];
5160
5161         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5162
5163         struct mlx5_ifc_cqc_bits cq_context;
5164
5165         u8         reserved_at_280[0x600];
5166
5167         u8         pas[0][0x40];
5168 };
5169
5170 struct mlx5_ifc_modify_cong_status_out_bits {
5171         u8         status[0x8];
5172         u8         reserved_at_8[0x18];
5173
5174         u8         syndrome[0x20];
5175
5176         u8         reserved_at_40[0x40];
5177 };
5178
5179 struct mlx5_ifc_modify_cong_status_in_bits {
5180         u8         opcode[0x10];
5181         u8         reserved_at_10[0x10];
5182
5183         u8         reserved_at_20[0x10];
5184         u8         op_mod[0x10];
5185
5186         u8         reserved_at_40[0x18];
5187         u8         priority[0x4];
5188         u8         cong_protocol[0x4];
5189
5190         u8         enable[0x1];
5191         u8         tag_enable[0x1];
5192         u8         reserved_at_62[0x1e];
5193 };
5194
5195 struct mlx5_ifc_modify_cong_params_out_bits {
5196         u8         status[0x8];
5197         u8         reserved_at_8[0x18];
5198
5199         u8         syndrome[0x20];
5200
5201         u8         reserved_at_40[0x40];
5202 };
5203
5204 struct mlx5_ifc_modify_cong_params_in_bits {
5205         u8         opcode[0x10];
5206         u8         reserved_at_10[0x10];
5207
5208         u8         reserved_at_20[0x10];
5209         u8         op_mod[0x10];
5210
5211         u8         reserved_at_40[0x1c];
5212         u8         cong_protocol[0x4];
5213
5214         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5215
5216         u8         reserved_at_80[0x80];
5217
5218         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5219 };
5220
5221 struct mlx5_ifc_manage_pages_out_bits {
5222         u8         status[0x8];
5223         u8         reserved_at_8[0x18];
5224
5225         u8         syndrome[0x20];
5226
5227         u8         output_num_entries[0x20];
5228
5229         u8         reserved_at_60[0x20];
5230
5231         u8         pas[0][0x40];
5232 };
5233
5234 enum {
5235         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5236         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5237         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5238 };
5239
5240 struct mlx5_ifc_manage_pages_in_bits {
5241         u8         opcode[0x10];
5242         u8         reserved_at_10[0x10];
5243
5244         u8         reserved_at_20[0x10];
5245         u8         op_mod[0x10];
5246
5247         u8         reserved_at_40[0x10];
5248         u8         function_id[0x10];
5249
5250         u8         input_num_entries[0x20];
5251
5252         u8         pas[0][0x40];
5253 };
5254
5255 struct mlx5_ifc_mad_ifc_out_bits {
5256         u8         status[0x8];
5257         u8         reserved_at_8[0x18];
5258
5259         u8         syndrome[0x20];
5260
5261         u8         reserved_at_40[0x40];
5262
5263         u8         response_mad_packet[256][0x8];
5264 };
5265
5266 struct mlx5_ifc_mad_ifc_in_bits {
5267         u8         opcode[0x10];
5268         u8         reserved_at_10[0x10];
5269
5270         u8         reserved_at_20[0x10];
5271         u8         op_mod[0x10];
5272
5273         u8         remote_lid[0x10];
5274         u8         reserved_at_50[0x8];
5275         u8         port[0x8];
5276
5277         u8         reserved_at_60[0x20];
5278
5279         u8         mad[256][0x8];
5280 };
5281
5282 struct mlx5_ifc_init_hca_out_bits {
5283         u8         status[0x8];
5284         u8         reserved_at_8[0x18];
5285
5286         u8         syndrome[0x20];
5287
5288         u8         reserved_at_40[0x40];
5289 };
5290
5291 struct mlx5_ifc_init_hca_in_bits {
5292         u8         opcode[0x10];
5293         u8         reserved_at_10[0x10];
5294
5295         u8         reserved_at_20[0x10];
5296         u8         op_mod[0x10];
5297
5298         u8         reserved_at_40[0x40];
5299 };
5300
5301 struct mlx5_ifc_init2rtr_qp_out_bits {
5302         u8         status[0x8];
5303         u8         reserved_at_8[0x18];
5304
5305         u8         syndrome[0x20];
5306
5307         u8         reserved_at_40[0x40];
5308 };
5309
5310 struct mlx5_ifc_init2rtr_qp_in_bits {
5311         u8         opcode[0x10];
5312         u8         reserved_at_10[0x10];
5313
5314         u8         reserved_at_20[0x10];
5315         u8         op_mod[0x10];
5316
5317         u8         reserved_at_40[0x8];
5318         u8         qpn[0x18];
5319
5320         u8         reserved_at_60[0x20];
5321
5322         u8         opt_param_mask[0x20];
5323
5324         u8         reserved_at_a0[0x20];
5325
5326         struct mlx5_ifc_qpc_bits qpc;
5327
5328         u8         reserved_at_800[0x80];
5329 };
5330
5331 struct mlx5_ifc_init2init_qp_out_bits {
5332         u8         status[0x8];
5333         u8         reserved_at_8[0x18];
5334
5335         u8         syndrome[0x20];
5336
5337         u8         reserved_at_40[0x40];
5338 };
5339
5340 struct mlx5_ifc_init2init_qp_in_bits {
5341         u8         opcode[0x10];
5342         u8         reserved_at_10[0x10];
5343
5344         u8         reserved_at_20[0x10];
5345         u8         op_mod[0x10];
5346
5347         u8         reserved_at_40[0x8];
5348         u8         qpn[0x18];
5349
5350         u8         reserved_at_60[0x20];
5351
5352         u8         opt_param_mask[0x20];
5353
5354         u8         reserved_at_a0[0x20];
5355
5356         struct mlx5_ifc_qpc_bits qpc;
5357
5358         u8         reserved_at_800[0x80];
5359 };
5360
5361 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5362         u8         status[0x8];
5363         u8         reserved_at_8[0x18];
5364
5365         u8         syndrome[0x20];
5366
5367         u8         reserved_at_40[0x40];
5368
5369         u8         packet_headers_log[128][0x8];
5370
5371         u8         packet_syndrome[64][0x8];
5372 };
5373
5374 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5375         u8         opcode[0x10];
5376         u8         reserved_at_10[0x10];
5377
5378         u8         reserved_at_20[0x10];
5379         u8         op_mod[0x10];
5380
5381         u8         reserved_at_40[0x40];
5382 };
5383
5384 struct mlx5_ifc_gen_eqe_in_bits {
5385         u8         opcode[0x10];
5386         u8         reserved_at_10[0x10];
5387
5388         u8         reserved_at_20[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         reserved_at_40[0x18];
5392         u8         eq_number[0x8];
5393
5394         u8         reserved_at_60[0x20];
5395
5396         u8         eqe[64][0x8];
5397 };
5398
5399 struct mlx5_ifc_gen_eq_out_bits {
5400         u8         status[0x8];
5401         u8         reserved_at_8[0x18];
5402
5403         u8         syndrome[0x20];
5404
5405         u8         reserved_at_40[0x40];
5406 };
5407
5408 struct mlx5_ifc_enable_hca_out_bits {
5409         u8         status[0x8];
5410         u8         reserved_at_8[0x18];
5411
5412         u8         syndrome[0x20];
5413
5414         u8         reserved_at_40[0x20];
5415 };
5416
5417 struct mlx5_ifc_enable_hca_in_bits {
5418         u8         opcode[0x10];
5419         u8         reserved_at_10[0x10];
5420
5421         u8         reserved_at_20[0x10];
5422         u8         op_mod[0x10];
5423
5424         u8         reserved_at_40[0x10];
5425         u8         function_id[0x10];
5426
5427         u8         reserved_at_60[0x20];
5428 };
5429
5430 struct mlx5_ifc_drain_dct_out_bits {
5431         u8         status[0x8];
5432         u8         reserved_at_8[0x18];
5433
5434         u8         syndrome[0x20];
5435
5436         u8         reserved_at_40[0x40];
5437 };
5438
5439 struct mlx5_ifc_drain_dct_in_bits {
5440         u8         opcode[0x10];
5441         u8         reserved_at_10[0x10];
5442
5443         u8         reserved_at_20[0x10];
5444         u8         op_mod[0x10];
5445
5446         u8         reserved_at_40[0x8];
5447         u8         dctn[0x18];
5448
5449         u8         reserved_at_60[0x20];
5450 };
5451
5452 struct mlx5_ifc_disable_hca_out_bits {
5453         u8         status[0x8];
5454         u8         reserved_at_8[0x18];
5455
5456         u8         syndrome[0x20];
5457
5458         u8         reserved_at_40[0x20];
5459 };
5460
5461 struct mlx5_ifc_disable_hca_in_bits {
5462         u8         opcode[0x10];
5463         u8         reserved_at_10[0x10];
5464
5465         u8         reserved_at_20[0x10];
5466         u8         op_mod[0x10];
5467
5468         u8         reserved_at_40[0x10];
5469         u8         function_id[0x10];
5470
5471         u8         reserved_at_60[0x20];
5472 };
5473
5474 struct mlx5_ifc_detach_from_mcg_out_bits {
5475         u8         status[0x8];
5476         u8         reserved_at_8[0x18];
5477
5478         u8         syndrome[0x20];
5479
5480         u8         reserved_at_40[0x40];
5481 };
5482
5483 struct mlx5_ifc_detach_from_mcg_in_bits {
5484         u8         opcode[0x10];
5485         u8         reserved_at_10[0x10];
5486
5487         u8         reserved_at_20[0x10];
5488         u8         op_mod[0x10];
5489
5490         u8         reserved_at_40[0x8];
5491         u8         qpn[0x18];
5492
5493         u8         reserved_at_60[0x20];
5494
5495         u8         multicast_gid[16][0x8];
5496 };
5497
5498 struct mlx5_ifc_destroy_xrq_out_bits {
5499         u8         status[0x8];
5500         u8         reserved_at_8[0x18];
5501
5502         u8         syndrome[0x20];
5503
5504         u8         reserved_at_40[0x40];
5505 };
5506
5507 struct mlx5_ifc_destroy_xrq_in_bits {
5508         u8         opcode[0x10];
5509         u8         reserved_at_10[0x10];
5510
5511         u8         reserved_at_20[0x10];
5512         u8         op_mod[0x10];
5513
5514         u8         reserved_at_40[0x8];
5515         u8         xrqn[0x18];
5516
5517         u8         reserved_at_60[0x20];
5518 };
5519
5520 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5521         u8         status[0x8];
5522         u8         reserved_at_8[0x18];
5523
5524         u8         syndrome[0x20];
5525
5526         u8         reserved_at_40[0x40];
5527 };
5528
5529 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5530         u8         opcode[0x10];
5531         u8         reserved_at_10[0x10];
5532
5533         u8         reserved_at_20[0x10];
5534         u8         op_mod[0x10];
5535
5536         u8         reserved_at_40[0x8];
5537         u8         xrc_srqn[0x18];
5538
5539         u8         reserved_at_60[0x20];
5540 };
5541
5542 struct mlx5_ifc_destroy_tis_out_bits {
5543         u8         status[0x8];
5544         u8         reserved_at_8[0x18];
5545
5546         u8         syndrome[0x20];
5547
5548         u8         reserved_at_40[0x40];
5549 };
5550
5551 struct mlx5_ifc_destroy_tis_in_bits {
5552         u8         opcode[0x10];
5553         u8         reserved_at_10[0x10];
5554
5555         u8         reserved_at_20[0x10];
5556         u8         op_mod[0x10];
5557
5558         u8         reserved_at_40[0x8];
5559         u8         tisn[0x18];
5560
5561         u8         reserved_at_60[0x20];
5562 };
5563
5564 struct mlx5_ifc_destroy_tir_out_bits {
5565         u8         status[0x8];
5566         u8         reserved_at_8[0x18];
5567
5568         u8         syndrome[0x20];
5569
5570         u8         reserved_at_40[0x40];
5571 };
5572
5573 struct mlx5_ifc_destroy_tir_in_bits {
5574         u8         opcode[0x10];
5575         u8         reserved_at_10[0x10];
5576
5577         u8         reserved_at_20[0x10];
5578         u8         op_mod[0x10];
5579
5580         u8         reserved_at_40[0x8];
5581         u8         tirn[0x18];
5582
5583         u8         reserved_at_60[0x20];
5584 };
5585
5586 struct mlx5_ifc_destroy_srq_out_bits {
5587         u8         status[0x8];
5588         u8         reserved_at_8[0x18];
5589
5590         u8         syndrome[0x20];
5591
5592         u8         reserved_at_40[0x40];
5593 };
5594
5595 struct mlx5_ifc_destroy_srq_in_bits {
5596         u8         opcode[0x10];
5597         u8         reserved_at_10[0x10];
5598
5599         u8         reserved_at_20[0x10];
5600         u8         op_mod[0x10];
5601
5602         u8         reserved_at_40[0x8];
5603         u8         srqn[0x18];
5604
5605         u8         reserved_at_60[0x20];
5606 };
5607
5608 struct mlx5_ifc_destroy_sq_out_bits {
5609         u8         status[0x8];
5610         u8         reserved_at_8[0x18];
5611
5612         u8         syndrome[0x20];
5613
5614         u8         reserved_at_40[0x40];
5615 };
5616
5617 struct mlx5_ifc_destroy_sq_in_bits {
5618         u8         opcode[0x10];
5619         u8         reserved_at_10[0x10];
5620
5621         u8         reserved_at_20[0x10];
5622         u8         op_mod[0x10];
5623
5624         u8         reserved_at_40[0x8];
5625         u8         sqn[0x18];
5626
5627         u8         reserved_at_60[0x20];
5628 };
5629
5630 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5631         u8         status[0x8];
5632         u8         reserved_at_8[0x18];
5633
5634         u8         syndrome[0x20];
5635
5636         u8         reserved_at_40[0x1c0];
5637 };
5638
5639 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5640         u8         opcode[0x10];
5641         u8         reserved_at_10[0x10];
5642
5643         u8         reserved_at_20[0x10];
5644         u8         op_mod[0x10];
5645
5646         u8         scheduling_hierarchy[0x8];
5647         u8         reserved_at_48[0x18];
5648
5649         u8         scheduling_element_id[0x20];
5650
5651         u8         reserved_at_80[0x180];
5652 };
5653
5654 struct mlx5_ifc_destroy_rqt_out_bits {
5655         u8         status[0x8];
5656         u8         reserved_at_8[0x18];
5657
5658         u8         syndrome[0x20];
5659
5660         u8         reserved_at_40[0x40];
5661 };
5662
5663 struct mlx5_ifc_destroy_rqt_in_bits {
5664         u8         opcode[0x10];
5665         u8         reserved_at_10[0x10];
5666
5667         u8         reserved_at_20[0x10];
5668         u8         op_mod[0x10];
5669
5670         u8         reserved_at_40[0x8];
5671         u8         rqtn[0x18];
5672
5673         u8         reserved_at_60[0x20];
5674 };
5675
5676 struct mlx5_ifc_destroy_rq_out_bits {
5677         u8         status[0x8];
5678         u8         reserved_at_8[0x18];
5679
5680         u8         syndrome[0x20];
5681
5682         u8         reserved_at_40[0x40];
5683 };
5684
5685 struct mlx5_ifc_destroy_rq_in_bits {
5686         u8         opcode[0x10];
5687         u8         reserved_at_10[0x10];
5688
5689         u8         reserved_at_20[0x10];
5690         u8         op_mod[0x10];
5691
5692         u8         reserved_at_40[0x8];
5693         u8         rqn[0x18];
5694
5695         u8         reserved_at_60[0x20];
5696 };
5697
5698 struct mlx5_ifc_destroy_rmp_out_bits {
5699         u8         status[0x8];
5700         u8         reserved_at_8[0x18];
5701
5702         u8         syndrome[0x20];
5703
5704         u8         reserved_at_40[0x40];
5705 };
5706
5707 struct mlx5_ifc_destroy_rmp_in_bits {
5708         u8         opcode[0x10];
5709         u8         reserved_at_10[0x10];
5710
5711         u8         reserved_at_20[0x10];
5712         u8         op_mod[0x10];
5713
5714         u8         reserved_at_40[0x8];
5715         u8         rmpn[0x18];
5716
5717         u8         reserved_at_60[0x20];
5718 };
5719
5720 struct mlx5_ifc_destroy_qp_out_bits {
5721         u8         status[0x8];
5722         u8         reserved_at_8[0x18];
5723
5724         u8         syndrome[0x20];
5725
5726         u8         reserved_at_40[0x40];
5727 };
5728
5729 struct mlx5_ifc_destroy_qp_in_bits {
5730         u8         opcode[0x10];
5731         u8         reserved_at_10[0x10];
5732
5733         u8         reserved_at_20[0x10];
5734         u8         op_mod[0x10];
5735
5736         u8         reserved_at_40[0x8];
5737         u8         qpn[0x18];
5738
5739         u8         reserved_at_60[0x20];
5740 };
5741
5742 struct mlx5_ifc_destroy_psv_out_bits {
5743         u8         status[0x8];
5744         u8         reserved_at_8[0x18];
5745
5746         u8         syndrome[0x20];
5747
5748         u8         reserved_at_40[0x40];
5749 };
5750
5751 struct mlx5_ifc_destroy_psv_in_bits {
5752         u8         opcode[0x10];
5753         u8         reserved_at_10[0x10];
5754
5755         u8         reserved_at_20[0x10];
5756         u8         op_mod[0x10];
5757
5758         u8         reserved_at_40[0x8];
5759         u8         psvn[0x18];
5760
5761         u8         reserved_at_60[0x20];
5762 };
5763
5764 struct mlx5_ifc_destroy_mkey_out_bits {
5765         u8         status[0x8];
5766         u8         reserved_at_8[0x18];
5767
5768         u8         syndrome[0x20];
5769
5770         u8         reserved_at_40[0x40];
5771 };
5772
5773 struct mlx5_ifc_destroy_mkey_in_bits {
5774         u8         opcode[0x10];
5775         u8         reserved_at_10[0x10];
5776
5777         u8         reserved_at_20[0x10];
5778         u8         op_mod[0x10];
5779
5780         u8         reserved_at_40[0x8];
5781         u8         mkey_index[0x18];
5782
5783         u8         reserved_at_60[0x20];
5784 };
5785
5786 struct mlx5_ifc_destroy_flow_table_out_bits {
5787         u8         status[0x8];
5788         u8         reserved_at_8[0x18];
5789
5790         u8         syndrome[0x20];
5791
5792         u8         reserved_at_40[0x40];
5793 };
5794
5795 struct mlx5_ifc_destroy_flow_table_in_bits {
5796         u8         opcode[0x10];
5797         u8         reserved_at_10[0x10];
5798
5799         u8         reserved_at_20[0x10];
5800         u8         op_mod[0x10];
5801
5802         u8         other_vport[0x1];
5803         u8         reserved_at_41[0xf];
5804         u8         vport_number[0x10];
5805
5806         u8         reserved_at_60[0x20];
5807
5808         u8         table_type[0x8];
5809         u8         reserved_at_88[0x18];
5810
5811         u8         reserved_at_a0[0x8];
5812         u8         table_id[0x18];
5813
5814         u8         reserved_at_c0[0x140];
5815 };
5816
5817 struct mlx5_ifc_destroy_flow_group_out_bits {
5818         u8         status[0x8];
5819         u8         reserved_at_8[0x18];
5820
5821         u8         syndrome[0x20];
5822
5823         u8         reserved_at_40[0x40];
5824 };
5825
5826 struct mlx5_ifc_destroy_flow_group_in_bits {
5827         u8         opcode[0x10];
5828         u8         reserved_at_10[0x10];
5829
5830         u8         reserved_at_20[0x10];
5831         u8         op_mod[0x10];
5832
5833         u8         other_vport[0x1];
5834         u8         reserved_at_41[0xf];
5835         u8         vport_number[0x10];
5836
5837         u8         reserved_at_60[0x20];
5838
5839         u8         table_type[0x8];
5840         u8         reserved_at_88[0x18];
5841
5842         u8         reserved_at_a0[0x8];
5843         u8         table_id[0x18];
5844
5845         u8         group_id[0x20];
5846
5847         u8         reserved_at_e0[0x120];
5848 };
5849
5850 struct mlx5_ifc_destroy_eq_out_bits {
5851         u8         status[0x8];
5852         u8         reserved_at_8[0x18];
5853
5854         u8         syndrome[0x20];
5855
5856         u8         reserved_at_40[0x40];
5857 };
5858
5859 struct mlx5_ifc_destroy_eq_in_bits {
5860         u8         opcode[0x10];
5861         u8         reserved_at_10[0x10];
5862
5863         u8         reserved_at_20[0x10];
5864         u8         op_mod[0x10];
5865
5866         u8         reserved_at_40[0x18];
5867         u8         eq_number[0x8];
5868
5869         u8         reserved_at_60[0x20];
5870 };
5871
5872 struct mlx5_ifc_destroy_dct_out_bits {
5873         u8         status[0x8];
5874         u8         reserved_at_8[0x18];
5875
5876         u8         syndrome[0x20];
5877
5878         u8         reserved_at_40[0x40];
5879 };
5880
5881 struct mlx5_ifc_destroy_dct_in_bits {
5882         u8         opcode[0x10];
5883         u8         reserved_at_10[0x10];
5884
5885         u8         reserved_at_20[0x10];
5886         u8         op_mod[0x10];
5887
5888         u8         reserved_at_40[0x8];
5889         u8         dctn[0x18];
5890
5891         u8         reserved_at_60[0x20];
5892 };
5893
5894 struct mlx5_ifc_destroy_cq_out_bits {
5895         u8         status[0x8];
5896         u8         reserved_at_8[0x18];
5897
5898         u8         syndrome[0x20];
5899
5900         u8         reserved_at_40[0x40];
5901 };
5902
5903 struct mlx5_ifc_destroy_cq_in_bits {
5904         u8         opcode[0x10];
5905         u8         reserved_at_10[0x10];
5906
5907         u8         reserved_at_20[0x10];
5908         u8         op_mod[0x10];
5909
5910         u8         reserved_at_40[0x8];
5911         u8         cqn[0x18];
5912
5913         u8         reserved_at_60[0x20];
5914 };
5915
5916 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5917         u8         status[0x8];
5918         u8         reserved_at_8[0x18];
5919
5920         u8         syndrome[0x20];
5921
5922         u8         reserved_at_40[0x40];
5923 };
5924
5925 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5926         u8         opcode[0x10];
5927         u8         reserved_at_10[0x10];
5928
5929         u8         reserved_at_20[0x10];
5930         u8         op_mod[0x10];
5931
5932         u8         reserved_at_40[0x20];
5933
5934         u8         reserved_at_60[0x10];
5935         u8         vxlan_udp_port[0x10];
5936 };
5937
5938 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5939         u8         status[0x8];
5940         u8         reserved_at_8[0x18];
5941
5942         u8         syndrome[0x20];
5943
5944         u8         reserved_at_40[0x40];
5945 };
5946
5947 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5948         u8         opcode[0x10];
5949         u8         reserved_at_10[0x10];
5950
5951         u8         reserved_at_20[0x10];
5952         u8         op_mod[0x10];
5953
5954         u8         reserved_at_40[0x60];
5955
5956         u8         reserved_at_a0[0x8];
5957         u8         table_index[0x18];
5958
5959         u8         reserved_at_c0[0x140];
5960 };
5961
5962 struct mlx5_ifc_delete_fte_out_bits {
5963         u8         status[0x8];
5964         u8         reserved_at_8[0x18];
5965
5966         u8         syndrome[0x20];
5967
5968         u8         reserved_at_40[0x40];
5969 };
5970
5971 struct mlx5_ifc_delete_fte_in_bits {
5972         u8         opcode[0x10];
5973         u8         reserved_at_10[0x10];
5974
5975         u8         reserved_at_20[0x10];
5976         u8         op_mod[0x10];
5977
5978         u8         other_vport[0x1];
5979         u8         reserved_at_41[0xf];
5980         u8         vport_number[0x10];
5981
5982         u8         reserved_at_60[0x20];
5983
5984         u8         table_type[0x8];
5985         u8         reserved_at_88[0x18];
5986
5987         u8         reserved_at_a0[0x8];
5988         u8         table_id[0x18];
5989
5990         u8         reserved_at_c0[0x40];
5991
5992         u8         flow_index[0x20];
5993
5994         u8         reserved_at_120[0xe0];
5995 };
5996
5997 struct mlx5_ifc_dealloc_xrcd_out_bits {
5998         u8         status[0x8];
5999         u8         reserved_at_8[0x18];
6000
6001         u8         syndrome[0x20];
6002
6003         u8         reserved_at_40[0x40];
6004 };
6005
6006 struct mlx5_ifc_dealloc_xrcd_in_bits {
6007         u8         opcode[0x10];
6008         u8         reserved_at_10[0x10];
6009
6010         u8         reserved_at_20[0x10];
6011         u8         op_mod[0x10];
6012
6013         u8         reserved_at_40[0x8];
6014         u8         xrcd[0x18];
6015
6016         u8         reserved_at_60[0x20];
6017 };
6018
6019 struct mlx5_ifc_dealloc_uar_out_bits {
6020         u8         status[0x8];
6021         u8         reserved_at_8[0x18];
6022
6023         u8         syndrome[0x20];
6024
6025         u8         reserved_at_40[0x40];
6026 };
6027
6028 struct mlx5_ifc_dealloc_uar_in_bits {
6029         u8         opcode[0x10];
6030         u8         reserved_at_10[0x10];
6031
6032         u8         reserved_at_20[0x10];
6033         u8         op_mod[0x10];
6034
6035         u8         reserved_at_40[0x8];
6036         u8         uar[0x18];
6037
6038         u8         reserved_at_60[0x20];
6039 };
6040
6041 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6042         u8         status[0x8];
6043         u8         reserved_at_8[0x18];
6044
6045         u8         syndrome[0x20];
6046
6047         u8         reserved_at_40[0x40];
6048 };
6049
6050 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6051         u8         opcode[0x10];
6052         u8         reserved_at_10[0x10];
6053
6054         u8         reserved_at_20[0x10];
6055         u8         op_mod[0x10];
6056
6057         u8         reserved_at_40[0x8];
6058         u8         transport_domain[0x18];
6059
6060         u8         reserved_at_60[0x20];
6061 };
6062
6063 struct mlx5_ifc_dealloc_q_counter_out_bits {
6064         u8         status[0x8];
6065         u8         reserved_at_8[0x18];
6066
6067         u8         syndrome[0x20];
6068
6069         u8         reserved_at_40[0x40];
6070 };
6071
6072 struct mlx5_ifc_dealloc_q_counter_in_bits {
6073         u8         opcode[0x10];
6074         u8         reserved_at_10[0x10];
6075
6076         u8         reserved_at_20[0x10];
6077         u8         op_mod[0x10];
6078
6079         u8         reserved_at_40[0x18];
6080         u8         counter_set_id[0x8];
6081
6082         u8         reserved_at_60[0x20];
6083 };
6084
6085 struct mlx5_ifc_dealloc_pd_out_bits {
6086         u8         status[0x8];
6087         u8         reserved_at_8[0x18];
6088
6089         u8         syndrome[0x20];
6090
6091         u8         reserved_at_40[0x40];
6092 };
6093
6094 struct mlx5_ifc_dealloc_pd_in_bits {
6095         u8         opcode[0x10];
6096         u8         reserved_at_10[0x10];
6097
6098         u8         reserved_at_20[0x10];
6099         u8         op_mod[0x10];
6100
6101         u8         reserved_at_40[0x8];
6102         u8         pd[0x18];
6103
6104         u8         reserved_at_60[0x20];
6105 };
6106
6107 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6108         u8         status[0x8];
6109         u8         reserved_at_8[0x18];
6110
6111         u8         syndrome[0x20];
6112
6113         u8         reserved_at_40[0x40];
6114 };
6115
6116 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6117         u8         opcode[0x10];
6118         u8         reserved_at_10[0x10];
6119
6120         u8         reserved_at_20[0x10];
6121         u8         op_mod[0x10];
6122
6123         u8         reserved_at_40[0x10];
6124         u8         flow_counter_id[0x10];
6125
6126         u8         reserved_at_60[0x20];
6127 };
6128
6129 struct mlx5_ifc_create_xrq_out_bits {
6130         u8         status[0x8];
6131         u8         reserved_at_8[0x18];
6132
6133         u8         syndrome[0x20];
6134
6135         u8         reserved_at_40[0x8];
6136         u8         xrqn[0x18];
6137
6138         u8         reserved_at_60[0x20];
6139 };
6140
6141 struct mlx5_ifc_create_xrq_in_bits {
6142         u8         opcode[0x10];
6143         u8         reserved_at_10[0x10];
6144
6145         u8         reserved_at_20[0x10];
6146         u8         op_mod[0x10];
6147
6148         u8         reserved_at_40[0x40];
6149
6150         struct mlx5_ifc_xrqc_bits xrq_context;
6151 };
6152
6153 struct mlx5_ifc_create_xrc_srq_out_bits {
6154         u8         status[0x8];
6155         u8         reserved_at_8[0x18];
6156
6157         u8         syndrome[0x20];
6158
6159         u8         reserved_at_40[0x8];
6160         u8         xrc_srqn[0x18];
6161
6162         u8         reserved_at_60[0x20];
6163 };
6164
6165 struct mlx5_ifc_create_xrc_srq_in_bits {
6166         u8         opcode[0x10];
6167         u8         reserved_at_10[0x10];
6168
6169         u8         reserved_at_20[0x10];
6170         u8         op_mod[0x10];
6171
6172         u8         reserved_at_40[0x40];
6173
6174         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6175
6176         u8         reserved_at_280[0x600];
6177
6178         u8         pas[0][0x40];
6179 };
6180
6181 struct mlx5_ifc_create_tis_out_bits {
6182         u8         status[0x8];
6183         u8         reserved_at_8[0x18];
6184
6185         u8         syndrome[0x20];
6186
6187         u8         reserved_at_40[0x8];
6188         u8         tisn[0x18];
6189
6190         u8         reserved_at_60[0x20];
6191 };
6192
6193 struct mlx5_ifc_create_tis_in_bits {
6194         u8         opcode[0x10];
6195         u8         reserved_at_10[0x10];
6196
6197         u8         reserved_at_20[0x10];
6198         u8         op_mod[0x10];
6199
6200         u8         reserved_at_40[0xc0];
6201
6202         struct mlx5_ifc_tisc_bits ctx;
6203 };
6204
6205 struct mlx5_ifc_create_tir_out_bits {
6206         u8         status[0x8];
6207         u8         reserved_at_8[0x18];
6208
6209         u8         syndrome[0x20];
6210
6211         u8         reserved_at_40[0x8];
6212         u8         tirn[0x18];
6213
6214         u8         reserved_at_60[0x20];
6215 };
6216
6217 struct mlx5_ifc_create_tir_in_bits {
6218         u8         opcode[0x10];
6219         u8         reserved_at_10[0x10];
6220
6221         u8         reserved_at_20[0x10];
6222         u8         op_mod[0x10];
6223
6224         u8         reserved_at_40[0xc0];
6225
6226         struct mlx5_ifc_tirc_bits ctx;
6227 };
6228
6229 struct mlx5_ifc_create_srq_out_bits {
6230         u8         status[0x8];
6231         u8         reserved_at_8[0x18];
6232
6233         u8         syndrome[0x20];
6234
6235         u8         reserved_at_40[0x8];
6236         u8         srqn[0x18];
6237
6238         u8         reserved_at_60[0x20];
6239 };
6240
6241 struct mlx5_ifc_create_srq_in_bits {
6242         u8         opcode[0x10];
6243         u8         reserved_at_10[0x10];
6244
6245         u8         reserved_at_20[0x10];
6246         u8         op_mod[0x10];
6247
6248         u8         reserved_at_40[0x40];
6249
6250         struct mlx5_ifc_srqc_bits srq_context_entry;
6251
6252         u8         reserved_at_280[0x600];
6253
6254         u8         pas[0][0x40];
6255 };
6256
6257 struct mlx5_ifc_create_sq_out_bits {
6258         u8         status[0x8];
6259         u8         reserved_at_8[0x18];
6260
6261         u8         syndrome[0x20];
6262
6263         u8         reserved_at_40[0x8];
6264         u8         sqn[0x18];
6265
6266         u8         reserved_at_60[0x20];
6267 };
6268
6269 struct mlx5_ifc_create_sq_in_bits {
6270         u8         opcode[0x10];
6271         u8         reserved_at_10[0x10];
6272
6273         u8         reserved_at_20[0x10];
6274         u8         op_mod[0x10];
6275
6276         u8         reserved_at_40[0xc0];
6277
6278         struct mlx5_ifc_sqc_bits ctx;
6279 };
6280
6281 struct mlx5_ifc_create_scheduling_element_out_bits {
6282         u8         status[0x8];
6283         u8         reserved_at_8[0x18];
6284
6285         u8         syndrome[0x20];
6286
6287         u8         reserved_at_40[0x40];
6288
6289         u8         scheduling_element_id[0x20];
6290
6291         u8         reserved_at_a0[0x160];
6292 };
6293
6294 struct mlx5_ifc_create_scheduling_element_in_bits {
6295         u8         opcode[0x10];
6296         u8         reserved_at_10[0x10];
6297
6298         u8         reserved_at_20[0x10];
6299         u8         op_mod[0x10];
6300
6301         u8         scheduling_hierarchy[0x8];
6302         u8         reserved_at_48[0x18];
6303
6304         u8         reserved_at_60[0xa0];
6305
6306         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6307
6308         u8         reserved_at_300[0x100];
6309 };
6310
6311 struct mlx5_ifc_create_rqt_out_bits {
6312         u8         status[0x8];
6313         u8         reserved_at_8[0x18];
6314
6315         u8         syndrome[0x20];
6316
6317         u8         reserved_at_40[0x8];
6318         u8         rqtn[0x18];
6319
6320         u8         reserved_at_60[0x20];
6321 };
6322
6323 struct mlx5_ifc_create_rqt_in_bits {
6324         u8         opcode[0x10];
6325         u8         reserved_at_10[0x10];
6326
6327         u8         reserved_at_20[0x10];
6328         u8         op_mod[0x10];
6329
6330         u8         reserved_at_40[0xc0];
6331
6332         struct mlx5_ifc_rqtc_bits rqt_context;
6333 };
6334
6335 struct mlx5_ifc_create_rq_out_bits {
6336         u8         status[0x8];
6337         u8         reserved_at_8[0x18];
6338
6339         u8         syndrome[0x20];
6340
6341         u8         reserved_at_40[0x8];
6342         u8         rqn[0x18];
6343
6344         u8         reserved_at_60[0x20];
6345 };
6346
6347 struct mlx5_ifc_create_rq_in_bits {
6348         u8         opcode[0x10];
6349         u8         reserved_at_10[0x10];
6350
6351         u8         reserved_at_20[0x10];
6352         u8         op_mod[0x10];
6353
6354         u8         reserved_at_40[0xc0];
6355
6356         struct mlx5_ifc_rqc_bits ctx;
6357 };
6358
6359 struct mlx5_ifc_create_rmp_out_bits {
6360         u8         status[0x8];
6361         u8         reserved_at_8[0x18];
6362
6363         u8         syndrome[0x20];
6364
6365         u8         reserved_at_40[0x8];
6366         u8         rmpn[0x18];
6367
6368         u8         reserved_at_60[0x20];
6369 };
6370
6371 struct mlx5_ifc_create_rmp_in_bits {
6372         u8         opcode[0x10];
6373         u8         reserved_at_10[0x10];
6374
6375         u8         reserved_at_20[0x10];
6376         u8         op_mod[0x10];
6377
6378         u8         reserved_at_40[0xc0];
6379
6380         struct mlx5_ifc_rmpc_bits ctx;
6381 };
6382
6383 struct mlx5_ifc_create_qp_out_bits {
6384         u8         status[0x8];
6385         u8         reserved_at_8[0x18];
6386
6387         u8         syndrome[0x20];
6388
6389         u8         reserved_at_40[0x8];
6390         u8         qpn[0x18];
6391
6392         u8         reserved_at_60[0x20];
6393 };
6394
6395 struct mlx5_ifc_create_qp_in_bits {
6396         u8         opcode[0x10];
6397         u8         reserved_at_10[0x10];
6398
6399         u8         reserved_at_20[0x10];
6400         u8         op_mod[0x10];
6401
6402         u8         reserved_at_40[0x40];
6403
6404         u8         opt_param_mask[0x20];
6405
6406         u8         reserved_at_a0[0x20];
6407
6408         struct mlx5_ifc_qpc_bits qpc;
6409
6410         u8         reserved_at_800[0x80];
6411
6412         u8         pas[0][0x40];
6413 };
6414
6415 struct mlx5_ifc_create_psv_out_bits {
6416         u8         status[0x8];
6417         u8         reserved_at_8[0x18];
6418
6419         u8         syndrome[0x20];
6420
6421         u8         reserved_at_40[0x40];
6422
6423         u8         reserved_at_80[0x8];
6424         u8         psv0_index[0x18];
6425
6426         u8         reserved_at_a0[0x8];
6427         u8         psv1_index[0x18];
6428
6429         u8         reserved_at_c0[0x8];
6430         u8         psv2_index[0x18];
6431
6432         u8         reserved_at_e0[0x8];
6433         u8         psv3_index[0x18];
6434 };
6435
6436 struct mlx5_ifc_create_psv_in_bits {
6437         u8         opcode[0x10];
6438         u8         reserved_at_10[0x10];
6439
6440         u8         reserved_at_20[0x10];
6441         u8         op_mod[0x10];
6442
6443         u8         num_psv[0x4];
6444         u8         reserved_at_44[0x4];
6445         u8         pd[0x18];
6446
6447         u8         reserved_at_60[0x20];
6448 };
6449
6450 struct mlx5_ifc_create_mkey_out_bits {
6451         u8         status[0x8];
6452         u8         reserved_at_8[0x18];
6453
6454         u8         syndrome[0x20];
6455
6456         u8         reserved_at_40[0x8];
6457         u8         mkey_index[0x18];
6458
6459         u8         reserved_at_60[0x20];
6460 };
6461
6462 struct mlx5_ifc_create_mkey_in_bits {
6463         u8         opcode[0x10];
6464         u8         reserved_at_10[0x10];
6465
6466         u8         reserved_at_20[0x10];
6467         u8         op_mod[0x10];
6468
6469         u8         reserved_at_40[0x20];
6470
6471         u8         pg_access[0x1];
6472         u8         reserved_at_61[0x1f];
6473
6474         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6475
6476         u8         reserved_at_280[0x80];
6477
6478         u8         translations_octword_actual_size[0x20];
6479
6480         u8         reserved_at_320[0x560];
6481
6482         u8         klm_pas_mtt[0][0x20];
6483 };
6484
6485 struct mlx5_ifc_create_flow_table_out_bits {
6486         u8         status[0x8];
6487         u8         reserved_at_8[0x18];
6488
6489         u8         syndrome[0x20];
6490
6491         u8         reserved_at_40[0x8];
6492         u8         table_id[0x18];
6493
6494         u8         reserved_at_60[0x20];
6495 };
6496
6497 struct mlx5_ifc_create_flow_table_in_bits {
6498         u8         opcode[0x10];
6499         u8         reserved_at_10[0x10];
6500
6501         u8         reserved_at_20[0x10];
6502         u8         op_mod[0x10];
6503
6504         u8         other_vport[0x1];
6505         u8         reserved_at_41[0xf];
6506         u8         vport_number[0x10];
6507
6508         u8         reserved_at_60[0x20];
6509
6510         u8         table_type[0x8];
6511         u8         reserved_at_88[0x18];
6512
6513         u8         reserved_at_a0[0x20];
6514
6515         u8         encap_en[0x1];
6516         u8         decap_en[0x1];
6517         u8         reserved_at_c2[0x2];
6518         u8         table_miss_mode[0x4];
6519         u8         level[0x8];
6520         u8         reserved_at_d0[0x8];
6521         u8         log_size[0x8];
6522
6523         u8         reserved_at_e0[0x8];
6524         u8         table_miss_id[0x18];
6525
6526         u8         reserved_at_100[0x8];
6527         u8         lag_master_next_table_id[0x18];
6528
6529         u8         reserved_at_120[0x80];
6530 };
6531
6532 struct mlx5_ifc_create_flow_group_out_bits {
6533         u8         status[0x8];
6534         u8         reserved_at_8[0x18];
6535
6536         u8         syndrome[0x20];
6537
6538         u8         reserved_at_40[0x8];
6539         u8         group_id[0x18];
6540
6541         u8         reserved_at_60[0x20];
6542 };
6543
6544 enum {
6545         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6546         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6547         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6548 };
6549
6550 struct mlx5_ifc_create_flow_group_in_bits {
6551         u8         opcode[0x10];
6552         u8         reserved_at_10[0x10];
6553
6554         u8         reserved_at_20[0x10];
6555         u8         op_mod[0x10];
6556
6557         u8         other_vport[0x1];
6558         u8         reserved_at_41[0xf];
6559         u8         vport_number[0x10];
6560
6561         u8         reserved_at_60[0x20];
6562
6563         u8         table_type[0x8];
6564         u8         reserved_at_88[0x18];
6565
6566         u8         reserved_at_a0[0x8];
6567         u8         table_id[0x18];
6568
6569         u8         reserved_at_c0[0x20];
6570
6571         u8         start_flow_index[0x20];
6572
6573         u8         reserved_at_100[0x20];
6574
6575         u8         end_flow_index[0x20];
6576
6577         u8         reserved_at_140[0xa0];
6578
6579         u8         reserved_at_1e0[0x18];
6580         u8         match_criteria_enable[0x8];
6581
6582         struct mlx5_ifc_fte_match_param_bits match_criteria;
6583
6584         u8         reserved_at_1200[0xe00];
6585 };
6586
6587 struct mlx5_ifc_create_eq_out_bits {
6588         u8         status[0x8];
6589         u8         reserved_at_8[0x18];
6590
6591         u8         syndrome[0x20];
6592
6593         u8         reserved_at_40[0x18];
6594         u8         eq_number[0x8];
6595
6596         u8         reserved_at_60[0x20];
6597 };
6598
6599 struct mlx5_ifc_create_eq_in_bits {
6600         u8         opcode[0x10];
6601         u8         reserved_at_10[0x10];
6602
6603         u8         reserved_at_20[0x10];
6604         u8         op_mod[0x10];
6605
6606         u8         reserved_at_40[0x40];
6607
6608         struct mlx5_ifc_eqc_bits eq_context_entry;
6609
6610         u8         reserved_at_280[0x40];
6611
6612         u8         event_bitmask[0x40];
6613
6614         u8         reserved_at_300[0x580];
6615
6616         u8         pas[0][0x40];
6617 };
6618
6619 struct mlx5_ifc_create_dct_out_bits {
6620         u8         status[0x8];
6621         u8         reserved_at_8[0x18];
6622
6623         u8         syndrome[0x20];
6624
6625         u8         reserved_at_40[0x8];
6626         u8         dctn[0x18];
6627
6628         u8         reserved_at_60[0x20];
6629 };
6630
6631 struct mlx5_ifc_create_dct_in_bits {
6632         u8         opcode[0x10];
6633         u8         reserved_at_10[0x10];
6634
6635         u8         reserved_at_20[0x10];
6636         u8         op_mod[0x10];
6637
6638         u8         reserved_at_40[0x40];
6639
6640         struct mlx5_ifc_dctc_bits dct_context_entry;
6641
6642         u8         reserved_at_280[0x180];
6643 };
6644
6645 struct mlx5_ifc_create_cq_out_bits {
6646         u8         status[0x8];
6647         u8         reserved_at_8[0x18];
6648
6649         u8         syndrome[0x20];
6650
6651         u8         reserved_at_40[0x8];
6652         u8         cqn[0x18];
6653
6654         u8         reserved_at_60[0x20];
6655 };
6656
6657 struct mlx5_ifc_create_cq_in_bits {
6658         u8         opcode[0x10];
6659         u8         reserved_at_10[0x10];
6660
6661         u8         reserved_at_20[0x10];
6662         u8         op_mod[0x10];
6663
6664         u8         reserved_at_40[0x40];
6665
6666         struct mlx5_ifc_cqc_bits cq_context;
6667
6668         u8         reserved_at_280[0x600];
6669
6670         u8         pas[0][0x40];
6671 };
6672
6673 struct mlx5_ifc_config_int_moderation_out_bits {
6674         u8         status[0x8];
6675         u8         reserved_at_8[0x18];
6676
6677         u8         syndrome[0x20];
6678
6679         u8         reserved_at_40[0x4];
6680         u8         min_delay[0xc];
6681         u8         int_vector[0x10];
6682
6683         u8         reserved_at_60[0x20];
6684 };
6685
6686 enum {
6687         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6688         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6689 };
6690
6691 struct mlx5_ifc_config_int_moderation_in_bits {
6692         u8         opcode[0x10];
6693         u8         reserved_at_10[0x10];
6694
6695         u8         reserved_at_20[0x10];
6696         u8         op_mod[0x10];
6697
6698         u8         reserved_at_40[0x4];
6699         u8         min_delay[0xc];
6700         u8         int_vector[0x10];
6701
6702         u8         reserved_at_60[0x20];
6703 };
6704
6705 struct mlx5_ifc_attach_to_mcg_out_bits {
6706         u8         status[0x8];
6707         u8         reserved_at_8[0x18];
6708
6709         u8         syndrome[0x20];
6710
6711         u8         reserved_at_40[0x40];
6712 };
6713
6714 struct mlx5_ifc_attach_to_mcg_in_bits {
6715         u8         opcode[0x10];
6716         u8         reserved_at_10[0x10];
6717
6718         u8         reserved_at_20[0x10];
6719         u8         op_mod[0x10];
6720
6721         u8         reserved_at_40[0x8];
6722         u8         qpn[0x18];
6723
6724         u8         reserved_at_60[0x20];
6725
6726         u8         multicast_gid[16][0x8];
6727 };
6728
6729 struct mlx5_ifc_arm_xrq_out_bits {
6730         u8         status[0x8];
6731         u8         reserved_at_8[0x18];
6732
6733         u8         syndrome[0x20];
6734
6735         u8         reserved_at_40[0x40];
6736 };
6737
6738 struct mlx5_ifc_arm_xrq_in_bits {
6739         u8         opcode[0x10];
6740         u8         reserved_at_10[0x10];
6741
6742         u8         reserved_at_20[0x10];
6743         u8         op_mod[0x10];
6744
6745         u8         reserved_at_40[0x8];
6746         u8         xrqn[0x18];
6747
6748         u8         reserved_at_60[0x10];
6749         u8         lwm[0x10];
6750 };
6751
6752 struct mlx5_ifc_arm_xrc_srq_out_bits {
6753         u8         status[0x8];
6754         u8         reserved_at_8[0x18];
6755
6756         u8         syndrome[0x20];
6757
6758         u8         reserved_at_40[0x40];
6759 };
6760
6761 enum {
6762         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6763 };
6764
6765 struct mlx5_ifc_arm_xrc_srq_in_bits {
6766         u8         opcode[0x10];
6767         u8         reserved_at_10[0x10];
6768
6769         u8         reserved_at_20[0x10];
6770         u8         op_mod[0x10];
6771
6772         u8         reserved_at_40[0x8];
6773         u8         xrc_srqn[0x18];
6774
6775         u8         reserved_at_60[0x10];
6776         u8         lwm[0x10];
6777 };
6778
6779 struct mlx5_ifc_arm_rq_out_bits {
6780         u8         status[0x8];
6781         u8         reserved_at_8[0x18];
6782
6783         u8         syndrome[0x20];
6784
6785         u8         reserved_at_40[0x40];
6786 };
6787
6788 enum {
6789         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6790         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6791 };
6792
6793 struct mlx5_ifc_arm_rq_in_bits {
6794         u8         opcode[0x10];
6795         u8         reserved_at_10[0x10];
6796
6797         u8         reserved_at_20[0x10];
6798         u8         op_mod[0x10];
6799
6800         u8         reserved_at_40[0x8];
6801         u8         srq_number[0x18];
6802
6803         u8         reserved_at_60[0x10];
6804         u8         lwm[0x10];
6805 };
6806
6807 struct mlx5_ifc_arm_dct_out_bits {
6808         u8         status[0x8];
6809         u8         reserved_at_8[0x18];
6810
6811         u8         syndrome[0x20];
6812
6813         u8         reserved_at_40[0x40];
6814 };
6815
6816 struct mlx5_ifc_arm_dct_in_bits {
6817         u8         opcode[0x10];
6818         u8         reserved_at_10[0x10];
6819
6820         u8         reserved_at_20[0x10];
6821         u8         op_mod[0x10];
6822
6823         u8         reserved_at_40[0x8];
6824         u8         dct_number[0x18];
6825
6826         u8         reserved_at_60[0x20];
6827 };
6828
6829 struct mlx5_ifc_alloc_xrcd_out_bits {
6830         u8         status[0x8];
6831         u8         reserved_at_8[0x18];
6832
6833         u8         syndrome[0x20];
6834
6835         u8         reserved_at_40[0x8];
6836         u8         xrcd[0x18];
6837
6838         u8         reserved_at_60[0x20];
6839 };
6840
6841 struct mlx5_ifc_alloc_xrcd_in_bits {
6842         u8         opcode[0x10];
6843         u8         reserved_at_10[0x10];
6844
6845         u8         reserved_at_20[0x10];
6846         u8         op_mod[0x10];
6847
6848         u8         reserved_at_40[0x40];
6849 };
6850
6851 struct mlx5_ifc_alloc_uar_out_bits {
6852         u8         status[0x8];
6853         u8         reserved_at_8[0x18];
6854
6855         u8         syndrome[0x20];
6856
6857         u8         reserved_at_40[0x8];
6858         u8         uar[0x18];
6859
6860         u8         reserved_at_60[0x20];
6861 };
6862
6863 struct mlx5_ifc_alloc_uar_in_bits {
6864         u8         opcode[0x10];
6865         u8         reserved_at_10[0x10];
6866
6867         u8         reserved_at_20[0x10];
6868         u8         op_mod[0x10];
6869
6870         u8         reserved_at_40[0x40];
6871 };
6872
6873 struct mlx5_ifc_alloc_transport_domain_out_bits {
6874         u8         status[0x8];
6875         u8         reserved_at_8[0x18];
6876
6877         u8         syndrome[0x20];
6878
6879         u8         reserved_at_40[0x8];
6880         u8         transport_domain[0x18];
6881
6882         u8         reserved_at_60[0x20];
6883 };
6884
6885 struct mlx5_ifc_alloc_transport_domain_in_bits {
6886         u8         opcode[0x10];
6887         u8         reserved_at_10[0x10];
6888
6889         u8         reserved_at_20[0x10];
6890         u8         op_mod[0x10];
6891
6892         u8         reserved_at_40[0x40];
6893 };
6894
6895 struct mlx5_ifc_alloc_q_counter_out_bits {
6896         u8         status[0x8];
6897         u8         reserved_at_8[0x18];
6898
6899         u8         syndrome[0x20];
6900
6901         u8         reserved_at_40[0x18];
6902         u8         counter_set_id[0x8];
6903
6904         u8         reserved_at_60[0x20];
6905 };
6906
6907 struct mlx5_ifc_alloc_q_counter_in_bits {
6908         u8         opcode[0x10];
6909         u8         reserved_at_10[0x10];
6910
6911         u8         reserved_at_20[0x10];
6912         u8         op_mod[0x10];
6913
6914         u8         reserved_at_40[0x40];
6915 };
6916
6917 struct mlx5_ifc_alloc_pd_out_bits {
6918         u8         status[0x8];
6919         u8         reserved_at_8[0x18];
6920
6921         u8         syndrome[0x20];
6922
6923         u8         reserved_at_40[0x8];
6924         u8         pd[0x18];
6925
6926         u8         reserved_at_60[0x20];
6927 };
6928
6929 struct mlx5_ifc_alloc_pd_in_bits {
6930         u8         opcode[0x10];
6931         u8         reserved_at_10[0x10];
6932
6933         u8         reserved_at_20[0x10];
6934         u8         op_mod[0x10];
6935
6936         u8         reserved_at_40[0x40];
6937 };
6938
6939 struct mlx5_ifc_alloc_flow_counter_out_bits {
6940         u8         status[0x8];
6941         u8         reserved_at_8[0x18];
6942
6943         u8         syndrome[0x20];
6944
6945         u8         reserved_at_40[0x10];
6946         u8         flow_counter_id[0x10];
6947
6948         u8         reserved_at_60[0x20];
6949 };
6950
6951 struct mlx5_ifc_alloc_flow_counter_in_bits {
6952         u8         opcode[0x10];
6953         u8         reserved_at_10[0x10];
6954
6955         u8         reserved_at_20[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         reserved_at_40[0x40];
6959 };
6960
6961 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6962         u8         status[0x8];
6963         u8         reserved_at_8[0x18];
6964
6965         u8         syndrome[0x20];
6966
6967         u8         reserved_at_40[0x40];
6968 };
6969
6970 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6971         u8         opcode[0x10];
6972         u8         reserved_at_10[0x10];
6973
6974         u8         reserved_at_20[0x10];
6975         u8         op_mod[0x10];
6976
6977         u8         reserved_at_40[0x20];
6978
6979         u8         reserved_at_60[0x10];
6980         u8         vxlan_udp_port[0x10];
6981 };
6982
6983 struct mlx5_ifc_set_rate_limit_out_bits {
6984         u8         status[0x8];
6985         u8         reserved_at_8[0x18];
6986
6987         u8         syndrome[0x20];
6988
6989         u8         reserved_at_40[0x40];
6990 };
6991
6992 struct mlx5_ifc_set_rate_limit_in_bits {
6993         u8         opcode[0x10];
6994         u8         reserved_at_10[0x10];
6995
6996         u8         reserved_at_20[0x10];
6997         u8         op_mod[0x10];
6998
6999         u8         reserved_at_40[0x10];
7000         u8         rate_limit_index[0x10];
7001
7002         u8         reserved_at_60[0x20];
7003
7004         u8         rate_limit[0x20];
7005 };
7006
7007 struct mlx5_ifc_access_register_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_at_8[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_at_40[0x40];
7014
7015         u8         register_data[0][0x20];
7016 };
7017
7018 enum {
7019         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7020         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7021 };
7022
7023 struct mlx5_ifc_access_register_in_bits {
7024         u8         opcode[0x10];
7025         u8         reserved_at_10[0x10];
7026
7027         u8         reserved_at_20[0x10];
7028         u8         op_mod[0x10];
7029
7030         u8         reserved_at_40[0x10];
7031         u8         register_id[0x10];
7032
7033         u8         argument[0x20];
7034
7035         u8         register_data[0][0x20];
7036 };
7037
7038 struct mlx5_ifc_sltp_reg_bits {
7039         u8         status[0x4];
7040         u8         version[0x4];
7041         u8         local_port[0x8];
7042         u8         pnat[0x2];
7043         u8         reserved_at_12[0x2];
7044         u8         lane[0x4];
7045         u8         reserved_at_18[0x8];
7046
7047         u8         reserved_at_20[0x20];
7048
7049         u8         reserved_at_40[0x7];
7050         u8         polarity[0x1];
7051         u8         ob_tap0[0x8];
7052         u8         ob_tap1[0x8];
7053         u8         ob_tap2[0x8];
7054
7055         u8         reserved_at_60[0xc];
7056         u8         ob_preemp_mode[0x4];
7057         u8         ob_reg[0x8];
7058         u8         ob_bias[0x8];
7059
7060         u8         reserved_at_80[0x20];
7061 };
7062
7063 struct mlx5_ifc_slrg_reg_bits {
7064         u8         status[0x4];
7065         u8         version[0x4];
7066         u8         local_port[0x8];
7067         u8         pnat[0x2];
7068         u8         reserved_at_12[0x2];
7069         u8         lane[0x4];
7070         u8         reserved_at_18[0x8];
7071
7072         u8         time_to_link_up[0x10];
7073         u8         reserved_at_30[0xc];
7074         u8         grade_lane_speed[0x4];
7075
7076         u8         grade_version[0x8];
7077         u8         grade[0x18];
7078
7079         u8         reserved_at_60[0x4];
7080         u8         height_grade_type[0x4];
7081         u8         height_grade[0x18];
7082
7083         u8         height_dz[0x10];
7084         u8         height_dv[0x10];
7085
7086         u8         reserved_at_a0[0x10];
7087         u8         height_sigma[0x10];
7088
7089         u8         reserved_at_c0[0x20];
7090
7091         u8         reserved_at_e0[0x4];
7092         u8         phase_grade_type[0x4];
7093         u8         phase_grade[0x18];
7094
7095         u8         reserved_at_100[0x8];
7096         u8         phase_eo_pos[0x8];
7097         u8         reserved_at_110[0x8];
7098         u8         phase_eo_neg[0x8];
7099
7100         u8         ffe_set_tested[0x10];
7101         u8         test_errors_per_lane[0x10];
7102 };
7103
7104 struct mlx5_ifc_pvlc_reg_bits {
7105         u8         reserved_at_0[0x8];
7106         u8         local_port[0x8];
7107         u8         reserved_at_10[0x10];
7108
7109         u8         reserved_at_20[0x1c];
7110         u8         vl_hw_cap[0x4];
7111
7112         u8         reserved_at_40[0x1c];
7113         u8         vl_admin[0x4];
7114
7115         u8         reserved_at_60[0x1c];
7116         u8         vl_operational[0x4];
7117 };
7118
7119 struct mlx5_ifc_pude_reg_bits {
7120         u8         swid[0x8];
7121         u8         local_port[0x8];
7122         u8         reserved_at_10[0x4];
7123         u8         admin_status[0x4];
7124         u8         reserved_at_18[0x4];
7125         u8         oper_status[0x4];
7126
7127         u8         reserved_at_20[0x60];
7128 };
7129
7130 struct mlx5_ifc_ptys_reg_bits {
7131         u8         reserved_at_0[0x1];
7132         u8         an_disable_admin[0x1];
7133         u8         an_disable_cap[0x1];
7134         u8         reserved_at_3[0x5];
7135         u8         local_port[0x8];
7136         u8         reserved_at_10[0xd];
7137         u8         proto_mask[0x3];
7138
7139         u8         an_status[0x4];
7140         u8         reserved_at_24[0x3c];
7141
7142         u8         eth_proto_capability[0x20];
7143
7144         u8         ib_link_width_capability[0x10];
7145         u8         ib_proto_capability[0x10];
7146
7147         u8         reserved_at_a0[0x20];
7148
7149         u8         eth_proto_admin[0x20];
7150
7151         u8         ib_link_width_admin[0x10];
7152         u8         ib_proto_admin[0x10];
7153
7154         u8         reserved_at_100[0x20];
7155
7156         u8         eth_proto_oper[0x20];
7157
7158         u8         ib_link_width_oper[0x10];
7159         u8         ib_proto_oper[0x10];
7160
7161         u8         reserved_at_160[0x20];
7162
7163         u8         eth_proto_lp_advertise[0x20];
7164
7165         u8         reserved_at_1a0[0x60];
7166 };
7167
7168 struct mlx5_ifc_mlcr_reg_bits {
7169         u8         reserved_at_0[0x8];
7170         u8         local_port[0x8];
7171         u8         reserved_at_10[0x20];
7172
7173         u8         beacon_duration[0x10];
7174         u8         reserved_at_40[0x10];
7175
7176         u8         beacon_remain[0x10];
7177 };
7178
7179 struct mlx5_ifc_ptas_reg_bits {
7180         u8         reserved_at_0[0x20];
7181
7182         u8         algorithm_options[0x10];
7183         u8         reserved_at_30[0x4];
7184         u8         repetitions_mode[0x4];
7185         u8         num_of_repetitions[0x8];
7186
7187         u8         grade_version[0x8];
7188         u8         height_grade_type[0x4];
7189         u8         phase_grade_type[0x4];
7190         u8         height_grade_weight[0x8];
7191         u8         phase_grade_weight[0x8];
7192
7193         u8         gisim_measure_bits[0x10];
7194         u8         adaptive_tap_measure_bits[0x10];
7195
7196         u8         ber_bath_high_error_threshold[0x10];
7197         u8         ber_bath_mid_error_threshold[0x10];
7198
7199         u8         ber_bath_low_error_threshold[0x10];
7200         u8         one_ratio_high_threshold[0x10];
7201
7202         u8         one_ratio_high_mid_threshold[0x10];
7203         u8         one_ratio_low_mid_threshold[0x10];
7204
7205         u8         one_ratio_low_threshold[0x10];
7206         u8         ndeo_error_threshold[0x10];
7207
7208         u8         mixer_offset_step_size[0x10];
7209         u8         reserved_at_110[0x8];
7210         u8         mix90_phase_for_voltage_bath[0x8];
7211
7212         u8         mixer_offset_start[0x10];
7213         u8         mixer_offset_end[0x10];
7214
7215         u8         reserved_at_140[0x15];
7216         u8         ber_test_time[0xb];
7217 };
7218
7219 struct mlx5_ifc_pspa_reg_bits {
7220         u8         swid[0x8];
7221         u8         local_port[0x8];
7222         u8         sub_port[0x8];
7223         u8         reserved_at_18[0x8];
7224
7225         u8         reserved_at_20[0x20];
7226 };
7227
7228 struct mlx5_ifc_pqdr_reg_bits {
7229         u8         reserved_at_0[0x8];
7230         u8         local_port[0x8];
7231         u8         reserved_at_10[0x5];
7232         u8         prio[0x3];
7233         u8         reserved_at_18[0x6];
7234         u8         mode[0x2];
7235
7236         u8         reserved_at_20[0x20];
7237
7238         u8         reserved_at_40[0x10];
7239         u8         min_threshold[0x10];
7240
7241         u8         reserved_at_60[0x10];
7242         u8         max_threshold[0x10];
7243
7244         u8         reserved_at_80[0x10];
7245         u8         mark_probability_denominator[0x10];
7246
7247         u8         reserved_at_a0[0x60];
7248 };
7249
7250 struct mlx5_ifc_ppsc_reg_bits {
7251         u8         reserved_at_0[0x8];
7252         u8         local_port[0x8];
7253         u8         reserved_at_10[0x10];
7254
7255         u8         reserved_at_20[0x60];
7256
7257         u8         reserved_at_80[0x1c];
7258         u8         wrps_admin[0x4];
7259
7260         u8         reserved_at_a0[0x1c];
7261         u8         wrps_status[0x4];
7262
7263         u8         reserved_at_c0[0x8];
7264         u8         up_threshold[0x8];
7265         u8         reserved_at_d0[0x8];
7266         u8         down_threshold[0x8];
7267
7268         u8         reserved_at_e0[0x20];
7269
7270         u8         reserved_at_100[0x1c];
7271         u8         srps_admin[0x4];
7272
7273         u8         reserved_at_120[0x1c];
7274         u8         srps_status[0x4];
7275
7276         u8         reserved_at_140[0x40];
7277 };
7278
7279 struct mlx5_ifc_pplr_reg_bits {
7280         u8         reserved_at_0[0x8];
7281         u8         local_port[0x8];
7282         u8         reserved_at_10[0x10];
7283
7284         u8         reserved_at_20[0x8];
7285         u8         lb_cap[0x8];
7286         u8         reserved_at_30[0x8];
7287         u8         lb_en[0x8];
7288 };
7289
7290 struct mlx5_ifc_pplm_reg_bits {
7291         u8         reserved_at_0[0x8];
7292         u8         local_port[0x8];
7293         u8         reserved_at_10[0x10];
7294
7295         u8         reserved_at_20[0x20];
7296
7297         u8         port_profile_mode[0x8];
7298         u8         static_port_profile[0x8];
7299         u8         active_port_profile[0x8];
7300         u8         reserved_at_58[0x8];
7301
7302         u8         retransmission_active[0x8];
7303         u8         fec_mode_active[0x18];
7304
7305         u8         reserved_at_80[0x20];
7306 };
7307
7308 struct mlx5_ifc_ppcnt_reg_bits {
7309         u8         swid[0x8];
7310         u8         local_port[0x8];
7311         u8         pnat[0x2];
7312         u8         reserved_at_12[0x8];
7313         u8         grp[0x6];
7314
7315         u8         clr[0x1];
7316         u8         reserved_at_21[0x1c];
7317         u8         prio_tc[0x3];
7318
7319         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7320 };
7321
7322 struct mlx5_ifc_mpcnt_reg_bits {
7323         u8         reserved_at_0[0x8];
7324         u8         pcie_index[0x8];
7325         u8         reserved_at_10[0xa];
7326         u8         grp[0x6];
7327
7328         u8         clr[0x1];
7329         u8         reserved_at_21[0x1f];
7330
7331         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7332 };
7333
7334 struct mlx5_ifc_ppad_reg_bits {
7335         u8         reserved_at_0[0x3];
7336         u8         single_mac[0x1];
7337         u8         reserved_at_4[0x4];
7338         u8         local_port[0x8];
7339         u8         mac_47_32[0x10];
7340
7341         u8         mac_31_0[0x20];
7342
7343         u8         reserved_at_40[0x40];
7344 };
7345
7346 struct mlx5_ifc_pmtu_reg_bits {
7347         u8         reserved_at_0[0x8];
7348         u8         local_port[0x8];
7349         u8         reserved_at_10[0x10];
7350
7351         u8         max_mtu[0x10];
7352         u8         reserved_at_30[0x10];
7353
7354         u8         admin_mtu[0x10];
7355         u8         reserved_at_50[0x10];
7356
7357         u8         oper_mtu[0x10];
7358         u8         reserved_at_70[0x10];
7359 };
7360
7361 struct mlx5_ifc_pmpr_reg_bits {
7362         u8         reserved_at_0[0x8];
7363         u8         module[0x8];
7364         u8         reserved_at_10[0x10];
7365
7366         u8         reserved_at_20[0x18];
7367         u8         attenuation_5g[0x8];
7368
7369         u8         reserved_at_40[0x18];
7370         u8         attenuation_7g[0x8];
7371
7372         u8         reserved_at_60[0x18];
7373         u8         attenuation_12g[0x8];
7374 };
7375
7376 struct mlx5_ifc_pmpe_reg_bits {
7377         u8         reserved_at_0[0x8];
7378         u8         module[0x8];
7379         u8         reserved_at_10[0xc];
7380         u8         module_status[0x4];
7381
7382         u8         reserved_at_20[0x60];
7383 };
7384
7385 struct mlx5_ifc_pmpc_reg_bits {
7386         u8         module_state_updated[32][0x8];
7387 };
7388
7389 struct mlx5_ifc_pmlpn_reg_bits {
7390         u8         reserved_at_0[0x4];
7391         u8         mlpn_status[0x4];
7392         u8         local_port[0x8];
7393         u8         reserved_at_10[0x10];
7394
7395         u8         e[0x1];
7396         u8         reserved_at_21[0x1f];
7397 };
7398
7399 struct mlx5_ifc_pmlp_reg_bits {
7400         u8         rxtx[0x1];
7401         u8         reserved_at_1[0x7];
7402         u8         local_port[0x8];
7403         u8         reserved_at_10[0x8];
7404         u8         width[0x8];
7405
7406         u8         lane0_module_mapping[0x20];
7407
7408         u8         lane1_module_mapping[0x20];
7409
7410         u8         lane2_module_mapping[0x20];
7411
7412         u8         lane3_module_mapping[0x20];
7413
7414         u8         reserved_at_a0[0x160];
7415 };
7416
7417 struct mlx5_ifc_pmaos_reg_bits {
7418         u8         reserved_at_0[0x8];
7419         u8         module[0x8];
7420         u8         reserved_at_10[0x4];
7421         u8         admin_status[0x4];
7422         u8         reserved_at_18[0x4];
7423         u8         oper_status[0x4];
7424
7425         u8         ase[0x1];
7426         u8         ee[0x1];
7427         u8         reserved_at_22[0x1c];
7428         u8         e[0x2];
7429
7430         u8         reserved_at_40[0x40];
7431 };
7432
7433 struct mlx5_ifc_plpc_reg_bits {
7434         u8         reserved_at_0[0x4];
7435         u8         profile_id[0xc];
7436         u8         reserved_at_10[0x4];
7437         u8         proto_mask[0x4];
7438         u8         reserved_at_18[0x8];
7439
7440         u8         reserved_at_20[0x10];
7441         u8         lane_speed[0x10];
7442
7443         u8         reserved_at_40[0x17];
7444         u8         lpbf[0x1];
7445         u8         fec_mode_policy[0x8];
7446
7447         u8         retransmission_capability[0x8];
7448         u8         fec_mode_capability[0x18];
7449
7450         u8         retransmission_support_admin[0x8];
7451         u8         fec_mode_support_admin[0x18];
7452
7453         u8         retransmission_request_admin[0x8];
7454         u8         fec_mode_request_admin[0x18];
7455
7456         u8         reserved_at_c0[0x80];
7457 };
7458
7459 struct mlx5_ifc_plib_reg_bits {
7460         u8         reserved_at_0[0x8];
7461         u8         local_port[0x8];
7462         u8         reserved_at_10[0x8];
7463         u8         ib_port[0x8];
7464
7465         u8         reserved_at_20[0x60];
7466 };
7467
7468 struct mlx5_ifc_plbf_reg_bits {
7469         u8         reserved_at_0[0x8];
7470         u8         local_port[0x8];
7471         u8         reserved_at_10[0xd];
7472         u8         lbf_mode[0x3];
7473
7474         u8         reserved_at_20[0x20];
7475 };
7476
7477 struct mlx5_ifc_pipg_reg_bits {
7478         u8         reserved_at_0[0x8];
7479         u8         local_port[0x8];
7480         u8         reserved_at_10[0x10];
7481
7482         u8         dic[0x1];
7483         u8         reserved_at_21[0x19];
7484         u8         ipg[0x4];
7485         u8         reserved_at_3e[0x2];
7486 };
7487
7488 struct mlx5_ifc_pifr_reg_bits {
7489         u8         reserved_at_0[0x8];
7490         u8         local_port[0x8];
7491         u8         reserved_at_10[0x10];
7492
7493         u8         reserved_at_20[0xe0];
7494
7495         u8         port_filter[8][0x20];
7496
7497         u8         port_filter_update_en[8][0x20];
7498 };
7499
7500 struct mlx5_ifc_pfcc_reg_bits {
7501         u8         reserved_at_0[0x8];
7502         u8         local_port[0x8];
7503         u8         reserved_at_10[0x10];
7504
7505         u8         ppan[0x4];
7506         u8         reserved_at_24[0x4];
7507         u8         prio_mask_tx[0x8];
7508         u8         reserved_at_30[0x8];
7509         u8         prio_mask_rx[0x8];
7510
7511         u8         pptx[0x1];
7512         u8         aptx[0x1];
7513         u8         reserved_at_42[0x6];
7514         u8         pfctx[0x8];
7515         u8         reserved_at_50[0x10];
7516
7517         u8         pprx[0x1];
7518         u8         aprx[0x1];
7519         u8         reserved_at_62[0x6];
7520         u8         pfcrx[0x8];
7521         u8         reserved_at_70[0x10];
7522
7523         u8         reserved_at_80[0x80];
7524 };
7525
7526 struct mlx5_ifc_pelc_reg_bits {
7527         u8         op[0x4];
7528         u8         reserved_at_4[0x4];
7529         u8         local_port[0x8];
7530         u8         reserved_at_10[0x10];
7531
7532         u8         op_admin[0x8];
7533         u8         op_capability[0x8];
7534         u8         op_request[0x8];
7535         u8         op_active[0x8];
7536
7537         u8         admin[0x40];
7538
7539         u8         capability[0x40];
7540
7541         u8         request[0x40];
7542
7543         u8         active[0x40];
7544
7545         u8         reserved_at_140[0x80];
7546 };
7547
7548 struct mlx5_ifc_peir_reg_bits {
7549         u8         reserved_at_0[0x8];
7550         u8         local_port[0x8];
7551         u8         reserved_at_10[0x10];
7552
7553         u8         reserved_at_20[0xc];
7554         u8         error_count[0x4];
7555         u8         reserved_at_30[0x10];
7556
7557         u8         reserved_at_40[0xc];
7558         u8         lane[0x4];
7559         u8         reserved_at_50[0x8];
7560         u8         error_type[0x8];
7561 };
7562
7563 struct mlx5_ifc_pcam_enhanced_features_bits {
7564         u8         reserved_at_0[0x7e];
7565
7566         u8         ppcnt_discard_group[0x1];
7567         u8         ppcnt_statistical_group[0x1];
7568 };
7569
7570 struct mlx5_ifc_pcam_reg_bits {
7571         u8         reserved_at_0[0x8];
7572         u8         feature_group[0x8];
7573         u8         reserved_at_10[0x8];
7574         u8         access_reg_group[0x8];
7575
7576         u8         reserved_at_20[0x20];
7577
7578         union {
7579                 u8         reserved_at_0[0x80];
7580         } port_access_reg_cap_mask;
7581
7582         u8         reserved_at_c0[0x80];
7583
7584         union {
7585                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7586                 u8         reserved_at_0[0x80];
7587         } feature_cap_mask;
7588
7589         u8         reserved_at_1c0[0xc0];
7590 };
7591
7592 struct mlx5_ifc_mcam_enhanced_features_bits {
7593         u8         reserved_at_0[0x7f];
7594
7595         u8         pcie_performance_group[0x1];
7596 };
7597
7598 struct mlx5_ifc_mcam_reg_bits {
7599         u8         reserved_at_0[0x8];
7600         u8         feature_group[0x8];
7601         u8         reserved_at_10[0x8];
7602         u8         access_reg_group[0x8];
7603
7604         u8         reserved_at_20[0x20];
7605
7606         union {
7607                 u8         reserved_at_0[0x80];
7608         } mng_access_reg_cap_mask;
7609
7610         u8         reserved_at_c0[0x80];
7611
7612         union {
7613                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7614                 u8         reserved_at_0[0x80];
7615         } mng_feature_cap_mask;
7616
7617         u8         reserved_at_1c0[0x80];
7618 };
7619
7620 struct mlx5_ifc_pcap_reg_bits {
7621         u8         reserved_at_0[0x8];
7622         u8         local_port[0x8];
7623         u8         reserved_at_10[0x10];
7624
7625         u8         port_capability_mask[4][0x20];
7626 };
7627
7628 struct mlx5_ifc_paos_reg_bits {
7629         u8         swid[0x8];
7630         u8         local_port[0x8];
7631         u8         reserved_at_10[0x4];
7632         u8         admin_status[0x4];
7633         u8         reserved_at_18[0x4];
7634         u8         oper_status[0x4];
7635
7636         u8         ase[0x1];
7637         u8         ee[0x1];
7638         u8         reserved_at_22[0x1c];
7639         u8         e[0x2];
7640
7641         u8         reserved_at_40[0x40];
7642 };
7643
7644 struct mlx5_ifc_pamp_reg_bits {
7645         u8         reserved_at_0[0x8];
7646         u8         opamp_group[0x8];
7647         u8         reserved_at_10[0xc];
7648         u8         opamp_group_type[0x4];
7649
7650         u8         start_index[0x10];
7651         u8         reserved_at_30[0x4];
7652         u8         num_of_indices[0xc];
7653
7654         u8         index_data[18][0x10];
7655 };
7656
7657 struct mlx5_ifc_pcmr_reg_bits {
7658         u8         reserved_at_0[0x8];
7659         u8         local_port[0x8];
7660         u8         reserved_at_10[0x2e];
7661         u8         fcs_cap[0x1];
7662         u8         reserved_at_3f[0x1f];
7663         u8         fcs_chk[0x1];
7664         u8         reserved_at_5f[0x1];
7665 };
7666
7667 struct mlx5_ifc_lane_2_module_mapping_bits {
7668         u8         reserved_at_0[0x6];
7669         u8         rx_lane[0x2];
7670         u8         reserved_at_8[0x6];
7671         u8         tx_lane[0x2];
7672         u8         reserved_at_10[0x8];
7673         u8         module[0x8];
7674 };
7675
7676 struct mlx5_ifc_bufferx_reg_bits {
7677         u8         reserved_at_0[0x6];
7678         u8         lossy[0x1];
7679         u8         epsb[0x1];
7680         u8         reserved_at_8[0xc];
7681         u8         size[0xc];
7682
7683         u8         xoff_threshold[0x10];
7684         u8         xon_threshold[0x10];
7685 };
7686
7687 struct mlx5_ifc_set_node_in_bits {
7688         u8         node_description[64][0x8];
7689 };
7690
7691 struct mlx5_ifc_register_power_settings_bits {
7692         u8         reserved_at_0[0x18];
7693         u8         power_settings_level[0x8];
7694
7695         u8         reserved_at_20[0x60];
7696 };
7697
7698 struct mlx5_ifc_register_host_endianness_bits {
7699         u8         he[0x1];
7700         u8         reserved_at_1[0x1f];
7701
7702         u8         reserved_at_20[0x60];
7703 };
7704
7705 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7706         u8         reserved_at_0[0x20];
7707
7708         u8         mkey[0x20];
7709
7710         u8         addressh_63_32[0x20];
7711
7712         u8         addressl_31_0[0x20];
7713 };
7714
7715 struct mlx5_ifc_ud_adrs_vector_bits {
7716         u8         dc_key[0x40];
7717
7718         u8         ext[0x1];
7719         u8         reserved_at_41[0x7];
7720         u8         destination_qp_dct[0x18];
7721
7722         u8         static_rate[0x4];
7723         u8         sl_eth_prio[0x4];
7724         u8         fl[0x1];
7725         u8         mlid[0x7];
7726         u8         rlid_udp_sport[0x10];
7727
7728         u8         reserved_at_80[0x20];
7729
7730         u8         rmac_47_16[0x20];
7731
7732         u8         rmac_15_0[0x10];
7733         u8         tclass[0x8];
7734         u8         hop_limit[0x8];
7735
7736         u8         reserved_at_e0[0x1];
7737         u8         grh[0x1];
7738         u8         reserved_at_e2[0x2];
7739         u8         src_addr_index[0x8];
7740         u8         flow_label[0x14];
7741
7742         u8         rgid_rip[16][0x8];
7743 };
7744
7745 struct mlx5_ifc_pages_req_event_bits {
7746         u8         reserved_at_0[0x10];
7747         u8         function_id[0x10];
7748
7749         u8         num_pages[0x20];
7750
7751         u8         reserved_at_40[0xa0];
7752 };
7753
7754 struct mlx5_ifc_eqe_bits {
7755         u8         reserved_at_0[0x8];
7756         u8         event_type[0x8];
7757         u8         reserved_at_10[0x8];
7758         u8         event_sub_type[0x8];
7759
7760         u8         reserved_at_20[0xe0];
7761
7762         union mlx5_ifc_event_auto_bits event_data;
7763
7764         u8         reserved_at_1e0[0x10];
7765         u8         signature[0x8];
7766         u8         reserved_at_1f8[0x7];
7767         u8         owner[0x1];
7768 };
7769
7770 enum {
7771         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7772 };
7773
7774 struct mlx5_ifc_cmd_queue_entry_bits {
7775         u8         type[0x8];
7776         u8         reserved_at_8[0x18];
7777
7778         u8         input_length[0x20];
7779
7780         u8         input_mailbox_pointer_63_32[0x20];
7781
7782         u8         input_mailbox_pointer_31_9[0x17];
7783         u8         reserved_at_77[0x9];
7784
7785         u8         command_input_inline_data[16][0x8];
7786
7787         u8         command_output_inline_data[16][0x8];
7788
7789         u8         output_mailbox_pointer_63_32[0x20];
7790
7791         u8         output_mailbox_pointer_31_9[0x17];
7792         u8         reserved_at_1b7[0x9];
7793
7794         u8         output_length[0x20];
7795
7796         u8         token[0x8];
7797         u8         signature[0x8];
7798         u8         reserved_at_1f0[0x8];
7799         u8         status[0x7];
7800         u8         ownership[0x1];
7801 };
7802
7803 struct mlx5_ifc_cmd_out_bits {
7804         u8         status[0x8];
7805         u8         reserved_at_8[0x18];
7806
7807         u8         syndrome[0x20];
7808
7809         u8         command_output[0x20];
7810 };
7811
7812 struct mlx5_ifc_cmd_in_bits {
7813         u8         opcode[0x10];
7814         u8         reserved_at_10[0x10];
7815
7816         u8         reserved_at_20[0x10];
7817         u8         op_mod[0x10];
7818
7819         u8         command[0][0x20];
7820 };
7821
7822 struct mlx5_ifc_cmd_if_box_bits {
7823         u8         mailbox_data[512][0x8];
7824
7825         u8         reserved_at_1000[0x180];
7826
7827         u8         next_pointer_63_32[0x20];
7828
7829         u8         next_pointer_31_10[0x16];
7830         u8         reserved_at_11b6[0xa];
7831
7832         u8         block_number[0x20];
7833
7834         u8         reserved_at_11e0[0x8];
7835         u8         token[0x8];
7836         u8         ctrl_signature[0x8];
7837         u8         signature[0x8];
7838 };
7839
7840 struct mlx5_ifc_mtt_bits {
7841         u8         ptag_63_32[0x20];
7842
7843         u8         ptag_31_8[0x18];
7844         u8         reserved_at_38[0x6];
7845         u8         wr_en[0x1];
7846         u8         rd_en[0x1];
7847 };
7848
7849 struct mlx5_ifc_query_wol_rol_out_bits {
7850         u8         status[0x8];
7851         u8         reserved_at_8[0x18];
7852
7853         u8         syndrome[0x20];
7854
7855         u8         reserved_at_40[0x10];
7856         u8         rol_mode[0x8];
7857         u8         wol_mode[0x8];
7858
7859         u8         reserved_at_60[0x20];
7860 };
7861
7862 struct mlx5_ifc_query_wol_rol_in_bits {
7863         u8         opcode[0x10];
7864         u8         reserved_at_10[0x10];
7865
7866         u8         reserved_at_20[0x10];
7867         u8         op_mod[0x10];
7868
7869         u8         reserved_at_40[0x40];
7870 };
7871
7872 struct mlx5_ifc_set_wol_rol_out_bits {
7873         u8         status[0x8];
7874         u8         reserved_at_8[0x18];
7875
7876         u8         syndrome[0x20];
7877
7878         u8         reserved_at_40[0x40];
7879 };
7880
7881 struct mlx5_ifc_set_wol_rol_in_bits {
7882         u8         opcode[0x10];
7883         u8         reserved_at_10[0x10];
7884
7885         u8         reserved_at_20[0x10];
7886         u8         op_mod[0x10];
7887
7888         u8         rol_mode_valid[0x1];
7889         u8         wol_mode_valid[0x1];
7890         u8         reserved_at_42[0xe];
7891         u8         rol_mode[0x8];
7892         u8         wol_mode[0x8];
7893
7894         u8         reserved_at_60[0x20];
7895 };
7896
7897 enum {
7898         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7899         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7900         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7901 };
7902
7903 enum {
7904         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7905         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7906         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7907 };
7908
7909 enum {
7910         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7911         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7912         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7913         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7914         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7915         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7916         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7917         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7918         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7919         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7920         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7921 };
7922
7923 struct mlx5_ifc_initial_seg_bits {
7924         u8         fw_rev_minor[0x10];
7925         u8         fw_rev_major[0x10];
7926
7927         u8         cmd_interface_rev[0x10];
7928         u8         fw_rev_subminor[0x10];
7929
7930         u8         reserved_at_40[0x40];
7931
7932         u8         cmdq_phy_addr_63_32[0x20];
7933
7934         u8         cmdq_phy_addr_31_12[0x14];
7935         u8         reserved_at_b4[0x2];
7936         u8         nic_interface[0x2];
7937         u8         log_cmdq_size[0x4];
7938         u8         log_cmdq_stride[0x4];
7939
7940         u8         command_doorbell_vector[0x20];
7941
7942         u8         reserved_at_e0[0xf00];
7943
7944         u8         initializing[0x1];
7945         u8         reserved_at_fe1[0x4];
7946         u8         nic_interface_supported[0x3];
7947         u8         reserved_at_fe8[0x18];
7948
7949         struct mlx5_ifc_health_buffer_bits health_buffer;
7950
7951         u8         no_dram_nic_offset[0x20];
7952
7953         u8         reserved_at_1220[0x6e40];
7954
7955         u8         reserved_at_8060[0x1f];
7956         u8         clear_int[0x1];
7957
7958         u8         health_syndrome[0x8];
7959         u8         health_counter[0x18];
7960
7961         u8         reserved_at_80a0[0x17fc0];
7962 };
7963
7964 struct mlx5_ifc_mtpps_reg_bits {
7965         u8         reserved_at_0[0xc];
7966         u8         cap_number_of_pps_pins[0x4];
7967         u8         reserved_at_10[0x4];
7968         u8         cap_max_num_of_pps_in_pins[0x4];
7969         u8         reserved_at_18[0x4];
7970         u8         cap_max_num_of_pps_out_pins[0x4];
7971
7972         u8         reserved_at_20[0x24];
7973         u8         cap_pin_3_mode[0x4];
7974         u8         reserved_at_48[0x4];
7975         u8         cap_pin_2_mode[0x4];
7976         u8         reserved_at_50[0x4];
7977         u8         cap_pin_1_mode[0x4];
7978         u8         reserved_at_58[0x4];
7979         u8         cap_pin_0_mode[0x4];
7980
7981         u8         reserved_at_60[0x4];
7982         u8         cap_pin_7_mode[0x4];
7983         u8         reserved_at_68[0x4];
7984         u8         cap_pin_6_mode[0x4];
7985         u8         reserved_at_70[0x4];
7986         u8         cap_pin_5_mode[0x4];
7987         u8         reserved_at_78[0x4];
7988         u8         cap_pin_4_mode[0x4];
7989
7990         u8         reserved_at_80[0x80];
7991
7992         u8         enable[0x1];
7993         u8         reserved_at_101[0xb];
7994         u8         pattern[0x4];
7995         u8         reserved_at_110[0x4];
7996         u8         pin_mode[0x4];
7997         u8         pin[0x8];
7998
7999         u8         reserved_at_120[0x20];
8000
8001         u8         time_stamp[0x40];
8002
8003         u8         out_pulse_duration[0x10];
8004         u8         out_periodic_adjustment[0x10];
8005
8006         u8         reserved_at_1a0[0x60];
8007 };
8008
8009 struct mlx5_ifc_mtppse_reg_bits {
8010         u8         reserved_at_0[0x18];
8011         u8         pin[0x8];
8012         u8         event_arm[0x1];
8013         u8         reserved_at_21[0x1b];
8014         u8         event_generation_mode[0x4];
8015         u8         reserved_at_40[0x40];
8016 };
8017
8018 union mlx5_ifc_ports_control_registers_document_bits {
8019         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8020         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8021         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8022         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8023         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8024         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8025         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8026         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8027         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8028         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8029         struct mlx5_ifc_paos_reg_bits paos_reg;
8030         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8031         struct mlx5_ifc_peir_reg_bits peir_reg;
8032         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8033         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8034         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8035         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8036         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8037         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8038         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8039         struct mlx5_ifc_plib_reg_bits plib_reg;
8040         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8041         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8042         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8043         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8044         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8045         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8046         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8047         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8048         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8049         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8050         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8051         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8052         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8053         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8054         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8055         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8056         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8057         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8058         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8059         struct mlx5_ifc_pude_reg_bits pude_reg;
8060         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8061         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8062         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8063         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8064         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8065         u8         reserved_at_0[0x60e0];
8066 };
8067
8068 union mlx5_ifc_debug_enhancements_document_bits {
8069         struct mlx5_ifc_health_buffer_bits health_buffer;
8070         u8         reserved_at_0[0x200];
8071 };
8072
8073 union mlx5_ifc_uplink_pci_interface_document_bits {
8074         struct mlx5_ifc_initial_seg_bits initial_seg;
8075         u8         reserved_at_0[0x20060];
8076 };
8077
8078 struct mlx5_ifc_set_flow_table_root_out_bits {
8079         u8         status[0x8];
8080         u8         reserved_at_8[0x18];
8081
8082         u8         syndrome[0x20];
8083
8084         u8         reserved_at_40[0x40];
8085 };
8086
8087 struct mlx5_ifc_set_flow_table_root_in_bits {
8088         u8         opcode[0x10];
8089         u8         reserved_at_10[0x10];
8090
8091         u8         reserved_at_20[0x10];
8092         u8         op_mod[0x10];
8093
8094         u8         other_vport[0x1];
8095         u8         reserved_at_41[0xf];
8096         u8         vport_number[0x10];
8097
8098         u8         reserved_at_60[0x20];
8099
8100         u8         table_type[0x8];
8101         u8         reserved_at_88[0x18];
8102
8103         u8         reserved_at_a0[0x8];
8104         u8         table_id[0x18];
8105
8106         u8         reserved_at_c0[0x140];
8107 };
8108
8109 enum {
8110         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8111         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8112 };
8113
8114 struct mlx5_ifc_modify_flow_table_out_bits {
8115         u8         status[0x8];
8116         u8         reserved_at_8[0x18];
8117
8118         u8         syndrome[0x20];
8119
8120         u8         reserved_at_40[0x40];
8121 };
8122
8123 struct mlx5_ifc_modify_flow_table_in_bits {
8124         u8         opcode[0x10];
8125         u8         reserved_at_10[0x10];
8126
8127         u8         reserved_at_20[0x10];
8128         u8         op_mod[0x10];
8129
8130         u8         other_vport[0x1];
8131         u8         reserved_at_41[0xf];
8132         u8         vport_number[0x10];
8133
8134         u8         reserved_at_60[0x10];
8135         u8         modify_field_select[0x10];
8136
8137         u8         table_type[0x8];
8138         u8         reserved_at_88[0x18];
8139
8140         u8         reserved_at_a0[0x8];
8141         u8         table_id[0x18];
8142
8143         u8         reserved_at_c0[0x4];
8144         u8         table_miss_mode[0x4];
8145         u8         reserved_at_c8[0x18];
8146
8147         u8         reserved_at_e0[0x8];
8148         u8         table_miss_id[0x18];
8149
8150         u8         reserved_at_100[0x8];
8151         u8         lag_master_next_table_id[0x18];
8152
8153         u8         reserved_at_120[0x80];
8154 };
8155
8156 struct mlx5_ifc_ets_tcn_config_reg_bits {
8157         u8         g[0x1];
8158         u8         b[0x1];
8159         u8         r[0x1];
8160         u8         reserved_at_3[0x9];
8161         u8         group[0x4];
8162         u8         reserved_at_10[0x9];
8163         u8         bw_allocation[0x7];
8164
8165         u8         reserved_at_20[0xc];
8166         u8         max_bw_units[0x4];
8167         u8         reserved_at_30[0x8];
8168         u8         max_bw_value[0x8];
8169 };
8170
8171 struct mlx5_ifc_ets_global_config_reg_bits {
8172         u8         reserved_at_0[0x2];
8173         u8         r[0x1];
8174         u8         reserved_at_3[0x1d];
8175
8176         u8         reserved_at_20[0xc];
8177         u8         max_bw_units[0x4];
8178         u8         reserved_at_30[0x8];
8179         u8         max_bw_value[0x8];
8180 };
8181
8182 struct mlx5_ifc_qetc_reg_bits {
8183         u8                                         reserved_at_0[0x8];
8184         u8                                         port_number[0x8];
8185         u8                                         reserved_at_10[0x30];
8186
8187         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8188         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8189 };
8190
8191 struct mlx5_ifc_qtct_reg_bits {
8192         u8         reserved_at_0[0x8];
8193         u8         port_number[0x8];
8194         u8         reserved_at_10[0xd];
8195         u8         prio[0x3];
8196
8197         u8         reserved_at_20[0x1d];
8198         u8         tclass[0x3];
8199 };
8200
8201 struct mlx5_ifc_mcia_reg_bits {
8202         u8         l[0x1];
8203         u8         reserved_at_1[0x7];
8204         u8         module[0x8];
8205         u8         reserved_at_10[0x8];
8206         u8         status[0x8];
8207
8208         u8         i2c_device_address[0x8];
8209         u8         page_number[0x8];
8210         u8         device_address[0x10];
8211
8212         u8         reserved_at_40[0x10];
8213         u8         size[0x10];
8214
8215         u8         reserved_at_60[0x20];
8216
8217         u8         dword_0[0x20];
8218         u8         dword_1[0x20];
8219         u8         dword_2[0x20];
8220         u8         dword_3[0x20];
8221         u8         dword_4[0x20];
8222         u8         dword_5[0x20];
8223         u8         dword_6[0x20];
8224         u8         dword_7[0x20];
8225         u8         dword_8[0x20];
8226         u8         dword_9[0x20];
8227         u8         dword_10[0x20];
8228         u8         dword_11[0x20];
8229 };
8230
8231 struct mlx5_ifc_dcbx_param_bits {
8232         u8         dcbx_cee_cap[0x1];
8233         u8         dcbx_ieee_cap[0x1];
8234         u8         dcbx_standby_cap[0x1];
8235         u8         reserved_at_0[0x5];
8236         u8         port_number[0x8];
8237         u8         reserved_at_10[0xa];
8238         u8         max_application_table_size[6];
8239         u8         reserved_at_20[0x15];
8240         u8         version_oper[0x3];
8241         u8         reserved_at_38[5];
8242         u8         version_admin[0x3];
8243         u8         willing_admin[0x1];
8244         u8         reserved_at_41[0x3];
8245         u8         pfc_cap_oper[0x4];
8246         u8         reserved_at_48[0x4];
8247         u8         pfc_cap_admin[0x4];
8248         u8         reserved_at_50[0x4];
8249         u8         num_of_tc_oper[0x4];
8250         u8         reserved_at_58[0x4];
8251         u8         num_of_tc_admin[0x4];
8252         u8         remote_willing[0x1];
8253         u8         reserved_at_61[3];
8254         u8         remote_pfc_cap[4];
8255         u8         reserved_at_68[0x14];
8256         u8         remote_num_of_tc[0x4];
8257         u8         reserved_at_80[0x18];
8258         u8         error[0x8];
8259         u8         reserved_at_a0[0x160];
8260 };
8261
8262 struct mlx5_ifc_lagc_bits {
8263         u8         reserved_at_0[0x1d];
8264         u8         lag_state[0x3];
8265
8266         u8         reserved_at_20[0x14];
8267         u8         tx_remap_affinity_2[0x4];
8268         u8         reserved_at_38[0x4];
8269         u8         tx_remap_affinity_1[0x4];
8270 };
8271
8272 struct mlx5_ifc_create_lag_out_bits {
8273         u8         status[0x8];
8274         u8         reserved_at_8[0x18];
8275
8276         u8         syndrome[0x20];
8277
8278         u8         reserved_at_40[0x40];
8279 };
8280
8281 struct mlx5_ifc_create_lag_in_bits {
8282         u8         opcode[0x10];
8283         u8         reserved_at_10[0x10];
8284
8285         u8         reserved_at_20[0x10];
8286         u8         op_mod[0x10];
8287
8288         struct mlx5_ifc_lagc_bits ctx;
8289 };
8290
8291 struct mlx5_ifc_modify_lag_out_bits {
8292         u8         status[0x8];
8293         u8         reserved_at_8[0x18];
8294
8295         u8         syndrome[0x20];
8296
8297         u8         reserved_at_40[0x40];
8298 };
8299
8300 struct mlx5_ifc_modify_lag_in_bits {
8301         u8         opcode[0x10];
8302         u8         reserved_at_10[0x10];
8303
8304         u8         reserved_at_20[0x10];
8305         u8         op_mod[0x10];
8306
8307         u8         reserved_at_40[0x20];
8308         u8         field_select[0x20];
8309
8310         struct mlx5_ifc_lagc_bits ctx;
8311 };
8312
8313 struct mlx5_ifc_query_lag_out_bits {
8314         u8         status[0x8];
8315         u8         reserved_at_8[0x18];
8316
8317         u8         syndrome[0x20];
8318
8319         u8         reserved_at_40[0x40];
8320
8321         struct mlx5_ifc_lagc_bits ctx;
8322 };
8323
8324 struct mlx5_ifc_query_lag_in_bits {
8325         u8         opcode[0x10];
8326         u8         reserved_at_10[0x10];
8327
8328         u8         reserved_at_20[0x10];
8329         u8         op_mod[0x10];
8330
8331         u8         reserved_at_40[0x40];
8332 };
8333
8334 struct mlx5_ifc_destroy_lag_out_bits {
8335         u8         status[0x8];
8336         u8         reserved_at_8[0x18];
8337
8338         u8         syndrome[0x20];
8339
8340         u8         reserved_at_40[0x40];
8341 };
8342
8343 struct mlx5_ifc_destroy_lag_in_bits {
8344         u8         opcode[0x10];
8345         u8         reserved_at_10[0x10];
8346
8347         u8         reserved_at_20[0x10];
8348         u8         op_mod[0x10];
8349
8350         u8         reserved_at_40[0x40];
8351 };
8352
8353 struct mlx5_ifc_create_vport_lag_out_bits {
8354         u8         status[0x8];
8355         u8         reserved_at_8[0x18];
8356
8357         u8         syndrome[0x20];
8358
8359         u8         reserved_at_40[0x40];
8360 };
8361
8362 struct mlx5_ifc_create_vport_lag_in_bits {
8363         u8         opcode[0x10];
8364         u8         reserved_at_10[0x10];
8365
8366         u8         reserved_at_20[0x10];
8367         u8         op_mod[0x10];
8368
8369         u8         reserved_at_40[0x40];
8370 };
8371
8372 struct mlx5_ifc_destroy_vport_lag_out_bits {
8373         u8         status[0x8];
8374         u8         reserved_at_8[0x18];
8375
8376         u8         syndrome[0x20];
8377
8378         u8         reserved_at_40[0x40];
8379 };
8380
8381 struct mlx5_ifc_destroy_vport_lag_in_bits {
8382         u8         opcode[0x10];
8383         u8         reserved_at_10[0x10];
8384
8385         u8         reserved_at_20[0x10];
8386         u8         op_mod[0x10];
8387
8388         u8         reserved_at_40[0x40];
8389 };
8390
8391 #endif /* MLX5_IFC_H */