include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 147         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 148         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 149         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 150         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 151         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 152         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 153         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 154         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 155         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 156         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 157         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 158         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 159         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 160         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 161         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 162         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 163         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 164         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 165         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 166         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 167         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 168         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 169         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 170         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 171         MLX5_CMD_OP_NOP                           = 0x80d,
 172         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 173         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 174         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 175         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 176         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 177         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 178         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 179         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 180         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 181         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 182         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 183         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 184         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 185         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 186         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 187         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 188         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 189         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 190         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 191         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 192         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 193         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 194         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 195         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 196         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 197         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 198         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 199         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 200         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 201         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 202         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 203         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 204         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 205         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 206         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 207         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 208         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 209         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 210         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 211         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 212         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 213         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 214         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 215         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 216         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 217         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 218         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 219         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 220         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 221         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 223         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 224         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 225         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 226         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 227         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 228         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 229         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 230         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 231         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 232         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 233         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 234         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 235         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 236         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 237         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 238         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 239         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 240         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 241         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 242         MLX5_CMD_OP_MAX
 243 };
 244
 245 struct mlx5_ifc_flow_table_fields_supported_bits {
 246         u8         outer_dmac[0x1];
 247         u8         outer_smac[0x1];
 248         u8         outer_ether_type[0x1];
 249         u8         outer_ip_version[0x1];
 250         u8         outer_first_prio[0x1];
 251         u8         outer_first_cfi[0x1];
 252         u8         outer_first_vid[0x1];
 253         u8         outer_ipv4_ttl[0x1];
 254         u8         outer_second_prio[0x1];
 255         u8         outer_second_cfi[0x1];
 256         u8         outer_second_vid[0x1];
 257         u8         reserved_at_b[0x1];
 258         u8         outer_sip[0x1];
 259         u8         outer_dip[0x1];
 260         u8         outer_frag[0x1];
 261         u8         outer_ip_protocol[0x1];
 262         u8         outer_ip_ecn[0x1];
 263         u8         outer_ip_dscp[0x1];
 264         u8         outer_udp_sport[0x1];
 265         u8         outer_udp_dport[0x1];
 266         u8         outer_tcp_sport[0x1];
 267         u8         outer_tcp_dport[0x1];
 268         u8         outer_tcp_flags[0x1];
 269         u8         outer_gre_protocol[0x1];
 270         u8         outer_gre_key[0x1];
 271         u8         outer_vxlan_vni[0x1];
 272         u8         reserved_at_1a[0x5];
 273         u8         source_eswitch_port[0x1];
 274
 275         u8         inner_dmac[0x1];
 276         u8         inner_smac[0x1];
 277         u8         inner_ether_type[0x1];
 278         u8         inner_ip_version[0x1];
 279         u8         inner_first_prio[0x1];
 280         u8         inner_first_cfi[0x1];
 281         u8         inner_first_vid[0x1];
 282         u8         reserved_at_27[0x1];
 283         u8         inner_second_prio[0x1];
 284         u8         inner_second_cfi[0x1];
 285         u8         inner_second_vid[0x1];
 286         u8         reserved_at_2b[0x1];
 287         u8         inner_sip[0x1];
 288         u8         inner_dip[0x1];
 289         u8         inner_frag[0x1];
 290         u8         inner_ip_protocol[0x1];
 291         u8         inner_ip_ecn[0x1];
 292         u8         inner_ip_dscp[0x1];
 293         u8         inner_udp_sport[0x1];
 294         u8         inner_udp_dport[0x1];
 295         u8         inner_tcp_sport[0x1];
 296         u8         inner_tcp_dport[0x1];
 297         u8         inner_tcp_flags[0x1];
 298         u8         reserved_at_37[0x9];
 299         u8         reserved_at_40[0x17];
 300         u8         outer_esp_spi[0x1];
 301         u8         reserved_at_58[0x2];
 302         u8         bth_dst_qp[0x1];
 303
 304         u8         reserved_at_5b[0x25];
 305 };
 306
 307 struct mlx5_ifc_flow_table_prop_layout_bits {
 308         u8         ft_support[0x1];
 309         u8         reserved_at_1[0x1];
 310         u8         flow_counter[0x1];
 311         u8         flow_modify_en[0x1];
 312         u8         modify_root[0x1];
 313         u8         identified_miss_table_mode[0x1];
 314         u8         flow_table_modify[0x1];
 315         u8         encap[0x1];
 316         u8         decap[0x1];
 317         u8         reserved_at_9[0x1];
 318         u8         pop_vlan[0x1];
 319         u8         push_vlan[0x1];
 320         u8         reserved_at_c[0x14];
 321
 322         u8         reserved_at_20[0x2];
 323         u8         log_max_ft_size[0x6];
 324         u8         log_max_modify_header_context[0x8];
 325         u8         max_modify_header_actions[0x8];
 326         u8         max_ft_level[0x8];
 327
 328         u8         reserved_at_40[0x20];
 329
 330         u8         reserved_at_60[0x18];
 331         u8         log_max_ft_num[0x8];
 332
 333         u8         reserved_at_80[0x18];
 334         u8         log_max_destination[0x8];
 335
 336         u8         log_max_flow_counter[0x8];
 337         u8         reserved_at_a8[0x10];
 338         u8         log_max_flow[0x8];
 339
 340         u8         reserved_at_c0[0x40];
 341
 342         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 343
 344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 345 };
 346
 347 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 348         u8         send[0x1];
 349         u8         receive[0x1];
 350         u8         write[0x1];
 351         u8         read[0x1];
 352         u8         atomic[0x1];
 353         u8         srq_receive[0x1];
 354         u8         reserved_at_6[0x1a];
 355 };
 356
 357 struct mlx5_ifc_ipv4_layout_bits {
 358         u8         reserved_at_0[0x60];
 359
 360         u8         ipv4[0x20];
 361 };
 362
 363 struct mlx5_ifc_ipv6_layout_bits {
 364         u8         ipv6[16][0x8];
 365 };
 366
 367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 368         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 369         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 370         u8         reserved_at_0[0x80];
 371 };
 372
 373 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 374         u8         smac_47_16[0x20];
 375
 376         u8         smac_15_0[0x10];
 377         u8         ethertype[0x10];
 378
 379         u8         dmac_47_16[0x20];
 380
 381         u8         dmac_15_0[0x10];
 382         u8         first_prio[0x3];
 383         u8         first_cfi[0x1];
 384         u8         first_vid[0xc];
 385
 386         u8         ip_protocol[0x8];
 387         u8         ip_dscp[0x6];
 388         u8         ip_ecn[0x2];
 389         u8         cvlan_tag[0x1];
 390         u8         svlan_tag[0x1];
 391         u8         frag[0x1];
 392         u8         ip_version[0x4];
 393         u8         tcp_flags[0x9];
 394
 395         u8         tcp_sport[0x10];
 396         u8         tcp_dport[0x10];
 397
 398         u8         reserved_at_c0[0x18];
 399         u8         ttl_hoplimit[0x8];
 400
 401         u8         udp_sport[0x10];
 402         u8         udp_dport[0x10];
 403
 404         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 405
 406         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 407 };
 408
 409 struct mlx5_ifc_fte_match_set_misc_bits {
 410         u8         reserved_at_0[0x8];
 411         u8         source_sqn[0x18];
 412
 413         u8         reserved_at_20[0x10];
 414         u8         source_port[0x10];
 415
 416         u8         outer_second_prio[0x3];
 417         u8         outer_second_cfi[0x1];
 418         u8         outer_second_vid[0xc];
 419         u8         inner_second_prio[0x3];
 420         u8         inner_second_cfi[0x1];
 421         u8         inner_second_vid[0xc];
 422
 423         u8         outer_second_cvlan_tag[0x1];
 424         u8         inner_second_cvlan_tag[0x1];
 425         u8         outer_second_svlan_tag[0x1];
 426         u8         inner_second_svlan_tag[0x1];
 427         u8         reserved_at_64[0xc];
 428         u8         gre_protocol[0x10];
 429
 430         u8         gre_key_h[0x18];
 431         u8         gre_key_l[0x8];
 432
 433         u8         vxlan_vni[0x18];
 434         u8         reserved_at_b8[0x8];
 435
 436         u8         reserved_at_c0[0x20];
 437
 438         u8         reserved_at_e0[0xc];
 439         u8         outer_ipv6_flow_label[0x14];
 440
 441         u8         reserved_at_100[0xc];
 442         u8         inner_ipv6_flow_label[0x14];
 443
 444         u8         reserved_at_120[0x28];
 445         u8         bth_dst_qp[0x18];
 446         u8         reserved_at_160[0x20];
 447         u8         outer_esp_spi[0x20];
 448         u8         reserved_at_1a0[0x60];
 449 };
 450
 451 struct mlx5_ifc_cmd_pas_bits {
 452         u8         pa_h[0x20];
 453
 454         u8         pa_l[0x14];
 455         u8         reserved_at_34[0xc];
 456 };
 457
 458 struct mlx5_ifc_uint64_bits {
 459         u8         hi[0x20];
 460
 461         u8         lo[0x20];
 462 };
 463
 464 enum {
 465         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 466         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 467         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 468         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 469         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 470         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 471         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 472         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 473         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 474         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 475 };
 476
 477 struct mlx5_ifc_ads_bits {
 478         u8         fl[0x1];
 479         u8         free_ar[0x1];
 480         u8         reserved_at_2[0xe];
 481         u8         pkey_index[0x10];
 482
 483         u8         reserved_at_20[0x8];
 484         u8         grh[0x1];
 485         u8         mlid[0x7];
 486         u8         rlid[0x10];
 487
 488         u8         ack_timeout[0x5];
 489         u8         reserved_at_45[0x3];
 490         u8         src_addr_index[0x8];
 491         u8         reserved_at_50[0x4];
 492         u8         stat_rate[0x4];
 493         u8         hop_limit[0x8];
 494
 495         u8         reserved_at_60[0x4];
 496         u8         tclass[0x8];
 497         u8         flow_label[0x14];
 498
 499         u8         rgid_rip[16][0x8];
 500
 501         u8         reserved_at_100[0x4];
 502         u8         f_dscp[0x1];
 503         u8         f_ecn[0x1];
 504         u8         reserved_at_106[0x1];
 505         u8         f_eth_prio[0x1];
 506         u8         ecn[0x2];
 507         u8         dscp[0x6];
 508         u8         udp_sport[0x10];
 509
 510         u8         dei_cfi[0x1];
 511         u8         eth_prio[0x3];
 512         u8         sl[0x4];
 513         u8         vhca_port_num[0x8];
 514         u8         rmac_47_32[0x10];
 515
 516         u8         rmac_31_0[0x20];
 517 };
 518
 519 struct mlx5_ifc_flow_table_nic_cap_bits {
 520         u8         nic_rx_multi_path_tirs[0x1];
 521         u8         nic_rx_multi_path_tirs_fts[0x1];
 522         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 523         u8         reserved_at_3[0x1fd];
 524
 525         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 526
 527         u8         reserved_at_400[0x200];
 528
 529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 532
 533         u8         reserved_at_a00[0x200];
 534
 535         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 536
 537         u8         reserved_at_e00[0x7200];
 538 };
 539
 540 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 541         u8     reserved_at_0[0x200];
 542
 543         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 544
 545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 546
 547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 548
 549         u8      reserved_at_800[0x7800];
 550 };
 551
 552 struct mlx5_ifc_e_switch_cap_bits {
 553         u8         vport_svlan_strip[0x1];
 554         u8         vport_cvlan_strip[0x1];
 555         u8         vport_svlan_insert[0x1];
 556         u8         vport_cvlan_insert_if_not_exist[0x1];
 557         u8         vport_cvlan_insert_overwrite[0x1];
 558         u8         reserved_at_5[0x19];
 559         u8         nic_vport_node_guid_modify[0x1];
 560         u8         nic_vport_port_guid_modify[0x1];
 561
 562         u8         vxlan_encap_decap[0x1];
 563         u8         nvgre_encap_decap[0x1];
 564         u8         reserved_at_22[0x9];
 565         u8         log_max_encap_headers[0x5];
 566         u8         reserved_2b[0x6];
 567         u8         max_encap_header_size[0xa];
 568
 569         u8         reserved_40[0x7c0];
 570
 571 };
 572
 573 struct mlx5_ifc_qos_cap_bits {
 574         u8         packet_pacing[0x1];
 575         u8         esw_scheduling[0x1];
 576         u8         esw_bw_share[0x1];
 577         u8         esw_rate_limit[0x1];
 578         u8         reserved_at_4[0x1c];
 579
 580         u8         reserved_at_20[0x20];
 581
 582         u8         packet_pacing_max_rate[0x20];
 583
 584         u8         packet_pacing_min_rate[0x20];
 585
 586         u8         reserved_at_80[0x10];
 587         u8         packet_pacing_rate_table_size[0x10];
 588
 589         u8         esw_element_type[0x10];
 590         u8         esw_tsar_type[0x10];
 591
 592         u8         reserved_at_c0[0x10];
 593         u8         max_qos_para_vport[0x10];
 594
 595         u8         max_tsar_bw_share[0x20];
 596
 597         u8         reserved_at_100[0x700];
 598 };
 599
 600 struct mlx5_ifc_debug_cap_bits {
 601         u8         reserved_at_0[0x20];
 602
 603         u8         reserved_at_20[0x2];
 604         u8         stall_detect[0x1];
 605         u8         reserved_at_23[0x1d];
 606
 607         u8         reserved_at_40[0x7c0];
 608 };
 609
 610 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 611         u8         csum_cap[0x1];
 612         u8         vlan_cap[0x1];
 613         u8         lro_cap[0x1];
 614         u8         lro_psh_flag[0x1];
 615         u8         lro_time_stamp[0x1];
 616         u8         reserved_at_5[0x2];
 617         u8         wqe_vlan_insert[0x1];
 618         u8         self_lb_en_modifiable[0x1];
 619         u8         reserved_at_9[0x2];
 620         u8         max_lso_cap[0x5];
 621         u8         multi_pkt_send_wqe[0x2];
 622         u8         wqe_inline_mode[0x2];
 623         u8         rss_ind_tbl_cap[0x4];
 624         u8         reg_umr_sq[0x1];
 625         u8         scatter_fcs[0x1];
 626         u8         enhanced_multi_pkt_send_wqe[0x1];
 627         u8         tunnel_lso_const_out_ip_id[0x1];
 628         u8         reserved_at_1c[0x2];
 629         u8         tunnel_stateless_gre[0x1];
 630         u8         tunnel_stateless_vxlan[0x1];
 631
 632         u8         swp[0x1];
 633         u8         swp_csum[0x1];
 634         u8         swp_lso[0x1];
 635         u8         reserved_at_23[0x1b];
 636         u8         max_geneve_opt_len[0x1];
 637         u8         tunnel_stateless_geneve_rx[0x1];
 638
 639         u8         reserved_at_40[0x10];
 640         u8         lro_min_mss_size[0x10];
 641
 642         u8         reserved_at_60[0x120];
 643
 644         u8         lro_timer_supported_periods[4][0x20];
 645
 646         u8         reserved_at_200[0x600];
 647 };
 648
 649 struct mlx5_ifc_roce_cap_bits {
 650         u8         roce_apm[0x1];
 651         u8         reserved_at_1[0x1f];
 652
 653         u8         reserved_at_20[0x60];
 654
 655         u8         reserved_at_80[0xc];
 656         u8         l3_type[0x4];
 657         u8         reserved_at_90[0x8];
 658         u8         roce_version[0x8];
 659
 660         u8         reserved_at_a0[0x10];
 661         u8         r_roce_dest_udp_port[0x10];
 662
 663         u8         r_roce_max_src_udp_port[0x10];
 664         u8         r_roce_min_src_udp_port[0x10];
 665
 666         u8         reserved_at_e0[0x10];
 667         u8         roce_address_table_size[0x10];
 668
 669         u8         reserved_at_100[0x700];
 670 };
 671
 672 enum {
 673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 674         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 675         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 676         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 677         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 678         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 679         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 680         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 681         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 682 };
 683
 684 enum {
 685         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 686         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 687         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 688         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 689         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 690         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 691         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 692         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 693         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 694 };
 695
 696 struct mlx5_ifc_atomic_caps_bits {
 697         u8         reserved_at_0[0x40];
 698
 699         u8         atomic_req_8B_endianness_mode[0x2];
 700         u8         reserved_at_42[0x4];
 701         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 702
 703         u8         reserved_at_47[0x19];
 704
 705         u8         reserved_at_60[0x20];
 706
 707         u8         reserved_at_80[0x10];
 708         u8         atomic_operations[0x10];
 709
 710         u8         reserved_at_a0[0x10];
 711         u8         atomic_size_qp[0x10];
 712
 713         u8         reserved_at_c0[0x10];
 714         u8         atomic_size_dc[0x10];
 715
 716         u8         reserved_at_e0[0x720];
 717 };
 718
 719 struct mlx5_ifc_odp_cap_bits {
 720         u8         reserved_at_0[0x40];
 721
 722         u8         sig[0x1];
 723         u8         reserved_at_41[0x1f];
 724
 725         u8         reserved_at_60[0x20];
 726
 727         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 728
 729         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 730
 731         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 732
 733         u8         reserved_at_e0[0x720];
 734 };
 735
 736 struct mlx5_ifc_calc_op {
 737         u8        reserved_at_0[0x10];
 738         u8        reserved_at_10[0x9];
 739         u8        op_swap_endianness[0x1];
 740         u8        op_min[0x1];
 741         u8        op_xor[0x1];
 742         u8        op_or[0x1];
 743         u8        op_and[0x1];
 744         u8        op_max[0x1];
 745         u8        op_add[0x1];
 746 };
 747
 748 struct mlx5_ifc_vector_calc_cap_bits {
 749         u8         calc_matrix[0x1];
 750         u8         reserved_at_1[0x1f];
 751         u8         reserved_at_20[0x8];
 752         u8         max_vec_count[0x8];
 753         u8         reserved_at_30[0xd];
 754         u8         max_chunk_size[0x3];
 755         struct mlx5_ifc_calc_op calc0;
 756         struct mlx5_ifc_calc_op calc1;
 757         struct mlx5_ifc_calc_op calc2;
 758         struct mlx5_ifc_calc_op calc3;
 759
 760         u8         reserved_at_e0[0x720];
 761 };
 762
 763 enum {
 764         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 765         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 766         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 767         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 768 };
 769
 770 enum {
 771         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 772         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 773 };
 774
 775 enum {
 776         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 777         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 778         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 779         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 780         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 781 };
 782
 783 enum {
 784         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 785         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 786         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 787         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 788         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 789         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 790 };
 791
 792 enum {
 793         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 794         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 795 };
 796
 797 enum {
 798         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 799         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 800         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 801 };
 802
 803 enum {
 804         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 805         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 806 };
 807
 808 enum {
 809         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 810         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 811         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 812 };
 813
 814 struct mlx5_ifc_cmd_hca_cap_bits {
 815         u8         reserved_at_0[0x30];
 816         u8         vhca_id[0x10];
 817
 818         u8         reserved_at_40[0x40];
 819
 820         u8         log_max_srq_sz[0x8];
 821         u8         log_max_qp_sz[0x8];
 822         u8         reserved_at_90[0xb];
 823         u8         log_max_qp[0x5];
 824
 825         u8         reserved_at_a0[0xb];
 826         u8         log_max_srq[0x5];
 827         u8         reserved_at_b0[0x10];
 828
 829         u8         reserved_at_c0[0x8];
 830         u8         log_max_cq_sz[0x8];
 831         u8         reserved_at_d0[0xb];
 832         u8         log_max_cq[0x5];
 833
 834         u8         log_max_eq_sz[0x8];
 835         u8         reserved_at_e8[0x2];
 836         u8         log_max_mkey[0x6];
 837         u8         reserved_at_f0[0xc];
 838         u8         log_max_eq[0x4];
 839
 840         u8         max_indirection[0x8];
 841         u8         fixed_buffer_size[0x1];
 842         u8         log_max_mrw_sz[0x7];
 843         u8         force_teardown[0x1];
 844         u8         reserved_at_111[0x1];
 845         u8         log_max_bsf_list_size[0x6];
 846         u8         umr_extended_translation_offset[0x1];
 847         u8         null_mkey[0x1];
 848         u8         log_max_klm_list_size[0x6];
 849
 850         u8         reserved_at_120[0xa];
 851         u8         log_max_ra_req_dc[0x6];
 852         u8         reserved_at_130[0xa];
 853         u8         log_max_ra_res_dc[0x6];
 854
 855         u8         reserved_at_140[0xa];
 856         u8         log_max_ra_req_qp[0x6];
 857         u8         reserved_at_150[0xa];
 858         u8         log_max_ra_res_qp[0x6];
 859
 860         u8         end_pad[0x1];
 861         u8         cc_query_allowed[0x1];
 862         u8         cc_modify_allowed[0x1];
 863         u8         start_pad[0x1];
 864         u8         cache_line_128byte[0x1];
 865         u8         reserved_at_165[0xa];
 866         u8         qcam_reg[0x1];
 867         u8         gid_table_size[0x10];
 868
 869         u8         out_of_seq_cnt[0x1];
 870         u8         vport_counters[0x1];
 871         u8         retransmission_q_counters[0x1];
 872         u8         debug[0x1];
 873         u8         modify_rq_counter_set_id[0x1];
 874         u8         rq_delay_drop[0x1];
 875         u8         max_qp_cnt[0xa];
 876         u8         pkey_table_size[0x10];
 877
 878         u8         vport_group_manager[0x1];
 879         u8         vhca_group_manager[0x1];
 880         u8         ib_virt[0x1];
 881         u8         eth_virt[0x1];
 882         u8         vnic_env_queue_counters[0x1];
 883         u8         ets[0x1];
 884         u8         nic_flow_table[0x1];
 885         u8         eswitch_flow_table[0x1];
 886         u8         early_vf_enable[0x1];
 887         u8         mcam_reg[0x1];
 888         u8         pcam_reg[0x1];
 889         u8         local_ca_ack_delay[0x5];
 890         u8         port_module_event[0x1];
 891         u8         enhanced_error_q_counters[0x1];
 892         u8         ports_check[0x1];
 893         u8         reserved_at_1b3[0x1];
 894         u8         disable_link_up[0x1];
 895         u8         beacon_led[0x1];
 896         u8         port_type[0x2];
 897         u8         num_ports[0x8];
 898
 899         u8         reserved_at_1c0[0x1];
 900         u8         pps[0x1];
 901         u8         pps_modify[0x1];
 902         u8         log_max_msg[0x5];
 903         u8         reserved_at_1c8[0x4];
 904         u8         max_tc[0x4];
 905         u8         reserved_at_1d0[0x1];
 906         u8         dcbx[0x1];
 907         u8         general_notification_event[0x1];
 908         u8         reserved_at_1d3[0x2];
 909         u8         fpga[0x1];
 910         u8         rol_s[0x1];
 911         u8         rol_g[0x1];
 912         u8         reserved_at_1d8[0x1];
 913         u8         wol_s[0x1];
 914         u8         wol_g[0x1];
 915         u8         wol_a[0x1];
 916         u8         wol_b[0x1];
 917         u8         wol_m[0x1];
 918         u8         wol_u[0x1];
 919         u8         wol_p[0x1];
 920
 921         u8         stat_rate_support[0x10];
 922         u8         reserved_at_1f0[0xc];
 923         u8         cqe_version[0x4];
 924
 925         u8         compact_address_vector[0x1];
 926         u8         striding_rq[0x1];
 927         u8         reserved_at_202[0x1];
 928         u8         ipoib_enhanced_offloads[0x1];
 929         u8         ipoib_basic_offloads[0x1];
 930         u8         reserved_at_205[0x5];
 931         u8         umr_fence[0x2];
 932         u8         reserved_at_20c[0x3];
 933         u8         drain_sigerr[0x1];
 934         u8         cmdif_checksum[0x2];
 935         u8         sigerr_cqe[0x1];
 936         u8         reserved_at_213[0x1];
 937         u8         wq_signature[0x1];
 938         u8         sctr_data_cqe[0x1];
 939         u8         reserved_at_216[0x1];
 940         u8         sho[0x1];
 941         u8         tph[0x1];
 942         u8         rf[0x1];
 943         u8         dct[0x1];
 944         u8         qos[0x1];
 945         u8         eth_net_offloads[0x1];
 946         u8         roce[0x1];
 947         u8         atomic[0x1];
 948         u8         reserved_at_21f[0x1];
 949
 950         u8         cq_oi[0x1];
 951         u8         cq_resize[0x1];
 952         u8         cq_moderation[0x1];
 953         u8         reserved_at_223[0x3];
 954         u8         cq_eq_remap[0x1];
 955         u8         pg[0x1];
 956         u8         block_lb_mc[0x1];
 957         u8         reserved_at_229[0x1];
 958         u8         scqe_break_moderation[0x1];
 959         u8         cq_period_start_from_cqe[0x1];
 960         u8         cd[0x1];
 961         u8         reserved_at_22d[0x1];
 962         u8         apm[0x1];
 963         u8         vector_calc[0x1];
 964         u8         umr_ptr_rlky[0x1];
 965         u8         imaicl[0x1];
 966         u8         reserved_at_232[0x4];
 967         u8         qkv[0x1];
 968         u8         pkv[0x1];
 969         u8         set_deth_sqpn[0x1];
 970         u8         reserved_at_239[0x3];
 971         u8         xrc[0x1];
 972         u8         ud[0x1];
 973         u8         uc[0x1];
 974         u8         rc[0x1];
 975
 976         u8         uar_4k[0x1];
 977         u8         reserved_at_241[0x9];
 978         u8         uar_sz[0x6];
 979         u8         reserved_at_250[0x8];
 980         u8         log_pg_sz[0x8];
 981
 982         u8         bf[0x1];
 983         u8         driver_version[0x1];
 984         u8         pad_tx_eth_packet[0x1];
 985         u8         reserved_at_263[0x8];
 986         u8         log_bf_reg_size[0x5];
 987
 988         u8         reserved_at_270[0xb];
 989         u8         lag_master[0x1];
 990         u8         num_lag_ports[0x4];
 991
 992         u8         reserved_at_280[0x10];
 993         u8         max_wqe_sz_sq[0x10];
 994
 995         u8         reserved_at_2a0[0x10];
 996         u8         max_wqe_sz_rq[0x10];
 997
 998         u8         max_flow_counter_31_16[0x10];
 999         u8         max_wqe_sz_sq_dc[0x10];
1000
1001         u8         reserved_at_2e0[0x7];
1002         u8         max_qp_mcg[0x19];
1003
1004         u8         reserved_at_300[0x18];
1005         u8         log_max_mcg[0x8];
1006
1007         u8         reserved_at_320[0x3];
1008         u8         log_max_transport_domain[0x5];
1009         u8         reserved_at_328[0x3];
1010         u8         log_max_pd[0x5];
1011         u8         reserved_at_330[0xb];
1012         u8         log_max_xrcd[0x5];
1013
1014         u8         nic_receive_steering_discard[0x1];
1015         u8         receive_discard_vport_down[0x1];
1016         u8         transmit_discard_vport_down[0x1];
1017         u8         reserved_at_343[0x5];
1018         u8         log_max_flow_counter_bulk[0x8];
1019         u8         max_flow_counter_15_0[0x10];
1020
1021
1022         u8         reserved_at_360[0x3];
1023         u8         log_max_rq[0x5];
1024         u8         reserved_at_368[0x3];
1025         u8         log_max_sq[0x5];
1026         u8         reserved_at_370[0x3];
1027         u8         log_max_tir[0x5];
1028         u8         reserved_at_378[0x3];
1029         u8         log_max_tis[0x5];
1030
1031         u8         basic_cyclic_rcv_wqe[0x1];
1032         u8         reserved_at_381[0x2];
1033         u8         log_max_rmp[0x5];
1034         u8         reserved_at_388[0x3];
1035         u8         log_max_rqt[0x5];
1036         u8         reserved_at_390[0x3];
1037         u8         log_max_rqt_size[0x5];
1038         u8         reserved_at_398[0x3];
1039         u8         log_max_tis_per_sq[0x5];
1040
1041         u8         reserved_at_3a0[0x3];
1042         u8         log_max_stride_sz_rq[0x5];
1043         u8         reserved_at_3a8[0x3];
1044         u8         log_min_stride_sz_rq[0x5];
1045         u8         reserved_at_3b0[0x3];
1046         u8         log_max_stride_sz_sq[0x5];
1047         u8         reserved_at_3b8[0x3];
1048         u8         log_min_stride_sz_sq[0x5];
1049
1050         u8         hairpin[0x1];
1051         u8         reserved_at_3c1[0x2];
1052         u8         log_max_hairpin_queues[0x5];
1053         u8         reserved_at_3c8[0x3];
1054         u8         log_max_hairpin_wq_data_sz[0x5];
1055         u8         reserved_at_3d0[0x3];
1056         u8         log_max_hairpin_num_packets[0x5];
1057         u8         reserved_at_3d8[0x3];
1058         u8         log_max_wq_sz[0x5];
1059
1060         u8         nic_vport_change_event[0x1];
1061         u8         disable_local_lb_uc[0x1];
1062         u8         disable_local_lb_mc[0x1];
1063         u8         log_min_hairpin_wq_data_sz[0x5];
1064         u8         reserved_at_3e8[0x3];
1065         u8         log_max_vlan_list[0x5];
1066         u8         reserved_at_3f0[0x3];
1067         u8         log_max_current_mc_list[0x5];
1068         u8         reserved_at_3f8[0x3];
1069         u8         log_max_current_uc_list[0x5];
1070
1071         u8         reserved_at_400[0x80];
1072
1073         u8         reserved_at_480[0x3];
1074         u8         log_max_l2_table[0x5];
1075         u8         reserved_at_488[0x8];
1076         u8         log_uar_page_sz[0x10];
1077
1078         u8         reserved_at_4a0[0x20];
1079         u8         device_frequency_mhz[0x20];
1080         u8         device_frequency_khz[0x20];
1081
1082         u8         reserved_at_500[0x20];
1083         u8         num_of_uars_per_page[0x20];
1084         u8         reserved_at_540[0x40];
1085
1086         u8         reserved_at_580[0x3d];
1087         u8         cqe_128_always[0x1];
1088         u8         cqe_compression_128[0x1];
1089         u8         cqe_compression[0x1];
1090
1091         u8         cqe_compression_timeout[0x10];
1092         u8         cqe_compression_max_num[0x10];
1093
1094         u8         reserved_at_5e0[0x10];
1095         u8         tag_matching[0x1];
1096         u8         rndv_offload_rc[0x1];
1097         u8         rndv_offload_dc[0x1];
1098         u8         log_tag_matching_list_sz[0x5];
1099         u8         reserved_at_5f8[0x3];
1100         u8         log_max_xrq[0x5];
1101
1102         u8         affiliate_nic_vport_criteria[0x8];
1103         u8         native_port_num[0x8];
1104         u8         num_vhca_ports[0x8];
1105         u8         reserved_at_618[0x6];
1106         u8         sw_owner_id[0x1];
1107         u8         reserved_at_61f[0x1e1];
1108 };
1109
1110 enum mlx5_flow_destination_type {
1111         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1112         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1113         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1114
1115         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1116         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1117 };
1118
1119 struct mlx5_ifc_dest_format_struct_bits {
1120         u8         destination_type[0x8];
1121         u8         destination_id[0x18];
1122
1123         u8         reserved_at_20[0x20];
1124 };
1125
1126 struct mlx5_ifc_flow_counter_list_bits {
1127         u8         flow_counter_id[0x20];
1128
1129         u8         reserved_at_20[0x20];
1130 };
1131
1132 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1133         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1134         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1135         u8         reserved_at_0[0x40];
1136 };
1137
1138 struct mlx5_ifc_fte_match_param_bits {
1139         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1140
1141         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1142
1143         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1144
1145         u8         reserved_at_600[0xa00];
1146 };
1147
1148 enum {
1149         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1150         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1151         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1152         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1153         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1154 };
1155
1156 struct mlx5_ifc_rx_hash_field_select_bits {
1157         u8         l3_prot_type[0x1];
1158         u8         l4_prot_type[0x1];
1159         u8         selected_fields[0x1e];
1160 };
1161
1162 enum {
1163         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1164         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1165 };
1166
1167 enum {
1168         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1169         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1170 };
1171
1172 struct mlx5_ifc_wq_bits {
1173         u8         wq_type[0x4];
1174         u8         wq_signature[0x1];
1175         u8         end_padding_mode[0x2];
1176         u8         cd_slave[0x1];
1177         u8         reserved_at_8[0x18];
1178
1179         u8         hds_skip_first_sge[0x1];
1180         u8         log2_hds_buf_size[0x3];
1181         u8         reserved_at_24[0x7];
1182         u8         page_offset[0x5];
1183         u8         lwm[0x10];
1184
1185         u8         reserved_at_40[0x8];
1186         u8         pd[0x18];
1187
1188         u8         reserved_at_60[0x8];
1189         u8         uar_page[0x18];
1190
1191         u8         dbr_addr[0x40];
1192
1193         u8         hw_counter[0x20];
1194
1195         u8         sw_counter[0x20];
1196
1197         u8         reserved_at_100[0xc];
1198         u8         log_wq_stride[0x4];
1199         u8         reserved_at_110[0x3];
1200         u8         log_wq_pg_sz[0x5];
1201         u8         reserved_at_118[0x3];
1202         u8         log_wq_sz[0x5];
1203
1204         u8         reserved_at_120[0x3];
1205         u8         log_hairpin_num_packets[0x5];
1206         u8         reserved_at_128[0x3];
1207         u8         log_hairpin_data_sz[0x5];
1208         u8         reserved_at_130[0x5];
1209
1210         u8         log_wqe_num_of_strides[0x3];
1211         u8         two_byte_shift_en[0x1];
1212         u8         reserved_at_139[0x4];
1213         u8         log_wqe_stride_size[0x3];
1214
1215         u8         reserved_at_140[0x4c0];
1216
1217         struct mlx5_ifc_cmd_pas_bits pas[0];
1218 };
1219
1220 struct mlx5_ifc_rq_num_bits {
1221         u8         reserved_at_0[0x8];
1222         u8         rq_num[0x18];
1223 };
1224
1225 struct mlx5_ifc_mac_address_layout_bits {
1226         u8         reserved_at_0[0x10];
1227         u8         mac_addr_47_32[0x10];
1228
1229         u8         mac_addr_31_0[0x20];
1230 };
1231
1232 struct mlx5_ifc_vlan_layout_bits {
1233         u8         reserved_at_0[0x14];
1234         u8         vlan[0x0c];
1235
1236         u8         reserved_at_20[0x20];
1237 };
1238
1239 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1240         u8         reserved_at_0[0xa0];
1241
1242         u8         min_time_between_cnps[0x20];
1243
1244         u8         reserved_at_c0[0x12];
1245         u8         cnp_dscp[0x6];
1246         u8         reserved_at_d8[0x4];
1247         u8         cnp_prio_mode[0x1];
1248         u8         cnp_802p_prio[0x3];
1249
1250         u8         reserved_at_e0[0x720];
1251 };
1252
1253 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1254         u8         reserved_at_0[0x60];
1255
1256         u8         reserved_at_60[0x4];
1257         u8         clamp_tgt_rate[0x1];
1258         u8         reserved_at_65[0x3];
1259         u8         clamp_tgt_rate_after_time_inc[0x1];
1260         u8         reserved_at_69[0x17];
1261
1262         u8         reserved_at_80[0x20];
1263
1264         u8         rpg_time_reset[0x20];
1265
1266         u8         rpg_byte_reset[0x20];
1267
1268         u8         rpg_threshold[0x20];
1269
1270         u8         rpg_max_rate[0x20];
1271
1272         u8         rpg_ai_rate[0x20];
1273
1274         u8         rpg_hai_rate[0x20];
1275
1276         u8         rpg_gd[0x20];
1277
1278         u8         rpg_min_dec_fac[0x20];
1279
1280         u8         rpg_min_rate[0x20];
1281
1282         u8         reserved_at_1c0[0xe0];
1283
1284         u8         rate_to_set_on_first_cnp[0x20];
1285
1286         u8         dce_tcp_g[0x20];
1287
1288         u8         dce_tcp_rtt[0x20];
1289
1290         u8         rate_reduce_monitor_period[0x20];
1291
1292         u8         reserved_at_320[0x20];
1293
1294         u8         initial_alpha_value[0x20];
1295
1296         u8         reserved_at_360[0x4a0];
1297 };
1298
1299 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1300         u8         reserved_at_0[0x80];
1301
1302         u8         rppp_max_rps[0x20];
1303
1304         u8         rpg_time_reset[0x20];
1305
1306         u8         rpg_byte_reset[0x20];
1307
1308         u8         rpg_threshold[0x20];
1309
1310         u8         rpg_max_rate[0x20];
1311
1312         u8         rpg_ai_rate[0x20];
1313
1314         u8         rpg_hai_rate[0x20];
1315
1316         u8         rpg_gd[0x20];
1317
1318         u8         rpg_min_dec_fac[0x20];
1319
1320         u8         rpg_min_rate[0x20];
1321
1322         u8         reserved_at_1c0[0x640];
1323 };
1324
1325 enum {
1326         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1327         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1328         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1329 };
1330
1331 struct mlx5_ifc_resize_field_select_bits {
1332         u8         resize_field_select[0x20];
1333 };
1334
1335 enum {
1336         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1337         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1338         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1339         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1340 };
1341
1342 struct mlx5_ifc_modify_field_select_bits {
1343         u8         modify_field_select[0x20];
1344 };
1345
1346 struct mlx5_ifc_field_select_r_roce_np_bits {
1347         u8         field_select_r_roce_np[0x20];
1348 };
1349
1350 struct mlx5_ifc_field_select_r_roce_rp_bits {
1351         u8         field_select_r_roce_rp[0x20];
1352 };
1353
1354 enum {
1355         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1356         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1357         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1358         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1359         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1360         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1361         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1362         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1363         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1364         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1365 };
1366
1367 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1368         u8         field_select_8021qaurp[0x20];
1369 };
1370
1371 struct mlx5_ifc_phys_layer_cntrs_bits {
1372         u8         time_since_last_clear_high[0x20];
1373
1374         u8         time_since_last_clear_low[0x20];
1375
1376         u8         symbol_errors_high[0x20];
1377
1378         u8         symbol_errors_low[0x20];
1379
1380         u8         sync_headers_errors_high[0x20];
1381
1382         u8         sync_headers_errors_low[0x20];
1383
1384         u8         edpl_bip_errors_lane0_high[0x20];
1385
1386         u8         edpl_bip_errors_lane0_low[0x20];
1387
1388         u8         edpl_bip_errors_lane1_high[0x20];
1389
1390         u8         edpl_bip_errors_lane1_low[0x20];
1391
1392         u8         edpl_bip_errors_lane2_high[0x20];
1393
1394         u8         edpl_bip_errors_lane2_low[0x20];
1395
1396         u8         edpl_bip_errors_lane3_high[0x20];
1397
1398         u8         edpl_bip_errors_lane3_low[0x20];
1399
1400         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1401
1402         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1403
1404         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1405
1406         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1407
1408         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1409
1410         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1411
1412         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1413
1414         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1415
1416         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1417
1418         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1419
1420         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1421
1422         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1423
1424         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1425
1426         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1427
1428         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1429
1430         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1431
1432         u8         rs_fec_corrected_blocks_high[0x20];
1433
1434         u8         rs_fec_corrected_blocks_low[0x20];
1435
1436         u8         rs_fec_uncorrectable_blocks_high[0x20];
1437
1438         u8         rs_fec_uncorrectable_blocks_low[0x20];
1439
1440         u8         rs_fec_no_errors_blocks_high[0x20];
1441
1442         u8         rs_fec_no_errors_blocks_low[0x20];
1443
1444         u8         rs_fec_single_error_blocks_high[0x20];
1445
1446         u8         rs_fec_single_error_blocks_low[0x20];
1447
1448         u8         rs_fec_corrected_symbols_total_high[0x20];
1449
1450         u8         rs_fec_corrected_symbols_total_low[0x20];
1451
1452         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1453
1454         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1455
1456         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1457
1458         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1459
1460         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1461
1462         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1463
1464         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1465
1466         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1467
1468         u8         link_down_events[0x20];
1469
1470         u8         successful_recovery_events[0x20];
1471
1472         u8         reserved_at_640[0x180];
1473 };
1474
1475 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1476         u8         time_since_last_clear_high[0x20];
1477
1478         u8         time_since_last_clear_low[0x20];
1479
1480         u8         phy_received_bits_high[0x20];
1481
1482         u8         phy_received_bits_low[0x20];
1483
1484         u8         phy_symbol_errors_high[0x20];
1485
1486         u8         phy_symbol_errors_low[0x20];
1487
1488         u8         phy_corrected_bits_high[0x20];
1489
1490         u8         phy_corrected_bits_low[0x20];
1491
1492         u8         phy_corrected_bits_lane0_high[0x20];
1493
1494         u8         phy_corrected_bits_lane0_low[0x20];
1495
1496         u8         phy_corrected_bits_lane1_high[0x20];
1497
1498         u8         phy_corrected_bits_lane1_low[0x20];
1499
1500         u8         phy_corrected_bits_lane2_high[0x20];
1501
1502         u8         phy_corrected_bits_lane2_low[0x20];
1503
1504         u8         phy_corrected_bits_lane3_high[0x20];
1505
1506         u8         phy_corrected_bits_lane3_low[0x20];
1507
1508         u8         reserved_at_200[0x5c0];
1509 };
1510
1511 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1512         u8         symbol_error_counter[0x10];
1513
1514         u8         link_error_recovery_counter[0x8];
1515
1516         u8         link_downed_counter[0x8];
1517
1518         u8         port_rcv_errors[0x10];
1519
1520         u8         port_rcv_remote_physical_errors[0x10];
1521
1522         u8         port_rcv_switch_relay_errors[0x10];
1523
1524         u8         port_xmit_discards[0x10];
1525
1526         u8         port_xmit_constraint_errors[0x8];
1527
1528         u8         port_rcv_constraint_errors[0x8];
1529
1530         u8         reserved_at_70[0x8];
1531
1532         u8         link_overrun_errors[0x8];
1533
1534         u8         reserved_at_80[0x10];
1535
1536         u8         vl_15_dropped[0x10];
1537
1538         u8         reserved_at_a0[0x80];
1539
1540         u8         port_xmit_wait[0x20];
1541 };
1542
1543 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1544         u8         transmit_queue_high[0x20];
1545
1546         u8         transmit_queue_low[0x20];
1547
1548         u8         reserved_at_40[0x780];
1549 };
1550
1551 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1552         u8         rx_octets_high[0x20];
1553
1554         u8         rx_octets_low[0x20];
1555
1556         u8         reserved_at_40[0xc0];
1557
1558         u8         rx_frames_high[0x20];
1559
1560         u8         rx_frames_low[0x20];
1561
1562         u8         tx_octets_high[0x20];
1563
1564         u8         tx_octets_low[0x20];
1565
1566         u8         reserved_at_180[0xc0];
1567
1568         u8         tx_frames_high[0x20];
1569
1570         u8         tx_frames_low[0x20];
1571
1572         u8         rx_pause_high[0x20];
1573
1574         u8         rx_pause_low[0x20];
1575
1576         u8         rx_pause_duration_high[0x20];
1577
1578         u8         rx_pause_duration_low[0x20];
1579
1580         u8         tx_pause_high[0x20];
1581
1582         u8         tx_pause_low[0x20];
1583
1584         u8         tx_pause_duration_high[0x20];
1585
1586         u8         tx_pause_duration_low[0x20];
1587
1588         u8         rx_pause_transition_high[0x20];
1589
1590         u8         rx_pause_transition_low[0x20];
1591
1592         u8         reserved_at_3c0[0x40];
1593
1594         u8         device_stall_minor_watermark_cnt_high[0x20];
1595
1596         u8         device_stall_minor_watermark_cnt_low[0x20];
1597
1598         u8         device_stall_critical_watermark_cnt_high[0x20];
1599
1600         u8         device_stall_critical_watermark_cnt_low[0x20];
1601
1602         u8         reserved_at_480[0x340];
1603 };
1604
1605 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1606         u8         port_transmit_wait_high[0x20];
1607
1608         u8         port_transmit_wait_low[0x20];
1609
1610         u8         reserved_at_40[0x100];
1611
1612         u8         rx_buffer_almost_full_high[0x20];
1613
1614         u8         rx_buffer_almost_full_low[0x20];
1615
1616         u8         rx_buffer_full_high[0x20];
1617
1618         u8         rx_buffer_full_low[0x20];
1619
1620         u8         reserved_at_1c0[0x600];
1621 };
1622
1623 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1624         u8         dot3stats_alignment_errors_high[0x20];
1625
1626         u8         dot3stats_alignment_errors_low[0x20];
1627
1628         u8         dot3stats_fcs_errors_high[0x20];
1629
1630         u8         dot3stats_fcs_errors_low[0x20];
1631
1632         u8         dot3stats_single_collision_frames_high[0x20];
1633
1634         u8         dot3stats_single_collision_frames_low[0x20];
1635
1636         u8         dot3stats_multiple_collision_frames_high[0x20];
1637
1638         u8         dot3stats_multiple_collision_frames_low[0x20];
1639
1640         u8         dot3stats_sqe_test_errors_high[0x20];
1641
1642         u8         dot3stats_sqe_test_errors_low[0x20];
1643
1644         u8         dot3stats_deferred_transmissions_high[0x20];
1645
1646         u8         dot3stats_deferred_transmissions_low[0x20];
1647
1648         u8         dot3stats_late_collisions_high[0x20];
1649
1650         u8         dot3stats_late_collisions_low[0x20];
1651
1652         u8         dot3stats_excessive_collisions_high[0x20];
1653
1654         u8         dot3stats_excessive_collisions_low[0x20];
1655
1656         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1657
1658         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1659
1660         u8         dot3stats_carrier_sense_errors_high[0x20];
1661
1662         u8         dot3stats_carrier_sense_errors_low[0x20];
1663
1664         u8         dot3stats_frame_too_longs_high[0x20];
1665
1666         u8         dot3stats_frame_too_longs_low[0x20];
1667
1668         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1669
1670         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1671
1672         u8         dot3stats_symbol_errors_high[0x20];
1673
1674         u8         dot3stats_symbol_errors_low[0x20];
1675
1676         u8         dot3control_in_unknown_opcodes_high[0x20];
1677
1678         u8         dot3control_in_unknown_opcodes_low[0x20];
1679
1680         u8         dot3in_pause_frames_high[0x20];
1681
1682         u8         dot3in_pause_frames_low[0x20];
1683
1684         u8         dot3out_pause_frames_high[0x20];
1685
1686         u8         dot3out_pause_frames_low[0x20];
1687
1688         u8         reserved_at_400[0x3c0];
1689 };
1690
1691 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1692         u8         ether_stats_drop_events_high[0x20];
1693
1694         u8         ether_stats_drop_events_low[0x20];
1695
1696         u8         ether_stats_octets_high[0x20];
1697
1698         u8         ether_stats_octets_low[0x20];
1699
1700         u8         ether_stats_pkts_high[0x20];
1701
1702         u8         ether_stats_pkts_low[0x20];
1703
1704         u8         ether_stats_broadcast_pkts_high[0x20];
1705
1706         u8         ether_stats_broadcast_pkts_low[0x20];
1707
1708         u8         ether_stats_multicast_pkts_high[0x20];
1709
1710         u8         ether_stats_multicast_pkts_low[0x20];
1711
1712         u8         ether_stats_crc_align_errors_high[0x20];
1713
1714         u8         ether_stats_crc_align_errors_low[0x20];
1715
1716         u8         ether_stats_undersize_pkts_high[0x20];
1717
1718         u8         ether_stats_undersize_pkts_low[0x20];
1719
1720         u8         ether_stats_oversize_pkts_high[0x20];
1721
1722         u8         ether_stats_oversize_pkts_low[0x20];
1723
1724         u8         ether_stats_fragments_high[0x20];
1725
1726         u8         ether_stats_fragments_low[0x20];
1727
1728         u8         ether_stats_jabbers_high[0x20];
1729
1730         u8         ether_stats_jabbers_low[0x20];
1731
1732         u8         ether_stats_collisions_high[0x20];
1733
1734         u8         ether_stats_collisions_low[0x20];
1735
1736         u8         ether_stats_pkts64octets_high[0x20];
1737
1738         u8         ether_stats_pkts64octets_low[0x20];
1739
1740         u8         ether_stats_pkts65to127octets_high[0x20];
1741
1742         u8         ether_stats_pkts65to127octets_low[0x20];
1743
1744         u8         ether_stats_pkts128to255octets_high[0x20];
1745
1746         u8         ether_stats_pkts128to255octets_low[0x20];
1747
1748         u8         ether_stats_pkts256to511octets_high[0x20];
1749
1750         u8         ether_stats_pkts256to511octets_low[0x20];
1751
1752         u8         ether_stats_pkts512to1023octets_high[0x20];
1753
1754         u8         ether_stats_pkts512to1023octets_low[0x20];
1755
1756         u8         ether_stats_pkts1024to1518octets_high[0x20];
1757
1758         u8         ether_stats_pkts1024to1518octets_low[0x20];
1759
1760         u8         ether_stats_pkts1519to2047octets_high[0x20];
1761
1762         u8         ether_stats_pkts1519to2047octets_low[0x20];
1763
1764         u8         ether_stats_pkts2048to4095octets_high[0x20];
1765
1766         u8         ether_stats_pkts2048to4095octets_low[0x20];
1767
1768         u8         ether_stats_pkts4096to8191octets_high[0x20];
1769
1770         u8         ether_stats_pkts4096to8191octets_low[0x20];
1771
1772         u8         ether_stats_pkts8192to10239octets_high[0x20];
1773
1774         u8         ether_stats_pkts8192to10239octets_low[0x20];
1775
1776         u8         reserved_at_540[0x280];
1777 };
1778
1779 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1780         u8         if_in_octets_high[0x20];
1781
1782         u8         if_in_octets_low[0x20];
1783
1784         u8         if_in_ucast_pkts_high[0x20];
1785
1786         u8         if_in_ucast_pkts_low[0x20];
1787
1788         u8         if_in_discards_high[0x20];
1789
1790         u8         if_in_discards_low[0x20];
1791
1792         u8         if_in_errors_high[0x20];
1793
1794         u8         if_in_errors_low[0x20];
1795
1796         u8         if_in_unknown_protos_high[0x20];
1797
1798         u8         if_in_unknown_protos_low[0x20];
1799
1800         u8         if_out_octets_high[0x20];
1801
1802         u8         if_out_octets_low[0x20];
1803
1804         u8         if_out_ucast_pkts_high[0x20];
1805
1806         u8         if_out_ucast_pkts_low[0x20];
1807
1808         u8         if_out_discards_high[0x20];
1809
1810         u8         if_out_discards_low[0x20];
1811
1812         u8         if_out_errors_high[0x20];
1813
1814         u8         if_out_errors_low[0x20];
1815
1816         u8         if_in_multicast_pkts_high[0x20];
1817
1818         u8         if_in_multicast_pkts_low[0x20];
1819
1820         u8         if_in_broadcast_pkts_high[0x20];
1821
1822         u8         if_in_broadcast_pkts_low[0x20];
1823
1824         u8         if_out_multicast_pkts_high[0x20];
1825
1826         u8         if_out_multicast_pkts_low[0x20];
1827
1828         u8         if_out_broadcast_pkts_high[0x20];
1829
1830         u8         if_out_broadcast_pkts_low[0x20];
1831
1832         u8         reserved_at_340[0x480];
1833 };
1834
1835 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1836         u8         a_frames_transmitted_ok_high[0x20];
1837
1838         u8         a_frames_transmitted_ok_low[0x20];
1839
1840         u8         a_frames_received_ok_high[0x20];
1841
1842         u8         a_frames_received_ok_low[0x20];
1843
1844         u8         a_frame_check_sequence_errors_high[0x20];
1845
1846         u8         a_frame_check_sequence_errors_low[0x20];
1847
1848         u8         a_alignment_errors_high[0x20];
1849
1850         u8         a_alignment_errors_low[0x20];
1851
1852         u8         a_octets_transmitted_ok_high[0x20];
1853
1854         u8         a_octets_transmitted_ok_low[0x20];
1855
1856         u8         a_octets_received_ok_high[0x20];
1857
1858         u8         a_octets_received_ok_low[0x20];
1859
1860         u8         a_multicast_frames_xmitted_ok_high[0x20];
1861
1862         u8         a_multicast_frames_xmitted_ok_low[0x20];
1863
1864         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1865
1866         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1867
1868         u8         a_multicast_frames_received_ok_high[0x20];
1869
1870         u8         a_multicast_frames_received_ok_low[0x20];
1871
1872         u8         a_broadcast_frames_received_ok_high[0x20];
1873
1874         u8         a_broadcast_frames_received_ok_low[0x20];
1875
1876         u8         a_in_range_length_errors_high[0x20];
1877
1878         u8         a_in_range_length_errors_low[0x20];
1879
1880         u8         a_out_of_range_length_field_high[0x20];
1881
1882         u8         a_out_of_range_length_field_low[0x20];
1883
1884         u8         a_frame_too_long_errors_high[0x20];
1885
1886         u8         a_frame_too_long_errors_low[0x20];
1887
1888         u8         a_symbol_error_during_carrier_high[0x20];
1889
1890         u8         a_symbol_error_during_carrier_low[0x20];
1891
1892         u8         a_mac_control_frames_transmitted_high[0x20];
1893
1894         u8         a_mac_control_frames_transmitted_low[0x20];
1895
1896         u8         a_mac_control_frames_received_high[0x20];
1897
1898         u8         a_mac_control_frames_received_low[0x20];
1899
1900         u8         a_unsupported_opcodes_received_high[0x20];
1901
1902         u8         a_unsupported_opcodes_received_low[0x20];
1903
1904         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1905
1906         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1907
1908         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1909
1910         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1911
1912         u8         reserved_at_4c0[0x300];
1913 };
1914
1915 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1916         u8         life_time_counter_high[0x20];
1917
1918         u8         life_time_counter_low[0x20];
1919
1920         u8         rx_errors[0x20];
1921
1922         u8         tx_errors[0x20];
1923
1924         u8         l0_to_recovery_eieos[0x20];
1925
1926         u8         l0_to_recovery_ts[0x20];
1927
1928         u8         l0_to_recovery_framing[0x20];
1929
1930         u8         l0_to_recovery_retrain[0x20];
1931
1932         u8         crc_error_dllp[0x20];
1933
1934         u8         crc_error_tlp[0x20];
1935
1936         u8         tx_overflow_buffer_pkt_high[0x20];
1937
1938         u8         tx_overflow_buffer_pkt_low[0x20];
1939
1940         u8         outbound_stalled_reads[0x20];
1941
1942         u8         outbound_stalled_writes[0x20];
1943
1944         u8         outbound_stalled_reads_events[0x20];
1945
1946         u8         outbound_stalled_writes_events[0x20];
1947
1948         u8         reserved_at_200[0x5c0];
1949 };
1950
1951 struct mlx5_ifc_cmd_inter_comp_event_bits {
1952         u8         command_completion_vector[0x20];
1953
1954         u8         reserved_at_20[0xc0];
1955 };
1956
1957 struct mlx5_ifc_stall_vl_event_bits {
1958         u8         reserved_at_0[0x18];
1959         u8         port_num[0x1];
1960         u8         reserved_at_19[0x3];
1961         u8         vl[0x4];
1962
1963         u8         reserved_at_20[0xa0];
1964 };
1965
1966 struct mlx5_ifc_db_bf_congestion_event_bits {
1967         u8         event_subtype[0x8];
1968         u8         reserved_at_8[0x8];
1969         u8         congestion_level[0x8];
1970         u8         reserved_at_18[0x8];
1971
1972         u8         reserved_at_20[0xa0];
1973 };
1974
1975 struct mlx5_ifc_gpio_event_bits {
1976         u8         reserved_at_0[0x60];
1977
1978         u8         gpio_event_hi[0x20];
1979
1980         u8         gpio_event_lo[0x20];
1981
1982         u8         reserved_at_a0[0x40];
1983 };
1984
1985 struct mlx5_ifc_port_state_change_event_bits {
1986         u8         reserved_at_0[0x40];
1987
1988         u8         port_num[0x4];
1989         u8         reserved_at_44[0x1c];
1990
1991         u8         reserved_at_60[0x80];
1992 };
1993
1994 struct mlx5_ifc_dropped_packet_logged_bits {
1995         u8         reserved_at_0[0xe0];
1996 };
1997
1998 enum {
1999         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2000         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2001 };
2002
2003 struct mlx5_ifc_cq_error_bits {
2004         u8         reserved_at_0[0x8];
2005         u8         cqn[0x18];
2006
2007         u8         reserved_at_20[0x20];
2008
2009         u8         reserved_at_40[0x18];
2010         u8         syndrome[0x8];
2011
2012         u8         reserved_at_60[0x80];
2013 };
2014
2015 struct mlx5_ifc_rdma_page_fault_event_bits {
2016         u8         bytes_committed[0x20];
2017
2018         u8         r_key[0x20];
2019
2020         u8         reserved_at_40[0x10];
2021         u8         packet_len[0x10];
2022
2023         u8         rdma_op_len[0x20];
2024
2025         u8         rdma_va[0x40];
2026
2027         u8         reserved_at_c0[0x5];
2028         u8         rdma[0x1];
2029         u8         write[0x1];
2030         u8         requestor[0x1];
2031         u8         qp_number[0x18];
2032 };
2033
2034 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2035         u8         bytes_committed[0x20];
2036
2037         u8         reserved_at_20[0x10];
2038         u8         wqe_index[0x10];
2039
2040         u8         reserved_at_40[0x10];
2041         u8         len[0x10];
2042
2043         u8         reserved_at_60[0x60];
2044
2045         u8         reserved_at_c0[0x5];
2046         u8         rdma[0x1];
2047         u8         write_read[0x1];
2048         u8         requestor[0x1];
2049         u8         qpn[0x18];
2050 };
2051
2052 struct mlx5_ifc_qp_events_bits {
2053         u8         reserved_at_0[0xa0];
2054
2055         u8         type[0x8];
2056         u8         reserved_at_a8[0x18];
2057
2058         u8         reserved_at_c0[0x8];
2059         u8         qpn_rqn_sqn[0x18];
2060 };
2061
2062 struct mlx5_ifc_dct_events_bits {
2063         u8         reserved_at_0[0xc0];
2064
2065         u8         reserved_at_c0[0x8];
2066         u8         dct_number[0x18];
2067 };
2068
2069 struct mlx5_ifc_comp_event_bits {
2070         u8         reserved_at_0[0xc0];
2071
2072         u8         reserved_at_c0[0x8];
2073         u8         cq_number[0x18];
2074 };
2075
2076 enum {
2077         MLX5_QPC_STATE_RST        = 0x0,
2078         MLX5_QPC_STATE_INIT       = 0x1,
2079         MLX5_QPC_STATE_RTR        = 0x2,
2080         MLX5_QPC_STATE_RTS        = 0x3,
2081         MLX5_QPC_STATE_SQER       = 0x4,
2082         MLX5_QPC_STATE_ERR        = 0x6,
2083         MLX5_QPC_STATE_SQD        = 0x7,
2084         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2085 };
2086
2087 enum {
2088         MLX5_QPC_ST_RC            = 0x0,
2089         MLX5_QPC_ST_UC            = 0x1,
2090         MLX5_QPC_ST_UD            = 0x2,
2091         MLX5_QPC_ST_XRC           = 0x3,
2092         MLX5_QPC_ST_DCI           = 0x5,
2093         MLX5_QPC_ST_QP0           = 0x7,
2094         MLX5_QPC_ST_QP1           = 0x8,
2095         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2096         MLX5_QPC_ST_REG_UMR       = 0xc,
2097 };
2098
2099 enum {
2100         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2101         MLX5_QPC_PM_STATE_REARM     = 0x1,
2102         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2103         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2104 };
2105
2106 enum {
2107         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2108 };
2109
2110 enum {
2111         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2112         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2113 };
2114
2115 enum {
2116         MLX5_QPC_MTU_256_BYTES        = 0x1,
2117         MLX5_QPC_MTU_512_BYTES        = 0x2,
2118         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2119         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2120         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2121         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2122 };
2123
2124 enum {
2125         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2126         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2127         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2128         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2129         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2130         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2131         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2132         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2133 };
2134
2135 enum {
2136         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2137         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2138         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2139 };
2140
2141 enum {
2142         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2143         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2144         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2145 };
2146
2147 struct mlx5_ifc_qpc_bits {
2148         u8         state[0x4];
2149         u8         lag_tx_port_affinity[0x4];
2150         u8         st[0x8];
2151         u8         reserved_at_10[0x3];
2152         u8         pm_state[0x2];
2153         u8         reserved_at_15[0x3];
2154         u8         offload_type[0x4];
2155         u8         end_padding_mode[0x2];
2156         u8         reserved_at_1e[0x2];
2157
2158         u8         wq_signature[0x1];
2159         u8         block_lb_mc[0x1];
2160         u8         atomic_like_write_en[0x1];
2161         u8         latency_sensitive[0x1];
2162         u8         reserved_at_24[0x1];
2163         u8         drain_sigerr[0x1];
2164         u8         reserved_at_26[0x2];
2165         u8         pd[0x18];
2166
2167         u8         mtu[0x3];
2168         u8         log_msg_max[0x5];
2169         u8         reserved_at_48[0x1];
2170         u8         log_rq_size[0x4];
2171         u8         log_rq_stride[0x3];
2172         u8         no_sq[0x1];
2173         u8         log_sq_size[0x4];
2174         u8         reserved_at_55[0x6];
2175         u8         rlky[0x1];
2176         u8         ulp_stateless_offload_mode[0x4];
2177
2178         u8         counter_set_id[0x8];
2179         u8         uar_page[0x18];
2180
2181         u8         reserved_at_80[0x8];
2182         u8         user_index[0x18];
2183
2184         u8         reserved_at_a0[0x3];
2185         u8         log_page_size[0x5];
2186         u8         remote_qpn[0x18];
2187
2188         struct mlx5_ifc_ads_bits primary_address_path;
2189
2190         struct mlx5_ifc_ads_bits secondary_address_path;
2191
2192         u8         log_ack_req_freq[0x4];
2193         u8         reserved_at_384[0x4];
2194         u8         log_sra_max[0x3];
2195         u8         reserved_at_38b[0x2];
2196         u8         retry_count[0x3];
2197         u8         rnr_retry[0x3];
2198         u8         reserved_at_393[0x1];
2199         u8         fre[0x1];
2200         u8         cur_rnr_retry[0x3];
2201         u8         cur_retry_count[0x3];
2202         u8         reserved_at_39b[0x5];
2203
2204         u8         reserved_at_3a0[0x20];
2205
2206         u8         reserved_at_3c0[0x8];
2207         u8         next_send_psn[0x18];
2208
2209         u8         reserved_at_3e0[0x8];
2210         u8         cqn_snd[0x18];
2211
2212         u8         reserved_at_400[0x8];
2213         u8         deth_sqpn[0x18];
2214
2215         u8         reserved_at_420[0x20];
2216
2217         u8         reserved_at_440[0x8];
2218         u8         last_acked_psn[0x18];
2219
2220         u8         reserved_at_460[0x8];
2221         u8         ssn[0x18];
2222
2223         u8         reserved_at_480[0x8];
2224         u8         log_rra_max[0x3];
2225         u8         reserved_at_48b[0x1];
2226         u8         atomic_mode[0x4];
2227         u8         rre[0x1];
2228         u8         rwe[0x1];
2229         u8         rae[0x1];
2230         u8         reserved_at_493[0x1];
2231         u8         page_offset[0x6];
2232         u8         reserved_at_49a[0x3];
2233         u8         cd_slave_receive[0x1];
2234         u8         cd_slave_send[0x1];
2235         u8         cd_master[0x1];
2236
2237         u8         reserved_at_4a0[0x3];
2238         u8         min_rnr_nak[0x5];
2239         u8         next_rcv_psn[0x18];
2240
2241         u8         reserved_at_4c0[0x8];
2242         u8         xrcd[0x18];
2243
2244         u8         reserved_at_4e0[0x8];
2245         u8         cqn_rcv[0x18];
2246
2247         u8         dbr_addr[0x40];
2248
2249         u8         q_key[0x20];
2250
2251         u8         reserved_at_560[0x5];
2252         u8         rq_type[0x3];
2253         u8         srqn_rmpn_xrqn[0x18];
2254
2255         u8         reserved_at_580[0x8];
2256         u8         rmsn[0x18];
2257
2258         u8         hw_sq_wqebb_counter[0x10];
2259         u8         sw_sq_wqebb_counter[0x10];
2260
2261         u8         hw_rq_counter[0x20];
2262
2263         u8         sw_rq_counter[0x20];
2264
2265         u8         reserved_at_600[0x20];
2266
2267         u8         reserved_at_620[0xf];
2268         u8         cgs[0x1];
2269         u8         cs_req[0x8];
2270         u8         cs_res[0x8];
2271
2272         u8         dc_access_key[0x40];
2273
2274         u8         reserved_at_680[0xc0];
2275 };
2276
2277 struct mlx5_ifc_roce_addr_layout_bits {
2278         u8         source_l3_address[16][0x8];
2279
2280         u8         reserved_at_80[0x3];
2281         u8         vlan_valid[0x1];
2282         u8         vlan_id[0xc];
2283         u8         source_mac_47_32[0x10];
2284
2285         u8         source_mac_31_0[0x20];
2286
2287         u8         reserved_at_c0[0x14];
2288         u8         roce_l3_type[0x4];
2289         u8         roce_version[0x8];
2290
2291         u8         reserved_at_e0[0x20];
2292 };
2293
2294 union mlx5_ifc_hca_cap_union_bits {
2295         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2296         struct mlx5_ifc_odp_cap_bits odp_cap;
2297         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2298         struct mlx5_ifc_roce_cap_bits roce_cap;
2299         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2300         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2301         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2302         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2303         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2304         struct mlx5_ifc_qos_cap_bits qos_cap;
2305         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2306         u8         reserved_at_0[0x8000];
2307 };
2308
2309 enum {
2310         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2311         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2312         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2313         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2314         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2315         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2316         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2317         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2318         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2319 };
2320
2321 struct mlx5_ifc_vlan_bits {
2322         u8         ethtype[0x10];
2323         u8         prio[0x3];
2324         u8         cfi[0x1];
2325         u8         vid[0xc];
2326 };
2327
2328 struct mlx5_ifc_flow_context_bits {
2329         struct mlx5_ifc_vlan_bits push_vlan;
2330
2331         u8         group_id[0x20];
2332
2333         u8         reserved_at_40[0x8];
2334         u8         flow_tag[0x18];
2335
2336         u8         reserved_at_60[0x10];
2337         u8         action[0x10];
2338
2339         u8         reserved_at_80[0x8];
2340         u8         destination_list_size[0x18];
2341
2342         u8         reserved_at_a0[0x8];
2343         u8         flow_counter_list_size[0x18];
2344
2345         u8         encap_id[0x20];
2346
2347         u8         modify_header_id[0x20];
2348
2349         u8         reserved_at_100[0x100];
2350
2351         struct mlx5_ifc_fte_match_param_bits match_value;
2352
2353         u8         reserved_at_1200[0x600];
2354
2355         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2356 };
2357
2358 enum {
2359         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2360         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2361 };
2362
2363 struct mlx5_ifc_xrc_srqc_bits {
2364         u8         state[0x4];
2365         u8         log_xrc_srq_size[0x4];
2366         u8         reserved_at_8[0x18];
2367
2368         u8         wq_signature[0x1];
2369         u8         cont_srq[0x1];
2370         u8         reserved_at_22[0x1];
2371         u8         rlky[0x1];
2372         u8         basic_cyclic_rcv_wqe[0x1];
2373         u8         log_rq_stride[0x3];
2374         u8         xrcd[0x18];
2375
2376         u8         page_offset[0x6];
2377         u8         reserved_at_46[0x2];
2378         u8         cqn[0x18];
2379
2380         u8         reserved_at_60[0x20];
2381
2382         u8         user_index_equal_xrc_srqn[0x1];
2383         u8         reserved_at_81[0x1];
2384         u8         log_page_size[0x6];
2385         u8         user_index[0x18];
2386
2387         u8         reserved_at_a0[0x20];
2388
2389         u8         reserved_at_c0[0x8];
2390         u8         pd[0x18];
2391
2392         u8         lwm[0x10];
2393         u8         wqe_cnt[0x10];
2394
2395         u8         reserved_at_100[0x40];
2396
2397         u8         db_record_addr_h[0x20];
2398
2399         u8         db_record_addr_l[0x1e];
2400         u8         reserved_at_17e[0x2];
2401
2402         u8         reserved_at_180[0x80];
2403 };
2404
2405 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2406         u8         counter_error_queues[0x20];
2407
2408         u8         total_error_queues[0x20];
2409
2410         u8         send_queue_priority_update_flow[0x20];
2411
2412         u8         reserved_at_60[0x20];
2413
2414         u8         nic_receive_steering_discard[0x40];
2415
2416         u8         receive_discard_vport_down[0x40];
2417
2418         u8         transmit_discard_vport_down[0x40];
2419
2420         u8         reserved_at_140[0xec0];
2421 };
2422
2423 struct mlx5_ifc_traffic_counter_bits {
2424         u8         packets[0x40];
2425
2426         u8         octets[0x40];
2427 };
2428
2429 struct mlx5_ifc_tisc_bits {
2430         u8         strict_lag_tx_port_affinity[0x1];
2431         u8         reserved_at_1[0x3];
2432         u8         lag_tx_port_affinity[0x04];
2433
2434         u8         reserved_at_8[0x4];
2435         u8         prio[0x4];
2436         u8         reserved_at_10[0x10];
2437
2438         u8         reserved_at_20[0x100];
2439
2440         u8         reserved_at_120[0x8];
2441         u8         transport_domain[0x18];
2442
2443         u8         reserved_at_140[0x8];
2444         u8         underlay_qpn[0x18];
2445         u8         reserved_at_160[0x3a0];
2446 };
2447
2448 enum {
2449         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2450         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2451 };
2452
2453 enum {
2454         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2455         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2456 };
2457
2458 enum {
2459         MLX5_RX_HASH_FN_NONE           = 0x0,
2460         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2461         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2462 };
2463
2464 enum {
2465         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2466         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2467 };
2468
2469 struct mlx5_ifc_tirc_bits {
2470         u8         reserved_at_0[0x20];
2471
2472         u8         disp_type[0x4];
2473         u8         reserved_at_24[0x1c];
2474
2475         u8         reserved_at_40[0x40];
2476
2477         u8         reserved_at_80[0x4];
2478         u8         lro_timeout_period_usecs[0x10];
2479         u8         lro_enable_mask[0x4];
2480         u8         lro_max_ip_payload_size[0x8];
2481
2482         u8         reserved_at_a0[0x40];
2483
2484         u8         reserved_at_e0[0x8];
2485         u8         inline_rqn[0x18];
2486
2487         u8         rx_hash_symmetric[0x1];
2488         u8         reserved_at_101[0x1];
2489         u8         tunneled_offload_en[0x1];
2490         u8         reserved_at_103[0x5];
2491         u8         indirect_table[0x18];
2492
2493         u8         rx_hash_fn[0x4];
2494         u8         reserved_at_124[0x2];
2495         u8         self_lb_block[0x2];
2496         u8         transport_domain[0x18];
2497
2498         u8         rx_hash_toeplitz_key[10][0x20];
2499
2500         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2501
2502         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2503
2504         u8         reserved_at_2c0[0x4c0];
2505 };
2506
2507 enum {
2508         MLX5_SRQC_STATE_GOOD   = 0x0,
2509         MLX5_SRQC_STATE_ERROR  = 0x1,
2510 };
2511
2512 struct mlx5_ifc_srqc_bits {
2513         u8         state[0x4];
2514         u8         log_srq_size[0x4];
2515         u8         reserved_at_8[0x18];
2516
2517         u8         wq_signature[0x1];
2518         u8         cont_srq[0x1];
2519         u8         reserved_at_22[0x1];
2520         u8         rlky[0x1];
2521         u8         reserved_at_24[0x1];
2522         u8         log_rq_stride[0x3];
2523         u8         xrcd[0x18];
2524
2525         u8         page_offset[0x6];
2526         u8         reserved_at_46[0x2];
2527         u8         cqn[0x18];
2528
2529         u8         reserved_at_60[0x20];
2530
2531         u8         reserved_at_80[0x2];
2532         u8         log_page_size[0x6];
2533         u8         reserved_at_88[0x18];
2534
2535         u8         reserved_at_a0[0x20];
2536
2537         u8         reserved_at_c0[0x8];
2538         u8         pd[0x18];
2539
2540         u8         lwm[0x10];
2541         u8         wqe_cnt[0x10];
2542
2543         u8         reserved_at_100[0x40];
2544
2545         u8         dbr_addr[0x40];
2546
2547         u8         reserved_at_180[0x80];
2548 };
2549
2550 enum {
2551         MLX5_SQC_STATE_RST  = 0x0,
2552         MLX5_SQC_STATE_RDY  = 0x1,
2553         MLX5_SQC_STATE_ERR  = 0x3,
2554 };
2555
2556 struct mlx5_ifc_sqc_bits {
2557         u8         rlky[0x1];
2558         u8         cd_master[0x1];
2559         u8         fre[0x1];
2560         u8         flush_in_error_en[0x1];
2561         u8         allow_multi_pkt_send_wqe[0x1];
2562         u8         min_wqe_inline_mode[0x3];
2563         u8         state[0x4];
2564         u8         reg_umr[0x1];
2565         u8         allow_swp[0x1];
2566         u8         hairpin[0x1];
2567         u8         reserved_at_f[0x11];
2568
2569         u8         reserved_at_20[0x8];
2570         u8         user_index[0x18];
2571
2572         u8         reserved_at_40[0x8];
2573         u8         cqn[0x18];
2574
2575         u8         reserved_at_60[0x8];
2576         u8         hairpin_peer_rq[0x18];
2577
2578         u8         reserved_at_80[0x10];
2579         u8         hairpin_peer_vhca[0x10];
2580
2581         u8         reserved_at_a0[0x50];
2582
2583         u8         packet_pacing_rate_limit_index[0x10];
2584         u8         tis_lst_sz[0x10];
2585         u8         reserved_at_110[0x10];
2586
2587         u8         reserved_at_120[0x40];
2588
2589         u8         reserved_at_160[0x8];
2590         u8         tis_num_0[0x18];
2591
2592         struct mlx5_ifc_wq_bits wq;
2593 };
2594
2595 enum {
2596         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2597         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2598         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2599         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2600 };
2601
2602 struct mlx5_ifc_scheduling_context_bits {
2603         u8         element_type[0x8];
2604         u8         reserved_at_8[0x18];
2605
2606         u8         element_attributes[0x20];
2607
2608         u8         parent_element_id[0x20];
2609
2610         u8         reserved_at_60[0x40];
2611
2612         u8         bw_share[0x20];
2613
2614         u8         max_average_bw[0x20];
2615
2616         u8         reserved_at_e0[0x120];
2617 };
2618
2619 struct mlx5_ifc_rqtc_bits {
2620         u8         reserved_at_0[0xa0];
2621
2622         u8         reserved_at_a0[0x10];
2623         u8         rqt_max_size[0x10];
2624
2625         u8         reserved_at_c0[0x10];
2626         u8         rqt_actual_size[0x10];
2627
2628         u8         reserved_at_e0[0x6a0];
2629
2630         struct mlx5_ifc_rq_num_bits rq_num[0];
2631 };
2632
2633 enum {
2634         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2635         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2636 };
2637
2638 enum {
2639         MLX5_RQC_STATE_RST  = 0x0,
2640         MLX5_RQC_STATE_RDY  = 0x1,
2641         MLX5_RQC_STATE_ERR  = 0x3,
2642 };
2643
2644 struct mlx5_ifc_rqc_bits {
2645         u8         rlky[0x1];
2646         u8         delay_drop_en[0x1];
2647         u8         scatter_fcs[0x1];
2648         u8         vsd[0x1];
2649         u8         mem_rq_type[0x4];
2650         u8         state[0x4];
2651         u8         reserved_at_c[0x1];
2652         u8         flush_in_error_en[0x1];
2653         u8         hairpin[0x1];
2654         u8         reserved_at_f[0x11];
2655
2656         u8         reserved_at_20[0x8];
2657         u8         user_index[0x18];
2658
2659         u8         reserved_at_40[0x8];
2660         u8         cqn[0x18];
2661
2662         u8         counter_set_id[0x8];
2663         u8         reserved_at_68[0x18];
2664
2665         u8         reserved_at_80[0x8];
2666         u8         rmpn[0x18];
2667
2668         u8         reserved_at_a0[0x8];
2669         u8         hairpin_peer_sq[0x18];
2670
2671         u8         reserved_at_c0[0x10];
2672         u8         hairpin_peer_vhca[0x10];
2673
2674         u8         reserved_at_e0[0xa0];
2675
2676         struct mlx5_ifc_wq_bits wq;
2677 };
2678
2679 enum {
2680         MLX5_RMPC_STATE_RDY  = 0x1,
2681         MLX5_RMPC_STATE_ERR  = 0x3,
2682 };
2683
2684 struct mlx5_ifc_rmpc_bits {
2685         u8         reserved_at_0[0x8];
2686         u8         state[0x4];
2687         u8         reserved_at_c[0x14];
2688
2689         u8         basic_cyclic_rcv_wqe[0x1];
2690         u8         reserved_at_21[0x1f];
2691
2692         u8         reserved_at_40[0x140];
2693
2694         struct mlx5_ifc_wq_bits wq;
2695 };
2696
2697 struct mlx5_ifc_nic_vport_context_bits {
2698         u8         reserved_at_0[0x5];
2699         u8         min_wqe_inline_mode[0x3];
2700         u8         reserved_at_8[0x15];
2701         u8         disable_mc_local_lb[0x1];
2702         u8         disable_uc_local_lb[0x1];
2703         u8         roce_en[0x1];
2704
2705         u8         arm_change_event[0x1];
2706         u8         reserved_at_21[0x1a];
2707         u8         event_on_mtu[0x1];
2708         u8         event_on_promisc_change[0x1];
2709         u8         event_on_vlan_change[0x1];
2710         u8         event_on_mc_address_change[0x1];
2711         u8         event_on_uc_address_change[0x1];
2712
2713         u8         reserved_at_40[0xc];
2714
2715         u8         affiliation_criteria[0x4];
2716         u8         affiliated_vhca_id[0x10];
2717
2718         u8         reserved_at_60[0xd0];
2719
2720         u8         mtu[0x10];
2721
2722         u8         system_image_guid[0x40];
2723         u8         port_guid[0x40];
2724         u8         node_guid[0x40];
2725
2726         u8         reserved_at_200[0x140];
2727         u8         qkey_violation_counter[0x10];
2728         u8         reserved_at_350[0x430];
2729
2730         u8         promisc_uc[0x1];
2731         u8         promisc_mc[0x1];
2732         u8         promisc_all[0x1];
2733         u8         reserved_at_783[0x2];
2734         u8         allowed_list_type[0x3];
2735         u8         reserved_at_788[0xc];
2736         u8         allowed_list_size[0xc];
2737
2738         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2739
2740         u8         reserved_at_7e0[0x20];
2741
2742         u8         current_uc_mac_address[0][0x40];
2743 };
2744
2745 enum {
2746         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2747         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2748         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2749         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2750 };
2751
2752 struct mlx5_ifc_mkc_bits {
2753         u8         reserved_at_0[0x1];
2754         u8         free[0x1];
2755         u8         reserved_at_2[0xd];
2756         u8         small_fence_on_rdma_read_response[0x1];
2757         u8         umr_en[0x1];
2758         u8         a[0x1];
2759         u8         rw[0x1];
2760         u8         rr[0x1];
2761         u8         lw[0x1];
2762         u8         lr[0x1];
2763         u8         access_mode[0x2];
2764         u8         reserved_at_18[0x8];
2765
2766         u8         qpn[0x18];
2767         u8         mkey_7_0[0x8];
2768
2769         u8         reserved_at_40[0x20];
2770
2771         u8         length64[0x1];
2772         u8         bsf_en[0x1];
2773         u8         sync_umr[0x1];
2774         u8         reserved_at_63[0x2];
2775         u8         expected_sigerr_count[0x1];
2776         u8         reserved_at_66[0x1];
2777         u8         en_rinval[0x1];
2778         u8         pd[0x18];
2779
2780         u8         start_addr[0x40];
2781
2782         u8         len[0x40];
2783
2784         u8         bsf_octword_size[0x20];
2785
2786         u8         reserved_at_120[0x80];
2787
2788         u8         translations_octword_size[0x20];
2789
2790         u8         reserved_at_1c0[0x1b];
2791         u8         log_page_size[0x5];
2792
2793         u8         reserved_at_1e0[0x20];
2794 };
2795
2796 struct mlx5_ifc_pkey_bits {
2797         u8         reserved_at_0[0x10];
2798         u8         pkey[0x10];
2799 };
2800
2801 struct mlx5_ifc_array128_auto_bits {
2802         u8         array128_auto[16][0x8];
2803 };
2804
2805 struct mlx5_ifc_hca_vport_context_bits {
2806         u8         field_select[0x20];
2807
2808         u8         reserved_at_20[0xe0];
2809
2810         u8         sm_virt_aware[0x1];
2811         u8         has_smi[0x1];
2812         u8         has_raw[0x1];
2813         u8         grh_required[0x1];
2814         u8         reserved_at_104[0xc];
2815         u8         port_physical_state[0x4];
2816         u8         vport_state_policy[0x4];
2817         u8         port_state[0x4];
2818         u8         vport_state[0x4];
2819
2820         u8         reserved_at_120[0x20];
2821
2822         u8         system_image_guid[0x40];
2823
2824         u8         port_guid[0x40];
2825
2826         u8         node_guid[0x40];
2827
2828         u8         cap_mask1[0x20];
2829
2830         u8         cap_mask1_field_select[0x20];
2831
2832         u8         cap_mask2[0x20];
2833
2834         u8         cap_mask2_field_select[0x20];
2835
2836         u8         reserved_at_280[0x80];
2837
2838         u8         lid[0x10];
2839         u8         reserved_at_310[0x4];
2840         u8         init_type_reply[0x4];
2841         u8         lmc[0x3];
2842         u8         subnet_timeout[0x5];
2843
2844         u8         sm_lid[0x10];
2845         u8         sm_sl[0x4];
2846         u8         reserved_at_334[0xc];
2847
2848         u8         qkey_violation_counter[0x10];
2849         u8         pkey_violation_counter[0x10];
2850
2851         u8         reserved_at_360[0xca0];
2852 };
2853
2854 struct mlx5_ifc_esw_vport_context_bits {
2855         u8         reserved_at_0[0x3];
2856         u8         vport_svlan_strip[0x1];
2857         u8         vport_cvlan_strip[0x1];
2858         u8         vport_svlan_insert[0x1];
2859         u8         vport_cvlan_insert[0x2];
2860         u8         reserved_at_8[0x18];
2861
2862         u8         reserved_at_20[0x20];
2863
2864         u8         svlan_cfi[0x1];
2865         u8         svlan_pcp[0x3];
2866         u8         svlan_id[0xc];
2867         u8         cvlan_cfi[0x1];
2868         u8         cvlan_pcp[0x3];
2869         u8         cvlan_id[0xc];
2870
2871         u8         reserved_at_60[0x7a0];
2872 };
2873
2874 enum {
2875         MLX5_EQC_STATUS_OK                = 0x0,
2876         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2877 };
2878
2879 enum {
2880         MLX5_EQC_ST_ARMED  = 0x9,
2881         MLX5_EQC_ST_FIRED  = 0xa,
2882 };
2883
2884 struct mlx5_ifc_eqc_bits {
2885         u8         status[0x4];
2886         u8         reserved_at_4[0x9];
2887         u8         ec[0x1];
2888         u8         oi[0x1];
2889         u8         reserved_at_f[0x5];
2890         u8         st[0x4];
2891         u8         reserved_at_18[0x8];
2892
2893         u8         reserved_at_20[0x20];
2894
2895         u8         reserved_at_40[0x14];
2896         u8         page_offset[0x6];
2897         u8         reserved_at_5a[0x6];
2898
2899         u8         reserved_at_60[0x3];
2900         u8         log_eq_size[0x5];
2901         u8         uar_page[0x18];
2902
2903         u8         reserved_at_80[0x20];
2904
2905         u8         reserved_at_a0[0x18];
2906         u8         intr[0x8];
2907
2908         u8         reserved_at_c0[0x3];
2909         u8         log_page_size[0x5];
2910         u8         reserved_at_c8[0x18];
2911
2912         u8         reserved_at_e0[0x60];
2913
2914         u8         reserved_at_140[0x8];
2915         u8         consumer_counter[0x18];
2916
2917         u8         reserved_at_160[0x8];
2918         u8         producer_counter[0x18];
2919
2920         u8         reserved_at_180[0x80];
2921 };
2922
2923 enum {
2924         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2925         MLX5_DCTC_STATE_DRAINING  = 0x1,
2926         MLX5_DCTC_STATE_DRAINED   = 0x2,
2927 };
2928
2929 enum {
2930         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2931         MLX5_DCTC_CS_RES_NA         = 0x1,
2932         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2933 };
2934
2935 enum {
2936         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2937         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2938         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2939         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2940         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2941 };
2942
2943 struct mlx5_ifc_dctc_bits {
2944         u8         reserved_at_0[0x4];
2945         u8         state[0x4];
2946         u8         reserved_at_8[0x18];
2947
2948         u8         reserved_at_20[0x8];
2949         u8         user_index[0x18];
2950
2951         u8         reserved_at_40[0x8];
2952         u8         cqn[0x18];
2953
2954         u8         counter_set_id[0x8];
2955         u8         atomic_mode[0x4];
2956         u8         rre[0x1];
2957         u8         rwe[0x1];
2958         u8         rae[0x1];
2959         u8         atomic_like_write_en[0x1];
2960         u8         latency_sensitive[0x1];
2961         u8         rlky[0x1];
2962         u8         free_ar[0x1];
2963         u8         reserved_at_73[0xd];
2964
2965         u8         reserved_at_80[0x8];
2966         u8         cs_res[0x8];
2967         u8         reserved_at_90[0x3];
2968         u8         min_rnr_nak[0x5];
2969         u8         reserved_at_98[0x8];
2970
2971         u8         reserved_at_a0[0x8];
2972         u8         srqn_xrqn[0x18];
2973
2974         u8         reserved_at_c0[0x8];
2975         u8         pd[0x18];
2976
2977         u8         tclass[0x8];
2978         u8         reserved_at_e8[0x4];
2979         u8         flow_label[0x14];
2980
2981         u8         dc_access_key[0x40];
2982
2983         u8         reserved_at_140[0x5];
2984         u8         mtu[0x3];
2985         u8         port[0x8];
2986         u8         pkey_index[0x10];
2987
2988         u8         reserved_at_160[0x8];
2989         u8         my_addr_index[0x8];
2990         u8         reserved_at_170[0x8];
2991         u8         hop_limit[0x8];
2992
2993         u8         dc_access_key_violation_count[0x20];
2994
2995         u8         reserved_at_1a0[0x14];
2996         u8         dei_cfi[0x1];
2997         u8         eth_prio[0x3];
2998         u8         ecn[0x2];
2999         u8         dscp[0x6];
3000
3001         u8         reserved_at_1c0[0x40];
3002 };
3003
3004 enum {
3005         MLX5_CQC_STATUS_OK             = 0x0,
3006         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3007         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3008 };
3009
3010 enum {
3011         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3012         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3013 };
3014
3015 enum {
3016         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3017         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3018         MLX5_CQC_ST_FIRED                                 = 0xa,
3019 };
3020
3021 enum {
3022         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3023         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3024         MLX5_CQ_PERIOD_NUM_MODES
3025 };
3026
3027 struct mlx5_ifc_cqc_bits {
3028         u8         status[0x4];
3029         u8         reserved_at_4[0x4];
3030         u8         cqe_sz[0x3];
3031         u8         cc[0x1];
3032         u8         reserved_at_c[0x1];
3033         u8         scqe_break_moderation_en[0x1];
3034         u8         oi[0x1];
3035         u8         cq_period_mode[0x2];
3036         u8         cqe_comp_en[0x1];
3037         u8         mini_cqe_res_format[0x2];
3038         u8         st[0x4];
3039         u8         reserved_at_18[0x8];
3040
3041         u8         reserved_at_20[0x20];
3042
3043         u8         reserved_at_40[0x14];
3044         u8         page_offset[0x6];
3045         u8         reserved_at_5a[0x6];
3046
3047         u8         reserved_at_60[0x3];
3048         u8         log_cq_size[0x5];
3049         u8         uar_page[0x18];
3050
3051         u8         reserved_at_80[0x4];
3052         u8         cq_period[0xc];
3053         u8         cq_max_count[0x10];
3054
3055         u8         reserved_at_a0[0x18];
3056         u8         c_eqn[0x8];
3057
3058         u8         reserved_at_c0[0x3];
3059         u8         log_page_size[0x5];
3060         u8         reserved_at_c8[0x18];
3061
3062         u8         reserved_at_e0[0x20];
3063
3064         u8         reserved_at_100[0x8];
3065         u8         last_notified_index[0x18];
3066
3067         u8         reserved_at_120[0x8];
3068         u8         last_solicit_index[0x18];
3069
3070         u8         reserved_at_140[0x8];
3071         u8         consumer_counter[0x18];
3072
3073         u8         reserved_at_160[0x8];
3074         u8         producer_counter[0x18];
3075
3076         u8         reserved_at_180[0x40];
3077
3078         u8         dbr_addr[0x40];
3079 };
3080
3081 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3082         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3083         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3084         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3085         u8         reserved_at_0[0x800];
3086 };
3087
3088 struct mlx5_ifc_query_adapter_param_block_bits {
3089         u8         reserved_at_0[0xc0];
3090
3091         u8         reserved_at_c0[0x8];
3092         u8         ieee_vendor_id[0x18];
3093
3094         u8         reserved_at_e0[0x10];
3095         u8         vsd_vendor_id[0x10];
3096
3097         u8         vsd[208][0x8];
3098
3099         u8         vsd_contd_psid[16][0x8];
3100 };
3101
3102 enum {
3103         MLX5_XRQC_STATE_GOOD   = 0x0,
3104         MLX5_XRQC_STATE_ERROR  = 0x1,
3105 };
3106
3107 enum {
3108         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3109         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3110 };
3111
3112 enum {
3113         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3114 };
3115
3116 struct mlx5_ifc_tag_matching_topology_context_bits {
3117         u8         log_matching_list_sz[0x4];
3118         u8         reserved_at_4[0xc];
3119         u8         append_next_index[0x10];
3120
3121         u8         sw_phase_cnt[0x10];
3122         u8         hw_phase_cnt[0x10];
3123
3124         u8         reserved_at_40[0x40];
3125 };
3126
3127 struct mlx5_ifc_xrqc_bits {
3128         u8         state[0x4];
3129         u8         rlkey[0x1];
3130         u8         reserved_at_5[0xf];
3131         u8         topology[0x4];
3132         u8         reserved_at_18[0x4];
3133         u8         offload[0x4];
3134
3135         u8         reserved_at_20[0x8];
3136         u8         user_index[0x18];
3137
3138         u8         reserved_at_40[0x8];
3139         u8         cqn[0x18];
3140
3141         u8         reserved_at_60[0xa0];
3142
3143         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3144
3145         u8         reserved_at_180[0x280];
3146
3147         struct mlx5_ifc_wq_bits wq;
3148 };
3149
3150 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3151         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3152         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3153         u8         reserved_at_0[0x20];
3154 };
3155
3156 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3157         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3158         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3159         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3160         u8         reserved_at_0[0x20];
3161 };
3162
3163 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3164         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3165         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3166         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3167         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3168         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3169         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3170         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3171         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3172         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3173         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3174         u8         reserved_at_0[0x7c0];
3175 };
3176
3177 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3178         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3179         u8         reserved_at_0[0x7c0];
3180 };
3181
3182 union mlx5_ifc_event_auto_bits {
3183         struct mlx5_ifc_comp_event_bits comp_event;
3184         struct mlx5_ifc_dct_events_bits dct_events;
3185         struct mlx5_ifc_qp_events_bits qp_events;
3186         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3187         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3188         struct mlx5_ifc_cq_error_bits cq_error;
3189         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3190         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3191         struct mlx5_ifc_gpio_event_bits gpio_event;
3192         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3193         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3194         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3195         u8         reserved_at_0[0xe0];
3196 };
3197
3198 struct mlx5_ifc_health_buffer_bits {
3199         u8         reserved_at_0[0x100];
3200
3201         u8         assert_existptr[0x20];
3202
3203         u8         assert_callra[0x20];
3204
3205         u8         reserved_at_140[0x40];
3206
3207         u8         fw_version[0x20];
3208
3209         u8         hw_id[0x20];
3210
3211         u8         reserved_at_1c0[0x20];
3212
3213         u8         irisc_index[0x8];
3214         u8         synd[0x8];
3215         u8         ext_synd[0x10];
3216 };
3217
3218 struct mlx5_ifc_register_loopback_control_bits {
3219         u8         no_lb[0x1];
3220         u8         reserved_at_1[0x7];
3221         u8         port[0x8];
3222         u8         reserved_at_10[0x10];
3223
3224         u8         reserved_at_20[0x60];
3225 };
3226
3227 struct mlx5_ifc_vport_tc_element_bits {
3228         u8         traffic_class[0x4];
3229         u8         reserved_at_4[0xc];
3230         u8         vport_number[0x10];
3231 };
3232
3233 struct mlx5_ifc_vport_element_bits {
3234         u8         reserved_at_0[0x10];
3235         u8         vport_number[0x10];
3236 };
3237
3238 enum {
3239         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3240         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3241         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3242 };
3243
3244 struct mlx5_ifc_tsar_element_bits {
3245         u8         reserved_at_0[0x8];
3246         u8         tsar_type[0x8];
3247         u8         reserved_at_10[0x10];
3248 };
3249
3250 enum {
3251         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3252         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3253 };
3254
3255 struct mlx5_ifc_teardown_hca_out_bits {
3256         u8         status[0x8];
3257         u8         reserved_at_8[0x18];
3258
3259         u8         syndrome[0x20];