b4ea8a9914c4f66f93db6e3a1953f9787b4018e4
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64
65 enum {
66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71
72 enum {
73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76
77 enum {
78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
96         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
132         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
133         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
134         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
135         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
136         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
137         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
138         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
139         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
140         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
141         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
142         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
143         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
144         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
145         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
146         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
147         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
148         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
149         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
150         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
151         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
152         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
153         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
154         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
155         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
156         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
157         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
158         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
159         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
160         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
161         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
162         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
163         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
164         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
165         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
166         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
167         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
168         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
169         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
170         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
171         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
172         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
173         MLX5_CMD_OP_NOP                           = 0x80d,
174         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
175         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
178         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
179         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
180         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
181         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
182         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
183         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
184         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
185         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
186         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
187         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
188         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
189         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
190         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
191         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
192         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
193         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
194         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
195         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
196         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
197         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
198         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
199         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
200         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
201         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
202         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
203         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
204         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
205         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
206         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
207         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
208         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
209         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
210         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
211         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
212         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
213         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
214         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
215         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
216         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
217         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
218         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
219         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
220         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
221         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
222         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
223         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
224         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
225         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
226         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
227         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
228         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
229         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
230         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
231         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
232         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
233         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
234         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
235         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
236         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
237         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
238         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
239         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
240         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
241         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
242         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
243         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
244         MLX5_CMD_OP_MAX
245 };
246
247 struct mlx5_ifc_flow_table_fields_supported_bits {
248         u8         outer_dmac[0x1];
249         u8         outer_smac[0x1];
250         u8         outer_ether_type[0x1];
251         u8         outer_ip_version[0x1];
252         u8         outer_first_prio[0x1];
253         u8         outer_first_cfi[0x1];
254         u8         outer_first_vid[0x1];
255         u8         outer_ipv4_ttl[0x1];
256         u8         outer_second_prio[0x1];
257         u8         outer_second_cfi[0x1];
258         u8         outer_second_vid[0x1];
259         u8         reserved_at_b[0x1];
260         u8         outer_sip[0x1];
261         u8         outer_dip[0x1];
262         u8         outer_frag[0x1];
263         u8         outer_ip_protocol[0x1];
264         u8         outer_ip_ecn[0x1];
265         u8         outer_ip_dscp[0x1];
266         u8         outer_udp_sport[0x1];
267         u8         outer_udp_dport[0x1];
268         u8         outer_tcp_sport[0x1];
269         u8         outer_tcp_dport[0x1];
270         u8         outer_tcp_flags[0x1];
271         u8         outer_gre_protocol[0x1];
272         u8         outer_gre_key[0x1];
273         u8         outer_vxlan_vni[0x1];
274         u8         reserved_at_1a[0x5];
275         u8         source_eswitch_port[0x1];
276
277         u8         inner_dmac[0x1];
278         u8         inner_smac[0x1];
279         u8         inner_ether_type[0x1];
280         u8         inner_ip_version[0x1];
281         u8         inner_first_prio[0x1];
282         u8         inner_first_cfi[0x1];
283         u8         inner_first_vid[0x1];
284         u8         reserved_at_27[0x1];
285         u8         inner_second_prio[0x1];
286         u8         inner_second_cfi[0x1];
287         u8         inner_second_vid[0x1];
288         u8         reserved_at_2b[0x1];
289         u8         inner_sip[0x1];
290         u8         inner_dip[0x1];
291         u8         inner_frag[0x1];
292         u8         inner_ip_protocol[0x1];
293         u8         inner_ip_ecn[0x1];
294         u8         inner_ip_dscp[0x1];
295         u8         inner_udp_sport[0x1];
296         u8         inner_udp_dport[0x1];
297         u8         inner_tcp_sport[0x1];
298         u8         inner_tcp_dport[0x1];
299         u8         inner_tcp_flags[0x1];
300         u8         reserved_at_37[0x9];
301         u8         reserved_at_40[0x17];
302         u8         outer_esp_spi[0x1];
303         u8         reserved_at_58[0x2];
304         u8         bth_dst_qp[0x1];
305
306         u8         reserved_at_5b[0x25];
307 };
308
309 struct mlx5_ifc_flow_table_prop_layout_bits {
310         u8         ft_support[0x1];
311         u8         reserved_at_1[0x1];
312         u8         flow_counter[0x1];
313         u8         flow_modify_en[0x1];
314         u8         modify_root[0x1];
315         u8         identified_miss_table_mode[0x1];
316         u8         flow_table_modify[0x1];
317         u8         encap[0x1];
318         u8         decap[0x1];
319         u8         reserved_at_9[0x1];
320         u8         pop_vlan[0x1];
321         u8         push_vlan[0x1];
322         u8         reserved_at_c[0x14];
323
324         u8         reserved_at_20[0x2];
325         u8         log_max_ft_size[0x6];
326         u8         log_max_modify_header_context[0x8];
327         u8         max_modify_header_actions[0x8];
328         u8         max_ft_level[0x8];
329
330         u8         reserved_at_40[0x20];
331
332         u8         reserved_at_60[0x18];
333         u8         log_max_ft_num[0x8];
334
335         u8         reserved_at_80[0x18];
336         u8         log_max_destination[0x8];
337
338         u8         log_max_flow_counter[0x8];
339         u8         reserved_at_a8[0x10];
340         u8         log_max_flow[0x8];
341
342         u8         reserved_at_c0[0x40];
343
344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347 };
348
349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
350         u8         send[0x1];
351         u8         receive[0x1];
352         u8         write[0x1];
353         u8         read[0x1];
354         u8         atomic[0x1];
355         u8         srq_receive[0x1];
356         u8         reserved_at_6[0x1a];
357 };
358
359 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
360         u8         smac_47_16[0x20];
361
362         u8         smac_15_0[0x10];
363         u8         ethertype[0x10];
364
365         u8         dmac_47_16[0x20];
366
367         u8         dmac_15_0[0x10];
368         u8         first_prio[0x3];
369         u8         first_cfi[0x1];
370         u8         first_vid[0xc];
371
372         u8         ip_protocol[0x8];
373         u8         ip_dscp[0x6];
374         u8         ip_ecn[0x2];
375         u8         cvlan_tag[0x1];
376         u8         svlan_tag[0x1];
377         u8         frag[0x1];
378         u8         ip_version[0x4];
379         u8         tcp_flags[0x9];
380
381         u8         tcp_sport[0x10];
382         u8         tcp_dport[0x10];
383
384         u8         reserved_at_c0[0x18];
385         u8         ttl_hoplimit[0x8];
386
387         u8         udp_sport[0x10];
388         u8         udp_dport[0x10];
389
390         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
391
392         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
393 };
394
395 struct mlx5_ifc_fte_match_set_misc_bits {
396         u8         reserved_at_0[0x8];
397         u8         source_sqn[0x18];
398
399         u8         source_eswitch_owner_vhca_id[0x10];
400         u8         source_port[0x10];
401
402         u8         outer_second_prio[0x3];
403         u8         outer_second_cfi[0x1];
404         u8         outer_second_vid[0xc];
405         u8         inner_second_prio[0x3];
406         u8         inner_second_cfi[0x1];
407         u8         inner_second_vid[0xc];
408
409         u8         outer_second_cvlan_tag[0x1];
410         u8         inner_second_cvlan_tag[0x1];
411         u8         outer_second_svlan_tag[0x1];
412         u8         inner_second_svlan_tag[0x1];
413         u8         reserved_at_64[0xc];
414         u8         gre_protocol[0x10];
415
416         u8         gre_key_h[0x18];
417         u8         gre_key_l[0x8];
418
419         u8         vxlan_vni[0x18];
420         u8         reserved_at_b8[0x8];
421
422         u8         reserved_at_c0[0x20];
423
424         u8         reserved_at_e0[0xc];
425         u8         outer_ipv6_flow_label[0x14];
426
427         u8         reserved_at_100[0xc];
428         u8         inner_ipv6_flow_label[0x14];
429
430         u8         reserved_at_120[0x28];
431         u8         bth_dst_qp[0x18];
432         u8         reserved_at_160[0x20];
433         u8         outer_esp_spi[0x20];
434         u8         reserved_at_1a0[0x60];
435 };
436
437 struct mlx5_ifc_cmd_pas_bits {
438         u8         pa_h[0x20];
439
440         u8         pa_l[0x14];
441         u8         reserved_at_34[0xc];
442 };
443
444 struct mlx5_ifc_uint64_bits {
445         u8         hi[0x20];
446
447         u8         lo[0x20];
448 };
449
450 enum {
451         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
452         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
453         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
454         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
455         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
456         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
457         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
458         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
459         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
460         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
461 };
462
463 struct mlx5_ifc_ads_bits {
464         u8         fl[0x1];
465         u8         free_ar[0x1];
466         u8         reserved_at_2[0xe];
467         u8         pkey_index[0x10];
468
469         u8         reserved_at_20[0x8];
470         u8         grh[0x1];
471         u8         mlid[0x7];
472         u8         rlid[0x10];
473
474         u8         ack_timeout[0x5];
475         u8         reserved_at_45[0x3];
476         u8         src_addr_index[0x8];
477         u8         reserved_at_50[0x4];
478         u8         stat_rate[0x4];
479         u8         hop_limit[0x8];
480
481         u8         reserved_at_60[0x4];
482         u8         tclass[0x8];
483         u8         flow_label[0x14];
484
485         u8         rgid_rip[16][0x8];
486
487         u8         reserved_at_100[0x4];
488         u8         f_dscp[0x1];
489         u8         f_ecn[0x1];
490         u8         reserved_at_106[0x1];
491         u8         f_eth_prio[0x1];
492         u8         ecn[0x2];
493         u8         dscp[0x6];
494         u8         udp_sport[0x10];
495
496         u8         dei_cfi[0x1];
497         u8         eth_prio[0x3];
498         u8         sl[0x4];
499         u8         vhca_port_num[0x8];
500         u8         rmac_47_32[0x10];
501
502         u8         rmac_31_0[0x20];
503 };
504
505 struct mlx5_ifc_flow_table_nic_cap_bits {
506         u8         nic_rx_multi_path_tirs[0x1];
507         u8         nic_rx_multi_path_tirs_fts[0x1];
508         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
509         u8         reserved_at_3[0x1fd];
510
511         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
512
513         u8         reserved_at_400[0x200];
514
515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
516
517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
518
519         u8         reserved_at_a00[0x200];
520
521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
522
523         u8         reserved_at_e00[0x7200];
524 };
525
526 struct mlx5_ifc_flow_table_eswitch_cap_bits {
527         u8     reserved_at_0[0x200];
528
529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
530
531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
532
533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
534
535         u8      reserved_at_800[0x7800];
536 };
537
538 struct mlx5_ifc_e_switch_cap_bits {
539         u8         vport_svlan_strip[0x1];
540         u8         vport_cvlan_strip[0x1];
541         u8         vport_svlan_insert[0x1];
542         u8         vport_cvlan_insert_if_not_exist[0x1];
543         u8         vport_cvlan_insert_overwrite[0x1];
544         u8         reserved_at_5[0x18];
545         u8         merged_eswitch[0x1];
546         u8         nic_vport_node_guid_modify[0x1];
547         u8         nic_vport_port_guid_modify[0x1];
548
549         u8         vxlan_encap_decap[0x1];
550         u8         nvgre_encap_decap[0x1];
551         u8         reserved_at_22[0x9];
552         u8         log_max_encap_headers[0x5];
553         u8         reserved_2b[0x6];
554         u8         max_encap_header_size[0xa];
555
556         u8         reserved_40[0x7c0];
557
558 };
559
560 struct mlx5_ifc_qos_cap_bits {
561         u8         packet_pacing[0x1];
562         u8         esw_scheduling[0x1];
563         u8         esw_bw_share[0x1];
564         u8         esw_rate_limit[0x1];
565         u8         reserved_at_4[0x1];
566         u8         packet_pacing_burst_bound[0x1];
567         u8         packet_pacing_typical_size[0x1];
568         u8         reserved_at_7[0x19];
569
570         u8         reserved_at_20[0x20];
571
572         u8         packet_pacing_max_rate[0x20];
573
574         u8         packet_pacing_min_rate[0x20];
575
576         u8         reserved_at_80[0x10];
577         u8         packet_pacing_rate_table_size[0x10];
578
579         u8         esw_element_type[0x10];
580         u8         esw_tsar_type[0x10];
581
582         u8         reserved_at_c0[0x10];
583         u8         max_qos_para_vport[0x10];
584
585         u8         max_tsar_bw_share[0x20];
586
587         u8         reserved_at_100[0x700];
588 };
589
590 struct mlx5_ifc_debug_cap_bits {
591         u8         reserved_at_0[0x20];
592
593         u8         reserved_at_20[0x2];
594         u8         stall_detect[0x1];
595         u8         reserved_at_23[0x1d];
596
597         u8         reserved_at_40[0x7c0];
598 };
599
600 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
601         u8         csum_cap[0x1];
602         u8         vlan_cap[0x1];
603         u8         lro_cap[0x1];
604         u8         lro_psh_flag[0x1];
605         u8         lro_time_stamp[0x1];
606         u8         reserved_at_5[0x2];
607         u8         wqe_vlan_insert[0x1];
608         u8         self_lb_en_modifiable[0x1];
609         u8         reserved_at_9[0x2];
610         u8         max_lso_cap[0x5];
611         u8         multi_pkt_send_wqe[0x2];
612         u8         wqe_inline_mode[0x2];
613         u8         rss_ind_tbl_cap[0x4];
614         u8         reg_umr_sq[0x1];
615         u8         scatter_fcs[0x1];
616         u8         enhanced_multi_pkt_send_wqe[0x1];
617         u8         tunnel_lso_const_out_ip_id[0x1];
618         u8         reserved_at_1c[0x2];
619         u8         tunnel_stateless_gre[0x1];
620         u8         tunnel_stateless_vxlan[0x1];
621
622         u8         swp[0x1];
623         u8         swp_csum[0x1];
624         u8         swp_lso[0x1];
625         u8         reserved_at_23[0x1b];
626         u8         max_geneve_opt_len[0x1];
627         u8         tunnel_stateless_geneve_rx[0x1];
628
629         u8         reserved_at_40[0x10];
630         u8         lro_min_mss_size[0x10];
631
632         u8         reserved_at_60[0x120];
633
634         u8         lro_timer_supported_periods[4][0x20];
635
636         u8         reserved_at_200[0x600];
637 };
638
639 struct mlx5_ifc_roce_cap_bits {
640         u8         roce_apm[0x1];
641         u8         reserved_at_1[0x1f];
642
643         u8         reserved_at_20[0x60];
644
645         u8         reserved_at_80[0xc];
646         u8         l3_type[0x4];
647         u8         reserved_at_90[0x8];
648         u8         roce_version[0x8];
649
650         u8         reserved_at_a0[0x10];
651         u8         r_roce_dest_udp_port[0x10];
652
653         u8         r_roce_max_src_udp_port[0x10];
654         u8         r_roce_min_src_udp_port[0x10];
655
656         u8         reserved_at_e0[0x10];
657         u8         roce_address_table_size[0x10];
658
659         u8         reserved_at_100[0x700];
660 };
661
662 struct mlx5_ifc_device_mem_cap_bits {
663         u8         memic[0x1];
664         u8         reserved_at_1[0x1f];
665
666         u8         reserved_at_20[0xb];
667         u8         log_min_memic_alloc_size[0x5];
668         u8         reserved_at_30[0x8];
669         u8         log_max_memic_addr_alignment[0x8];
670
671         u8         memic_bar_start_addr[0x40];
672
673         u8         memic_bar_size[0x20];
674
675         u8         max_memic_size[0x20];
676
677         u8         reserved_at_c0[0x740];
678 };
679
680 enum {
681         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
682         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
683         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
684         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
685         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
686         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
687         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
688         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
689         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
690 };
691
692 enum {
693         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
694         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
695         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
696         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
701         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
702 };
703
704 struct mlx5_ifc_atomic_caps_bits {
705         u8         reserved_at_0[0x40];
706
707         u8         atomic_req_8B_endianness_mode[0x2];
708         u8         reserved_at_42[0x4];
709         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
710
711         u8         reserved_at_47[0x19];
712
713         u8         reserved_at_60[0x20];
714
715         u8         reserved_at_80[0x10];
716         u8         atomic_operations[0x10];
717
718         u8         reserved_at_a0[0x10];
719         u8         atomic_size_qp[0x10];
720
721         u8         reserved_at_c0[0x10];
722         u8         atomic_size_dc[0x10];
723
724         u8         reserved_at_e0[0x720];
725 };
726
727 struct mlx5_ifc_odp_cap_bits {
728         u8         reserved_at_0[0x40];
729
730         u8         sig[0x1];
731         u8         reserved_at_41[0x1f];
732
733         u8         reserved_at_60[0x20];
734
735         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
736
737         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
738
739         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
740
741         u8         reserved_at_e0[0x720];
742 };
743
744 struct mlx5_ifc_calc_op {
745         u8        reserved_at_0[0x10];
746         u8        reserved_at_10[0x9];
747         u8        op_swap_endianness[0x1];
748         u8        op_min[0x1];
749         u8        op_xor[0x1];
750         u8        op_or[0x1];
751         u8        op_and[0x1];
752         u8        op_max[0x1];
753         u8        op_add[0x1];
754 };
755
756 struct mlx5_ifc_vector_calc_cap_bits {
757         u8         calc_matrix[0x1];
758         u8         reserved_at_1[0x1f];
759         u8         reserved_at_20[0x8];
760         u8         max_vec_count[0x8];
761         u8         reserved_at_30[0xd];
762         u8         max_chunk_size[0x3];
763         struct mlx5_ifc_calc_op calc0;
764         struct mlx5_ifc_calc_op calc1;
765         struct mlx5_ifc_calc_op calc2;
766         struct mlx5_ifc_calc_op calc3;
767
768         u8         reserved_at_e0[0x720];
769 };
770
771 enum {
772         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
773         MLX5_WQ_TYPE_CYCLIC       = 0x1,
774         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
775         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
776 };
777
778 enum {
779         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
780         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
781 };
782
783 enum {
784         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
785         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
786         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
787         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
788         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
789 };
790
791 enum {
792         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
793         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
794         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
795         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
796         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
797         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
798 };
799
800 enum {
801         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
802         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
803 };
804
805 enum {
806         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
807         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
808         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
809 };
810
811 enum {
812         MLX5_CAP_PORT_TYPE_IB  = 0x0,
813         MLX5_CAP_PORT_TYPE_ETH = 0x1,
814 };
815
816 enum {
817         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
818         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
819         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
820 };
821
822 struct mlx5_ifc_cmd_hca_cap_bits {
823         u8         reserved_at_0[0x30];
824         u8         vhca_id[0x10];
825
826         u8         reserved_at_40[0x40];
827
828         u8         log_max_srq_sz[0x8];
829         u8         log_max_qp_sz[0x8];
830         u8         reserved_at_90[0xb];
831         u8         log_max_qp[0x5];
832
833         u8         reserved_at_a0[0xb];
834         u8         log_max_srq[0x5];
835         u8         reserved_at_b0[0x10];
836
837         u8         reserved_at_c0[0x8];
838         u8         log_max_cq_sz[0x8];
839         u8         reserved_at_d0[0xb];
840         u8         log_max_cq[0x5];
841
842         u8         log_max_eq_sz[0x8];
843         u8         reserved_at_e8[0x2];
844         u8         log_max_mkey[0x6];
845         u8         reserved_at_f0[0xc];
846         u8         log_max_eq[0x4];
847
848         u8         max_indirection[0x8];
849         u8         fixed_buffer_size[0x1];
850         u8         log_max_mrw_sz[0x7];
851         u8         force_teardown[0x1];
852         u8         reserved_at_111[0x1];
853         u8         log_max_bsf_list_size[0x6];
854         u8         umr_extended_translation_offset[0x1];
855         u8         null_mkey[0x1];
856         u8         log_max_klm_list_size[0x6];
857
858         u8         reserved_at_120[0xa];
859         u8         log_max_ra_req_dc[0x6];
860         u8         reserved_at_130[0xa];
861         u8         log_max_ra_res_dc[0x6];
862
863         u8         reserved_at_140[0xa];
864         u8         log_max_ra_req_qp[0x6];
865         u8         reserved_at_150[0xa];
866         u8         log_max_ra_res_qp[0x6];
867
868         u8         end_pad[0x1];
869         u8         cc_query_allowed[0x1];
870         u8         cc_modify_allowed[0x1];
871         u8         start_pad[0x1];
872         u8         cache_line_128byte[0x1];
873         u8         reserved_at_165[0xa];
874         u8         qcam_reg[0x1];
875         u8         gid_table_size[0x10];
876
877         u8         out_of_seq_cnt[0x1];
878         u8         vport_counters[0x1];
879         u8         retransmission_q_counters[0x1];
880         u8         debug[0x1];
881         u8         modify_rq_counter_set_id[0x1];
882         u8         rq_delay_drop[0x1];
883         u8         max_qp_cnt[0xa];
884         u8         pkey_table_size[0x10];
885
886         u8         vport_group_manager[0x1];
887         u8         vhca_group_manager[0x1];
888         u8         ib_virt[0x1];
889         u8         eth_virt[0x1];
890         u8         vnic_env_queue_counters[0x1];
891         u8         ets[0x1];
892         u8         nic_flow_table[0x1];
893         u8         eswitch_flow_table[0x1];
894         u8         device_memory[0x1];
895         u8         mcam_reg[0x1];
896         u8         pcam_reg[0x1];
897         u8         local_ca_ack_delay[0x5];
898         u8         port_module_event[0x1];
899         u8         enhanced_error_q_counters[0x1];
900         u8         ports_check[0x1];
901         u8         reserved_at_1b3[0x1];
902         u8         disable_link_up[0x1];
903         u8         beacon_led[0x1];
904         u8         port_type[0x2];
905         u8         num_ports[0x8];
906
907         u8         reserved_at_1c0[0x1];
908         u8         pps[0x1];
909         u8         pps_modify[0x1];
910         u8         log_max_msg[0x5];
911         u8         reserved_at_1c8[0x4];
912         u8         max_tc[0x4];
913         u8         reserved_at_1d0[0x1];
914         u8         dcbx[0x1];
915         u8         general_notification_event[0x1];
916         u8         reserved_at_1d3[0x2];
917         u8         fpga[0x1];
918         u8         rol_s[0x1];
919         u8         rol_g[0x1];
920         u8         reserved_at_1d8[0x1];
921         u8         wol_s[0x1];
922         u8         wol_g[0x1];
923         u8         wol_a[0x1];
924         u8         wol_b[0x1];
925         u8         wol_m[0x1];
926         u8         wol_u[0x1];
927         u8         wol_p[0x1];
928
929         u8         stat_rate_support[0x10];
930         u8         reserved_at_1f0[0xc];
931         u8         cqe_version[0x4];
932
933         u8         compact_address_vector[0x1];
934         u8         striding_rq[0x1];
935         u8         reserved_at_202[0x1];
936         u8         ipoib_enhanced_offloads[0x1];
937         u8         ipoib_basic_offloads[0x1];
938         u8         reserved_at_205[0x1];
939         u8         repeated_block_disabled[0x1];
940         u8         umr_modify_entity_size_disabled[0x1];
941         u8         umr_modify_atomic_disabled[0x1];
942         u8         umr_indirect_mkey_disabled[0x1];
943         u8         umr_fence[0x2];
944         u8         reserved_at_20c[0x3];
945         u8         drain_sigerr[0x1];
946         u8         cmdif_checksum[0x2];
947         u8         sigerr_cqe[0x1];
948         u8         reserved_at_213[0x1];
949         u8         wq_signature[0x1];
950         u8         sctr_data_cqe[0x1];
951         u8         reserved_at_216[0x1];
952         u8         sho[0x1];
953         u8         tph[0x1];
954         u8         rf[0x1];
955         u8         dct[0x1];
956         u8         qos[0x1];
957         u8         eth_net_offloads[0x1];
958         u8         roce[0x1];
959         u8         atomic[0x1];
960         u8         reserved_at_21f[0x1];
961
962         u8         cq_oi[0x1];
963         u8         cq_resize[0x1];
964         u8         cq_moderation[0x1];
965         u8         reserved_at_223[0x3];
966         u8         cq_eq_remap[0x1];
967         u8         pg[0x1];
968         u8         block_lb_mc[0x1];
969         u8         reserved_at_229[0x1];
970         u8         scqe_break_moderation[0x1];
971         u8         cq_period_start_from_cqe[0x1];
972         u8         cd[0x1];
973         u8         reserved_at_22d[0x1];
974         u8         apm[0x1];
975         u8         vector_calc[0x1];
976         u8         umr_ptr_rlky[0x1];
977         u8         imaicl[0x1];
978         u8         reserved_at_232[0x4];
979         u8         qkv[0x1];
980         u8         pkv[0x1];
981         u8         set_deth_sqpn[0x1];
982         u8         reserved_at_239[0x3];
983         u8         xrc[0x1];
984         u8         ud[0x1];
985         u8         uc[0x1];
986         u8         rc[0x1];
987
988         u8         uar_4k[0x1];
989         u8         reserved_at_241[0x9];
990         u8         uar_sz[0x6];
991         u8         reserved_at_250[0x8];
992         u8         log_pg_sz[0x8];
993
994         u8         bf[0x1];
995         u8         driver_version[0x1];
996         u8         pad_tx_eth_packet[0x1];
997         u8         reserved_at_263[0x8];
998         u8         log_bf_reg_size[0x5];
999
1000         u8         reserved_at_270[0xb];
1001         u8         lag_master[0x1];
1002         u8         num_lag_ports[0x4];
1003
1004         u8         reserved_at_280[0x10];
1005         u8         max_wqe_sz_sq[0x10];
1006
1007         u8         reserved_at_2a0[0x10];
1008         u8         max_wqe_sz_rq[0x10];
1009
1010         u8         max_flow_counter_31_16[0x10];
1011         u8         max_wqe_sz_sq_dc[0x10];
1012
1013         u8         reserved_at_2e0[0x7];
1014         u8         max_qp_mcg[0x19];
1015
1016         u8         reserved_at_300[0x18];
1017         u8         log_max_mcg[0x8];
1018
1019         u8         reserved_at_320[0x3];
1020         u8         log_max_transport_domain[0x5];
1021         u8         reserved_at_328[0x3];
1022         u8         log_max_pd[0x5];
1023         u8         reserved_at_330[0xb];
1024         u8         log_max_xrcd[0x5];
1025
1026         u8         nic_receive_steering_discard[0x1];
1027         u8         receive_discard_vport_down[0x1];
1028         u8         transmit_discard_vport_down[0x1];
1029         u8         reserved_at_343[0x5];
1030         u8         log_max_flow_counter_bulk[0x8];
1031         u8         max_flow_counter_15_0[0x10];
1032
1033
1034         u8         reserved_at_360[0x3];
1035         u8         log_max_rq[0x5];
1036         u8         reserved_at_368[0x3];
1037         u8         log_max_sq[0x5];
1038         u8         reserved_at_370[0x3];
1039         u8         log_max_tir[0x5];
1040         u8         reserved_at_378[0x3];
1041         u8         log_max_tis[0x5];
1042
1043         u8         basic_cyclic_rcv_wqe[0x1];
1044         u8         reserved_at_381[0x2];
1045         u8         log_max_rmp[0x5];
1046         u8         reserved_at_388[0x3];
1047         u8         log_max_rqt[0x5];
1048         u8         reserved_at_390[0x3];
1049         u8         log_max_rqt_size[0x5];
1050         u8         reserved_at_398[0x3];
1051         u8         log_max_tis_per_sq[0x5];
1052
1053         u8         ext_stride_num_range[0x1];
1054         u8         reserved_at_3a1[0x2];
1055         u8         log_max_stride_sz_rq[0x5];
1056         u8         reserved_at_3a8[0x3];
1057         u8         log_min_stride_sz_rq[0x5];
1058         u8         reserved_at_3b0[0x3];
1059         u8         log_max_stride_sz_sq[0x5];
1060         u8         reserved_at_3b8[0x3];
1061         u8         log_min_stride_sz_sq[0x5];
1062
1063         u8         hairpin[0x1];
1064         u8         reserved_at_3c1[0x2];
1065         u8         log_max_hairpin_queues[0x5];
1066         u8         reserved_at_3c8[0x3];
1067         u8         log_max_hairpin_wq_data_sz[0x5];
1068         u8         reserved_at_3d0[0x3];
1069         u8         log_max_hairpin_num_packets[0x5];
1070         u8         reserved_at_3d8[0x3];
1071         u8         log_max_wq_sz[0x5];
1072
1073         u8         nic_vport_change_event[0x1];
1074         u8         disable_local_lb_uc[0x1];
1075         u8         disable_local_lb_mc[0x1];
1076         u8         log_min_hairpin_wq_data_sz[0x5];
1077         u8         reserved_at_3e8[0x3];
1078         u8         log_max_vlan_list[0x5];
1079         u8         reserved_at_3f0[0x3];
1080         u8         log_max_current_mc_list[0x5];
1081         u8         reserved_at_3f8[0x3];
1082         u8         log_max_current_uc_list[0x5];
1083
1084         u8         reserved_at_400[0x80];
1085
1086         u8         reserved_at_480[0x3];
1087         u8         log_max_l2_table[0x5];
1088         u8         reserved_at_488[0x8];
1089         u8         log_uar_page_sz[0x10];
1090
1091         u8         reserved_at_4a0[0x20];
1092         u8         device_frequency_mhz[0x20];
1093         u8         device_frequency_khz[0x20];
1094
1095         u8         reserved_at_500[0x20];
1096         u8         num_of_uars_per_page[0x20];
1097         u8         reserved_at_540[0x40];
1098
1099         u8         reserved_at_580[0x3d];
1100         u8         cqe_128_always[0x1];
1101         u8         cqe_compression_128[0x1];
1102         u8         cqe_compression[0x1];
1103
1104         u8         cqe_compression_timeout[0x10];
1105         u8         cqe_compression_max_num[0x10];
1106
1107         u8         reserved_at_5e0[0x10];
1108         u8         tag_matching[0x1];
1109         u8         rndv_offload_rc[0x1];
1110         u8         rndv_offload_dc[0x1];
1111         u8         log_tag_matching_list_sz[0x5];
1112         u8         reserved_at_5f8[0x3];
1113         u8         log_max_xrq[0x5];
1114
1115         u8         affiliate_nic_vport_criteria[0x8];
1116         u8         native_port_num[0x8];
1117         u8         num_vhca_ports[0x8];
1118         u8         reserved_at_618[0x6];
1119         u8         sw_owner_id[0x1];
1120         u8         reserved_at_61f[0x1e1];
1121 };
1122
1123 enum mlx5_flow_destination_type {
1124         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1125         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1126         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1127
1128         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1129         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1130 };
1131
1132 struct mlx5_ifc_dest_format_struct_bits {
1133         u8         destination_type[0x8];
1134         u8         destination_id[0x18];
1135         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1136         u8         reserved_at_21[0xf];
1137         u8         destination_eswitch_owner_vhca_id[0x10];
1138 };
1139
1140 struct mlx5_ifc_flow_counter_list_bits {
1141         u8         flow_counter_id[0x20];
1142
1143         u8         reserved_at_20[0x20];
1144 };
1145
1146 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1147         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1148         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1149         u8         reserved_at_0[0x40];
1150 };
1151
1152 struct mlx5_ifc_fte_match_param_bits {
1153         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1154
1155         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1156
1157         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1158
1159         u8         reserved_at_600[0xa00];
1160 };
1161
1162 enum {
1163         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1164         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1165         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1166         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1167         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1168 };
1169
1170 struct mlx5_ifc_rx_hash_field_select_bits {
1171         u8         l3_prot_type[0x1];
1172         u8         l4_prot_type[0x1];
1173         u8         selected_fields[0x1e];
1174 };
1175
1176 enum {
1177         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1178         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1179 };
1180
1181 enum {
1182         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1183         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1184 };
1185
1186 struct mlx5_ifc_wq_bits {
1187         u8         wq_type[0x4];
1188         u8         wq_signature[0x1];
1189         u8         end_padding_mode[0x2];
1190         u8         cd_slave[0x1];
1191         u8         reserved_at_8[0x18];
1192
1193         u8         hds_skip_first_sge[0x1];
1194         u8         log2_hds_buf_size[0x3];
1195         u8         reserved_at_24[0x7];
1196         u8         page_offset[0x5];
1197         u8         lwm[0x10];
1198
1199         u8         reserved_at_40[0x8];
1200         u8         pd[0x18];
1201
1202         u8         reserved_at_60[0x8];
1203         u8         uar_page[0x18];
1204
1205         u8         dbr_addr[0x40];
1206
1207         u8         hw_counter[0x20];
1208
1209         u8         sw_counter[0x20];
1210
1211         u8         reserved_at_100[0xc];
1212         u8         log_wq_stride[0x4];
1213         u8         reserved_at_110[0x3];
1214         u8         log_wq_pg_sz[0x5];
1215         u8         reserved_at_118[0x3];
1216         u8         log_wq_sz[0x5];
1217
1218         u8         reserved_at_120[0x3];
1219         u8         log_hairpin_num_packets[0x5];
1220         u8         reserved_at_128[0x3];
1221         u8         log_hairpin_data_sz[0x5];
1222
1223         u8         reserved_at_130[0x4];
1224         u8         log_wqe_num_of_strides[0x4];
1225         u8         two_byte_shift_en[0x1];
1226         u8         reserved_at_139[0x4];
1227         u8         log_wqe_stride_size[0x3];
1228
1229         u8         reserved_at_140[0x4c0];
1230
1231         struct mlx5_ifc_cmd_pas_bits pas[0];
1232 };
1233
1234 struct mlx5_ifc_rq_num_bits {
1235         u8         reserved_at_0[0x8];
1236         u8         rq_num[0x18];
1237 };
1238
1239 struct mlx5_ifc_mac_address_layout_bits {
1240         u8         reserved_at_0[0x10];
1241         u8         mac_addr_47_32[0x10];
1242
1243         u8         mac_addr_31_0[0x20];
1244 };
1245
1246 struct mlx5_ifc_vlan_layout_bits {
1247         u8         reserved_at_0[0x14];
1248         u8         vlan[0x0c];
1249
1250         u8         reserved_at_20[0x20];
1251 };
1252
1253 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1254         u8         reserved_at_0[0xa0];
1255
1256         u8         min_time_between_cnps[0x20];
1257
1258         u8         reserved_at_c0[0x12];
1259         u8         cnp_dscp[0x6];
1260         u8         reserved_at_d8[0x4];
1261         u8         cnp_prio_mode[0x1];
1262         u8         cnp_802p_prio[0x3];
1263
1264         u8         reserved_at_e0[0x720];
1265 };
1266
1267 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1268         u8         reserved_at_0[0x60];
1269
1270         u8         reserved_at_60[0x4];
1271         u8         clamp_tgt_rate[0x1];
1272         u8         reserved_at_65[0x3];
1273         u8         clamp_tgt_rate_after_time_inc[0x1];
1274         u8         reserved_at_69[0x17];
1275
1276         u8         reserved_at_80[0x20];
1277
1278         u8         rpg_time_reset[0x20];
1279
1280         u8         rpg_byte_reset[0x20];
1281
1282         u8         rpg_threshold[0x20];
1283
1284         u8         rpg_max_rate[0x20];
1285
1286         u8         rpg_ai_rate[0x20];
1287
1288         u8         rpg_hai_rate[0x20];
1289
1290         u8         rpg_gd[0x20];
1291
1292         u8         rpg_min_dec_fac[0x20];
1293
1294         u8         rpg_min_rate[0x20];
1295
1296         u8         reserved_at_1c0[0xe0];
1297
1298         u8         rate_to_set_on_first_cnp[0x20];
1299
1300         u8         dce_tcp_g[0x20];
1301
1302         u8         dce_tcp_rtt[0x20];
1303
1304         u8         rate_reduce_monitor_period[0x20];
1305
1306         u8         reserved_at_320[0x20];
1307
1308         u8         initial_alpha_value[0x20];
1309
1310         u8         reserved_at_360[0x4a0];
1311 };
1312
1313 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1314         u8         reserved_at_0[0x80];
1315
1316         u8         rppp_max_rps[0x20];
1317
1318         u8         rpg_time_reset[0x20];
1319
1320         u8         rpg_byte_reset[0x20];
1321
1322         u8         rpg_threshold[0x20];
1323
1324         u8         rpg_max_rate[0x20];
1325
1326         u8         rpg_ai_rate[0x20];
1327
1328         u8         rpg_hai_rate[0x20];
1329
1330         u8         rpg_gd[0x20];
1331
1332         u8         rpg_min_dec_fac[0x20];
1333
1334         u8         rpg_min_rate[0x20];
1335
1336         u8         reserved_at_1c0[0x640];
1337 };
1338
1339 enum {
1340         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1341         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1342         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1343 };
1344
1345 struct mlx5_ifc_resize_field_select_bits {
1346         u8         resize_field_select[0x20];
1347 };
1348
1349 enum {
1350         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1351         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1352         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1353         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1354 };
1355
1356 struct mlx5_ifc_modify_field_select_bits {
1357         u8         modify_field_select[0x20];
1358 };
1359
1360 struct mlx5_ifc_field_select_r_roce_np_bits {
1361         u8         field_select_r_roce_np[0x20];
1362 };
1363
1364 struct mlx5_ifc_field_select_r_roce_rp_bits {
1365         u8         field_select_r_roce_rp[0x20];
1366 };
1367
1368 enum {
1369         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1370         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1371         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1372         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1373         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1374         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1375         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1376         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1377         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1378         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1379 };
1380
1381 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1382         u8         field_select_8021qaurp[0x20];
1383 };
1384
1385 struct mlx5_ifc_phys_layer_cntrs_bits {
1386         u8         time_since_last_clear_high[0x20];
1387
1388         u8         time_since_last_clear_low[0x20];
1389
1390         u8         symbol_errors_high[0x20];
1391
1392         u8         symbol_errors_low[0x20];
1393
1394         u8         sync_headers_errors_high[0x20];
1395
1396         u8         sync_headers_errors_low[0x20];
1397
1398         u8         edpl_bip_errors_lane0_high[0x20];
1399
1400         u8         edpl_bip_errors_lane0_low[0x20];
1401
1402         u8         edpl_bip_errors_lane1_high[0x20];
1403
1404         u8         edpl_bip_errors_lane1_low[0x20];
1405
1406         u8         edpl_bip_errors_lane2_high[0x20];
1407
1408         u8         edpl_bip_errors_lane2_low[0x20];
1409
1410         u8         edpl_bip_errors_lane3_high[0x20];
1411
1412         u8         edpl_bip_errors_lane3_low[0x20];
1413
1414         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1415
1416         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1417
1418         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1419
1420         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1421
1422         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1423
1424         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1425
1426         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1427
1428         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1429
1430         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1431
1432         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1433
1434         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1435
1436         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1437
1438         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1439
1440         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1441
1442         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1443
1444         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1445
1446         u8         rs_fec_corrected_blocks_high[0x20];
1447
1448         u8         rs_fec_corrected_blocks_low[0x20];
1449
1450         u8         rs_fec_uncorrectable_blocks_high[0x20];
1451
1452         u8         rs_fec_uncorrectable_blocks_low[0x20];
1453
1454         u8         rs_fec_no_errors_blocks_high[0x20];
1455
1456         u8         rs_fec_no_errors_blocks_low[0x20];
1457
1458         u8         rs_fec_single_error_blocks_high[0x20];
1459
1460         u8         rs_fec_single_error_blocks_low[0x20];
1461
1462         u8         rs_fec_corrected_symbols_total_high[0x20];
1463
1464         u8         rs_fec_corrected_symbols_total_low[0x20];
1465
1466         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1467
1468         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1469
1470         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1471
1472         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1473
1474         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1475
1476         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1477
1478         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1479
1480         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1481
1482         u8         link_down_events[0x20];
1483
1484         u8         successful_recovery_events[0x20];
1485
1486         u8         reserved_at_640[0x180];
1487 };
1488
1489 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1490         u8         time_since_last_clear_high[0x20];
1491
1492         u8         time_since_last_clear_low[0x20];
1493
1494         u8         phy_received_bits_high[0x20];
1495
1496         u8         phy_received_bits_low[0x20];
1497
1498         u8         phy_symbol_errors_high[0x20];
1499
1500         u8         phy_symbol_errors_low[0x20];
1501
1502         u8         phy_corrected_bits_high[0x20];
1503
1504         u8         phy_corrected_bits_low[0x20];
1505
1506         u8         phy_corrected_bits_lane0_high[0x20];
1507
1508         u8         phy_corrected_bits_lane0_low[0x20];
1509
1510         u8         phy_corrected_bits_lane1_high[0x20];
1511
1512         u8         phy_corrected_bits_lane1_low[0x20];
1513
1514         u8         phy_corrected_bits_lane2_high[0x20];
1515
1516         u8         phy_corrected_bits_lane2_low[0x20];
1517
1518         u8         phy_corrected_bits_lane3_high[0x20];
1519
1520         u8         phy_corrected_bits_lane3_low[0x20];
1521
1522         u8         reserved_at_200[0x5c0];
1523 };
1524
1525 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1526         u8         symbol_error_counter[0x10];
1527
1528         u8         link_error_recovery_counter[0x8];
1529
1530         u8         link_downed_counter[0x8];
1531
1532         u8         port_rcv_errors[0x10];
1533
1534         u8         port_rcv_remote_physical_errors[0x10];
1535
1536         u8         port_rcv_switch_relay_errors[0x10];
1537
1538         u8         port_xmit_discards[0x10];
1539
1540         u8         port_xmit_constraint_errors[0x8];
1541
1542         u8         port_rcv_constraint_errors[0x8];
1543
1544         u8         reserved_at_70[0x8];
1545
1546         u8         link_overrun_errors[0x8];
1547
1548         u8         reserved_at_80[0x10];
1549
1550         u8         vl_15_dropped[0x10];
1551
1552         u8         reserved_at_a0[0x80];
1553
1554         u8         port_xmit_wait[0x20];
1555 };
1556
1557 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1558         u8         transmit_queue_high[0x20];
1559
1560         u8         transmit_queue_low[0x20];
1561
1562         u8         reserved_at_40[0x780];
1563 };
1564
1565 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1566         u8         rx_octets_high[0x20];
1567
1568         u8         rx_octets_low[0x20];
1569
1570         u8         reserved_at_40[0xc0];
1571
1572         u8         rx_frames_high[0x20];
1573
1574         u8         rx_frames_low[0x20];
1575
1576         u8         tx_octets_high[0x20];
1577
1578         u8         tx_octets_low[0x20];
1579
1580         u8         reserved_at_180[0xc0];
1581
1582         u8         tx_frames_high[0x20];
1583
1584         u8         tx_frames_low[0x20];
1585
1586         u8         rx_pause_high[0x20];
1587
1588         u8         rx_pause_low[0x20];
1589
1590         u8         rx_pause_duration_high[0x20];
1591
1592         u8         rx_pause_duration_low[0x20];
1593
1594         u8         tx_pause_high[0x20];
1595
1596         u8         tx_pause_low[0x20];
1597
1598         u8         tx_pause_duration_high[0x20];
1599
1600         u8         tx_pause_duration_low[0x20];
1601
1602         u8         rx_pause_transition_high[0x20];
1603
1604         u8         rx_pause_transition_low[0x20];
1605
1606         u8         reserved_at_3c0[0x40];
1607
1608         u8         device_stall_minor_watermark_cnt_high[0x20];
1609
1610         u8         device_stall_minor_watermark_cnt_low[0x20];
1611
1612         u8         device_stall_critical_watermark_cnt_high[0x20];
1613
1614         u8         device_stall_critical_watermark_cnt_low[0x20];
1615
1616         u8         reserved_at_480[0x340];
1617 };
1618
1619 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1620         u8         port_transmit_wait_high[0x20];
1621
1622         u8         port_transmit_wait_low[0x20];
1623
1624         u8         reserved_at_40[0x100];
1625
1626         u8         rx_buffer_almost_full_high[0x20];
1627
1628         u8         rx_buffer_almost_full_low[0x20];
1629
1630         u8         rx_buffer_full_high[0x20];
1631
1632         u8         rx_buffer_full_low[0x20];
1633
1634         u8         reserved_at_1c0[0x600];
1635 };
1636
1637 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1638         u8         dot3stats_alignment_errors_high[0x20];
1639
1640         u8         dot3stats_alignment_errors_low[0x20];
1641
1642         u8         dot3stats_fcs_errors_high[0x20];
1643
1644         u8         dot3stats_fcs_errors_low[0x20];
1645
1646         u8         dot3stats_single_collision_frames_high[0x20];
1647
1648         u8         dot3stats_single_collision_frames_low[0x20];
1649
1650         u8         dot3stats_multiple_collision_frames_high[0x20];
1651
1652         u8         dot3stats_multiple_collision_frames_low[0x20];
1653
1654         u8         dot3stats_sqe_test_errors_high[0x20];
1655
1656         u8         dot3stats_sqe_test_errors_low[0x20];
1657
1658         u8         dot3stats_deferred_transmissions_high[0x20];
1659
1660         u8         dot3stats_deferred_transmissions_low[0x20];
1661
1662         u8         dot3stats_late_collisions_high[0x20];
1663
1664         u8         dot3stats_late_collisions_low[0x20];
1665
1666         u8         dot3stats_excessive_collisions_high[0x20];
1667
1668         u8         dot3stats_excessive_collisions_low[0x20];
1669
1670         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1671
1672         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1673
1674         u8         dot3stats_carrier_sense_errors_high[0x20];
1675
1676         u8         dot3stats_carrier_sense_errors_low[0x20];
1677
1678         u8         dot3stats_frame_too_longs_high[0x20];
1679
1680         u8         dot3stats_frame_too_longs_low[0x20];
1681
1682         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1683
1684         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1685
1686         u8         dot3stats_symbol_errors_high[0x20];
1687
1688         u8         dot3stats_symbol_errors_low[0x20];
1689
1690         u8         dot3control_in_unknown_opcodes_high[0x20];
1691
1692         u8         dot3control_in_unknown_opcodes_low[0x20];
1693
1694         u8         dot3in_pause_frames_high[0x20];
1695
1696         u8         dot3in_pause_frames_low[0x20];
1697
1698         u8         dot3out_pause_frames_high[0x20];
1699
1700         u8         dot3out_pause_frames_low[0x20];
1701
1702         u8         reserved_at_400[0x3c0];
1703 };
1704
1705 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1706         u8         ether_stats_drop_events_high[0x20];
1707
1708         u8         ether_stats_drop_events_low[0x20];
1709
1710         u8         ether_stats_octets_high[0x20];
1711
1712         u8         ether_stats_octets_low[0x20];
1713
1714         u8         ether_stats_pkts_high[0x20];
1715
1716         u8         ether_stats_pkts_low[0x20];
1717
1718         u8         ether_stats_broadcast_pkts_high[0x20];
1719
1720         u8         ether_stats_broadcast_pkts_low[0x20];
1721
1722         u8         ether_stats_multicast_pkts_high[0x20];
1723
1724         u8         ether_stats_multicast_pkts_low[0x20];
1725
1726         u8         ether_stats_crc_align_errors_high[0x20];
1727
1728         u8         ether_stats_crc_align_errors_low[0x20];
1729
1730         u8         ether_stats_undersize_pkts_high[0x20];
1731
1732         u8         ether_stats_undersize_pkts_low[0x20];
1733
1734         u8         ether_stats_oversize_pkts_high[0x20];
1735
1736         u8         ether_stats_oversize_pkts_low[0x20];
1737
1738         u8         ether_stats_fragments_high[0x20];
1739
1740         u8         ether_stats_fragments_low[0x20];
1741
1742         u8         ether_stats_jabbers_high[0x20];
1743
1744         u8         ether_stats_jabbers_low[0x20];
1745
1746         u8         ether_stats_collisions_high[0x20];
1747
1748         u8         ether_stats_collisions_low[0x20];
1749
1750         u8         ether_stats_pkts64octets_high[0x20];
1751
1752         u8         ether_stats_pkts64octets_low[0x20];
1753
1754         u8         ether_stats_pkts65to127octets_high[0x20];
1755
1756         u8         ether_stats_pkts65to127octets_low[0x20];
1757
1758         u8         ether_stats_pkts128to255octets_high[0x20];
1759
1760         u8         ether_stats_pkts128to255octets_low[0x20];
1761
1762         u8         ether_stats_pkts256to511octets_high[0x20];
1763
1764         u8         ether_stats_pkts256to511octets_low[0x20];
1765
1766         u8         ether_stats_pkts512to1023octets_high[0x20];
1767
1768         u8         ether_stats_pkts512to1023octets_low[0x20];
1769
1770         u8         ether_stats_pkts1024to1518octets_high[0x20];
1771
1772         u8         ether_stats_pkts1024to1518octets_low[0x20];
1773
1774         u8         ether_stats_pkts1519to2047octets_high[0x20];
1775
1776         u8         ether_stats_pkts1519to2047octets_low[0x20];
1777
1778         u8         ether_stats_pkts2048to4095octets_high[0x20];
1779
1780         u8         ether_stats_pkts2048to4095octets_low[0x20];
1781
1782         u8         ether_stats_pkts4096to8191octets_high[0x20];
1783
1784         u8         ether_stats_pkts4096to8191octets_low[0x20];
1785
1786         u8         ether_stats_pkts8192to10239octets_high[0x20];
1787
1788         u8         ether_stats_pkts8192to10239octets_low[0x20];
1789
1790         u8         reserved_at_540[0x280];
1791 };
1792
1793 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1794         u8         if_in_octets_high[0x20];
1795
1796         u8         if_in_octets_low[0x20];
1797
1798         u8         if_in_ucast_pkts_high[0x20];
1799
1800         u8         if_in_ucast_pkts_low[0x20];
1801
1802         u8         if_in_discards_high[0x20];
1803
1804         u8         if_in_discards_low[0x20];
1805
1806         u8         if_in_errors_high[0x20];
1807
1808         u8         if_in_errors_low[0x20];
1809
1810         u8         if_in_unknown_protos_high[0x20];
1811
1812         u8         if_in_unknown_protos_low[0x20];
1813
1814         u8         if_out_octets_high[0x20];
1815
1816         u8         if_out_octets_low[0x20];
1817
1818         u8         if_out_ucast_pkts_high[0x20];
1819
1820         u8         if_out_ucast_pkts_low[0x20];
1821
1822         u8         if_out_discards_high[0x20];
1823
1824         u8         if_out_discards_low[0x20];
1825
1826         u8         if_out_errors_high[0x20];
1827
1828         u8         if_out_errors_low[0x20];
1829
1830         u8         if_in_multicast_pkts_high[0x20];
1831
1832         u8         if_in_multicast_pkts_low[0x20];
1833
1834         u8         if_in_broadcast_pkts_high[0x20];
1835
1836         u8         if_in_broadcast_pkts_low[0x20];
1837
1838         u8         if_out_multicast_pkts_high[0x20];
1839
1840         u8         if_out_multicast_pkts_low[0x20];
1841
1842         u8         if_out_broadcast_pkts_high[0x20];
1843
1844         u8         if_out_broadcast_pkts_low[0x20];
1845
1846         u8         reserved_at_340[0x480];
1847 };
1848
1849 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1850         u8         a_frames_transmitted_ok_high[0x20];
1851
1852         u8         a_frames_transmitted_ok_low[0x20];
1853
1854         u8         a_frames_received_ok_high[0x20];
1855
1856         u8         a_frames_received_ok_low[0x20];
1857
1858         u8         a_frame_check_sequence_errors_high[0x20];
1859
1860         u8         a_frame_check_sequence_errors_low[0x20];
1861
1862         u8         a_alignment_errors_high[0x20];
1863
1864         u8         a_alignment_errors_low[0x20];
1865
1866         u8         a_octets_transmitted_ok_high[0x20];
1867
1868         u8         a_octets_transmitted_ok_low[0x20];
1869
1870         u8         a_octets_received_ok_high[0x20];
1871
1872         u8         a_octets_received_ok_low[0x20];
1873
1874         u8         a_multicast_frames_xmitted_ok_high[0x20];
1875
1876         u8         a_multicast_frames_xmitted_ok_low[0x20];
1877
1878         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1879
1880         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1881
1882         u8         a_multicast_frames_received_ok_high[0x20];
1883
1884         u8         a_multicast_frames_received_ok_low[0x20];
1885
1886         u8         a_broadcast_frames_received_ok_high[0x20];
1887
1888         u8         a_broadcast_frames_received_ok_low[0x20];
1889
1890         u8         a_in_range_length_errors_high[0x20];
1891
1892         u8         a_in_range_length_errors_low[0x20];
1893
1894         u8         a_out_of_range_length_field_high[0x20];
1895
1896         u8         a_out_of_range_length_field_low[0x20];
1897
1898         u8         a_frame_too_long_errors_high[0x20];
1899
1900         u8         a_frame_too_long_errors_low[0x20];
1901
1902         u8         a_symbol_error_during_carrier_high[0x20];
1903
1904         u8         a_symbol_error_during_carrier_low[0x20];
1905
1906         u8         a_mac_control_frames_transmitted_high[0x20];
1907
1908         u8         a_mac_control_frames_transmitted_low[0x20];
1909
1910         u8         a_mac_control_frames_received_high[0x20];
1911
1912         u8         a_mac_control_frames_received_low[0x20];
1913
1914         u8         a_unsupported_opcodes_received_high[0x20];
1915
1916         u8         a_unsupported_opcodes_received_low[0x20];
1917
1918         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1919
1920         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1921
1922         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1923
1924         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1925
1926         u8         reserved_at_4c0[0x300];
1927 };
1928
1929 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1930         u8         life_time_counter_high[0x20];
1931
1932         u8         life_time_counter_low[0x20];
1933
1934         u8         rx_errors[0x20];
1935
1936         u8         tx_errors[0x20];
1937
1938         u8         l0_to_recovery_eieos[0x20];
1939
1940         u8         l0_to_recovery_ts[0x20];
1941
1942         u8         l0_to_recovery_framing[0x20];
1943
1944         u8         l0_to_recovery_retrain[0x20];
1945
1946         u8         crc_error_dllp[0x20];
1947
1948         u8         crc_error_tlp[0x20];
1949
1950         u8         tx_overflow_buffer_pkt_high[0x20];
1951
1952         u8         tx_overflow_buffer_pkt_low[0x20];
1953
1954         u8         outbound_stalled_reads[0x20];
1955
1956         u8         outbound_stalled_writes[0x20];
1957
1958         u8         outbound_stalled_reads_events[0x20];
1959
1960         u8         outbound_stalled_writes_events[0x20];
1961
1962         u8         reserved_at_200[0x5c0];
1963 };
1964
1965 struct mlx5_ifc_cmd_inter_comp_event_bits {
1966         u8         command_completion_vector[0x20];
1967
1968         u8         reserved_at_20[0xc0];
1969 };
1970
1971 struct mlx5_ifc_stall_vl_event_bits {
1972         u8         reserved_at_0[0x18];
1973         u8         port_num[0x1];
1974         u8         reserved_at_19[0x3];
1975         u8         vl[0x4];
1976
1977         u8         reserved_at_20[0xa0];
1978 };
1979
1980 struct mlx5_ifc_db_bf_congestion_event_bits {
1981         u8         event_subtype[0x8];
1982         u8         reserved_at_8[0x8];
1983         u8         congestion_level[0x8];
1984         u8         reserved_at_18[0x8];
1985
1986         u8         reserved_at_20[0xa0];
1987 };
1988
1989 struct mlx5_ifc_gpio_event_bits {
1990         u8         reserved_at_0[0x60];
1991
1992         u8         gpio_event_hi[0x20];
1993
1994         u8         gpio_event_lo[0x20];
1995
1996         u8         reserved_at_a0[0x40];
1997 };
1998
1999 struct mlx5_ifc_port_state_change_event_bits {
2000         u8         reserved_at_0[0x40];
2001
2002         u8         port_num[0x4];
2003         u8         reserved_at_44[0x1c];
2004
2005         u8         reserved_at_60[0x80];
2006 };
2007
2008 struct mlx5_ifc_dropped_packet_logged_bits {
2009         u8         reserved_at_0[0xe0];
2010 };
2011
2012 enum {
2013         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2014         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2015 };
2016
2017 struct mlx5_ifc_cq_error_bits {
2018         u8         reserved_at_0[0x8];
2019         u8         cqn[0x18];
2020
2021         u8         reserved_at_20[0x20];
2022
2023         u8         reserved_at_40[0x18];
2024         u8         syndrome[0x8];
2025
2026         u8         reserved_at_60[0x80];
2027 };
2028
2029 struct mlx5_ifc_rdma_page_fault_event_bits {
2030         u8         bytes_committed[0x20];
2031
2032         u8         r_key[0x20];
2033
2034         u8         reserved_at_40[0x10];
2035         u8         packet_len[0x10];
2036
2037         u8         rdma_op_len[0x20];
2038
2039         u8         rdma_va[0x40];
2040
2041         u8         reserved_at_c0[0x5];
2042         u8         rdma[0x1];
2043         u8         write[0x1];
2044         u8         requestor[0x1];
2045         u8         qp_number[0x18];
2046 };
2047
2048 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2049         u8         bytes_committed[0x20];
2050
2051         u8         reserved_at_20[0x10];
2052         u8         wqe_index[0x10];
2053
2054         u8         reserved_at_40[0x10];
2055         u8         len[0x10];
2056
2057         u8         reserved_at_60[0x60];
2058
2059         u8         reserved_at_c0[0x5];
2060         u8         rdma[0x1];
2061         u8         write_read[0x1];
2062         u8         requestor[0x1];
2063         u8         qpn[0x18];
2064 };
2065
2066 struct mlx5_ifc_qp_events_bits {
2067         u8         reserved_at_0[0xa0];
2068
2069         u8         type[0x8];
2070         u8         reserved_at_a8[0x18];
2071
2072         u8         reserved_at_c0[0x8];
2073         u8         qpn_rqn_sqn[0x18];
2074 };
2075
2076 struct mlx5_ifc_dct_events_bits {
2077         u8         reserved_at_0[0xc0];
2078
2079         u8         reserved_at_c0[0x8];
2080         u8         dct_number[0x18];
2081 };
2082
2083 struct mlx5_ifc_comp_event_bits {
2084         u8         reserved_at_0[0xc0];
2085
2086         u8         reserved_at_c0[0x8];
2087         u8         cq_number[0x18];
2088 };
2089
2090 enum {
2091         MLX5_QPC_STATE_RST        = 0x0,
2092         MLX5_QPC_STATE_INIT       = 0x1,
2093         MLX5_QPC_STATE_RTR        = 0x2,
2094         MLX5_QPC_STATE_RTS        = 0x3,
2095         MLX5_QPC_STATE_SQER       = 0x4,
2096         MLX5_QPC_STATE_ERR        = 0x6,
2097         MLX5_QPC_STATE_SQD        = 0x7,
2098         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2099 };
2100
2101 enum {
2102         MLX5_QPC_ST_RC            = 0x0,
2103         MLX5_QPC_ST_UC            = 0x1,
2104         MLX5_QPC_ST_UD            = 0x2,
2105         MLX5_QPC_ST_XRC           = 0x3,
2106         MLX5_QPC_ST_DCI           = 0x5,
2107         MLX5_QPC_ST_QP0           = 0x7,
2108         MLX5_QPC_ST_QP1           = 0x8,
2109         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2110         MLX5_QPC_ST_REG_UMR       = 0xc,
2111 };
2112
2113 enum {
2114         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2115         MLX5_QPC_PM_STATE_REARM     = 0x1,
2116         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2117         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2118 };
2119
2120 enum {
2121         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2122 };
2123
2124 enum {
2125         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2126         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2127 };
2128
2129 enum {
2130         MLX5_QPC_MTU_256_BYTES        = 0x1,
2131         MLX5_QPC_MTU_512_BYTES        = 0x2,
2132         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2133         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2134         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2135         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2136 };
2137
2138 enum {
2139         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2140         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2141         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2142         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2143         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2144         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2145         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2146         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2147 };
2148
2149 enum {
2150         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2151         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2152         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2153 };
2154
2155 enum {
2156         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2157         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2158         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2159 };
2160
2161 struct mlx5_ifc_qpc_bits {
2162         u8         state[0x4];
2163         u8         lag_tx_port_affinity[0x4];
2164         u8         st[0x8];
2165         u8         reserved_at_10[0x3];
2166         u8         pm_state[0x2];
2167         u8         reserved_at_15[0x3];
2168         u8         offload_type[0x4];
2169         u8         end_padding_mode[0x2];
2170         u8         reserved_at_1e[0x2];
2171
2172         u8         wq_signature[0x1];
2173         u8         block_lb_mc[0x1];
2174         u8         atomic_like_write_en[0x1];
2175         u8         latency_sensitive[0x1];
2176         u8         reserved_at_24[0x1];
2177         u8         drain_sigerr[0x1];
2178         u8         reserved_at_26[0x2];
2179         u8         pd[0x18];
2180
2181         u8         mtu[0x3];
2182         u8         log_msg_max[0x5];
2183         u8         reserved_at_48[0x1];
2184         u8         log_rq_size[0x4];
2185         u8         log_rq_stride[0x3];
2186         u8         no_sq[0x1];
2187         u8         log_sq_size[0x4];
2188         u8         reserved_at_55[0x6];
2189         u8         rlky[0x1];
2190         u8         ulp_stateless_offload_mode[0x4];
2191
2192         u8         counter_set_id[0x8];
2193         u8         uar_page[0x18];
2194
2195         u8         reserved_at_80[0x8];
2196         u8         user_index[0x18];
2197
2198         u8         reserved_at_a0[0x3];
2199         u8         log_page_size[0x5];
2200         u8         remote_qpn[0x18];
2201
2202         struct mlx5_ifc_ads_bits primary_address_path;
2203
2204         struct mlx5_ifc_ads_bits secondary_address_path;
2205
2206         u8         log_ack_req_freq[0x4];
2207         u8         reserved_at_384[0x4];
2208         u8         log_sra_max[0x3];
2209         u8         reserved_at_38b[0x2];
2210         u8         retry_count[0x3];
2211         u8         rnr_retry[0x3];
2212         u8         reserved_at_393[0x1];
2213         u8         fre[0x1];
2214         u8         cur_rnr_retry[0x3];
2215         u8         cur_retry_count[0x3];
2216         u8         reserved_at_39b[0x5];
2217
2218         u8         reserved_at_3a0[0x20];
2219
2220         u8         reserved_at_3c0[0x8];
2221         u8         next_send_psn[0x18];
2222
2223         u8         reserved_at_3e0[0x8];
2224         u8         cqn_snd[0x18];
2225
2226         u8         reserved_at_400[0x8];
2227         u8         deth_sqpn[0x18];
2228
2229         u8         reserved_at_420[0x20];
2230
2231         u8         reserved_at_440[0x8];
2232         u8         last_acked_psn[0x18];
2233
2234         u8         reserved_at_460[0x8];
2235         u8         ssn[0x18];
2236
2237         u8         reserved_at_480[0x8];
2238         u8         log_rra_max[0x3];
2239         u8         reserved_at_48b[0x1];
2240         u8         atomic_mode[0x4];
2241         u8         rre[0x1];
2242         u8         rwe[0x1];
2243         u8         rae[0x1];
2244         u8         reserved_at_493[0x1];
2245         u8         page_offset[0x6];
2246         u8         reserved_at_49a[0x3];
2247         u8         cd_slave_receive[0x1];
2248         u8         cd_slave_send[0x1];
2249         u8         cd_master[0x1];
2250
2251         u8         reserved_at_4a0[0x3];
2252         u8         min_rnr_nak[0x5];
2253         u8         next_rcv_psn[0x18];
2254
2255         u8         reserved_at_4c0[0x8];
2256         u8         xrcd[0x18];
2257
2258         u8         reserved_at_4e0[0x8];
2259         u8         cqn_rcv[0x18];
2260
2261         u8         dbr_addr[0x40];
2262
2263         u8         q_key[0x20];
2264
2265         u8         reserved_at_560[0x5];
2266         u8         rq_type[0x3];
2267         u8         srqn_rmpn_xrqn[0x18];
2268
2269         u8         reserved_at_580[0x8];
2270         u8         rmsn[0x18];
2271
2272         u8         hw_sq_wqebb_counter[0x10];
2273         u8         sw_sq_wqebb_counter[0x10];
2274
2275         u8         hw_rq_counter[0x20];
2276
2277         u8         sw_rq_counter[0x20];
2278
2279         u8         reserved_at_600[0x20];
2280
2281         u8         reserved_at_620[0xf];
2282         u8         cgs[0x1];
2283         u8         cs_req[0x8];
2284         u8         cs_res[0x8];
2285
2286         u8         dc_access_key[0x40];
2287
2288         u8         reserved_at_680[0xc0];
2289 };
2290
2291 struct mlx5_ifc_roce_addr_layout_bits {
2292         u8         source_l3_address[16][0x8];
2293
2294         u8         reserved_at_80[0x3];
2295         u8         vlan_valid[0x1];
2296         u8         vlan_id[0xc];
2297         u8         source_mac_47_32[0x10];
2298
2299         u8         source_mac_31_0[0x20];
2300
2301         u8         reserved_at_c0[0x14];
2302         u8         roce_l3_type[0x4];
2303         u8         roce_version[0x8];
2304
2305         u8         reserved_at_e0[0x20];
2306 };
2307
2308 union mlx5_ifc_hca_cap_union_bits {
2309         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2310         struct mlx5_ifc_odp_cap_bits odp_cap;
2311         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2312         struct mlx5_ifc_roce_cap_bits roce_cap;
2313         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2314         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2315         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2316         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2317         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2318         struct mlx5_ifc_qos_cap_bits qos_cap;
2319         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2320         u8         reserved_at_0[0x8000];
2321 };
2322
2323 enum {
2324         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2325         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2326         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2327         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2328         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2329         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2330         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2331         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2332         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2333 };
2334
2335 struct mlx5_ifc_vlan_bits {
2336         u8         ethtype[0x10];
2337         u8         prio[0x3];
2338         u8         cfi[0x1];
2339         u8         vid[0xc];
2340 };
2341
2342 struct mlx5_ifc_flow_context_bits {
2343         struct mlx5_ifc_vlan_bits push_vlan;
2344
2345         u8         group_id[0x20];
2346
2347         u8         reserved_at_40[0x8];
2348         u8         flow_tag[0x18];
2349
2350         u8         reserved_at_60[0x10];
2351         u8         action[0x10];
2352
2353         u8         reserved_at_80[0x8];
2354         u8         destination_list_size[0x18];
2355
2356         u8         reserved_at_a0[0x8];
2357         u8         flow_counter_list_size[0x18];
2358
2359         u8         encap_id[0x20];
2360
2361         u8         modify_header_id[0x20];
2362
2363         u8         reserved_at_100[0x100];
2364
2365         struct mlx5_ifc_fte_match_param_bits match_value;
2366
2367         u8         reserved_at_1200[0x600];
2368
2369         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2370 };
2371
2372 enum {
2373         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2374         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2375 };
2376
2377 struct mlx5_ifc_xrc_srqc_bits {
2378         u8         state[0x4];
2379         u8         log_xrc_srq_size[0x4];
2380         u8         reserved_at_8[0x18];
2381
2382         u8         wq_signature[0x1];
2383         u8         cont_srq[0x1];
2384         u8         reserved_at_22[0x1];
2385         u8         rlky[0x1];
2386         u8         basic_cyclic_rcv_wqe[0x1];
2387         u8         log_rq_stride[0x3];
2388         u8         xrcd[0x18];
2389
2390         u8         page_offset[0x6];
2391         u8         reserved_at_46[0x2];
2392         u8         cqn[0x18];
2393
2394         u8         reserved_at_60[0x20];
2395
2396         u8         user_index_equal_xrc_srqn[0x1];
2397         u8         reserved_at_81[0x1];
2398         u8         log_page_size[0x6];
2399         u8         user_index[0x18];
2400
2401         u8         reserved_at_a0[0x20];
2402
2403         u8         reserved_at_c0[0x8];
2404         u8         pd[0x18];
2405
2406         u8         lwm[0x10];
2407         u8         wqe_cnt[0x10];
2408
2409         u8         reserved_at_100[0x40];
2410
2411         u8         db_record_addr_h[0x20];
2412
2413         u8         db_record_addr_l[0x1e];
2414         u8         reserved_at_17e[0x2];
2415
2416         u8         reserved_at_180[0x80];
2417 };
2418
2419 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2420         u8         counter_error_queues[0x20];
2421
2422         u8         total_error_queues[0x20];
2423
2424         u8         send_queue_priority_update_flow[0x20];
2425
2426         u8         reserved_at_60[0x20];
2427
2428         u8         nic_receive_steering_discard[0x40];
2429
2430         u8         receive_discard_vport_down[0x40];
2431
2432         u8         transmit_discard_vport_down[0x40];
2433
2434         u8         reserved_at_140[0xec0];
2435 };
2436
2437 struct mlx5_ifc_traffic_counter_bits {
2438         u8         packets[0x40];
2439
2440         u8         octets[0x40];
2441 };
2442
2443 struct mlx5_ifc_tisc_bits {
2444         u8         strict_lag_tx_port_affinity[0x1];
2445         u8         reserved_at_1[0x3];
2446         u8         lag_tx_port_affinity[0x04];
2447
2448         u8         reserved_at_8[0x4];
2449         u8         prio[0x4];
2450         u8         reserved_at_10[0x10];
2451
2452         u8         reserved_at_20[0x100];
2453
2454         u8         reserved_at_120[0x8];
2455         u8         transport_domain[0x18];
2456
2457         u8         reserved_at_140[0x8];
2458         u8         underlay_qpn[0x18];
2459         u8         reserved_at_160[0x3a0];
2460 };
2461
2462 enum {
2463         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2464         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2465 };
2466
2467 enum {
2468         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2469         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2470 };
2471
2472 enum {
2473         MLX5_RX_HASH_FN_NONE           = 0x0,
2474         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2475         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2476 };
2477
2478 enum {
2479         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2480         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2481 };
2482
2483 struct mlx5_ifc_tirc_bits {
2484         u8         reserved_at_0[0x20];
2485
2486         u8         disp_type[0x4];
2487         u8         reserved_at_24[0x1c];
2488
2489         u8         reserved_at_40[0x40];
2490
2491         u8         reserved_at_80[0x4];
2492         u8         lro_timeout_period_usecs[0x10];
2493         u8         lro_enable_mask[0x4];
2494         u8         lro_max_ip_payload_size[0x8];
2495
2496         u8         reserved_at_a0[0x40];
2497
2498         u8         reserved_at_e0[0x8];
2499         u8         inline_rqn[0x18];
2500
2501         u8         rx_hash_symmetric[0x1];
2502         u8         reserved_at_101[0x1];
2503         u8         tunneled_offload_en[0x1];
2504         u8         reserved_at_103[0x5];
2505         u8         indirect_table[0x18];
2506
2507         u8         rx_hash_fn[0x4];
2508         u8         reserved_at_124[0x2];
2509         u8         self_lb_block[0x2];
2510         u8         transport_domain[0x18];
2511
2512         u8         rx_hash_toeplitz_key[10][0x20];
2513
2514         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2515
2516         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2517
2518         u8         reserved_at_2c0[0x4c0];
2519 };
2520
2521 enum {
2522         MLX5_SRQC_STATE_GOOD   = 0x0,
2523         MLX5_SRQC_STATE_ERROR  = 0x1,
2524 };
2525
2526 struct mlx5_ifc_srqc_bits {
2527         u8         state[0x4];
2528         u8         log_srq_size[0x4];
2529         u8         reserved_at_8[0x18];
2530
2531         u8         wq_signature[0x1];
2532         u8         cont_srq[0x1];
2533         u8         reserved_at_22[0x1];
2534         u8         rlky[0x1];
2535         u8         reserved_at_24[0x1];
2536         u8         log_rq_stride[0x3];
2537         u8         xrcd[0x18];
2538
2539         u8         page_offset[0x6];
2540         u8         reserved_at_46[0x2];
2541         u8         cqn[0x18];
2542
2543         u8         reserved_at_60[0x20];
2544
2545         u8         reserved_at_80[0x2];
2546         u8         log_page_size[0x6];
2547         u8         reserved_at_88[0x18];
2548
2549         u8         reserved_at_a0[0x20];
2550
2551         u8         reserved_at_c0[0x8];
2552         u8         pd[0x18];
2553
2554         u8         lwm[0x10];
2555         u8         wqe_cnt[0x10];
2556
2557         u8         reserved_at_100[0x40];
2558
2559         u8         dbr_addr[0x40];
2560
2561         u8         reserved_at_180[0x80];
2562 };
2563
2564 enum {
2565         MLX5_SQC_STATE_RST  = 0x0,
2566         MLX5_SQC_STATE_RDY  = 0x1,
2567         MLX5_SQC_STATE_ERR  = 0x3,
2568 };
2569
2570 struct mlx5_ifc_sqc_bits {
2571         u8         rlky[0x1];
2572         u8         cd_master[0x1];
2573         u8         fre[0x1];
2574         u8         flush_in_error_en[0x1];
2575         u8         allow_multi_pkt_send_wqe[0x1];
2576         u8         min_wqe_inline_mode[0x3];
2577         u8         state[0x4];
2578         u8         reg_umr[0x1];
2579         u8         allow_swp[0x1];
2580         u8         hairpin[0x1];
2581         u8         reserved_at_f[0x11];
2582
2583         u8         reserved_at_20[0x8];
2584         u8         user_index[0x18];
2585
2586         u8         reserved_at_40[0x8];
2587         u8         cqn[0x18];
2588
2589         u8         reserved_at_60[0x8];
2590         u8         hairpin_peer_rq[0x18];
2591
2592         u8         reserved_at_80[0x10];
2593         u8         hairpin_peer_vhca[0x10];
2594
2595         u8         reserved_at_a0[0x50];
2596
2597         u8         packet_pacing_rate_limit_index[0x10];
2598         u8         tis_lst_sz[0x10];
2599         u8         reserved_at_110[0x10];
2600
2601         u8         reserved_at_120[0x40];
2602
2603         u8         reserved_at_160[0x8];
2604         u8         tis_num_0[0x18];
2605
2606         struct mlx5_ifc_wq_bits wq;
2607 };
2608
2609 enum {
2610         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2611         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2612         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2613         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2614 };
2615
2616 struct mlx5_ifc_scheduling_context_bits {
2617         u8         element_type[0x8];
2618         u8         reserved_at_8[0x18];
2619
2620         u8         element_attributes[0x20];
2621
2622         u8         parent_element_id[0x20];
2623
2624         u8         reserved_at_60[0x40];
2625
2626         u8         bw_share[0x20];
2627
2628         u8         max_average_bw[0x20];
2629
2630         u8         reserved_at_e0[0x120];
2631 };
2632
2633 struct mlx5_ifc_rqtc_bits {
2634         u8         reserved_at_0[0xa0];
2635
2636         u8         reserved_at_a0[0x10];
2637         u8         rqt_max_size[0x10];
2638
2639         u8         reserved_at_c0[0x10];
2640         u8         rqt_actual_size[0x10];
2641
2642         u8         reserved_at_e0[0x6a0];
2643
2644         struct mlx5_ifc_rq_num_bits rq_num[0];
2645 };
2646
2647 enum {
2648         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2649         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2650 };
2651
2652 enum {
2653         MLX5_RQC_STATE_RST  = 0x0,
2654         MLX5_RQC_STATE_RDY  = 0x1,
2655         MLX5_RQC_STATE_ERR  = 0x3,
2656 };
2657
2658 struct mlx5_ifc_rqc_bits {
2659         u8         rlky[0x1];
2660         u8         delay_drop_en[0x1];
2661         u8         scatter_fcs[0x1];
2662         u8         vsd[0x1];
2663         u8         mem_rq_type[0x4];
2664         u8         state[0x4];
2665         u8         reserved_at_c[0x1];
2666         u8         flush_in_error_en[0x1];
2667         u8         hairpin[0x1];
2668         u8         reserved_at_f[0x11];
2669
2670         u8         reserved_at_20[0x8];
2671         u8         user_index[0x18];
2672
2673         u8         reserved_at_40[0x8];
2674         u8         cqn[0x18];
2675
2676         u8         counter_set_id[0x8];
2677         u8         reserved_at_68[0x18];
2678
2679         u8         reserved_at_80[0x8];
2680         u8         rmpn[0x18];
2681
2682         u8         reserved_at_a0[0x8];
2683         u8         hairpin_peer_sq[0x18];
2684
2685         u8         reserved_at_c0[0x10];
2686         u8         hairpin_peer_vhca[0x10];
2687
2688         u8         reserved_at_e0[0xa0];
2689
2690         struct mlx5_ifc_wq_bits wq;
2691 };
2692
2693 enum {
2694         MLX5_RMPC_STATE_RDY  = 0x1,
2695         MLX5_RMPC_STATE_ERR  = 0x3,
2696 };
2697
2698 struct mlx5_ifc_rmpc_bits {
2699         u8         reserved_at_0[0x8];
2700         u8         state[0x4];
2701         u8         reserved_at_c[0x14];
2702
2703         u8         basic_cyclic_rcv_wqe[0x1];
2704         u8         reserved_at_21[0x1f];
2705
2706         u8         reserved_at_40[0x140];
2707
2708         struct mlx5_ifc_wq_bits wq;
2709 };
2710
2711 struct mlx5_ifc_nic_vport_context_bits {
2712         u8         reserved_at_0[0x5];
2713         u8         min_wqe_inline_mode[0x3];
2714         u8         reserved_at_8[0x15];
2715         u8         disable_mc_local_lb[0x1];
2716         u8         disable_uc_local_lb[0x1];
2717         u8         roce_en[0x1];
2718
2719         u8         arm_change_event[0x1];
2720         u8         reserved_at_21[0x1a];
2721         u8         event_on_mtu[0x1];
2722         u8         event_on_promisc_change[0x1];
2723         u8         event_on_vlan_change[0x1];
2724         u8         event_on_mc_address_change[0x1];
2725         u8         event_on_uc_address_change[0x1];
2726
2727         u8         reserved_at_40[0xc];
2728
2729         u8         affiliation_criteria[0x4];
2730         u8         affiliated_vhca_id[0x10];
2731
2732         u8         reserved_at_60[0xd0];
2733
2734         u8         mtu[0x10];
2735
2736         u8         system_image_guid[0x40];
2737         u8         port_guid[0x40];
2738         u8         node_guid[0x40];
2739
2740         u8         reserved_at_200[0x140];
2741         u8         qkey_violation_counter[0x10];
2742         u8         reserved_at_350[0x430];
2743
2744         u8         promisc_uc[0x1];
2745         u8         promisc_mc[0x1];
2746         u8         promisc_all[0x1];
2747         u8         reserved_at_783[0x2];
2748         u8         allowed_list_type[0x3];
2749         u8         reserved_at_788[0xc];
2750         u8         allowed_list_size[0xc];
2751
2752         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2753
2754         u8         reserved_at_7e0[0x20];
2755
2756         u8         current_uc_mac_address[0][0x40];
2757 };
2758
2759 enum {
2760         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2761         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2762         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2763         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2764         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2765 };
2766
2767 struct mlx5_ifc_mkc_bits {
2768         u8         reserved_at_0[0x1];
2769         u8         free[0x1];
2770         u8         reserved_at_2[0x1];
2771         u8         access_mode_4_2[0x3];
2772         u8         reserved_at_6[0x7];
2773         u8         relaxed_ordering_write[0x1];
2774         u8         reserved_at_e[0x1];
2775         u8         small_fence_on_rdma_read_response[0x1];
2776         u8         umr_en[0x1];
2777         u8         a[0x1];
2778         u8         rw[0x1];
2779         u8         rr[0x1];
2780         u8         lw[0x1];
2781         u8         lr[0x1];
2782         u8         access_mode_1_0[0x2];
2783         u8         reserved_at_18[0x8];
2784
2785         u8         qpn[0x18];
2786         u8         mkey_7_0[0x8];
2787
2788         u8         reserved_at_40[0x20];
2789
2790         u8         length64[0x1];
2791         u8         bsf_en[0x1];
2792         u8         sync_umr[0x1];
2793         u8         reserved_at_63[0x2];
2794         u8         expected_sigerr_count[0x1];
2795         u8         reserved_at_66[0x1];
2796         u8         en_rinval[0x1];
2797         u8         pd[0x18];
2798
2799         u8         start_addr[0x40];
2800
2801         u8         len[0x40];
2802
2803         u8         bsf_octword_size[0x20];
2804
2805         u8         reserved_at_120[0x80];
2806
2807         u8         translations_octword_size[0x20];
2808
2809         u8         reserved_at_1c0[0x1b];
2810         u8         log_page_size[0x5];
2811
2812         u8         reserved_at_1e0[0x20];
2813 };
2814
2815 struct mlx5_ifc_pkey_bits {
2816         u8         reserved_at_0[0x10];
2817         u8         pkey[0x10];
2818 };
2819
2820 struct mlx5_ifc_array128_auto_bits {
2821         u8         array128_auto[16][0x8];
2822 };
2823
2824 struct mlx5_ifc_hca_vport_context_bits {
2825         u8         field_select[0x20];
2826
2827         u8         reserved_at_20[0xe0];
2828
2829         u8         sm_virt_aware[0x1];
2830         u8         has_smi[0x1];
2831         u8         has_raw[0x1];
2832         u8         grh_required[0x1];
2833         u8         reserved_at_104[0xc];
2834         u8         port_physical_state[0x4];
2835         u8         vport_state_policy[0x4];
2836         u8         port_state[0x4];
2837         u8         vport_state[0x4];
2838
2839         u8         reserved_at_120[0x20];
2840
2841         u8         system_image_guid[0x40];
2842
2843         u8         port_guid[0x40];
2844
2845         u8         node_guid[0x40];
2846
2847         u8         cap_mask1[0x20];
2848
2849         u8         cap_mask1_field_select[0x20];
2850
2851         u8         cap_mask2[0x20];
2852
2853         u8         cap_mask2_field_select[0x20];
2854
2855         u8         reserved_at_280[0x80];
2856
2857         u8         lid[0x10];
2858         u8         reserved_at_310[0x4];
2859         u8         init_type_reply[0x4];
2860         u8         lmc[0x3];
2861         u8         subnet_timeout[0x5];
2862
2863         u8         sm_lid[0x10];
2864         u8         sm_sl[0x4];
2865         u8         reserved_at_334[0xc];
2866
2867         u8         qkey_violation_counter[0x10];
2868         u8         pkey_violation_counter[0x10];
2869
2870         u8         reserved_at_360[0xca0];
2871 };
2872
2873 struct mlx5_ifc_esw_vport_context_bits {
2874         u8         reserved_at_0[0x3];
2875         u8         vport_svlan_strip[0x1];
2876         u8         vport_cvlan_strip[0x1];
2877         u8         vport_svlan_insert[0x1];
2878         u8         vport_cvlan_insert[0x2];
2879         u8         reserved_at_8[0x18];
2880
2881         u8         reserved_at_20[0x20];
2882
2883         u8         svlan_cfi[0x1];
2884         u8         svlan_pcp[0x3];
2885         u8         svlan_id[0xc];
2886         u8         cvlan_cfi[0x1];
2887         u8         cvlan_pcp[0x3];
2888         u8         cvlan_id[0xc];
2889
2890         u8         reserved_at_60[0x7a0];
2891 };
2892
2893 enum {
2894         MLX5_EQC_STATUS_OK                = 0x0,
2895         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2896 };
2897
2898 enum {
2899         MLX5_EQC_ST_ARMED  = 0x9,
2900         MLX5_EQC_ST_FIRED  = 0xa,
2901 };
2902
2903 struct mlx5_ifc_eqc_bits {
2904         u8         status[0x4];
2905         u8         reserved_at_4[0x9];
2906         u8         ec[0x1];
2907         u8         oi[0x1];
2908         u8         reserved_at_f[0x5];
2909         u8         st[0x4];
2910         u8         reserved_at_18[0x8];
2911
2912         u8         reserved_at_20[0x20];
2913
2914         u8         reserved_at_40[0x14];
2915         u8         page_offset[0x6];
2916         u8         reserved_at_5a[0x6];
2917
2918         u8         reserved_at_60[0x3];
2919         u8         log_eq_size[0x5];
2920         u8         uar_page[0x18];
2921
2922         u8         reserved_at_80[0x20];
2923
2924         u8         reserved_at_a0[0x18];
2925         u8         intr[0x8];
2926
2927         u8         reserved_at_c0[0x3];
2928         u8         log_page_size[0x5];
2929         u8         reserved_at_c8[0x18];
2930
2931         u8         reserved_at_e0[0x60];
2932
2933         u8         reserved_at_140[0x8];
2934         u8         consumer_counter[0x18];
2935
2936         u8         reserved_at_160[0x8];
2937         u8         producer_counter[0x18];
2938
2939         u8         reserved_at_180[0x80];
2940 };
2941
2942 enum {
2943         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2944         MLX5_DCTC_STATE_DRAINING  = 0x1,
2945         MLX5_DCTC_STATE_DRAINED   = 0x2,
2946 };
2947
2948 enum {
2949         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2950         MLX5_DCTC_CS_RES_NA         = 0x1,
2951         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2952 };
2953
2954 enum {
2955         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2956         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2957         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2958         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2959         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2960 };
2961
2962 struct mlx5_ifc_dctc_bits {
2963         u8         reserved_at_0[0x4];
2964         u8         state[0x4];
2965         u8         reserved_at_8[0x18];
2966
2967         u8         reserved_at_20[0x8];
2968         u8         user_index[0x18];
2969
2970         u8         reserved_at_40[0x8];
2971         u8         cqn[0x18];
2972
2973         u8         counter_set_id[0x8];
2974         u8         atomic_mode[0x4];
2975         u8         rre[0x1];
2976         u8         rwe[0x1];
2977         u8         rae[0x1];
2978         u8         atomic_like_write_en[0x1];
2979         u8         latency_sensitive[0x1];
2980         u8         rlky[0x1];
2981         u8         free_ar[0x1];
2982         u8         reserved_at_73[0xd];
2983
2984         u8         reserved_at_80[0x8];
2985         u8         cs_res[0x8];
2986         u8         reserved_at_90[0x3];
2987         u8         min_rnr_nak[0x5];
2988         u8         reserved_at_98[0x8];
2989
2990         u8         reserved_at_a0[0x8];
2991         u8         srqn_xrqn[0x18];
2992
2993         u8         reserved_at_c0[0x8];
2994         u8         pd[0x18];
2995
2996         u8         tclass[0x8];
2997         u8         reserved_at_e8[0x4];
2998         u8         flow_label[0x14];
2999
3000         u8         dc_access_key[0x40];
3001
3002         u8         reserved_at_140[0x5];
3003         u8         mtu[0x3];
3004         u8         port[0x8];
3005         u8         pkey_index[0x10];
3006
3007         u8         reserved_at_160[0x8];
3008         u8         my_addr_index[0x8];
3009         u8         reserved_at_170[0x8];
3010         u8         hop_limit[0x8];
3011
3012         u8         dc_access_key_violation_count[0x20];
3013
3014         u8         reserved_at_1a0[0x14];
3015         u8         dei_cfi[0x1];
3016         u8         eth_prio[0x3];
3017         u8         ecn[0x2];
3018         u8         dscp[0x6];
3019
3020         u8         reserved_at_1c0[0x40];
3021 };
3022
3023 enum {
3024         MLX5_CQC_STATUS_OK             = 0x0,
3025         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3026         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3027 };
3028
3029 enum {
3030         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3031         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3032 };
3033
3034 enum {
3035         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3036         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3037         MLX5_CQC_ST_FIRED                                 = 0xa,
3038 };
3039
3040 enum {
3041         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3042         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3043         MLX5_CQ_PERIOD_NUM_MODES
3044 };
3045
3046 struct mlx5_ifc_cqc_bits {
3047         u8         status[0x4];
3048         u8         reserved_at_4[0x4];
3049         u8         cqe_sz[0x3];
3050         u8         cc[0x1];
3051         u8         reserved_at_c[0x1];
3052         u8         scqe_break_moderation_en[0x1];
3053         u8         oi[0x1];
3054         u8         cq_period_mode[0x2];
3055         u8         cqe_comp_en[0x1];
3056         u8         mini_cqe_res_format[0x2];
3057         u8         st[0x4];
3058         u8         reserved_at_18[0x8];
3059
3060         u8         reserved_at_20[0x20];
3061
3062         u8         reserved_at_40[0x14];
3063         u8         page_offset[0x6];
3064         u8         reserved_at_5a[0x6];
3065
3066         u8         reserved_at_60[0x3];
3067         u8         log_cq_size[0x5];
3068         u8         uar_page[0x18];
3069
3070         u8         reserved_at_80[0x4];
3071         u8         cq_period[0xc];
3072         u8         cq_max_count[0x10];
3073
3074         u8         reserved_at_a0[0x18];
3075         u8         c_eqn[0x8];
3076
3077         u8         reserved_at_c0[0x3];
3078         u8         log_page_size[0x5];
3079         u8         reserved_at_c8[0x18];
3080
3081         u8         reserved_at_e0[0x20];
3082
3083         u8         reserved_at_100[0x8];
3084         u8         last_notified_index[0x18];
3085
3086         u8         reserved_at_120[0x8];
3087         u8         last_solicit_index[0x18];
3088
3089         u8         reserved_at_140[0x8];
3090         u8         consumer_counter[0x18];
3091
3092         u8         reserved_at_160[0x8];
3093         u8         producer_counter[0x18];
3094
3095         u8         reserved_at_180[0x40];
3096
3097         u8         dbr_addr[0x40];
3098 };
3099
3100 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3101         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3102         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3103         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3104         u8         reserved_at_0[0x800];
3105 };
3106
3107 struct mlx5_ifc_query_adapter_param_block_bits {
3108         u8         reserved_at_0[0xc0];
3109
3110         u8         reserved_at_c0[0x8];
3111         u8         ieee_vendor_id[0x18];
3112
3113         u8         reserved_at_e0[0x10];
3114         u8         vsd_vendor_id[0x10];
3115
3116         u8         vsd[208][0x8];
3117
3118         u8         vsd_contd_psid[16][0x8];
3119 };
3120
3121 enum {
3122         MLX5_XRQC_STATE_GOOD   = 0x0,
3123         MLX5_XRQC_STATE_ERROR  = 0x1,
3124 };
3125
3126 enum {
3127         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3128         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3129 };
3130
3131 enum {
3132         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3133 };
3134
3135 struct mlx5_ifc_tag_matching_topology_context_bits {
3136         u8         log_matching_list_sz[0x4];
3137         u8         reserved_at_4[0xc];
3138         u8         append_next_index[0x10];
3139
3140         u8         sw_phase_cnt[0x10];
3141         u8         hw_phase_cnt[0x10];
3142
3143         u8         reserved_at_40[0x40];
3144 };
3145
3146 struct mlx5_ifc_xrqc_bits {
3147         u8         state[0x4];
3148         u8         rlkey[0x1];
3149         u8         reserved_at_5[0xf];
3150         u8         topology[0x4];
3151         u8         reserved_at_18[0x4];
3152         u8         offload[0x4];
3153
3154         u8         reserved_at_20[0x8];
3155         u8         user_index[0x18];
3156
3157         u8         reserved_at_40[0x8];
3158         u8         cqn[0x18];
3159
3160         u8         reserved_at_60[0xa0];
3161
3162         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3163
3164         u8         reserved_at_180[0x280];
3165
3166         struct mlx5_ifc_wq_bits wq;
3167 };
3168
3169 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3170         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3171         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3172         u8         reserved_at_0[0x20];
3173 };
3174
3175 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3176         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3177         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3178         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3179         u8         reserved_at_0[0x20];
3180 };
3181
3182 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3183         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3184         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3185         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3186         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3187         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3188         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3189         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3190         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3191         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3192         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3193         u8         reserved_at_0[0x7c0];
3194 };
3195
3196 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3197         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3198         u8         reserved_at_0[0x7c0];
3199 };
3200
3201 union mlx5_ifc_event_auto_bits {
3202         struct mlx5_ifc_comp_event_bits comp_event;
3203         struct mlx5_ifc_dct_events_bits dct_events;
3204         struct mlx5_ifc_qp_events_bits qp_events;
3205         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3206         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3207         struct mlx5_ifc_cq_error_bits cq_error;
3208         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3209         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3210         struct mlx5_ifc_gpio_event_bits gpio_event;
3211         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3212         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3213         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3214         u8         reserved_at_0[0xe0];
3215 };
3216
3217 struct mlx5_ifc_health_buffer_bits {
3218         u8         reserved_at_0[0x100];
3219
3220         u8         assert_existptr[0x20];
3221
3222         u8         assert_callra[0x20];
3223
3224         u8         reserved_at_140[0x40];
3225
3226         u8         fw_version[0x20];
3227
3228         u8         hw_id[0x20];
3229
3230         u8         reserved_at_1c0[0x20];
3231
3232         u8         irisc_index[0x8];
3233         u8         synd[0x8];
3234         u8         ext_synd[0x10];
3235 };
3236
3237 struct mlx5_ifc_register_loopback_control_bits {
3238         u8         no_lb[0x1];
3239         u8         reserved_at_1[0x7];
3240         u8         port[0x8];
3241         u8         reserved_at_10[0x10];
3242
3243         u8         reserved_at_20[0x60];
3244 };
3245
3246 struct mlx5_ifc_vport_tc_element_bits {
3247         u8         traffic_class[0x4];
3248         u8         reserved_at_4[0xc];
3249         u8         vport_number[0x10];
3250 };
3251
3252 struct mlx5_ifc_vport_element_bits {
3253         u8         reserved_at_0[0x10];
3254         u8         vport_number[0x10];
3255 };
3256
3257 enum {