Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65
66 enum {
67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72
73 enum {
74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
77 };
78
79 enum {
80         MLX5_SHARED_RESOURCE_UID = 0xffff,
81 };
82
83 enum {
84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85 };
86
87 enum {
88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 };
91
92 enum {
93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94         MLX5_OBJ_TYPE_MKEY = 0xff01,
95         MLX5_OBJ_TYPE_QP = 0xff02,
96         MLX5_OBJ_TYPE_PSV = 0xff03,
97         MLX5_OBJ_TYPE_RMP = 0xff04,
98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99         MLX5_OBJ_TYPE_RQ = 0xff06,
100         MLX5_OBJ_TYPE_SQ = 0xff07,
101         MLX5_OBJ_TYPE_TIR = 0xff08,
102         MLX5_OBJ_TYPE_TIS = 0xff09,
103         MLX5_OBJ_TYPE_DCT = 0xff0a,
104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
105         MLX5_OBJ_TYPE_RQT = 0xff0e,
106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107         MLX5_OBJ_TYPE_CQ = 0xff10,
108 };
109
110 enum {
111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
175         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
176         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
177         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
178         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
179         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
180         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
181         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
182         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
183         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
184         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
185         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
186         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
187         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
188         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
189         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
190         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
191         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
192         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
193         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
194         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
195         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
196         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
197         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
198         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
199         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
200         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
201         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
202         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
203         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
204         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
205         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
206         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
207         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
208         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
209         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
210         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
211         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
212         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
213         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
214         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
215         MLX5_CMD_OP_NOP                           = 0x80d,
216         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
217         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
218         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
219         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
220         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
221         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
222         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
223         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
224         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
225         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
226         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
227         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
228         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
229         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
230         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
231         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
232         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
233         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
234         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
235         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
236         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
237         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
238         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
239         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
240         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
241         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
242         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
243         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
244         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
245         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
246         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
247         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
248         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
249         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
250         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
251         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
252         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
253         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
254         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
255         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
256         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
257         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
258         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
259         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
260         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
261         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
262         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
263         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
264         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
265         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
266         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
267         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
268         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
269         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
270         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
271         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
272         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
273         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
274         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
275         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
276         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
277         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
278         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
279         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
280         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
281         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
282         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
283         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
284         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
285         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
286         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
287         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
288         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
289         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
290         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
291         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
292         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
293         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
294         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
295         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
296         MLX5_CMD_OP_MAX
297 };
298
299 /* Valid range for general commands that don't work over an object */
300 enum {
301         MLX5_CMD_OP_GENERAL_START = 0xb00,
302         MLX5_CMD_OP_GENERAL_END = 0xd00,
303 };
304
305 struct mlx5_ifc_flow_table_fields_supported_bits {
306         u8         outer_dmac[0x1];
307         u8         outer_smac[0x1];
308         u8         outer_ether_type[0x1];
309         u8         outer_ip_version[0x1];
310         u8         outer_first_prio[0x1];
311         u8         outer_first_cfi[0x1];
312         u8         outer_first_vid[0x1];
313         u8         outer_ipv4_ttl[0x1];
314         u8         outer_second_prio[0x1];
315         u8         outer_second_cfi[0x1];
316         u8         outer_second_vid[0x1];
317         u8         reserved_at_b[0x1];
318         u8         outer_sip[0x1];
319         u8         outer_dip[0x1];
320         u8         outer_frag[0x1];
321         u8         outer_ip_protocol[0x1];
322         u8         outer_ip_ecn[0x1];
323         u8         outer_ip_dscp[0x1];
324         u8         outer_udp_sport[0x1];
325         u8         outer_udp_dport[0x1];
326         u8         outer_tcp_sport[0x1];
327         u8         outer_tcp_dport[0x1];
328         u8         outer_tcp_flags[0x1];
329         u8         outer_gre_protocol[0x1];
330         u8         outer_gre_key[0x1];
331         u8         outer_vxlan_vni[0x1];
332         u8         outer_geneve_vni[0x1];
333         u8         outer_geneve_oam[0x1];
334         u8         outer_geneve_protocol_type[0x1];
335         u8         outer_geneve_opt_len[0x1];
336         u8         reserved_at_1e[0x1];
337         u8         source_eswitch_port[0x1];
338
339         u8         inner_dmac[0x1];
340         u8         inner_smac[0x1];
341         u8         inner_ether_type[0x1];
342         u8         inner_ip_version[0x1];
343         u8         inner_first_prio[0x1];
344         u8         inner_first_cfi[0x1];
345         u8         inner_first_vid[0x1];
346         u8         reserved_at_27[0x1];
347         u8         inner_second_prio[0x1];
348         u8         inner_second_cfi[0x1];
349         u8         inner_second_vid[0x1];
350         u8         reserved_at_2b[0x1];
351         u8         inner_sip[0x1];
352         u8         inner_dip[0x1];
353         u8         inner_frag[0x1];
354         u8         inner_ip_protocol[0x1];
355         u8         inner_ip_ecn[0x1];
356         u8         inner_ip_dscp[0x1];
357         u8         inner_udp_sport[0x1];
358         u8         inner_udp_dport[0x1];
359         u8         inner_tcp_sport[0x1];
360         u8         inner_tcp_dport[0x1];
361         u8         inner_tcp_flags[0x1];
362         u8         reserved_at_37[0x9];
363
364         u8         geneve_tlv_option_0_data[0x1];
365         u8         reserved_at_41[0x4];
366         u8         outer_first_mpls_over_udp[0x4];
367         u8         outer_first_mpls_over_gre[0x4];
368         u8         inner_first_mpls[0x4];
369         u8         outer_first_mpls[0x4];
370         u8         reserved_at_55[0x2];
371         u8         outer_esp_spi[0x1];
372         u8         reserved_at_58[0x2];
373         u8         bth_dst_qp[0x1];
374
375         u8         reserved_at_5b[0x25];
376 };
377
378 struct mlx5_ifc_flow_table_prop_layout_bits {
379         u8         ft_support[0x1];
380         u8         reserved_at_1[0x1];
381         u8         flow_counter[0x1];
382         u8         flow_modify_en[0x1];
383         u8         modify_root[0x1];
384         u8         identified_miss_table_mode[0x1];
385         u8         flow_table_modify[0x1];
386         u8         reformat[0x1];
387         u8         decap[0x1];
388         u8         reserved_at_9[0x1];
389         u8         pop_vlan[0x1];
390         u8         push_vlan[0x1];
391         u8         reserved_at_c[0x1];
392         u8         pop_vlan_2[0x1];
393         u8         push_vlan_2[0x1];
394         u8         reformat_and_vlan_action[0x1];
395         u8         reserved_at_10[0x1];
396         u8         sw_owner[0x1];
397         u8         reformat_l3_tunnel_to_l2[0x1];
398         u8         reformat_l2_to_l3_tunnel[0x1];
399         u8         reformat_and_modify_action[0x1];
400         u8         reserved_at_15[0x2];
401         u8         table_miss_action_domain[0x1];
402         u8         termination_table[0x1];
403         u8         reserved_at_19[0x7];
404         u8         reserved_at_20[0x2];
405         u8         log_max_ft_size[0x6];
406         u8         log_max_modify_header_context[0x8];
407         u8         max_modify_header_actions[0x8];
408         u8         max_ft_level[0x8];
409
410         u8         reserved_at_40[0x20];
411
412         u8         reserved_at_60[0x18];
413         u8         log_max_ft_num[0x8];
414
415         u8         reserved_at_80[0x18];
416         u8         log_max_destination[0x8];
417
418         u8         log_max_flow_counter[0x8];
419         u8         reserved_at_a8[0x10];
420         u8         log_max_flow[0x8];
421
422         u8         reserved_at_c0[0x40];
423
424         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
425
426         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
427 };
428
429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
430         u8         send[0x1];
431         u8         receive[0x1];
432         u8         write[0x1];
433         u8         read[0x1];
434         u8         atomic[0x1];
435         u8         srq_receive[0x1];
436         u8         reserved_at_6[0x1a];
437 };
438
439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
440         u8         smac_47_16[0x20];
441
442         u8         smac_15_0[0x10];
443         u8         ethertype[0x10];
444
445         u8         dmac_47_16[0x20];
446
447         u8         dmac_15_0[0x10];
448         u8         first_prio[0x3];
449         u8         first_cfi[0x1];
450         u8         first_vid[0xc];
451
452         u8         ip_protocol[0x8];
453         u8         ip_dscp[0x6];
454         u8         ip_ecn[0x2];
455         u8         cvlan_tag[0x1];
456         u8         svlan_tag[0x1];
457         u8         frag[0x1];
458         u8         ip_version[0x4];
459         u8         tcp_flags[0x9];
460
461         u8         tcp_sport[0x10];
462         u8         tcp_dport[0x10];
463
464         u8         reserved_at_c0[0x18];
465         u8         ttl_hoplimit[0x8];
466
467         u8         udp_sport[0x10];
468         u8         udp_dport[0x10];
469
470         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
471
472         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
473 };
474
475 struct mlx5_ifc_nvgre_key_bits {
476         u8 hi[0x18];
477         u8 lo[0x8];
478 };
479
480 union mlx5_ifc_gre_key_bits {
481         struct mlx5_ifc_nvgre_key_bits nvgre;
482         u8 key[0x20];
483 };
484
485 struct mlx5_ifc_fte_match_set_misc_bits {
486         u8         reserved_at_0[0x8];
487         u8         source_sqn[0x18];
488
489         u8         source_eswitch_owner_vhca_id[0x10];
490         u8         source_port[0x10];
491
492         u8         outer_second_prio[0x3];
493         u8         outer_second_cfi[0x1];
494         u8         outer_second_vid[0xc];
495         u8         inner_second_prio[0x3];
496         u8         inner_second_cfi[0x1];
497         u8         inner_second_vid[0xc];
498
499         u8         outer_second_cvlan_tag[0x1];
500         u8         inner_second_cvlan_tag[0x1];
501         u8         outer_second_svlan_tag[0x1];
502         u8         inner_second_svlan_tag[0x1];
503         u8         reserved_at_64[0xc];
504         u8         gre_protocol[0x10];
505
506         union mlx5_ifc_gre_key_bits gre_key;
507
508         u8         vxlan_vni[0x18];
509         u8         reserved_at_b8[0x8];
510
511         u8         geneve_vni[0x18];
512         u8         reserved_at_d8[0x7];
513         u8         geneve_oam[0x1];
514
515         u8         reserved_at_e0[0xc];
516         u8         outer_ipv6_flow_label[0x14];
517
518         u8         reserved_at_100[0xc];
519         u8         inner_ipv6_flow_label[0x14];
520
521         u8         reserved_at_120[0xa];
522         u8         geneve_opt_len[0x6];
523         u8         geneve_protocol_type[0x10];
524
525         u8         reserved_at_140[0x8];
526         u8         bth_dst_qp[0x18];
527         u8         reserved_at_160[0x20];
528         u8         outer_esp_spi[0x20];
529         u8         reserved_at_1a0[0x60];
530 };
531
532 struct mlx5_ifc_fte_match_mpls_bits {
533         u8         mpls_label[0x14];
534         u8         mpls_exp[0x3];
535         u8         mpls_s_bos[0x1];
536         u8         mpls_ttl[0x8];
537 };
538
539 struct mlx5_ifc_fte_match_set_misc2_bits {
540         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
541
542         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
543
544         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
545
546         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
547
548         u8         metadata_reg_c_7[0x20];
549
550         u8         metadata_reg_c_6[0x20];
551
552         u8         metadata_reg_c_5[0x20];
553
554         u8         metadata_reg_c_4[0x20];
555
556         u8         metadata_reg_c_3[0x20];
557
558         u8         metadata_reg_c_2[0x20];
559
560         u8         metadata_reg_c_1[0x20];
561
562         u8         metadata_reg_c_0[0x20];
563
564         u8         metadata_reg_a[0x20];
565
566         u8         reserved_at_1a0[0x60];
567 };
568
569 struct mlx5_ifc_fte_match_set_misc3_bits {
570         u8         reserved_at_0[0x120];
571         u8         geneve_tlv_option_0_data[0x20];
572         u8         reserved_at_140[0xc0];
573 };
574
575 struct mlx5_ifc_cmd_pas_bits {
576         u8         pa_h[0x20];
577
578         u8         pa_l[0x14];
579         u8         reserved_at_34[0xc];
580 };
581
582 struct mlx5_ifc_uint64_bits {
583         u8         hi[0x20];
584
585         u8         lo[0x20];
586 };
587
588 enum {
589         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
590         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
591         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
592         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
593         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
594         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
595         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
596         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
597         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
598         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
599 };
600
601 struct mlx5_ifc_ads_bits {
602         u8         fl[0x1];
603         u8         free_ar[0x1];
604         u8         reserved_at_2[0xe];
605         u8         pkey_index[0x10];
606
607         u8         reserved_at_20[0x8];
608         u8         grh[0x1];
609         u8         mlid[0x7];
610         u8         rlid[0x10];
611
612         u8         ack_timeout[0x5];
613         u8         reserved_at_45[0x3];
614         u8         src_addr_index[0x8];
615         u8         reserved_at_50[0x4];
616         u8         stat_rate[0x4];
617         u8         hop_limit[0x8];
618
619         u8         reserved_at_60[0x4];
620         u8         tclass[0x8];
621         u8         flow_label[0x14];
622
623         u8         rgid_rip[16][0x8];
624
625         u8         reserved_at_100[0x4];
626         u8         f_dscp[0x1];
627         u8         f_ecn[0x1];
628         u8         reserved_at_106[0x1];
629         u8         f_eth_prio[0x1];
630         u8         ecn[0x2];
631         u8         dscp[0x6];
632         u8         udp_sport[0x10];
633
634         u8         dei_cfi[0x1];
635         u8         eth_prio[0x3];
636         u8         sl[0x4];
637         u8         vhca_port_num[0x8];
638         u8         rmac_47_32[0x10];
639
640         u8         rmac_31_0[0x20];
641 };
642
643 struct mlx5_ifc_flow_table_nic_cap_bits {
644         u8         nic_rx_multi_path_tirs[0x1];
645         u8         nic_rx_multi_path_tirs_fts[0x1];
646         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
647         u8         reserved_at_3[0x1d];
648         u8         encap_general_header[0x1];
649         u8         reserved_at_21[0xa];
650         u8         log_max_packet_reformat_context[0x5];
651         u8         reserved_at_30[0x6];
652         u8         max_encap_header_size[0xa];
653         u8         reserved_at_40[0x1c0];
654
655         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
656
657         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
658
659         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
660
661         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
662
663         u8         reserved_at_a00[0x200];
664
665         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
666
667         u8         reserved_at_e00[0x7200];
668 };
669
670 enum {
671         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
672         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
673         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
674         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
675         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
676         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
677         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
678         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
679 };
680
681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
682         u8      fdb_to_vport_reg_c_id[0x8];
683         u8      reserved_at_8[0xf];
684         u8      flow_source[0x1];
685         u8      reserved_at_18[0x2];
686         u8      multi_fdb_encap[0x1];
687         u8      reserved_at_1b[0x1];
688         u8      fdb_multi_path_to_table[0x1];
689         u8      reserved_at_1d[0x3];
690
691         u8      reserved_at_20[0x1e0];
692
693         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
694
695         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
696
697         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
698
699         u8      reserved_at_800[0x7800];
700 };
701
702 enum {
703         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
704         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
705 };
706
707 struct mlx5_ifc_e_switch_cap_bits {
708         u8         vport_svlan_strip[0x1];
709         u8         vport_cvlan_strip[0x1];
710         u8         vport_svlan_insert[0x1];
711         u8         vport_cvlan_insert_if_not_exist[0x1];
712         u8         vport_cvlan_insert_overwrite[0x1];
713         u8         reserved_at_5[0x3];
714         u8         esw_uplink_ingress_acl[0x1];
715         u8         reserved_at_9[0x10];
716         u8         esw_functions_changed[0x1];
717         u8         reserved_at_1a[0x1];
718         u8         ecpf_vport_exists[0x1];
719         u8         counter_eswitch_affinity[0x1];
720         u8         merged_eswitch[0x1];
721         u8         nic_vport_node_guid_modify[0x1];
722         u8         nic_vport_port_guid_modify[0x1];
723
724         u8         vxlan_encap_decap[0x1];
725         u8         nvgre_encap_decap[0x1];
726         u8         reserved_at_22[0x1];
727         u8         log_max_fdb_encap_uplink[0x5];
728         u8         reserved_at_21[0x3];
729         u8         log_max_packet_reformat_context[0x5];
730         u8         reserved_2b[0x6];
731         u8         max_encap_header_size[0xa];
732
733         u8         reserved_at_40[0xb];
734         u8         log_max_esw_sf[0x5];
735         u8         esw_sf_base_id[0x10];
736
737         u8         reserved_at_60[0x7a0];
738
739 };
740
741 struct mlx5_ifc_qos_cap_bits {
742         u8         packet_pacing[0x1];
743         u8         esw_scheduling[0x1];
744         u8         esw_bw_share[0x1];
745         u8         esw_rate_limit[0x1];
746         u8         reserved_at_4[0x1];
747         u8         packet_pacing_burst_bound[0x1];
748         u8         packet_pacing_typical_size[0x1];
749         u8         reserved_at_7[0x19];
750
751         u8         reserved_at_20[0x20];
752
753         u8         packet_pacing_max_rate[0x20];
754
755         u8         packet_pacing_min_rate[0x20];
756
757         u8         reserved_at_80[0x10];
758         u8         packet_pacing_rate_table_size[0x10];
759
760         u8         esw_element_type[0x10];
761         u8         esw_tsar_type[0x10];
762
763         u8         reserved_at_c0[0x10];
764         u8         max_qos_para_vport[0x10];
765
766         u8         max_tsar_bw_share[0x20];
767
768         u8         reserved_at_100[0x700];
769 };
770
771 struct mlx5_ifc_debug_cap_bits {
772         u8         core_dump_general[0x1];
773         u8         core_dump_qp[0x1];
774         u8         reserved_at_2[0x1e];
775
776         u8         reserved_at_20[0x2];
777         u8         stall_detect[0x1];
778         u8         reserved_at_23[0x1d];
779
780         u8         reserved_at_40[0x7c0];
781 };
782
783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
784         u8         csum_cap[0x1];
785         u8         vlan_cap[0x1];
786         u8         lro_cap[0x1];
787         u8         lro_psh_flag[0x1];
788         u8         lro_time_stamp[0x1];
789         u8         reserved_at_5[0x2];
790         u8         wqe_vlan_insert[0x1];
791         u8         self_lb_en_modifiable[0x1];
792         u8         reserved_at_9[0x2];
793         u8         max_lso_cap[0x5];
794         u8         multi_pkt_send_wqe[0x2];
795         u8         wqe_inline_mode[0x2];
796         u8         rss_ind_tbl_cap[0x4];
797         u8         reg_umr_sq[0x1];
798         u8         scatter_fcs[0x1];
799         u8         enhanced_multi_pkt_send_wqe[0x1];
800         u8         tunnel_lso_const_out_ip_id[0x1];
801         u8         reserved_at_1c[0x2];
802         u8         tunnel_stateless_gre[0x1];
803         u8         tunnel_stateless_vxlan[0x1];
804
805         u8         swp[0x1];
806         u8         swp_csum[0x1];
807         u8         swp_lso[0x1];
808         u8         cqe_checksum_full[0x1];
809         u8         reserved_at_24[0xc];
810         u8         max_vxlan_udp_ports[0x8];
811         u8         reserved_at_38[0x6];
812         u8         max_geneve_opt_len[0x1];
813         u8         tunnel_stateless_geneve_rx[0x1];
814
815         u8         reserved_at_40[0x10];
816         u8         lro_min_mss_size[0x10];
817
818         u8         reserved_at_60[0x120];
819
820         u8         lro_timer_supported_periods[4][0x20];
821
822         u8         reserved_at_200[0x600];
823 };
824
825 struct mlx5_ifc_roce_cap_bits {
826         u8         roce_apm[0x1];
827         u8         reserved_at_1[0x1f];
828
829         u8         reserved_at_20[0x60];
830
831         u8         reserved_at_80[0xc];
832         u8         l3_type[0x4];
833         u8         reserved_at_90[0x8];
834         u8         roce_version[0x8];
835
836         u8         reserved_at_a0[0x10];
837         u8         r_roce_dest_udp_port[0x10];
838
839         u8         r_roce_max_src_udp_port[0x10];
840         u8         r_roce_min_src_udp_port[0x10];
841
842         u8         reserved_at_e0[0x10];
843         u8         roce_address_table_size[0x10];
844
845         u8         reserved_at_100[0x700];
846 };
847
848 struct mlx5_ifc_device_mem_cap_bits {
849         u8         memic[0x1];
850         u8         reserved_at_1[0x1f];
851
852         u8         reserved_at_20[0xb];
853         u8         log_min_memic_alloc_size[0x5];
854         u8         reserved_at_30[0x8];
855         u8         log_max_memic_addr_alignment[0x8];
856
857         u8         memic_bar_start_addr[0x40];
858
859         u8         memic_bar_size[0x20];
860
861         u8         max_memic_size[0x20];
862
863         u8         steering_sw_icm_start_address[0x40];
864
865         u8         reserved_at_100[0x8];
866         u8         log_header_modify_sw_icm_size[0x8];
867         u8         reserved_at_110[0x2];
868         u8         log_sw_icm_alloc_granularity[0x6];
869         u8         log_steering_sw_icm_size[0x8];
870
871         u8         reserved_at_120[0x20];
872
873         u8         header_modify_sw_icm_start_address[0x40];
874
875         u8         reserved_at_180[0x680];
876 };
877
878 struct mlx5_ifc_device_event_cap_bits {
879         u8         user_affiliated_events[4][0x40];
880
881         u8         user_unaffiliated_events[4][0x40];
882 };
883
884 enum {
885         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
886         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
887         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
888         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
889         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
890         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
891         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
892         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
893         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
894 };
895
896 enum {
897         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
898         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
899         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
900         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
901         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
902         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
903         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
904         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
905         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
906 };
907
908 struct mlx5_ifc_atomic_caps_bits {
909         u8         reserved_at_0[0x40];
910
911         u8         atomic_req_8B_endianness_mode[0x2];
912         u8         reserved_at_42[0x4];
913         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
914
915         u8         reserved_at_47[0x19];
916
917         u8         reserved_at_60[0x20];
918
919         u8         reserved_at_80[0x10];
920         u8         atomic_operations[0x10];
921
922         u8         reserved_at_a0[0x10];
923         u8         atomic_size_qp[0x10];
924
925         u8         reserved_at_c0[0x10];
926         u8         atomic_size_dc[0x10];
927
928         u8         reserved_at_e0[0x720];
929 };
930
931 struct mlx5_ifc_odp_cap_bits {
932         u8         reserved_at_0[0x40];
933
934         u8         sig[0x1];
935         u8         reserved_at_41[0x1f];
936
937         u8         reserved_at_60[0x20];
938
939         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
940
941         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
942
943         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
944
945         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
946
947         u8         reserved_at_100[0x700];
948 };
949
950 struct mlx5_ifc_calc_op {
951         u8        reserved_at_0[0x10];
952         u8        reserved_at_10[0x9];
953         u8        op_swap_endianness[0x1];
954         u8        op_min[0x1];
955         u8        op_xor[0x1];
956         u8        op_or[0x1];
957         u8        op_and[0x1];
958         u8        op_max[0x1];
959         u8        op_add[0x1];
960 };
961
962 struct mlx5_ifc_vector_calc_cap_bits {
963         u8         calc_matrix[0x1];
964         u8         reserved_at_1[0x1f];
965         u8         reserved_at_20[0x8];
966         u8         max_vec_count[0x8];
967         u8         reserved_at_30[0xd];
968         u8         max_chunk_size[0x3];
969         struct mlx5_ifc_calc_op calc0;
970         struct mlx5_ifc_calc_op calc1;
971         struct mlx5_ifc_calc_op calc2;
972         struct mlx5_ifc_calc_op calc3;
973
974         u8         reserved_at_c0[0x720];
975 };
976
977 struct mlx5_ifc_tls_cap_bits {
978         u8         tls_1_2_aes_gcm_128[0x1];
979         u8         tls_1_3_aes_gcm_128[0x1];
980         u8         tls_1_2_aes_gcm_256[0x1];
981         u8         tls_1_3_aes_gcm_256[0x1];
982         u8         reserved_at_4[0x1c];
983
984         u8         reserved_at_20[0x7e0];
985 };
986
987 enum {
988         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
989         MLX5_WQ_TYPE_CYCLIC       = 0x1,
990         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
991         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
992 };
993
994 enum {
995         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
996         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
997 };
998
999 enum {
1000         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1001         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1002         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1003         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1004         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1005 };
1006
1007 enum {
1008         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1009         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1010         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1011         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1012         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1013         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1014 };
1015
1016 enum {
1017         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1018         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1019 };
1020
1021 enum {
1022         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1023         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1024         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1025 };
1026
1027 enum {
1028         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1029         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1030 };
1031
1032 enum {
1033         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1034         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1035         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1036 };
1037
1038 enum {
1039         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1040         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1041 };
1042
1043 struct mlx5_ifc_cmd_hca_cap_bits {
1044         u8         reserved_at_0[0x30];
1045         u8         vhca_id[0x10];
1046
1047         u8         reserved_at_40[0x40];
1048
1049         u8         log_max_srq_sz[0x8];
1050         u8         log_max_qp_sz[0x8];
1051         u8         event_cap[0x1];
1052         u8         reserved_at_91[0x7];
1053         u8         prio_tag_required[0x1];
1054         u8         reserved_at_99[0x2];
1055         u8         log_max_qp[0x5];
1056
1057         u8         reserved_at_a0[0xb];
1058         u8         log_max_srq[0x5];
1059         u8         reserved_at_b0[0x10];
1060
1061         u8         reserved_at_c0[0x8];
1062         u8         log_max_cq_sz[0x8];
1063         u8         reserved_at_d0[0xb];
1064         u8         log_max_cq[0x5];
1065
1066         u8         log_max_eq_sz[0x8];
1067         u8         reserved_at_e8[0x2];
1068         u8         log_max_mkey[0x6];
1069         u8         reserved_at_f0[0x8];
1070         u8         dump_fill_mkey[0x1];
1071         u8         reserved_at_f9[0x2];
1072         u8         fast_teardown[0x1];
1073         u8         log_max_eq[0x4];
1074
1075         u8         max_indirection[0x8];
1076         u8         fixed_buffer_size[0x1];
1077         u8         log_max_mrw_sz[0x7];
1078         u8         force_teardown[0x1];
1079         u8         reserved_at_111[0x1];
1080         u8         log_max_bsf_list_size[0x6];
1081         u8         umr_extended_translation_offset[0x1];
1082         u8         null_mkey[0x1];
1083         u8         log_max_klm_list_size[0x6];
1084
1085         u8         reserved_at_120[0xa];
1086         u8         log_max_ra_req_dc[0x6];
1087         u8         reserved_at_130[0xa];
1088         u8         log_max_ra_res_dc[0x6];
1089
1090         u8         reserved_at_140[0xa];
1091         u8         log_max_ra_req_qp[0x6];
1092         u8         reserved_at_150[0xa];
1093         u8         log_max_ra_res_qp[0x6];
1094
1095         u8         end_pad[0x1];
1096         u8         cc_query_allowed[0x1];
1097         u8         cc_modify_allowed[0x1];
1098         u8         start_pad[0x1];
1099         u8         cache_line_128byte[0x1];
1100         u8         reserved_at_165[0x4];
1101         u8         rts2rts_qp_counters_set_id[0x1];
1102         u8         reserved_at_16a[0x5];
1103         u8         qcam_reg[0x1];
1104         u8         gid_table_size[0x10];
1105
1106         u8         out_of_seq_cnt[0x1];
1107         u8         vport_counters[0x1];
1108         u8         retransmission_q_counters[0x1];
1109         u8         debug[0x1];
1110         u8         modify_rq_counter_set_id[0x1];
1111         u8         rq_delay_drop[0x1];
1112         u8         max_qp_cnt[0xa];
1113         u8         pkey_table_size[0x10];
1114
1115         u8         vport_group_manager[0x1];
1116         u8         vhca_group_manager[0x1];
1117         u8         ib_virt[0x1];
1118         u8         eth_virt[0x1];
1119         u8         vnic_env_queue_counters[0x1];
1120         u8         ets[0x1];
1121         u8         nic_flow_table[0x1];
1122         u8         eswitch_manager[0x1];
1123         u8         device_memory[0x1];
1124         u8         mcam_reg[0x1];
1125         u8         pcam_reg[0x1];
1126         u8         local_ca_ack_delay[0x5];
1127         u8         port_module_event[0x1];
1128         u8         enhanced_error_q_counters[0x1];
1129         u8         ports_check[0x1];
1130         u8         reserved_at_1b3[0x1];
1131         u8         disable_link_up[0x1];
1132         u8         beacon_led[0x1];
1133         u8         port_type[0x2];
1134         u8         num_ports[0x8];
1135
1136         u8         reserved_at_1c0[0x1];
1137         u8         pps[0x1];
1138         u8         pps_modify[0x1];
1139         u8         log_max_msg[0x5];
1140         u8         reserved_at_1c8[0x4];
1141         u8         max_tc[0x4];
1142         u8         temp_warn_event[0x1];
1143         u8         dcbx[0x1];
1144         u8         general_notification_event[0x1];
1145         u8         reserved_at_1d3[0x2];
1146         u8         fpga[0x1];
1147         u8         rol_s[0x1];
1148         u8         rol_g[0x1];
1149         u8         reserved_at_1d8[0x1];
1150         u8         wol_s[0x1];
1151         u8         wol_g[0x1];
1152         u8         wol_a[0x1];
1153         u8         wol_b[0x1];
1154         u8         wol_m[0x1];
1155         u8         wol_u[0x1];
1156         u8         wol_p[0x1];
1157
1158         u8         stat_rate_support[0x10];
1159         u8         reserved_at_1f0[0xc];
1160         u8         cqe_version[0x4];
1161
1162         u8         compact_address_vector[0x1];
1163         u8         striding_rq[0x1];
1164         u8         reserved_at_202[0x1];
1165         u8         ipoib_enhanced_offloads[0x1];
1166         u8         ipoib_basic_offloads[0x1];
1167         u8         reserved_at_205[0x1];
1168         u8         repeated_block_disabled[0x1];
1169         u8         umr_modify_entity_size_disabled[0x1];
1170         u8         umr_modify_atomic_disabled[0x1];
1171         u8         umr_indirect_mkey_disabled[0x1];
1172         u8         umr_fence[0x2];
1173         u8         dc_req_scat_data_cqe[0x1];
1174         u8         reserved_at_20d[0x2];
1175         u8         drain_sigerr[0x1];
1176         u8         cmdif_checksum[0x2];
1177         u8         sigerr_cqe[0x1];
1178         u8         reserved_at_213[0x1];
1179         u8         wq_signature[0x1];
1180         u8         sctr_data_cqe[0x1];
1181         u8         reserved_at_216[0x1];
1182         u8         sho[0x1];
1183         u8         tph[0x1];
1184         u8         rf[0x1];
1185         u8         dct[0x1];
1186         u8         qos[0x1];
1187         u8         eth_net_offloads[0x1];
1188         u8         roce[0x1];
1189         u8         atomic[0x1];
1190         u8         reserved_at_21f[0x1];
1191
1192         u8         cq_oi[0x1];
1193         u8         cq_resize[0x1];
1194         u8         cq_moderation[0x1];
1195         u8         reserved_at_223[0x3];
1196         u8         cq_eq_remap[0x1];
1197         u8         pg[0x1];
1198         u8         block_lb_mc[0x1];
1199         u8         reserved_at_229[0x1];
1200         u8         scqe_break_moderation[0x1];
1201         u8         cq_period_start_from_cqe[0x1];
1202         u8         cd[0x1];
1203         u8         reserved_at_22d[0x1];
1204         u8         apm[0x1];
1205         u8         vector_calc[0x1];
1206         u8         umr_ptr_rlky[0x1];
1207         u8         imaicl[0x1];
1208         u8         qp_packet_based[0x1];
1209         u8         reserved_at_233[0x3];
1210         u8         qkv[0x1];
1211         u8         pkv[0x1];
1212         u8         set_deth_sqpn[0x1];
1213         u8         reserved_at_239[0x3];
1214         u8         xrc[0x1];
1215         u8         ud[0x1];
1216         u8         uc[0x1];
1217         u8         rc[0x1];
1218
1219         u8         uar_4k[0x1];
1220         u8         reserved_at_241[0x9];
1221         u8         uar_sz[0x6];
1222         u8         reserved_at_250[0x8];
1223         u8         log_pg_sz[0x8];
1224
1225         u8         bf[0x1];
1226         u8         driver_version[0x1];
1227         u8         pad_tx_eth_packet[0x1];
1228         u8         reserved_at_263[0x8];
1229         u8         log_bf_reg_size[0x5];
1230
1231         u8         reserved_at_270[0xb];
1232         u8         lag_master[0x1];
1233         u8         num_lag_ports[0x4];
1234
1235         u8         reserved_at_280[0x10];
1236         u8         max_wqe_sz_sq[0x10];
1237
1238         u8         reserved_at_2a0[0x10];
1239         u8         max_wqe_sz_rq[0x10];
1240
1241         u8         max_flow_counter_31_16[0x10];
1242         u8         max_wqe_sz_sq_dc[0x10];
1243
1244         u8         reserved_at_2e0[0x7];
1245         u8         max_qp_mcg[0x19];
1246
1247         u8         reserved_at_300[0x18];
1248         u8         log_max_mcg[0x8];
1249
1250         u8         reserved_at_320[0x3];
1251         u8         log_max_transport_domain[0x5];
1252         u8         reserved_at_328[0x3];
1253         u8         log_max_pd[0x5];
1254         u8         reserved_at_330[0xb];
1255         u8         log_max_xrcd[0x5];
1256
1257         u8         nic_receive_steering_discard[0x1];
1258         u8         receive_discard_vport_down[0x1];
1259         u8         transmit_discard_vport_down[0x1];
1260         u8         reserved_at_343[0x5];
1261         u8         log_max_flow_counter_bulk[0x8];
1262         u8         max_flow_counter_15_0[0x10];
1263
1264
1265         u8         reserved_at_360[0x3];
1266         u8         log_max_rq[0x5];
1267         u8         reserved_at_368[0x3];
1268         u8         log_max_sq[0x5];
1269         u8         reserved_at_370[0x3];
1270         u8         log_max_tir[0x5];
1271         u8         reserved_at_378[0x3];
1272         u8         log_max_tis[0x5];
1273
1274         u8         basic_cyclic_rcv_wqe[0x1];
1275         u8         reserved_at_381[0x2];
1276         u8         log_max_rmp[0x5];
1277         u8         reserved_at_388[0x3];
1278         u8         log_max_rqt[0x5];
1279         u8         reserved_at_390[0x3];
1280         u8         log_max_rqt_size[0x5];
1281         u8         reserved_at_398[0x3];
1282         u8         log_max_tis_per_sq[0x5];
1283
1284         u8         ext_stride_num_range[0x1];
1285         u8         reserved_at_3a1[0x2];
1286         u8         log_max_stride_sz_rq[0x5];
1287         u8         reserved_at_3a8[0x3];
1288         u8         log_min_stride_sz_rq[0x5];
1289         u8         reserved_at_3b0[0x3];
1290         u8         log_max_stride_sz_sq[0x5];
1291         u8         reserved_at_3b8[0x3];
1292         u8         log_min_stride_sz_sq[0x5];
1293
1294         u8         hairpin[0x1];
1295         u8         reserved_at_3c1[0x2];
1296         u8         log_max_hairpin_queues[0x5];
1297         u8         reserved_at_3c8[0x3];
1298         u8         log_max_hairpin_wq_data_sz[0x5];
1299         u8         reserved_at_3d0[0x3];
1300         u8         log_max_hairpin_num_packets[0x5];
1301         u8         reserved_at_3d8[0x3];
1302         u8         log_max_wq_sz[0x5];
1303
1304         u8         nic_vport_change_event[0x1];
1305         u8         disable_local_lb_uc[0x1];
1306         u8         disable_local_lb_mc[0x1];
1307         u8         log_min_hairpin_wq_data_sz[0x5];
1308         u8         reserved_at_3e8[0x3];
1309         u8         log_max_vlan_list[0x5];
1310         u8         reserved_at_3f0[0x3];
1311         u8         log_max_current_mc_list[0x5];
1312         u8         reserved_at_3f8[0x3];
1313         u8         log_max_current_uc_list[0x5];
1314
1315         u8         general_obj_types[0x40];
1316
1317         u8         reserved_at_440[0x20];
1318
1319         u8         tls[0x1];
1320         u8         reserved_at_461[0x2];
1321         u8         log_max_uctx[0x5];
1322         u8         reserved_at_468[0x3];
1323         u8         log_max_umem[0x5];
1324         u8         max_num_eqs[0x10];
1325
1326         u8         reserved_at_480[0x3];
1327         u8         log_max_l2_table[0x5];
1328         u8         reserved_at_488[0x8];
1329         u8         log_uar_page_sz[0x10];
1330
1331         u8         reserved_at_4a0[0x20];
1332         u8         device_frequency_mhz[0x20];
1333         u8         device_frequency_khz[0x20];
1334
1335         u8         reserved_at_500[0x20];
1336         u8         num_of_uars_per_page[0x20];
1337
1338         u8         flex_parser_protocols[0x20];
1339
1340         u8         max_geneve_tlv_options[0x8];
1341         u8         reserved_at_568[0x3];
1342         u8         max_geneve_tlv_option_data_len[0x5];
1343         u8         reserved_at_570[0x10];
1344
1345         u8         reserved_at_580[0x33];
1346         u8         log_max_dek[0x5];
1347         u8         reserved_at_5b8[0x4];
1348         u8         mini_cqe_resp_stride_index[0x1];
1349         u8         cqe_128_always[0x1];
1350         u8         cqe_compression_128[0x1];
1351         u8         cqe_compression[0x1];
1352
1353         u8         cqe_compression_timeout[0x10];
1354         u8         cqe_compression_max_num[0x10];
1355
1356         u8         reserved_at_5e0[0x10];
1357         u8         tag_matching[0x1];
1358         u8         rndv_offload_rc[0x1];
1359         u8         rndv_offload_dc[0x1];
1360         u8         log_tag_matching_list_sz[0x5];
1361         u8         reserved_at_5f8[0x3];
1362         u8         log_max_xrq[0x5];
1363
1364         u8         affiliate_nic_vport_criteria[0x8];
1365         u8         native_port_num[0x8];
1366         u8         num_vhca_ports[0x8];
1367         u8         reserved_at_618[0x6];
1368         u8         sw_owner_id[0x1];
1369         u8         reserved_at_61f[0x1];
1370
1371         u8         max_num_of_monitor_counters[0x10];
1372         u8         num_ppcnt_monitor_counters[0x10];
1373
1374         u8         reserved_at_640[0x10];
1375         u8         num_q_monitor_counters[0x10];
1376
1377         u8         reserved_at_660[0x20];
1378
1379         u8         sf[0x1];
1380         u8         sf_set_partition[0x1];
1381         u8         reserved_at_682[0x1];
1382         u8         log_max_sf[0x5];
1383         u8         reserved_at_688[0x8];
1384         u8         log_min_sf_size[0x8];
1385         u8         max_num_sf_partitions[0x8];
1386
1387         u8         uctx_cap[0x20];
1388
1389         u8         reserved_at_6c0[0x4];
1390         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1391         u8         reserved_at_6c8[0x28];
1392         u8         sf_base_id[0x10];
1393
1394         u8         reserved_at_700[0x80];
1395         u8         vhca_tunnel_commands[0x40];
1396         u8         reserved_at_7c0[0x40];
1397 };
1398
1399 enum mlx5_flow_destination_type {
1400         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1401         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1402         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1403
1404         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1405         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1406         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1407 };
1408
1409 enum mlx5_flow_table_miss_action {
1410         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1411         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1412         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1413 };
1414
1415 struct mlx5_ifc_dest_format_struct_bits {
1416         u8         destination_type[0x8];
1417         u8         destination_id[0x18];
1418
1419         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1420         u8         packet_reformat[0x1];
1421         u8         reserved_at_22[0xe];
1422         u8         destination_eswitch_owner_vhca_id[0x10];
1423 };
1424
1425 struct mlx5_ifc_flow_counter_list_bits {
1426         u8         flow_counter_id[0x20];
1427
1428         u8         reserved_at_20[0x20];
1429 };
1430
1431 struct mlx5_ifc_extended_dest_format_bits {
1432         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1433
1434         u8         packet_reformat_id[0x20];
1435
1436         u8         reserved_at_60[0x20];
1437 };
1438
1439 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1440         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1441         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1442         u8         reserved_at_0[0x40];
1443 };
1444
1445 struct mlx5_ifc_fte_match_param_bits {
1446         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1447
1448         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1449
1450         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1451
1452         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1453
1454         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1455
1456         u8         reserved_at_a00[0x600];
1457 };
1458
1459 enum {
1460         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1461         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1462         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1463         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1464         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1465 };
1466
1467 struct mlx5_ifc_rx_hash_field_select_bits {
1468         u8         l3_prot_type[0x1];
1469         u8         l4_prot_type[0x1];
1470         u8         selected_fields[0x1e];
1471 };
1472
1473 enum {
1474         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1475         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1476 };
1477
1478 enum {
1479         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1480         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1481 };
1482
1483 struct mlx5_ifc_wq_bits {
1484         u8         wq_type[0x4];
1485         u8         wq_signature[0x1];
1486         u8         end_padding_mode[0x2];
1487         u8         cd_slave[0x1];
1488         u8         reserved_at_8[0x18];
1489
1490         u8         hds_skip_first_sge[0x1];
1491         u8         log2_hds_buf_size[0x3];
1492         u8         reserved_at_24[0x7];
1493         u8         page_offset[0x5];
1494         u8         lwm[0x10];
1495
1496         u8         reserved_at_40[0x8];
1497         u8         pd[0x18];
1498
1499         u8         reserved_at_60[0x8];
1500         u8         uar_page[0x18];
1501
1502         u8         dbr_addr[0x40];
1503
1504         u8         hw_counter[0x20];
1505
1506         u8         sw_counter[0x20];
1507
1508         u8         reserved_at_100[0xc];
1509         u8         log_wq_stride[0x4];
1510         u8         reserved_at_110[0x3];
1511         u8         log_wq_pg_sz[0x5];
1512         u8         reserved_at_118[0x3];
1513         u8         log_wq_sz[0x5];
1514
1515         u8         dbr_umem_valid[0x1];
1516         u8         wq_umem_valid[0x1];
1517         u8         reserved_at_122[0x1];
1518         u8         log_hairpin_num_packets[0x5];
1519         u8         reserved_at_128[0x3];
1520         u8         log_hairpin_data_sz[0x5];
1521
1522         u8         reserved_at_130[0x4];
1523         u8         log_wqe_num_of_strides[0x4];
1524         u8         two_byte_shift_en[0x1];
1525         u8         reserved_at_139[0x4];
1526         u8         log_wqe_stride_size[0x3];
1527
1528         u8         reserved_at_140[0x4c0];
1529
1530         struct mlx5_ifc_cmd_pas_bits pas[0];
1531 };
1532
1533 struct mlx5_ifc_rq_num_bits {
1534         u8         reserved_at_0[0x8];
1535         u8         rq_num[0x18];
1536 };
1537
1538 struct mlx5_ifc_mac_address_layout_bits {
1539         u8         reserved_at_0[0x10];
1540         u8         mac_addr_47_32[0x10];
1541
1542         u8         mac_addr_31_0[0x20];
1543 };
1544
1545 struct mlx5_ifc_vlan_layout_bits {
1546         u8         reserved_at_0[0x14];
1547         u8         vlan[0x0c];
1548
1549         u8         reserved_at_20[0x20];
1550 };
1551
1552 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1553         u8         reserved_at_0[0xa0];
1554
1555         u8         min_time_between_cnps[0x20];
1556
1557         u8         reserved_at_c0[0x12];
1558         u8         cnp_dscp[0x6];
1559         u8         reserved_at_d8[0x4];
1560         u8         cnp_prio_mode[0x1];
1561         u8         cnp_802p_prio[0x3];
1562
1563         u8         reserved_at_e0[0x720];
1564 };
1565
1566 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1567         u8         reserved_at_0[0x60];
1568
1569         u8         reserved_at_60[0x4];
1570         u8         clamp_tgt_rate[0x1];
1571         u8         reserved_at_65[0x3];
1572         u8         clamp_tgt_rate_after_time_inc[0x1];
1573         u8         reserved_at_69[0x17];
1574
1575         u8         reserved_at_80[0x20];
1576
1577         u8         rpg_time_reset[0x20];
1578
1579         u8         rpg_byte_reset[0x20];
1580
1581         u8         rpg_threshold[0x20];
1582
1583         u8         rpg_max_rate[0x20];
1584
1585         u8         rpg_ai_rate[0x20];
1586
1587         u8         rpg_hai_rate[0x20];
1588
1589         u8         rpg_gd[0x20];
1590
1591         u8         rpg_min_dec_fac[0x20];
1592
1593         u8         rpg_min_rate[0x20];
1594
1595         u8         reserved_at_1c0[0xe0];
1596
1597         u8         rate_to_set_on_first_cnp[0x20];
1598
1599         u8         dce_tcp_g[0x20];
1600
1601         u8         dce_tcp_rtt[0x20];
1602
1603         u8         rate_reduce_monitor_period[0x20];
1604
1605         u8         reserved_at_320[0x20];
1606
1607         u8         initial_alpha_value[0x20];
1608
1609         u8         reserved_at_360[0x4a0];
1610 };
1611
1612 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1613         u8         reserved_at_0[0x80];
1614
1615         u8         rppp_max_rps[0x20];
1616
1617         u8         rpg_time_reset[0x20];
1618
1619         u8         rpg_byte_reset[0x20];
1620
1621         u8         rpg_threshold[0x20];
1622
1623         u8         rpg_max_rate[0x20];
1624
1625         u8         rpg_ai_rate[0x20];
1626
1627         u8         rpg_hai_rate[0x20];
1628
1629         u8         rpg_gd[0x20];
1630
1631         u8         rpg_min_dec_fac[0x20];
1632
1633         u8         rpg_min_rate[0x20];
1634
1635         u8         reserved_at_1c0[0x640];
1636 };
1637
1638 enum {
1639         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1640         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1641         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1642 };
1643
1644 struct mlx5_ifc_resize_field_select_bits {
1645         u8         resize_field_select[0x20];
1646 };
1647
1648 enum {
1649         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1650         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1651         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1652         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1653 };
1654
1655 struct mlx5_ifc_modify_field_select_bits {
1656         u8         modify_field_select[0x20];
1657 };
1658
1659 struct mlx5_ifc_field_select_r_roce_np_bits {
1660         u8         field_select_r_roce_np[0x20];
1661 };
1662
1663 struct mlx5_ifc_field_select_r_roce_rp_bits {
1664         u8         field_select_r_roce_rp[0x20];
1665 };
1666
1667 enum {
1668         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1669         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1670         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1671         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1672         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1673         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1674         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1675         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1676         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1677         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1678 };
1679
1680 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1681         u8         field_select_8021qaurp[0x20];
1682 };
1683
1684 struct mlx5_ifc_phys_layer_cntrs_bits {
1685         u8         time_since_last_clear_high[0x20];
1686
1687         u8         time_since_last_clear_low[0x20];
1688
1689         u8         symbol_errors_high[0x20];
1690
1691         u8         symbol_errors_low[0x20];
1692
1693         u8         sync_headers_errors_high[0x20];
1694
1695         u8         sync_headers_errors_low[0x20];
1696
1697         u8         edpl_bip_errors_lane0_high[0x20];
1698
1699         u8         edpl_bip_errors_lane0_low[0x20];
1700
1701         u8         edpl_bip_errors_lane1_high[0x20];
1702
1703         u8         edpl_bip_errors_lane1_low[0x20];
1704
1705         u8         edpl_bip_errors_lane2_high[0x20];
1706
1707         u8         edpl_bip_errors_lane2_low[0x20];
1708
1709         u8         edpl_bip_errors_lane3_high[0x20];
1710
1711         u8         edpl_bip_errors_lane3_low[0x20];
1712
1713         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1714
1715         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1716
1717         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1718
1719         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1720
1721         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1722
1723         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1724
1725         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1726
1727         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1728
1729         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1730
1731         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1732
1733         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1734
1735         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1736
1737         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1738
1739         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1740
1741         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1742
1743         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1744
1745         u8         rs_fec_corrected_blocks_high[0x20];
1746
1747         u8         rs_fec_corrected_blocks_low[0x20];
1748
1749         u8         rs_fec_uncorrectable_blocks_high[0x20];
1750
1751         u8         rs_fec_uncorrectable_blocks_low[0x20];
1752
1753         u8         rs_fec_no_errors_blocks_high[0x20];
1754
1755         u8         rs_fec_no_errors_blocks_low[0x20];
1756
1757         u8         rs_fec_single_error_blocks_high[0x20];
1758
1759         u8         rs_fec_single_error_blocks_low[0x20];
1760
1761         u8         rs_fec_corrected_symbols_total_high[0x20];
1762
1763         u8         rs_fec_corrected_symbols_total_low[0x20];
1764
1765         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1766
1767         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1768
1769         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1770
1771         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1772
1773         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1774
1775         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1776
1777         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1778
1779         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1780
1781         u8         link_down_events[0x20];
1782
1783         u8         successful_recovery_events[0x20];
1784
1785         u8         reserved_at_640[0x180];
1786 };
1787
1788 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1789         u8         time_since_last_clear_high[0x20];
1790
1791         u8         time_since_last_clear_low[0x20];
1792
1793         u8         phy_received_bits_high[0x20];
1794
1795         u8         phy_received_bits_low[0x20];
1796
1797         u8         phy_symbol_errors_high[0x20];
1798
1799         u8         phy_symbol_errors_low[0x20];
1800
1801         u8         phy_corrected_bits_high[0x20];
1802
1803         u8         phy_corrected_bits_low[0x20];
1804
1805         u8         phy_corrected_bits_lane0_high[0x20];
1806
1807         u8         phy_corrected_bits_lane0_low[0x20];
1808
1809         u8         phy_corrected_bits_lane1_high[0x20];
1810
1811         u8         phy_corrected_bits_lane1_low[0x20];
1812
1813         u8         phy_corrected_bits_lane2_high[0x20];
1814
1815         u8         phy_corrected_bits_lane2_low[0x20];
1816
1817         u8         phy_corrected_bits_lane3_high[0x20];
1818
1819         u8         phy_corrected_bits_lane3_low[0x20];
1820
1821         u8         reserved_at_200[0x5c0];
1822 };
1823
1824 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1825         u8         symbol_error_counter[0x10];
1826
1827         u8         link_error_recovery_counter[0x8];
1828
1829         u8         link_downed_counter[0x8];
1830
1831         u8         port_rcv_errors[0x10];
1832
1833         u8         port_rcv_remote_physical_errors[0x10];
1834
1835         u8         port_rcv_switch_relay_errors[0x10];
1836
1837         u8         port_xmit_discards[0x10];
1838
1839         u8         port_xmit_constraint_errors[0x8];
1840
1841         u8         port_rcv_constraint_errors[0x8];
1842
1843         u8         reserved_at_70[0x8];
1844
1845         u8         link_overrun_errors[0x8];
1846
1847         u8         reserved_at_80[0x10];
1848
1849         u8         vl_15_dropped[0x10];
1850
1851         u8         reserved_at_a0[0x80];
1852
1853         u8         port_xmit_wait[0x20];
1854 };
1855
1856 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1857         u8         transmit_queue_high[0x20];
1858
1859         u8         transmit_queue_low[0x20];
1860
1861         u8         reserved_at_40[0x780];
1862 };
1863
1864 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1865         u8         rx_octets_high[0x20];
1866
1867         u8         rx_octets_low[0x20];
1868
1869         u8         reserved_at_40[0xc0];
1870
1871         u8         rx_frames_high[0x20];
1872
1873         u8         rx_frames_low[0x20];
1874
1875         u8         tx_octets_high[0x20];
1876
1877         u8         tx_octets_low[0x20];
1878
1879         u8         reserved_at_180[0xc0];
1880
1881         u8         tx_frames_high[0x20];
1882
1883         u8         tx_frames_low[0x20];
1884
1885         u8         rx_pause_high[0x20];
1886
1887         u8         rx_pause_low[0x20];
1888
1889         u8         rx_pause_duration_high[0x20];
1890
1891         u8         rx_pause_duration_low[0x20];
1892
1893         u8         tx_pause_high[0x20];
1894
1895         u8         tx_pause_low[0x20];
1896
1897         u8         tx_pause_duration_high[0x20];
1898
1899         u8         tx_pause_duration_low[0x20];
1900
1901         u8         rx_pause_transition_high[0x20];
1902
1903         u8         rx_pause_transition_low[0x20];
1904
1905         u8         reserved_at_3c0[0x40];
1906
1907         u8         device_stall_minor_watermark_cnt_high[0x20];
1908
1909         u8         device_stall_minor_watermark_cnt_low[0x20];
1910
1911         u8         device_stall_critical_watermark_cnt_high[0x20];
1912
1913         u8         device_stall_critical_watermark_cnt_low[0x20];
1914
1915         u8         reserved_at_480[0x340];
1916 };
1917
1918 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1919         u8         port_transmit_wait_high[0x20];
1920
1921         u8         port_transmit_wait_low[0x20];
1922
1923         u8         reserved_at_40[0x100];
1924
1925         u8         rx_buffer_almost_full_high[0x20];
1926
1927         u8         rx_buffer_almost_full_low[0x20];
1928
1929         u8         rx_buffer_full_high[0x20];
1930
1931         u8         rx_buffer_full_low[0x20];
1932
1933         u8         rx_icrc_encapsulated_high[0x20];
1934
1935         u8         rx_icrc_encapsulated_low[0x20];
1936
1937         u8         reserved_at_200[0x5c0];
1938 };
1939
1940 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1941         u8         dot3stats_alignment_errors_high[0x20];
1942
1943         u8         dot3stats_alignment_errors_low[0x20];
1944
1945         u8         dot3stats_fcs_errors_high[0x20];
1946
1947         u8         dot3stats_fcs_errors_low[0x20];
1948
1949         u8         dot3stats_single_collision_frames_high[0x20];
1950
1951         u8         dot3stats_single_collision_frames_low[0x20];
1952
1953         u8         dot3stats_multiple_collision_frames_high[0x20];
1954
1955         u8         dot3stats_multiple_collision_frames_low[0x20];
1956
1957         u8         dot3stats_sqe_test_errors_high[0x20];
1958
1959         u8         dot3stats_sqe_test_errors_low[0x20];
1960
1961         u8         dot3stats_deferred_transmissions_high[0x20];
1962
1963         u8         dot3stats_deferred_transmissions_low[0x20];
1964
1965         u8         dot3stats_late_collisions_high[0x20];
1966
1967         u8         dot3stats_late_collisions_low[0x20];
1968
1969         u8         dot3stats_excessive_collisions_high[0x20];
1970
1971         u8         dot3stats_excessive_collisions_low[0x20];
1972
1973         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1974
1975         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1976
1977         u8         dot3stats_carrier_sense_errors_high[0x20];
1978
1979         u8         dot3stats_carrier_sense_errors_low[0x20];
1980
1981         u8         dot3stats_frame_too_longs_high[0x20];
1982
1983         u8         dot3stats_frame_too_longs_low[0x20];
1984
1985         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1986
1987         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1988
1989         u8         dot3stats_symbol_errors_high[0x20];
1990
1991         u8         dot3stats_symbol_errors_low[0x20];
1992
1993         u8         dot3control_in_unknown_opcodes_high[0x20];
1994
1995         u8         dot3control_in_unknown_opcodes_low[0x20];
1996
1997         u8         dot3in_pause_frames_high[0x20];
1998
1999         u8         dot3in_pause_frames_low[0x20];
2000
2001         u8         dot3out_pause_frames_high[0x20];
2002
2003         u8         dot3out_pause_frames_low[0x20];
2004
2005         u8         reserved_at_400[0x3c0];
2006 };
2007
2008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2009         u8         ether_stats_drop_events_high[0x20];
2010
2011         u8         ether_stats_drop_events_low[0x20];
2012
2013         u8         ether_stats_octets_high[0x20];
2014
2015         u8         ether_stats_octets_low[0x20];
2016
2017         u8         ether_stats_pkts_high[0x20];
2018
2019         u8         ether_stats_pkts_low[0x20];
2020
2021         u8         ether_stats_broadcast_pkts_high[0x20];
2022
2023         u8         ether_stats_broadcast_pkts_low[0x20];
2024
2025         u8         ether_stats_multicast_pkts_high[0x20];
2026
2027         u8         ether_stats_multicast_pkts_low[0x20];
2028
2029         u8         ether_stats_crc_align_errors_high[0x20];
2030
2031         u8         ether_stats_crc_align_errors_low[0x20];
2032
2033         u8         ether_stats_undersize_pkts_high[0x20];
2034
2035         u8         ether_stats_undersize_pkts_low[0x20];
2036
2037         u8         ether_stats_oversize_pkts_high[0x20];
2038
2039         u8         ether_stats_oversize_pkts_low[0x20];
2040
2041         u8         ether_stats_fragments_high[0x20];
2042
2043         u8         ether_stats_fragments_low[0x20];
2044
2045         u8         ether_stats_jabbers_high[0x20];
2046
2047         u8         ether_stats_jabbers_low[0x20];
2048
2049         u8         ether_stats_collisions_high[0x20];
2050
2051         u8         ether_stats_collisions_low[0x20];
2052
2053         u8         ether_stats_pkts64octets_high[0x20];
2054
2055         u8         ether_stats_pkts64octets_low[0x20];
2056
2057         u8         ether_stats_pkts65to127octets_high[0x20];
2058
2059         u8         ether_stats_pkts65to127octets_low[0x20];
2060
2061         u8         ether_stats_pkts128to255octets_high[0x20];
2062
2063         u8         ether_stats_pkts128to255octets_low[0x20];
2064
2065         u8         ether_stats_pkts256to511octets_high[0x20];
2066
2067         u8         ether_stats_pkts256to511octets_low[0x20];
2068
2069         u8         ether_stats_pkts512to1023octets_high[0x20];
2070
2071         u8         ether_stats_pkts512to1023octets_low[0x20];
2072
2073         u8         ether_stats_pkts1024to1518octets_high[0x20];
2074
2075         u8         ether_stats_pkts1024to1518octets_low[0x20];
2076
2077         u8         ether_stats_pkts1519to2047octets_high[0x20];
2078
2079         u8         ether_stats_pkts1519to2047octets_low[0x20];
2080
2081         u8         ether_stats_pkts2048to4095octets_high[0x20];
2082
2083         u8         ether_stats_pkts2048to4095octets_low[0x20];
2084
2085         u8         ether_stats_pkts4096to8191octets_high[0x20];
2086
2087         u8         ether_stats_pkts4096to8191octets_low[0x20];
2088
2089         u8         ether_stats_pkts8192to10239octets_high[0x20];
2090
2091         u8         ether_stats_pkts8192to10239octets_low[0x20];
2092
2093         u8         reserved_at_540[0x280];
2094 };
2095
2096 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2097         u8         if_in_octets_high[0x20];
2098
2099         u8         if_in_octets_low[0x20];
2100
2101         u8         if_in_ucast_pkts_high[0x20];
2102
2103         u8         if_in_ucast_pkts_low[0x20];
2104
2105         u8         if_in_discards_high[0x20];
2106
2107         u8         if_in_discards_low[0x20];
2108
2109         u8         if_in_errors_high[0x20];
2110
2111         u8         if_in_errors_low[0x20];
2112
2113         u8         if_in_unknown_protos_high[0x20];
2114
2115         u8         if_in_unknown_protos_low[0x20];
2116
2117         u8         if_out_octets_high[0x20];
2118
2119         u8         if_out_octets_low[0x20];
2120
2121         u8         if_out_ucast_pkts_high[0x20];
2122
2123         u8         if_out_ucast_pkts_low[0x20];
2124
2125         u8         if_out_discards_high[0x20];
2126
2127         u8         if_out_discards_low[0x20];
2128
2129         u8         if_out_errors_high[0x20];
2130
2131         u8         if_out_errors_low[0x20];
2132
2133         u8         if_in_multicast_pkts_high[0x20];
2134
2135         u8         if_in_multicast_pkts_low[0x20];
2136
2137         u8         if_in_broadcast_pkts_high[0x20];
2138
2139         u8         if_in_broadcast_pkts_low[0x20];
2140
2141         u8         if_out_multicast_pkts_high[0x20];
2142
2143         u8         if_out_multicast_pkts_low[0x20];
2144
2145         u8         if_out_broadcast_pkts_high[0x20];
2146
2147         u8         if_out_broadcast_pkts_low[0x20];
2148
2149         u8         reserved_at_340[0x480];
2150 };
2151
2152 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2153         u8         a_frames_transmitted_ok_high[0x20];
2154
2155         u8         a_frames_transmitted_ok_low[0x20];
2156
2157         u8         a_frames_received_ok_high[0x20];
2158
2159         u8         a_frames_received_ok_low[0x20];
2160
2161         u8         a_frame_check_sequence_errors_high[0x20];
2162
2163         u8         a_frame_check_sequence_errors_low[0x20];
2164
2165         u8         a_alignment_errors_high[0x20];
2166
2167         u8         a_alignment_errors_low[0x20];
2168
2169         u8         a_octets_transmitted_ok_high[0x20];
2170
2171         u8         a_octets_transmitted_ok_low[0x20];
2172
2173         u8         a_octets_received_ok_high[0x20];
2174
2175         u8         a_octets_received_ok_low[0x20];
2176
2177         u8         a_multicast_frames_xmitted_ok_high[0x20];
2178
2179         u8         a_multicast_frames_xmitted_ok_low[0x20];
2180
2181         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2182
2183         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2184
2185         u8         a_multicast_frames_received_ok_high[0x20];
2186
2187         u8         a_multicast_frames_received_ok_low[0x20];
2188
2189         u8         a_broadcast_frames_received_ok_high[0x20];
2190
2191         u8         a_broadcast_frames_received_ok_low[0x20];
2192
2193         u8         a_in_range_length_errors_high[0x20];
2194
2195         u8         a_in_range_length_errors_low[0x20];
2196
2197         u8         a_out_of_range_length_field_high[0x20];
2198
2199         u8         a_out_of_range_length_field_low[0x20];
2200
2201         u8         a_frame_too_long_errors_high[0x20];
2202
2203         u8         a_frame_too_long_errors_low[0x20];
2204
2205         u8         a_symbol_error_during_carrier_high[0x20];
2206
2207         u8         a_symbol_error_during_carrier_low[0x20];
2208
2209         u8         a_mac_control_frames_transmitted_high[0x20];
2210
2211         u8         a_mac_control_frames_transmitted_low[0x20];
2212
2213         u8         a_mac_control_frames_received_high[0x20];
2214
2215         u8         a_mac_control_frames_received_low[0x20];
2216
2217         u8         a_unsupported_opcodes_received_high[0x20];
2218
2219         u8         a_unsupported_opcodes_received_low[0x20];
2220
2221         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2222
2223         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2224
2225         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2226
2227         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2228
2229         u8         reserved_at_4c0[0x300];
2230 };
2231
2232 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2233         u8         life_time_counter_high[0x20];
2234
2235         u8         life_time_counter_low[0x20];
2236
2237         u8         rx_errors[0x20];
2238
2239         u8         tx_errors[0x20];
2240
2241         u8         l0_to_recovery_eieos[0x20];
2242
2243         u8         l0_to_recovery_ts[0x20];
2244
2245         u8         l0_to_recovery_framing[0x20];
2246
2247         u8         l0_to_recovery_retrain[0x20];
2248
2249         u8         crc_error_dllp[0x20];
2250
2251         u8         crc_error_tlp[0x20];
2252
2253         u8         tx_overflow_buffer_pkt_high[0x20];
2254
2255         u8         tx_overflow_buffer_pkt_low[0x20];
2256
2257         u8         outbound_stalled_reads[0x20];
2258
2259         u8         outbound_stalled_writes[0x20];
2260
2261         u8         outbound_stalled_reads_events[0x20];
2262
2263         u8         outbound_stalled_writes_events[0x20];
2264
2265         u8         reserved_at_200[0x5c0];
2266 };
2267
2268 struct mlx5_ifc_cmd_inter_comp_event_bits {
2269         u8         command_completion_vector[0x20];
2270
2271         u8         reserved_at_20[0xc0];
2272 };
2273
2274 struct mlx5_ifc_stall_vl_event_bits {
2275         u8         reserved_at_0[0x18];
2276         u8         port_num[0x1];
2277         u8         reserved_at_19[0x3];
2278         u8         vl[0x4];
2279
2280         u8         reserved_at_20[0xa0];
2281 };
2282
2283 struct mlx5_ifc_db_bf_congestion_event_bits {
2284         u8         event_subtype[0x8];
2285         u8         reserved_at_8[0x8];
2286         u8         congestion_level[0x8];
2287         u8         reserved_at_18[0x8];
2288
2289         u8         reserved_at_20[0xa0];
2290 };
2291
2292 struct mlx5_ifc_gpio_event_bits {
2293         u8         reserved_at_0[0x60];
2294
2295         u8         gpio_event_hi[0x20];
2296
2297         u8         gpio_event_lo[0x20];
2298
2299         u8         reserved_at_a0[0x40];
2300 };
2301
2302 struct mlx5_ifc_port_state_change_event_bits {
2303         u8         reserved_at_0[0x40];
2304
2305         u8         port_num[0x4];
2306         u8         reserved_at_44[0x1c];
2307
2308         u8         reserved_at_60[0x80];
2309 };
2310
2311 struct mlx5_ifc_dropped_packet_logged_bits {
2312         u8         reserved_at_0[0xe0];
2313 };
2314
2315 enum {
2316         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2317         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2318 };
2319
2320 struct mlx5_ifc_cq_error_bits {
2321         u8         reserved_at_0[0x8];
2322         u8         cqn[0x18];
2323
2324         u8         reserved_at_20[0x20];
2325
2326         u8         reserved_at_40[0x18];
2327         u8         syndrome[0x8];
2328
2329         u8         reserved_at_60[0x80];
2330 };
2331
2332 struct mlx5_ifc_rdma_page_fault_event_bits {
2333         u8         bytes_committed[0x20];
2334
2335         u8         r_key[0x20];
2336
2337         u8         reserved_at_40[0x10];
2338         u8         packet_len[0x10];
2339
2340         u8         rdma_op_len[0x20];
2341
2342         u8         rdma_va[0x40];
2343
2344         u8         reserved_at_c0[0x5];
2345         u8         rdma[0x1];
2346         u8         write[0x1];
2347         u8         requestor[0x1];
2348         u8         qp_number[0x18];
2349 };
2350
2351 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2352         u8         bytes_committed[0x20];
2353
2354         u8         reserved_at_20[0x10];
2355         u8         wqe_index[0x10];
2356
2357         u8         reserved_at_40[0x10];
2358         u8         len[0x10];
2359
2360         u8         reserved_at_60[0x60];
2361
2362         u8         reserved_at_c0[0x5];
2363         u8         rdma[0x1];
2364         u8         write_read[0x1];
2365         u8         requestor[0x1];
2366         u8         qpn[0x18];
2367 };
2368
2369 struct mlx5_ifc_qp_events_bits {
2370         u8         reserved_at_0[0xa0];
2371
2372         u8         type[0x8];
2373         u8         reserved_at_a8[0x18];
2374
2375         u8         reserved_at_c0[0x8];
2376         u8         qpn_rqn_sqn[0x18];
2377 };
2378
2379 struct mlx5_ifc_dct_events_bits {
2380         u8         reserved_at_0[0xc0];
2381
2382         u8         reserved_at_c0[0x8];
2383         u8         dct_number[0x18];
2384 };
2385
2386 struct mlx5_ifc_comp_event_bits {
2387         u8         reserved_at_0[0xc0];
2388
2389         u8         reserved_at_c0[0x8];
2390         u8         cq_number[0x18];
2391 };
2392
2393 enum {
2394         MLX5_QPC_STATE_RST        = 0x0,
2395         MLX5_QPC_STATE_INIT       = 0x1,
2396         MLX5_QPC_STATE_RTR        = 0x2,
2397         MLX5_QPC_STATE_RTS        = 0x3,
2398         MLX5_QPC_STATE_SQER       = 0x4,
2399         MLX5_QPC_STATE_ERR        = 0x6,
2400         MLX5_QPC_STATE_SQD        = 0x7,
2401         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2402 };
2403
2404 enum {
2405         MLX5_QPC_ST_RC            = 0x0,
2406         MLX5_QPC_ST_UC            = 0x1,
2407         MLX5_QPC_ST_UD            = 0x2,
2408         MLX5_QPC_ST_XRC           = 0x3,
2409         MLX5_QPC_ST_DCI           = 0x5,
2410         MLX5_QPC_ST_QP0           = 0x7,
2411         MLX5_QPC_ST_QP1           = 0x8,
2412         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2413         MLX5_QPC_ST_REG_UMR       = 0xc,
2414 };
2415
2416 enum {
2417         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2418         MLX5_QPC_PM_STATE_REARM     = 0x1,
2419         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2420         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2421 };
2422
2423 enum {
2424         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2425 };
2426
2427 enum {
2428         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2429         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2430 };
2431
2432 enum {
2433         MLX5_QPC_MTU_256_BYTES        = 0x1,
2434         MLX5_QPC_MTU_512_BYTES        = 0x2,
2435         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2436         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2437         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2438         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2439 };
2440
2441 enum {
2442         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2443         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2444         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2445         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2446         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2447         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2448         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2449         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2450 };
2451
2452 enum {
2453         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2454         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2455         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2456 };
2457
2458 enum {
2459         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2460         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2461         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2462 };
2463
2464 struct mlx5_ifc_qpc_bits {
2465         u8         state[0x4];
2466         u8         lag_tx_port_affinity[0x4];
2467         u8         st[0x8];
2468         u8         reserved_at_10[0x3];
2469         u8         pm_state[0x2];
2470         u8         reserved_at_15[0x1];
2471         u8         req_e2e_credit_mode[0x2];
2472         u8         offload_type[0x4];
2473         u8         end_padding_mode[0x2];
2474         u8         reserved_at_1e[0x2];
2475
2476         u8         wq_signature[0x1];
2477         u8         block_lb_mc[0x1];
2478         u8         atomic_like_write_en[0x1];
2479         u8         latency_sensitive[0x1];
2480         u8         reserved_at_24[0x1];
2481         u8         drain_sigerr[0x1];
2482         u8         reserved_at_26[0x2];
2483         u8         pd[0x18];
2484
2485         u8         mtu[0x3];
2486         u8         log_msg_max[0x5];
2487         u8         reserved_at_48[0x1];
2488         u8         log_rq_size[0x4];
2489         u8         log_rq_stride[0x3];
2490         u8         no_sq[0x1];
2491         u8         log_sq_size[0x4];
2492         u8         reserved_at_55[0x6];
2493         u8         rlky[0x1];
2494         u8         ulp_stateless_offload_mode[0x4];
2495
2496         u8         counter_set_id[0x8];
2497         u8         uar_page[0x18];
2498
2499         u8         reserved_at_80[0x8];
2500         u8         user_index[0x18];
2501
2502         u8         reserved_at_a0[0x3];
2503         u8         log_page_size[0x5];
2504         u8         remote_qpn[0x18];
2505
2506         struct mlx5_ifc_ads_bits primary_address_path;
2507
2508         struct mlx5_ifc_ads_bits secondary_address_path;
2509
2510         u8         log_ack_req_freq[0x4];
2511         u8         reserved_at_384[0x4];
2512         u8         log_sra_max[0x3];
2513         u8         reserved_at_38b[0x2];
2514         u8         retry_count[0x3];
2515         u8         rnr_retry[0x3];
2516         u8         reserved_at_393[0x1];
2517         u8         fre[0x1];
2518         u8         cur_rnr_retry[0x3];
2519         u8         cur_retry_count[0x3];
2520         u8         reserved_at_39b[0x5];
2521
2522         u8         reserved_at_3a0[0x20];
2523
2524         u8         reserved_at_3c0[0x8];
2525         u8         next_send_psn[0x18];
2526
2527         u8         reserved_at_3e0[0x8];
2528         u8         cqn_snd[0x18];
2529
2530         u8         reserved_at_400[0x8];
2531         u8         deth_sqpn[0x18];
2532
2533         u8         reserved_at_420[0x20];
2534
2535         u8         reserved_at_440[0x8];
2536         u8         last_acked_psn[0x18];
2537
2538         u8         reserved_at_460[0x8];
2539         u8         ssn[0x18];
2540
2541         u8         reserved_at_480[0x8];
2542         u8         log_rra_max[0x3];
2543         u8         reserved_at_48b[0x1];
2544         u8         atomic_mode[0x4];
2545         u8         rre[0x1];
2546         u8         rwe[0x1];
2547         u8         rae[0x1];
2548         u8         reserved_at_493[0x1];
2549         u8         page_offset[0x6];
2550         u8         reserved_at_49a[0x3];
2551         u8         cd_slave_receive[0x1];
2552         u8         cd_slave_send[0x1];
2553         u8         cd_master[0x1];
2554
2555         u8         reserved_at_4a0[0x3];
2556         u8         min_rnr_nak[0x5];
2557         u8         next_rcv_psn[0x18];
2558
2559         u8         reserved_at_4c0[0x8];
2560         u8         xrcd[0x18];
2561
2562         u8         reserved_at_4e0[0x8];
2563         u8         cqn_rcv[0x18];
2564
2565         u8         dbr_addr[0x40];
2566
2567         u8         q_key[0x20];
2568
2569         u8         reserved_at_560[0x5];
2570         u8         rq_type[0x3];
2571         u8         srqn_rmpn_xrqn[0x18];
2572
2573         u8         reserved_at_580[0x8];
2574         u8         rmsn[0x18];
2575
2576         u8         hw_sq_wqebb_counter[0x10];
2577         u8         sw_sq_wqebb_counter[0x10];
2578
2579         u8         hw_rq_counter[0x20];
2580
2581         u8         sw_rq_counter[0x20];
2582
2583         u8         reserved_at_600[0x20];
2584
2585         u8         reserved_at_620[0xf];
2586         u8         cgs[0x1];
2587         u8         cs_req[0x8];
2588         u8         cs_res[0x8];
2589
2590         u8         dc_access_key[0x40];
2591
2592         u8         reserved_at_680[0x3];
2593         u8         dbr_umem_valid[0x1];
2594
2595         u8         reserved_at_684[0xbc];
2596 };
2597
2598 struct mlx5_ifc_roce_addr_layout_bits {
2599         u8         source_l3_address[16][0x8];
2600
2601         u8         reserved_at_80[0x3];
2602         u8         vlan_valid[0x1];
2603         u8         vlan_id[0xc];
2604         u8         source_mac_47_32[0x10];
2605
2606         u8         source_mac_31_0[0x20];
2607
2608         u8         reserved_at_c0[0x14];
2609         u8         roce_l3_type[0x4];
2610         u8         roce_version[0x8];
2611
2612         u8         reserved_at_e0[0x20];
2613 };
2614
2615 union mlx5_ifc_hca_cap_union_bits {
2616         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2617         struct mlx5_ifc_odp_cap_bits odp_cap;
2618         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2619         struct mlx5_ifc_roce_cap_bits roce_cap;
2620         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2621         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2622         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2623         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2624         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2625         struct mlx5_ifc_qos_cap_bits qos_cap;
2626         struct mlx5_ifc_debug_cap_bits debug_cap;
2627         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2628         struct mlx5_ifc_tls_cap_bits tls_cap;
2629         u8         reserved_at_0[0x8000];
2630 };
2631
2632 enum {
2633         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2634         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2635         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2636         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2637         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2638         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2639         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2640         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2641         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2642         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2643         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2644 };
2645
2646 enum {
2647         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2648         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2649         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2650 };
2651
2652 struct mlx5_ifc_vlan_bits {
2653         u8         ethtype[0x10];
2654         u8         prio[0x3];
2655         u8         cfi[0x1];
2656         u8         vid[0xc];
2657 };
2658
2659 struct mlx5_ifc_flow_context_bits {
2660         struct mlx5_ifc_vlan_bits push_vlan;
2661
2662         u8         group_id[0x20];
2663
2664         u8         reserved_at_40[0x8];
2665         u8         flow_tag[0x18];
2666
2667         u8         reserved_at_60[0x10];
2668         u8         action[0x10];
2669
2670         u8         extended_destination[0x1];
2671         u8         reserved_at_81[0x1];
2672         u8         flow_source[0x2];
2673         u8         reserved_at_84[0x4];
2674         u8         destination_list_size[0x18];
2675
2676         u8         reserved_at_a0[0x8];
2677         u8         flow_counter_list_size[0x18];
2678
2679         u8         packet_reformat_id[0x20];
2680
2681         u8         modify_header_id[0x20];
2682
2683         struct mlx5_ifc_vlan_bits push_vlan_2;
2684
2685         u8         reserved_at_120[0xe0];
2686
2687         struct mlx5_ifc_fte_match_param_bits match_value;
2688
2689         u8         reserved_at_1200[0x600];
2690
2691         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2692 };
2693
2694 enum {
2695         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2696         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2697 };
2698
2699 struct mlx5_ifc_xrc_srqc_bits {
2700         u8         state[0x4];
2701         u8         log_xrc_srq_size[0x4];
2702         u8         reserved_at_8[0x18];
2703
2704         u8         wq_signature[0x1];
2705         u8         cont_srq[0x1];
2706         u8         reserved_at_22[0x1];
2707         u8         rlky[0x1];
2708         u8         basic_cyclic_rcv_wqe[0x1];
2709         u8         log_rq_stride[0x3];
2710         u8         xrcd[0x18];
2711
2712         u8         page_offset[0x6];
2713         u8         reserved_at_46[0x1];
2714         u8         dbr_umem_valid[0x1];
2715         u8         cqn[0x18];
2716
2717         u8         reserved_at_60[0x20];
2718
2719         u8         user_index_equal_xrc_srqn[0x1];
2720         u8         reserved_at_81[0x1];
2721         u8         log_page_size[0x6];
2722         u8         user_index[0x18];
2723
2724         u8         reserved_at_a0[0x20];
2725
2726         u8         reserved_at_c0[0x8];
2727         u8         pd[0x18];
2728
2729         u8         lwm[0x10];
2730         u8         wqe_cnt[0x10];
2731
2732         u8         reserved_at_100[0x40];
2733
2734         u8         db_record_addr_h[0x20];
2735
2736         u8         db_record_addr_l[0x1e];
2737         u8         reserved_at_17e[0x2];
2738
2739         u8         reserved_at_180[0x80];
2740 };
2741
2742 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2743         u8         counter_error_queues[0x20];
2744
2745         u8         total_error_queues[0x20];
2746
2747         u8         send_queue_priority_update_flow[0x20];
2748
2749         u8         reserved_at_60[0x20];
2750
2751         u8         nic_receive_steering_discard[0x40];
2752
2753         u8         receive_discard_vport_down[0x40];
2754
2755         u8         transmit_discard_vport_down[0x40];
2756
2757         u8         reserved_at_140[0xec0];
2758 };
2759
2760 struct mlx5_ifc_traffic_counter_bits {
2761         u8         packets[0x40];
2762
2763         u8         octets[0x40];
2764 };
2765
2766 struct mlx5_ifc_tisc_bits {
2767         u8         strict_lag_tx_port_affinity[0x1];
2768         u8         tls_en[0x1];
2769         u8         reserved_at_1[0x2];
2770         u8         lag_tx_port_affinity[0x04];
2771
2772         u8         reserved_at_8[0x4];
2773         u8         prio[0x4];
2774         u8         reserved_at_10[0x10];
2775
2776         u8         reserved_at_20[0x100];
2777
2778         u8         reserved_at_120[0x8];
2779         u8         transport_domain[0x18];
2780
2781         u8         reserved_at_140[0x8];
2782         u8         underlay_qpn[0x18];
2783
2784         u8         reserved_at_160[0x8];
2785         u8         pd[0x18];
2786
2787         u8         reserved_at_180[0x380];
2788 };
2789
2790 enum {
2791         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2792         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2793 };
2794
2795 enum {
2796         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2797         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2798 };
2799
2800 enum {
2801         MLX5_RX_HASH_FN_NONE           = 0x0,
2802         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2803         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2804 };
2805
2806 enum {
2807         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2808         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2809 };
2810
2811 struct mlx5_ifc_tirc_bits {
2812         u8         reserved_at_0[0x20];
2813
2814         u8         disp_type[0x4];
2815         u8         reserved_at_24[0x1c];
2816
2817         u8         reserved_at_40[0x40];
2818
2819         u8         reserved_at_80[0x4];
2820         u8         lro_timeout_period_usecs[0x10];
2821         u8         lro_enable_mask[0x4];
2822         u8         lro_max_ip_payload_size[0x8];
2823
2824         u8         reserved_at_a0[0x40];
2825
2826         u8         reserved_at_e0[0x8];
2827         u8         inline_rqn[0x18];
2828
2829         u8         rx_hash_symmetric[0x1];
2830         u8         reserved_at_101[0x1];
2831         u8         tunneled_offload_en[0x1];
2832         u8         reserved_at_103[0x5];
2833         u8         indirect_table[0x18];
2834
2835         u8         rx_hash_fn[0x4];
2836         u8         reserved_at_124[0x2];
2837         u8         self_lb_block[0x2];
2838         u8         transport_domain[0x18];
2839
2840         u8         rx_hash_toeplitz_key[10][0x20];
2841
2842         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2843
2844         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2845
2846         u8         reserved_at_2c0[0x4c0];
2847 };
2848
2849 enum {
2850         MLX5_SRQC_STATE_GOOD   = 0x0,
2851         MLX5_SRQC_STATE_ERROR  = 0x1,
2852 };
2853
2854 struct mlx5_ifc_srqc_bits {
2855         u8         state[0x4];
2856         u8         log_srq_size[0x4];
2857         u8         reserved_at_8[0x18];
2858
2859         u8         wq_signature[0x1];
2860         u8         cont_srq[0x1];
2861         u8         reserved_at_22[0x1];
2862         u8         rlky[0x1];
2863         u8         reserved_at_24[0x1];
2864         u8         log_rq_stride[0x3];
2865         u8         xrcd[0x18];
2866
2867         u8         page_offset[0x6];
2868         u8         reserved_at_46[0x2];
2869         u8         cqn[0x18];
2870
2871         u8         reserved_at_60[0x20];
2872
2873         u8         reserved_at_80[0x2];
2874         u8         log_page_size[0x6];
2875         u8         reserved_at_88[0x18];
2876
2877         u8         reserved_at_a0[0x20];
2878
2879         u8         reserved_at_c0[0x8];
2880         u8         pd[0x18];
2881
2882         u8         lwm[0x10];
2883         u8         wqe_cnt[0x10];
2884
2885         u8         reserved_at_100[0x40];
2886
2887         u8         dbr_addr[0x40];
2888
2889         u8         reserved_at_180[0x80];
2890 };
2891
2892 enum {
2893         MLX5_SQC_STATE_RST  = 0x0,
2894         MLX5_SQC_STATE_RDY  = 0x1,
2895         MLX5_SQC_STATE_ERR  = 0x3,
2896 };
2897
2898 struct mlx5_ifc_sqc_bits {
2899         u8         rlky[0x1];
2900         u8         cd_master[0x1];
2901         u8         fre[0x1];
2902         u8         flush_in_error_en[0x1];
2903         u8         allow_multi_pkt_send_wqe[0x1];
2904         u8         min_wqe_inline_mode[0x3];
2905         u8         state[0x4];
2906         u8         reg_umr[0x1];
2907         u8         allow_swp[0x1];
2908         u8         hairpin[0x1];
2909         u8         reserved_at_f[0x11];
2910
2911         u8         reserved_at_20[0x8];
2912         u8         user_index[0x18];
2913
2914         u8         reserved_at_40[0x8];
2915         u8         cqn[0x18];
2916
2917         u8         reserved_at_60[0x8];
2918         u8         hairpin_peer_rq[0x18];
2919
2920         u8         reserved_at_80[0x10];
2921         u8         hairpin_peer_vhca[0x10];
2922
2923         u8         reserved_at_a0[0x50];
2924
2925         u8         packet_pacing_rate_limit_index[0x10];
2926         u8         tis_lst_sz[0x10];
2927         u8         reserved_at_110[0x10];
2928
2929         u8         reserved_at_120[0x40];
2930
2931         u8         reserved_at_160[0x8];
2932         u8         tis_num_0[0x18];
2933
2934         struct mlx5_ifc_wq_bits wq;
2935 };
2936
2937 enum {
2938         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2939         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2940         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2941         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2942 };
2943
2944 struct mlx5_ifc_scheduling_context_bits {
2945         u8         element_type[0x8];
2946         u8         reserved_at_8[0x18];
2947
2948         u8         element_attributes[0x20];
2949
2950         u8         parent_element_id[0x20];
2951
2952         u8         reserved_at_60[0x40];
2953
2954         u8         bw_share[0x20];
2955
2956         u8         max_average_bw[0x20];
2957
2958         u8         reserved_at_e0[0x120];
2959 };
2960
2961 struct mlx5_ifc_rqtc_bits {
2962         u8         reserved_at_0[0xa0];
2963
2964         u8         reserved_at_a0[0x10];
2965         u8         rqt_max_size[0x10];
2966
2967         u8         reserved_at_c0[0x10];
2968         u8         rqt_actual_size[0x10];
2969
2970         u8         reserved_at_e0[0x6a0];
2971
2972         struct mlx5_ifc_rq_num_bits rq_num[0];
2973 };
2974
2975 enum {
2976         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2977         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2978 };
2979
2980 enum {
2981         MLX5_RQC_STATE_RST  = 0x0,
2982         MLX5_RQC_STATE_RDY  = 0x1,
2983         MLX5_RQC_STATE_ERR  = 0x3,
2984 };
2985
2986 struct mlx5_ifc_rqc_bits {
2987         u8         rlky[0x1];
2988         u8         delay_drop_en[0x1];
2989         u8         scatter_fcs[0x1];
2990         u8         vsd[0x1];
2991         u8         mem_rq_type[0x4];
2992         u8         state[0x4];
2993         u8         reserved_at_c[0x1];
2994         u8         flush_in_error_en[0x1];
2995         u8         hairpin[0x1];
2996         u8         reserved_at_f[0x11];
2997
2998         u8         reserved_at_20[0x8];
2999         u8         user_index[0x18];
3000
3001         u8         reserved_at_40[0x8];
3002         u8         cqn[0x18];
3003
3004         u8         counter_set_id[0x8];
3005         u8         reserved_at_68[0x18];
3006
3007         u8         reserved_at_80[0x8];
3008         u8         rmpn[0x18];
3009
3010         u8         reserved_at_a0[0x8];
3011         u8         hairpin_peer_sq[0x18];
3012
3013         u8         reserved_at_c0[0x10];
3014         u8         hairpin_peer_vhca[0x10];
3015
3016         u8         reserved_at_e0[0xa0];
3017
3018         struct mlx5_ifc_wq_bits wq;
3019 };
3020
3021 enum {
3022         MLX5_RMPC_STATE_RDY  = 0x1,
3023         MLX5_RMPC_STATE_ERR  = 0x3,
3024 };
3025
3026 struct mlx5_ifc_rmpc_bits {
3027         u8         reserved_at_0[0x8];
3028         u8         state[0x4];
3029         u8         reserved_at_c[0x14];
3030
3031         u8         basic_cyclic_rcv_wqe[0x1];
3032         u8         reserved_at_21[0x1f];
3033
3034         u8         reserved_at_40[0x140];
3035
3036         struct mlx5_ifc_wq_bits wq;
3037 };
3038
3039 struct mlx5_ifc_nic_vport_context_bits {
3040         u8         reserved_at_0[0x5];
3041         u8         min_wqe_inline_mode[0x3];
3042         u8         reserved_at_8[0x15];
3043         u8         disable_mc_local_lb[0x1];
3044         u8         disable_uc_local_lb[0x1];
3045         u8         roce_en[0x1];
3046
3047         u8         arm_change_event[0x1];
3048         u8         reserved_at_21[0x1a];
3049         u8         event_on_mtu[0x1];
3050         u8         event_on_promisc_change[0x1];
3051         u8         event_on_vlan_change[0x1];
3052         u8         event_on_mc_address_change[0x1];
3053         u8         event_on_uc_address_change[0x1];
3054
3055         u8         reserved_at_40[0xc];
3056
3057         u8         affiliation_criteria[0x4];
3058         u8         affiliated_vhca_id[0x10];
3059
3060         u8         reserved_at_60[0xd0];
3061
3062         u8         mtu[0x10];
3063
3064         u8         system_image_guid[0x40];
3065         u8         port_guid[0x40];
3066         u8         node_guid[0x40];
3067
3068         u8         reserved_at_200[0x140];
3069         u8         qkey_violation_counter[0x10];
3070         u8         reserved_at_350[0x430];
3071
3072         u8         promisc_uc[0x1];
3073         u8         promisc_mc[0x1];
3074         u8         promisc_all[0x1];
3075         u8         reserved_at_783[0x2];
3076         u8         allowed_list_type[0x3];
3077         u8         reserved_at_788[0xc];
3078         u8         allowed_list_size[0xc];
3079
3080         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3081
3082         u8         reserved_at_7e0[0x20];
3083
3084         u8         current_uc_mac_address[0][0x40];
3085 };
3086
3087 enum {
3088         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3089         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3090         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3091         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3092         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3093         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3094 };
3095
3096 struct mlx5_ifc_mkc_bits {
3097         u8         reserved_at_0[0x1];
3098         u8         free[0x1];
3099         u8         reserved_at_2[0x1];
3100         u8         access_mode_4_2[0x3];
3101         u8         reserved_at_6[0x7];
3102         u8         relaxed_ordering_write[0x1];
3103         u8         reserved_at_e[0x1];
3104         u8         small_fence_on_rdma_read_response[0x1];
3105         u8         umr_en[0x1];
3106         u8         a[0x1];
3107         u8         rw[0x1];
3108         u8         rr[0x1];
3109         u8         lw[0x1];
3110         u8         lr[0x1];
3111         u8         access_mode_1_0[0x2];
3112         u8         reserved_at_18[0x8];
3113
3114         u8         qpn[0x18];
3115         u8         mkey_7_0[0x8];
3116
3117         u8         reserved_at_40[0x20];
3118
3119         u8         length64[0x1];
3120         u8         bsf_en[0x1];
3121         u8         sync_umr[0x1];
3122         u8         reserved_at_63[0x2];
3123         u8         expected_sigerr_count[0x1];
3124         u8         reserved_at_66[0x1];
3125         u8         en_rinval[0x1];
3126         u8         pd[0x18];
3127
3128         u8         start_addr[0x40];
3129
3130         u8         len[0x40];
3131
3132         u8         bsf_octword_size[0x20];
3133
3134         u8         reserved_at_120[0x80];
3135
3136         u8         translations_octword_size[0x20];
3137
3138         u8         reserved_at_1c0[0x1b];
3139         u8         log_page_size[0x5];
3140
3141         u8         reserved_at_1e0[0x20];
3142 };
3143
3144 struct mlx5_ifc_pkey_bits {
3145         u8         reserved_at_0[0x10];
3146         u8         pkey[0x10];
3147 };
3148
3149 struct mlx5_ifc_array128_auto_bits {
3150         u8         array128_auto[16][0x8];
3151 };
3152
3153 struct mlx5_ifc_hca_vport_context_bits {
3154         u8         field_select[0x20];
3155
3156         u8         reserved_at_20[0xe0];
3157
3158         u8         sm_virt_aware[0x1];
3159         u8         has_smi[0x1];
3160         u8         has_raw[0x1];
3161         u8         grh_required[0x1];
3162         u8         reserved_at_104[0xc];
3163         u8         port_physical_state[0x4];
3164         u8         vport_state_policy[0x4];
3165         u8         port_state[0x4];
3166         u8         vport_state[0x4];
3167
3168         u8         reserved_at_120[0x20];
3169
3170         u8         system_image_guid[0x40];
3171
3172         u8         port_guid[0x40];
3173
3174         u8         node_guid[0x40];
3175
3176         u8         cap_mask1[0x20];
3177
3178         u8         cap_mask1_field_select[0x20];
3179
3180         u8         cap_mask2[0x20];
3181
3182         u8         cap_mask2_field_select[0x20];
3183
3184         u8         reserved_at_280[0x80];
3185
3186         u8         lid[0x10];
3187         u8         reserved_at_310[0x4];
3188         u8         init_type_reply[0x4];
3189         u8         lmc[0x3];
3190         u8         subnet_timeout[0x5];
3191
3192         u8         sm_lid[0x10];
3193         u8         sm_sl[0x4];
3194         u8         reserved_at_334[0xc];
3195
3196         u8         qkey_violation_counter[0x10];
3197         u8         pkey_violation_counter[0x10];
3198
3199         u8         reserved_at_360[0xca0];
3200 };
3201
3202 struct mlx5_ifc_esw_vport_context_bits {
3203         u8         fdb_to_vport_reg_c[0x1];
3204         u8         reserved_at_1[0x2];
3205         u8         vport_svlan_strip[0x1];
3206         u8         vport_cvlan_strip[0x1];
3207         u8         vport_svlan_insert[0x1];
3208         u8         vport_cvlan_insert[0x2];
3209         u8         fdb_to_vport_reg_c_id[0x8];
3210         u8         reserved_at_10[0x10];
3211
3212         u8         reserved_at_20[0x20];
3213
3214         u8         svlan_cfi[0x1];
3215         u8         svlan_pcp[0x3];
3216         u8         svlan_id[0xc];
3217         u8         cvlan_cfi[0x1];
3218         u8         cvlan_pcp[0x3];
3219         u8         cvlan_id[0xc];
3220
3221         u8         reserved_at_60[0x7a0];
3222 };
3223
3224 enum {
3225         MLX5_EQC_STATUS_OK                = 0x0,
3226         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3227 };
3228
3229 enum {
3230         MLX5_EQC_ST_ARMED  = 0x9,
3231         MLX5_EQC_ST_FIRED  = 0xa,
3232 };
3233
3234 struct mlx5_ifc_eqc_bits {
3235         u8         status[0x4];
3236         u8         reserved_at_4[0x9];
3237         u8         ec[0x1];
3238         u8         oi[0x1];
3239         u8         reserved_at_f[0x5];
3240         u8         st[0x4];
3241         u8         reserved_at_18[0x8];
3242
3243         u8         reserved_at_20[0x20];</