net/mlx5: Add core support for double vlan push/pop steering action
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65
66 enum {
67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72
73 enum {
74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
76 };
77
78 enum {
79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
81 };
82
83 enum {
84         MLX5_OBJ_TYPE_UCTX = 0x0004,
85 };
86
87 enum {
88         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
89         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
90         MLX5_CMD_OP_INIT_HCA                      = 0x102,
91         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
92         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
93         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
94         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
95         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
96         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
97         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
98         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
99         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
100         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
101         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
102         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
103         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
104         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
105         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
106         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
107         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
108         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
109         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
110         MLX5_CMD_OP_GEN_EQE                       = 0x304,
111         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
112         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
113         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
114         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
115         MLX5_CMD_OP_CREATE_QP                     = 0x500,
116         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
117         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
118         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
119         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
120         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
121         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
122         MLX5_CMD_OP_2ERR_QP                       = 0x507,
123         MLX5_CMD_OP_2RST_QP                       = 0x50a,
124         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
125         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
126         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
127         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
128         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
129         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
130         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
131         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
132         MLX5_CMD_OP_ARM_RQ                        = 0x703,
133         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
134         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
135         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
136         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
137         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
138         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
139         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
140         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
141         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
142         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
143         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
144         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
145         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
146         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
147         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
148         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
149         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
150         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
151         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
152         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
153         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
154         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
155         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
156         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
157         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
158         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
159         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
160         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
161         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
162         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
163         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
164         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
165         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
166         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
167         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
168         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
169         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
170         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
171         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
172         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
173         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
174         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
175         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
176         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
177         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
178         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
179         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
180         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
181         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
182         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
183         MLX5_CMD_OP_NOP                           = 0x80d,
184         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
185         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
186         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
187         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
188         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
189         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
190         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
191         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
192         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
193         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
194         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
195         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
196         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
197         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
198         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
199         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
200         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
201         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
202         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
203         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
204         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
205         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
206         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
207         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
208         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
209         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
210         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
211         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
212         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
213         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
214         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
215         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
216         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
217         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
218         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
219         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
220         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
221         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
222         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
223         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
224         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
225         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
226         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
227         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
228         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
229         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
230         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
231         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
232         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
233         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
234         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
235         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
236         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
237         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
238         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
239         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
240         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
241         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
242         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
243         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
244         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
245         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
246         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
247         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
248         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
249         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
250         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
251         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
252         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
253         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
254         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
255         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
256         MLX5_CMD_OP_MAX
257 };
258
259 struct mlx5_ifc_flow_table_fields_supported_bits {
260         u8         outer_dmac[0x1];
261         u8         outer_smac[0x1];
262         u8         outer_ether_type[0x1];
263         u8         outer_ip_version[0x1];
264         u8         outer_first_prio[0x1];
265         u8         outer_first_cfi[0x1];
266         u8         outer_first_vid[0x1];
267         u8         outer_ipv4_ttl[0x1];
268         u8         outer_second_prio[0x1];
269         u8         outer_second_cfi[0x1];
270         u8         outer_second_vid[0x1];
271         u8         reserved_at_b[0x1];
272         u8         outer_sip[0x1];
273         u8         outer_dip[0x1];
274         u8         outer_frag[0x1];
275         u8         outer_ip_protocol[0x1];
276         u8         outer_ip_ecn[0x1];
277         u8         outer_ip_dscp[0x1];
278         u8         outer_udp_sport[0x1];
279         u8         outer_udp_dport[0x1];
280         u8         outer_tcp_sport[0x1];
281         u8         outer_tcp_dport[0x1];
282         u8         outer_tcp_flags[0x1];
283         u8         outer_gre_protocol[0x1];
284         u8         outer_gre_key[0x1];
285         u8         outer_vxlan_vni[0x1];
286         u8         reserved_at_1a[0x5];
287         u8         source_eswitch_port[0x1];
288
289         u8         inner_dmac[0x1];
290         u8         inner_smac[0x1];
291         u8         inner_ether_type[0x1];
292         u8         inner_ip_version[0x1];
293         u8         inner_first_prio[0x1];
294         u8         inner_first_cfi[0x1];
295         u8         inner_first_vid[0x1];
296         u8         reserved_at_27[0x1];
297         u8         inner_second_prio[0x1];
298         u8         inner_second_cfi[0x1];
299         u8         inner_second_vid[0x1];
300         u8         reserved_at_2b[0x1];
301         u8         inner_sip[0x1];
302         u8         inner_dip[0x1];
303         u8         inner_frag[0x1];
304         u8         inner_ip_protocol[0x1];
305         u8         inner_ip_ecn[0x1];
306         u8         inner_ip_dscp[0x1];
307         u8         inner_udp_sport[0x1];
308         u8         inner_udp_dport[0x1];
309         u8         inner_tcp_sport[0x1];
310         u8         inner_tcp_dport[0x1];
311         u8         inner_tcp_flags[0x1];
312         u8         reserved_at_37[0x9];
313
314         u8         reserved_at_40[0x5];
315         u8         outer_first_mpls_over_udp[0x4];
316         u8         outer_first_mpls_over_gre[0x4];
317         u8         inner_first_mpls[0x4];
318         u8         outer_first_mpls[0x4];
319         u8         reserved_at_55[0x2];
320         u8         outer_esp_spi[0x1];
321         u8         reserved_at_58[0x2];
322         u8         bth_dst_qp[0x1];
323
324         u8         reserved_at_5b[0x25];
325 };
326
327 struct mlx5_ifc_flow_table_prop_layout_bits {
328         u8         ft_support[0x1];
329         u8         reserved_at_1[0x1];
330         u8         flow_counter[0x1];
331         u8         flow_modify_en[0x1];
332         u8         modify_root[0x1];
333         u8         identified_miss_table_mode[0x1];
334         u8         flow_table_modify[0x1];
335         u8         encap[0x1];
336         u8         decap[0x1];
337         u8         reserved_at_9[0x1];
338         u8         pop_vlan[0x1];
339         u8         push_vlan[0x1];
340         u8         reserved_at_c[0x1];
341         u8         pop_vlan_2[0x1];
342         u8         push_vlan_2[0x1];
343         u8         reserved_at_f[0x11];
344
345         u8         reserved_at_20[0x2];
346         u8         log_max_ft_size[0x6];
347         u8         log_max_modify_header_context[0x8];
348         u8         max_modify_header_actions[0x8];
349         u8         max_ft_level[0x8];
350
351         u8         reserved_at_40[0x20];
352
353         u8         reserved_at_60[0x18];
354         u8         log_max_ft_num[0x8];
355
356         u8         reserved_at_80[0x18];
357         u8         log_max_destination[0x8];
358
359         u8         log_max_flow_counter[0x8];
360         u8         reserved_at_a8[0x10];
361         u8         log_max_flow[0x8];
362
363         u8         reserved_at_c0[0x40];
364
365         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
366
367         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
368 };
369
370 struct mlx5_ifc_odp_per_transport_service_cap_bits {
371         u8         send[0x1];
372         u8         receive[0x1];
373         u8         write[0x1];
374         u8         read[0x1];
375         u8         atomic[0x1];
376         u8         srq_receive[0x1];
377         u8         reserved_at_6[0x1a];
378 };
379
380 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
381         u8         smac_47_16[0x20];
382
383         u8         smac_15_0[0x10];
384         u8         ethertype[0x10];
385
386         u8         dmac_47_16[0x20];
387
388         u8         dmac_15_0[0x10];
389         u8         first_prio[0x3];
390         u8         first_cfi[0x1];
391         u8         first_vid[0xc];
392
393         u8         ip_protocol[0x8];
394         u8         ip_dscp[0x6];
395         u8         ip_ecn[0x2];
396         u8         cvlan_tag[0x1];
397         u8         svlan_tag[0x1];
398         u8         frag[0x1];
399         u8         ip_version[0x4];
400         u8         tcp_flags[0x9];
401
402         u8         tcp_sport[0x10];
403         u8         tcp_dport[0x10];
404
405         u8         reserved_at_c0[0x18];
406         u8         ttl_hoplimit[0x8];
407
408         u8         udp_sport[0x10];
409         u8         udp_dport[0x10];
410
411         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
412
413         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
414 };
415
416 struct mlx5_ifc_fte_match_set_misc_bits {
417         u8         reserved_at_0[0x8];
418         u8         source_sqn[0x18];
419
420         u8         source_eswitch_owner_vhca_id[0x10];
421         u8         source_port[0x10];
422
423         u8         outer_second_prio[0x3];
424         u8         outer_second_cfi[0x1];
425         u8         outer_second_vid[0xc];
426         u8         inner_second_prio[0x3];
427         u8         inner_second_cfi[0x1];
428         u8         inner_second_vid[0xc];
429
430         u8         outer_second_cvlan_tag[0x1];
431         u8         inner_second_cvlan_tag[0x1];
432         u8         outer_second_svlan_tag[0x1];
433         u8         inner_second_svlan_tag[0x1];
434         u8         reserved_at_64[0xc];
435         u8         gre_protocol[0x10];
436
437         u8         gre_key_h[0x18];
438         u8         gre_key_l[0x8];
439
440         u8         vxlan_vni[0x18];
441         u8         reserved_at_b8[0x8];
442
443         u8         reserved_at_c0[0x20];
444
445         u8         reserved_at_e0[0xc];
446         u8         outer_ipv6_flow_label[0x14];
447
448         u8         reserved_at_100[0xc];
449         u8         inner_ipv6_flow_label[0x14];
450
451         u8         reserved_at_120[0x28];
452         u8         bth_dst_qp[0x18];
453         u8         reserved_at_160[0x20];
454         u8         outer_esp_spi[0x20];
455         u8         reserved_at_1a0[0x60];
456 };
457
458 struct mlx5_ifc_fte_match_mpls_bits {
459         u8         mpls_label[0x14];
460         u8         mpls_exp[0x3];
461         u8         mpls_s_bos[0x1];
462         u8         mpls_ttl[0x8];
463 };
464
465 struct mlx5_ifc_fte_match_set_misc2_bits {
466         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
467
468         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
469
470         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
471
472         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
473
474         u8         reserved_at_80[0x100];
475
476         u8         metadata_reg_a[0x20];
477
478         u8         reserved_at_1a0[0x60];
479 };
480
481 struct mlx5_ifc_cmd_pas_bits {
482         u8         pa_h[0x20];
483
484         u8         pa_l[0x14];
485         u8         reserved_at_34[0xc];
486 };
487
488 struct mlx5_ifc_uint64_bits {
489         u8         hi[0x20];
490
491         u8         lo[0x20];
492 };
493
494 enum {
495         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
496         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
497         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
498         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
499         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
500         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
501         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
502         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
503         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
504         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
505 };
506
507 struct mlx5_ifc_ads_bits {
508         u8         fl[0x1];
509         u8         free_ar[0x1];
510         u8         reserved_at_2[0xe];
511         u8         pkey_index[0x10];
512
513         u8         reserved_at_20[0x8];
514         u8         grh[0x1];
515         u8         mlid[0x7];
516         u8         rlid[0x10];
517
518         u8         ack_timeout[0x5];
519         u8         reserved_at_45[0x3];
520         u8         src_addr_index[0x8];
521         u8         reserved_at_50[0x4];
522         u8         stat_rate[0x4];
523         u8         hop_limit[0x8];
524
525         u8         reserved_at_60[0x4];
526         u8         tclass[0x8];
527         u8         flow_label[0x14];
528
529         u8         rgid_rip[16][0x8];
530
531         u8         reserved_at_100[0x4];
532         u8         f_dscp[0x1];
533         u8         f_ecn[0x1];
534         u8         reserved_at_106[0x1];
535         u8         f_eth_prio[0x1];
536         u8         ecn[0x2];
537         u8         dscp[0x6];
538         u8         udp_sport[0x10];
539
540         u8         dei_cfi[0x1];
541         u8         eth_prio[0x3];
542         u8         sl[0x4];
543         u8         vhca_port_num[0x8];
544         u8         rmac_47_32[0x10];
545
546         u8         rmac_31_0[0x20];
547 };
548
549 struct mlx5_ifc_flow_table_nic_cap_bits {
550         u8         nic_rx_multi_path_tirs[0x1];
551         u8         nic_rx_multi_path_tirs_fts[0x1];
552         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
553         u8         reserved_at_3[0x1fd];
554
555         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
556
557         u8         reserved_at_400[0x200];
558
559         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
560
561         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
562
563         u8         reserved_at_a00[0x200];
564
565         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
566
567         u8         reserved_at_e00[0x7200];
568 };
569
570 struct mlx5_ifc_flow_table_eswitch_cap_bits {
571         u8      reserved_at_0[0x1c];
572         u8      fdb_multi_path_to_table[0x1];
573         u8      reserved_at_1d[0x1e3];
574
575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
576
577         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
578
579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
580
581         u8      reserved_at_800[0x7800];
582 };
583
584 struct mlx5_ifc_e_switch_cap_bits {
585         u8         vport_svlan_strip[0x1];
586         u8         vport_cvlan_strip[0x1];
587         u8         vport_svlan_insert[0x1];
588         u8         vport_cvlan_insert_if_not_exist[0x1];
589         u8         vport_cvlan_insert_overwrite[0x1];
590         u8         reserved_at_5[0x18];
591         u8         merged_eswitch[0x1];
592         u8         nic_vport_node_guid_modify[0x1];
593         u8         nic_vport_port_guid_modify[0x1];
594
595         u8         vxlan_encap_decap[0x1];
596         u8         nvgre_encap_decap[0x1];
597         u8         reserved_at_22[0x9];
598         u8         log_max_encap_headers[0x5];
599         u8         reserved_2b[0x6];
600         u8         max_encap_header_size[0xa];
601
602         u8         reserved_40[0x7c0];
603
604 };
605
606 struct mlx5_ifc_qos_cap_bits {
607         u8         packet_pacing[0x1];
608         u8         esw_scheduling[0x1];
609         u8         esw_bw_share[0x1];
610         u8         esw_rate_limit[0x1];
611         u8         reserved_at_4[0x1];
612         u8         packet_pacing_burst_bound[0x1];
613         u8         packet_pacing_typical_size[0x1];
614         u8         reserved_at_7[0x19];
615
616         u8         reserved_at_20[0x20];
617
618         u8         packet_pacing_max_rate[0x20];
619
620         u8         packet_pacing_min_rate[0x20];
621
622         u8         reserved_at_80[0x10];
623         u8         packet_pacing_rate_table_size[0x10];
624
625         u8         esw_element_type[0x10];
626         u8         esw_tsar_type[0x10];
627
628         u8         reserved_at_c0[0x10];
629         u8         max_qos_para_vport[0x10];
630
631         u8         max_tsar_bw_share[0x20];
632
633         u8         reserved_at_100[0x700];
634 };
635
636 struct mlx5_ifc_debug_cap_bits {
637         u8         reserved_at_0[0x20];
638
639         u8         reserved_at_20[0x2];
640         u8         stall_detect[0x1];
641         u8         reserved_at_23[0x1d];
642
643         u8         reserved_at_40[0x7c0];
644 };
645
646 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
647         u8         csum_cap[0x1];
648         u8         vlan_cap[0x1];
649         u8         lro_cap[0x1];
650         u8         lro_psh_flag[0x1];
651         u8         lro_time_stamp[0x1];
652         u8         reserved_at_5[0x2];
653         u8         wqe_vlan_insert[0x1];
654         u8         self_lb_en_modifiable[0x1];
655         u8         reserved_at_9[0x2];
656         u8         max_lso_cap[0x5];
657         u8         multi_pkt_send_wqe[0x2];
658         u8         wqe_inline_mode[0x2];
659         u8         rss_ind_tbl_cap[0x4];
660         u8         reg_umr_sq[0x1];
661         u8         scatter_fcs[0x1];
662         u8         enhanced_multi_pkt_send_wqe[0x1];
663         u8         tunnel_lso_const_out_ip_id[0x1];
664         u8         reserved_at_1c[0x2];
665         u8         tunnel_stateless_gre[0x1];
666         u8         tunnel_stateless_vxlan[0x1];
667
668         u8         swp[0x1];
669         u8         swp_csum[0x1];
670         u8         swp_lso[0x1];
671         u8         reserved_at_23[0x1b];
672         u8         max_geneve_opt_len[0x1];
673         u8         tunnel_stateless_geneve_rx[0x1];
674
675         u8         reserved_at_40[0x10];
676         u8         lro_min_mss_size[0x10];
677
678         u8         reserved_at_60[0x120];
679
680         u8         lro_timer_supported_periods[4][0x20];
681
682         u8         reserved_at_200[0x600];
683 };
684
685 struct mlx5_ifc_roce_cap_bits {
686         u8         roce_apm[0x1];
687         u8         reserved_at_1[0x1f];
688
689         u8         reserved_at_20[0x60];
690
691         u8         reserved_at_80[0xc];
692         u8         l3_type[0x4];
693         u8         reserved_at_90[0x8];
694         u8         roce_version[0x8];
695
696         u8         reserved_at_a0[0x10];
697         u8         r_roce_dest_udp_port[0x10];
698
699         u8         r_roce_max_src_udp_port[0x10];
700         u8         r_roce_min_src_udp_port[0x10];
701
702         u8         reserved_at_e0[0x10];
703         u8         roce_address_table_size[0x10];
704
705         u8         reserved_at_100[0x700];
706 };
707
708 struct mlx5_ifc_device_mem_cap_bits {
709         u8         memic[0x1];
710         u8         reserved_at_1[0x1f];
711
712         u8         reserved_at_20[0xb];
713         u8         log_min_memic_alloc_size[0x5];
714         u8         reserved_at_30[0x8];
715         u8         log_max_memic_addr_alignment[0x8];
716
717         u8         memic_bar_start_addr[0x40];
718
719         u8         memic_bar_size[0x20];
720
721         u8         max_memic_size[0x20];
722
723         u8         reserved_at_c0[0x740];
724 };
725
726 enum {
727         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
728         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
729         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
730         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
733         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
734         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
735         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
736 };
737
738 enum {
739         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
740         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
741         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
742         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
748 };
749
750 struct mlx5_ifc_atomic_caps_bits {
751         u8         reserved_at_0[0x40];
752
753         u8         atomic_req_8B_endianness_mode[0x2];
754         u8         reserved_at_42[0x4];
755         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
756
757         u8         reserved_at_47[0x19];
758
759         u8         reserved_at_60[0x20];
760
761         u8         reserved_at_80[0x10];
762         u8         atomic_operations[0x10];
763
764         u8         reserved_at_a0[0x10];
765         u8         atomic_size_qp[0x10];
766
767         u8         reserved_at_c0[0x10];
768         u8         atomic_size_dc[0x10];
769
770         u8         reserved_at_e0[0x720];
771 };
772
773 struct mlx5_ifc_odp_cap_bits {
774         u8         reserved_at_0[0x40];
775
776         u8         sig[0x1];
777         u8         reserved_at_41[0x1f];
778
779         u8         reserved_at_60[0x20];
780
781         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
782
783         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
784
785         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
786
787         u8         reserved_at_e0[0x720];
788 };
789
790 struct mlx5_ifc_calc_op {
791         u8        reserved_at_0[0x10];
792         u8        reserved_at_10[0x9];
793         u8        op_swap_endianness[0x1];
794         u8        op_min[0x1];
795         u8        op_xor[0x1];
796         u8        op_or[0x1];
797         u8        op_and[0x1];
798         u8        op_max[0x1];
799         u8        op_add[0x1];
800 };
801
802 struct mlx5_ifc_vector_calc_cap_bits {
803         u8         calc_matrix[0x1];
804         u8         reserved_at_1[0x1f];
805         u8         reserved_at_20[0x8];
806         u8         max_vec_count[0x8];
807         u8         reserved_at_30[0xd];
808         u8         max_chunk_size[0x3];
809         struct mlx5_ifc_calc_op calc0;
810         struct mlx5_ifc_calc_op calc1;
811         struct mlx5_ifc_calc_op calc2;
812         struct mlx5_ifc_calc_op calc3;
813
814         u8         reserved_at_e0[0x720];
815 };
816
817 enum {
818         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
819         MLX5_WQ_TYPE_CYCLIC       = 0x1,
820         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
821         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
822 };
823
824 enum {
825         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
826         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
827 };
828
829 enum {
830         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
831         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
832         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
833         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
834         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
835 };
836
837 enum {
838         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
839         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
840         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
841         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
842         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
843         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
844 };
845
846 enum {
847         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
848         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
849 };
850
851 enum {
852         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
853         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
854         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
855 };
856
857 enum {
858         MLX5_CAP_PORT_TYPE_IB  = 0x0,
859         MLX5_CAP_PORT_TYPE_ETH = 0x1,
860 };
861
862 enum {
863         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
864         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
865         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
866 };
867
868 struct mlx5_ifc_cmd_hca_cap_bits {
869         u8         reserved_at_0[0x30];
870         u8         vhca_id[0x10];
871
872         u8         reserved_at_40[0x40];
873
874         u8         log_max_srq_sz[0x8];
875         u8         log_max_qp_sz[0x8];
876         u8         reserved_at_90[0xb];
877         u8         log_max_qp[0x5];
878
879         u8         reserved_at_a0[0xb];
880         u8         log_max_srq[0x5];
881         u8         reserved_at_b0[0x10];
882
883         u8         reserved_at_c0[0x8];
884         u8         log_max_cq_sz[0x8];
885         u8         reserved_at_d0[0xb];
886         u8         log_max_cq[0x5];
887
888         u8         log_max_eq_sz[0x8];
889         u8         reserved_at_e8[0x2];
890         u8         log_max_mkey[0x6];
891         u8         reserved_at_f0[0x8];
892         u8         dump_fill_mkey[0x1];
893         u8         reserved_at_f9[0x3];
894         u8         log_max_eq[0x4];
895
896         u8         max_indirection[0x8];
897         u8         fixed_buffer_size[0x1];
898         u8         log_max_mrw_sz[0x7];
899         u8         force_teardown[0x1];
900         u8         reserved_at_111[0x1];
901         u8         log_max_bsf_list_size[0x6];
902         u8         umr_extended_translation_offset[0x1];
903         u8         null_mkey[0x1];
904         u8         log_max_klm_list_size[0x6];
905
906         u8         reserved_at_120[0xa];
907         u8         log_max_ra_req_dc[0x6];
908         u8         reserved_at_130[0xa];
909         u8         log_max_ra_res_dc[0x6];
910
911         u8         reserved_at_140[0xa];
912         u8         log_max_ra_req_qp[0x6];
913         u8         reserved_at_150[0xa];
914         u8         log_max_ra_res_qp[0x6];
915
916         u8         end_pad[0x1];
917         u8         cc_query_allowed[0x1];
918         u8         cc_modify_allowed[0x1];
919         u8         start_pad[0x1];
920         u8         cache_line_128byte[0x1];
921         u8         reserved_at_165[0xa];
922         u8         qcam_reg[0x1];
923         u8         gid_table_size[0x10];
924
925         u8         out_of_seq_cnt[0x1];
926         u8         vport_counters[0x1];
927         u8         retransmission_q_counters[0x1];
928         u8         debug[0x1];
929         u8         modify_rq_counter_set_id[0x1];
930         u8         rq_delay_drop[0x1];
931         u8         max_qp_cnt[0xa];
932         u8         pkey_table_size[0x10];
933
934         u8         vport_group_manager[0x1];
935         u8         vhca_group_manager[0x1];
936         u8         ib_virt[0x1];
937         u8         eth_virt[0x1];
938         u8         vnic_env_queue_counters[0x1];
939         u8         ets[0x1];
940         u8         nic_flow_table[0x1];
941         u8         eswitch_flow_table[0x1];
942         u8         device_memory[0x1];
943         u8         mcam_reg[0x1];
944         u8         pcam_reg[0x1];
945         u8         local_ca_ack_delay[0x5];
946         u8         port_module_event[0x1];
947         u8         enhanced_error_q_counters[0x1];
948         u8         ports_check[0x1];
949         u8         reserved_at_1b3[0x1];
950         u8         disable_link_up[0x1];
951         u8         beacon_led[0x1];
952         u8         port_type[0x2];
953         u8         num_ports[0x8];
954
955         u8         reserved_at_1c0[0x1];
956         u8         pps[0x1];
957         u8         pps_modify[0x1];
958         u8         log_max_msg[0x5];
959         u8         reserved_at_1c8[0x4];
960         u8         max_tc[0x4];
961         u8         temp_warn_event[0x1];
962         u8         dcbx[0x1];
963         u8         general_notification_event[0x1];
964         u8         reserved_at_1d3[0x2];
965         u8         fpga[0x1];
966         u8         rol_s[0x1];
967         u8         rol_g[0x1];
968         u8         reserved_at_1d8[0x1];
969         u8         wol_s[0x1];
970         u8         wol_g[0x1];
971         u8         wol_a[0x1];
972         u8         wol_b[0x1];
973         u8         wol_m[0x1];
974         u8         wol_u[0x1];
975         u8         wol_p[0x1];
976
977         u8         stat_rate_support[0x10];
978         u8         reserved_at_1f0[0xc];
979         u8         cqe_version[0x4];
980
981         u8         compact_address_vector[0x1];
982         u8         striding_rq[0x1];
983         u8         reserved_at_202[0x1];
984         u8         ipoib_enhanced_offloads[0x1];
985         u8         ipoib_basic_offloads[0x1];
986         u8         reserved_at_205[0x1];
987         u8         repeated_block_disabled[0x1];
988         u8         umr_modify_entity_size_disabled[0x1];
989         u8         umr_modify_atomic_disabled[0x1];
990         u8         umr_indirect_mkey_disabled[0x1];
991         u8         umr_fence[0x2];
992         u8         reserved_at_20c[0x3];
993         u8         drain_sigerr[0x1];
994         u8         cmdif_checksum[0x2];
995         u8         sigerr_cqe[0x1];
996         u8         reserved_at_213[0x1];
997         u8         wq_signature[0x1];
998         u8         sctr_data_cqe[0x1];
999         u8         reserved_at_216[0x1];
1000         u8         sho[0x1];
1001         u8         tph[0x1];
1002         u8         rf[0x1];
1003         u8         dct[0x1];
1004         u8         qos[0x1];
1005         u8         eth_net_offloads[0x1];
1006         u8         roce[0x1];
1007         u8         atomic[0x1];
1008         u8         reserved_at_21f[0x1];
1009
1010         u8         cq_oi[0x1];
1011         u8         cq_resize[0x1];
1012         u8         cq_moderation[0x1];
1013         u8         reserved_at_223[0x3];
1014         u8         cq_eq_remap[0x1];
1015         u8         pg[0x1];
1016         u8         block_lb_mc[0x1];
1017         u8         reserved_at_229[0x1];
1018         u8         scqe_break_moderation[0x1];
1019         u8         cq_period_start_from_cqe[0x1];
1020         u8         cd[0x1];
1021         u8         reserved_at_22d[0x1];
1022         u8         apm[0x1];
1023         u8         vector_calc[0x1];
1024         u8         umr_ptr_rlky[0x1];
1025         u8         imaicl[0x1];
1026         u8         reserved_at_232[0x4];
1027         u8         qkv[0x1];
1028         u8         pkv[0x1];
1029         u8         set_deth_sqpn[0x1];
1030         u8         reserved_at_239[0x3];
1031         u8         xrc[0x1];
1032         u8         ud[0x1];
1033         u8         uc[0x1];
1034         u8         rc[0x1];
1035
1036         u8         uar_4k[0x1];
1037         u8         reserved_at_241[0x9];
1038         u8         uar_sz[0x6];
1039         u8         reserved_at_250[0x8];
1040         u8         log_pg_sz[0x8];
1041
1042         u8         bf[0x1];
1043         u8         driver_version[0x1];
1044         u8         pad_tx_eth_packet[0x1];
1045         u8         reserved_at_263[0x8];
1046         u8         log_bf_reg_size[0x5];
1047
1048         u8         reserved_at_270[0xb];
1049         u8         lag_master[0x1];
1050         u8         num_lag_ports[0x4];
1051
1052         u8         reserved_at_280[0x10];
1053         u8         max_wqe_sz_sq[0x10];
1054
1055         u8         reserved_at_2a0[0x10];
1056         u8         max_wqe_sz_rq[0x10];
1057
1058         u8         max_flow_counter_31_16[0x10];
1059         u8         max_wqe_sz_sq_dc[0x10];
1060
1061         u8         reserved_at_2e0[0x7];
1062         u8         max_qp_mcg[0x19];
1063
1064         u8         reserved_at_300[0x18];
1065         u8         log_max_mcg[0x8];
1066
1067         u8         reserved_at_320[0x3];
1068         u8         log_max_transport_domain[0x5];
1069         u8         reserved_at_328[0x3];
1070         u8         log_max_pd[0x5];
1071         u8         reserved_at_330[0xb];
1072         u8         log_max_xrcd[0x5];
1073
1074         u8         nic_receive_steering_discard[0x1];
1075         u8         receive_discard_vport_down[0x1];
1076         u8         transmit_discard_vport_down[0x1];
1077         u8         reserved_at_343[0x5];
1078         u8         log_max_flow_counter_bulk[0x8];
1079         u8         max_flow_counter_15_0[0x10];
1080
1081
1082         u8         reserved_at_360[0x3];
1083         u8         log_max_rq[0x5];
1084         u8         reserved_at_368[0x3];
1085         u8         log_max_sq[0x5];
1086         u8         reserved_at_370[0x3];
1087         u8         log_max_tir[0x5];
1088         u8         reserved_at_378[0x3];
1089         u8         log_max_tis[0x5];
1090
1091         u8         basic_cyclic_rcv_wqe[0x1];
1092         u8         reserved_at_381[0x2];
1093         u8         log_max_rmp[0x5];
1094         u8         reserved_at_388[0x3];
1095         u8         log_max_rqt[0x5];
1096         u8         reserved_at_390[0x3];
1097         u8         log_max_rqt_size[0x5];
1098         u8         reserved_at_398[0x3];
1099         u8         log_max_tis_per_sq[0x5];
1100
1101         u8         ext_stride_num_range[0x1];
1102         u8         reserved_at_3a1[0x2];
1103         u8         log_max_stride_sz_rq[0x5];
1104         u8         reserved_at_3a8[0x3];
1105         u8         log_min_stride_sz_rq[0x5];
1106         u8         reserved_at_3b0[0x3];
1107         u8         log_max_stride_sz_sq[0x5];
1108         u8         reserved_at_3b8[0x3];
1109         u8         log_min_stride_sz_sq[0x5];
1110
1111         u8         hairpin[0x1];
1112         u8         reserved_at_3c1[0x2];
1113         u8         log_max_hairpin_queues[0x5];
1114         u8         reserved_at_3c8[0x3];
1115         u8         log_max_hairpin_wq_data_sz[0x5];
1116         u8         reserved_at_3d0[0x3];
1117         u8         log_max_hairpin_num_packets[0x5];
1118         u8         reserved_at_3d8[0x3];
1119         u8         log_max_wq_sz[0x5];
1120
1121         u8         nic_vport_change_event[0x1];
1122         u8         disable_local_lb_uc[0x1];
1123         u8         disable_local_lb_mc[0x1];
1124         u8         log_min_hairpin_wq_data_sz[0x5];
1125         u8         reserved_at_3e8[0x3];
1126         u8         log_max_vlan_list[0x5];
1127         u8         reserved_at_3f0[0x3];
1128         u8         log_max_current_mc_list[0x5];
1129         u8         reserved_at_3f8[0x3];
1130         u8         log_max_current_uc_list[0x5];
1131
1132         u8         general_obj_types[0x40];
1133
1134         u8         reserved_at_440[0x40];
1135
1136         u8         reserved_at_480[0x3];
1137         u8         log_max_l2_table[0x5];
1138         u8         reserved_at_488[0x8];
1139         u8         log_uar_page_sz[0x10];
1140
1141         u8         reserved_at_4a0[0x20];
1142         u8         device_frequency_mhz[0x20];
1143         u8         device_frequency_khz[0x20];
1144
1145         u8         reserved_at_500[0x20];
1146         u8         num_of_uars_per_page[0x20];
1147
1148         u8         flex_parser_protocols[0x20];
1149         u8         reserved_at_560[0x20];
1150
1151         u8         reserved_at_580[0x3c];
1152         u8         mini_cqe_resp_stride_index[0x1];
1153         u8         cqe_128_always[0x1];
1154         u8         cqe_compression_128[0x1];
1155         u8         cqe_compression[0x1];
1156
1157         u8         cqe_compression_timeout[0x10];
1158         u8         cqe_compression_max_num[0x10];
1159
1160         u8         reserved_at_5e0[0x10];
1161         u8         tag_matching[0x1];
1162         u8         rndv_offload_rc[0x1];
1163         u8         rndv_offload_dc[0x1];
1164         u8         log_tag_matching_list_sz[0x5];
1165         u8         reserved_at_5f8[0x3];
1166         u8         log_max_xrq[0x5];
1167
1168         u8         affiliate_nic_vport_criteria[0x8];
1169         u8         native_port_num[0x8];
1170         u8         num_vhca_ports[0x8];
1171         u8         reserved_at_618[0x6];
1172         u8         sw_owner_id[0x1];
1173         u8         reserved_at_61f[0x1e1];
1174 };
1175
1176 enum mlx5_flow_destination_type {
1177         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1178         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1179         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1180
1181         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1182         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1183 };
1184
1185 struct mlx5_ifc_dest_format_struct_bits {
1186         u8         destination_type[0x8];
1187         u8         destination_id[0x18];
1188         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1189         u8         reserved_at_21[0xf];
1190         u8         destination_eswitch_owner_vhca_id[0x10];
1191 };
1192
1193 struct mlx5_ifc_flow_counter_list_bits {
1194         u8         flow_counter_id[0x20];
1195
1196         u8         reserved_at_20[0x20];
1197 };
1198
1199 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1200         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1201         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1202         u8         reserved_at_0[0x40];
1203 };
1204
1205 struct mlx5_ifc_fte_match_param_bits {
1206         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1207
1208         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1209
1210         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1211
1212         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1213
1214         u8         reserved_at_800[0x800];
1215 };
1216
1217 enum {
1218         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1219         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1220         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1221         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1222         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1223 };
1224
1225 struct mlx5_ifc_rx_hash_field_select_bits {
1226         u8         l3_prot_type[0x1];
1227         u8         l4_prot_type[0x1];
1228         u8         selected_fields[0x1e];
1229 };
1230
1231 enum {
1232         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1233         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1234 };
1235
1236 enum {
1237         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1238         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1239 };
1240
1241 struct mlx5_ifc_wq_bits {
1242         u8         wq_type[0x4];
1243         u8         wq_signature[0x1];
1244         u8         end_padding_mode[0x2];
1245         u8         cd_slave[0x1];
1246         u8         reserved_at_8[0x18];
1247
1248         u8         hds_skip_first_sge[0x1];
1249         u8         log2_hds_buf_size[0x3];
1250         u8         reserved_at_24[0x7];
1251         u8         page_offset[0x5];
1252         u8         lwm[0x10];
1253
1254         u8         reserved_at_40[0x8];
1255         u8         pd[0x18];
1256
1257         u8         reserved_at_60[0x8];
1258         u8         uar_page[0x18];
1259
1260         u8         dbr_addr[0x40];
1261
1262         u8         hw_counter[0x20];
1263
1264         u8         sw_counter[0x20];
1265
1266         u8         reserved_at_100[0xc];
1267         u8         log_wq_stride[0x4];
1268         u8         reserved_at_110[0x3];
1269         u8         log_wq_pg_sz[0x5];
1270         u8         reserved_at_118[0x3];
1271         u8         log_wq_sz[0x5];
1272
1273         u8         reserved_at_120[0x3];
1274         u8         log_hairpin_num_packets[0x5];
1275         u8         reserved_at_128[0x3];
1276         u8         log_hairpin_data_sz[0x5];
1277
1278         u8         reserved_at_130[0x4];
1279         u8         log_wqe_num_of_strides[0x4];
1280         u8         two_byte_shift_en[0x1];
1281         u8         reserved_at_139[0x4];
1282         u8         log_wqe_stride_size[0x3];
1283
1284         u8         reserved_at_140[0x4c0];
1285
1286         struct mlx5_ifc_cmd_pas_bits pas[0];
1287 };
1288
1289 struct mlx5_ifc_rq_num_bits {
1290         u8         reserved_at_0[0x8];
1291         u8         rq_num[0x18];
1292 };
1293
1294 struct mlx5_ifc_mac_address_layout_bits {
1295         u8         reserved_at_0[0x10];
1296         u8         mac_addr_47_32[0x10];
1297
1298         u8         mac_addr_31_0[0x20];
1299 };
1300
1301 struct mlx5_ifc_vlan_layout_bits {
1302         u8         reserved_at_0[0x14];
1303         u8         vlan[0x0c];
1304
1305         u8         reserved_at_20[0x20];
1306 };
1307
1308 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1309         u8         reserved_at_0[0xa0];
1310
1311         u8         min_time_between_cnps[0x20];
1312
1313         u8         reserved_at_c0[0x12];
1314         u8         cnp_dscp[0x6];
1315         u8         reserved_at_d8[0x4];
1316         u8         cnp_prio_mode[0x1];
1317         u8         cnp_802p_prio[0x3];
1318
1319         u8         reserved_at_e0[0x720];
1320 };
1321
1322 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1323         u8         reserved_at_0[0x60];
1324
1325         u8         reserved_at_60[0x4];
1326         u8         clamp_tgt_rate[0x1];
1327         u8         reserved_at_65[0x3];
1328         u8         clamp_tgt_rate_after_time_inc[0x1];
1329         u8         reserved_at_69[0x17];
1330
1331         u8         reserved_at_80[0x20];
1332
1333         u8         rpg_time_reset[0x20];
1334
1335         u8         rpg_byte_reset[0x20];
1336
1337         u8         rpg_threshold[0x20];
1338
1339         u8         rpg_max_rate[0x20];
1340
1341         u8         rpg_ai_rate[0x20];
1342
1343         u8         rpg_hai_rate[0x20];
1344
1345         u8         rpg_gd[0x20];
1346
1347         u8         rpg_min_dec_fac[0x20];
1348
1349         u8         rpg_min_rate[0x20];
1350
1351         u8         reserved_at_1c0[0xe0];
1352
1353         u8         rate_to_set_on_first_cnp[0x20];
1354
1355         u8         dce_tcp_g[0x20];
1356
1357         u8         dce_tcp_rtt[0x20];
1358
1359         u8         rate_reduce_monitor_period[0x20];
1360
1361         u8         reserved_at_320[0x20];
1362
1363         u8         initial_alpha_value[0x20];
1364
1365         u8         reserved_at_360[0x4a0];
1366 };
1367
1368 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1369         u8         reserved_at_0[0x80];
1370
1371         u8         rppp_max_rps[0x20];
1372
1373         u8         rpg_time_reset[0x20];
1374
1375         u8         rpg_byte_reset[0x20];
1376
1377         u8         rpg_threshold[0x20];
1378
1379         u8         rpg_max_rate[0x20];
1380
1381         u8         rpg_ai_rate[0x20];
1382
1383         u8         rpg_hai_rate[0x20];
1384
1385         u8         rpg_gd[0x20];
1386
1387         u8         rpg_min_dec_fac[0x20];
1388
1389         u8         rpg_min_rate[0x20];
1390
1391         u8         reserved_at_1c0[0x640];
1392 };
1393
1394 enum {
1395         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1396         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1397         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1398 };
1399
1400 struct mlx5_ifc_resize_field_select_bits {
1401         u8         resize_field_select[0x20];
1402 };
1403
1404 enum {
1405         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1406         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1407         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1408         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1409 };
1410
1411 struct mlx5_ifc_modify_field_select_bits {
1412         u8         modify_field_select[0x20];
1413 };
1414
1415 struct mlx5_ifc_field_select_r_roce_np_bits {
1416         u8         field_select_r_roce_np[0x20];
1417 };
1418
1419 struct mlx5_ifc_field_select_r_roce_rp_bits {
1420         u8         field_select_r_roce_rp[0x20];
1421 };
1422
1423 enum {
1424         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1425         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1426         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1427         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1428         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1429         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1430         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1431         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1432         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1433         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1434 };
1435
1436 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1437         u8         field_select_8021qaurp[0x20];
1438 };
1439
1440 struct mlx5_ifc_phys_layer_cntrs_bits {
1441         u8         time_since_last_clear_high[0x20];
1442
1443         u8         time_since_last_clear_low[0x20];
1444
1445         u8         symbol_errors_high[0x20];
1446
1447         u8         symbol_errors_low[0x20];
1448
1449         u8         sync_headers_errors_high[0x20];
1450
1451         u8         sync_headers_errors_low[0x20];
1452
1453         u8         edpl_bip_errors_lane0_high[0x20];
1454
1455         u8         edpl_bip_errors_lane0_low[0x20];
1456
1457         u8         edpl_bip_errors_lane1_high[0x20];
1458
1459         u8         edpl_bip_errors_lane1_low[0x20];
1460
1461         u8         edpl_bip_errors_lane2_high[0x20];
1462
1463         u8         edpl_bip_errors_lane2_low[0x20];
1464
1465         u8         edpl_bip_errors_lane3_high[0x20];
1466
1467         u8         edpl_bip_errors_lane3_low[0x20];
1468
1469         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1470
1471         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1472
1473         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1474
1475         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1476
1477         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1478
1479         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1480
1481         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1482
1483         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1484
1485         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1486
1487         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1488
1489         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1490
1491         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1492
1493         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1494
1495         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1496
1497         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1498
1499         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1500
1501         u8         rs_fec_corrected_blocks_high[0x20];
1502
1503         u8         rs_fec_corrected_blocks_low[0x20];
1504
1505         u8         rs_fec_uncorrectable_blocks_high[0x20];
1506
1507         u8         rs_fec_uncorrectable_blocks_low[0x20];
1508
1509         u8         rs_fec_no_errors_blocks_high[0x20];
1510
1511         u8         rs_fec_no_errors_blocks_low[0x20];
1512
1513         u8         rs_fec_single_error_blocks_high[0x20];
1514
1515         u8         rs_fec_single_error_blocks_low[0x20];
1516
1517         u8         rs_fec_corrected_symbols_total_high[0x20];
1518
1519         u8         rs_fec_corrected_symbols_total_low[0x20];
1520
1521         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1522
1523         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1524
1525         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1526
1527         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1528
1529         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1530
1531         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1532
1533         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1534
1535         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1536
1537         u8         link_down_events[0x20];
1538
1539         u8         successful_recovery_events[0x20];
1540
1541         u8         reserved_at_640[0x180];
1542 };
1543
1544 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1545         u8         time_since_last_clear_high[0x20];
1546
1547         u8         time_since_last_clear_low[0x20];
1548
1549         u8         phy_received_bits_high[0x20];
1550
1551         u8         phy_received_bits_low[0x20];
1552
1553         u8         phy_symbol_errors_high[0x20];
1554
1555         u8         phy_symbol_errors_low[0x20];
1556
1557         u8         phy_corrected_bits_high[0x20];
1558
1559         u8         phy_corrected_bits_low[0x20];
1560
1561         u8         phy_corrected_bits_lane0_high[0x20];
1562
1563         u8         phy_corrected_bits_lane0_low[0x20];
1564
1565         u8         phy_corrected_bits_lane1_high[0x20];
1566
1567         u8         phy_corrected_bits_lane1_low[0x20];
1568
1569         u8         phy_corrected_bits_lane2_high[0x20];
1570
1571         u8         phy_corrected_bits_lane2_low[0x20];
1572
1573         u8         phy_corrected_bits_lane3_high[0x20];
1574
1575         u8         phy_corrected_bits_lane3_low[0x20];
1576
1577         u8         reserved_at_200[0x5c0];
1578 };
1579
1580 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1581         u8         symbol_error_counter[0x10];
1582
1583         u8         link_error_recovery_counter[0x8];
1584
1585         u8         link_downed_counter[0x8];
1586
1587         u8         port_rcv_errors[0x10];
1588
1589         u8         port_rcv_remote_physical_errors[0x10];
1590
1591         u8         port_rcv_switch_relay_errors[0x10];
1592
1593         u8         port_xmit_discards[0x10];
1594
1595         u8         port_xmit_constraint_errors[0x8];
1596
1597         u8         port_rcv_constraint_errors[0x8];
1598
1599         u8         reserved_at_70[0x8];
1600
1601         u8         link_overrun_errors[0x8];
1602
1603         u8         reserved_at_80[0x10];
1604
1605         u8         vl_15_dropped[0x10];
1606
1607         u8         reserved_at_a0[0x80];
1608
1609         u8         port_xmit_wait[0x20];
1610 };
1611
1612 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1613         u8         transmit_queue_high[0x20];
1614
1615         u8         transmit_queue_low[0x20];
1616
1617         u8         reserved_at_40[0x780];
1618 };
1619
1620 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1621         u8         rx_octets_high[0x20];
1622
1623         u8         rx_octets_low[0x20];
1624
1625         u8         reserved_at_40[0xc0];
1626
1627         u8         rx_frames_high[0x20];
1628
1629         u8         rx_frames_low[0x20];
1630
1631         u8         tx_octets_high[0x20];
1632
1633         u8         tx_octets_low[0x20];
1634
1635         u8         reserved_at_180[0xc0];
1636
1637         u8         tx_frames_high[0x20];
1638
1639         u8         tx_frames_low[0x20];
1640
1641         u8         rx_pause_high[0x20];
1642
1643         u8         rx_pause_low[0x20];
1644
1645         u8         rx_pause_duration_high[0x20];
1646
1647         u8         rx_pause_duration_low[0x20];
1648
1649         u8         tx_pause_high[0x20];
1650
1651         u8         tx_pause_low[0x20];
1652
1653         u8         tx_pause_duration_high[0x20];
1654
1655         u8         tx_pause_duration_low[0x20];
1656
1657         u8         rx_pause_transition_high[0x20];
1658
1659         u8         rx_pause_transition_low[0x20];
1660
1661         u8         reserved_at_3c0[0x40];
1662
1663         u8         device_stall_minor_watermark_cnt_high[0x20];
1664
1665         u8         device_stall_minor_watermark_cnt_low[0x20];
1666
1667         u8         device_stall_critical_watermark_cnt_high[0x20];
1668
1669         u8         device_stall_critical_watermark_cnt_low[0x20];
1670
1671         u8         reserved_at_480[0x340];
1672 };
1673
1674 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1675         u8         port_transmit_wait_high[0x20];
1676
1677         u8         port_transmit_wait_low[0x20];
1678
1679         u8         reserved_at_40[0x100];
1680
1681         u8         rx_buffer_almost_full_high[0x20];
1682
1683         u8         rx_buffer_almost_full_low[0x20];
1684
1685         u8         rx_buffer_full_high[0x20];
1686
1687         u8         rx_buffer_full_low[0x20];
1688
1689         u8         rx_icrc_encapsulated_high[0x20];
1690
1691         u8         rx_icrc_encapsulated_low[0x20];
1692
1693         u8         reserved_at_200[0x5c0];
1694 };
1695
1696 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1697         u8         dot3stats_alignment_errors_high[0x20];
1698
1699         u8         dot3stats_alignment_errors_low[0x20];
1700
1701         u8         dot3stats_fcs_errors_high[0x20];
1702
1703         u8         dot3stats_fcs_errors_low[0x20];
1704
1705         u8         dot3stats_single_collision_frames_high[0x20];
1706
1707         u8         dot3stats_single_collision_frames_low[0x20];
1708
1709         u8         dot3stats_multiple_collision_frames_high[0x20];
1710
1711         u8         dot3stats_multiple_collision_frames_low[0x20];
1712
1713         u8         dot3stats_sqe_test_errors_high[0x20];
1714
1715         u8         dot3stats_sqe_test_errors_low[0x20];
1716
1717         u8         dot3stats_deferred_transmissions_high[0x20];
1718
1719         u8         dot3stats_deferred_transmissions_low[0x20];
1720
1721         u8         dot3stats_late_collisions_high[0x20];
1722
1723         u8         dot3stats_late_collisions_low[0x20];
1724
1725         u8         dot3stats_excessive_collisions_high[0x20];
1726
1727         u8         dot3stats_excessive_collisions_low[0x20];
1728
1729         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1730
1731         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1732
1733         u8         dot3stats_carrier_sense_errors_high[0x20];
1734
1735         u8         dot3stats_carrier_sense_errors_low[0x20];
1736
1737         u8         dot3stats_frame_too_longs_high[0x20];
1738
1739         u8         dot3stats_frame_too_longs_low[0x20];
1740
1741         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1742
1743         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1744
1745         u8         dot3stats_symbol_errors_high[0x20];
1746
1747         u8         dot3stats_symbol_errors_low[0x20];
1748
1749         u8         dot3control_in_unknown_opcodes_high[0x20];
1750
1751         u8         dot3control_in_unknown_opcodes_low[0x20];
1752
1753         u8         dot3in_pause_frames_high[0x20];
1754
1755         u8         dot3in_pause_frames_low[0x20];
1756
1757         u8         dot3out_pause_frames_high[0x20];
1758
1759         u8         dot3out_pause_frames_low[0x20];
1760
1761         u8         reserved_at_400[0x3c0];
1762 };
1763
1764 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1765         u8         ether_stats_drop_events_high[0x20];
1766
1767         u8         ether_stats_drop_events_low[0x20];
1768
1769         u8         ether_stats_octets_high[0x20];
1770
1771         u8         ether_stats_octets_low[0x20];
1772
1773         u8         ether_stats_pkts_high[0x20];
1774
1775         u8         ether_stats_pkts_low[0x20];
1776
1777         u8         ether_stats_broadcast_pkts_high[0x20];
1778
1779         u8         ether_stats_broadcast_pkts_low[0x20];
1780
1781         u8         ether_stats_multicast_pkts_high[0x20];
1782
1783         u8         ether_stats_multicast_pkts_low[0x20];
1784
1785         u8         ether_stats_crc_align_errors_high[0x20];
1786
1787         u8         ether_stats_crc_align_errors_low[0x20];
1788
1789         u8         ether_stats_undersize_pkts_high[0x20];
1790
1791         u8         ether_stats_undersize_pkts_low[0x20];
1792
1793         u8         ether_stats_oversize_pkts_high[0x20];
1794
1795         u8         ether_stats_oversize_pkts_low[0x20];
1796
1797         u8         ether_stats_fragments_high[0x20];
1798
1799         u8         ether_stats_fragments_low[0x20];
1800
1801         u8         ether_stats_jabbers_high[0x20];
1802
1803         u8         ether_stats_jabbers_low[0x20];
1804
1805         u8         ether_stats_collisions_high[0x20];
1806
1807         u8         ether_stats_collisions_low[0x20];
1808
1809         u8         ether_stats_pkts64octets_high[0x20];
1810
1811         u8         ether_stats_pkts64octets_low[0x20];
1812
1813         u8         ether_stats_pkts65to127octets_high[0x20];
1814
1815         u8         ether_stats_pkts65to127octets_low[0x20];
1816
1817         u8         ether_stats_pkts128to255octets_high[0x20];
1818
1819         u8         ether_stats_pkts128to255octets_low[0x20];
1820
1821         u8         ether_stats_pkts256to511octets_high[0x20];
1822
1823         u8         ether_stats_pkts256to511octets_low[0x20];
1824
1825         u8         ether_stats_pkts512to1023octets_high[0x20];
1826
1827         u8         ether_stats_pkts512to1023octets_low[0x20];
1828
1829         u8         ether_stats_pkts1024to1518octets_high[0x20];
1830
1831         u8         ether_stats_pkts1024to1518octets_low[0x20];
1832
1833         u8         ether_stats_pkts1519to2047octets_high[0x20];
1834
1835         u8         ether_stats_pkts1519to2047octets_low[0x20];
1836
1837         u8         ether_stats_pkts2048to4095octets_high[0x20];
1838
1839         u8         ether_stats_pkts2048to4095octets_low[0x20];
1840
1841         u8         ether_stats_pkts4096to8191octets_high[0x20];
1842
1843         u8         ether_stats_pkts4096to8191octets_low[0x20];
1844
1845         u8         ether_stats_pkts8192to10239octets_high[0x20];
1846
1847         u8         ether_stats_pkts8192to10239octets_low[0x20];
1848
1849         u8         reserved_at_540[0x280];
1850 };
1851
1852 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1853         u8         if_in_octets_high[0x20];
1854
1855         u8         if_in_octets_low[0x20];
1856
1857         u8         if_in_ucast_pkts_high[0x20];
1858
1859         u8         if_in_ucast_pkts_low[0x20];
1860
1861         u8         if_in_discards_high[0x20];
1862
1863         u8         if_in_discards_low[0x20];
1864
1865         u8         if_in_errors_high[0x20];
1866
1867         u8         if_in_errors_low[0x20];
1868
1869         u8         if_in_unknown_protos_high[0x20];
1870
1871         u8         if_in_unknown_protos_low[0x20];
1872
1873         u8         if_out_octets_high[0x20];
1874
1875         u8         if_out_octets_low[0x20];
1876
1877         u8         if_out_ucast_pkts_high[0x20];
1878
1879         u8         if_out_ucast_pkts_low[0x20];
1880
1881         u8         if_out_discards_high[0x20];
1882
1883         u8         if_out_discards_low[0x20];
1884
1885         u8         if_out_errors_high[0x20];
1886
1887         u8         if_out_errors_low[0x20];
1888
1889         u8         if_in_multicast_pkts_high[0x20];
1890
1891         u8         if_in_multicast_pkts_low[0x20];
1892
1893         u8         if_in_broadcast_pkts_high[0x20];
1894
1895         u8         if_in_broadcast_pkts_low[0x20];
1896
1897         u8         if_out_multicast_pkts_high[0x20];
1898
1899         u8         if_out_multicast_pkts_low[0x20];
1900
1901         u8         if_out_broadcast_pkts_high[0x20];
1902
1903         u8         if_out_broadcast_pkts_low[0x20];
1904
1905         u8         reserved_at_340[0x480];
1906 };
1907
1908 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1909         u8         a_frames_transmitted_ok_high[0x20];
1910
1911         u8         a_frames_transmitted_ok_low[0x20];
1912
1913         u8         a_frames_received_ok_high[0x20];
1914
1915         u8         a_frames_received_ok_low[0x20];
1916
1917         u8         a_frame_check_sequence_errors_high[0x20];
1918
1919         u8         a_frame_check_sequence_errors_low[0x20];
1920
1921         u8         a_alignment_errors_high[0x20];
1922
1923         u8         a_alignment_errors_low[0x20];
1924
1925         u8         a_octets_transmitted_ok_high[0x20];
1926
1927         u8         a_octets_transmitted_ok_low[0x20];
1928
1929         u8         a_octets_received_ok_high[0x20];
1930
1931         u8         a_octets_received_ok_low[0x20];
1932
1933         u8         a_multicast_frames_xmitted_ok_high[0x20];
1934
1935         u8         a_multicast_frames_xmitted_ok_low[0x20];
1936
1937         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1938
1939         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1940
1941         u8         a_multicast_frames_received_ok_high[0x20];
1942
1943         u8         a_multicast_frames_received_ok_low[0x20];
1944
1945         u8         a_broadcast_frames_received_ok_high[0x20];
1946
1947         u8         a_broadcast_frames_received_ok_low[0x20];
1948
1949         u8         a_in_range_length_errors_high[0x20];
1950
1951         u8         a_in_range_length_errors_low[0x20];
1952
1953         u8         a_out_of_range_length_field_high[0x20];
1954
1955         u8         a_out_of_range_length_field_low[0x20];
1956
1957         u8         a_frame_too_long_errors_high[0x20];
1958
1959         u8         a_frame_too_long_errors_low[0x20];
1960
1961         u8         a_symbol_error_during_carrier_high[0x20];
1962
1963         u8         a_symbol_error_during_carrier_low[0x20];
1964
1965         u8         a_mac_control_frames_transmitted_high[0x20];
1966
1967         u8         a_mac_control_frames_transmitted_low[0x20];
1968
1969         u8         a_mac_control_frames_received_high[0x20];
1970
1971         u8         a_mac_control_frames_received_low[0x20];
1972
1973         u8         a_unsupported_opcodes_received_high[0x20];
1974
1975         u8         a_unsupported_opcodes_received_low[0x20];
1976
1977         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1978
1979         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1980
1981         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1982
1983         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1984
1985         u8         reserved_at_4c0[0x300];
1986 };
1987
1988 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1989         u8         life_time_counter_high[0x20];
1990
1991         u8         life_time_counter_low[0x20];
1992
1993         u8         rx_errors[0x20];
1994
1995         u8         tx_errors[0x20];
1996
1997         u8         l0_to_recovery_eieos[0x20];
1998
1999         u8         l0_to_recovery_ts[0x20];
2000
2001         u8         l0_to_recovery_framing[0x20];
2002
2003         u8         l0_to_recovery_retrain[0x20];
2004
2005         u8         crc_error_dllp[0x20];
2006
2007         u8         crc_error_tlp[0x20];
2008
2009         u8         tx_overflow_buffer_pkt_high[0x20];
2010
2011         u8         tx_overflow_buffer_pkt_low[0x20];
2012
2013         u8         outbound_stalled_reads[0x20];
2014
2015         u8         outbound_stalled_writes[0x20];
2016
2017         u8         outbound_stalled_reads_events[0x20];
2018
2019         u8         outbound_stalled_writes_events[0x20];
2020
2021         u8         reserved_at_200[0x5c0];
2022 };
2023
2024 struct mlx5_ifc_cmd_inter_comp_event_bits {
2025         u8         command_completion_vector[0x20];
2026
2027         u8         reserved_at_20[0xc0];
2028 };
2029
2030 struct mlx5_ifc_stall_vl_event_bits {
2031         u8         reserved_at_0[0x18];
2032         u8         port_num[0x1];
2033         u8         reserved_at_19[0x3];
2034         u8         vl[0x4];
2035
2036         u8         reserved_at_20[0xa0];
2037 };
2038
2039 struct mlx5_ifc_db_bf_congestion_event_bits {
2040         u8         event_subtype[0x8];
2041         u8         reserved_at_8[0x8];
2042         u8         congestion_level[0x8];
2043         u8         reserved_at_18[0x8];
2044
2045         u8         reserved_at_20[0xa0];
2046 };
2047
2048 struct mlx5_ifc_gpio_event_bits {
2049         u8         reserved_at_0[0x60];
2050
2051         u8         gpio_event_hi[0x20];
2052
2053         u8         gpio_event_lo[0x20];
2054
2055         u8         reserved_at_a0[0x40];
2056 };
2057
2058 struct mlx5_ifc_port_state_change_event_bits {
2059         u8         reserved_at_0[0x40];
2060
2061         u8         port_num[0x4];
2062         u8         reserved_at_44[0x1c];
2063
2064         u8         reserved_at_60[0x80];
2065 };
2066
2067 struct mlx5_ifc_dropped_packet_logged_bits {
2068         u8         reserved_at_0[0xe0];
2069 };
2070
2071 enum {
2072         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2073         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2074 };
2075
2076 struct mlx5_ifc_cq_error_bits {
2077         u8         reserved_at_0[0x8];
2078         u8         cqn[0x18];
2079
2080         u8         reserved_at_20[0x20];
2081
2082         u8         reserved_at_40[0x18];
2083         u8         syndrome[0x8];
2084
2085         u8         reserved_at_60[0x80];
2086 };
2087
2088 struct mlx5_ifc_rdma_page_fault_event_bits {
2089         u8         bytes_committed[0x20];
2090
2091         u8         r_key[0x20];
2092
2093         u8         reserved_at_40[0x10];
2094         u8         packet_len[0x10];
2095
2096         u8         rdma_op_len[0x20];
2097
2098         u8         rdma_va[0x40];
2099
2100         u8         reserved_at_c0[0x5];
2101         u8         rdma[0x1];
2102         u8         write[0x1];
2103         u8         requestor[0x1];
2104         u8         qp_number[0x18];
2105 };
2106
2107 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2108         u8         bytes_committed[0x20];
2109
2110         u8         reserved_at_20[0x10];
2111         u8         wqe_index[0x10];
2112
2113         u8         reserved_at_40[0x10];
2114         u8         len[0x10];
2115
2116         u8         reserved_at_60[0x60];
2117
2118         u8         reserved_at_c0[0x5];
2119         u8         rdma[0x1];
2120         u8         write_read[0x1];
2121         u8         requestor[0x1];
2122         u8         qpn[0x18];
2123 };
2124
2125 struct mlx5_ifc_qp_events_bits {
2126         u8         reserved_at_0[0xa0];
2127
2128         u8         type[0x8];
2129         u8         reserved_at_a8[0x18];
2130
2131         u8         reserved_at_c0[0x8];
2132         u8         qpn_rqn_sqn[0x18];
2133 };
2134
2135 struct mlx5_ifc_dct_events_bits {
2136         u8         reserved_at_0[0xc0];
2137
2138         u8         reserved_at_c0[0x8];
2139         u8         dct_number[0x18];
2140 };
2141
2142 struct mlx5_ifc_comp_event_bits {
2143         u8         reserved_at_0[0xc0];
2144
2145         u8         reserved_at_c0[0x8];
2146         u8         cq_number[0x18];
2147 };
2148
2149 enum {
2150         MLX5_QPC_STATE_RST        = 0x0,
2151         MLX5_QPC_STATE_INIT       = 0x1,
2152         MLX5_QPC_STATE_RTR        = 0x2,
2153         MLX5_QPC_STATE_RTS        = 0x3,
2154         MLX5_QPC_STATE_SQER       = 0x4,
2155         MLX5_QPC_STATE_ERR        = 0x6,
2156         MLX5_QPC_STATE_SQD        = 0x7,
2157         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2158 };
2159
2160 enum {
2161         MLX5_QPC_ST_RC            = 0x0,
2162         MLX5_QPC_ST_UC            = 0x1,
2163         MLX5_QPC_ST_UD            = 0x2,
2164         MLX5_QPC_ST_XRC           = 0x3,
2165         MLX5_QPC_ST_DCI           = 0x5,
2166         MLX5_QPC_ST_QP0           = 0x7,
2167         MLX5_QPC_ST_QP1           = 0x8,
2168         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2169         MLX5_QPC_ST_REG_UMR       = 0xc,
2170 };
2171
2172 enum {
2173         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2174         MLX5_QPC_PM_STATE_REARM     = 0x1,
2175         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2176         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2177 };
2178
2179 enum {
2180         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2181 };
2182
2183 enum {
2184         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2185         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2186 };
2187
2188 enum {
2189         MLX5_QPC_MTU_256_BYTES        = 0x1,
2190         MLX5_QPC_MTU_512_BYTES        = 0x2,
2191         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2192         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2193         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2194         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2195 };
2196
2197 enum {
2198         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2199         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2200         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2201         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2202         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2203         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2204         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2205         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2206 };
2207
2208 enum {
2209         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2210         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2211         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2212 };
2213
2214 enum {
2215         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2216         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2217         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2218 };
2219
2220 struct mlx5_ifc_qpc_bits {
2221         u8         state[0x4];
2222         u8         lag_tx_port_affinity[0x4];
2223         u8         st[0x8];
2224         u8         reserved_at_10[0x3];
2225         u8         pm_state[0x2];
2226         u8         reserved_at_15[0x3];
2227         u8         offload_type[0x4];
2228         u8         end_padding_mode[0x2];
2229         u8         reserved_at_1e[0x2];
2230
2231         u8         wq_signature[0x1];
2232         u8         block_lb_mc[0x1];
2233         u8         atomic_like_write_en[0x1];
2234         u8         latency_sensitive[0x1];
2235         u8         reserved_at_24[0x1];
2236         u8         drain_sigerr[0x1];
2237         u8         reserved_at_26[0x2];
2238         u8         pd[0x18];
2239
2240         u8         mtu[0x3];
2241         u8         log_msg_max[0x5];
2242         u8         reserved_at_48[0x1];
2243         u8         log_rq_size[0x4];
2244         u8         log_rq_stride[0x3];
2245         u8         no_sq[0x1];
2246         u8         log_sq_size[0x4];
2247         u8         reserved_at_55[0x6];
2248         u8         rlky[0x1];
2249         u8         ulp_stateless_offload_mode[0x4];
2250
2251         u8         counter_set_id[0x8];
2252         u8         uar_page[0x18];
2253
2254         u8         reserved_at_80[0x8];
2255         u8         user_index[0x18];
2256
2257         u8         reserved_at_a0[0x3];
2258         u8         log_page_size[0x5];
2259         u8         remote_qpn[0x18];
2260
2261         struct mlx5_ifc_ads_bits primary_address_path;
2262
2263         struct mlx5_ifc_ads_bits secondary_address_path;
2264
2265         u8         log_ack_req_freq[0x4];
2266         u8         reserved_at_384[0x4];
2267         u8         log_sra_max[0x3];
2268         u8         reserved_at_38b[0x2];
2269         u8         retry_count[0x3];
2270         u8         rnr_retry[0x3];
2271         u8         reserved_at_393[0x1];
2272         u8         fre[0x1];
2273         u8         cur_rnr_retry[0x3];
2274         u8         cur_retry_count[0x3];
2275         u8         reserved_at_39b[0x5];
2276
2277         u8         reserved_at_3a0[0x20];
2278
2279         u8         reserved_at_3c0[0x8];
2280         u8         next_send_psn[0x18];
2281
2282         u8         reserved_at_3e0[0x8];
2283         u8         cqn_snd[0x18];
2284
2285         u8         reserved_at_400[0x8];
2286         u8         deth_sqpn[0x18];
2287
2288         u8         reserved_at_420[0x20];
2289
2290         u8         reserved_at_440[0x8];
2291         u8         last_acked_psn[0x18];
2292
2293         u8         reserved_at_460[0x8];
2294         u8         ssn[0x18];
2295
2296         u8         reserved_at_480[0x8];
2297         u8         log_rra_max[0x3];
2298         u8         reserved_at_48b[0x1];
2299         u8         atomic_mode[0x4];
2300         u8         rre[0x1];
2301         u8         rwe[0x1];
2302         u8         rae[0x1];
2303         u8         reserved_at_493[0x1];
2304         u8         page_offset[0x6];
2305         u8         reserved_at_49a[0x3];
2306         u8         cd_slave_receive[0x1];
2307         u8         cd_slave_send[0x1];
2308         u8         cd_master[0x1];
2309
2310         u8         reserved_at_4a0[0x3];
2311         u8         min_rnr_nak[0x5];
2312         u8         next_rcv_psn[0x18];
2313
2314         u8         reserved_at_4c0[0x8];
2315         u8         xrcd[0x18];
2316
2317         u8         reserved_at_4e0[0x8];
2318         u8         cqn_rcv[0x18];
2319
2320         u8         dbr_addr[0x40];
2321
2322         u8         q_key[0x20];
2323
2324         u8         reserved_at_560[0x5];
2325         u8         rq_type[0x3];
2326         u8         srqn_rmpn_xrqn[0x18];
2327
2328         u8         reserved_at_580[0x8];
2329         u8         rmsn[0x18];
2330
2331         u8         hw_sq_wqebb_counter[0x10];
2332         u8         sw_sq_wqebb_counter[0x10];
2333
2334         u8         hw_rq_counter[0x20];
2335
2336         u8         sw_rq_counter[0x20];
2337
2338         u8         reserved_at_600[0x20];
2339
2340         u8         reserved_at_620[0xf];
2341         u8         cgs[0x1];
2342         u8         cs_req[0x8];
2343         u8         cs_res[0x8];
2344
2345         u8         dc_access_key[0x40];
2346
2347         u8         reserved_at_680[0xc0];
2348 };
2349
2350 struct mlx5_ifc_roce_addr_layout_bits {
2351         u8         source_l3_address[16][0x8];
2352
2353         u8         reserved_at_80[0x3];
2354         u8         vlan_valid[0x1];
2355         u8         vlan_id[0xc];
2356         u8         source_mac_47_32[0x10];
2357
2358         u8         source_mac_31_0[0x20];
2359
2360         u8         reserved_at_c0[0x14];
2361         u8         roce_l3_type[0x4];
2362         u8         roce_version[0x8];
2363
2364         u8         reserved_at_e0[0x20];
2365 };
2366
2367 union mlx5_ifc_hca_cap_union_bits {
2368         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2369         struct mlx5_ifc_odp_cap_bits odp_cap;
2370         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2371         struct mlx5_ifc_roce_cap_bits roce_cap;
2372         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2373         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2374         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2375         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2376         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2377         struct mlx5_ifc_qos_cap_bits qos_cap;
2378         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2379         u8         reserved_at_0[0x8000];
2380 };
2381
2382 enum {
2383         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2384         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2385         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2386         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2387         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2388         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2389         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2390         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2391         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2392         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2393         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2394 };
2395
2396 struct mlx5_ifc_vlan_bits {
2397         u8         ethtype[0x10];
2398         u8         prio[0x3];
2399         u8         cfi[0x1];
2400         u8         vid[0xc];
2401 };
2402
2403 struct mlx5_ifc_flow_context_bits {
2404         struct mlx5_ifc_vlan_bits push_vlan;
2405
2406         u8         group_id[0x20];
2407
2408         u8         reserved_at_40[0x8];
2409         u8         flow_tag[0x18];
2410
2411         u8         reserved_at_60[0x10];
2412         u8         action[0x10];
2413
2414         u8         reserved_at_80[0x8];
2415         u8         destination_list_size[0x18];
2416
2417         u8         reserved_at_a0[0x8];
2418         u8         flow_counter_list_size[0x18];
2419
2420         u8         encap_id[0x20];
2421
2422         u8         modify_header_id[0x20];
2423
2424         struct mlx5_ifc_vlan_bits push_vlan_2;
2425
2426         u8         reserved_at_120[0xe0];
2427
2428         struct mlx5_ifc_fte_match_param_bits match_value;
2429
2430         u8         reserved_at_1200[0x600];
2431
2432         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2433 };
2434
2435 enum {
2436         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2437         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2438 };
2439
2440 struct mlx5_ifc_xrc_srqc_bits {
2441         u8         state[0x4];
2442         u8         log_xrc_srq_size[0x4];
2443         u8         reserved_at_8[0x18];
2444
2445         u8         wq_signature[0x1];
2446         u8         cont_srq[0x1];
2447         u8         reserved_at_22[0x1];
2448         u8         rlky[0x1];
2449         u8         basic_cyclic_rcv_wqe[0x1];
2450         u8         log_rq_stride[0x3];
2451         u8         xrcd[0x18];
2452
2453         u8         page_offset[0x6];
2454         u8         reserved_at_46[0x2];
2455         u8         cqn[0x18];
2456
2457         u8         reserved_at_60[0x20];
2458
2459         u8         user_index_equal_xrc_srqn[0x1];
2460         u8         reserved_at_81[0x1];
2461         u8         log_page_size[0x6];
2462         u8         user_index[0x18];
2463
2464         u8         reserved_at_a0[0x20];
2465
2466         u8         reserved_at_c0[0x8];
2467         u8         pd[0x18];
2468
2469         u8         lwm[0x10];
2470         u8         wqe_cnt[0x10];
2471
2472         u8         reserved_at_100[0x40];
2473
2474         u8         db_record_addr_h[0x20];
2475
2476         u8         db_record_addr_l[0x1e];
2477         u8         reserved_at_17e[0x2];
2478
2479         u8         reserved_at_180[0x80];
2480 };
2481
2482 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2483         u8         counter_error_queues[0x20];
2484
2485         u8         total_error_queues[0x20];
2486
2487         u8         send_queue_priority_update_flow[0x20];
2488
2489         u8         reserved_at_60[0x20];
2490
2491         u8         nic_receive_steering_discard[0x40];
2492
2493         u8         receive_discard_vport_down[0x40];
2494
2495         u8         transmit_discard_vport_down[0x40];
2496
2497         u8         reserved_at_140[0xec0];
2498 };
2499
2500 struct mlx5_ifc_traffic_counter_bits {
2501         u8         packets[0x40];
2502
2503         u8         octets[0x40];
2504 };
2505
2506 struct mlx5_ifc_tisc_bits {
2507         u8         strict_lag_tx_port_affinity[0x1];
2508         u8         reserved_at_1[0x3];
2509         u8         lag_tx_port_affinity[0x04];
2510
2511         u8         reserved_at_8[0x4];
2512         u8         prio[0x4];
2513         u8         reserved_at_10[0x10];
2514
2515         u8         reserved_at_20[0x100];
2516
2517         u8         reserved_at_120[0x8];
2518         u8         transport_domain[0x18];
2519
2520         u8         reserved_at_140[0x8];
2521         u8         underlay_qpn[0x18];
2522         u8         reserved_at_160[0x3a0];
2523 };
2524
2525 enum {
2526         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2527         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2528 };
2529
2530 enum {
2531         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2532         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2533 };
2534
2535 enum {
2536         MLX5_RX_HASH_FN_NONE           = 0x0,
2537         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2538         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2539 };
2540
2541 enum {
2542         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2543         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2544 };
2545
2546 struct mlx5_ifc_tirc_bits {
2547         u8         reserved_at_0[0x20];
2548
2549         u8         disp_type[0x4];
2550         u8         reserved_at_24[0x1c];
2551
2552         u8         reserved_at_40[0x40];
2553
2554         u8         reserved_at_80[0x4];
2555         u8         lro_timeout_period_usecs[0x10];
2556         u8         lro_enable_mask[0x4];
2557         u8         lro_max_ip_payload_size[0x8];
2558
2559         u8         reserved_at_a0[0x40];
2560
2561         u8         reserved_at_e0[0x8];
2562         u8         inline_rqn[0x18];
2563
2564         u8         rx_hash_symmetric[0x1];
2565         u8         reserved_at_101[0x1];
2566         u8         tunneled_offload_en[0x1];
2567         u8         reserved_at_103[0x5];
2568         u8         indirect_table[0x18];
2569
2570         u8         rx_hash_fn[0x4];
2571         u8         reserved_at_124[0x2];
2572         u8         self_lb_block[0x2];
2573         u8         transport_domain[0x18];
2574
2575         u8         rx_hash_toeplitz_key[10][0x20];
2576
2577         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2578
2579         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2580
2581         u8         reserved_at_2c0[0x4c0];
2582 };
2583
2584 enum {
2585         MLX5_SRQC_STATE_GOOD   = 0x0,
2586         MLX5_SRQC_STATE_ERROR  = 0x1,
2587 };
2588
2589 struct mlx5_ifc_srqc_bits {
2590         u8         state[0x4];
2591         u8         log_srq_size[0x4];
2592         u8         reserved_at_8[0x18];
2593
2594         u8         wq_signature[0x1];
2595         u8         cont_srq[0x1];
2596         u8         reserved_at_22[0x1];
2597         u8         rlky[0x1];
2598         u8         reserved_at_24[0x1];
2599         u8         log_rq_stride[0x3];
2600         u8         xrcd[0x18];
2601
2602         u8         page_offset[0x6];
2603         u8         reserved_at_46[0x2];
2604         u8         cqn[0x18];
2605
2606         u8         reserved_at_60[0x20];
2607
2608         u8         reserved_at_80[0x2];
2609         u8         log_page_size[0x6];
2610         u8         reserved_at_88[0x18];
2611
2612         u8         reserved_at_a0[0x20];
2613
2614         u8         reserved_at_c0[0x8];
2615         u8         pd[0x18];
2616
2617         u8         lwm[0x10];
2618         u8         wqe_cnt[0x10];
2619
2620         u8         reserved_at_100[0x40];
2621
2622         u8         dbr_addr[0x40];
2623
2624         u8         reserved_at_180[0x80];
2625 };
2626
2627 enum {
2628         MLX5_SQC_STATE_RST  = 0x0,
2629         MLX5_SQC_STATE_RDY  = 0x1,
2630         MLX5_SQC_STATE_ERR  = 0x3,
2631 };
2632
2633 struct mlx5_ifc_sqc_bits {
2634         u8         rlky[0x1];
2635         u8         cd_master[0x1];
2636         u8         fre[0x1];
2637         u8         flush_in_error_en[0x1];
2638         u8         allow_multi_pkt_send_wqe[0x1];
2639         u8         min_wqe_inline_mode[0x3];
2640         u8         state[0x4];
2641         u8         reg_umr[0x1];
2642         u8         allow_swp[0x1];
2643         u8         hairpin[0x1];
2644         u8         reserved_at_f[0x11];
2645
2646         u8         reserved_at_20[0x8];
2647         u8         user_index[0x18];
2648
2649         u8         reserved_at_40[0x8];
2650         u8         cqn[0x18];
2651
2652         u8         reserved_at_60[0x8];
2653         u8         hairpin_peer_rq[0x18];
2654
2655         u8         reserved_at_80[0x10];
2656         u8         hairpin_peer_vhca[0x10];
2657
2658         u8         reserved_at_a0[0x50];
2659
2660         u8         packet_pacing_rate_limit_index[0x10];
2661         u8         tis_lst_sz[0x10];
2662         u8         reserved_at_110[0x10];
2663
2664         u8         reserved_at_120[0x40];
2665
2666         u8         reserved_at_160[0x8];
2667         u8         tis_num_0[0x18];
2668
2669         struct mlx5_ifc_wq_bits wq;
2670 };
2671
2672 enum {
2673         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2674         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2675         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2676         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2677 };
2678
2679 struct mlx5_ifc_scheduling_context_bits {
2680         u8         element_type[0x8];
2681         u8         reserved_at_8[0x18];
2682
2683         u8         element_attributes[0x20];
2684
2685         u8         parent_element_id[0x20];
2686
2687         u8         reserved_at_60[0x40];
2688
2689         u8         bw_share[0x20];
2690
2691         u8         max_average_bw[0x20];
2692
2693         u8         reserved_at_e0[0x120];
2694 };
2695
2696 struct mlx5_ifc_rqtc_bits {
2697         u8         reserved_at_0[0xa0];
2698
2699         u8         reserved_at_a0[0x10];
2700         u8         rqt_max_size[0x10];
2701
2702         u8         reserved_at_c0[0x10];
2703         u8         rqt_actual_size[0x10];
2704
2705         u8         reserved_at_e0[0x6a0];
2706
2707         struct mlx5_ifc_rq_num_bits rq_num[0];
2708 };
2709
2710 enum {
2711         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2712         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2713 };
2714
2715 enum {
2716         MLX5_RQC_STATE_RST  = 0x0,
2717         MLX5_RQC_STATE_RDY  = 0x1,
2718         MLX5_RQC_STATE_ERR  = 0x3,
2719 };
2720
2721 struct mlx5_ifc_rqc_bits {
2722         u8         rlky[0x1];
2723         u8         delay_drop_en[0x1];
2724         u8         scatter_fcs[0x1];
2725         u8         vsd[0x1];
2726         u8         mem_rq_type[0x4];
2727         u8         state[0x4];
2728         u8         reserved_at_c[0x1];
2729         u8         flush_in_error_en[0x1];
2730         u8         hairpin[0x1];
2731         u8         reserved_at_f[0x11];
2732
2733         u8         reserved_at_20[0x8];
2734         u8         user_index[0x18];
2735
2736         u8         reserved_at_40[0x8];
2737         u8         cqn[0x18];
2738
2739         u8         counter_set_id[0x8];
2740         u8         reserved_at_68[0x18];
2741
2742         u8         reserved_at_80[0x8];
2743         u8         rmpn[0x18];
2744
2745         u8         reserved_at_a0[0x8];
2746         u8         hairpin_peer_sq[0x18];
2747
2748         u8         reserved_at_c0[0x10];
2749         u8         hairpin_peer_vhca[0x10];
2750
2751         u8         reserved_at_e0[0xa0];
2752
2753         struct mlx5_ifc_wq_bits wq;
2754 };
2755
2756 enum {
2757         MLX5_RMPC_STATE_RDY  = 0x1,
2758         MLX5_RMPC_STATE_ERR  = 0x3,
2759 };
2760
2761 struct mlx5_ifc_rmpc_bits {
2762         u8         reserved_at_0[0x8];
2763         u8         state[0x4];
2764         u8         reserved_at_c[0x14];
2765
2766         u8         basic_cyclic_rcv_wqe[0x1];
2767         u8         reserved_at_21[0x1f];
2768
2769         u8         reserved_at_40[0x140];
2770
2771         struct mlx5_ifc_wq_bits wq;
2772 };
2773
2774 struct mlx5_ifc_nic_vport_context_bits {
2775         u8         reserved_at_0[0x5];
2776         u8         min_wqe_inline_mode[0x3];
2777         u8         reserved_at_8[0x15];
2778         u8         disable_mc_local_lb[0x1];
2779         u8         disable_uc_local_lb[0x1];
2780         u8         roce_en[0x1];
2781
2782         u8         arm_change_event[0x1];
2783         u8         reserved_at_21[0x1a];
2784         u8         event_on_mtu[0x1];
2785         u8         event_on_promisc_change[0x1];
2786         u8         event_on_vlan_change[0x1];
2787         u8         event_on_mc_address_change[0x1];
2788         u8         event_on_uc_address_change[0x1];
2789
2790         u8         reserved_at_40[0xc];
2791
2792         u8         affiliation_criteria[0x4];
2793         u8         affiliated_vhca_id[0x10];
2794
2795         u8         reserved_at_60[0xd0];
2796
2797         u8         mtu[0x10];
2798
2799         u8         system_image_guid[0x40];
2800         u8         port_guid[0x40];
2801         u8         node_guid[0x40];
2802
2803         u8         reserved_at_200[0x140];
2804         u8         qkey_violation_counter[0x10];
2805         u8         reserved_at_350[0x430];
2806
2807         u8         promisc_uc[0x1];
2808         u8         promisc_mc[0x1];
2809         u8         promisc_all[0x1];
2810         u8         reserved_at_783[0x2];
2811         u8         allowed_list_type[0x3];
2812         u8         reserved_at_788[0xc];
2813         u8         allowed_list_size[0xc];
2814
2815         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2816
2817         u8         reserved_at_7e0[0x20];
2818
2819         u8         current_uc_mac_address[0][0x40];
2820 };
2821
2822 enum {
2823         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2824         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2825         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2826         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2827         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2828 };
2829
2830 struct mlx5_ifc_mkc_bits {
2831         u8         reserved_at_0[0x1];
2832         u8         free[0x1];
2833         u8         reserved_at_2[0x1];
2834         u8         access_mode_4_2[0x3];
2835         u8         reserved_at_6[0x7];
2836         u8         relaxed_ordering_write[0x1];
2837         u8         reserved_at_e[0x1];
2838         u8         small_fence_on_rdma_read_response[0x1];
2839         u8         umr_en[0x1];
2840         u8         a[0x1];
2841         u8         rw[0x1];
2842         u8         rr[0x1];
2843         u8         lw[0x1];
2844         u8         lr[0x1];
2845         u8         access_mode_1_0[0x2];
2846         u8         reserved_at_18[0x8];
2847
2848         u8         qpn[0x18];
2849         u8         mkey_7_0[0x8];
2850
2851         u8         reserved_at_40[0x20];
2852
2853         u8         length64[0x1];
2854         u8         bsf_en[0x1];
2855         u8         sync_umr[0x1];
2856         u8         reserved_at_63[0x2];
2857         u8         expected_sigerr_count[0x1];
2858         u8         reserved_at_66[0x1];
2859         u8         en_rinval[0x1];
2860         u8         pd[0x18];
2861
2862         u8         start_addr[0x40];
2863
2864         u8         len[0x40];
2865
2866         u8         bsf_octword_size[0x20];
2867
2868         u8         reserved_at_120[0x80];
2869
2870         u8         translations_octword_size[0x20];
2871
2872         u8         reserved_at_1c0[0x1b];
2873         u8         log_page_size[0x5];
2874
2875         u8         reserved_at_1e0[0x20];
2876 };
2877
2878 struct mlx5_ifc_pkey_bits {
2879         u8         reserved_at_0[0x10];
2880         u8         pkey[0x10];
2881 };
2882
2883 struct mlx5_ifc_array128_auto_bits {
2884         u8         array128_auto[16][0x8];
2885 };
2886
2887 struct mlx5_ifc_hca_vport_context_bits {
2888         u8         field_select[0x20];
2889
2890         u8         reserved_at_20[0xe0];
2891
2892         u8         sm_virt_aware[0x1];
2893         u8         has_smi[0x1];
2894         u8         has_raw[0x1];
2895         u8         grh_required[0x1];
2896         u8         reserved_at_104[0xc];
2897         u8         port_physical_state[0x4];
2898         u8         vport_state_policy[0x4];
2899         u8         port_state[0x4];
2900         u8         vport_state[0x4];
2901
2902         u8         reserved_at_120[0x20];
2903
2904         u8         system_image_guid[0x40];
2905
2906         u8         port_guid[0x40];
2907
2908         u8         node_guid[0x40];
2909
2910         u8         cap_mask1[0x20];
2911
2912         u8         cap_mask1_field_select[0x20];
2913
2914         u8         cap_mask2[0x20];
2915
2916         u8         cap_mask2_field_select[0x20];
2917
2918         u8         reserved_at_280[0x80];
2919
2920         u8         lid[0x10];
2921         u8         reserved_at_310[0x4];
2922         u8         init_type_reply[0x4];
2923         u8         lmc[0x3];
2924         u8         subnet_timeout[0x5];
2925
2926         u8         sm_lid[0x10];
2927         u8         sm_sl[0x4];
2928         u8         reserved_at_334[0xc];
2929
2930         u8         qkey_violation_counter[0x10];
2931         u8         pkey_violation_counter[0x10];
2932
2933         u8         reserved_at_360[0xca0];
2934 };
2935
2936 struct mlx5_ifc_esw_vport_context_bits {
2937         u8         reserved_at_0[0x3];
2938         u8         vport_svlan_strip[0x1];
2939         u8         vport_cvlan_strip[0x1];
2940         u8         vport_svlan_insert[0x1];
2941         u8         vport_cvlan_insert[0x2];
2942         u8         reserved_at_8[0x18];
2943
2944         u8         reserved_at_20[0x20];
2945
2946         u8         svlan_cfi[0x1];
2947         u8         svlan_pcp[0x3];
2948         u8         svlan_id[0xc];
2949         u8         cvlan_cfi[0x1];
2950         u8         cvlan_pcp[0x3];
2951         u8         cvlan_id[0xc];
2952
2953         u8         reserved_at_60[0x7a0];
2954 };
2955
2956 enum {
2957         MLX5_EQC_STATUS_OK                = 0x0,
2958         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2959 };
2960
2961 enum {
2962         MLX5_EQC_ST_ARMED  = 0x9,
2963         MLX5_EQC_ST_FIRED  = 0xa,
2964 };
2965
2966 struct mlx5_ifc_eqc_bits {
2967         u8         status[0x4];
2968         u8         reserved_at_4[0x9];
2969         u8         ec[0x1];
2970         u8         oi[0x1];
2971         u8         reserved_at_f[0x5];
2972         u8         st[0x4];
2973         u8         reserved_at_18[0x8];
2974
2975         u8         reserved_at_20[0x20];
2976
2977         u8         reserved_at_40[0x14];
2978         u8         page_offset[0x6];
2979         u8         reserved_at_5a[0x6];
2980
2981         u8         reserved_at_60[0x3];
2982         u8         log_eq_size[0x5];
2983         u8         uar_page[0x18];
2984
2985         u8         reserved_at_80[0x20];
2986
2987         u8         reserved_at_a0[0x18];
2988         u8         intr[0x8];
2989
2990         u8         reserved_at_c0[0x3];
2991         u8         log_page_size[0x5];
2992         u8         reserved_at_c8[0x18];
2993
2994         u8         reserved_at_e0[0x60];
2995
2996         u8         reserved_at_140[0x8];
2997         u8         consumer_counter[0x18];
2998
2999         u8         reserved_at_160[0x8];
3000         u8         producer_counter[0x18];
3001
3002         u8         reserved_at_180[0x80];
3003 };
3004
3005 enum {
3006         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3007         MLX5_DCTC_STATE_DRAINING  = 0x1,
3008         MLX5_DCTC_STATE_DRAINED   = 0x2,
3009 };
3010
3011 enum {
3012         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3013         MLX5_DCTC_CS_RES_NA         = 0x1,
3014         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3015 };
3016
3017 enum {
3018         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3019         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3020         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3021         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3022         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3023 };
3024
3025 struct mlx5_ifc_dctc_bits {
3026         u8         reserved_at_0[0x4];
3027         u8         state[0x4];
3028         u8         reserved_at_8[0x18];
3029
3030         u8         reserved_at_20[0x8];
3031         u8         user_index[0x18];
3032
3033         u8         reserved_at_40[0x8];
3034         u8         cqn[0x18];
3035
3036         u8         counter_set_id[0x8];
3037         u8         atomic_mode[0x4];
3038         u8         rre[0x1];
3039         u8         rwe[0x1];
3040         u8         rae[0x1];
3041         u8         atomic_like_write_en[0x1];
3042         u8         latency_sensitive[0x1];
3043         u8         rlky[0x1];
3044         u8         free_ar[0x1];
3045         u8         reserved_at_73[0xd];
3046
3047         u8         reserved_at_80[0x8];
3048         u8         cs_res[0x8];
3049         u8         reserved_at_90[0x3];
3050         u8         min_rnr_nak[0x5];
3051         u8         reserved_at_98[0x8];
3052
3053         u8         reserved_at_a0[0x8];
3054         u8         srqn_xrqn[0x18];
3055
3056         u8         reserved_at_c0[0x8];
3057         u8         pd[0x18];
3058
3059         u8         tclass[0x8];
3060         u8         reserved_at_e8[0x4];
3061         u8         flow_label[0x14];
3062
3063         u8         dc_access_key[0x40];
3064
3065         u8         reserved_at_140[0x5];
3066         u8         mtu[0x3];
3067         u8         port[0x8];
3068         u8         pkey_index[0x10];
3069
3070         u8         reserved_at_160[0x8];
3071         u8         my_addr_index[0x8];
3072         u8         reserved_at_170[0x8];
3073         u8         hop_limit[0x8];
3074
3075         u8         dc_access_key_violation_count[0x20];
3076
3077         u8         reserved_at_1a0[0x14];
3078         u8         dei_cfi[0x1];
3079         u8         eth_prio[0x3];
3080         u8         ecn[0x2];
3081         u8         dscp[0x6];
3082
3083         u8         reserved_at_1c0[0x40];
3084 };
3085
3086 enum {
3087         MLX5_CQC_STATUS_OK             = 0x0,
3088         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3089         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3090 };
3091
3092 enum {
3093         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3094         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3095 };
3096
3097 enum {
3098         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3099         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3100         MLX5_CQC_ST_FIRED                                 = 0xa,
3101 };
3102
3103 enum {
3104         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3105         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3106         MLX5_CQ_PERIOD_NUM_MODES
3107 };
3108
3109 struct mlx5_ifc_cqc_bits {
3110         u8         status[0x4];
3111         u8         reserved_at_4[0x4];
3112         u8         cqe_sz[0x3];
3113         u8         cc[0x1];
3114         u8         reserved_at_c[0x1];
3115         u8         scqe_break_moderation_en[0x1];
3116         u8         oi[0x1];
3117         u8         cq_period_mode[0x2];
3118         u8         cqe_comp_en[0x1];
3119         u8         mini_cqe_res_format[0x2];
3120         u8         st[0x4];
3121         u8         reserved_at_18[0x8];
3122
3123         u8         reserved_at_20[0x20];
3124
3125         u8         reserved_at_40[0x14];
3126         u8         page_offset[0x6];
3127         u8         reserved_at_5a[0x6];
3128
3129         u8         reserved_at_60[0x3];
3130         u8         log_cq_size[0x5];
3131         u8         uar_page[0x18];
3132
3133         u8         reserved_at_80[0x4];
3134         u8         cq_period[0xc];
3135         u8         cq_max_count[0x10];
3136
3137         u8         reserved_at_a0[0x18];
3138         u8         c_eqn[0x8];
3139
3140         u8         reserved_at_c0[0x3];
3141         u8         log_page_size[0x5];
3142         u8         reserved_at_c8[0x18];
3143
3144         u8         reserved_at_e0[0x20];
3145
3146         u8         reserved_at_100[0x8];
3147         u8         last_notified_index[0x18];
3148
3149         u8         reserved_at_120[0x8];
3150         u8         last_solicit_index[0x18];
3151
3152         u8         reserved_at_140[0x8];
3153         u8         consumer_counter[0x18];
3154
3155         u8         reserved_at_160[0x8];
3156         u8         producer_counter[0x18];
3157
3158         u8         reserved_at_180[0x40];
3159
3160         u8         dbr_addr[0x40];
3161 };
3162
3163 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3164         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3165         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3166         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3167         u8         reserved_at_0[0x800];
3168 };
3169
3170 struct mlx5_ifc_query_adapter_param_block_bits {
3171         u8         reserved_at_0[0xc0];
3172
3173         u8         reserved_at_c0[0x8];
3174         u8         ieee_vendor_id[0x18];
3175
3176         u8         reserved_at_e0[0x10];
3177         u8         vsd_vendor_id[0x10];
3178
3179         u8         vsd[208][0x8];
3180
3181         u8         vsd_contd_psid[16][0x8];
3182 };
3183
3184 enum {
3185         MLX5_XRQC_STATE_GOOD   = 0x0,
3186         MLX5_XRQC_STATE_ERROR  = 0x1,
3187 };
3188
3189 enum {
3190         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3191         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3192 };
3193
3194 enum {
3195         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3196 };
3197
3198 struct mlx5_ifc_tag_matching_topology_context_bits {
3199         u8         log_matching_list_sz[0x4];
3200         u8         reserved_at_4[0xc];
3201         u8         append_next_index[0x10];
3202
3203         u8         sw_phase_cnt[0x10];
3204         u8         hw_phase_cnt[0x10];
3205
3206         u8         reserved_at_40[0x40];
3207 };
3208
3209 struct mlx5_ifc_xrqc_bits {
3210         u8         state[0x4];
3211         u8         rlkey[0x1];
3212         u8         reserved_at_5[0xf];
3213         u8         topology[0x4];
3214         u8         reserved_at_18[0x4];
3215         u8         offload[0x4];
3216
3217         u8         reserved_at_20[0x8];
3218         u8         user_index[0x18];
3219
3220         u8         reserved_at_40[0x8];
3221         u8         cqn[0x18];
3222
3223         u8         reserved_at_60[0xa0];
3224
3225         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3226
3227         u8         reserved_at_180[0x280];
3228
3229         struct mlx5_ifc_wq_bits wq;
3230 };
3231
3232 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3233         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3234         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3235         u8         reserved_at_0[0x20];
3236 };
3237
3238 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3239         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3240         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3241         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3242         u8         reserved_at_0[0x20];
3243 };
3244
3245 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3246         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3247         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3248         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3249         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3250         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3251         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3252         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3253         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib