include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         reserved_at_4[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         vlan_tag[0x1];
 369         u8         reserved_at_91[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_vlan_tag[0x1];
 402         u8         inner_second_vlan_tag[0x1];
 403         u8         reserved_at_62[0xe];
 404         u8         gre_protocol[0x10];
 405
 406         u8         gre_key_h[0x18];
 407         u8         gre_key_l[0x8];
 408
 409         u8         vxlan_vni[0x18];
 410         u8         reserved_at_b8[0x8];
 411
 412         u8         reserved_at_c0[0x20];
 413
 414         u8         reserved_at_e0[0xc];
 415         u8         outer_ipv6_flow_label[0x14];
 416
 417         u8         reserved_at_100[0xc];
 418         u8         inner_ipv6_flow_label[0x14];
 419
 420         u8         reserved_at_120[0xe0];
 421 };
 422
 423 struct mlx5_ifc_cmd_pas_bits {
 424         u8         pa_h[0x20];
 425
 426         u8         pa_l[0x14];
 427         u8         reserved_at_34[0xc];
 428 };
 429
 430 struct mlx5_ifc_uint64_bits {
 431         u8         hi[0x20];
 432
 433         u8         lo[0x20];
 434 };
 435
 436 enum {
 437         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 438         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 439         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 440         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 441         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 442         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 443         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 444         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 445         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 446         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 447 };
 448
 449 struct mlx5_ifc_ads_bits {
 450         u8         fl[0x1];
 451         u8         free_ar[0x1];
 452         u8         reserved_at_2[0xe];
 453         u8         pkey_index[0x10];
 454
 455         u8         reserved_at_20[0x8];
 456         u8         grh[0x1];
 457         u8         mlid[0x7];
 458         u8         rlid[0x10];
 459
 460         u8         ack_timeout[0x5];
 461         u8         reserved_at_45[0x3];
 462         u8         src_addr_index[0x8];
 463         u8         reserved_at_50[0x4];
 464         u8         stat_rate[0x4];
 465         u8         hop_limit[0x8];
 466
 467         u8         reserved_at_60[0x4];
 468         u8         tclass[0x8];
 469         u8         flow_label[0x14];
 470
 471         u8         rgid_rip[16][0x8];
 472
 473         u8         reserved_at_100[0x4];
 474         u8         f_dscp[0x1];
 475         u8         f_ecn[0x1];
 476         u8         reserved_at_106[0x1];
 477         u8         f_eth_prio[0x1];
 478         u8         ecn[0x2];
 479         u8         dscp[0x6];
 480         u8         udp_sport[0x10];
 481
 482         u8         dei_cfi[0x1];
 483         u8         eth_prio[0x3];
 484         u8         sl[0x4];
 485         u8         port[0x8];
 486         u8         rmac_47_32[0x10];
 487
 488         u8         rmac_31_0[0x20];
 489 };
 490
 491 struct mlx5_ifc_flow_table_nic_cap_bits {
 492         u8         nic_rx_multi_path_tirs[0x1];
 493         u8         nic_rx_multi_path_tirs_fts[0x1];
 494         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 495         u8         reserved_at_3[0x1fd];
 496
 497         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 498
 499         u8         reserved_at_400[0x200];
 500
 501         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 504
 505         u8         reserved_at_a00[0x200];
 506
 507         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 508
 509         u8         reserved_at_e00[0x7200];
 510 };
 511
 512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 513         u8     reserved_at_0[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 520
 521         u8      reserved_at_800[0x7800];
 522 };
 523
 524 struct mlx5_ifc_e_switch_cap_bits {
 525         u8         vport_svlan_strip[0x1];
 526         u8         vport_cvlan_strip[0x1];
 527         u8         vport_svlan_insert[0x1];
 528         u8         vport_cvlan_insert_if_not_exist[0x1];
 529         u8         vport_cvlan_insert_overwrite[0x1];
 530         u8         reserved_at_5[0x19];
 531         u8         nic_vport_node_guid_modify[0x1];
 532         u8         nic_vport_port_guid_modify[0x1];
 533
 534         u8         vxlan_encap_decap[0x1];
 535         u8         nvgre_encap_decap[0x1];
 536         u8         reserved_at_22[0x9];
 537         u8         log_max_encap_headers[0x5];
 538         u8         reserved_2b[0x6];
 539         u8         max_encap_header_size[0xa];
 540
 541         u8         reserved_40[0x7c0];
 542
 543 };
 544
 545 struct mlx5_ifc_qos_cap_bits {
 546         u8         packet_pacing[0x1];
 547         u8         esw_scheduling[0x1];
 548         u8         reserved_at_2[0x1e];
 549
 550         u8         reserved_at_20[0x20];
 551
 552         u8         packet_pacing_max_rate[0x20];
 553
 554         u8         packet_pacing_min_rate[0x20];
 555
 556         u8         reserved_at_80[0x10];
 557         u8         packet_pacing_rate_table_size[0x10];
 558
 559         u8         esw_element_type[0x10];
 560         u8         esw_tsar_type[0x10];
 561
 562         u8         reserved_at_c0[0x10];
 563         u8         max_qos_para_vport[0x10];
 564
 565         u8         max_tsar_bw_share[0x20];
 566
 567         u8         reserved_at_100[0x700];
 568 };
 569
 570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 571         u8         csum_cap[0x1];
 572         u8         vlan_cap[0x1];
 573         u8         lro_cap[0x1];
 574         u8         lro_psh_flag[0x1];
 575         u8         lro_time_stamp[0x1];
 576         u8         reserved_at_5[0x3];
 577         u8         self_lb_en_modifiable[0x1];
 578         u8         reserved_at_9[0x2];
 579         u8         max_lso_cap[0x5];
 580         u8         multi_pkt_send_wqe[0x2];
 581         u8         wqe_inline_mode[0x2];
 582         u8         rss_ind_tbl_cap[0x4];
 583         u8         reg_umr_sq[0x1];
 584         u8         scatter_fcs[0x1];
 585         u8         reserved_at_1a[0x1];
 586         u8         tunnel_lso_const_out_ip_id[0x1];
 587         u8         reserved_at_1c[0x2];
 588         u8         tunnel_statless_gre[0x1];
 589         u8         tunnel_stateless_vxlan[0x1];
 590
 591         u8         reserved_at_20[0x20];
 592
 593         u8         reserved_at_40[0x10];
 594         u8         lro_min_mss_size[0x10];
 595
 596         u8         reserved_at_60[0x120];
 597
 598         u8         lro_timer_supported_periods[4][0x20];
 599
 600         u8         reserved_at_200[0x600];
 601 };
 602
 603 struct mlx5_ifc_roce_cap_bits {
 604         u8         roce_apm[0x1];
 605         u8         reserved_at_1[0x1f];
 606
 607         u8         reserved_at_20[0x60];
 608
 609         u8         reserved_at_80[0xc];
 610         u8         l3_type[0x4];
 611         u8         reserved_at_90[0x8];
 612         u8         roce_version[0x8];
 613
 614         u8         reserved_at_a0[0x10];
 615         u8         r_roce_dest_udp_port[0x10];
 616
 617         u8         r_roce_max_src_udp_port[0x10];
 618         u8         r_roce_min_src_udp_port[0x10];
 619
 620         u8         reserved_at_e0[0x10];
 621         u8         roce_address_table_size[0x10];
 622
 623         u8         reserved_at_100[0x700];
 624 };
 625
 626 enum {
 627         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 628         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 636 };
 637
 638 enum {
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 648 };
 649
 650 struct mlx5_ifc_atomic_caps_bits {
 651         u8         reserved_at_0[0x40];
 652
 653         u8         atomic_req_8B_endianess_mode[0x2];
 654         u8         reserved_at_42[0x4];
 655         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 656
 657         u8         reserved_at_47[0x19];
 658
 659         u8         reserved_at_60[0x20];
 660
 661         u8         reserved_at_80[0x10];
 662         u8         atomic_operations[0x10];
 663
 664         u8         reserved_at_a0[0x10];
 665         u8         atomic_size_qp[0x10];
 666
 667         u8         reserved_at_c0[0x10];
 668         u8         atomic_size_dc[0x10];
 669
 670         u8         reserved_at_e0[0x720];
 671 };
 672
 673 struct mlx5_ifc_odp_cap_bits {
 674         u8         reserved_at_0[0x40];
 675
 676         u8         sig[0x1];
 677         u8         reserved_at_41[0x1f];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 682
 683         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 686
 687         u8         reserved_at_e0[0x720];
 688 };
 689
 690 struct mlx5_ifc_calc_op {
 691         u8        reserved_at_0[0x10];
 692         u8        reserved_at_10[0x9];
 693         u8        op_swap_endianness[0x1];
 694         u8        op_min[0x1];
 695         u8        op_xor[0x1];
 696         u8        op_or[0x1];
 697         u8        op_and[0x1];
 698         u8        op_max[0x1];
 699         u8        op_add[0x1];
 700 };
 701
 702 struct mlx5_ifc_vector_calc_cap_bits {
 703         u8         calc_matrix[0x1];
 704         u8         reserved_at_1[0x1f];
 705         u8         reserved_at_20[0x8];
 706         u8         max_vec_count[0x8];
 707         u8         reserved_at_30[0xd];
 708         u8         max_chunk_size[0x3];
 709         struct mlx5_ifc_calc_op calc0;
 710         struct mlx5_ifc_calc_op calc1;
 711         struct mlx5_ifc_calc_op calc2;
 712         struct mlx5_ifc_calc_op calc3;
 713
 714         u8         reserved_at_e0[0x720];
 715 };
 716
 717 enum {
 718         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 719         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 720         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 721 };
 722
 723 enum {
 724         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 725         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 726 };
 727
 728 enum {
 729         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 730         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 734 };
 735
 736 enum {
 737         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 738         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 743 };
 744
 745 enum {
 746         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 747         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 748 };
 749
 750 enum {
 751         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 752         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 754 };
 755
 756 enum {
 757         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 758         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 759 };
 760
 761 struct mlx5_ifc_cmd_hca_cap_bits {
 762         u8         reserved_at_0[0x80];
 763
 764         u8         log_max_srq_sz[0x8];
 765         u8         log_max_qp_sz[0x8];
 766         u8         reserved_at_90[0xb];
 767         u8         log_max_qp[0x5];
 768
 769         u8         reserved_at_a0[0xb];
 770         u8         log_max_srq[0x5];
 771         u8         reserved_at_b0[0x10];
 772
 773         u8         reserved_at_c0[0x8];
 774         u8         log_max_cq_sz[0x8];
 775         u8         reserved_at_d0[0xb];
 776         u8         log_max_cq[0x5];
 777
 778         u8         log_max_eq_sz[0x8];
 779         u8         reserved_at_e8[0x2];
 780         u8         log_max_mkey[0x6];
 781         u8         reserved_at_f0[0xc];
 782         u8         log_max_eq[0x4];
 783
 784         u8         max_indirection[0x8];
 785         u8         reserved_at_108[0x1];
 786         u8         log_max_mrw_sz[0x7];
 787         u8         reserved_at_110[0x2];
 788         u8         log_max_bsf_list_size[0x6];
 789         u8         reserved_at_118[0x2];
 790         u8         log_max_klm_list_size[0x6];
 791
 792         u8         reserved_at_120[0xa];
 793         u8         log_max_ra_req_dc[0x6];
 794         u8         reserved_at_130[0xa];
 795         u8         log_max_ra_res_dc[0x6];
 796
 797         u8         reserved_at_140[0xa];
 798         u8         log_max_ra_req_qp[0x6];
 799         u8         reserved_at_150[0xa];
 800         u8         log_max_ra_res_qp[0x6];
 801
 802         u8         pad_cap[0x1];
 803         u8         cc_query_allowed[0x1];
 804         u8         cc_modify_allowed[0x1];
 805         u8         reserved_at_163[0xd];
 806         u8         gid_table_size[0x10];
 807
 808         u8         out_of_seq_cnt[0x1];
 809         u8         vport_counters[0x1];
 810         u8         retransmission_q_counters[0x1];
 811         u8         reserved_at_183[0x1];
 812         u8         modify_rq_counter_set_id[0x1];
 813         u8         reserved_at_185[0x1];
 814         u8         max_qp_cnt[0xa];
 815         u8         pkey_table_size[0x10];
 816
 817         u8         vport_group_manager[0x1];
 818         u8         vhca_group_manager[0x1];
 819         u8         ib_virt[0x1];
 820         u8         eth_virt[0x1];
 821         u8         reserved_at_1a4[0x1];
 822         u8         ets[0x1];
 823         u8         nic_flow_table[0x1];
 824         u8         eswitch_flow_table[0x1];
 825         u8         early_vf_enable[0x1];
 826         u8         reserved_at_1a9[0x2];
 827         u8         local_ca_ack_delay[0x5];
 828         u8         port_module_event[0x1];
 829         u8         reserved_at_1b0[0x1];
 830         u8         ports_check[0x1];
 831         u8         reserved_at_1b2[0x1];
 832         u8         disable_link_up[0x1];
 833         u8         beacon_led[0x1];
 834         u8         port_type[0x2];
 835         u8         num_ports[0x8];
 836
 837         u8         reserved_at_1c0[0x3];
 838         u8         log_max_msg[0x5];
 839         u8         reserved_at_1c8[0x4];
 840         u8         max_tc[0x4];
 841         u8         reserved_at_1d0[0x1];
 842         u8         dcbx[0x1];
 843         u8         reserved_at_1d2[0x4];
 844         u8         rol_s[0x1];
 845         u8         rol_g[0x1];
 846         u8         reserved_at_1d8[0x1];
 847         u8         wol_s[0x1];
 848         u8         wol_g[0x1];
 849         u8         wol_a[0x1];
 850         u8         wol_b[0x1];
 851         u8         wol_m[0x1];
 852         u8         wol_u[0x1];
 853         u8         wol_p[0x1];
 854
 855         u8         stat_rate_support[0x10];
 856         u8         reserved_at_1f0[0xc];
 857         u8         cqe_version[0x4];
 858
 859         u8         compact_address_vector[0x1];
 860         u8         striding_rq[0x1];
 861         u8         reserved_at_201[0x2];
 862         u8         ipoib_basic_offloads[0x1];
 863         u8         reserved_at_205[0xa];
 864         u8         drain_sigerr[0x1];
 865         u8         cmdif_checksum[0x2];
 866         u8         sigerr_cqe[0x1];
 867         u8         reserved_at_213[0x1];
 868         u8         wq_signature[0x1];
 869         u8         sctr_data_cqe[0x1];
 870         u8         reserved_at_216[0x1];
 871         u8         sho[0x1];
 872         u8         tph[0x1];
 873         u8         rf[0x1];
 874         u8         dct[0x1];
 875         u8         qos[0x1];
 876         u8         eth_net_offloads[0x1];
 877         u8         roce[0x1];
 878         u8         atomic[0x1];
 879         u8         reserved_at_21f[0x1];
 880
 881         u8         cq_oi[0x1];
 882         u8         cq_resize[0x1];
 883         u8         cq_moderation[0x1];
 884         u8         reserved_at_223[0x3];
 885         u8         cq_eq_remap[0x1];
 886         u8         pg[0x1];
 887         u8         block_lb_mc[0x1];
 888         u8         reserved_at_229[0x1];
 889         u8         scqe_break_moderation[0x1];
 890         u8         cq_period_start_from_cqe[0x1];
 891         u8         cd[0x1];
 892         u8         reserved_at_22d[0x1];
 893         u8         apm[0x1];
 894         u8         vector_calc[0x1];
 895         u8         umr_ptr_rlky[0x1];
 896         u8         imaicl[0x1];
 897         u8         reserved_at_232[0x4];
 898         u8         qkv[0x1];
 899         u8         pkv[0x1];
 900         u8         set_deth_sqpn[0x1];
 901         u8         reserved_at_239[0x3];
 902         u8         xrc[0x1];
 903         u8         ud[0x1];
 904         u8         uc[0x1];
 905         u8         rc[0x1];
 906
 907         u8         reserved_at_240[0xa];
 908         u8         uar_sz[0x6];
 909         u8         reserved_at_250[0x8];
 910         u8         log_pg_sz[0x8];
 911
 912         u8         bf[0x1];
 913         u8         driver_version[0x1];
 914         u8         pad_tx_eth_packet[0x1];
 915         u8         reserved_at_263[0x8];
 916         u8         log_bf_reg_size[0x5];
 917
 918         u8         reserved_at_270[0xb];
 919         u8         lag_master[0x1];
 920         u8         num_lag_ports[0x4];
 921
 922         u8         reserved_at_280[0x10];
 923         u8         max_wqe_sz_sq[0x10];
 924
 925         u8         reserved_at_2a0[0x10];
 926         u8         max_wqe_sz_rq[0x10];
 927
 928         u8         reserved_at_2c0[0x10];
 929         u8         max_wqe_sz_sq_dc[0x10];
 930
 931         u8         reserved_at_2e0[0x7];
 932         u8         max_qp_mcg[0x19];
 933
 934         u8         reserved_at_300[0x18];
 935         u8         log_max_mcg[0x8];
 936
 937         u8         reserved_at_320[0x3];
 938         u8         log_max_transport_domain[0x5];
 939         u8         reserved_at_328[0x3];
 940         u8         log_max_pd[0x5];
 941         u8         reserved_at_330[0xb];
 942         u8         log_max_xrcd[0x5];
 943
 944         u8         reserved_at_340[0x8];
 945         u8         log_max_flow_counter_bulk[0x8];
 946         u8         max_flow_counter[0x10];
 947
 948
 949         u8         reserved_at_360[0x3];
 950         u8         log_max_rq[0x5];
 951         u8         reserved_at_368[0x3];
 952         u8         log_max_sq[0x5];
 953         u8         reserved_at_370[0x3];
 954         u8         log_max_tir[0x5];
 955         u8         reserved_at_378[0x3];
 956         u8         log_max_tis[0x5];
 957
 958         u8         basic_cyclic_rcv_wqe[0x1];
 959         u8         reserved_at_381[0x2];
 960         u8         log_max_rmp[0x5];
 961         u8         reserved_at_388[0x3];
 962         u8         log_max_rqt[0x5];
 963         u8         reserved_at_390[0x3];
 964         u8         log_max_rqt_size[0x5];
 965         u8         reserved_at_398[0x3];
 966         u8         log_max_tis_per_sq[0x5];
 967
 968         u8         reserved_at_3a0[0x3];
 969         u8         log_max_stride_sz_rq[0x5];
 970         u8         reserved_at_3a8[0x3];
 971         u8         log_min_stride_sz_rq[0x5];
 972         u8         reserved_at_3b0[0x3];
 973         u8         log_max_stride_sz_sq[0x5];
 974         u8         reserved_at_3b8[0x3];
 975         u8         log_min_stride_sz_sq[0x5];
 976
 977         u8         reserved_at_3c0[0x1b];
 978         u8         log_max_wq_sz[0x5];
 979
 980         u8         nic_vport_change_event[0x1];
 981         u8         reserved_at_3e1[0xa];
 982         u8         log_max_vlan_list[0x5];
 983         u8         reserved_at_3f0[0x3];
 984         u8         log_max_current_mc_list[0x5];
 985         u8         reserved_at_3f8[0x3];
 986         u8         log_max_current_uc_list[0x5];
 987
 988         u8         reserved_at_400[0x80];
 989
 990         u8         reserved_at_480[0x3];
 991         u8         log_max_l2_table[0x5];
 992         u8         reserved_at_488[0x8];
 993         u8         log_uar_page_sz[0x10];
 994
 995         u8         reserved_at_4a0[0x20];
 996         u8         device_frequency_mhz[0x20];
 997         u8         device_frequency_khz[0x20];
 998
 999         u8         reserved_at_500[0x80];
1000
1001         u8         reserved_at_580[0x3f];
1002         u8         cqe_compression[0x1];
1003
1004         u8         cqe_compression_timeout[0x10];
1005         u8         cqe_compression_max_num[0x10];
1006
1007         u8         reserved_at_5e0[0x10];
1008         u8         tag_matching[0x1];
1009         u8         rndv_offload_rc[0x1];
1010         u8         rndv_offload_dc[0x1];
1011         u8         log_tag_matching_list_sz[0x5];
1012         u8         reserved_at_5e8[0x3];
1013         u8         log_max_xrq[0x5];
1014
1015         u8         reserved_at_5f0[0x200];
1016 };
1017
1018 enum mlx5_flow_destination_type {
1019         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1020         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1021         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1022
1023         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1024 };
1025
1026 struct mlx5_ifc_dest_format_struct_bits {
1027         u8         destination_type[0x8];
1028         u8         destination_id[0x18];
1029
1030         u8         reserved_at_20[0x20];
1031 };
1032
1033 struct mlx5_ifc_flow_counter_list_bits {
1034         u8         clear[0x1];
1035         u8         num_of_counters[0xf];
1036         u8         flow_counter_id[0x10];
1037
1038         u8         reserved_at_20[0x20];
1039 };
1040
1041 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1042         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1043         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1044         u8         reserved_at_0[0x40];
1045 };
1046
1047 struct mlx5_ifc_fte_match_param_bits {
1048         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1049
1050         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1051
1052         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1053
1054         u8         reserved_at_600[0xa00];
1055 };
1056
1057 enum {
1058         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1059         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1060         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1061         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1062         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1063 };
1064
1065 struct mlx5_ifc_rx_hash_field_select_bits {
1066         u8         l3_prot_type[0x1];
1067         u8         l4_prot_type[0x1];
1068         u8         selected_fields[0x1e];
1069 };
1070
1071 enum {
1072         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1073         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1074 };
1075
1076 enum {
1077         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1078         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1079 };
1080
1081 struct mlx5_ifc_wq_bits {
1082         u8         wq_type[0x4];
1083         u8         wq_signature[0x1];
1084         u8         end_padding_mode[0x2];
1085         u8         cd_slave[0x1];
1086         u8         reserved_at_8[0x18];
1087
1088         u8         hds_skip_first_sge[0x1];
1089         u8         log2_hds_buf_size[0x3];
1090         u8         reserved_at_24[0x7];
1091         u8         page_offset[0x5];
1092         u8         lwm[0x10];
1093
1094         u8         reserved_at_40[0x8];
1095         u8         pd[0x18];
1096
1097         u8         reserved_at_60[0x8];
1098         u8         uar_page[0x18];
1099
1100         u8         dbr_addr[0x40];
1101
1102         u8         hw_counter[0x20];
1103
1104         u8         sw_counter[0x20];
1105
1106         u8         reserved_at_100[0xc];
1107         u8         log_wq_stride[0x4];
1108         u8         reserved_at_110[0x3];
1109         u8         log_wq_pg_sz[0x5];
1110         u8         reserved_at_118[0x3];
1111         u8         log_wq_sz[0x5];
1112
1113         u8         reserved_at_120[0x15];
1114         u8         log_wqe_num_of_strides[0x3];
1115         u8         two_byte_shift_en[0x1];
1116         u8         reserved_at_139[0x4];
1117         u8         log_wqe_stride_size[0x3];
1118
1119         u8         reserved_at_140[0x4c0];
1120
1121         struct mlx5_ifc_cmd_pas_bits pas[0];
1122 };
1123
1124 struct mlx5_ifc_rq_num_bits {
1125         u8         reserved_at_0[0x8];
1126         u8         rq_num[0x18];
1127 };
1128
1129 struct mlx5_ifc_mac_address_layout_bits {
1130         u8         reserved_at_0[0x10];
1131         u8         mac_addr_47_32[0x10];
1132
1133         u8         mac_addr_31_0[0x20];
1134 };
1135
1136 struct mlx5_ifc_vlan_layout_bits {
1137         u8         reserved_at_0[0x14];
1138         u8         vlan[0x0c];
1139
1140         u8         reserved_at_20[0x20];
1141 };
1142
1143 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1144         u8         reserved_at_0[0xa0];
1145
1146         u8         min_time_between_cnps[0x20];
1147
1148         u8         reserved_at_c0[0x12];
1149         u8         cnp_dscp[0x6];
1150         u8         reserved_at_d8[0x5];
1151         u8         cnp_802p_prio[0x3];
1152
1153         u8         reserved_at_e0[0x720];
1154 };
1155
1156 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1157         u8         reserved_at_0[0x60];
1158
1159         u8         reserved_at_60[0x4];
1160         u8         clamp_tgt_rate[0x1];
1161         u8         reserved_at_65[0x3];
1162         u8         clamp_tgt_rate_after_time_inc[0x1];
1163         u8         reserved_at_69[0x17];
1164
1165         u8         reserved_at_80[0x20];
1166
1167         u8         rpg_time_reset[0x20];
1168
1169         u8         rpg_byte_reset[0x20];
1170
1171         u8         rpg_threshold[0x20];
1172
1173         u8         rpg_max_rate[0x20];
1174
1175         u8         rpg_ai_rate[0x20];
1176
1177         u8         rpg_hai_rate[0x20];
1178
1179         u8         rpg_gd[0x20];
1180
1181         u8         rpg_min_dec_fac[0x20];
1182
1183         u8         rpg_min_rate[0x20];
1184
1185         u8         reserved_at_1c0[0xe0];
1186
1187         u8         rate_to_set_on_first_cnp[0x20];
1188
1189         u8         dce_tcp_g[0x20];
1190
1191         u8         dce_tcp_rtt[0x20];
1192
1193         u8         rate_reduce_monitor_period[0x20];
1194
1195         u8         reserved_at_320[0x20];
1196
1197         u8         initial_alpha_value[0x20];
1198
1199         u8         reserved_at_360[0x4a0];
1200 };
1201
1202 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1203         u8         reserved_at_0[0x80];
1204
1205         u8         rppp_max_rps[0x20];
1206
1207         u8         rpg_time_reset[0x20];
1208
1209         u8         rpg_byte_reset[0x20];
1210
1211         u8         rpg_threshold[0x20];
1212
1213         u8         rpg_max_rate[0x20];
1214
1215         u8         rpg_ai_rate[0x20];
1216
1217         u8         rpg_hai_rate[0x20];
1218
1219         u8         rpg_gd[0x20];
1220
1221         u8         rpg_min_dec_fac[0x20];
1222
1223         u8         rpg_min_rate[0x20];
1224
1225         u8         reserved_at_1c0[0x640];
1226 };
1227
1228 enum {
1229         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1230         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1231         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1232 };
1233
1234 struct mlx5_ifc_resize_field_select_bits {
1235         u8         resize_field_select[0x20];
1236 };
1237
1238 enum {
1239         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1240         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1241         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1242         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1243 };
1244
1245 struct mlx5_ifc_modify_field_select_bits {
1246         u8         modify_field_select[0x20];
1247 };
1248
1249 struct mlx5_ifc_field_select_r_roce_np_bits {
1250         u8         field_select_r_roce_np[0x20];
1251 };
1252
1253 struct mlx5_ifc_field_select_r_roce_rp_bits {
1254         u8         field_select_r_roce_rp[0x20];
1255 };
1256
1257 enum {
1258         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1259         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1260         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1261         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1262         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1268 };
1269
1270 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1271         u8         field_select_8021qaurp[0x20];
1272 };
1273
1274 struct mlx5_ifc_phys_layer_cntrs_bits {
1275         u8         time_since_last_clear_high[0x20];
1276
1277         u8         time_since_last_clear_low[0x20];
1278
1279         u8         symbol_errors_high[0x20];
1280
1281         u8         symbol_errors_low[0x20];
1282
1283         u8         sync_headers_errors_high[0x20];
1284
1285         u8         sync_headers_errors_low[0x20];
1286
1287         u8         edpl_bip_errors_lane0_high[0x20];
1288
1289         u8         edpl_bip_errors_lane0_low[0x20];
1290
1291         u8         edpl_bip_errors_lane1_high[0x20];
1292
1293         u8         edpl_bip_errors_lane1_low[0x20];
1294
1295         u8         edpl_bip_errors_lane2_high[0x20];
1296
1297         u8         edpl_bip_errors_lane2_low[0x20];
1298
1299         u8         edpl_bip_errors_lane3_high[0x20];
1300
1301         u8         edpl_bip_errors_lane3_low[0x20];
1302
1303         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1304
1305         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1306
1307         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1308
1309         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1310
1311         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1312
1313         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1314
1315         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1316
1317         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1318
1319         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1320
1321         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1322
1323         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1324
1325         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1326
1327         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1328
1329         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1330
1331         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1332
1333         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1334
1335         u8         rs_fec_corrected_blocks_high[0x20];
1336
1337         u8         rs_fec_corrected_blocks_low[0x20];
1338
1339         u8         rs_fec_uncorrectable_blocks_high[0x20];
1340
1341         u8         rs_fec_uncorrectable_blocks_low[0x20];
1342
1343         u8         rs_fec_no_errors_blocks_high[0x20];
1344
1345         u8         rs_fec_no_errors_blocks_low[0x20];
1346
1347         u8         rs_fec_single_error_blocks_high[0x20];
1348
1349         u8         rs_fec_single_error_blocks_low[0x20];
1350
1351         u8         rs_fec_corrected_symbols_total_high[0x20];
1352
1353         u8         rs_fec_corrected_symbols_total_low[0x20];
1354
1355         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1356
1357         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1358
1359         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1360
1361         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1362
1363         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1364
1365         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1366
1367         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1368
1369         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1370
1371         u8         link_down_events[0x20];
1372
1373         u8         successful_recovery_events[0x20];
1374
1375         u8         reserved_at_640[0x180];
1376 };
1377
1378 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1379         u8         symbol_error_counter[0x10];
1380
1381         u8         link_error_recovery_counter[0x8];
1382
1383         u8         link_downed_counter[0x8];
1384
1385         u8         port_rcv_errors[0x10];
1386
1387         u8         port_rcv_remote_physical_errors[0x10];
1388
1389         u8         port_rcv_switch_relay_errors[0x10];
1390
1391         u8         port_xmit_discards[0x10];
1392
1393         u8         port_xmit_constraint_errors[0x8];
1394
1395         u8         port_rcv_constraint_errors[0x8];
1396
1397         u8         reserved_at_70[0x8];
1398
1399         u8         link_overrun_errors[0x8];
1400
1401         u8         reserved_at_80[0x10];
1402
1403         u8         vl_15_dropped[0x10];
1404
1405         u8         reserved_at_a0[0xa0];
1406 };
1407
1408 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1409         u8         transmit_queue_high[0x20];
1410
1411         u8         transmit_queue_low[0x20];
1412
1413         u8         reserved_at_40[0x780];
1414 };
1415
1416 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1417         u8         rx_octets_high[0x20];
1418
1419         u8         rx_octets_low[0x20];
1420
1421         u8         reserved_at_40[0xc0];
1422
1423         u8         rx_frames_high[0x20];
1424
1425         u8         rx_frames_low[0x20];
1426
1427         u8         tx_octets_high[0x20];
1428
1429         u8         tx_octets_low[0x20];
1430
1431         u8         reserved_at_180[0xc0];
1432
1433         u8         tx_frames_high[0x20];
1434
1435         u8         tx_frames_low[0x20];
1436
1437         u8         rx_pause_high[0x20];
1438
1439         u8         rx_pause_low[0x20];
1440
1441         u8         rx_pause_duration_high[0x20];
1442
1443         u8         rx_pause_duration_low[0x20];
1444
1445         u8         tx_pause_high[0x20];
1446
1447         u8         tx_pause_low[0x20];
1448
1449         u8         tx_pause_duration_high[0x20];
1450
1451         u8         tx_pause_duration_low[0x20];
1452
1453         u8         rx_pause_transition_high[0x20];
1454
1455         u8         rx_pause_transition_low[0x20];
1456
1457         u8         reserved_at_3c0[0x400];
1458 };
1459
1460 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1461         u8         port_transmit_wait_high[0x20];
1462
1463         u8         port_transmit_wait_low[0x20];
1464
1465         u8         reserved_at_40[0x780];
1466 };
1467
1468 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1469         u8         dot3stats_alignment_errors_high[0x20];
1470
1471         u8         dot3stats_alignment_errors_low[0x20];
1472
1473         u8         dot3stats_fcs_errors_high[0x20];
1474
1475         u8         dot3stats_fcs_errors_low[0x20];
1476
1477         u8         dot3stats_single_collision_frames_high[0x20];
1478
1479         u8         dot3stats_single_collision_frames_low[0x20];
1480
1481         u8         dot3stats_multiple_collision_frames_high[0x20];
1482
1483         u8         dot3stats_multiple_collision_frames_low[0x20];
1484
1485         u8         dot3stats_sqe_test_errors_high[0x20];
1486
1487         u8         dot3stats_sqe_test_errors_low[0x20];
1488
1489         u8         dot3stats_deferred_transmissions_high[0x20];
1490
1491         u8         dot3stats_deferred_transmissions_low[0x20];
1492
1493         u8         dot3stats_late_collisions_high[0x20];
1494
1495         u8         dot3stats_late_collisions_low[0x20];
1496
1497         u8         dot3stats_excessive_collisions_high[0x20];
1498
1499         u8         dot3stats_excessive_collisions_low[0x20];
1500
1501         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1502
1503         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1504
1505         u8         dot3stats_carrier_sense_errors_high[0x20];
1506
1507         u8         dot3stats_carrier_sense_errors_low[0x20];
1508
1509         u8         dot3stats_frame_too_longs_high[0x20];
1510
1511         u8         dot3stats_frame_too_longs_low[0x20];
1512
1513         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1514
1515         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1516
1517         u8         dot3stats_symbol_errors_high[0x20];
1518
1519         u8         dot3stats_symbol_errors_low[0x20];
1520
1521         u8         dot3control_in_unknown_opcodes_high[0x20];
1522
1523         u8         dot3control_in_unknown_opcodes_low[0x20];
1524
1525         u8         dot3in_pause_frames_high[0x20];
1526
1527         u8         dot3in_pause_frames_low[0x20];
1528
1529         u8         dot3out_pause_frames_high[0x20];
1530
1531         u8         dot3out_pause_frames_low[0x20];
1532
1533         u8         reserved_at_400[0x3c0];
1534 };
1535
1536 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1537         u8         ether_stats_drop_events_high[0x20];
1538
1539         u8         ether_stats_drop_events_low[0x20];
1540
1541         u8         ether_stats_octets_high[0x20];
1542
1543         u8         ether_stats_octets_low[0x20];
1544
1545         u8         ether_stats_pkts_high[0x20];
1546
1547         u8         ether_stats_pkts_low[0x20];
1548
1549         u8         ether_stats_broadcast_pkts_high[0x20];
1550
1551         u8         ether_stats_broadcast_pkts_low[0x20];
1552
1553         u8         ether_stats_multicast_pkts_high[0x20];
1554
1555         u8         ether_stats_multicast_pkts_low[0x20];
1556
1557         u8         ether_stats_crc_align_errors_high[0x20];
1558
1559         u8         ether_stats_crc_align_errors_low[0x20];
1560
1561         u8         ether_stats_undersize_pkts_high[0x20];
1562
1563         u8         ether_stats_undersize_pkts_low[0x20];
1564
1565         u8         ether_stats_oversize_pkts_high[0x20];
1566
1567         u8         ether_stats_oversize_pkts_low[0x20];
1568
1569         u8         ether_stats_fragments_high[0x20];
1570
1571         u8         ether_stats_fragments_low[0x20];
1572
1573         u8         ether_stats_jabbers_high[0x20];
1574
1575         u8         ether_stats_jabbers_low[0x20];
1576
1577         u8         ether_stats_collisions_high[0x20];
1578
1579         u8         ether_stats_collisions_low[0x20];
1580
1581         u8         ether_stats_pkts64octets_high[0x20];
1582
1583         u8         ether_stats_pkts64octets_low[0x20];
1584
1585         u8         ether_stats_pkts65to127octets_high[0x20];
1586
1587         u8         ether_stats_pkts65to127octets_low[0x20];
1588
1589         u8         ether_stats_pkts128to255octets_high[0x20];
1590
1591         u8         ether_stats_pkts128to255octets_low[0x20];
1592
1593         u8         ether_stats_pkts256to511octets_high[0x20];
1594
1595         u8         ether_stats_pkts256to511octets_low[0x20];
1596
1597         u8         ether_stats_pkts512to1023octets_high[0x20];
1598
1599         u8         ether_stats_pkts512to1023octets_low[0x20];
1600
1601         u8         ether_stats_pkts1024to1518octets_high[0x20];
1602
1603         u8         ether_stats_pkts1024to1518octets_low[0x20];
1604
1605         u8         ether_stats_pkts1519to2047octets_high[0x20];
1606
1607         u8         ether_stats_pkts1519to2047octets_low[0x20];
1608
1609         u8         ether_stats_pkts2048to4095octets_high[0x20];
1610
1611         u8         ether_stats_pkts2048to4095octets_low[0x20];
1612
1613         u8         ether_stats_pkts4096to8191octets_high[0x20];
1614
1615         u8         ether_stats_pkts4096to8191octets_low[0x20];
1616
1617         u8         ether_stats_pkts8192to10239octets_high[0x20];
1618
1619         u8         ether_stats_pkts8192to10239octets_low[0x20];
1620
1621         u8         reserved_at_540[0x280];
1622 };
1623
1624 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1625         u8         if_in_octets_high[0x20];
1626
1627         u8         if_in_octets_low[0x20];
1628
1629         u8         if_in_ucast_pkts_high[0x20];
1630
1631         u8         if_in_ucast_pkts_low[0x20];
1632
1633         u8         if_in_discards_high[0x20];
1634
1635         u8         if_in_discards_low[0x20];
1636
1637         u8         if_in_errors_high[0x20];
1638
1639         u8         if_in_errors_low[0x20];
1640
1641         u8         if_in_unknown_protos_high[0x20];
1642
1643         u8         if_in_unknown_protos_low[0x20];
1644
1645         u8         if_out_octets_high[0x20];
1646
1647         u8         if_out_octets_low[0x20];
1648
1649         u8         if_out_ucast_pkts_high[0x20];
1650
1651         u8         if_out_ucast_pkts_low[0x20];
1652
1653         u8         if_out_discards_high[0x20];
1654
1655         u8         if_out_discards_low[0x20];
1656
1657         u8         if_out_errors_high[0x20];
1658
1659         u8         if_out_errors_low[0x20];
1660
1661         u8         if_in_multicast_pkts_high[0x20];
1662
1663         u8         if_in_multicast_pkts_low[0x20];
1664
1665         u8         if_in_broadcast_pkts_high[0x20];
1666
1667         u8         if_in_broadcast_pkts_low[0x20];
1668
1669         u8         if_out_multicast_pkts_high[0x20];
1670
1671         u8         if_out_multicast_pkts_low[0x20];
1672
1673         u8         if_out_broadcast_pkts_high[0x20];
1674
1675         u8         if_out_broadcast_pkts_low[0x20];
1676
1677         u8         reserved_at_340[0x480];
1678 };
1679
1680 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1681         u8         a_frames_transmitted_ok_high[0x20];
1682
1683         u8         a_frames_transmitted_ok_low[0x20];
1684
1685         u8         a_frames_received_ok_high[0x20];
1686
1687         u8         a_frames_received_ok_low[0x20];
1688
1689         u8         a_frame_check_sequence_errors_high[0x20];
1690
1691         u8         a_frame_check_sequence_errors_low[0x20];
1692
1693         u8         a_alignment_errors_high[0x20];
1694
1695         u8         a_alignment_errors_low[0x20];
1696
1697         u8         a_octets_transmitted_ok_high[0x20];
1698
1699         u8         a_octets_transmitted_ok_low[0x20];
1700
1701         u8         a_octets_received_ok_high[0x20];
1702
1703         u8         a_octets_received_ok_low[0x20];
1704
1705         u8         a_multicast_frames_xmitted_ok_high[0x20];
1706
1707         u8         a_multicast_frames_xmitted_ok_low[0x20];
1708
1709         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1710
1711         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1712
1713         u8         a_multicast_frames_received_ok_high[0x20];
1714
1715         u8         a_multicast_frames_received_ok_low[0x20];
1716
1717         u8         a_broadcast_frames_received_ok_high[0x20];
1718
1719         u8         a_broadcast_frames_received_ok_low[0x20];
1720
1721         u8         a_in_range_length_errors_high[0x20];
1722
1723         u8         a_in_range_length_errors_low[0x20];
1724
1725         u8         a_out_of_range_length_field_high[0x20];
1726
1727         u8         a_out_of_range_length_field_low[0x20];
1728
1729         u8         a_frame_too_long_errors_high[0x20];
1730
1731         u8         a_frame_too_long_errors_low[0x20];
1732
1733         u8         a_symbol_error_during_carrier_high[0x20];
1734
1735         u8         a_symbol_error_during_carrier_low[0x20];
1736
1737         u8         a_mac_control_frames_transmitted_high[0x20];
1738
1739         u8         a_mac_control_frames_transmitted_low[0x20];
1740
1741         u8         a_mac_control_frames_received_high[0x20];
1742
1743         u8         a_mac_control_frames_received_low[0x20];
1744
1745         u8         a_unsupported_opcodes_received_high[0x20];
1746
1747         u8         a_unsupported_opcodes_received_low[0x20];
1748
1749         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1750
1751         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1752
1753         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1754
1755         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1756
1757         u8         reserved_at_4c0[0x300];
1758 };
1759
1760 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1761         u8         life_time_counter_high[0x20];
1762
1763         u8         life_time_counter_low[0x20];
1764
1765         u8         rx_errors[0x20];
1766
1767         u8         tx_errors[0x20];
1768
1769         u8         l0_to_recovery_eieos[0x20];
1770
1771         u8         l0_to_recovery_ts[0x20];
1772
1773         u8         l0_to_recovery_framing[0x20];
1774
1775         u8         l0_to_recovery_retrain[0x20];
1776
1777         u8         crc_error_dllp[0x20];
1778
1779         u8         crc_error_tlp[0x20];
1780
1781         u8         reserved_at_140[0x680];
1782 };
1783
1784 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
1785         u8         life_time_counter_high[0x20];
1786
1787         u8         life_time_counter_low[0x20];
1788
1789         u8         time_to_boot_image_start[0x20];
1790
1791         u8         time_to_link_image[0x20];
1792
1793         u8         calibration_time[0x20];
1794
1795         u8         time_to_first_perst[0x20];
1796
1797         u8         time_to_detect_state[0x20];
1798
1799         u8         time_to_l0[0x20];
1800
1801         u8         time_to_crs_en[0x20];
1802
1803         u8         time_to_plastic_image_start[0x20];
1804
1805         u8         time_to_iron_image_start[0x20];
1806
1807         u8         perst_handler[0x20];
1808
1809         u8         times_in_l1[0x20];
1810
1811         u8         times_in_l23[0x20];
1812
1813         u8         dl_down[0x20];
1814
1815         u8         config_cycle1usec[0x20];
1816
1817         u8         config_cycle2to7usec[0x20];
1818
1819         u8         config_cycle_8to15usec[0x20];
1820
1821         u8         config_cycle_16_to_63usec[0x20];
1822
1823         u8         config_cycle_64usec[0x20];
1824
1825         u8         correctable_err_msg_sent[0x20];
1826
1827         u8         non_fatal_err_msg_sent[0x20];
1828
1829         u8         fatal_err_msg_sent[0x20];
1830
1831         u8         reserved_at_2e0[0x4e0];
1832 };
1833
1834 struct mlx5_ifc_cmd_inter_comp_event_bits {
1835         u8         command_completion_vector[0x20];
1836
1837         u8         reserved_at_20[0xc0];
1838 };
1839
1840 struct mlx5_ifc_stall_vl_event_bits {
1841         u8         reserved_at_0[0x18];
1842         u8         port_num[0x1];
1843         u8         reserved_at_19[0x3];
1844         u8         vl[0x4];
1845
1846         u8         reserved_at_20[0xa0];
1847 };
1848
1849 struct mlx5_ifc_db_bf_congestion_event_bits {
1850         u8         event_subtype[0x8];
1851         u8         reserved_at_8[0x8];
1852         u8         congestion_level[0x8];
1853         u8         reserved_at_18[0x8];
1854
1855         u8         reserved_at_20[0xa0];
1856 };
1857
1858 struct mlx5_ifc_gpio_event_bits {
1859         u8         reserved_at_0[0x60];
1860
1861         u8         gpio_event_hi[0x20];
1862
1863         u8         gpio_event_lo[0x20];
1864
1865         u8         reserved_at_a0[0x40];
1866 };
1867
1868 struct mlx5_ifc_port_state_change_event_bits {
1869         u8         reserved_at_0[0x40];
1870
1871         u8         port_num[0x4];
1872         u8         reserved_at_44[0x1c];
1873
1874         u8         reserved_at_60[0x80];
1875 };
1876
1877 struct mlx5_ifc_dropped_packet_logged_bits {
1878         u8         reserved_at_0[0xe0];
1879 };
1880
1881 enum {
1882         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1883         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1884 };
1885
1886 struct mlx5_ifc_cq_error_bits {
1887         u8         reserved_at_0[0x8];
1888         u8         cqn[0x18];
1889
1890         u8         reserved_at_20[0x20];
1891
1892         u8         reserved_at_40[0x18];
1893         u8         syndrome[0x8];
1894
1895         u8         reserved_at_60[0x80];
1896 };
1897
1898 struct mlx5_ifc_rdma_page_fault_event_bits {
1899         u8         bytes_committed[0x20];
1900
1901         u8         r_key[0x20];
1902
1903         u8         reserved_at_40[0x10];
1904         u8         packet_len[0x10];
1905
1906         u8         rdma_op_len[0x20];
1907
1908         u8         rdma_va[0x40];
1909
1910         u8         reserved_at_c0[0x5];
1911         u8         rdma[0x1];
1912         u8         write[0x1];
1913         u8         requestor[0x1];
1914         u8         qp_number[0x18];
1915 };
1916
1917 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1918         u8         bytes_committed[0x20];
1919
1920         u8         reserved_at_20[0x10];
1921         u8         wqe_index[0x10];
1922
1923         u8         reserved_at_40[0x10];
1924         u8         len[0x10];
1925
1926         u8         reserved_at_60[0x60];
1927
1928         u8         reserved_at_c0[0x5];
1929         u8         rdma[0x1];
1930         u8         write_read[0x1];
1931         u8         requestor[0x1];
1932         u8         qpn[0x18];
1933 };
1934
1935 struct mlx5_ifc_qp_events_bits {
1936         u8         reserved_at_0[0xa0];
1937
1938         u8         type[0x8];
1939         u8         reserved_at_a8[0x18];
1940
1941         u8         reserved_at_c0[0x8];
1942         u8         qpn_rqn_sqn[0x18];
1943 };
1944
1945 struct mlx5_ifc_dct_events_bits {
1946         u8         reserved_at_0[0xc0];
1947
1948         u8         reserved_at_c0[0x8];
1949         u8         dct_number[0x18];
1950 };
1951
1952 struct mlx5_ifc_comp_event_bits {
1953         u8         reserved_at_0[0xc0];
1954
1955         u8         reserved_at_c0[0x8];
1956         u8         cq_number[0x18];
1957 };
1958
1959 enum {
1960         MLX5_QPC_STATE_RST        = 0x0,
1961         MLX5_QPC_STATE_INIT       = 0x1,
1962         MLX5_QPC_STATE_RTR        = 0x2,
1963         MLX5_QPC_STATE_RTS        = 0x3,
1964         MLX5_QPC_STATE_SQER       = 0x4,
1965         MLX5_QPC_STATE_ERR        = 0x6,
1966         MLX5_QPC_STATE_SQD        = 0x7,
1967         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1968 };
1969
1970 enum {
1971         MLX5_QPC_ST_RC            = 0x0,
1972         MLX5_QPC_ST_UC            = 0x1,
1973         MLX5_QPC_ST_UD            = 0x2,
1974         MLX5_QPC_ST_XRC           = 0x3,
1975         MLX5_QPC_ST_DCI           = 0x5,
1976         MLX5_QPC_ST_QP0           = 0x7,
1977         MLX5_QPC_ST_QP1           = 0x8,
1978         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1979         MLX5_QPC_ST_REG_UMR       = 0xc,
1980 };
1981
1982 enum {
1983         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1984         MLX5_QPC_PM_STATE_REARM     = 0x1,
1985         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1986         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1987 };
1988
1989 enum {
1990         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1991         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1992 };
1993
1994 enum {
1995         MLX5_QPC_MTU_256_BYTES        = 0x1,
1996         MLX5_QPC_MTU_512_BYTES        = 0x2,
1997         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1998         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1999         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2000         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2001 };
2002
2003 enum {
2004         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2005         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2006         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2007         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2008         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2009         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2010         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2011         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2012 };
2013
2014 enum {
2015         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2016         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2017         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2018 };
2019
2020 enum {
2021         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2022         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2023         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2024 };
2025
2026 struct mlx5_ifc_qpc_bits {
2027         u8         state[0x4];
2028         u8         lag_tx_port_affinity[0x4];
2029         u8         st[0x8];
2030         u8         reserved_at_10[0x3];
2031         u8         pm_state[0x2];
2032         u8         reserved_at_15[0x7];
2033         u8         end_padding_mode[0x2];
2034         u8         reserved_at_1e[0x2];
2035
2036         u8         wq_signature[0x1];
2037         u8         block_lb_mc[0x1];
2038         u8         atomic_like_write_en[0x1];
2039         u8         latency_sensitive[0x1];
2040         u8         reserved_at_24[0x1];
2041         u8         drain_sigerr[0x1];
2042         u8         reserved_at_26[0x2];
2043         u8         pd[0x18];
2044
2045         u8         mtu[0x3];
2046         u8         log_msg_max[0x5];
2047         u8         reserved_at_48[0x1];
2048         u8         log_rq_size[0x4];
2049         u8         log_rq_stride[0x3];
2050         u8         no_sq[0x1];
2051         u8         log_sq_size[0x4];
2052         u8         reserved_at_55[0x6];
2053         u8         rlky[0x1];
2054         u8         ulp_stateless_offload_mode[0x4];
2055
2056         u8         counter_set_id[0x8];
2057         u8         uar_page[0x18];
2058
2059         u8         reserved_at_80[0x8];
2060         u8         user_index[0x18];
2061
2062         u8         reserved_at_a0[0x3];
2063         u8         log_page_size[0x5];
2064         u8         remote_qpn[0x18];
2065
2066         struct mlx5_ifc_ads_bits primary_address_path;
2067
2068         struct mlx5_ifc_ads_bits secondary_address_path;
2069
2070         u8         log_ack_req_freq[0x4];
2071         u8         reserved_at_384[0x4];
2072         u8         log_sra_max[0x3];
2073         u8         reserved_at_38b[0x2];
2074         u8         retry_count[0x3];
2075         u8         rnr_retry[0x3];
2076         u8         reserved_at_393[0x1];
2077         u8         fre[0x1];
2078         u8         cur_rnr_retry[0x3];
2079         u8         cur_retry_count[0x3];
2080         u8         reserved_at_39b[0x5];
2081
2082         u8         reserved_at_3a0[0x20];
2083
2084         u8         reserved_at_3c0[0x8];
2085         u8         next_send_psn[0x18];
2086
2087         u8         reserved_at_3e0[0x8];
2088         u8         cqn_snd[0x18];
2089
2090         u8         reserved_at_400[0x8];
2091         u8         deth_sqpn[0x18];
2092
2093         u8         reserved_at_420[0x20];
2094
2095         u8         reserved_at_440[0x8];
2096         u8         last_acked_psn[0x18];
2097
2098         u8         reserved_at_460[0x8];
2099         u8         ssn[0x18];
2100
2101         u8         reserved_at_480[0x8];
2102         u8         log_rra_max[0x3];
2103         u8         reserved_at_48b[0x1];
2104         u8         atomic_mode[0x4];
2105         u8         rre[0x1];
2106         u8         rwe[0x1];
2107         u8         rae[0x1];
2108         u8         reserved_at_493[0x1];
2109         u8         page_offset[0x6];
2110         u8         reserved_at_49a[0x3];
2111         u8         cd_slave_receive[0x1];
2112         u8         cd_slave_send[0x1];
2113         u8         cd_master[0x1];
2114
2115         u8         reserved_at_4a0[0x3];
2116         u8         min_rnr_nak[0x5];
2117         u8         next_rcv_psn[0x18];
2118
2119         u8         reserved_at_4c0[0x8];
2120         u8         xrcd[0x18];
2121
2122         u8         reserved_at_4e0[0x8];
2123         u8         cqn_rcv[0x18];
2124
2125         u8         dbr_addr[0x40];
2126
2127         u8         q_key[0x20];
2128
2129         u8         reserved_at_560[0x5];
2130         u8         rq_type[0x3];
2131         u8         srqn_rmpn_xrqn[0x18];
2132
2133         u8         reserved_at_580[0x8];
2134         u8         rmsn[0x18];
2135
2136         u8         hw_sq_wqebb_counter[0x10];
2137         u8         sw_sq_wqebb_counter[0x10];
2138
2139         u8         hw_rq_counter[0x20];
2140
2141         u8         sw_rq_counter[0x20];
2142
2143         u8         reserved_at_600[0x20];
2144
2145         u8         reserved_at_620[0xf];
2146         u8         cgs[0x1];
2147         u8         cs_req[0x8];
2148         u8         cs_res[0x8];
2149
2150         u8         dc_access_key[0x40];
2151
2152         u8         reserved_at_680[0xc0];
2153 };
2154
2155 struct mlx5_ifc_roce_addr_layout_bits {
2156         u8         source_l3_address[16][0x8];
2157
2158         u8         reserved_at_80[0x3];
2159         u8         vlan_valid[0x1];
2160         u8         vlan_id[0xc];
2161         u8         source_mac_47_32[0x10];
2162
2163         u8         source_mac_31_0[0x20];
2164
2165         u8         reserved_at_c0[0x14];
2166         u8         roce_l3_type[0x4];
2167         u8         roce_version[0x8];
2168
2169         u8         reserved_at_e0[0x20];
2170 };
2171
2172 union mlx5_ifc_hca_cap_union_bits {
2173         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2174         struct mlx5_ifc_odp_cap_bits odp_cap;
2175         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2176         struct mlx5_ifc_roce_cap_bits roce_cap;
2177         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2178         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2179         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2180         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2181         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2182         struct mlx5_ifc_qos_cap_bits qos_cap;
2183         u8         reserved_at_0[0x8000];
2184 };
2185
2186 enum {
2187         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2188         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2189         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2190         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2191         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2192         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2193 };
2194
2195 struct mlx5_ifc_flow_context_bits {
2196         u8         reserved_at_0[0x20];
2197
2198         u8         group_id[0x20];
2199
2200         u8         reserved_at_40[0x8];
2201         u8         flow_tag[0x18];
2202
2203         u8         reserved_at_60[0x10];
2204         u8         action[0x10];
2205
2206         u8         reserved_at_80[0x8];
2207         u8         destination_list_size[0x18];
2208
2209         u8         reserved_at_a0[0x8];
2210         u8         flow_counter_list_size[0x18];
2211
2212         u8         encap_id[0x20];
2213
2214         u8         reserved_at_e0[0x120];
2215
2216         struct mlx5_ifc_fte_match_param_bits match_value;
2217
2218         u8         reserved_at_1200[0x600];
2219
2220         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2221 };
2222
2223 enum {
2224         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2225         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2226 };
2227
2228 struct mlx5_ifc_xrc_srqc_bits {
2229         u8         state[0x4];
2230         u8         log_xrc_srq_size[0x4];
2231         u8         reserved_at_8[0x18];
2232
2233         u8         wq_signature[0x1];
2234         u8         cont_srq[0x1];
2235         u8         reserved_at_22[0x1];
2236         u8         rlky[0x1];
2237         u8         basic_cyclic_rcv_wqe[0x1];
2238         u8         log_rq_stride[0x3];
2239         u8         xrcd[0x18];
2240
2241         u8         page_offset[0x6];
2242         u8         reserved_at_46[0x2];
2243         u8         cqn[0x18];
2244
2245         u8         reserved_at_60[0x20];
2246
2247         u8         user_index_equal_xrc_srqn[0x1];
2248         u8         reserved_at_81[0x1];
2249         u8         log_page_size[0x6];
2250         u8         user_index[0x18];
2251
2252         u8         reserved_at_a0[0x20];
2253
2254         u8         reserved_at_c0[0x8];
2255         u8         pd[0x18];
2256
2257         u8         lwm[0x10];
2258         u8         wqe_cnt[0x10];
2259
2260         u8         reserved_at_100[0x40];
2261
2262         u8         db_record_addr_h[0x20];
2263
2264         u8         db_record_addr_l[0x1e];
2265         u8         reserved_at_17e[0x2];
2266
2267         u8         reserved_at_180[0x80];
2268 };
2269
2270 struct mlx5_ifc_traffic_counter_bits {
2271         u8         packets[0x40];
2272
2273         u8         octets[0x40];
2274 };
2275
2276 struct mlx5_ifc_tisc_bits {
2277         u8         strict_lag_tx_port_affinity[0x1];
2278         u8         reserved_at_1[0x3];
2279         u8         lag_tx_port_affinity[0x04];
2280
2281         u8         reserved_at_8[0x4];
2282         u8         prio[0x4];
2283         u8         reserved_at_10[0x10];
2284
2285         u8         reserved_at_20[0x100];
2286
2287         u8         reserved_at_120[0x8];
2288         u8         transport_domain[0x18];
2289
2290         u8         reserved_at_140[0x3c0];
2291 };
2292
2293 enum {
2294         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2295         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2296 };
2297
2298 enum {
2299         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2300         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2301 };
2302
2303 enum {
2304         MLX5_RX_HASH_FN_NONE           = 0x0,
2305         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2306         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2307 };
2308
2309 enum {
2310         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2311         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2312 };
2313
2314 struct mlx5_ifc_tirc_bits {
2315         u8         reserved_at_0[0x20];
2316
2317         u8         disp_type[0x4];
2318         u8         reserved_at_24[0x1c];
2319
2320         u8         reserved_at_40[0x40];
2321
2322         u8         reserved_at_80[0x4];
2323         u8         lro_timeout_period_usecs[0x10];
2324         u8         lro_enable_mask[0x4];
2325         u8         lro_max_ip_payload_size[0x8];
2326
2327         u8         reserved_at_a0[0x40];
2328
2329         u8         reserved_at_e0[0x8];
2330         u8         inline_rqn[0x18];
2331
2332         u8         rx_hash_symmetric[0x1];
2333         u8         reserved_at_101[0x1];
2334         u8         tunneled_offload_en[0x1];
2335         u8         reserved_at_103[0x5];
2336         u8         indirect_table[0x18];
2337
2338         u8         rx_hash_fn[0x4];
2339         u8         reserved_at_124[0x2];
2340         u8         self_lb_block[0x2];
2341         u8         transport_domain[0x18];
2342
2343         u8         rx_hash_toeplitz_key[10][0x20];
2344
2345         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2346
2347         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2348
2349         u8         reserved_at_2c0[0x4c0];
2350 };
2351
2352 enum {
2353         MLX5_SRQC_STATE_GOOD   = 0x0,
2354         MLX5_SRQC_STATE_ERROR  = 0x1,
2355 };
2356
2357 struct mlx5_ifc_srqc_bits {
2358         u8         state[0x4];
2359         u8         log_srq_size[0x4];
2360         u8         reserved_at_8[0x18];
2361
2362         u8         wq_signature[0x1];
2363         u8         cont_srq[0x1];
2364         u8         reserved_at_22[0x1];
2365         u8         rlky[0x1];
2366         u8         reserved_at_24[0x1];
2367         u8         log_rq_stride[0x3];
2368         u8         xrcd[0x18];
2369
2370         u8         page_offset[0x6];
2371         u8         reserved_at_46[0x2];
2372         u8         cqn[0x18];
2373
2374         u8         reserved_at_60[0x20];
2375
2376         u8         reserved_at_80[0x2];
2377         u8         log_page_size[0x6];
2378         u8         reserved_at_88[0x18];
2379
2380         u8         reserved_at_a0[0x20];
2381
2382         u8         reserved_at_c0[0x8];
2383         u8         pd[0x18];
2384
2385         u8         lwm[0x10];
2386         u8         wqe_cnt[0x10];
2387
2388         u8         reserved_at_100[0x40];
2389
2390         u8         dbr_addr[0x40];
2391
2392         u8         reserved_at_180[0x80];
2393 };
2394
2395 enum {
2396         MLX5_SQC_STATE_RST  = 0x0,
2397         MLX5_SQC_STATE_RDY  = 0x1,
2398         MLX5_SQC_STATE_ERR  = 0x3,
2399 };
2400
2401 struct mlx5_ifc_sqc_bits {
2402         u8         rlky[0x1];
2403         u8         cd_master[0x1];
2404         u8         fre[0x1];
2405         u8         flush_in_error_en[0x1];
2406         u8         reserved_at_4[0x1];
2407         u8         min_wqe_inline_mode[0x3];
2408         u8         state[0x4];
2409         u8         reg_umr[0x1];
2410         u8         reserved_at_d[0x13];
2411
2412         u8         reserved_at_20[0x8];
2413         u8         user_index[0x18];
2414
2415         u8         reserved_at_40[0x8];
2416         u8         cqn[0x18];
2417
2418         u8         reserved_at_60[0x90];
2419
2420         u8         packet_pacing_rate_limit_index[0x10];
2421         u8         tis_lst_sz[0x10];
2422         u8         reserved_at_110[0x10];
2423
2424         u8         reserved_at_120[0x40];
2425
2426         u8         reserved_at_160[0x8];
2427         u8         tis_num_0[0x18];
2428
2429         struct mlx5_ifc_wq_bits wq;
2430 };
2431
2432 enum {
2433         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2434         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2435         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2436         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2437 };
2438
2439 struct mlx5_ifc_scheduling_context_bits {
2440         u8         element_type[0x8];
2441         u8         reserved_at_8[0x18];
2442
2443         u8         element_attributes[0x20];
2444
2445         u8         parent_element_id[0x20];
2446
2447         u8         reserved_at_60[0x40];
2448
2449         u8         bw_share[0x20];
2450
2451         u8         max_average_bw[0x20];
2452
2453         u8         reserved_at_e0[0x120];
2454 };
2455
2456 struct mlx5_ifc_rqtc_bits {
2457         u8         reserved_at_0[0xa0];
2458
2459         u8         reserved_at_a0[0x10];
2460         u8         rqt_max_size[0x10];
2461
2462         u8         reserved_at_c0[0x10];
2463         u8         rqt_actual_size[0x10];
2464
2465         u8         reserved_at_e0[0x6a0];
2466
2467         struct mlx5_ifc_rq_num_bits rq_num[0];
2468 };
2469
2470 enum {
2471         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2472         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2473 };
2474
2475 enum {
2476         MLX5_RQC_STATE_RST  = 0x0,
2477         MLX5_RQC_STATE_RDY  = 0x1,
2478         MLX5_RQC_STATE_ERR  = 0x3,
2479 };
2480
2481 struct mlx5_ifc_rqc_bits {
2482         u8         rlky[0x1];
2483         u8         reserved_at_1[0x1];
2484         u8         scatter_fcs[0x1];
2485         u8         vsd[0x1];
2486         u8         mem_rq_type[0x4];
2487         u8         state[0x4];
2488         u8         reserved_at_c[0x1];
2489         u8         flush_in_error_en[0x1];
2490         u8         reserved_at_e[0x12];
2491
2492         u8         reserved_at_20[0x8];
2493         u8         user_index[0x18];
2494
2495         u8         reserved_at_40[0x8];
2496         u8         cqn[0x18];
2497
2498         u8         counter_set_id[0x8];
2499         u8         reserved_at_68[0x18];
2500
2501         u8         reserved_at_80[0x8];
2502         u8         rmpn[0x18];
2503
2504         u8         reserved_at_a0[0xe0];
2505
2506         struct mlx5_ifc_wq_bits wq;
2507 };
2508
2509 enum {
2510         MLX5_RMPC_STATE_RDY  = 0x1,
2511         MLX5_RMPC_STATE_ERR  = 0x3,
2512 };
2513
2514 struct mlx5_ifc_rmpc_bits {
2515         u8         reserved_at_0[0x8];
2516         u8         state[0x4];
2517         u8         reserved_at_c[0x14];
2518
2519         u8         basic_cyclic_rcv_wqe[0x1];
2520         u8         reserved_at_21[0x1f];
2521
2522         u8         reserved_at_40[0x140];
2523
2524         struct mlx5_ifc_wq_bits wq;
2525 };
2526
2527 struct mlx5_ifc_nic_vport_context_bits {
2528         u8         reserved_at_0[0x5];
2529         u8         min_wqe_inline_mode[0x3];
2530         u8         reserved_at_8[0x17];
2531         u8         roce_en[0x1];
2532
2533         u8         arm_change_event[0x1];
2534         u8         reserved_at_21[0x1a];
2535         u8         event_on_mtu[0x1];
2536         u8         event_on_promisc_change[0x1];
2537         u8         event_on_vlan_change[0x1];
2538         u8         event_on_mc_address_change[0x1];
2539         u8         event_on_uc_address_change[0x1];
2540
2541         u8         reserved_at_40[0xf0];
2542
2543         u8         mtu[0x10];
2544
2545         u8         system_image_guid[0x40];
2546         u8         port_guid[0x40];
2547         u8         node_guid[0x40];
2548
2549         u8         reserved_at_200[0x140];
2550         u8         qkey_violation_counter[0x10];
2551         u8         reserved_at_350[0x430];
2552
2553         u8         promisc_uc[0x1];
2554         u8         promisc_mc[0x1];
2555         u8         promisc_all[0x1];
2556         u8         reserved_at_783[0x2];
2557         u8         allowed_list_type[0x3];
2558         u8         reserved_at_788[0xc];
2559         u8         allowed_list_size[0xc];
2560
2561         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2562
2563         u8         reserved_at_7e0[0x20];
2564
2565         u8         current_uc_mac_address[0][0x40];
2566 };
2567
2568 enum {
2569         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2570         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2571         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2572 };
2573
2574 struct mlx5_ifc_mkc_bits {
2575         u8         reserved_at_0[0x1];
2576         u8         free[0x1];
2577         u8         reserved_at_2[0xd];
2578         u8         small_fence_on_rdma_read_response[0x1];
2579         u8         umr_en[0x1];
2580         u8         a[0x1];
2581         u8         rw[0x1];
2582         u8         rr[0x1];
2583         u8         lw[0x1];
2584         u8         lr[0x1];
2585         u8         access_mode[0x2];
2586         u8         reserved_at_18[0x8];
2587
2588         u8         qpn[0x18];
2589         u8         mkey_7_0[0x8];
2590
2591         u8         reserved_at_40[0x20];
2592
2593         u8         length64[0x1];
2594         u8         bsf_en[0x1];
2595         u8         sync_umr[0x1];
2596         u8         reserved_at_63[0x2];
2597         u8         expected_sigerr_count[0x1];
2598         u8         reserved_at_66[0x1];
2599         u8         en_rinval[0x1];
2600         u8         pd[0x18];
2601
2602         u8         start_addr[0x40];
2603
2604         u8         len[0x40];
2605
2606         u8         bsf_octword_size[0x20];
2607
2608         u8         reserved_at_120[0x80];
2609
2610         u8         translations_octword_size[0x20];
2611
2612         u8         reserved_at_1c0[0x1b];
2613         u8         log_page_size[0x5];
2614
2615         u8         reserved_at_1e0[0x20];
2616 };
2617
2618 struct mlx5_ifc_pkey_bits {
2619         u8         reserved_at_0[0x10];
2620         u8         pkey[0x10];
2621 };
2622
2623 struct mlx5_ifc_array128_auto_bits {
2624         u8         array128_auto[16][0x8];
2625 };
2626
2627 struct mlx5_ifc_hca_vport_context_bits {
2628         u8         field_select[0x20];
2629
2630         u8         reserved_at_20[0xe0];
2631
2632         u8         sm_virt_aware[0x1];
2633         u8         has_smi[0x1];
2634         u8         has_raw[0x1];
2635         u8         grh_required[0x1];
2636         u8         reserved_at_104[0xc];
2637         u8         port_physical_state[0x4];
2638         u8         vport_state_policy[0x4];
2639         u8         port_state[0x4];
2640         u8         vport_state[0x4];
2641
2642         u8         reserved_at_120[0x20];
2643
2644         u8         system_image_guid[0x40];
2645
2646         u8         port_guid[0x40];
2647
2648         u8         node_guid[0x40];
2649
2650         u8         cap_mask1[0x20];
2651
2652         u8         cap_mask1_field_select[0x20];
2653
2654         u8         cap_mask2[0x20];
2655
2656         u8         cap_mask2_field_select[0x20];
2657
2658         u8         reserved_at_280[0x80];
2659
2660         u8         lid[0x10];
2661         u8         reserved_at_310[0x4];
2662         u8         init_type_reply[0x4];
2663         u8         lmc[0x3];
2664         u8         subnet_timeout[0x5];
2665
2666         u8         sm_lid[0x10];
2667         u8         sm_sl[0x4];
2668         u8         reserved_at_334[0xc];
2669
2670         u8         qkey_violation_counter[0x10];
2671         u8         pkey_violation_counter[0x10];
2672
2673         u8         reserved_at_360[0xca0];
2674 };
2675
2676 struct mlx5_ifc_esw_vport_context_bits {
2677         u8         reserved_at_0[0x3];
2678         u8         vport_svlan_strip[0x1];
2679         u8         vport_cvlan_strip[0x1];
2680         u8         vport_svlan_insert[0x1];
2681         u8         vport_cvlan_insert[0x2];
2682         u8         reserved_at_8[0x18];
2683
2684         u8         reserved_at_20[0x20];
2685
2686         u8         svlan_cfi[0x1];
2687         u8         svlan_pcp[0x3];
2688         u8         svlan_id[0xc];
2689         u8         cvlan_cfi[0x1];
2690         u8         cvlan_pcp[0x3];
2691         u8         cvlan_id[0xc];
2692
2693         u8         reserved_at_60[0x7a0];
2694 };
2695
2696 enum {
2697         MLX5_EQC_STATUS_OK                = 0x0,
2698         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2699 };
2700
2701 enum {
2702         MLX5_EQC_ST_ARMED  = 0x9,
2703         MLX5_EQC_ST_FIRED  = 0xa,
2704 };
2705
2706 struct mlx5_ifc_eqc_bits {
2707         u8         status[0x4];
2708         u8         reserved_at_4[0x9];
2709         u8         ec[0x1];
2710         u8         oi[0x1];
2711         u8         reserved_at_f[0x5];
2712         u8         st[0x4];
2713         u8         reserved_at_18[0x8];
2714
2715         u8         reserved_at_20[0x20];
2716
2717         u8         reserved_at_40[0x14];
2718         u8         page_offset[0x6];
2719         u8         reserved_at_5a[0x6];
2720
2721         u8         reserved_at_60[0x3];
2722         u8         log_eq_size[0x5];
2723         u8         uar_page[0x18];
2724
2725         u8         reserved_at_80[0x20];
2726
2727         u8         reserved_at_a0[0x18];
2728         u8         intr[0x8];
2729
2730         u8         reserved_at_c0[0x3];
2731         u8         log_page_size[0x5];
2732         u8         reserved_at_c8[0x18];
2733
2734         u8         reserved_at_e0[0x60];
2735
2736         u8         reserved_at_140[0x8];
2737         u8         consumer_counter[0x18];
2738
2739         u8         reserved_at_160[0x8];
2740         u8         producer_counter[0x18];
2741
2742         u8         reserved_at_180[0x80];
2743 };
2744
2745 enum {
2746         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2747         MLX5_DCTC_STATE_DRAINING  = 0x1,
2748         MLX5_DCTC_STATE_DRAINED   = 0x2,
2749 };
2750
2751 enum {
2752         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2753         MLX5_DCTC_CS_RES_NA         = 0x1,
2754         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2755 };
2756
2757 enum {
2758         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2759         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2760         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2761         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2762         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2763 };
2764
2765 struct mlx5_ifc_dctc_bits {
2766         u8         reserved_at_0[0x4];
2767         u8         state[0x4];
2768         u8         reserved_at_8[0x18];
2769
2770         u8         reserved_at_20[0x8];
2771         u8         user_index[0x18];
2772
2773         u8         reserved_at_40[0x8];
2774         u8         cqn[0x18];
2775
2776         u8         counter_set_id[0x8];
2777         u8         atomic_mode[0x4];
2778         u8         rre[0x1];
2779         u8         rwe[0x1];
2780         u8         rae[0x1];
2781         u8         atomic_like_write_en[0x1];
2782         u8         latency_sensitive[0x1];
2783         u8         rlky[0x1];
2784         u8         free_ar[0x1];
2785         u8         reserved_at_73[0xd];
2786
2787         u8         reserved_at_80[0x8];
2788         u8         cs_res[0x8];
2789         u8         reserved_at_90[0x3];
2790         u8         min_rnr_nak[0x5];
2791         u8         reserved_at_98[0x8];
2792
2793         u8         reserved_at_a0[0x8];
2794         u8         srqn_xrqn[0x18];
2795
2796         u8         reserved_at_c0[0x8];
2797         u8         pd[0x18];
2798
2799         u8         tclass[0x8];
2800         u8         reserved_at_e8[0x4];
2801         u8         flow_label[0x14];
2802
2803         u8         dc_access_key[0x40];
2804
2805         u8         reserved_at_140[0x5];
2806         u8         mtu[0x3];
2807         u8         port[0x8];
2808         u8         pkey_index[0x10];
2809
2810         u8         reserved_at_160[0x8];
2811         u8         my_addr_index[0x8];
2812         u8         reserved_at_170[0x8];
2813         u8         hop_limit[0x8];
2814
2815         u8         dc_access_key_violation_count[0x20];
2816
2817         u8         reserved_at_1a0[0x14];
2818         u8         dei_cfi[0x1];
2819         u8         eth_prio[0x3];
2820         u8         ecn[0x2];
2821         u8         dscp[0x6];
2822
2823         u8         reserved_at_1c0[0x40];
2824 };
2825
2826 enum {
2827         MLX5_CQC_STATUS_OK             = 0x0,
2828         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2829         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2830 };
2831
2832 enum {
2833         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2834         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2835 };
2836
2837 enum {
2838         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2839         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2840         MLX5_CQC_ST_FIRED                                 = 0xa,
2841 };
2842
2843 enum {
2844         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2845         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2846         MLX5_CQ_PERIOD_NUM_MODES
2847 };
2848
2849 struct mlx5_ifc_cqc_bits {
2850         u8         status[0x4];
2851         u8         reserved_at_4[0x4];
2852         u8         cqe_sz[0x3];
2853         u8         cc[0x1];
2854         u8         reserved_at_c[0x1];
2855         u8         scqe_break_moderation_en[0x1];
2856         u8         oi[0x1];
2857         u8         cq_period_mode[0x2];
2858         u8         cqe_comp_en[0x1];
2859         u8         mini_cqe_res_format[0x2];
2860         u8         st[0x4];
2861         u8         reserved_at_18[0x8];
2862
2863         u8         reserved_at_20[0x20];
2864
2865         u8         reserved_at_40[0x14];
2866         u8         page_offset[0x6];
2867         u8         reserved_at_5a[0x6];
2868
2869         u8         reserved_at_60[0x3];
2870         u8         log_cq_size[0x5];
2871         u8         uar_page[0x18];
2872
2873         u8         reserved_at_80[0x4];
2874         u8         cq_period[0xc];
2875         u8         cq_max_count[0x10];
2876
2877         u8         reserved_at_a0[0x18];
2878         u8         c_eqn[0x8];
2879
2880         u8         reserved_at_c0[0x3];
2881         u8         log_page_size[0x5];
2882         u8         reserved_at_c8[0x18];
2883
2884         u8         reserved_at_e0[0x20];
2885
2886         u8         reserved_at_100[0x8];
2887         u8         last_notified_index[0x18];
2888
2889         u8         reserved_at_120[0x8];
2890         u8         last_solicit_index[0x18];
2891
2892         u8         reserved_at_140[0x8];
2893         u8         consumer_counter[0x18];
2894
2895         u8         reserved_at_160[0x8];
2896         u8         producer_counter[0x18];
2897
2898         u8         reserved_at_180[0x40];
2899
2900         u8         dbr_addr[0x40];
2901 };
2902
2903 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2904         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2905         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2906         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2907         u8         reserved_at_0[0x800];
2908 };
2909
2910 struct mlx5_ifc_query_adapter_param_block_bits {
2911         u8         reserved_at_0[0xc0];
2912
2913         u8         reserved_at_c0[0x8];
2914         u8         ieee_vendor_id[0x18];
2915
2916         u8         reserved_at_e0[0x10];
2917         u8         vsd_vendor_id[0x10];
2918
2919         u8         vsd[208][0x8];
2920
2921         u8         vsd_contd_psid[16][0x8];
2922 };
2923
2924 enum {
2925         MLX5_XRQC_STATE_GOOD   = 0x0,
2926         MLX5_XRQC_STATE_ERROR  = 0x1,
2927 };
2928
2929 enum {
2930         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2931         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2932 };
2933
2934 enum {
2935         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2936 };
2937
2938 struct mlx5_ifc_tag_matching_topology_context_bits {
2939         u8         log_matching_list_sz[0x4];
2940         u8         reserved_at_4[0xc];
2941         u8         append_next_index[0x10];
2942
2943         u8         sw_phase_cnt[0x10];
2944         u8         hw_phase_cnt[0x10];
2945
2946         u8         reserved_at_40[0x40];
2947 };
2948
2949 struct mlx5_ifc_xrqc_bits {
2950         u8         state[0x4];
2951         u8         rlkey[0x1];
2952         u8         reserved_at_5[0xf];
2953         u8         topology[0x4];
2954         u8         reserved_at_18[0x4];
2955         u8         offload[0x4];
2956
2957         u8         reserved_at_20[0x8];
2958         u8         user_index[0x18];
2959
2960         u8         reserved_at_40[0x8];
2961         u8         cqn[0x18];
2962
2963         u8         reserved_at_60[0xa0];
2964
2965         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2966
2967         u8         reserved_at_180[0x880];
2968
2969         struct mlx5_ifc_wq_bits wq;
2970 };
2971
2972 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2973         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2974         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2975         u8         reserved_at_0[0x20];
2976 };
2977
2978 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2979         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2980         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2981         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2982         u8         reserved_at_0[0x20];
2983 };
2984
2985 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2986         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2987         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2988         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2989         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2990         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2991         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2992         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2993         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2994         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2995         u8         reserved_at_0[0x7c0];
2996 };
2997
2998 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2999         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3000         struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
3001         u8         reserved_at_0[0x7c0];
3002 };
3003
3004 union mlx5_ifc_event_auto_bits {
3005         struct mlx5_ifc_comp_event_bits comp_event;
3006         struct mlx5_ifc_dct_events_bits dct_events;
3007         struct mlx5_ifc_qp_events_bits qp_events;
3008         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3009         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3010         struct mlx5_ifc_cq_error_bits cq_error;
3011         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3012         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3013         struct mlx5_ifc_gpio_event_bits gpio_event;
3014         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3015         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3016         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3017         u8         reserved_at_0[0xe0];
3018 };
3019
3020 struct mlx5_ifc_health_buffer_bits {
3021         u8         reserved_at_0[0x100];
3022
3023         u8         assert_existptr[0x20];
3024
3025         u8         assert_callra[0x20];
3026
3027         u8         reserved_at_140[0x40];
3028
3029         u8         fw_version[0x20];
3030
3031         u8         hw_id[0x20];
3032
3033         u8         reserved_at_1c0[0x20];
3034
3035         u8         irisc_index[0x8];
3036         u8         synd[0x8];
3037         u8         ext_synd[0x10];
3038 };
3039
3040 struct mlx5_ifc_register_loopback_control_bits {
3041         u8         no_lb[0x1];
3042         u8         reserved_at_1[0x7];
3043         u8         port[0x8];
3044         u8         reserved_at_10[0x10];
3045
3046         u8         reserved_at_20[0x60];
3047 };
3048
3049 struct mlx5_ifc_vport_tc_element_bits {
3050         u8         traffic_class[0x4];
3051         u8         reserved_at_4[0xc];
3052         u8         vport_number[0x10];
3053 };
3054
3055 struct mlx5_ifc_vport_element_bits {
3056         u8         reserved_at_0[0x10];
3057         u8         vport_number[0x10];
3058 };
3059
3060 enum {
3061         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3062         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3063         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3064 };
3065
3066 struct mlx5_ifc_tsar_element_bits {
3067         u8         reserved_at_0[0x8];
3068         u8         tsar_type[0x8];
3069         u8         reserved_at_10[0x10];
3070 };
3071
3072 struct mlx5_ifc_teardown_hca_out_bits {
3073         u8         status[0x8];
3074         u8         reserved_at_8[0x18];
3075
3076         u8         syndrome[0x20];
3077
3078         u8         reserved_at_40[0x40];
3079 };
3080
3081 enum {
3082         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3083         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3084 };
3085
3086 struct mlx5_ifc_teardown_hca_in_bits {
3087         u8         opcode[0x10];
3088         u8         reserved_at_10[0x10];
3089
3090         u8         reserved_at_20[0x10];
3091         u8         op_mod[0x10];
3092
3093         u8         reserved_at_40[0x10];
3094         u8         profile[0x10];
3095
3096         u8         reserved_at_60[0x20];
3097 };
3098
3099 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3100         u8         status[0x8];
3101         u8         reserved_at_8[0x18];
3102
3103         u8         syndrome[0x20];
3104
3105         u8         reserved_at_40[0x40];
3106 };
3107
3108 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3109         u8         opcode[0x10];
3110         u8         reserved_at_10[0x10];
3111
3112         u8         reserved_at_20[0x10];
3113         u8         op_mod[0x10];
3114
3115         u8         reserved_at_40[0x8];
3116         u8         qpn[0x18];
3117
3118         u8         reserved_at_60[0x20];
3119
3120         u8         opt_param_mask[0x20];
3121
3122         u8         reserved_at_a0[0x20];
3123
3124         struct mlx5_ifc_qpc_bits qpc;
3125
3126         u8         reserved_at_800[0x80];
3127 };
3128
3129 struct mlx5_ifc_sqd2rts_qp_out_bits {
3130         u8         status[0x8];
3131         u8         reserved_at_8[0x18];
3132
3133         u8         syndrome[0x20];
3134
3135         u8         reserved_at_40[0x40];
3136 };
3137
3138 struct mlx5_ifc_sqd2rts_qp_in_bits {
3139         u8         opcode[0x10];
3140         u8         reserved_at_10[0x10];
3141
3142         u8         reserved_at_20[0x10];
3143         u8         op_mod[0x10];
3144
3145         u8         reserved_at_40[0x8];
3146         u8         qpn[0x18];
3147
3148         u8         reserved_at_60[0x20];
3149
3150         u8         opt_param_mask[0x20];
3151
3152         u8         reserved_at_a0[0x20];
3153
3154         struct mlx5_ifc_qpc_bits qpc;
3155
3156         u8         reserved_at_800[0x80];
3157 };
3158
3159 struct mlx5_ifc_set_roce_address_out_bits {
3160         u8         status[0x8];
3161         u8         reserved_at_8[0x18];
3162
3163         u8         syndrome[0x20];
3164
3165         u8         reserved_at_40[0x40];
3166 };
3167
3168 struct mlx5_ifc_set_roce_address_in_bits {
3169         u8         opcode[0x10];
3170         u8         reserved_at_10[0x10];
3171
3172         u8         reserved_at_20[0x10];
3173         u8         op_mod[0x10];
3174
3175         u8         roce_address_index[0x10];
3176         u8         reserved_at_50[0x10];
3177
3178         u8         reserved_at_60[0x20];
3179
3180         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3181 };
3182
3183 struct mlx5_ifc_set_mad_demux_out_bits {
3184         u8         status[0x8];
3185         u8         reserved_at_8[0x18];
3186
3187         u8         syndrome[0x20];
3188
3189         u8         reserved_at_40[0x40];
3190 };
3191
3192 enum {
3193         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3194         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3195 };
3196
3197 struct mlx5_ifc_set_mad_demux_in_bits {
3198         u8         opcode[0x10];
3199         u8         reserved_at_10[0x10];
3200
3201         u8         reserved_at_20[0x10];
3202         u8         op_mod[0x10];
3203
3204         u8         reserved_at_40[0x20];
3205
3206         u8         reserved_at_60[0x6];
3207         u8         demux_mode[0x2];
3208         u8         reserved_at_68[0x18];
3209 };
3210
3211 struct mlx5_ifc_set_l2_table_entry_out_bits {
3212         u8         status[0x8];
3213         u8         reserved_at_8[0x18];
3214
3215         u8         syndrome[0x20];
3216
3217         u8         reserved_at_40[0x40];
3218 };
3219
3220 struct mlx5_ifc_set_l2_table_entry_in_bits {
3221         u8         opcode[0x10];
3222         u8         reserved_at_10[0x10];
3223
3224         u8         reserved_at_20[0x10];
3225         u8         op_mod[0x10];
3226
3227         u8         reserved_at_40[0x60];
3228
3229         u8         reserved_at_a0[0x8];
3230         u8         table_index[0x18];
3231
3232         u8         reserved_at_c0[0x20];
3233
3234         u8         reserved_at_e0[0x13];
3235         u8         vlan_valid[0x1];
3236         u8         vlan[0xc];
3237
3238         struct mlx5_ifc_mac_address_layout_bits mac_address;
3239
3240         u8         reserved_at_140[0xc0];
3241 };
3242
3243 struct mlx5_ifc_set_issi_out_bits {
3244         u8         status[0x8];
3245         u8         reserved_at_8[0x18];
3246
3247         u8         syndrome[0x20];
3248
3249         u8         reserved_at_40[0x40];
3250 };
3251
3252 struct mlx5_ifc_set_issi_in_bits {
3253         u8         opcode[0x10];
3254         u8         reserved_at_10[0x10];
3255
3256         u8         reserved_at_20[0x10];
3257         u8         op_mod[0x10];
3258
3259         u8         reserved_at_40[0x10];
3260         u8         current_issi[0x10];
3261
3262         u8         reserved_at_60[0x20];
3263 };
3264
3265 struct mlx5_ifc_set_hca_cap_out_bits {
3266         u8         status[0x8];
3267         u8         reserved_at_8[0x18];
3268
3269         u8         syndrome[0x20];
3270
3271         u8         reserved_at_40[0x40];
3272 };
3273
3274 struct mlx5_ifc_set_hca_cap_in_bits {
3275         u8         opcode[0x10];
3276         u8         reserved_at_10[0x10];
3277
3278         u8         reserved_at_20[0x10];
3279         u8         op_mod[0x10];