net/mlx5: Add MCC (Management Component Control) register definitions
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64
65 enum {
66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71
72 enum {
73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76
77 enum {
78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
170         MLX5_CMD_OP_NOP                           = 0x80d,
171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
203         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
204         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
205         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
206         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
207         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
208         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
209         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
210         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
211         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
212         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
213         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
214         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
215         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
216         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
217         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
218         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
219         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
220         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
221         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
222         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
223         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
224         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
225         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
226         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
227         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
228         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
229         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
230         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
231         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
232         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
233         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
234         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
235         MLX5_CMD_OP_MAX
236 };
237
238 struct mlx5_ifc_flow_table_fields_supported_bits {
239         u8         outer_dmac[0x1];
240         u8         outer_smac[0x1];
241         u8         outer_ether_type[0x1];
242         u8         outer_ip_version[0x1];
243         u8         outer_first_prio[0x1];
244         u8         outer_first_cfi[0x1];
245         u8         outer_first_vid[0x1];
246         u8         outer_ipv4_ttl[0x1];
247         u8         outer_second_prio[0x1];
248         u8         outer_second_cfi[0x1];
249         u8         outer_second_vid[0x1];
250         u8         reserved_at_b[0x1];
251         u8         outer_sip[0x1];
252         u8         outer_dip[0x1];
253         u8         outer_frag[0x1];
254         u8         outer_ip_protocol[0x1];
255         u8         outer_ip_ecn[0x1];
256         u8         outer_ip_dscp[0x1];
257         u8         outer_udp_sport[0x1];
258         u8         outer_udp_dport[0x1];
259         u8         outer_tcp_sport[0x1];
260         u8         outer_tcp_dport[0x1];
261         u8         outer_tcp_flags[0x1];
262         u8         outer_gre_protocol[0x1];
263         u8         outer_gre_key[0x1];
264         u8         outer_vxlan_vni[0x1];
265         u8         reserved_at_1a[0x5];
266         u8         source_eswitch_port[0x1];
267
268         u8         inner_dmac[0x1];
269         u8         inner_smac[0x1];
270         u8         inner_ether_type[0x1];
271         u8         inner_ip_version[0x1];
272         u8         inner_first_prio[0x1];
273         u8         inner_first_cfi[0x1];
274         u8         inner_first_vid[0x1];
275         u8         reserved_at_27[0x1];
276         u8         inner_second_prio[0x1];
277         u8         inner_second_cfi[0x1];
278         u8         inner_second_vid[0x1];
279         u8         reserved_at_2b[0x1];
280         u8         inner_sip[0x1];
281         u8         inner_dip[0x1];
282         u8         inner_frag[0x1];
283         u8         inner_ip_protocol[0x1];
284         u8         inner_ip_ecn[0x1];
285         u8         inner_ip_dscp[0x1];
286         u8         inner_udp_sport[0x1];
287         u8         inner_udp_dport[0x1];
288         u8         inner_tcp_sport[0x1];
289         u8         inner_tcp_dport[0x1];
290         u8         inner_tcp_flags[0x1];
291         u8         reserved_at_37[0x9];
292
293         u8         reserved_at_40[0x40];
294 };
295
296 struct mlx5_ifc_flow_table_prop_layout_bits {
297         u8         ft_support[0x1];
298         u8         reserved_at_1[0x1];
299         u8         flow_counter[0x1];
300         u8         flow_modify_en[0x1];
301         u8         modify_root[0x1];
302         u8         identified_miss_table_mode[0x1];
303         u8         flow_table_modify[0x1];
304         u8         encap[0x1];
305         u8         decap[0x1];
306         u8         reserved_at_9[0x17];
307
308         u8         reserved_at_20[0x2];
309         u8         log_max_ft_size[0x6];
310         u8         log_max_modify_header_context[0x8];
311         u8         max_modify_header_actions[0x8];
312         u8         max_ft_level[0x8];
313
314         u8         reserved_at_40[0x20];
315
316         u8         reserved_at_60[0x18];
317         u8         log_max_ft_num[0x8];
318
319         u8         reserved_at_80[0x18];
320         u8         log_max_destination[0x8];
321
322         u8         reserved_at_a0[0x18];
323         u8         log_max_flow[0x8];
324
325         u8         reserved_at_c0[0x40];
326
327         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
328
329         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
330 };
331
332 struct mlx5_ifc_odp_per_transport_service_cap_bits {
333         u8         send[0x1];
334         u8         receive[0x1];
335         u8         write[0x1];
336         u8         read[0x1];
337         u8         atomic[0x1];
338         u8         srq_receive[0x1];
339         u8         reserved_at_6[0x1a];
340 };
341
342 struct mlx5_ifc_ipv4_layout_bits {
343         u8         reserved_at_0[0x60];
344
345         u8         ipv4[0x20];
346 };
347
348 struct mlx5_ifc_ipv6_layout_bits {
349         u8         ipv6[16][0x8];
350 };
351
352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
353         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
354         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
355         u8         reserved_at_0[0x80];
356 };
357
358 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
359         u8         smac_47_16[0x20];
360
361         u8         smac_15_0[0x10];
362         u8         ethertype[0x10];
363
364         u8         dmac_47_16[0x20];
365
366         u8         dmac_15_0[0x10];
367         u8         first_prio[0x3];
368         u8         first_cfi[0x1];
369         u8         first_vid[0xc];
370
371         u8         ip_protocol[0x8];
372         u8         ip_dscp[0x6];
373         u8         ip_ecn[0x2];
374         u8         cvlan_tag[0x1];
375         u8         svlan_tag[0x1];
376         u8         frag[0x1];
377         u8         ip_version[0x4];
378         u8         tcp_flags[0x9];
379
380         u8         tcp_sport[0x10];
381         u8         tcp_dport[0x10];
382
383         u8         reserved_at_c0[0x18];
384         u8         ttl_hoplimit[0x8];
385
386         u8         udp_sport[0x10];
387         u8         udp_dport[0x10];
388
389         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
390
391         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
392 };
393
394 struct mlx5_ifc_fte_match_set_misc_bits {
395         u8         reserved_at_0[0x8];
396         u8         source_sqn[0x18];
397
398         u8         reserved_at_20[0x10];
399         u8         source_port[0x10];
400
401         u8         outer_second_prio[0x3];
402         u8         outer_second_cfi[0x1];
403         u8         outer_second_vid[0xc];
404         u8         inner_second_prio[0x3];
405         u8         inner_second_cfi[0x1];
406         u8         inner_second_vid[0xc];
407
408         u8         outer_second_cvlan_tag[0x1];
409         u8         inner_second_cvlan_tag[0x1];
410         u8         outer_second_svlan_tag[0x1];
411         u8         inner_second_svlan_tag[0x1];
412         u8         reserved_at_64[0xc];
413         u8         gre_protocol[0x10];
414
415         u8         gre_key_h[0x18];
416         u8         gre_key_l[0x8];
417
418         u8         vxlan_vni[0x18];
419         u8         reserved_at_b8[0x8];
420
421         u8         reserved_at_c0[0x20];
422
423         u8         reserved_at_e0[0xc];
424         u8         outer_ipv6_flow_label[0x14];
425
426         u8         reserved_at_100[0xc];
427         u8         inner_ipv6_flow_label[0x14];
428
429         u8         reserved_at_120[0xe0];
430 };
431
432 struct mlx5_ifc_cmd_pas_bits {
433         u8         pa_h[0x20];
434
435         u8         pa_l[0x14];
436         u8         reserved_at_34[0xc];
437 };
438
439 struct mlx5_ifc_uint64_bits {
440         u8         hi[0x20];
441
442         u8         lo[0x20];
443 };
444
445 enum {
446         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
447         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
448         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
449         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
450         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
451         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
452         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
453         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
454         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
455         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
456 };
457
458 struct mlx5_ifc_ads_bits {
459         u8         fl[0x1];
460         u8         free_ar[0x1];
461         u8         reserved_at_2[0xe];
462         u8         pkey_index[0x10];
463
464         u8         reserved_at_20[0x8];
465         u8         grh[0x1];
466         u8         mlid[0x7];
467         u8         rlid[0x10];
468
469         u8         ack_timeout[0x5];
470         u8         reserved_at_45[0x3];
471         u8         src_addr_index[0x8];
472         u8         reserved_at_50[0x4];
473         u8         stat_rate[0x4];
474         u8         hop_limit[0x8];
475
476         u8         reserved_at_60[0x4];
477         u8         tclass[0x8];
478         u8         flow_label[0x14];
479
480         u8         rgid_rip[16][0x8];
481
482         u8         reserved_at_100[0x4];
483         u8         f_dscp[0x1];
484         u8         f_ecn[0x1];
485         u8         reserved_at_106[0x1];
486         u8         f_eth_prio[0x1];
487         u8         ecn[0x2];
488         u8         dscp[0x6];
489         u8         udp_sport[0x10];
490
491         u8         dei_cfi[0x1];
492         u8         eth_prio[0x3];
493         u8         sl[0x4];
494         u8         port[0x8];
495         u8         rmac_47_32[0x10];
496
497         u8         rmac_31_0[0x20];
498 };
499
500 struct mlx5_ifc_flow_table_nic_cap_bits {
501         u8         nic_rx_multi_path_tirs[0x1];
502         u8         nic_rx_multi_path_tirs_fts[0x1];
503         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
504         u8         reserved_at_3[0x1fd];
505
506         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
507
508         u8         reserved_at_400[0x200];
509
510         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
511
512         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
513
514         u8         reserved_at_a00[0x200];
515
516         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
517
518         u8         reserved_at_e00[0x7200];
519 };
520
521 struct mlx5_ifc_flow_table_eswitch_cap_bits {
522         u8     reserved_at_0[0x200];
523
524         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
525
526         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
527
528         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
529
530         u8      reserved_at_800[0x7800];
531 };
532
533 struct mlx5_ifc_e_switch_cap_bits {
534         u8         vport_svlan_strip[0x1];
535         u8         vport_cvlan_strip[0x1];
536         u8         vport_svlan_insert[0x1];
537         u8         vport_cvlan_insert_if_not_exist[0x1];
538         u8         vport_cvlan_insert_overwrite[0x1];
539         u8         reserved_at_5[0x19];
540         u8         nic_vport_node_guid_modify[0x1];
541         u8         nic_vport_port_guid_modify[0x1];
542
543         u8         vxlan_encap_decap[0x1];
544         u8         nvgre_encap_decap[0x1];
545         u8         reserved_at_22[0x9];
546         u8         log_max_encap_headers[0x5];
547         u8         reserved_2b[0x6];
548         u8         max_encap_header_size[0xa];
549
550         u8         reserved_40[0x7c0];
551
552 };
553
554 struct mlx5_ifc_qos_cap_bits {
555         u8         packet_pacing[0x1];
556         u8         esw_scheduling[0x1];
557         u8         esw_bw_share[0x1];
558         u8         esw_rate_limit[0x1];
559         u8         reserved_at_4[0x1c];
560
561         u8         reserved_at_20[0x20];
562
563         u8         packet_pacing_max_rate[0x20];
564
565         u8         packet_pacing_min_rate[0x20];
566
567         u8         reserved_at_80[0x10];
568         u8         packet_pacing_rate_table_size[0x10];
569
570         u8         esw_element_type[0x10];
571         u8         esw_tsar_type[0x10];
572
573         u8         reserved_at_c0[0x10];
574         u8         max_qos_para_vport[0x10];
575
576         u8         max_tsar_bw_share[0x20];
577
578         u8         reserved_at_100[0x700];
579 };
580
581 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
582         u8         csum_cap[0x1];
583         u8         vlan_cap[0x1];
584         u8         lro_cap[0x1];
585         u8         lro_psh_flag[0x1];
586         u8         lro_time_stamp[0x1];
587         u8         reserved_at_5[0x2];
588         u8         wqe_vlan_insert[0x1];
589         u8         self_lb_en_modifiable[0x1];
590         u8         reserved_at_9[0x2];
591         u8         max_lso_cap[0x5];
592         u8         multi_pkt_send_wqe[0x2];
593         u8         wqe_inline_mode[0x2];
594         u8         rss_ind_tbl_cap[0x4];
595         u8         reg_umr_sq[0x1];
596         u8         scatter_fcs[0x1];
597         u8         reserved_at_1a[0x1];
598         u8         tunnel_lso_const_out_ip_id[0x1];
599         u8         reserved_at_1c[0x2];
600         u8         tunnel_statless_gre[0x1];
601         u8         tunnel_stateless_vxlan[0x1];
602
603         u8         reserved_at_20[0x20];
604
605         u8         reserved_at_40[0x10];
606         u8         lro_min_mss_size[0x10];
607
608         u8         reserved_at_60[0x120];
609
610         u8         lro_timer_supported_periods[4][0x20];
611
612         u8         reserved_at_200[0x600];
613 };
614
615 struct mlx5_ifc_roce_cap_bits {
616         u8         roce_apm[0x1];
617         u8         reserved_at_1[0x1f];
618
619         u8         reserved_at_20[0x60];
620
621         u8         reserved_at_80[0xc];
622         u8         l3_type[0x4];
623         u8         reserved_at_90[0x8];
624         u8         roce_version[0x8];
625
626         u8         reserved_at_a0[0x10];
627         u8         r_roce_dest_udp_port[0x10];
628
629         u8         r_roce_max_src_udp_port[0x10];
630         u8         r_roce_min_src_udp_port[0x10];
631
632         u8         reserved_at_e0[0x10];
633         u8         roce_address_table_size[0x10];
634
635         u8         reserved_at_100[0x700];
636 };
637
638 enum {
639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
648 };
649
650 enum {
651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
660 };
661
662 struct mlx5_ifc_atomic_caps_bits {
663         u8         reserved_at_0[0x40];
664
665         u8         atomic_req_8B_endianness_mode[0x2];
666         u8         reserved_at_42[0x4];
667         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
668
669         u8         reserved_at_47[0x19];
670
671         u8         reserved_at_60[0x20];
672
673         u8         reserved_at_80[0x10];
674         u8         atomic_operations[0x10];
675
676         u8         reserved_at_a0[0x10];
677         u8         atomic_size_qp[0x10];
678
679         u8         reserved_at_c0[0x10];
680         u8         atomic_size_dc[0x10];
681
682         u8         reserved_at_e0[0x720];
683 };
684
685 struct mlx5_ifc_odp_cap_bits {
686         u8         reserved_at_0[0x40];
687
688         u8         sig[0x1];
689         u8         reserved_at_41[0x1f];
690
691         u8         reserved_at_60[0x20];
692
693         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
694
695         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
696
697         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
698
699         u8         reserved_at_e0[0x720];
700 };
701
702 struct mlx5_ifc_calc_op {
703         u8        reserved_at_0[0x10];
704         u8        reserved_at_10[0x9];
705         u8        op_swap_endianness[0x1];
706         u8        op_min[0x1];
707         u8        op_xor[0x1];
708         u8        op_or[0x1];
709         u8        op_and[0x1];
710         u8        op_max[0x1];
711         u8        op_add[0x1];
712 };
713
714 struct mlx5_ifc_vector_calc_cap_bits {
715         u8         calc_matrix[0x1];
716         u8         reserved_at_1[0x1f];
717         u8         reserved_at_20[0x8];
718         u8         max_vec_count[0x8];
719         u8         reserved_at_30[0xd];
720         u8         max_chunk_size[0x3];
721         struct mlx5_ifc_calc_op calc0;
722         struct mlx5_ifc_calc_op calc1;
723         struct mlx5_ifc_calc_op calc2;
724         struct mlx5_ifc_calc_op calc3;
725
726         u8         reserved_at_e0[0x720];
727 };
728
729 enum {
730         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
731         MLX5_WQ_TYPE_CYCLIC       = 0x1,
732         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
733 };
734
735 enum {
736         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
737         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
738 };
739
740 enum {
741         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
742         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
743         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
744         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
745         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
746 };
747
748 enum {
749         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
750         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
751         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
752         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
753         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
754         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
755 };
756
757 enum {
758         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
759         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
760 };
761
762 enum {
763         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
764         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
765         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
766 };
767
768 enum {
769         MLX5_CAP_PORT_TYPE_IB  = 0x0,
770         MLX5_CAP_PORT_TYPE_ETH = 0x1,
771 };
772
773 enum {
774         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
775         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
776         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
777 };
778
779 struct mlx5_ifc_cmd_hca_cap_bits {
780         u8         reserved_at_0[0x80];
781
782         u8         log_max_srq_sz[0x8];
783         u8         log_max_qp_sz[0x8];
784         u8         reserved_at_90[0xb];
785         u8         log_max_qp[0x5];
786
787         u8         reserved_at_a0[0xb];
788         u8         log_max_srq[0x5];
789         u8         reserved_at_b0[0x10];
790
791         u8         reserved_at_c0[0x8];
792         u8         log_max_cq_sz[0x8];
793         u8         reserved_at_d0[0xb];
794         u8         log_max_cq[0x5];
795
796         u8         log_max_eq_sz[0x8];
797         u8         reserved_at_e8[0x2];
798         u8         log_max_mkey[0x6];
799         u8         reserved_at_f0[0xc];
800         u8         log_max_eq[0x4];
801
802         u8         max_indirection[0x8];
803         u8         fixed_buffer_size[0x1];
804         u8         log_max_mrw_sz[0x7];
805         u8         force_teardown[0x1];
806         u8         reserved_at_111[0x1];
807         u8         log_max_bsf_list_size[0x6];
808         u8         umr_extended_translation_offset[0x1];
809         u8         null_mkey[0x1];
810         u8         log_max_klm_list_size[0x6];
811
812         u8         reserved_at_120[0xa];
813         u8         log_max_ra_req_dc[0x6];
814         u8         reserved_at_130[0xa];
815         u8         log_max_ra_res_dc[0x6];
816
817         u8         reserved_at_140[0xa];
818         u8         log_max_ra_req_qp[0x6];
819         u8         reserved_at_150[0xa];
820         u8         log_max_ra_res_qp[0x6];
821
822         u8         end_pad[0x1];
823         u8         cc_query_allowed[0x1];
824         u8         cc_modify_allowed[0x1];
825         u8         start_pad[0x1];
826         u8         cache_line_128byte[0x1];
827         u8         reserved_at_163[0xb];
828         u8         gid_table_size[0x10];
829
830         u8         out_of_seq_cnt[0x1];
831         u8         vport_counters[0x1];
832         u8         retransmission_q_counters[0x1];
833         u8         reserved_at_183[0x1];
834         u8         modify_rq_counter_set_id[0x1];
835         u8         reserved_at_185[0x1];
836         u8         max_qp_cnt[0xa];
837         u8         pkey_table_size[0x10];
838
839         u8         vport_group_manager[0x1];
840         u8         vhca_group_manager[0x1];
841         u8         ib_virt[0x1];
842         u8         eth_virt[0x1];
843         u8         reserved_at_1a4[0x1];
844         u8         ets[0x1];
845         u8         nic_flow_table[0x1];
846         u8         eswitch_flow_table[0x1];
847         u8         early_vf_enable[0x1];
848         u8         mcam_reg[0x1];
849         u8         pcam_reg[0x1];
850         u8         local_ca_ack_delay[0x5];
851         u8         port_module_event[0x1];
852         u8         reserved_at_1b1[0x1];
853         u8         ports_check[0x1];
854         u8         reserved_at_1b3[0x1];
855         u8         disable_link_up[0x1];
856         u8         beacon_led[0x1];
857         u8         port_type[0x2];
858         u8         num_ports[0x8];
859
860         u8         reserved_at_1c0[0x1];
861         u8         pps[0x1];
862         u8         pps_modify[0x1];
863         u8         log_max_msg[0x5];
864         u8         reserved_at_1c8[0x4];
865         u8         max_tc[0x4];
866         u8         reserved_at_1d0[0x1];
867         u8         dcbx[0x1];
868         u8         reserved_at_1d2[0x3];
869         u8         fpga[0x1];
870         u8         rol_s[0x1];
871         u8         rol_g[0x1];
872         u8         reserved_at_1d8[0x1];
873         u8         wol_s[0x1];
874         u8         wol_g[0x1];
875         u8         wol_a[0x1];
876         u8         wol_b[0x1];
877         u8         wol_m[0x1];
878         u8         wol_u[0x1];
879         u8         wol_p[0x1];
880
881         u8         stat_rate_support[0x10];
882         u8         reserved_at_1f0[0xc];
883         u8         cqe_version[0x4];
884
885         u8         compact_address_vector[0x1];
886         u8         striding_rq[0x1];
887         u8         reserved_at_202[0x1];
888         u8         ipoib_enhanced_offloads[0x1];
889         u8         ipoib_basic_offloads[0x1];
890         u8         reserved_at_205[0x5];
891         u8         umr_fence[0x2];
892         u8         reserved_at_20c[0x3];
893         u8         drain_sigerr[0x1];
894         u8         cmdif_checksum[0x2];
895         u8         sigerr_cqe[0x1];
896         u8         reserved_at_213[0x1];
897         u8         wq_signature[0x1];
898         u8         sctr_data_cqe[0x1];
899         u8         reserved_at_216[0x1];
900         u8         sho[0x1];
901         u8         tph[0x1];
902         u8         rf[0x1];
903         u8         dct[0x1];
904         u8         qos[0x1];
905         u8         eth_net_offloads[0x1];
906         u8         roce[0x1];
907         u8         atomic[0x1];
908         u8         reserved_at_21f[0x1];
909
910         u8         cq_oi[0x1];
911         u8         cq_resize[0x1];
912         u8         cq_moderation[0x1];
913         u8         reserved_at_223[0x3];
914         u8         cq_eq_remap[0x1];
915         u8         pg[0x1];
916         u8         block_lb_mc[0x1];
917         u8         reserved_at_229[0x1];
918         u8         scqe_break_moderation[0x1];
919         u8         cq_period_start_from_cqe[0x1];
920         u8         cd[0x1];
921         u8         reserved_at_22d[0x1];
922         u8         apm[0x1];
923         u8         vector_calc[0x1];
924         u8         umr_ptr_rlky[0x1];
925         u8         imaicl[0x1];
926         u8         reserved_at_232[0x4];
927         u8         qkv[0x1];
928         u8         pkv[0x1];
929         u8         set_deth_sqpn[0x1];
930         u8         reserved_at_239[0x3];
931         u8         xrc[0x1];
932         u8         ud[0x1];
933         u8         uc[0x1];
934         u8         rc[0x1];
935
936         u8         uar_4k[0x1];
937         u8         reserved_at_241[0x9];
938         u8         uar_sz[0x6];
939         u8         reserved_at_250[0x8];
940         u8         log_pg_sz[0x8];
941
942         u8         bf[0x1];
943         u8         driver_version[0x1];
944         u8         pad_tx_eth_packet[0x1];
945         u8         reserved_at_263[0x8];
946         u8         log_bf_reg_size[0x5];
947
948         u8         reserved_at_270[0xb];
949         u8         lag_master[0x1];
950         u8         num_lag_ports[0x4];
951
952         u8         reserved_at_280[0x10];
953         u8         max_wqe_sz_sq[0x10];
954
955         u8         reserved_at_2a0[0x10];
956         u8         max_wqe_sz_rq[0x10];
957
958         u8         reserved_at_2c0[0x10];
959         u8         max_wqe_sz_sq_dc[0x10];
960
961         u8         reserved_at_2e0[0x7];
962         u8         max_qp_mcg[0x19];
963
964         u8         reserved_at_300[0x18];
965         u8         log_max_mcg[0x8];
966
967         u8         reserved_at_320[0x3];
968         u8         log_max_transport_domain[0x5];
969         u8         reserved_at_328[0x3];
970         u8         log_max_pd[0x5];
971         u8         reserved_at_330[0xb];
972         u8         log_max_xrcd[0x5];
973
974         u8         reserved_at_340[0x8];
975         u8         log_max_flow_counter_bulk[0x8];
976         u8         max_flow_counter[0x10];
977
978
979         u8         reserved_at_360[0x3];
980         u8         log_max_rq[0x5];
981         u8         reserved_at_368[0x3];
982         u8         log_max_sq[0x5];
983         u8         reserved_at_370[0x3];
984         u8         log_max_tir[0x5];
985         u8         reserved_at_378[0x3];
986         u8         log_max_tis[0x5];
987
988         u8         basic_cyclic_rcv_wqe[0x1];
989         u8         reserved_at_381[0x2];
990         u8         log_max_rmp[0x5];
991         u8         reserved_at_388[0x3];
992         u8         log_max_rqt[0x5];
993         u8         reserved_at_390[0x3];
994         u8         log_max_rqt_size[0x5];
995         u8         reserved_at_398[0x3];
996         u8         log_max_tis_per_sq[0x5];
997
998         u8         reserved_at_3a0[0x3];
999         u8         log_max_stride_sz_rq[0x5];
1000         u8         reserved_at_3a8[0x3];
1001         u8         log_min_stride_sz_rq[0x5];
1002         u8         reserved_at_3b0[0x3];
1003         u8         log_max_stride_sz_sq[0x5];
1004         u8         reserved_at_3b8[0x3];
1005         u8         log_min_stride_sz_sq[0x5];
1006
1007         u8         reserved_at_3c0[0x1b];
1008         u8         log_max_wq_sz[0x5];
1009
1010         u8         nic_vport_change_event[0x1];
1011         u8         reserved_at_3e1[0xa];
1012         u8         log_max_vlan_list[0x5];
1013         u8         reserved_at_3f0[0x3];
1014         u8         log_max_current_mc_list[0x5];
1015         u8         reserved_at_3f8[0x3];
1016         u8         log_max_current_uc_list[0x5];
1017
1018         u8         reserved_at_400[0x80];
1019
1020         u8         reserved_at_480[0x3];
1021         u8         log_max_l2_table[0x5];
1022         u8         reserved_at_488[0x8];
1023         u8         log_uar_page_sz[0x10];
1024
1025         u8         reserved_at_4a0[0x20];
1026         u8         device_frequency_mhz[0x20];
1027         u8         device_frequency_khz[0x20];
1028
1029         u8         reserved_at_500[0x20];
1030         u8         num_of_uars_per_page[0x20];
1031         u8         reserved_at_540[0x40];
1032
1033         u8         reserved_at_580[0x3f];
1034         u8         cqe_compression[0x1];
1035
1036         u8         cqe_compression_timeout[0x10];
1037         u8         cqe_compression_max_num[0x10];
1038
1039         u8         reserved_at_5e0[0x10];
1040         u8         tag_matching[0x1];
1041         u8         rndv_offload_rc[0x1];
1042         u8         rndv_offload_dc[0x1];
1043         u8         log_tag_matching_list_sz[0x5];
1044         u8         reserved_at_5f8[0x3];
1045         u8         log_max_xrq[0x5];
1046
1047         u8         reserved_at_600[0x200];
1048 };
1049
1050 enum mlx5_flow_destination_type {
1051         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1052         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1053         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1054
1055         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1056 };
1057
1058 struct mlx5_ifc_dest_format_struct_bits {
1059         u8         destination_type[0x8];
1060         u8         destination_id[0x18];
1061
1062         u8         reserved_at_20[0x20];
1063 };
1064
1065 struct mlx5_ifc_flow_counter_list_bits {
1066         u8         clear[0x1];
1067         u8         num_of_counters[0xf];
1068         u8         flow_counter_id[0x10];
1069
1070         u8         reserved_at_20[0x20];
1071 };
1072
1073 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1074         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1075         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1076         u8         reserved_at_0[0x40];
1077 };
1078
1079 struct mlx5_ifc_fte_match_param_bits {
1080         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1081
1082         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1083
1084         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1085
1086         u8         reserved_at_600[0xa00];
1087 };
1088
1089 enum {
1090         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1091         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1092         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1093         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1094         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1095 };
1096
1097 struct mlx5_ifc_rx_hash_field_select_bits {
1098         u8         l3_prot_type[0x1];
1099         u8         l4_prot_type[0x1];
1100         u8         selected_fields[0x1e];
1101 };
1102
1103 enum {
1104         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1105         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1106 };
1107
1108 enum {
1109         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1110         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1111 };
1112
1113 struct mlx5_ifc_wq_bits {
1114         u8         wq_type[0x4];
1115         u8         wq_signature[0x1];
1116         u8         end_padding_mode[0x2];
1117         u8         cd_slave[0x1];
1118         u8         reserved_at_8[0x18];
1119
1120         u8         hds_skip_first_sge[0x1];
1121         u8         log2_hds_buf_size[0x3];
1122         u8         reserved_at_24[0x7];
1123         u8         page_offset[0x5];
1124         u8         lwm[0x10];
1125
1126         u8         reserved_at_40[0x8];
1127         u8         pd[0x18];
1128
1129         u8         reserved_at_60[0x8];
1130         u8         uar_page[0x18];
1131
1132         u8         dbr_addr[0x40];
1133
1134         u8         hw_counter[0x20];
1135
1136         u8         sw_counter[0x20];
1137
1138         u8         reserved_at_100[0xc];
1139         u8         log_wq_stride[0x4];
1140         u8         reserved_at_110[0x3];
1141         u8         log_wq_pg_sz[0x5];
1142         u8         reserved_at_118[0x3];
1143         u8         log_wq_sz[0x5];
1144
1145         u8         reserved_at_120[0x15];
1146         u8         log_wqe_num_of_strides[0x3];
1147         u8         two_byte_shift_en[0x1];
1148         u8         reserved_at_139[0x4];
1149         u8         log_wqe_stride_size[0x3];
1150
1151         u8         reserved_at_140[0x4c0];
1152
1153         struct mlx5_ifc_cmd_pas_bits pas[0];
1154 };
1155
1156 struct mlx5_ifc_rq_num_bits {
1157         u8         reserved_at_0[0x8];
1158         u8         rq_num[0x18];
1159 };
1160
1161 struct mlx5_ifc_mac_address_layout_bits {
1162         u8         reserved_at_0[0x10];
1163         u8         mac_addr_47_32[0x10];
1164
1165         u8         mac_addr_31_0[0x20];
1166 };
1167
1168 struct mlx5_ifc_vlan_layout_bits {
1169         u8         reserved_at_0[0x14];
1170         u8         vlan[0x0c];
1171
1172         u8         reserved_at_20[0x20];
1173 };
1174
1175 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1176         u8         reserved_at_0[0xa0];
1177
1178         u8         min_time_between_cnps[0x20];
1179
1180         u8         reserved_at_c0[0x12];
1181         u8         cnp_dscp[0x6];
1182         u8         reserved_at_d8[0x5];
1183         u8         cnp_802p_prio[0x3];
1184
1185         u8         reserved_at_e0[0x720];
1186 };
1187
1188 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1189         u8         reserved_at_0[0x60];
1190
1191         u8         reserved_at_60[0x4];
1192         u8         clamp_tgt_rate[0x1];
1193         u8         reserved_at_65[0x3];
1194         u8         clamp_tgt_rate_after_time_inc[0x1];
1195         u8         reserved_at_69[0x17];
1196
1197         u8         reserved_at_80[0x20];
1198
1199         u8         rpg_time_reset[0x20];
1200
1201         u8         rpg_byte_reset[0x20];
1202
1203         u8         rpg_threshold[0x20];
1204
1205         u8         rpg_max_rate[0x20];
1206
1207         u8         rpg_ai_rate[0x20];
1208
1209         u8         rpg_hai_rate[0x20];
1210
1211         u8         rpg_gd[0x20];
1212
1213         u8         rpg_min_dec_fac[0x20];
1214
1215         u8         rpg_min_rate[0x20];
1216
1217         u8         reserved_at_1c0[0xe0];
1218
1219         u8         rate_to_set_on_first_cnp[0x20];
1220
1221         u8         dce_tcp_g[0x20];
1222
1223         u8         dce_tcp_rtt[0x20];
1224
1225         u8         rate_reduce_monitor_period[0x20];
1226
1227         u8         reserved_at_320[0x20];
1228
1229         u8         initial_alpha_value[0x20];
1230
1231         u8         reserved_at_360[0x4a0];
1232 };
1233
1234 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1235         u8         reserved_at_0[0x80];
1236
1237         u8         rppp_max_rps[0x20];
1238
1239         u8         rpg_time_reset[0x20];
1240
1241         u8         rpg_byte_reset[0x20];
1242
1243         u8         rpg_threshold[0x20];
1244
1245         u8         rpg_max_rate[0x20];
1246
1247         u8         rpg_ai_rate[0x20];
1248
1249         u8         rpg_hai_rate[0x20];
1250
1251         u8         rpg_gd[0x20];
1252
1253         u8         rpg_min_dec_fac[0x20];
1254
1255         u8         rpg_min_rate[0x20];
1256
1257         u8         reserved_at_1c0[0x640];
1258 };
1259
1260 enum {
1261         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1262         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1263         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1264 };
1265
1266 struct mlx5_ifc_resize_field_select_bits {
1267         u8         resize_field_select[0x20];
1268 };
1269
1270 enum {
1271         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1272         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1273         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1274         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1275 };
1276
1277 struct mlx5_ifc_modify_field_select_bits {
1278         u8         modify_field_select[0x20];
1279 };
1280
1281 struct mlx5_ifc_field_select_r_roce_np_bits {
1282         u8         field_select_r_roce_np[0x20];
1283 };
1284
1285 struct mlx5_ifc_field_select_r_roce_rp_bits {
1286         u8         field_select_r_roce_rp[0x20];
1287 };
1288
1289 enum {
1290         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1291         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1292         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1293         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1294         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1295         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1296         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1297         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1298         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1299         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1300 };
1301
1302 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1303         u8         field_select_8021qaurp[0x20];
1304 };
1305
1306 struct mlx5_ifc_phys_layer_cntrs_bits {
1307         u8         time_since_last_clear_high[0x20];
1308
1309         u8         time_since_last_clear_low[0x20];
1310
1311         u8         symbol_errors_high[0x20];
1312
1313         u8         symbol_errors_low[0x20];
1314
1315         u8         sync_headers_errors_high[0x20];
1316
1317         u8         sync_headers_errors_low[0x20];
1318
1319         u8         edpl_bip_errors_lane0_high[0x20];
1320
1321         u8         edpl_bip_errors_lane0_low[0x20];
1322
1323         u8         edpl_bip_errors_lane1_high[0x20];
1324
1325         u8         edpl_bip_errors_lane1_low[0x20];
1326
1327         u8         edpl_bip_errors_lane2_high[0x20];
1328
1329         u8         edpl_bip_errors_lane2_low[0x20];
1330
1331         u8         edpl_bip_errors_lane3_high[0x20];
1332
1333         u8         edpl_bip_errors_lane3_low[0x20];
1334
1335         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1336
1337         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1338
1339         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1340
1341         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1342
1343         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1344
1345         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1346
1347         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1348
1349         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1350
1351         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1352
1353         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1354
1355         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1356
1357         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1358
1359         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1360
1361         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1362
1363         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1364
1365         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1366
1367         u8         rs_fec_corrected_blocks_high[0x20];
1368
1369         u8         rs_fec_corrected_blocks_low[0x20];
1370
1371         u8         rs_fec_uncorrectable_blocks_high[0x20];
1372
1373         u8         rs_fec_uncorrectable_blocks_low[0x20];
1374
1375         u8         rs_fec_no_errors_blocks_high[0x20];
1376
1377         u8         rs_fec_no_errors_blocks_low[0x20];
1378
1379         u8         rs_fec_single_error_blocks_high[0x20];
1380
1381         u8         rs_fec_single_error_blocks_low[0x20];
1382
1383         u8         rs_fec_corrected_symbols_total_high[0x20];
1384
1385         u8         rs_fec_corrected_symbols_total_low[0x20];
1386
1387         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1388
1389         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1390
1391         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1392
1393         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1394
1395         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1396
1397         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1398
1399         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1400
1401         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1402
1403         u8         link_down_events[0x20];
1404
1405         u8         successful_recovery_events[0x20];
1406
1407         u8         reserved_at_640[0x180];
1408 };
1409
1410 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1411         u8         time_since_last_clear_high[0x20];
1412
1413         u8         time_since_last_clear_low[0x20];
1414
1415         u8         phy_received_bits_high[0x20];
1416
1417         u8         phy_received_bits_low[0x20];
1418
1419         u8         phy_symbol_errors_high[0x20];
1420
1421         u8         phy_symbol_errors_low[0x20];
1422
1423         u8         phy_corrected_bits_high[0x20];
1424
1425         u8         phy_corrected_bits_low[0x20];
1426
1427         u8         phy_corrected_bits_lane0_high[0x20];
1428
1429         u8         phy_corrected_bits_lane0_low[0x20];
1430
1431         u8         phy_corrected_bits_lane1_high[0x20];
1432
1433         u8         phy_corrected_bits_lane1_low[0x20];
1434
1435         u8         phy_corrected_bits_lane2_high[0x20];
1436
1437         u8         phy_corrected_bits_lane2_low[0x20];
1438
1439         u8         phy_corrected_bits_lane3_high[0x20];
1440
1441         u8         phy_corrected_bits_lane3_low[0x20];
1442
1443         u8         reserved_at_200[0x5c0];
1444 };
1445
1446 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1447         u8         symbol_error_counter[0x10];
1448
1449         u8         link_error_recovery_counter[0x8];
1450
1451         u8         link_downed_counter[0x8];
1452
1453         u8         port_rcv_errors[0x10];
1454
1455         u8         port_rcv_remote_physical_errors[0x10];
1456
1457         u8         port_rcv_switch_relay_errors[0x10];
1458
1459         u8         port_xmit_discards[0x10];
1460
1461         u8         port_xmit_constraint_errors[0x8];
1462
1463         u8         port_rcv_constraint_errors[0x8];
1464
1465         u8         reserved_at_70[0x8];
1466
1467         u8         link_overrun_errors[0x8];
1468
1469         u8         reserved_at_80[0x10];
1470
1471         u8         vl_15_dropped[0x10];
1472
1473         u8         reserved_at_a0[0x80];
1474
1475         u8         port_xmit_wait[0x20];
1476 };
1477
1478 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1479         u8         transmit_queue_high[0x20];
1480
1481         u8         transmit_queue_low[0x20];
1482
1483         u8         reserved_at_40[0x780];
1484 };
1485
1486 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1487         u8         rx_octets_high[0x20];
1488
1489         u8         rx_octets_low[0x20];
1490
1491         u8         reserved_at_40[0xc0];
1492
1493         u8         rx_frames_high[0x20];
1494
1495         u8         rx_frames_low[0x20];
1496
1497         u8         tx_octets_high[0x20];
1498
1499         u8         tx_octets_low[0x20];
1500
1501         u8         reserved_at_180[0xc0];
1502
1503         u8         tx_frames_high[0x20];
1504
1505         u8         tx_frames_low[0x20];
1506
1507         u8         rx_pause_high[0x20];
1508
1509         u8         rx_pause_low[0x20];
1510
1511         u8         rx_pause_duration_high[0x20];
1512
1513         u8         rx_pause_duration_low[0x20];
1514
1515         u8         tx_pause_high[0x20];
1516
1517         u8         tx_pause_low[0x20];
1518
1519         u8         tx_pause_duration_high[0x20];
1520
1521         u8         tx_pause_duration_low[0x20];
1522
1523         u8         rx_pause_transition_high[0x20];
1524
1525         u8         rx_pause_transition_low[0x20];
1526
1527         u8         reserved_at_3c0[0x400];
1528 };
1529
1530 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1531         u8         port_transmit_wait_high[0x20];
1532
1533         u8         port_transmit_wait_low[0x20];
1534
1535         u8         reserved_at_40[0x780];
1536 };
1537
1538 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1539         u8         dot3stats_alignment_errors_high[0x20];
1540
1541         u8         dot3stats_alignment_errors_low[0x20];
1542
1543         u8         dot3stats_fcs_errors_high[0x20];
1544
1545         u8         dot3stats_fcs_errors_low[0x20];
1546
1547         u8         dot3stats_single_collision_frames_high[0x20];
1548
1549         u8         dot3stats_single_collision_frames_low[0x20];
1550
1551         u8         dot3stats_multiple_collision_frames_high[0x20];
1552
1553         u8         dot3stats_multiple_collision_frames_low[0x20];
1554
1555         u8         dot3stats_sqe_test_errors_high[0x20];
1556
1557         u8         dot3stats_sqe_test_errors_low[0x20];
1558
1559         u8         dot3stats_deferred_transmissions_high[0x20];
1560
1561         u8         dot3stats_deferred_transmissions_low[0x20];
1562
1563         u8         dot3stats_late_collisions_high[0x20];
1564
1565         u8         dot3stats_late_collisions_low[0x20];
1566
1567         u8         dot3stats_excessive_collisions_high[0x20];
1568
1569         u8         dot3stats_excessive_collisions_low[0x20];
1570
1571         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1572
1573         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1574
1575         u8         dot3stats_carrier_sense_errors_high[0x20];
1576
1577         u8         dot3stats_carrier_sense_errors_low[0x20];
1578
1579         u8         dot3stats_frame_too_longs_high[0x20];
1580
1581         u8         dot3stats_frame_too_longs_low[0x20];
1582
1583         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1584
1585         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1586
1587         u8         dot3stats_symbol_errors_high[0x20];
1588
1589         u8         dot3stats_symbol_errors_low[0x20];
1590
1591         u8         dot3control_in_unknown_opcodes_high[0x20];
1592
1593         u8         dot3control_in_unknown_opcodes_low[0x20];
1594
1595         u8         dot3in_pause_frames_high[0x20];
1596
1597         u8         dot3in_pause_frames_low[0x20];
1598
1599         u8         dot3out_pause_frames_high[0x20];
1600
1601         u8         dot3out_pause_frames_low[0x20];
1602
1603         u8         reserved_at_400[0x3c0];
1604 };
1605
1606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1607         u8         ether_stats_drop_events_high[0x20];
1608
1609         u8         ether_stats_drop_events_low[0x20];
1610
1611         u8         ether_stats_octets_high[0x20];
1612
1613         u8         ether_stats_octets_low[0x20];
1614
1615         u8         ether_stats_pkts_high[0x20];
1616
1617         u8         ether_stats_pkts_low[0x20];
1618
1619         u8         ether_stats_broadcast_pkts_high[0x20];
1620
1621         u8         ether_stats_broadcast_pkts_low[0x20];
1622
1623         u8         ether_stats_multicast_pkts_high[0x20];
1624
1625         u8         ether_stats_multicast_pkts_low[0x20];
1626
1627         u8         ether_stats_crc_align_errors_high[0x20];
1628
1629         u8         ether_stats_crc_align_errors_low[0x20];
1630
1631         u8         ether_stats_undersize_pkts_high[0x20];
1632
1633         u8         ether_stats_undersize_pkts_low[0x20];
1634
1635         u8         ether_stats_oversize_pkts_high[0x20];
1636
1637         u8         ether_stats_oversize_pkts_low[0x20];
1638
1639         u8         ether_stats_fragments_high[0x20];
1640
1641         u8         ether_stats_fragments_low[0x20];
1642
1643         u8         ether_stats_jabbers_high[0x20];
1644
1645         u8         ether_stats_jabbers_low[0x20];
1646
1647         u8         ether_stats_collisions_high[0x20];
1648
1649         u8         ether_stats_collisions_low[0x20];
1650
1651         u8         ether_stats_pkts64octets_high[0x20];
1652
1653         u8         ether_stats_pkts64octets_low[0x20];
1654
1655         u8         ether_stats_pkts65to127octets_high[0x20];
1656
1657         u8         ether_stats_pkts65to127octets_low[0x20];
1658
1659         u8         ether_stats_pkts128to255octets_high[0x20];
1660
1661         u8         ether_stats_pkts128to255octets_low[0x20];
1662
1663         u8         ether_stats_pkts256to511octets_high[0x20];
1664
1665         u8         ether_stats_pkts256to511octets_low[0x20];
1666
1667         u8         ether_stats_pkts512to1023octets_high[0x20];
1668
1669         u8         ether_stats_pkts512to1023octets_low[0x20];
1670
1671         u8         ether_stats_pkts1024to1518octets_high[0x20];
1672
1673         u8         ether_stats_pkts1024to1518octets_low[0x20];
1674
1675         u8         ether_stats_pkts1519to2047octets_high[0x20];
1676
1677         u8         ether_stats_pkts1519to2047octets_low[0x20];
1678
1679         u8         ether_stats_pkts2048to4095octets_high[0x20];
1680
1681         u8         ether_stats_pkts2048to4095octets_low[0x20];
1682
1683         u8         ether_stats_pkts4096to8191octets_high[0x20];
1684
1685         u8         ether_stats_pkts4096to8191octets_low[0x20];
1686
1687         u8         ether_stats_pkts8192to10239octets_high[0x20];
1688
1689         u8         ether_stats_pkts8192to10239octets_low[0x20];
1690
1691         u8         reserved_at_540[0x280];
1692 };
1693
1694 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1695         u8         if_in_octets_high[0x20];
1696
1697         u8         if_in_octets_low[0x20];
1698
1699         u8         if_in_ucast_pkts_high[0x20];
1700
1701         u8         if_in_ucast_pkts_low[0x20];
1702
1703         u8         if_in_discards_high[0x20];
1704
1705         u8         if_in_discards_low[0x20];
1706
1707         u8         if_in_errors_high[0x20];
1708
1709         u8         if_in_errors_low[0x20];
1710
1711         u8         if_in_unknown_protos_high[0x20];
1712
1713         u8         if_in_unknown_protos_low[0x20];
1714
1715         u8         if_out_octets_high[0x20];
1716
1717         u8         if_out_octets_low[0x20];
1718
1719         u8         if_out_ucast_pkts_high[0x20];
1720
1721         u8         if_out_ucast_pkts_low[0x20];
1722
1723         u8         if_out_discards_high[0x20];
1724
1725         u8         if_out_discards_low[0x20];
1726
1727         u8         if_out_errors_high[0x20];
1728
1729         u8         if_out_errors_low[0x20];
1730
1731         u8         if_in_multicast_pkts_high[0x20];
1732
1733         u8         if_in_multicast_pkts_low[0x20];
1734
1735         u8         if_in_broadcast_pkts_high[0x20];
1736
1737         u8         if_in_broadcast_pkts_low[0x20];
1738
1739         u8         if_out_multicast_pkts_high[0x20];
1740
1741         u8         if_out_multicast_pkts_low[0x20];
1742
1743         u8         if_out_broadcast_pkts_high[0x20];
1744
1745         u8         if_out_broadcast_pkts_low[0x20];
1746
1747         u8         reserved_at_340[0x480];
1748 };
1749
1750 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1751         u8         a_frames_transmitted_ok_high[0x20];
1752
1753         u8         a_frames_transmitted_ok_low[0x20];
1754
1755         u8         a_frames_received_ok_high[0x20];
1756
1757         u8         a_frames_received_ok_low[0x20];
1758
1759         u8         a_frame_check_sequence_errors_high[0x20];
1760
1761         u8         a_frame_check_sequence_errors_low[0x20];
1762
1763         u8         a_alignment_errors_high[0x20];
1764
1765         u8         a_alignment_errors_low[0x20];
1766
1767         u8         a_octets_transmitted_ok_high[0x20];
1768
1769         u8         a_octets_transmitted_ok_low[0x20];
1770
1771         u8         a_octets_received_ok_high[0x20];
1772
1773         u8         a_octets_received_ok_low[0x20];
1774
1775         u8         a_multicast_frames_xmitted_ok_high[0x20];
1776
1777         u8         a_multicast_frames_xmitted_ok_low[0x20];
1778
1779         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1780
1781         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1782
1783         u8         a_multicast_frames_received_ok_high[0x20];
1784
1785         u8         a_multicast_frames_received_ok_low[0x20];
1786
1787         u8         a_broadcast_frames_received_ok_high[0x20];
1788
1789         u8         a_broadcast_frames_received_ok_low[0x20];
1790
1791         u8         a_in_range_length_errors_high[0x20];
1792
1793         u8         a_in_range_length_errors_low[0x20];
1794
1795         u8         a_out_of_range_length_field_high[0x20];
1796
1797         u8         a_out_of_range_length_field_low[0x20];
1798
1799         u8         a_frame_too_long_errors_high[0x20];
1800
1801         u8         a_frame_too_long_errors_low[0x20];
1802
1803         u8         a_symbol_error_during_carrier_high[0x20];
1804
1805         u8         a_symbol_error_during_carrier_low[0x20];
1806
1807         u8         a_mac_control_frames_transmitted_high[0x20];
1808
1809         u8         a_mac_control_frames_transmitted_low[0x20];
1810
1811         u8         a_mac_control_frames_received_high[0x20];
1812
1813         u8         a_mac_control_frames_received_low[0x20];
1814
1815         u8         a_unsupported_opcodes_received_high[0x20];
1816
1817         u8         a_unsupported_opcodes_received_low[0x20];
1818
1819         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1820
1821         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1822
1823         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1824
1825         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1826
1827         u8         reserved_at_4c0[0x300];
1828 };
1829
1830 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1831         u8         life_time_counter_high[0x20];
1832
1833         u8         life_time_counter_low[0x20];
1834
1835         u8         rx_errors[0x20];
1836
1837         u8         tx_errors[0x20];
1838
1839         u8         l0_to_recovery_eieos[0x20];
1840
1841         u8         l0_to_recovery_ts[0x20];
1842
1843         u8         l0_to_recovery_framing[0x20];
1844
1845         u8         l0_to_recovery_retrain[0x20];
1846
1847         u8         crc_error_dllp[0x20];
1848
1849         u8         crc_error_tlp[0x20];
1850
1851         u8         reserved_at_140[0x680];
1852 };
1853
1854 struct mlx5_ifc_cmd_inter_comp_event_bits {
1855         u8         command_completion_vector[0x20];
1856
1857         u8         reserved_at_20[0xc0];
1858 };
1859
1860 struct mlx5_ifc_stall_vl_event_bits {
1861         u8         reserved_at_0[0x18];
1862         u8         port_num[0x1];
1863         u8         reserved_at_19[0x3];
1864         u8         vl[0x4];
1865
1866         u8         reserved_at_20[0xa0];
1867 };
1868
1869 struct mlx5_ifc_db_bf_congestion_event_bits {
1870         u8         event_subtype[0x8];
1871         u8         reserved_at_8[0x8];
1872         u8         congestion_level[0x8];
1873         u8         reserved_at_18[0x8];
1874
1875         u8         reserved_at_20[0xa0];
1876 };
1877
1878 struct mlx5_ifc_gpio_event_bits {
1879         u8         reserved_at_0[0x60];
1880
1881         u8         gpio_event_hi[0x20];
1882
1883         u8         gpio_event_lo[0x20];
1884
1885         u8         reserved_at_a0[0x40];
1886 };
1887
1888 struct mlx5_ifc_port_state_change_event_bits {
1889         u8         reserved_at_0[0x40];
1890
1891         u8         port_num[0x4];
1892         u8         reserved_at_44[0x1c];
1893
1894         u8         reserved_at_60[0x80];
1895 };
1896
1897 struct mlx5_ifc_dropped_packet_logged_bits {
1898         u8         reserved_at_0[0xe0];
1899 };
1900
1901 enum {
1902         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1903         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1904 };
1905
1906 struct mlx5_ifc_cq_error_bits {
1907         u8         reserved_at_0[0x8];
1908         u8         cqn[0x18];
1909
1910         u8         reserved_at_20[0x20];
1911
1912         u8         reserved_at_40[0x18];
1913         u8         syndrome[0x8];
1914
1915         u8         reserved_at_60[0x80];
1916 };
1917
1918 struct mlx5_ifc_rdma_page_fault_event_bits {
1919         u8         bytes_committed[0x20];
1920
1921         u8         r_key[0x20];
1922
1923         u8         reserved_at_40[0x10];
1924         u8         packet_len[0x10];
1925
1926         u8         rdma_op_len[0x20];
1927
1928         u8         rdma_va[0x40];
1929
1930         u8         reserved_at_c0[0x5];
1931         u8         rdma[0x1];
1932         u8         write[0x1];
1933         u8         requestor[0x1];
1934         u8         qp_number[0x18];
1935 };
1936
1937 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1938         u8         bytes_committed[0x20];
1939
1940         u8         reserved_at_20[0x10];
1941         u8         wqe_index[0x10];
1942
1943         u8         reserved_at_40[0x10];
1944         u8         len[0x10];
1945
1946         u8         reserved_at_60[0x60];
1947
1948         u8         reserved_at_c0[0x5];
1949         u8         rdma[0x1];
1950         u8         write_read[0x1];
1951         u8         requestor[0x1];
1952         u8         qpn[0x18];
1953 };
1954
1955 struct mlx5_ifc_qp_events_bits {
1956         u8         reserved_at_0[0xa0];
1957
1958         u8         type[0x8];
1959         u8         reserved_at_a8[0x18];
1960
1961         u8         reserved_at_c0[0x8];
1962         u8         qpn_rqn_sqn[0x18];
1963 };
1964
1965 struct mlx5_ifc_dct_events_bits {
1966         u8         reserved_at_0[0xc0];
1967
1968         u8         reserved_at_c0[0x8];
1969         u8         dct_number[0x18];
1970 };
1971
1972 struct mlx5_ifc_comp_event_bits {
1973         u8         reserved_at_0[0xc0];
1974
1975         u8         reserved_at_c0[0x8];
1976         u8         cq_number[0x18];
1977 };
1978
1979 enum {
1980         MLX5_QPC_STATE_RST        = 0x0,
1981         MLX5_QPC_STATE_INIT       = 0x1,
1982         MLX5_QPC_STATE_RTR        = 0x2,
1983         MLX5_QPC_STATE_RTS        = 0x3,
1984         MLX5_QPC_STATE_SQER       = 0x4,
1985         MLX5_QPC_STATE_ERR        = 0x6,
1986         MLX5_QPC_STATE_SQD        = 0x7,
1987         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1988 };
1989
1990 enum {
1991         MLX5_QPC_ST_RC            = 0x0,
1992         MLX5_QPC_ST_UC            = 0x1,
1993         MLX5_QPC_ST_UD            = 0x2,
1994         MLX5_QPC_ST_XRC           = 0x3,
1995         MLX5_QPC_ST_DCI           = 0x5,
1996         MLX5_QPC_ST_QP0           = 0x7,
1997         MLX5_QPC_ST_QP1           = 0x8,
1998         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1999         MLX5_QPC_ST_REG_UMR       = 0xc,
2000 };
2001
2002 enum {
2003         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2004         MLX5_QPC_PM_STATE_REARM     = 0x1,
2005         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2006         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2007 };
2008
2009 enum {
2010         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2011         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2012 };
2013
2014 enum {
2015         MLX5_QPC_MTU_256_BYTES        = 0x1,
2016         MLX5_QPC_MTU_512_BYTES        = 0x2,
2017         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2018         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2019         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2020         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2021 };
2022
2023 enum {
2024         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2025         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2026         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2027         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2028         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2029         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2030         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2031         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2032 };
2033
2034 enum {
2035         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2036         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2037         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2038 };
2039
2040 enum {
2041         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2042         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2043         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2044 };
2045
2046 struct mlx5_ifc_qpc_bits {
2047         u8         state[0x4];
2048         u8         lag_tx_port_affinity[0x4];
2049         u8         st[0x8];
2050         u8         reserved_at_10[0x3];
2051         u8         pm_state[0x2];
2052         u8         reserved_at_15[0x7];
2053         u8         end_padding_mode[0x2];
2054         u8         reserved_at_1e[0x2];
2055
2056         u8         wq_signature[0x1];
2057         u8         block_lb_mc[0x1];
2058         u8         atomic_like_write_en[0x1];
2059         u8         latency_sensitive[0x1];
2060         u8         reserved_at_24[0x1];
2061         u8         drain_sigerr[0x1];
2062         u8         reserved_at_26[0x2];
2063         u8         pd[0x18];
2064
2065         u8         mtu[0x3];
2066         u8         log_msg_max[0x5];
2067         u8         reserved_at_48[0x1];
2068         u8         log_rq_size[0x4];
2069         u8         log_rq_stride[0x3];
2070         u8         no_sq[0x1];
2071         u8         log_sq_size[0x4];
2072         u8         reserved_at_55[0x6];
2073         u8         rlky[0x1];
2074         u8         ulp_stateless_offload_mode[0x4];
2075
2076         u8         counter_set_id[0x8];
2077         u8         uar_page[0x18];
2078
2079         u8         reserved_at_80[0x8];
2080         u8         user_index[0x18];
2081
2082         u8         reserved_at_a0[0x3];
2083         u8         log_page_size[0x5];
2084         u8         remote_qpn[0x18];
2085
2086         struct mlx5_ifc_ads_bits primary_address_path;
2087
2088         struct mlx5_ifc_ads_bits secondary_address_path;
2089
2090         u8         log_ack_req_freq[0x4];
2091         u8         reserved_at_384[0x4];
2092         u8         log_sra_max[0x3];
2093         u8         reserved_at_38b[0x2];
2094         u8         retry_count[0x3];
2095         u8         rnr_retry[0x3];
2096         u8         reserved_at_393[0x1];
2097         u8         fre[0x1];
2098         u8         cur_rnr_retry[0x3];
2099         u8         cur_retry_count[0x3];
2100         u8         reserved_at_39b[0x5];
2101
2102         u8         reserved_at_3a0[0x20];
2103
2104         u8         reserved_at_3c0[0x8];
2105         u8         next_send_psn[0x18];
2106
2107         u8         reserved_at_3e0[0x8];
2108         u8         cqn_snd[0x18];
2109
2110         u8         reserved_at_400[0x8];
2111         u8         deth_sqpn[0x18];
2112
2113         u8         reserved_at_420[0x20];
2114
2115         u8         reserved_at_440[0x8];
2116         u8         last_acked_psn[0x18];
2117
2118         u8         reserved_at_460[0x8];
2119         u8         ssn[0x18];
2120
2121         u8         reserved_at_480[0x8];
2122         u8         log_rra_max[0x3];
2123         u8         reserved_at_48b[0x1];
2124         u8         atomic_mode[0x4];
2125         u8         rre[0x1];
2126         u8         rwe[0x1];
2127         u8         rae[0x1];
2128         u8         reserved_at_493[0x1];
2129         u8         page_offset[0x6];
2130         u8         reserved_at_49a[0x3];
2131         u8         cd_slave_receive[0x1];
2132         u8         cd_slave_send[0x1];
2133         u8         cd_master[0x1];
2134
2135         u8         reserved_at_4a0[0x3];
2136         u8         min_rnr_nak[0x5];
2137         u8         next_rcv_psn[0x18];
2138
2139         u8         reserved_at_4c0[0x8];
2140         u8         xrcd[0x18];
2141
2142         u8         reserved_at_4e0[0x8];
2143         u8         cqn_rcv[0x18];
2144
2145         u8         dbr_addr[0x40];
2146
2147         u8         q_key[0x20];
2148
2149         u8         reserved_at_560[0x5];
2150         u8         rq_type[0x3];
2151         u8         srqn_rmpn_xrqn[0x18];
2152
2153         u8         reserved_at_580[0x8];
2154         u8         rmsn[0x18];
2155
2156         u8         hw_sq_wqebb_counter[0x10];
2157         u8         sw_sq_wqebb_counter[0x10];
2158
2159         u8         hw_rq_counter[0x20];
2160
2161         u8         sw_rq_counter[0x20];
2162
2163         u8         reserved_at_600[0x20];
2164
2165         u8         reserved_at_620[0xf];
2166         u8         cgs[0x1];
2167         u8         cs_req[0x8];
2168         u8         cs_res[0x8];
2169
2170         u8         dc_access_key[0x40];
2171
2172         u8         reserved_at_680[0xc0];
2173 };
2174
2175 struct mlx5_ifc_roce_addr_layout_bits {
2176         u8         source_l3_address[16][0x8];
2177
2178         u8         reserved_at_80[0x3];
2179         u8         vlan_valid[0x1];
2180         u8         vlan_id[0xc];
2181         u8         source_mac_47_32[0x10];
2182
2183         u8         source_mac_31_0[0x20];
2184
2185         u8         reserved_at_c0[0x14];
2186         u8         roce_l3_type[0x4];
2187         u8         roce_version[0x8];
2188
2189         u8         reserved_at_e0[0x20];
2190 };
2191
2192 union mlx5_ifc_hca_cap_union_bits {
2193         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2194         struct mlx5_ifc_odp_cap_bits odp_cap;
2195         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2196         struct mlx5_ifc_roce_cap_bits roce_cap;
2197         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2198         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2199         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2200         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2201         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2202         struct mlx5_ifc_qos_cap_bits qos_cap;
2203         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2204         u8         reserved_at_0[0x8000];
2205 };
2206
2207 enum {
2208         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2209         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2210         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2211         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2212         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2213         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2214         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2215 };
2216
2217 struct mlx5_ifc_flow_context_bits {
2218         u8         reserved_at_0[0x20];
2219
2220         u8         group_id[0x20];
2221
2222         u8         reserved_at_40[0x8];
2223         u8         flow_tag[0x18];
2224
2225         u8         reserved_at_60[0x10];
2226         u8         action[0x10];
2227
2228         u8         reserved_at_80[0x8];
2229         u8         destination_list_size[0x18];
2230
2231         u8         reserved_at_a0[0x8];
2232         u8         flow_counter_list_size[0x18];
2233
2234         u8         encap_id[0x20];
2235
2236         u8         modify_header_id[0x20];
2237
2238         u8         reserved_at_100[0x100];
2239
2240         struct mlx5_ifc_fte_match_param_bits match_value;
2241
2242         u8         reserved_at_1200[0x600];
2243
2244         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2245 };
2246
2247 enum {
2248         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2249         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2250 };
2251
2252 struct mlx5_ifc_xrc_srqc_bits {
2253         u8         state[0x4];
2254         u8         log_xrc_srq_size[0x4];
2255         u8         reserved_at_8[0x18];
2256
2257         u8         wq_signature[0x1];
2258         u8         cont_srq[0x1];
2259         u8         reserved_at_22[0x1];
2260         u8         rlky[0x1];
2261         u8         basic_cyclic_rcv_wqe[0x1];
2262         u8         log_rq_stride[0x3];
2263         u8         xrcd[0x18];
2264
2265         u8         page_offset[0x6];
2266         u8         reserved_at_46[0x2];
2267         u8         cqn[0x18];
2268
2269         u8         reserved_at_60[0x20];
2270
2271         u8         user_index_equal_xrc_srqn[0x1];
2272         u8         reserved_at_81[0x1];
2273         u8         log_page_size[0x6];
2274         u8         user_index[0x18];
2275
2276         u8         reserved_at_a0[0x20];
2277
2278         u8         reserved_at_c0[0x8];
2279         u8         pd[0x18];
2280
2281         u8         lwm[0x10];
2282         u8         wqe_cnt[0x10];
2283
2284         u8         reserved_at_100[0x40];
2285
2286         u8         db_record_addr_h[0x20];
2287
2288         u8         db_record_addr_l[0x1e];
2289         u8         reserved_at_17e[0x2];
2290
2291         u8         reserved_at_180[0x80];
2292 };
2293
2294 struct mlx5_ifc_traffic_counter_bits {
2295         u8         packets[0x40];
2296
2297         u8         octets[0x40];
2298 };
2299
2300 struct mlx5_ifc_tisc_bits {
2301         u8         strict_lag_tx_port_affinity[0x1];
2302         u8         reserved_at_1[0x3];
2303         u8         lag_tx_port_affinity[0x04];
2304
2305         u8         reserved_at_8[0x4];
2306         u8         prio[0x4];
2307         u8         reserved_at_10[0x10];
2308
2309         u8         reserved_at_20[0x100];
2310
2311         u8         reserved_at_120[0x8];
2312         u8         transport_domain[0x18];
2313
2314         u8         reserved_at_140[0x8];
2315         u8         underlay_qpn[0x18];
2316         u8         reserved_at_160[0x3a0];
2317 };
2318
2319 enum {
2320         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2321         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2322 };
2323
2324 enum {
2325         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2326         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2327 };
2328
2329 enum {
2330         MLX5_RX_HASH_FN_NONE           = 0x0,
2331         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2332         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2333 };
2334
2335 enum {
2336         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2337         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2338 };
2339
2340 struct mlx5_ifc_tirc_bits {
2341         u8         reserved_at_0[0x20];
2342
2343         u8         disp_type[0x4];
2344         u8         reserved_at_24[0x1c];
2345
2346         u8         reserved_at_40[0x40];
2347
2348         u8         reserved_at_80[0x4];
2349         u8         lro_timeout_period_usecs[0x10];
2350         u8         lro_enable_mask[0x4];
2351         u8         lro_max_ip_payload_size[0x8];
2352
2353         u8         reserved_at_a0[0x40];
2354
2355         u8         reserved_at_e0[0x8];
2356         u8         inline_rqn[0x18];
2357
2358         u8         rx_hash_symmetric[0x1];
2359         u8         reserved_at_101[0x1];
2360         u8         tunneled_offload_en[0x1];
2361         u8         reserved_at_103[0x5];
2362         u8         indirect_table[0x18];
2363
2364         u8         rx_hash_fn[0x4];
2365         u8         reserved_at_124[0x2];
2366         u8         self_lb_block[0x2];
2367         u8         transport_domain[0x18];
2368
2369         u8         rx_hash_toeplitz_key[10][0x20];
2370
2371         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2372
2373         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2374
2375         u8         reserved_at_2c0[0x4c0];
2376 };
2377
2378 enum {
2379         MLX5_SRQC_STATE_GOOD   = 0x0,
2380         MLX5_SRQC_STATE_ERROR  = 0x1,
2381 };
2382
2383 struct mlx5_ifc_srqc_bits {
2384         u8         state[0x4];
2385         u8         log_srq_size[0x4];
2386         u8         reserved_at_8[0x18];
2387
2388         u8         wq_signature[0x1];
2389         u8         cont_srq[0x1];
2390         u8         reserved_at_22[0x1];
2391         u8         rlky[0x1];
2392         u8         reserved_at_24[0x1];
2393         u8         log_rq_stride[0x3];
2394         u8         xrcd[0x18];
2395
2396         u8         page_offset[0x6];
2397         u8         reserved_at_46[0x2];
2398         u8         cqn[0x18];
2399
2400         u8         reserved_at_60[0x20];
2401
2402         u8         reserved_at_80[0x2];
2403         u8         log_page_size[0x6];
2404         u8         reserved_at_88[0x18];
2405
2406         u8         reserved_at_a0[0x20];
2407
2408         u8         reserved_at_c0[0x8];
2409         u8         pd[0x18];
2410
2411         u8         lwm[0x10];
2412         u8         wqe_cnt[0x10];
2413
2414         u8         reserved_at_100[0x40];
2415
2416         u8         dbr_addr[0x40];
2417
2418         u8         reserved_at_180[0x80];
2419 };
2420
2421 enum {
2422         MLX5_SQC_STATE_RST  = 0x0,
2423         MLX5_SQC_STATE_RDY  = 0x1,
2424         MLX5_SQC_STATE_ERR  = 0x3,
2425 };
2426
2427 struct mlx5_ifc_sqc_bits {
2428         u8         rlky[0x1];
2429         u8         cd_master[0x1];
2430         u8         fre[0x1];
2431         u8         flush_in_error_en[0x1];
2432         u8         reserved_at_4[0x1];
2433         u8         min_wqe_inline_mode[0x3];
2434         u8         state[0x4];
2435         u8         reg_umr[0x1];
2436         u8         reserved_at_d[0x13];
2437
2438         u8         reserved_at_20[0x8];
2439         u8         user_index[0x18];
2440
2441         u8         reserved_at_40[0x8];
2442         u8         cqn[0x18];
2443
2444         u8         reserved_at_60[0x90];
2445
2446         u8         packet_pacing_rate_limit_index[0x10];
2447         u8         tis_lst_sz[0x10];
2448         u8         reserved_at_110[0x10];
2449
2450         u8         reserved_at_120[0x40];
2451
2452         u8         reserved_at_160[0x8];
2453         u8         tis_num_0[0x18];
2454
2455         struct mlx5_ifc_wq_bits wq;
2456 };
2457
2458 enum {
2459         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2460         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2461         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2462         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2463 };
2464
2465 struct mlx5_ifc_scheduling_context_bits {
2466         u8         element_type[0x8];
2467         u8         reserved_at_8[0x18];
2468
2469         u8         element_attributes[0x20];
2470
2471         u8         parent_element_id[0x20];
2472
2473         u8         reserved_at_60[0x40];
2474
2475         u8         bw_share[0x20];
2476
2477         u8         max_average_bw[0x20];
2478
2479         u8         reserved_at_e0[0x120];
2480 };
2481
2482 struct mlx5_ifc_rqtc_bits {
2483         u8         reserved_at_0[0xa0];
2484
2485         u8         reserved_at_a0[0x10];
2486         u8         rqt_max_size[0x10];
2487
2488         u8         reserved_at_c0[0x10];
2489         u8         rqt_actual_size[0x10];
2490
2491         u8         reserved_at_e0[0x6a0];
2492
2493         struct mlx5_ifc_rq_num_bits rq_num[0];
2494 };
2495
2496 enum {
2497         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2498         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2499 };
2500
2501 enum {
2502         MLX5_RQC_STATE_RST  = 0x0,
2503         MLX5_RQC_STATE_RDY  = 0x1,
2504         MLX5_RQC_STATE_ERR  = 0x3,
2505 };
2506
2507 struct mlx5_ifc_rqc_bits {
2508         u8         rlky[0x1];
2509         u8         reserved_at_1[0x1];
2510         u8         scatter_fcs[0x1];
2511         u8         vsd[0x1];
2512         u8         mem_rq_type[0x4];
2513         u8         state[0x4];
2514         u8         reserved_at_c[0x1];
2515         u8         flush_in_error_en[0x1];
2516         u8         reserved_at_e[0x12];
2517
2518         u8         reserved_at_20[0x8];
2519         u8         user_index[0x18];
2520
2521         u8         reserved_at_40[0x8];
2522         u8         cqn[0x18];
2523
2524         u8         counter_set_id[0x8];
2525         u8         reserved_at_68[0x18];
2526
2527         u8         reserved_at_80[0x8];
2528         u8         rmpn[0x18];
2529
2530         u8         reserved_at_a0[0xe0];
2531
2532         struct mlx5_ifc_wq_bits wq;
2533 };
2534
2535 enum {
2536         MLX5_RMPC_STATE_RDY  = 0x1,
2537         MLX5_RMPC_STATE_ERR  = 0x3,
2538 };
2539
2540 struct mlx5_ifc_rmpc_bits {
2541         u8         reserved_at_0[0x8];
2542         u8         state[0x4];
2543         u8         reserved_at_c[0x14];
2544
2545         u8         basic_cyclic_rcv_wqe[0x1];
2546         u8         reserved_at_21[0x1f];
2547
2548         u8         reserved_at_40[0x140];
2549
2550         struct mlx5_ifc_wq_bits wq;
2551 };
2552
2553 struct mlx5_ifc_nic_vport_context_bits {
2554         u8         reserved_at_0[0x5];
2555         u8         min_wqe_inline_mode[0x3];
2556         u8         reserved_at_8[0x17];
2557         u8         roce_en[0x1];
2558
2559         u8         arm_change_event[0x1];
2560         u8         reserved_at_21[0x1a];
2561         u8         event_on_mtu[0x1];
2562         u8         event_on_promisc_change[0x1];
2563         u8         event_on_vlan_change[0x1];
2564         u8         event_on_mc_address_change[0x1];
2565         u8         event_on_uc_address_change[0x1];
2566
2567         u8         reserved_at_40[0xf0];
2568
2569         u8         mtu[0x10];
2570
2571         u8         system_image_guid[0x40];
2572         u8         port_guid[0x40];
2573         u8         node_guid[0x40];
2574
2575         u8         reserved_at_200[0x140];
2576         u8         qkey_violation_counter[0x10];
2577         u8         reserved_at_350[0x430];
2578
2579         u8         promisc_uc[0x1];
2580         u8         promisc_mc[0x1];
2581         u8         promisc_all[0x1];
2582         u8         reserved_at_783[0x2];
2583         u8         allowed_list_type[0x3];
2584         u8         reserved_at_788[0xc];
2585         u8         allowed_list_size[0xc];
2586
2587         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2588
2589         u8         reserved_at_7e0[0x20];
2590
2591         u8         current_uc_mac_address[0][0x40];
2592 };
2593
2594 enum {
2595         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2596         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2597         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2598         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2599 };
2600
2601 struct mlx5_ifc_mkc_bits {
2602         u8         reserved_at_0[0x1];
2603         u8         free[0x1];
2604         u8         reserved_at_2[0xd];
2605         u8         small_fence_on_rdma_read_response[0x1];
2606         u8         umr_en[0x1];
2607         u8         a[0x1];
2608         u8         rw[0x1];
2609         u8         rr[0x1];
2610         u8         lw[0x1];
2611         u8         lr[0x1];
2612         u8         access_mode[0x2];
2613         u8         reserved_at_18[0x8];
2614
2615         u8         qpn[0x18];
2616         u8         mkey_7_0[0x8];
2617
2618         u8         reserved_at_40[0x20];
2619
2620         u8         length64[0x1];
2621         u8         bsf_en[0x1];
2622         u8         sync_umr[0x1];
2623         u8         reserved_at_63[0x2];
2624         u8         expected_sigerr_count[0x1];
2625         u8         reserved_at_66[0x1];
2626         u8         en_rinval[0x1];
2627         u8         pd[0x18];
2628
2629         u8         start_addr[0x40];
2630
2631         u8         len[0x40];
2632
2633         u8         bsf_octword_size[0x20];
2634
2635         u8         reserved_at_120[0x80];
2636
2637         u8         translations_octword_size[0x20];
2638
2639         u8         reserved_at_1c0[0x1b];
2640         u8         log_page_size[0x5];
2641
2642         u8         reserved_at_1e0[0x20];
2643 };
2644
2645 struct mlx5_ifc_pkey_bits {
2646         u8         reserved_at_0[0x10];
2647         u8         pkey[0x10];
2648 };
2649
2650 struct mlx5_ifc_array128_auto_bits {
2651         u8         array128_auto[16][0x8];
2652 };
2653
2654 struct mlx5_ifc_hca_vport_context_bits {
2655         u8         field_select[0x20];
2656
2657         u8         reserved_at_20[0xe0];
2658
2659         u8         sm_virt_aware[0x1];
2660         u8         has_smi[0x1];
2661         u8         has_raw[0x1];
2662         u8         grh_required[0x1];
2663         u8         reserved_at_104[0xc];
2664         u8         port_physical_state[0x4];
2665         u8         vport_state_policy[0x4];
2666         u8         port_state[0x4];
2667         u8         vport_state[0x4];
2668
2669         u8         reserved_at_120[0x20];
2670
2671         u8         system_image_guid[0x40];
2672
2673         u8         port_guid[0x40];
2674
2675         u8         node_guid[0x40];
2676
2677         u8         cap_mask1[0x20];
2678
2679         u8         cap_mask1_field_select[0x20];
2680
2681         u8         cap_mask2[0x20];
2682
2683         u8         cap_mask2_field_select[0x20];
2684
2685         u8         reserved_at_280[0x80];
2686
2687         u8         lid[0x10];
2688         u8         reserved_at_310[0x4];
2689         u8         init_type_reply[0x4];
2690         u8         lmc[0x3];
2691         u8         subnet_timeout[0x5];
2692
2693         u8         sm_lid[0x10];
2694         u8         sm_sl[0x4];
2695         u8         reserved_at_334[0xc];
2696
2697         u8         qkey_violation_counter[0x10];
2698         u8         pkey_violation_counter[0x10];
2699
2700         u8         reserved_at_360[0xca0];
2701 };
2702
2703 struct mlx5_ifc_esw_vport_context_bits {
2704         u8         reserved_at_0[0x3];
2705         u8         vport_svlan_strip[0x1];
2706         u8         vport_cvlan_strip[0x1];
2707         u8         vport_svlan_insert[0x1];
2708         u8         vport_cvlan_insert[0x2];
2709         u8         reserved_at_8[0x18];
2710
2711         u8         reserved_at_20[0x20];
2712
2713         u8         svlan_cfi[0x1];
2714         u8         svlan_pcp[0x3];
2715         u8         svlan_id[0xc];
2716         u8         cvlan_cfi[0x1];
2717         u8         cvlan_pcp[0x3];
2718         u8         cvlan_id[0xc];
2719
2720         u8         reserved_at_60[0x7a0];
2721 };
2722
2723 enum {
2724         MLX5_EQC_STATUS_OK                = 0x0,
2725         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2726 };
2727
2728 enum {
2729         MLX5_EQC_ST_ARMED  = 0x9,
2730         MLX5_EQC_ST_FIRED  = 0xa,
2731 };
2732
2733 struct mlx5_ifc_eqc_bits {
2734         u8         status[0x4];
2735         u8         reserved_at_4[0x9];
2736         u8         ec[0x1];
2737         u8         oi[0x1];
2738         u8         reserved_at_f[0x5];
2739         u8         st[0x4];
2740         u8         reserved_at_18[0x8];
2741
2742         u8         reserved_at_20[0x20];
2743
2744         u8         reserved_at_40[0x14];
2745         u8         page_offset[0x6];
2746         u8         reserved_at_5a[0x6];
2747
2748         u8         reserved_at_60[0x3];
2749         u8         log_eq_size[0x5];
2750         u8         uar_page[0x18];
2751
2752         u8         reserved_at_80[0x20];
2753
2754         u8         reserved_at_a0[0x18];
2755         u8         intr[0x8];
2756
2757         u8         reserved_at_c0[0x3];
2758         u8         log_page_size[0x5];
2759         u8         reserved_at_c8[0x18];
2760
2761         u8         reserved_at_e0[0x60];
2762
2763         u8         reserved_at_140[0x8];
2764         u8         consumer_counter[0x18];
2765
2766         u8         reserved_at_160[0x8];
2767         u8         producer_counter[0x18];
2768
2769         u8         reserved_at_180[0x80];
2770 };
2771
2772 enum {
2773         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2774         MLX5_DCTC_STATE_DRAINING  = 0x1,
2775         MLX5_DCTC_STATE_DRAINED   = 0x2,
2776 };
2777
2778 enum {
2779         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2780         MLX5_DCTC_CS_RES_NA         = 0x1,
2781         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2782 };
2783
2784 enum {
2785         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2786         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2787         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2788         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2789         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2790 };
2791
2792 struct mlx5_ifc_dctc_bits {
2793         u8         reserved_at_0[0x4];
2794         u8         state[0x4];
2795         u8         reserved_at_8[0x18];
2796
2797         u8         reserved_at_20[0x8];
2798         u8         user_index[0x18];
2799
2800         u8         reserved_at_40[0x8];
2801         u8         cqn[0x18];
2802
2803         u8         counter_set_id[0x8];
2804         u8         atomic_mode[0x4];
2805         u8         rre[0x1];
2806         u8         rwe[0x1];
2807         u8         rae[0x1];
2808         u8         atomic_like_write_en[0x1];
2809         u8         latency_sensitive[0x1];
2810         u8         rlky[0x1];
2811         u8         free_ar[0x1];
2812         u8         reserved_at_73[0xd];
2813
2814         u8         reserved_at_80[0x8];
2815         u8         cs_res[0x8];
2816         u8         reserved_at_90[0x3];
2817         u8         min_rnr_nak[0x5];
2818         u8         reserved_at_98[0x8];
2819
2820         u8         reserved_at_a0[0x8];
2821         u8         srqn_xrqn[0x18];
2822
2823         u8         reserved_at_c0[0x8];
2824         u8         pd[0x18];
2825
2826         u8         tclass[0x8];
2827         u8         reserved_at_e8[0x4];
2828         u8         flow_label[0x14];
2829
2830         u8         dc_access_key[0x40];
2831
2832         u8         reserved_at_140[0x5];
2833         u8         mtu[0x3];
2834         u8         port[0x8];
2835         u8         pkey_index[0x10];
2836
2837         u8         reserved_at_160[0x8];
2838         u8         my_addr_index[0x8];
2839         u8         reserved_at_170[0x8];
2840         u8         hop_limit[0x8];
2841
2842         u8         dc_access_key_violation_count[0x20];
2843
2844         u8         reserved_at_1a0[0x14];
2845         u8         dei_cfi[0x1];
2846         u8         eth_prio[0x3];
2847         u8         ecn[0x2];
2848         u8         dscp[0x6];
2849
2850         u8         reserved_at_1c0[0x40];
2851 };
2852
2853 enum {
2854         MLX5_CQC_STATUS_OK             = 0x0,
2855         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2856         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2857 };
2858
2859 enum {
2860         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2861         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2862 };
2863
2864 enum {
2865         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2866         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2867         MLX5_CQC_ST_FIRED                                 = 0xa,
2868 };
2869
2870 enum {
2871         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2872         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2873         MLX5_CQ_PERIOD_NUM_MODES
2874 };
2875
2876 struct mlx5_ifc_cqc_bits {
2877         u8         status[0x4];
2878         u8         reserved_at_4[0x4];
2879         u8         cqe_sz[0x3];
2880         u8         cc[0x1];
2881         u8         reserved_at_c[0x1];
2882         u8         scqe_break_moderation_en[0x1];
2883         u8         oi[0x1];
2884         u8         cq_period_mode[0x2];
2885         u8         cqe_comp_en[0x1];
2886         u8         mini_cqe_res_format[0x2];
2887         u8         st[0x4];
2888         u8         reserved_at_18[0x8];
2889
2890         u8         reserved_at_20[0x20];
2891
2892         u8         reserved_at_40[0x14];
2893         u8         page_offset[0x6];
2894         u8         reserved_at_5a[0x6];
2895
2896         u8         reserved_at_60[0x3];
2897         u8         log_cq_size[0x5];
2898         u8         uar_page[0x18];
2899
2900         u8         reserved_at_80[0x4];
2901         u8         cq_period[0xc];
2902         u8         cq_max_count[0x10];
2903
2904         u8         reserved_at_a0[0x18];
2905         u8         c_eqn[0x8];
2906
2907         u8         reserved_at_c0[0x3];
2908         u8         log_page_size[0x5];
2909         u8         reserved_at_c8[0x18];
2910
2911         u8         reserved_at_e0[0x20];
2912
2913         u8         reserved_at_100[0x8];
2914         u8         last_notified_index[0x18];
2915
2916         u8         reserved_at_120[0x8];
2917         u8         last_solicit_index[0x18];
2918
2919         u8         reserved_at_140[0x8];
2920         u8         consumer_counter[0x18];
2921
2922         u8         reserved_at_160[0x8];
2923         u8         producer_counter[0x18];
2924
2925         u8         reserved_at_180[0x40];
2926
2927         u8         dbr_addr[0x40];
2928 };
2929
2930 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2931         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2932         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2933         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2934         u8         reserved_at_0[0x800];
2935 };
2936
2937 struct mlx5_ifc_query_adapter_param_block_bits {
2938         u8         reserved_at_0[0xc0];
2939
2940         u8         reserved_at_c0[0x8];
2941         u8         ieee_vendor_id[0x18];
2942
2943         u8         reserved_at_e0[0x10];
2944         u8         vsd_vendor_id[0x10];
2945
2946         u8         vsd[208][0x8];
2947
2948         u8         vsd_contd_psid[16][0x8];
2949 };
2950
2951 enum {
2952         MLX5_XRQC_STATE_GOOD   = 0x0,
2953         MLX5_XRQC_STATE_ERROR  = 0x1,
2954 };
2955
2956 enum {
2957         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2958         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2959 };
2960
2961 enum {
2962         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2963 };
2964
2965 struct mlx5_ifc_tag_matching_topology_context_bits {
2966         u8         log_matching_list_sz[0x4];
2967         u8         reserved_at_4[0xc];
2968         u8         append_next_index[0x10];
2969
2970         u8         sw_phase_cnt[0x10];
2971         u8         hw_phase_cnt[0x10];
2972
2973         u8         reserved_at_40[0x40];
2974 };
2975
2976 struct mlx5_ifc_xrqc_bits {
2977         u8         state[0x4];
2978         u8         rlkey[0x1];
2979         u8         reserved_at_5[0xf];
2980         u8         topology[0x4];
2981         u8         reserved_at_18[0x4];
2982         u8         offload[0x4];
2983
2984         u8         reserved_at_20[0x8];
2985         u8         user_index[0x18];
2986
2987         u8         reserved_at_40[0x8];
2988         u8         cqn[0x18];
2989
2990         u8         reserved_at_60[0xa0];
2991
2992         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2993
2994         u8         reserved_at_180[0x880];
2995
2996         struct mlx5_ifc_wq_bits wq;
2997 };
2998
2999 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3000         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3001         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3002         u8         reserved_at_0[0x20];
3003 };
3004
3005 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3006         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3007         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3008         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3009         u8         reserved_at_0[0x20];
3010 };
3011
3012 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3013         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3014         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3015         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3016         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3017         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3018         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3019         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3020         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3021         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3022         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3023         u8         reserved_at_0[0x7c0];
3024 };
3025
3026 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3027         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3028         u8         reserved_at_0[0x7c0];
3029 };
3030
3031 union mlx5_ifc_event_auto_bits {
3032         struct mlx5_ifc_comp_event_bits comp_event;
3033         struct mlx5_ifc_dct_events_bits dct_events;
3034         struct mlx5_ifc_qp_events_bits qp_events;
3035         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3036         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3037         struct mlx5_ifc_cq_error_bits cq_error;
3038         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3039         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3040         struct mlx5_ifc_gpio_event_bits gpio_event;
3041         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3042         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3043         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3044         u8         reserved_at_0[0xe0];
3045 };
3046
3047 struct mlx5_ifc_health_buffer_bits {
3048         u8         reserved_at_0[0x100];
3049
3050         u8         assert_existptr[0x20];
3051
3052         u8         assert_callra[0x20];
3053
3054         u8         reserved_at_140[0x40];
3055
3056         u8         fw_version[0x20];
3057
3058         u8         hw_id[0x20];
3059
3060         u8         reserved_at_1c0[0x20];
3061
3062         u8         irisc_index[0x8];
3063         u8         synd[0x8];
3064         u8         ext_synd[0x10];
3065 };
3066
3067 struct mlx5_ifc_register_loopback_control_bits {
3068         u8         no_lb[0x1];
3069         u8         reserved_at_1[0x7];
3070         u8         port[0x8];
3071         u8         reserved_at_10[0x10];
3072
3073         u8         reserved_at_20[0x60];
3074 };
3075
3076 struct mlx5_ifc_vport_tc_element_bits {
3077         u8         traffic_class[0x4];
3078         u8         reserved_at_4[0xc];
3079         u8         vport_number[0x10];
3080 };
3081
3082 struct mlx5_ifc_vport_element_bits {
3083         u8         reserved_at_0[0x10];
3084         u8         vport_number[0x10];
3085 };
3086
3087 enum {
3088         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3089         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3090         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3091 };
3092
3093 struct mlx5_ifc_tsar_element_bits {
3094         u8         reserved_at_0[0x8];
3095         u8         tsar_type[0x8];
3096         u8         reserved_at_10[0x10];
3097 };
3098
3099 enum {
3100         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3101         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3102 };
3103
3104 struct mlx5_ifc_teardown_hca_out_bits {
3105         u8         status[0x8];
3106         u8         reserved_at_8[0x18];
3107
3108         u8         syndrome[0x20];
3109
3110         u8         reserved_at_40[0x3f];
3111
3112         u8         force_state[0x1];
3113 };
3114
3115 enum {
3116         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3117         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3118 };
3119
3120 struct mlx5_ifc_teardown_hca_in_bits {
3121         u8         opcode[0x10];
3122         u8         reserved_at_10[0x10];
3123
3124         u8         reserved_at_20[0x10];
3125         u8         op_mod[0x10];
3126
3127         u8         reserved_at_40[0x10];
3128         u8         profile[0x10];
3129
3130         u8         reserved_at_60[0x20];
3131 };
3132
3133 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3134         u8         status[0x8];
3135         u8         reserved_at_8[0x18];
3136
3137         u8         syndrome[0x20];
3138
3139         u8         reserved_at_40[0x40];
3140 };
3141
3142 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3143         u8         opcode[0x10];
3144         u8         reserved_at_10[0x10];
3145
3146         u8         reserved_at_20[0x10];
3147         u8         op_mod[0x10];
3148
3149         u8         reserved_at_40[0x8];
3150         u8         qpn[0x18];
3151
3152         u8         reserved_at_60[0x20];
3153
3154         u8         opt_param_mask[0x20];
3155
3156         u8         reserved_at_a0[0x20];
3157
3158         struct mlx5_ifc_qpc_bits qpc;
3159
3160         u8         reserved_at_800[0x80];
3161 };
3162
3163 struct mlx5_ifc_sqd2rts_qp_out_bits {
3164         u8         status[0x8];
3165         u8         reserved_at_8[0x18];
3166
3167         u8         syndrome[0x20];
3168
3169         u8         reserved_at_40[0x40];
3170 };
3171
3172 struct mlx5_ifc_sqd2rts_qp_in_bits {
3173         u8         opcode[0x10];
3174         u8         reserved_at_10[0x10];
3175
3176         u8         reserved_at_20[0x10];
3177         u8         op_mod[0x10];
3178
3179         u8         reserved_at_40[0x8];
3180         u8         qpn[0x18];
3181
3182         u8         reserved_at_60[0x20];
3183
3184         u8         opt_param_mask[0x20];
3185
3186         u8         reserved_at_a0[0x20];
3187
3188         struct mlx5_ifc_qpc_bits qpc;
3189
3190         u8         reserved_at_800[0x80];
3191 };
3192
3193 struct mlx5_ifc_set_roce_address_out_bits {
3194         u8         status[0x8];
3195         u8         reserved_at_8[0x18];
3196
3197         u8         syndrome[0x20];
3198
3199         u8         reserved_at_40[0x40];
3200 };
3201
3202 struct mlx5_ifc_set_roce_address_in_bits {
3203         u8         opcode[0x10];
3204         u8         reserved_at_10[0x10];
3205
3206         u8         reserved_at_20[0x10];
3207         u8         op_mod[0x10];
3208
3209         u8         roce_address_index[0x10];
3210         u8         reserved_at_50[0x10];
3211
3212         u8         reserved_at_60[0x20];
3213
3214         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3215 };
3216
3217 struct mlx5_ifc_set_mad_demux_out_bits {
3218         u8         status[0x8];
3219         u8         reserved_at_8[0x18];
3220
3221         u8         syndrome[0x20];
3222
3223         u8         reserved_at_40[0x40];
3224 };
3225
3226 enum {
3227         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3228         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3229 };
3230
3231 struct mlx5_ifc_set_mad_demux_in_bits {
3232         u8         opcode[0x10];
3233         u8         reserved_at_10[0x10];
3234
3235         u8         reserved_at_20[0x10];
3236         u8         op_mod[0x10];
3237
3238         u8         reserved_at_40[0x20];
3239
3240         u8         reserved_at_60[0x6];
3241         u8         demux_mode[0x2];
3242         u8         reserved_at_68[0x18];
3243 };
3244
3245 struct mlx5_ifc_set_l2_table_entry_out_bits {
3246         u8         status[0x8];
3247         u8         reserved_at_8[0x18];
3248
3249         u8         syndrome[0x20];
3250
3251         u8         reserved_at_40[0x40];
3252 };
3253
3254 struct mlx5_ifc_set_l2_table_entry_in_bits {
3255         u8         opcode[0x10];
3256         u8         reserved_at_10[0x10];
3257
3258         u8         reserved_at_20[0x10];
3259         u8         op_mod[0x10];
3260
3261         u8         reserved_at_40[0x60];
3262
3263         u8         reserved_at_a0[0x8];
3264         u8         table_index[0x18];
3265
3266         u8         reserved_at_c0[0x20];
3267
3268         u8         reserved_at_e0[0x13];
3269         u8         vlan_valid[0x1];
3270         u8         vlan[0xc];
3271
3272         struct mlx5_ifc_mac_address_layout_bits mac_address;
3273