27134c4fcb76eb5140ff4828066e73e11d671cd9
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65
66 enum {
67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72
73 enum {
74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
76 };
77
78 enum {
79         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
80         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
81         MLX5_CMD_OP_INIT_HCA                      = 0x102,
82         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
83         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
84         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
85         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
86         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
87         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
88         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
89         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
90         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
91         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
92         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
93         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
94         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
95         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
96         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
97         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
98         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
99         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
100         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
101         MLX5_CMD_OP_GEN_EQE                       = 0x304,
102         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
103         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
104         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
105         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
106         MLX5_CMD_OP_CREATE_QP                     = 0x500,
107         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
108         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
109         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
110         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
111         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
112         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
113         MLX5_CMD_OP_2ERR_QP                       = 0x507,
114         MLX5_CMD_OP_2RST_QP                       = 0x50a,
115         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
116         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
117         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
118         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
119         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
120         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
121         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
122         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
123         MLX5_CMD_OP_ARM_RQ                        = 0x703,
124         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
125         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
126         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
127         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
128         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
129         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
130         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
131         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
132         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
133         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
134         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
135         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
136         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
137         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
138         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
139         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
140         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
141         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
142         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
143         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
144         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
145         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
146         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
147         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
148         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
149         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
150         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
151         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
152         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
153         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
154         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
155         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
156         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
157         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
158         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
159         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
160         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
161         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
162         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
163         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
164         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
165         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
166         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
167         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
168         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
169         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
170         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
171         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
172         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
173         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
174         MLX5_CMD_OP_NOP                           = 0x80d,
175         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
176         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
177         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
178         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
179         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
180         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
181         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
182         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
183         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
184         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
185         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
186         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
187         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
188         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
189         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
190         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
191         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
192         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
193         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
194         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
195         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
196         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
197         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
198         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
199         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
200         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
201         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
202         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
203         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
204         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
205         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
206         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
207         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
208         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
209         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
210         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
211         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
212         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
213         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
214         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
215         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
216         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
217         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
218         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
219         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
220         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
221         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
222         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
223         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
224         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
225         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
226         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
227         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
228         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
229         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
230         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
231         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
232         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
233         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
234         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
235         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
236         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
237         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
238         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
239         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
240         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
241         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
242         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
243         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
244         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
245         MLX5_CMD_OP_MAX
246 };
247
248 struct mlx5_ifc_flow_table_fields_supported_bits {
249         u8         outer_dmac[0x1];
250         u8         outer_smac[0x1];
251         u8         outer_ether_type[0x1];
252         u8         outer_ip_version[0x1];
253         u8         outer_first_prio[0x1];
254         u8         outer_first_cfi[0x1];
255         u8         outer_first_vid[0x1];
256         u8         outer_ipv4_ttl[0x1];
257         u8         outer_second_prio[0x1];
258         u8         outer_second_cfi[0x1];
259         u8         outer_second_vid[0x1];
260         u8         reserved_at_b[0x1];
261         u8         outer_sip[0x1];
262         u8         outer_dip[0x1];
263         u8         outer_frag[0x1];
264         u8         outer_ip_protocol[0x1];
265         u8         outer_ip_ecn[0x1];
266         u8         outer_ip_dscp[0x1];
267         u8         outer_udp_sport[0x1];
268         u8         outer_udp_dport[0x1];
269         u8         outer_tcp_sport[0x1];
270         u8         outer_tcp_dport[0x1];
271         u8         outer_tcp_flags[0x1];
272         u8         outer_gre_protocol[0x1];
273         u8         outer_gre_key[0x1];
274         u8         outer_vxlan_vni[0x1];
275         u8         reserved_at_1a[0x5];
276         u8         source_eswitch_port[0x1];
277
278         u8         inner_dmac[0x1];
279         u8         inner_smac[0x1];
280         u8         inner_ether_type[0x1];
281         u8         inner_ip_version[0x1];
282         u8         inner_first_prio[0x1];
283         u8         inner_first_cfi[0x1];
284         u8         inner_first_vid[0x1];
285         u8         reserved_at_27[0x1];
286         u8         inner_second_prio[0x1];
287         u8         inner_second_cfi[0x1];
288         u8         inner_second_vid[0x1];
289         u8         reserved_at_2b[0x1];
290         u8         inner_sip[0x1];
291         u8         inner_dip[0x1];
292         u8         inner_frag[0x1];
293         u8         inner_ip_protocol[0x1];
294         u8         inner_ip_ecn[0x1];
295         u8         inner_ip_dscp[0x1];
296         u8         inner_udp_sport[0x1];
297         u8         inner_udp_dport[0x1];
298         u8         inner_tcp_sport[0x1];
299         u8         inner_tcp_dport[0x1];
300         u8         inner_tcp_flags[0x1];
301         u8         reserved_at_37[0x9];
302
303         u8         reserved_at_40[0x5];
304         u8         outer_first_mpls_over_udp[0x4];
305         u8         outer_first_mpls_over_gre[0x4];
306         u8         inner_first_mpls[0x4];
307         u8         outer_first_mpls[0x4];
308         u8         reserved_at_55[0x2];
309         u8         outer_esp_spi[0x1];
310         u8         reserved_at_58[0x2];
311         u8         bth_dst_qp[0x1];
312
313         u8         reserved_at_5b[0x25];
314 };
315
316 struct mlx5_ifc_flow_table_prop_layout_bits {
317         u8         ft_support[0x1];
318         u8         reserved_at_1[0x1];
319         u8         flow_counter[0x1];
320         u8         flow_modify_en[0x1];
321         u8         modify_root[0x1];
322         u8         identified_miss_table_mode[0x1];
323         u8         flow_table_modify[0x1];
324         u8         encap[0x1];
325         u8         decap[0x1];
326         u8         reserved_at_9[0x1];
327         u8         pop_vlan[0x1];
328         u8         push_vlan[0x1];
329         u8         reserved_at_c[0x14];
330
331         u8         reserved_at_20[0x2];
332         u8         log_max_ft_size[0x6];
333         u8         log_max_modify_header_context[0x8];
334         u8         max_modify_header_actions[0x8];
335         u8         max_ft_level[0x8];
336
337         u8         reserved_at_40[0x20];
338
339         u8         reserved_at_60[0x18];
340         u8         log_max_ft_num[0x8];
341
342         u8         reserved_at_80[0x18];
343         u8         log_max_destination[0x8];
344
345         u8         log_max_flow_counter[0x8];
346         u8         reserved_at_a8[0x10];
347         u8         log_max_flow[0x8];
348
349         u8         reserved_at_c0[0x40];
350
351         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
352
353         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
354 };
355
356 struct mlx5_ifc_odp_per_transport_service_cap_bits {
357         u8         send[0x1];
358         u8         receive[0x1];
359         u8         write[0x1];
360         u8         read[0x1];
361         u8         atomic[0x1];
362         u8         srq_receive[0x1];
363         u8         reserved_at_6[0x1a];
364 };
365
366 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
367         u8         smac_47_16[0x20];
368
369         u8         smac_15_0[0x10];
370         u8         ethertype[0x10];
371
372         u8         dmac_47_16[0x20];
373
374         u8         dmac_15_0[0x10];
375         u8         first_prio[0x3];
376         u8         first_cfi[0x1];
377         u8         first_vid[0xc];
378
379         u8         ip_protocol[0x8];
380         u8         ip_dscp[0x6];
381         u8         ip_ecn[0x2];
382         u8         cvlan_tag[0x1];
383         u8         svlan_tag[0x1];
384         u8         frag[0x1];
385         u8         ip_version[0x4];
386         u8         tcp_flags[0x9];
387
388         u8         tcp_sport[0x10];
389         u8         tcp_dport[0x10];
390
391         u8         reserved_at_c0[0x18];
392         u8         ttl_hoplimit[0x8];
393
394         u8         udp_sport[0x10];
395         u8         udp_dport[0x10];
396
397         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
398
399         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
400 };
401
402 struct mlx5_ifc_fte_match_set_misc_bits {
403         u8         reserved_at_0[0x8];
404         u8         source_sqn[0x18];
405
406         u8         source_eswitch_owner_vhca_id[0x10];
407         u8         source_port[0x10];
408
409         u8         outer_second_prio[0x3];
410         u8         outer_second_cfi[0x1];
411         u8         outer_second_vid[0xc];
412         u8         inner_second_prio[0x3];
413         u8         inner_second_cfi[0x1];
414         u8         inner_second_vid[0xc];
415
416         u8         outer_second_cvlan_tag[0x1];
417         u8         inner_second_cvlan_tag[0x1];
418         u8         outer_second_svlan_tag[0x1];
419         u8         inner_second_svlan_tag[0x1];
420         u8         reserved_at_64[0xc];
421         u8         gre_protocol[0x10];
422
423         u8         gre_key_h[0x18];
424         u8         gre_key_l[0x8];
425
426         u8         vxlan_vni[0x18];
427         u8         reserved_at_b8[0x8];
428
429         u8         reserved_at_c0[0x20];
430
431         u8         reserved_at_e0[0xc];
432         u8         outer_ipv6_flow_label[0x14];
433
434         u8         reserved_at_100[0xc];
435         u8         inner_ipv6_flow_label[0x14];
436
437         u8         reserved_at_120[0x28];
438         u8         bth_dst_qp[0x18];
439         u8         reserved_at_160[0x20];
440         u8         outer_esp_spi[0x20];
441         u8         reserved_at_1a0[0x60];
442 };
443
444 struct mlx5_ifc_fte_match_mpls_bits {
445         u8         mpls_label[0x14];
446         u8         mpls_exp[0x3];
447         u8         mpls_s_bos[0x1];
448         u8         mpls_ttl[0x8];
449 };
450
451 struct mlx5_ifc_fte_match_set_misc2_bits {
452         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
453
454         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
455
456         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
457
458         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
459
460         u8         reserved_at_80[0x100];
461
462         u8         metadata_reg_a[0x20];
463
464         u8         reserved_at_1a0[0x60];
465 };
466
467 struct mlx5_ifc_cmd_pas_bits {
468         u8         pa_h[0x20];
469
470         u8         pa_l[0x14];
471         u8         reserved_at_34[0xc];
472 };
473
474 struct mlx5_ifc_uint64_bits {
475         u8         hi[0x20];
476
477         u8         lo[0x20];
478 };
479
480 enum {
481         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
482         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
483         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
484         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
485         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
486         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
487         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
488         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
489         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
490         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
491 };
492
493 struct mlx5_ifc_ads_bits {
494         u8         fl[0x1];
495         u8         free_ar[0x1];
496         u8         reserved_at_2[0xe];
497         u8         pkey_index[0x10];
498
499         u8         reserved_at_20[0x8];
500         u8         grh[0x1];
501         u8         mlid[0x7];
502         u8         rlid[0x10];
503
504         u8         ack_timeout[0x5];
505         u8         reserved_at_45[0x3];
506         u8         src_addr_index[0x8];
507         u8         reserved_at_50[0x4];
508         u8         stat_rate[0x4];
509         u8         hop_limit[0x8];
510
511         u8         reserved_at_60[0x4];
512         u8         tclass[0x8];
513         u8         flow_label[0x14];
514
515         u8         rgid_rip[16][0x8];
516
517         u8         reserved_at_100[0x4];
518         u8         f_dscp[0x1];
519         u8         f_ecn[0x1];
520         u8         reserved_at_106[0x1];
521         u8         f_eth_prio[0x1];
522         u8         ecn[0x2];
523         u8         dscp[0x6];
524         u8         udp_sport[0x10];
525
526         u8         dei_cfi[0x1];
527         u8         eth_prio[0x3];
528         u8         sl[0x4];
529         u8         vhca_port_num[0x8];
530         u8         rmac_47_32[0x10];
531
532         u8         rmac_31_0[0x20];
533 };
534
535 struct mlx5_ifc_flow_table_nic_cap_bits {
536         u8         nic_rx_multi_path_tirs[0x1];
537         u8         nic_rx_multi_path_tirs_fts[0x1];
538         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
539         u8         reserved_at_3[0x1fd];
540
541         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
542
543         u8         reserved_at_400[0x200];
544
545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
546
547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
548
549         u8         reserved_at_a00[0x200];
550
551         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
552
553         u8         reserved_at_e00[0x7200];
554 };
555
556 struct mlx5_ifc_flow_table_eswitch_cap_bits {
557         u8      reserved_at_0[0x1c];
558         u8      fdb_multi_path_to_table[0x1];
559         u8      reserved_at_1d[0x1e3];
560
561         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
562
563         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
564
565         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
566
567         u8      reserved_at_800[0x7800];
568 };
569
570 struct mlx5_ifc_e_switch_cap_bits {
571         u8         vport_svlan_strip[0x1];
572         u8         vport_cvlan_strip[0x1];
573         u8         vport_svlan_insert[0x1];
574         u8         vport_cvlan_insert_if_not_exist[0x1];
575         u8         vport_cvlan_insert_overwrite[0x1];
576         u8         reserved_at_5[0x18];
577         u8         merged_eswitch[0x1];
578         u8         nic_vport_node_guid_modify[0x1];
579         u8         nic_vport_port_guid_modify[0x1];
580
581         u8         vxlan_encap_decap[0x1];
582         u8         nvgre_encap_decap[0x1];
583         u8         reserved_at_22[0x9];
584         u8         log_max_encap_headers[0x5];
585         u8         reserved_2b[0x6];
586         u8         max_encap_header_size[0xa];
587
588         u8         reserved_40[0x7c0];
589
590 };
591
592 struct mlx5_ifc_qos_cap_bits {
593         u8         packet_pacing[0x1];
594         u8         esw_scheduling[0x1];
595         u8         esw_bw_share[0x1];
596         u8         esw_rate_limit[0x1];
597         u8         reserved_at_4[0x1];
598         u8         packet_pacing_burst_bound[0x1];
599         u8         packet_pacing_typical_size[0x1];
600         u8         reserved_at_7[0x19];
601
602         u8         reserved_at_20[0x20];
603
604         u8         packet_pacing_max_rate[0x20];
605
606         u8         packet_pacing_min_rate[0x20];
607
608         u8         reserved_at_80[0x10];
609         u8         packet_pacing_rate_table_size[0x10];
610
611         u8         esw_element_type[0x10];
612         u8         esw_tsar_type[0x10];
613
614         u8         reserved_at_c0[0x10];
615         u8         max_qos_para_vport[0x10];
616
617         u8         max_tsar_bw_share[0x20];
618
619         u8         reserved_at_100[0x700];
620 };
621
622 struct mlx5_ifc_debug_cap_bits {
623         u8         reserved_at_0[0x20];
624
625         u8         reserved_at_20[0x2];
626         u8         stall_detect[0x1];
627         u8         reserved_at_23[0x1d];
628
629         u8         reserved_at_40[0x7c0];
630 };
631
632 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
633         u8         csum_cap[0x1];
634         u8         vlan_cap[0x1];
635         u8         lro_cap[0x1];
636         u8         lro_psh_flag[0x1];
637         u8         lro_time_stamp[0x1];
638         u8         reserved_at_5[0x2];
639         u8         wqe_vlan_insert[0x1];
640         u8         self_lb_en_modifiable[0x1];
641         u8         reserved_at_9[0x2];
642         u8         max_lso_cap[0x5];
643         u8         multi_pkt_send_wqe[0x2];
644         u8         wqe_inline_mode[0x2];
645         u8         rss_ind_tbl_cap[0x4];
646         u8         reg_umr_sq[0x1];
647         u8         scatter_fcs[0x1];
648         u8         enhanced_multi_pkt_send_wqe[0x1];
649         u8         tunnel_lso_const_out_ip_id[0x1];
650         u8         reserved_at_1c[0x2];
651         u8         tunnel_stateless_gre[0x1];
652         u8         tunnel_stateless_vxlan[0x1];
653
654         u8         swp[0x1];
655         u8         swp_csum[0x1];
656         u8         swp_lso[0x1];
657         u8         reserved_at_23[0x1b];
658         u8         max_geneve_opt_len[0x1];
659         u8         tunnel_stateless_geneve_rx[0x1];
660
661         u8         reserved_at_40[0x10];
662         u8         lro_min_mss_size[0x10];
663
664         u8         reserved_at_60[0x120];
665
666         u8         lro_timer_supported_periods[4][0x20];
667
668         u8         reserved_at_200[0x600];
669 };
670
671 struct mlx5_ifc_roce_cap_bits {
672         u8         roce_apm[0x1];
673         u8         reserved_at_1[0x1f];
674
675         u8         reserved_at_20[0x60];
676
677         u8         reserved_at_80[0xc];
678         u8         l3_type[0x4];
679         u8         reserved_at_90[0x8];
680         u8         roce_version[0x8];
681
682         u8         reserved_at_a0[0x10];
683         u8         r_roce_dest_udp_port[0x10];
684
685         u8         r_roce_max_src_udp_port[0x10];
686         u8         r_roce_min_src_udp_port[0x10];
687
688         u8         reserved_at_e0[0x10];
689         u8         roce_address_table_size[0x10];
690
691         u8         reserved_at_100[0x700];
692 };
693
694 struct mlx5_ifc_device_mem_cap_bits {
695         u8         memic[0x1];
696         u8         reserved_at_1[0x1f];
697
698         u8         reserved_at_20[0xb];
699         u8         log_min_memic_alloc_size[0x5];
700         u8         reserved_at_30[0x8];
701         u8         log_max_memic_addr_alignment[0x8];
702
703         u8         memic_bar_start_addr[0x40];
704
705         u8         memic_bar_size[0x20];
706
707         u8         max_memic_size[0x20];
708
709         u8         reserved_at_c0[0x740];
710 };
711
712 enum {
713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
717         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
718         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
719         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
720         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
721         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
722 };
723
724 enum {
725         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
726         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
727         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
728         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
729         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
730         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
733         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
734 };
735
736 struct mlx5_ifc_atomic_caps_bits {
737         u8         reserved_at_0[0x40];
738
739         u8         atomic_req_8B_endianness_mode[0x2];
740         u8         reserved_at_42[0x4];
741         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
742
743         u8         reserved_at_47[0x19];
744
745         u8         reserved_at_60[0x20];
746
747         u8         reserved_at_80[0x10];
748         u8         atomic_operations[0x10];
749
750         u8         reserved_at_a0[0x10];
751         u8         atomic_size_qp[0x10];
752
753         u8         reserved_at_c0[0x10];
754         u8         atomic_size_dc[0x10];
755
756         u8         reserved_at_e0[0x720];
757 };
758
759 struct mlx5_ifc_odp_cap_bits {
760         u8         reserved_at_0[0x40];
761
762         u8         sig[0x1];
763         u8         reserved_at_41[0x1f];
764
765         u8         reserved_at_60[0x20];
766
767         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
768
769         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
770
771         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
772
773         u8         reserved_at_e0[0x720];
774 };
775
776 struct mlx5_ifc_calc_op {
777         u8        reserved_at_0[0x10];
778         u8        reserved_at_10[0x9];
779         u8        op_swap_endianness[0x1];
780         u8        op_min[0x1];
781         u8        op_xor[0x1];
782         u8        op_or[0x1];
783         u8        op_and[0x1];
784         u8        op_max[0x1];
785         u8        op_add[0x1];
786 };
787
788 struct mlx5_ifc_vector_calc_cap_bits {
789         u8         calc_matrix[0x1];
790         u8         reserved_at_1[0x1f];
791         u8         reserved_at_20[0x8];
792         u8         max_vec_count[0x8];
793         u8         reserved_at_30[0xd];
794         u8         max_chunk_size[0x3];
795         struct mlx5_ifc_calc_op calc0;
796         struct mlx5_ifc_calc_op calc1;
797         struct mlx5_ifc_calc_op calc2;
798         struct mlx5_ifc_calc_op calc3;
799
800         u8         reserved_at_e0[0x720];
801 };
802
803 enum {
804         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
805         MLX5_WQ_TYPE_CYCLIC       = 0x1,
806         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
807         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
808 };
809
810 enum {
811         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
812         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
813 };
814
815 enum {
816         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
817         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
818         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
819         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
820         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
821 };
822
823 enum {
824         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
825         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
826         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
827         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
828         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
829         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
830 };
831
832 enum {
833         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
834         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
835 };
836
837 enum {
838         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
839         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
840         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
841 };
842
843 enum {
844         MLX5_CAP_PORT_TYPE_IB  = 0x0,
845         MLX5_CAP_PORT_TYPE_ETH = 0x1,
846 };
847
848 enum {
849         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
850         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
851         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
852 };
853
854 struct mlx5_ifc_cmd_hca_cap_bits {
855         u8         reserved_at_0[0x30];
856         u8         vhca_id[0x10];
857
858         u8         reserved_at_40[0x40];
859
860         u8         log_max_srq_sz[0x8];
861         u8         log_max_qp_sz[0x8];
862         u8         reserved_at_90[0xb];
863         u8         log_max_qp[0x5];
864
865         u8         reserved_at_a0[0xb];
866         u8         log_max_srq[0x5];
867         u8         reserved_at_b0[0x10];
868
869         u8         reserved_at_c0[0x8];
870         u8         log_max_cq_sz[0x8];
871         u8         reserved_at_d0[0xb];
872         u8         log_max_cq[0x5];
873
874         u8         log_max_eq_sz[0x8];
875         u8         reserved_at_e8[0x2];
876         u8         log_max_mkey[0x6];
877         u8         reserved_at_f0[0xc];
878         u8         log_max_eq[0x4];
879
880         u8         max_indirection[0x8];
881         u8         fixed_buffer_size[0x1];
882         u8         log_max_mrw_sz[0x7];
883         u8         force_teardown[0x1];
884         u8         reserved_at_111[0x1];
885         u8         log_max_bsf_list_size[0x6];
886         u8         umr_extended_translation_offset[0x1];
887         u8         null_mkey[0x1];
888         u8         log_max_klm_list_size[0x6];
889
890         u8         reserved_at_120[0xa];
891         u8         log_max_ra_req_dc[0x6];
892         u8         reserved_at_130[0xa];
893         u8         log_max_ra_res_dc[0x6];
894
895         u8         reserved_at_140[0xa];
896         u8         log_max_ra_req_qp[0x6];
897         u8         reserved_at_150[0xa];
898         u8         log_max_ra_res_qp[0x6];
899
900         u8         end_pad[0x1];
901         u8         cc_query_allowed[0x1];
902         u8         cc_modify_allowed[0x1];
903         u8         start_pad[0x1];
904         u8         cache_line_128byte[0x1];
905         u8         reserved_at_165[0xa];
906         u8         qcam_reg[0x1];
907         u8         gid_table_size[0x10];
908
909         u8         out_of_seq_cnt[0x1];
910         u8         vport_counters[0x1];
911         u8         retransmission_q_counters[0x1];
912         u8         debug[0x1];
913         u8         modify_rq_counter_set_id[0x1];
914         u8         rq_delay_drop[0x1];
915         u8         max_qp_cnt[0xa];
916         u8         pkey_table_size[0x10];
917
918         u8         vport_group_manager[0x1];
919         u8         vhca_group_manager[0x1];
920         u8         ib_virt[0x1];
921         u8         eth_virt[0x1];
922         u8         vnic_env_queue_counters[0x1];
923         u8         ets[0x1];
924         u8         nic_flow_table[0x1];
925         u8         eswitch_flow_table[0x1];
926         u8         device_memory[0x1];
927         u8         mcam_reg[0x1];
928         u8         pcam_reg[0x1];
929         u8         local_ca_ack_delay[0x5];
930         u8         port_module_event[0x1];
931         u8         enhanced_error_q_counters[0x1];
932         u8         ports_check[0x1];
933         u8         reserved_at_1b3[0x1];
934         u8         disable_link_up[0x1];
935         u8         beacon_led[0x1];
936         u8         port_type[0x2];
937         u8         num_ports[0x8];
938
939         u8         reserved_at_1c0[0x1];
940         u8         pps[0x1];
941         u8         pps_modify[0x1];
942         u8         log_max_msg[0x5];
943         u8         reserved_at_1c8[0x4];
944         u8         max_tc[0x4];
945         u8         temp_warn_event[0x1];
946         u8         dcbx[0x1];
947         u8         general_notification_event[0x1];
948         u8         reserved_at_1d3[0x2];
949         u8         fpga[0x1];
950         u8         rol_s[0x1];
951         u8         rol_g[0x1];
952         u8         reserved_at_1d8[0x1];
953         u8         wol_s[0x1];
954         u8         wol_g[0x1];
955         u8         wol_a[0x1];
956         u8         wol_b[0x1];
957         u8         wol_m[0x1];
958         u8         wol_u[0x1];
959         u8         wol_p[0x1];
960
961         u8         stat_rate_support[0x10];
962         u8         reserved_at_1f0[0xc];
963         u8         cqe_version[0x4];
964
965         u8         compact_address_vector[0x1];
966         u8         striding_rq[0x1];
967         u8         reserved_at_202[0x1];
968         u8         ipoib_enhanced_offloads[0x1];
969         u8         ipoib_basic_offloads[0x1];
970         u8         reserved_at_205[0x1];
971         u8         repeated_block_disabled[0x1];
972         u8         umr_modify_entity_size_disabled[0x1];
973         u8         umr_modify_atomic_disabled[0x1];
974         u8         umr_indirect_mkey_disabled[0x1];
975         u8         umr_fence[0x2];
976         u8         reserved_at_20c[0x3];
977         u8         drain_sigerr[0x1];
978         u8         cmdif_checksum[0x2];
979         u8         sigerr_cqe[0x1];
980         u8         reserved_at_213[0x1];
981         u8         wq_signature[0x1];
982         u8         sctr_data_cqe[0x1];
983         u8         reserved_at_216[0x1];
984         u8         sho[0x1];
985         u8         tph[0x1];
986         u8         rf[0x1];
987         u8         dct[0x1];
988         u8         qos[0x1];
989         u8         eth_net_offloads[0x1];
990         u8         roce[0x1];
991         u8         atomic[0x1];
992         u8         reserved_at_21f[0x1];
993
994         u8         cq_oi[0x1];
995         u8         cq_resize[0x1];
996         u8         cq_moderation[0x1];
997         u8         reserved_at_223[0x3];
998         u8         cq_eq_remap[0x1];
999         u8         pg[0x1];
1000         u8         block_lb_mc[0x1];
1001         u8         reserved_at_229[0x1];
1002         u8         scqe_break_moderation[0x1];
1003         u8         cq_period_start_from_cqe[0x1];
1004         u8         cd[0x1];
1005         u8         reserved_at_22d[0x1];
1006         u8         apm[0x1];
1007         u8         vector_calc[0x1];
1008         u8         umr_ptr_rlky[0x1];
1009         u8         imaicl[0x1];
1010         u8         reserved_at_232[0x4];
1011         u8         qkv[0x1];
1012         u8         pkv[0x1];
1013         u8         set_deth_sqpn[0x1];
1014         u8         reserved_at_239[0x3];
1015         u8         xrc[0x1];
1016         u8         ud[0x1];
1017         u8         uc[0x1];
1018         u8         rc[0x1];
1019
1020         u8         uar_4k[0x1];
1021         u8         reserved_at_241[0x9];
1022         u8         uar_sz[0x6];
1023         u8         reserved_at_250[0x8];
1024         u8         log_pg_sz[0x8];
1025
1026         u8         bf[0x1];
1027         u8         driver_version[0x1];
1028         u8         pad_tx_eth_packet[0x1];
1029         u8         reserved_at_263[0x8];
1030         u8         log_bf_reg_size[0x5];
1031
1032         u8         reserved_at_270[0xb];
1033         u8         lag_master[0x1];
1034         u8         num_lag_ports[0x4];
1035
1036         u8         reserved_at_280[0x10];
1037         u8         max_wqe_sz_sq[0x10];
1038
1039         u8         reserved_at_2a0[0x10];
1040         u8         max_wqe_sz_rq[0x10];
1041
1042         u8         max_flow_counter_31_16[0x10];
1043         u8         max_wqe_sz_sq_dc[0x10];
1044
1045         u8         reserved_at_2e0[0x7];
1046         u8         max_qp_mcg[0x19];
1047
1048         u8         reserved_at_300[0x18];
1049         u8         log_max_mcg[0x8];
1050
1051         u8         reserved_at_320[0x3];
1052         u8         log_max_transport_domain[0x5];
1053         u8         reserved_at_328[0x3];
1054         u8         log_max_pd[0x5];
1055         u8         reserved_at_330[0xb];
1056         u8         log_max_xrcd[0x5];
1057
1058         u8         nic_receive_steering_discard[0x1];
1059         u8         receive_discard_vport_down[0x1];
1060         u8         transmit_discard_vport_down[0x1];
1061         u8         reserved_at_343[0x5];
1062         u8         log_max_flow_counter_bulk[0x8];
1063         u8         max_flow_counter_15_0[0x10];
1064
1065
1066         u8         reserved_at_360[0x3];
1067         u8         log_max_rq[0x5];
1068         u8         reserved_at_368[0x3];
1069         u8         log_max_sq[0x5];
1070         u8         reserved_at_370[0x3];
1071         u8         log_max_tir[0x5];
1072         u8         reserved_at_378[0x3];
1073         u8         log_max_tis[0x5];
1074
1075         u8         basic_cyclic_rcv_wqe[0x1];
1076         u8         reserved_at_381[0x2];
1077         u8         log_max_rmp[0x5];
1078         u8         reserved_at_388[0x3];
1079         u8         log_max_rqt[0x5];
1080         u8         reserved_at_390[0x3];
1081         u8         log_max_rqt_size[0x5];
1082         u8         reserved_at_398[0x3];
1083         u8         log_max_tis_per_sq[0x5];
1084
1085         u8         ext_stride_num_range[0x1];
1086         u8         reserved_at_3a1[0x2];
1087         u8         log_max_stride_sz_rq[0x5];
1088         u8         reserved_at_3a8[0x3];
1089         u8         log_min_stride_sz_rq[0x5];
1090         u8         reserved_at_3b0[0x3];
1091         u8         log_max_stride_sz_sq[0x5];
1092         u8         reserved_at_3b8[0x3];
1093         u8         log_min_stride_sz_sq[0x5];
1094
1095         u8         hairpin[0x1];
1096         u8         reserved_at_3c1[0x2];
1097         u8         log_max_hairpin_queues[0x5];
1098         u8         reserved_at_3c8[0x3];
1099         u8         log_max_hairpin_wq_data_sz[0x5];
1100         u8         reserved_at_3d0[0x3];
1101         u8         log_max_hairpin_num_packets[0x5];
1102         u8         reserved_at_3d8[0x3];
1103         u8         log_max_wq_sz[0x5];
1104
1105         u8         nic_vport_change_event[0x1];
1106         u8         disable_local_lb_uc[0x1];
1107         u8         disable_local_lb_mc[0x1];
1108         u8         log_min_hairpin_wq_data_sz[0x5];
1109         u8         reserved_at_3e8[0x3];
1110         u8         log_max_vlan_list[0x5];
1111         u8         reserved_at_3f0[0x3];
1112         u8         log_max_current_mc_list[0x5];
1113         u8         reserved_at_3f8[0x3];
1114         u8         log_max_current_uc_list[0x5];
1115
1116         u8         reserved_at_400[0x80];
1117
1118         u8         reserved_at_480[0x3];
1119         u8         log_max_l2_table[0x5];
1120         u8         reserved_at_488[0x8];
1121         u8         log_uar_page_sz[0x10];
1122
1123         u8         reserved_at_4a0[0x20];
1124         u8         device_frequency_mhz[0x20];
1125         u8         device_frequency_khz[0x20];
1126
1127         u8         reserved_at_500[0x20];
1128         u8         num_of_uars_per_page[0x20];
1129
1130         u8         flex_parser_protocols[0x20];
1131         u8         reserved_at_560[0x20];
1132
1133         u8         reserved_at_580[0x3c];
1134         u8         mini_cqe_resp_stride_index[0x1];
1135         u8         cqe_128_always[0x1];
1136         u8         cqe_compression_128[0x1];
1137         u8         cqe_compression[0x1];
1138
1139         u8         cqe_compression_timeout[0x10];
1140         u8         cqe_compression_max_num[0x10];
1141
1142         u8         reserved_at_5e0[0x10];
1143         u8         tag_matching[0x1];
1144         u8         rndv_offload_rc[0x1];
1145         u8         rndv_offload_dc[0x1];
1146         u8         log_tag_matching_list_sz[0x5];
1147         u8         reserved_at_5f8[0x3];
1148         u8         log_max_xrq[0x5];
1149
1150         u8         affiliate_nic_vport_criteria[0x8];
1151         u8         native_port_num[0x8];
1152         u8         num_vhca_ports[0x8];
1153         u8         reserved_at_618[0x6];
1154         u8         sw_owner_id[0x1];
1155         u8         reserved_at_61f[0x1e1];
1156 };
1157
1158 enum mlx5_flow_destination_type {
1159         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1160         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1161         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1162
1163         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1164         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1165 };
1166
1167 struct mlx5_ifc_dest_format_struct_bits {
1168         u8         destination_type[0x8];
1169         u8         destination_id[0x18];
1170         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1171         u8         reserved_at_21[0xf];
1172         u8         destination_eswitch_owner_vhca_id[0x10];
1173 };
1174
1175 struct mlx5_ifc_flow_counter_list_bits {
1176         u8         flow_counter_id[0x20];
1177
1178         u8         reserved_at_20[0x20];
1179 };
1180
1181 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1182         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1183         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1184         u8         reserved_at_0[0x40];
1185 };
1186
1187 struct mlx5_ifc_fte_match_param_bits {
1188         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1189
1190         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1191
1192         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1193
1194         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1195
1196         u8         reserved_at_800[0x800];
1197 };
1198
1199 enum {
1200         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1201         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1202         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1203         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1204         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1205 };
1206
1207 struct mlx5_ifc_rx_hash_field_select_bits {
1208         u8         l3_prot_type[0x1];
1209         u8         l4_prot_type[0x1];
1210         u8         selected_fields[0x1e];
1211 };
1212
1213 enum {
1214         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1215         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1216 };
1217
1218 enum {
1219         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1220         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1221 };
1222
1223 struct mlx5_ifc_wq_bits {
1224         u8         wq_type[0x4];
1225         u8         wq_signature[0x1];
1226         u8         end_padding_mode[0x2];
1227         u8         cd_slave[0x1];
1228         u8         reserved_at_8[0x18];
1229
1230         u8         hds_skip_first_sge[0x1];
1231         u8         log2_hds_buf_size[0x3];
1232         u8         reserved_at_24[0x7];
1233         u8         page_offset[0x5];
1234         u8         lwm[0x10];
1235
1236         u8         reserved_at_40[0x8];
1237         u8         pd[0x18];
1238
1239         u8         reserved_at_60[0x8];
1240         u8         uar_page[0x18];
1241
1242         u8         dbr_addr[0x40];
1243
1244         u8         hw_counter[0x20];
1245
1246         u8         sw_counter[0x20];
1247
1248         u8         reserved_at_100[0xc];
1249         u8         log_wq_stride[0x4];
1250         u8         reserved_at_110[0x3];
1251         u8         log_wq_pg_sz[0x5];
1252         u8         reserved_at_118[0x3];
1253         u8         log_wq_sz[0x5];
1254
1255         u8         reserved_at_120[0x3];
1256         u8         log_hairpin_num_packets[0x5];
1257         u8         reserved_at_128[0x3];
1258         u8         log_hairpin_data_sz[0x5];
1259
1260         u8         reserved_at_130[0x4];
1261         u8         log_wqe_num_of_strides[0x4];
1262         u8         two_byte_shift_en[0x1];
1263         u8         reserved_at_139[0x4];
1264         u8         log_wqe_stride_size[0x3];
1265
1266         u8         reserved_at_140[0x4c0];
1267
1268         struct mlx5_ifc_cmd_pas_bits pas[0];
1269 };
1270
1271 struct mlx5_ifc_rq_num_bits {
1272         u8         reserved_at_0[0x8];
1273         u8         rq_num[0x18];
1274 };
1275
1276 struct mlx5_ifc_mac_address_layout_bits {
1277         u8         reserved_at_0[0x10];
1278         u8         mac_addr_47_32[0x10];
1279
1280         u8         mac_addr_31_0[0x20];
1281 };
1282
1283 struct mlx5_ifc_vlan_layout_bits {
1284         u8         reserved_at_0[0x14];
1285         u8         vlan[0x0c];
1286
1287         u8         reserved_at_20[0x20];
1288 };
1289
1290 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1291         u8         reserved_at_0[0xa0];
1292
1293         u8         min_time_between_cnps[0x20];
1294
1295         u8         reserved_at_c0[0x12];
1296         u8         cnp_dscp[0x6];
1297         u8         reserved_at_d8[0x4];
1298         u8         cnp_prio_mode[0x1];
1299         u8         cnp_802p_prio[0x3];
1300
1301         u8         reserved_at_e0[0x720];
1302 };
1303
1304 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1305         u8         reserved_at_0[0x60];
1306
1307         u8         reserved_at_60[0x4];
1308         u8         clamp_tgt_rate[0x1];
1309         u8         reserved_at_65[0x3];
1310         u8         clamp_tgt_rate_after_time_inc[0x1];
1311         u8         reserved_at_69[0x17];
1312
1313         u8         reserved_at_80[0x20];
1314
1315         u8         rpg_time_reset[0x20];
1316
1317         u8         rpg_byte_reset[0x20];
1318
1319         u8         rpg_threshold[0x20];
1320
1321         u8         rpg_max_rate[0x20];
1322
1323         u8         rpg_ai_rate[0x20];
1324
1325         u8         rpg_hai_rate[0x20];
1326
1327         u8         rpg_gd[0x20];
1328
1329         u8         rpg_min_dec_fac[0x20];
1330
1331         u8         rpg_min_rate[0x20];
1332
1333         u8         reserved_at_1c0[0xe0];
1334
1335         u8         rate_to_set_on_first_cnp[0x20];
1336
1337         u8         dce_tcp_g[0x20];
1338
1339         u8         dce_tcp_rtt[0x20];
1340
1341         u8         rate_reduce_monitor_period[0x20];
1342
1343         u8         reserved_at_320[0x20];
1344
1345         u8         initial_alpha_value[0x20];
1346
1347         u8         reserved_at_360[0x4a0];
1348 };
1349
1350 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1351         u8         reserved_at_0[0x80];
1352
1353         u8         rppp_max_rps[0x20];
1354
1355         u8         rpg_time_reset[0x20];
1356
1357         u8         rpg_byte_reset[0x20];
1358
1359         u8         rpg_threshold[0x20];
1360
1361         u8         rpg_max_rate[0x20];
1362
1363         u8         rpg_ai_rate[0x20];
1364
1365         u8         rpg_hai_rate[0x20];
1366
1367         u8         rpg_gd[0x20];
1368
1369         u8         rpg_min_dec_fac[0x20];
1370
1371         u8         rpg_min_rate[0x20];
1372
1373         u8         reserved_at_1c0[0x640];
1374 };
1375
1376 enum {
1377         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1378         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1379         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1380 };
1381
1382 struct mlx5_ifc_resize_field_select_bits {
1383         u8         resize_field_select[0x20];
1384 };
1385
1386 enum {
1387         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1388         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1389         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1390         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1391 };
1392
1393 struct mlx5_ifc_modify_field_select_bits {
1394         u8         modify_field_select[0x20];
1395 };
1396
1397 struct mlx5_ifc_field_select_r_roce_np_bits {
1398         u8         field_select_r_roce_np[0x20];
1399 };
1400
1401 struct mlx5_ifc_field_select_r_roce_rp_bits {
1402         u8         field_select_r_roce_rp[0x20];
1403 };
1404
1405 enum {
1406         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1407         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1408         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1409         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1410         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1411         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1412         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1413         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1414         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1415         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1416 };
1417
1418 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1419         u8         field_select_8021qaurp[0x20];
1420 };
1421
1422 struct mlx5_ifc_phys_layer_cntrs_bits {
1423         u8         time_since_last_clear_high[0x20];
1424
1425         u8         time_since_last_clear_low[0x20];
1426
1427         u8         symbol_errors_high[0x20];
1428
1429         u8         symbol_errors_low[0x20];
1430
1431         u8         sync_headers_errors_high[0x20];
1432
1433         u8         sync_headers_errors_low[0x20];
1434
1435         u8         edpl_bip_errors_lane0_high[0x20];
1436
1437         u8         edpl_bip_errors_lane0_low[0x20];
1438
1439         u8         edpl_bip_errors_lane1_high[0x20];
1440
1441         u8         edpl_bip_errors_lane1_low[0x20];
1442
1443         u8         edpl_bip_errors_lane2_high[0x20];
1444
1445         u8         edpl_bip_errors_lane2_low[0x20];
1446
1447         u8         edpl_bip_errors_lane3_high[0x20];
1448
1449         u8         edpl_bip_errors_lane3_low[0x20];
1450
1451         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1452
1453         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1454
1455         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1456
1457         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1458
1459         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1460
1461         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1462
1463         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1464
1465         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1466
1467         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1468
1469         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1470
1471         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1472
1473         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1474
1475         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1476
1477         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1478
1479         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1480
1481         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1482
1483         u8         rs_fec_corrected_blocks_high[0x20];
1484
1485         u8         rs_fec_corrected_blocks_low[0x20];
1486
1487         u8         rs_fec_uncorrectable_blocks_high[0x20];
1488
1489         u8         rs_fec_uncorrectable_blocks_low[0x20];
1490
1491         u8         rs_fec_no_errors_blocks_high[0x20];
1492
1493         u8         rs_fec_no_errors_blocks_low[0x20];
1494
1495         u8         rs_fec_single_error_blocks_high[0x20];
1496
1497         u8         rs_fec_single_error_blocks_low[0x20];
1498
1499         u8         rs_fec_corrected_symbols_total_high[0x20];
1500
1501         u8         rs_fec_corrected_symbols_total_low[0x20];
1502
1503         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1504
1505         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1506
1507         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1508
1509         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1510
1511         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1512
1513         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1514
1515         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1516
1517         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1518
1519         u8         link_down_events[0x20];
1520
1521         u8         successful_recovery_events[0x20];
1522
1523         u8         reserved_at_640[0x180];
1524 };
1525
1526 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1527         u8         time_since_last_clear_high[0x20];
1528
1529         u8         time_since_last_clear_low[0x20];
1530
1531         u8         phy_received_bits_high[0x20];
1532
1533         u8         phy_received_bits_low[0x20];
1534
1535         u8         phy_symbol_errors_high[0x20];
1536
1537         u8         phy_symbol_errors_low[0x20];
1538
1539         u8         phy_corrected_bits_high[0x20];
1540
1541         u8         phy_corrected_bits_low[0x20];
1542
1543         u8         phy_corrected_bits_lane0_high[0x20];
1544
1545         u8         phy_corrected_bits_lane0_low[0x20];
1546
1547         u8         phy_corrected_bits_lane1_high[0x20];
1548
1549         u8         phy_corrected_bits_lane1_low[0x20];
1550
1551         u8         phy_corrected_bits_lane2_high[0x20];
1552
1553         u8         phy_corrected_bits_lane2_low[0x20];
1554
1555         u8         phy_corrected_bits_lane3_high[0x20];
1556
1557         u8         phy_corrected_bits_lane3_low[0x20];
1558
1559         u8         reserved_at_200[0x5c0];
1560 };
1561
1562 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1563         u8         symbol_error_counter[0x10];
1564
1565         u8         link_error_recovery_counter[0x8];
1566
1567         u8         link_downed_counter[0x8];
1568
1569         u8         port_rcv_errors[0x10];
1570
1571         u8         port_rcv_remote_physical_errors[0x10];
1572
1573         u8         port_rcv_switch_relay_errors[0x10];
1574
1575         u8         port_xmit_discards[0x10];
1576
1577         u8         port_xmit_constraint_errors[0x8];
1578
1579         u8         port_rcv_constraint_errors[0x8];
1580
1581         u8         reserved_at_70[0x8];
1582
1583         u8         link_overrun_errors[0x8];
1584
1585         u8         reserved_at_80[0x10];
1586
1587         u8         vl_15_dropped[0x10];
1588
1589         u8         reserved_at_a0[0x80];
1590
1591         u8         port_xmit_wait[0x20];
1592 };
1593
1594 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1595         u8         transmit_queue_high[0x20];
1596
1597         u8         transmit_queue_low[0x20];
1598
1599         u8         reserved_at_40[0x780];
1600 };
1601
1602 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1603         u8         rx_octets_high[0x20];
1604
1605         u8         rx_octets_low[0x20];
1606
1607         u8         reserved_at_40[0xc0];
1608
1609         u8         rx_frames_high[0x20];
1610
1611         u8         rx_frames_low[0x20];
1612
1613         u8         tx_octets_high[0x20];
1614
1615         u8         tx_octets_low[0x20];
1616
1617         u8         reserved_at_180[0xc0];
1618
1619         u8         tx_frames_high[0x20];
1620
1621         u8         tx_frames_low[0x20];
1622
1623         u8         rx_pause_high[0x20];
1624
1625         u8         rx_pause_low[0x20];
1626
1627         u8         rx_pause_duration_high[0x20];
1628
1629         u8         rx_pause_duration_low[0x20];
1630
1631         u8         tx_pause_high[0x20];
1632
1633         u8         tx_pause_low[0x20];
1634
1635         u8         tx_pause_duration_high[0x20];
1636
1637         u8         tx_pause_duration_low[0x20];
1638
1639         u8         rx_pause_transition_high[0x20];
1640
1641         u8         rx_pause_transition_low[0x20];
1642
1643         u8         reserved_at_3c0[0x40];
1644
1645         u8         device_stall_minor_watermark_cnt_high[0x20];
1646
1647         u8         device_stall_minor_watermark_cnt_low[0x20];
1648
1649         u8         device_stall_critical_watermark_cnt_high[0x20];
1650
1651         u8         device_stall_critical_watermark_cnt_low[0x20];
1652
1653         u8         reserved_at_480[0x340];
1654 };
1655
1656 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1657         u8         port_transmit_wait_high[0x20];
1658
1659         u8         port_transmit_wait_low[0x20];
1660
1661         u8         reserved_at_40[0x100];
1662
1663         u8         rx_buffer_almost_full_high[0x20];
1664
1665         u8         rx_buffer_almost_full_low[0x20];
1666
1667         u8         rx_buffer_full_high[0x20];
1668
1669         u8         rx_buffer_full_low[0x20];
1670
1671         u8         reserved_at_1c0[0x600];
1672 };
1673
1674 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1675         u8         dot3stats_alignment_errors_high[0x20];
1676
1677         u8         dot3stats_alignment_errors_low[0x20];
1678
1679         u8         dot3stats_fcs_errors_high[0x20];
1680
1681         u8         dot3stats_fcs_errors_low[0x20];
1682
1683         u8         dot3stats_single_collision_frames_high[0x20];
1684
1685         u8         dot3stats_single_collision_frames_low[0x20];
1686
1687         u8         dot3stats_multiple_collision_frames_high[0x20];
1688
1689         u8         dot3stats_multiple_collision_frames_low[0x20];
1690
1691         u8         dot3stats_sqe_test_errors_high[0x20];
1692
1693         u8         dot3stats_sqe_test_errors_low[0x20];
1694
1695         u8         dot3stats_deferred_transmissions_high[0x20];
1696
1697         u8         dot3stats_deferred_transmissions_low[0x20];
1698
1699         u8         dot3stats_late_collisions_high[0x20];
1700
1701         u8         dot3stats_late_collisions_low[0x20];
1702
1703         u8         dot3stats_excessive_collisions_high[0x20];
1704
1705         u8         dot3stats_excessive_collisions_low[0x20];
1706
1707         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1708
1709         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1710
1711         u8         dot3stats_carrier_sense_errors_high[0x20];
1712
1713         u8         dot3stats_carrier_sense_errors_low[0x20];
1714
1715         u8         dot3stats_frame_too_longs_high[0x20];
1716
1717         u8         dot3stats_frame_too_longs_low[0x20];
1718
1719         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1720
1721         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1722
1723         u8         dot3stats_symbol_errors_high[0x20];
1724
1725         u8         dot3stats_symbol_errors_low[0x20];
1726
1727         u8         dot3control_in_unknown_opcodes_high[0x20];
1728
1729         u8         dot3control_in_unknown_opcodes_low[0x20];
1730
1731         u8         dot3in_pause_frames_high[0x20];
1732
1733         u8         dot3in_pause_frames_low[0x20];
1734
1735         u8         dot3out_pause_frames_high[0x20];
1736
1737         u8         dot3out_pause_frames_low[0x20];
1738
1739         u8         reserved_at_400[0x3c0];
1740 };
1741
1742 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1743         u8         ether_stats_drop_events_high[0x20];
1744
1745         u8         ether_stats_drop_events_low[0x20];
1746
1747         u8         ether_stats_octets_high[0x20];
1748
1749         u8         ether_stats_octets_low[0x20];
1750
1751         u8         ether_stats_pkts_high[0x20];
1752
1753         u8         ether_stats_pkts_low[0x20];
1754
1755         u8         ether_stats_broadcast_pkts_high[0x20];
1756
1757         u8         ether_stats_broadcast_pkts_low[0x20];
1758
1759         u8         ether_stats_multicast_pkts_high[0x20];
1760
1761         u8         ether_stats_multicast_pkts_low[0x20];
1762
1763         u8         ether_stats_crc_align_errors_high[0x20];
1764
1765         u8         ether_stats_crc_align_errors_low[0x20];
1766
1767         u8         ether_stats_undersize_pkts_high[0x20];
1768
1769         u8         ether_stats_undersize_pkts_low[0x20];
1770
1771         u8         ether_stats_oversize_pkts_high[0x20];
1772
1773         u8         ether_stats_oversize_pkts_low[0x20];
1774
1775         u8         ether_stats_fragments_high[0x20];
1776
1777         u8         ether_stats_fragments_low[0x20];
1778
1779         u8         ether_stats_jabbers_high[0x20];
1780
1781         u8         ether_stats_jabbers_low[0x20];
1782
1783         u8         ether_stats_collisions_high[0x20];
1784
1785         u8         ether_stats_collisions_low[0x20];
1786
1787         u8         ether_stats_pkts64octets_high[0x20];
1788
1789         u8         ether_stats_pkts64octets_low[0x20];
1790
1791         u8         ether_stats_pkts65to127octets_high[0x20];
1792
1793         u8         ether_stats_pkts65to127octets_low[0x20];
1794
1795         u8         ether_stats_pkts128to255octets_high[0x20];
1796
1797         u8         ether_stats_pkts128to255octets_low[0x20];
1798
1799         u8         ether_stats_pkts256to511octets_high[0x20];
1800
1801         u8         ether_stats_pkts256to511octets_low[0x20];
1802
1803         u8         ether_stats_pkts512to1023octets_high[0x20];
1804
1805         u8         ether_stats_pkts512to1023octets_low[0x20];
1806
1807         u8         ether_stats_pkts1024to1518octets_high[0x20];
1808
1809         u8         ether_stats_pkts1024to1518octets_low[0x20];
1810
1811         u8         ether_stats_pkts1519to2047octets_high[0x20];
1812
1813         u8         ether_stats_pkts1519to2047octets_low[0x20];
1814
1815         u8         ether_stats_pkts2048to4095octets_high[0x20];
1816
1817         u8         ether_stats_pkts2048to4095octets_low[0x20];
1818
1819         u8         ether_stats_pkts4096to8191octets_high[0x20];
1820
1821         u8         ether_stats_pkts4096to8191octets_low[0x20];
1822
1823         u8         ether_stats_pkts8192to10239octets_high[0x20];
1824
1825         u8         ether_stats_pkts8192to10239octets_low[0x20];
1826
1827         u8         reserved_at_540[0x280];
1828 };
1829
1830 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1831         u8         if_in_octets_high[0x20];
1832
1833         u8         if_in_octets_low[0x20];
1834
1835         u8         if_in_ucast_pkts_high[0x20];
1836
1837         u8         if_in_ucast_pkts_low[0x20];
1838
1839         u8         if_in_discards_high[0x20];
1840
1841         u8         if_in_discards_low[0x20];
1842
1843         u8         if_in_errors_high[0x20];
1844
1845         u8         if_in_errors_low[0x20];
1846
1847         u8         if_in_unknown_protos_high[0x20];
1848
1849         u8         if_in_unknown_protos_low[0x20];
1850
1851         u8         if_out_octets_high[0x20];
1852
1853         u8         if_out_octets_low[0x20];
1854
1855         u8         if_out_ucast_pkts_high[0x20];
1856
1857         u8         if_out_ucast_pkts_low[0x20];
1858
1859         u8         if_out_discards_high[0x20];
1860
1861         u8         if_out_discards_low[0x20];
1862
1863         u8         if_out_errors_high[0x20];
1864
1865         u8         if_out_errors_low[0x20];
1866
1867         u8         if_in_multicast_pkts_high[0x20];
1868
1869         u8         if_in_multicast_pkts_low[0x20];
1870
1871         u8         if_in_broadcast_pkts_high[0x20];
1872
1873         u8         if_in_broadcast_pkts_low[0x20];
1874
1875         u8         if_out_multicast_pkts_high[0x20];
1876
1877         u8         if_out_multicast_pkts_low[0x20];
1878
1879         u8         if_out_broadcast_pkts_high[0x20];
1880
1881         u8         if_out_broadcast_pkts_low[0x20];
1882
1883         u8         reserved_at_340[0x480];
1884 };
1885
1886 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1887         u8         a_frames_transmitted_ok_high[0x20];
1888
1889         u8         a_frames_transmitted_ok_low[0x20];
1890
1891         u8         a_frames_received_ok_high[0x20];
1892
1893         u8         a_frames_received_ok_low[0x20];
1894
1895         u8         a_frame_check_sequence_errors_high[0x20];
1896
1897         u8         a_frame_check_sequence_errors_low[0x20];
1898
1899         u8         a_alignment_errors_high[0x20];
1900
1901         u8         a_alignment_errors_low[0x20];
1902
1903         u8         a_octets_transmitted_ok_high[0x20];
1904
1905         u8         a_octets_transmitted_ok_low[0x20];
1906
1907         u8         a_octets_received_ok_high[0x20];
1908
1909         u8         a_octets_received_ok_low[0x20];
1910
1911         u8         a_multicast_frames_xmitted_ok_high[0x20];
1912
1913         u8         a_multicast_frames_xmitted_ok_low[0x20];
1914
1915         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1916
1917         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1918
1919         u8         a_multicast_frames_received_ok_high[0x20];
1920
1921         u8         a_multicast_frames_received_ok_low[0x20];
1922
1923         u8         a_broadcast_frames_received_ok_high[0x20];
1924
1925         u8         a_broadcast_frames_received_ok_low[0x20];
1926
1927         u8         a_in_range_length_errors_high[0x20];
1928
1929         u8         a_in_range_length_errors_low[0x20];
1930
1931         u8         a_out_of_range_length_field_high[0x20];
1932
1933         u8         a_out_of_range_length_field_low[0x20];
1934
1935         u8         a_frame_too_long_errors_high[0x20];
1936
1937         u8         a_frame_too_long_errors_low[0x20];
1938
1939         u8         a_symbol_error_during_carrier_high[0x20];
1940
1941         u8         a_symbol_error_during_carrier_low[0x20];
1942
1943         u8         a_mac_control_frames_transmitted_high[0x20];
1944
1945         u8         a_mac_control_frames_transmitted_low[0x20];
1946
1947         u8         a_mac_control_frames_received_high[0x20];
1948
1949         u8         a_mac_control_frames_received_low[0x20];
1950
1951         u8         a_unsupported_opcodes_received_high[0x20];
1952
1953         u8         a_unsupported_opcodes_received_low[0x20];
1954
1955         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1956
1957         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1958
1959         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1960
1961         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1962
1963         u8         reserved_at_4c0[0x300];
1964 };
1965
1966 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1967         u8         life_time_counter_high[0x20];
1968
1969         u8         life_time_counter_low[0x20];
1970
1971         u8         rx_errors[0x20];
1972
1973         u8         tx_errors[0x20];
1974
1975         u8         l0_to_recovery_eieos[0x20];
1976
1977         u8         l0_to_recovery_ts[0x20];
1978
1979         u8         l0_to_recovery_framing[0x20];
1980
1981         u8         l0_to_recovery_retrain[0x20];
1982
1983         u8         crc_error_dllp[0x20];
1984
1985         u8         crc_error_tlp[0x20];
1986
1987         u8         tx_overflow_buffer_pkt_high[0x20];
1988
1989         u8         tx_overflow_buffer_pkt_low[0x20];
1990
1991         u8         outbound_stalled_reads[0x20];
1992
1993         u8         outbound_stalled_writes[0x20];
1994
1995         u8         outbound_stalled_reads_events[0x20];
1996
1997         u8         outbound_stalled_writes_events[0x20];
1998
1999         u8         reserved_at_200[0x5c0];
2000 };
2001
2002 struct mlx5_ifc_cmd_inter_comp_event_bits {
2003         u8         command_completion_vector[0x20];
2004
2005         u8         reserved_at_20[0xc0];
2006 };
2007
2008 struct mlx5_ifc_stall_vl_event_bits {
2009         u8         reserved_at_0[0x18];
2010         u8         port_num[0x1];
2011         u8         reserved_at_19[0x3];
2012         u8         vl[0x4];
2013
2014         u8         reserved_at_20[0xa0];
2015 };
2016
2017 struct mlx5_ifc_db_bf_congestion_event_bits {
2018         u8         event_subtype[0x8];
2019         u8         reserved_at_8[0x8];
2020         u8         congestion_level[0x8];
2021         u8         reserved_at_18[0x8];
2022
2023         u8         reserved_at_20[0xa0];
2024 };
2025
2026 struct mlx5_ifc_gpio_event_bits {
2027         u8         reserved_at_0[0x60];
2028
2029         u8         gpio_event_hi[0x20];
2030
2031         u8         gpio_event_lo[0x20];
2032
2033         u8         reserved_at_a0[0x40];
2034 };
2035
2036 struct mlx5_ifc_port_state_change_event_bits {
2037         u8         reserved_at_0[0x40];
2038
2039         u8         port_num[0x4];
2040         u8         reserved_at_44[0x1c];
2041
2042         u8         reserved_at_60[0x80];
2043 };
2044
2045 struct mlx5_ifc_dropped_packet_logged_bits {
2046         u8         reserved_at_0[0xe0];
2047 };
2048
2049 enum {
2050         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2051         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2052 };
2053
2054 struct mlx5_ifc_cq_error_bits {
2055         u8         reserved_at_0[0x8];
2056         u8         cqn[0x18];
2057
2058         u8         reserved_at_20[0x20];
2059
2060         u8         reserved_at_40[0x18];
2061         u8         syndrome[0x8];
2062
2063         u8         reserved_at_60[0x80];
2064 };
2065
2066 struct mlx5_ifc_rdma_page_fault_event_bits {
2067         u8         bytes_committed[0x20];
2068
2069         u8         r_key[0x20];
2070
2071         u8         reserved_at_40[0x10];
2072         u8         packet_len[0x10];
2073
2074         u8         rdma_op_len[0x20];
2075
2076         u8         rdma_va[0x40];
2077
2078         u8         reserved_at_c0[0x5];
2079         u8         rdma[0x1];
2080         u8         write[0x1];
2081         u8         requestor[0x1];
2082         u8         qp_number[0x18];
2083 };
2084
2085 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2086         u8         bytes_committed[0x20];
2087
2088         u8         reserved_at_20[0x10];
2089         u8         wqe_index[0x10];
2090
2091         u8         reserved_at_40[0x10];
2092         u8         len[0x10];
2093
2094         u8         reserved_at_60[0x60];
2095
2096         u8         reserved_at_c0[0x5];
2097         u8         rdma[0x1];
2098         u8         write_read[0x1];
2099         u8         requestor[0x1];
2100         u8         qpn[0x18];
2101 };
2102
2103 struct mlx5_ifc_qp_events_bits {
2104         u8         reserved_at_0[0xa0];
2105
2106         u8         type[0x8];
2107         u8         reserved_at_a8[0x18];
2108
2109         u8         reserved_at_c0[0x8];
2110         u8         qpn_rqn_sqn[0x18];
2111 };
2112
2113 struct mlx5_ifc_dct_events_bits {
2114         u8         reserved_at_0[0xc0];
2115
2116         u8         reserved_at_c0[0x8];
2117         u8         dct_number[0x18];
2118 };
2119
2120 struct mlx5_ifc_comp_event_bits {
2121         u8         reserved_at_0[0xc0];
2122
2123         u8         reserved_at_c0[0x8];
2124         u8         cq_number[0x18];
2125 };
2126
2127 enum {
2128         MLX5_QPC_STATE_RST        = 0x0,
2129         MLX5_QPC_STATE_INIT       = 0x1,
2130         MLX5_QPC_STATE_RTR        = 0x2,
2131         MLX5_QPC_STATE_RTS        = 0x3,
2132         MLX5_QPC_STATE_SQER       = 0x4,
2133         MLX5_QPC_STATE_ERR        = 0x6,
2134         MLX5_QPC_STATE_SQD        = 0x7,
2135         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2136 };
2137
2138 enum {
2139         MLX5_QPC_ST_RC            = 0x0,
2140         MLX5_QPC_ST_UC            = 0x1,
2141         MLX5_QPC_ST_UD            = 0x2,
2142         MLX5_QPC_ST_XRC           = 0x3,
2143         MLX5_QPC_ST_DCI           = 0x5,
2144         MLX5_QPC_ST_QP0           = 0x7,
2145         MLX5_QPC_ST_QP1           = 0x8,
2146         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2147         MLX5_QPC_ST_REG_UMR       = 0xc,
2148 };
2149
2150 enum {
2151         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2152         MLX5_QPC_PM_STATE_REARM     = 0x1,
2153         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2154         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2155 };
2156
2157 enum {
2158         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2159 };
2160
2161 enum {
2162         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2163         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2164 };
2165
2166 enum {
2167         MLX5_QPC_MTU_256_BYTES        = 0x1,
2168         MLX5_QPC_MTU_512_BYTES        = 0x2,
2169         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2170         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2171         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2172         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2173 };
2174
2175 enum {
2176         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2177         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2178         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2179         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2180         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2181         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2182         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2183         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2184 };
2185
2186 enum {
2187         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2188         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2189         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2190 };
2191
2192 enum {
2193         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2194         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2195         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2196 };
2197
2198 struct mlx5_ifc_qpc_bits {
2199         u8         state[0x4];
2200         u8         lag_tx_port_affinity[0x4];
2201         u8         st[0x8];
2202         u8         reserved_at_10[0x3];
2203         u8         pm_state[0x2];
2204         u8         reserved_at_15[0x3];
2205         u8         offload_type[0x4];
2206         u8         end_padding_mode[0x2];
2207         u8         reserved_at_1e[0x2];
2208
2209         u8         wq_signature[0x1];
2210         u8         block_lb_mc[0x1];
2211         u8         atomic_like_write_en[0x1];
2212         u8         latency_sensitive[0x1];
2213         u8         reserved_at_24[0x1];
2214         u8         drain_sigerr[0x1];
2215         u8         reserved_at_26[0x2];
2216         u8         pd[0x18];
2217
2218         u8         mtu[0x3];
2219         u8         log_msg_max[0x5];
2220         u8         reserved_at_48[0x1];
2221         u8         log_rq_size[0x4];
2222         u8         log_rq_stride[0x3];
2223         u8         no_sq[0x1];
2224         u8         log_sq_size[0x4];
2225         u8         reserved_at_55[0x6];
2226         u8         rlky[0x1];
2227         u8         ulp_stateless_offload_mode[0x4];
2228
2229         u8         counter_set_id[0x8];
2230         u8         uar_page[0x18];
2231
2232         u8         reserved_at_80[0x8];
2233         u8         user_index[0x18];
2234
2235         u8         reserved_at_a0[0x3];
2236         u8         log_page_size[0x5];
2237         u8         remote_qpn[0x18];
2238
2239         struct mlx5_ifc_ads_bits primary_address_path;
2240
2241         struct mlx5_ifc_ads_bits secondary_address_path;
2242
2243         u8         log_ack_req_freq[0x4];
2244         u8         reserved_at_384[0x4];
2245         u8         log_sra_max[0x3];
2246         u8         reserved_at_38b[0x2];
2247         u8         retry_count[0x3];
2248         u8         rnr_retry[0x3];
2249         u8         reserved_at_393[0x1];
2250         u8         fre[0x1];
2251         u8         cur_rnr_retry[0x3];
2252         u8         cur_retry_count[0x3];
2253         u8         reserved_at_39b[0x5];
2254
2255         u8         reserved_at_3a0[0x20];
2256
2257         u8         reserved_at_3c0[0x8];
2258         u8         next_send_psn[0x18];
2259
2260         u8         reserved_at_3e0[0x8];
2261         u8         cqn_snd[0x18];
2262
2263         u8         reserved_at_400[0x8];
2264         u8         deth_sqpn[0x18];
2265
2266         u8         reserved_at_420[0x20];
2267
2268         u8         reserved_at_440[0x8];
2269         u8         last_acked_psn[0x18];
2270
2271         u8         reserved_at_460[0x8];
2272         u8         ssn[0x18];
2273
2274         u8         reserved_at_480[0x8];
2275         u8         log_rra_max[0x3];
2276         u8         reserved_at_48b[0x1];
2277         u8         atomic_mode[0x4];
2278         u8         rre[0x1];
2279         u8         rwe[0x1];
2280         u8         rae[0x1];
2281         u8         reserved_at_493[0x1];
2282         u8         page_offset[0x6];
2283         u8         reserved_at_49a[0x3];
2284         u8         cd_slave_receive[0x1];
2285         u8         cd_slave_send[0x1];
2286         u8         cd_master[0x1];
2287
2288         u8         reserved_at_4a0[0x3];
2289         u8         min_rnr_nak[0x5];
2290         u8         next_rcv_psn[0x18];
2291
2292         u8         reserved_at_4c0[0x8];
2293         u8         xrcd[0x18];
2294
2295         u8         reserved_at_4e0[0x8];
2296         u8         cqn_rcv[0x18];
2297
2298         u8         dbr_addr[0x40];
2299
2300         u8         q_key[0x20];
2301
2302         u8         reserved_at_560[0x5];
2303         u8         rq_type[0x3];
2304         u8         srqn_rmpn_xrqn[0x18];
2305
2306         u8         reserved_at_580[0x8];
2307         u8         rmsn[0x18];
2308
2309         u8         hw_sq_wqebb_counter[0x10];
2310         u8         sw_sq_wqebb_counter[0x10];
2311
2312         u8         hw_rq_counter[0x20];
2313
2314         u8         sw_rq_counter[0x20];
2315
2316         u8         reserved_at_600[0x20];
2317
2318         u8         reserved_at_620[0xf];
2319         u8         cgs[0x1];
2320         u8         cs_req[0x8];
2321         u8         cs_res[0x8];
2322
2323         u8         dc_access_key[0x40];
2324
2325         u8         reserved_at_680[0xc0];
2326 };
2327
2328 struct mlx5_ifc_roce_addr_layout_bits {
2329         u8         source_l3_address[16][0x8];
2330
2331         u8         reserved_at_80[0x3];
2332         u8         vlan_valid[0x1];
2333         u8         vlan_id[0xc];
2334         u8         source_mac_47_32[0x10];
2335
2336         u8         source_mac_31_0[0x20];
2337
2338         u8         reserved_at_c0[0x14];
2339         u8         roce_l3_type[0x4];
2340         u8         roce_version[0x8];
2341
2342         u8         reserved_at_e0[0x20];
2343 };
2344
2345 union mlx5_ifc_hca_cap_union_bits {
2346         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2347         struct mlx5_ifc_odp_cap_bits odp_cap;
2348         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2349         struct mlx5_ifc_roce_cap_bits roce_cap;
2350         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2351         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2352         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2353         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2354         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2355         struct mlx5_ifc_qos_cap_bits qos_cap;
2356         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2357         u8         reserved_at_0[0x8000];
2358 };
2359
2360 enum {
2361         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2362         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2363         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2364         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2365         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2366         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2367         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2368         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2369         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2370 };
2371
2372 struct mlx5_ifc_vlan_bits {
2373         u8         ethtype[0x10];
2374         u8         prio[0x3];
2375         u8         cfi[0x1];
2376         u8         vid[0xc];
2377 };
2378
2379 struct mlx5_ifc_flow_context_bits {
2380         struct mlx5_ifc_vlan_bits push_vlan;
2381
2382         u8         group_id[0x20];
2383
2384         u8         reserved_at_40[0x8];
2385         u8         flow_tag[0x18];
2386
2387         u8         reserved_at_60[0x10];
2388         u8         action[0x10];
2389
2390         u8         reserved_at_80[0x8];
2391         u8         destination_list_size[0x18];
2392
2393         u8         reserved_at_a0[0x8];
2394         u8         flow_counter_list_size[0x18];
2395
2396         u8         encap_id[0x20];
2397
2398         u8         modify_header_id[0x20];
2399
2400         u8         reserved_at_100[0x100];
2401
2402         struct mlx5_ifc_fte_match_param_bits match_value;
2403
2404         u8         reserved_at_1200[0x600];
2405
2406         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2407 };
2408
2409 enum {
2410         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2411         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2412 };
2413
2414 struct mlx5_ifc_xrc_srqc_bits {
2415         u8         state[0x4];
2416         u8         log_xrc_srq_size[0x4];
2417         u8         reserved_at_8[0x18];
2418
2419         u8         wq_signature[0x1];
2420         u8         cont_srq[0x1];
2421         u8         reserved_at_22[0x1];
2422         u8         rlky[0x1];
2423         u8         basic_cyclic_rcv_wqe[0x1];
2424         u8         log_rq_stride[0x3];
2425         u8         xrcd[0x18];
2426
2427         u8         page_offset[0x6];
2428         u8         reserved_at_46[0x2];
2429         u8         cqn[0x18];
2430
2431         u8         reserved_at_60[0x20];
2432
2433         u8         user_index_equal_xrc_srqn[0x1];
2434         u8         reserved_at_81[0x1];
2435         u8         log_page_size[0x6];
2436         u8         user_index[0x18];
2437
2438         u8         reserved_at_a0[0x20];
2439
2440         u8         reserved_at_c0[0x8];
2441         u8         pd[0x18];
2442
2443         u8         lwm[0x10];
2444         u8         wqe_cnt[0x10];
2445
2446         u8         reserved_at_100[0x40];
2447
2448         u8         db_record_addr_h[0x20];
2449
2450         u8         db_record_addr_l[0x1e];
2451         u8         reserved_at_17e[0x2];
2452
2453         u8         reserved_at_180[0x80];
2454 };
2455
2456 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2457         u8         counter_error_queues[0x20];
2458
2459         u8         total_error_queues[0x20];
2460
2461         u8         send_queue_priority_update_flow[0x20];
2462
2463         u8         reserved_at_60[0x20];
2464
2465         u8         nic_receive_steering_discard[0x40];
2466
2467         u8         receive_discard_vport_down[0x40];
2468
2469         u8         transmit_discard_vport_down[0x40];
2470
2471         u8         reserved_at_140[0xec0];
2472 };
2473
2474 struct mlx5_ifc_traffic_counter_bits {
2475         u8         packets[0x40];
2476
2477         u8         octets[0x40];
2478 };
2479
2480 struct mlx5_ifc_tisc_bits {
2481         u8         strict_lag_tx_port_affinity[0x1];
2482         u8         reserved_at_1[0x3];
2483         u8         lag_tx_port_affinity[0x04];
2484
2485         u8         reserved_at_8[0x4];
2486         u8         prio[0x4];
2487         u8         reserved_at_10[0x10];
2488
2489         u8         reserved_at_20[0x100];
2490
2491         u8         reserved_at_120[0x8];
2492         u8         transport_domain[0x18];
2493
2494         u8         reserved_at_140[0x8];
2495         u8         underlay_qpn[0x18];
2496         u8         reserved_at_160[0x3a0];
2497 };
2498
2499 enum {
2500         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2501         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2502 };
2503
2504 enum {
2505         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2506         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2507 };
2508
2509 enum {
2510         MLX5_RX_HASH_FN_NONE           = 0x0,
2511         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2512         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2513 };
2514
2515 enum {
2516         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2517         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2518 };
2519
2520 struct mlx5_ifc_tirc_bits {
2521         u8         reserved_at_0[0x20];
2522
2523         u8         disp_type[0x4];
2524         u8         reserved_at_24[0x1c];
2525
2526         u8         reserved_at_40[0x40];
2527
2528         u8         reserved_at_80[0x4];
2529         u8         lro_timeout_period_usecs[0x10];
2530         u8         lro_enable_mask[0x4];
2531         u8         lro_max_ip_payload_size[0x8];
2532
2533         u8         reserved_at_a0[0x40];
2534
2535         u8         reserved_at_e0[0x8];
2536         u8         inline_rqn[0x18];
2537
2538         u8         rx_hash_symmetric[0x1];
2539         u8         reserved_at_101[0x1];
2540         u8         tunneled_offload_en[0x1];
2541         u8         reserved_at_103[0x5];
2542         u8         indirect_table[0x18];
2543
2544         u8         rx_hash_fn[0x4];
2545         u8         reserved_at_124[0x2];
2546         u8         self_lb_block[0x2];
2547         u8         transport_domain[0x18];
2548
2549         u8         rx_hash_toeplitz_key[10][0x20];
2550
2551         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2552
2553         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2554
2555         u8         reserved_at_2c0[0x4c0];
2556 };
2557
2558 enum {
2559         MLX5_SRQC_STATE_GOOD   = 0x0,
2560         MLX5_SRQC_STATE_ERROR  = 0x1,
2561 };
2562
2563 struct mlx5_ifc_srqc_bits {
2564         u8         state[0x4];
2565         u8         log_srq_size[0x4];
2566         u8         reserved_at_8[0x18];
2567
2568         u8         wq_signature[0x1];
2569         u8         cont_srq[0x1];
2570         u8         reserved_at_22[0x1];
2571         u8         rlky[0x1];
2572         u8         reserved_at_24[0x1];
2573         u8         log_rq_stride[0x3];
2574         u8         xrcd[0x18];
2575
2576         u8         page_offset[0x6];
2577         u8         reserved_at_46[0x2];
2578         u8         cqn[0x18];
2579
2580         u8         reserved_at_60[0x20];
2581
2582         u8         reserved_at_80[0x2];
2583         u8         log_page_size[0x6];
2584         u8         reserved_at_88[0x18];
2585
2586         u8         reserved_at_a0[0x20];
2587
2588         u8         reserved_at_c0[0x8];
2589         u8         pd[0x18];
2590
2591         u8         lwm[0x10];
2592         u8         wqe_cnt[0x10];
2593
2594         u8         reserved_at_100[0x40];
2595
2596         u8         dbr_addr[0x40];
2597
2598         u8         reserved_at_180[0x80];
2599 };
2600
2601 enum {
2602         MLX5_SQC_STATE_RST  = 0x0,
2603         MLX5_SQC_STATE_RDY  = 0x1,
2604         MLX5_SQC_STATE_ERR  = 0x3,
2605 };
2606
2607 struct mlx5_ifc_sqc_bits {
2608         u8         rlky[0x1];
2609         u8         cd_master[0x1];
2610         u8         fre[0x1];
2611         u8         flush_in_error_en[0x1];
2612         u8         allow_multi_pkt_send_wqe[0x1];
2613         u8         min_wqe_inline_mode[0x3];
2614         u8         state[0x4];
2615         u8         reg_umr[0x1];
2616         u8         allow_swp[0x1];
2617         u8         hairpin[0x1];
2618         u8         reserved_at_f[0x11];
2619
2620         u8         reserved_at_20[0x8];
2621         u8         user_index[0x18];
2622
2623         u8         reserved_at_40[0x8];
2624         u8         cqn[0x18];
2625
2626         u8         reserved_at_60[0x8];
2627         u8         hairpin_peer_rq[0x18];
2628
2629         u8         reserved_at_80[0x10];
2630         u8         hairpin_peer_vhca[0x10];
2631
2632         u8         reserved_at_a0[0x50];
2633
2634         u8         packet_pacing_rate_limit_index[0x10];
2635         u8         tis_lst_sz[0x10];
2636         u8         reserved_at_110[0x10];
2637
2638         u8         reserved_at_120[0x40];
2639
2640         u8         reserved_at_160[0x8];
2641         u8         tis_num_0[0x18];
2642
2643         struct mlx5_ifc_wq_bits wq;
2644 };
2645
2646 enum {
2647         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2648         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2649         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2650         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2651 };
2652
2653 struct mlx5_ifc_scheduling_context_bits {
2654         u8         element_type[0x8];
2655         u8         reserved_at_8[0x18];
2656
2657         u8         element_attributes[0x20];
2658
2659         u8         parent_element_id[0x20];
2660
2661         u8         reserved_at_60[0x40];
2662
2663         u8         bw_share[0x20];
2664
2665         u8         max_average_bw[0x20];
2666
2667         u8         reserved_at_e0[0x120];
2668 };
2669
2670 struct mlx5_ifc_rqtc_bits {
2671         u8         reserved_at_0[0xa0];
2672
2673         u8         reserved_at_a0[0x10];
2674         u8         rqt_max_size[0x10];
2675
2676         u8         reserved_at_c0[0x10];
2677         u8         rqt_actual_size[0x10];
2678
2679         u8         reserved_at_e0[0x6a0];
2680
2681         struct mlx5_ifc_rq_num_bits rq_num[0];
2682 };
2683
2684 enum {
2685         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2686         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2687 };
2688
2689 enum {
2690         MLX5_RQC_STATE_RST  = 0x0,
2691         MLX5_RQC_STATE_RDY  = 0x1,
2692         MLX5_RQC_STATE_ERR  = 0x3,
2693 };
2694
2695 struct mlx5_ifc_rqc_bits {
2696         u8         rlky[0x1];
2697         u8         delay_drop_en[0x1];
2698         u8         scatter_fcs[0x1];
2699         u8         vsd[0x1];
2700         u8         mem_rq_type[0x4];
2701         u8         state[0x4];
2702         u8         reserved_at_c[0x1];
2703         u8         flush_in_error_en[0x1];
2704         u8         hairpin[0x1];
2705         u8         reserved_at_f[0x11];
2706
2707         u8         reserved_at_20[0x8];
2708         u8         user_index[0x18];
2709
2710         u8         reserved_at_40[0x8];
2711         u8         cqn[0x18];
2712
2713         u8         counter_set_id[0x8];
2714         u8         reserved_at_68[0x18];
2715
2716         u8         reserved_at_80[0x8];
2717         u8         rmpn[0x18];
2718
2719         u8         reserved_at_a0[0x8];
2720         u8         hairpin_peer_sq[0x18];
2721
2722         u8         reserved_at_c0[0x10];
2723         u8         hairpin_peer_vhca[0x10];
2724
2725         u8         reserved_at_e0[0xa0];
2726
2727         struct mlx5_ifc_wq_bits wq;
2728 };
2729
2730 enum {
2731         MLX5_RMPC_STATE_RDY  = 0x1,
2732         MLX5_RMPC_STATE_ERR  = 0x3,
2733 };
2734
2735 struct mlx5_ifc_rmpc_bits {
2736         u8         reserved_at_0[0x8];
2737         u8         state[0x4];
2738         u8         reserved_at_c[0x14];
2739
2740         u8         basic_cyclic_rcv_wqe[0x1];
2741         u8         reserved_at_21[0x1f];
2742
2743         u8         reserved_at_40[0x140];
2744
2745         struct mlx5_ifc_wq_bits wq;
2746 };
2747
2748 struct mlx5_ifc_nic_vport_context_bits {
2749         u8         reserved_at_0[0x5];
2750         u8         min_wqe_inline_mode[0x3];
2751         u8         reserved_at_8[0x15];
2752         u8         disable_mc_local_lb[0x1];
2753         u8         disable_uc_local_lb[0x1];
2754         u8         roce_en[0x1];
2755
2756         u8         arm_change_event[0x1];
2757         u8         reserved_at_21[0x1a];
2758         u8         event_on_mtu[0x1];
2759         u8         event_on_promisc_change[0x1];
2760         u8         event_on_vlan_change[0x1];
2761         u8         event_on_mc_address_change[0x1];
2762         u8         event_on_uc_address_change[0x1];
2763
2764         u8         reserved_at_40[0xc];
2765
2766         u8         affiliation_criteria[0x4];
2767         u8         affiliated_vhca_id[0x10];
2768
2769         u8         reserved_at_60[0xd0];
2770
2771         u8         mtu[0x10];
2772
2773         u8         system_image_guid[0x40];
2774         u8         port_guid[0x40];
2775         u8         node_guid[0x40];
2776
2777         u8         reserved_at_200[0x140];
2778         u8         qkey_violation_counter[0x10];
2779         u8         reserved_at_350[0x430];
2780
2781         u8         promisc_uc[0x1];
2782         u8         promisc_mc[0x1];
2783         u8         promisc_all[0x1];
2784         u8         reserved_at_783[0x2];
2785         u8         allowed_list_type[0x3];
2786         u8         reserved_at_788[0xc];
2787         u8         allowed_list_size[0xc];
2788
2789         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2790
2791         u8         reserved_at_7e0[0x20];
2792
2793         u8         current_uc_mac_address[0][0x40];
2794 };
2795
2796 enum {
2797         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2798         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2799         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2800         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2801         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2802 };
2803
2804 struct mlx5_ifc_mkc_bits {
2805         u8         reserved_at_0[0x1];
2806         u8         free[0x1];
2807         u8         reserved_at_2[0x1];
2808         u8         access_mode_4_2[0x3];
2809         u8         reserved_at_6[0x7];
2810         u8         relaxed_ordering_write[0x1];
2811         u8         reserved_at_e[0x1];
2812         u8         small_fence_on_rdma_read_response[0x1];
2813         u8         umr_en[0x1];
2814         u8         a[0x1];
2815         u8         rw[0x1];
2816         u8         rr[0x1];
2817         u8         lw[0x1];
2818         u8         lr[0x1];
2819         u8         access_mode_1_0[0x2];
2820         u8         reserved_at_18[0x8];
2821
2822         u8         qpn[0x18];
2823         u8         mkey_7_0[0x8];
2824
2825         u8         reserved_at_40[0x20];
2826
2827         u8         length64[0x1];
2828         u8         bsf_en[0x1];
2829         u8         sync_umr[0x1];
2830         u8         reserved_at_63[0x2];
2831         u8         expected_sigerr_count[0x1];
2832         u8         reserved_at_66[0x1];
2833         u8         en_rinval[0x1];
2834         u8         pd[0x18];
2835
2836         u8         start_addr[0x40];
2837
2838         u8         len[0x40];
2839
2840         u8         bsf_octword_size[0x20];
2841
2842         u8         reserved_at_120[0x80];
2843
2844         u8         translations_octword_size[0x20];
2845
2846         u8         reserved_at_1c0[0x1b];
2847         u8         log_page_size[0x5];
2848
2849         u8         reserved_at_1e0[0x20];
2850 };
2851
2852 struct mlx5_ifc_pkey_bits {
2853         u8         reserved_at_0[0x10];
2854         u8         pkey[0x10];
2855 };
2856
2857 struct mlx5_ifc_array128_auto_bits {
2858         u8         array128_auto[16][0x8];
2859 };
2860
2861 struct mlx5_ifc_hca_vport_context_bits {
2862         u8         field_select[0x20];
2863
2864         u8         reserved_at_20[0xe0];
2865
2866         u8         sm_virt_aware[0x1];
2867         u8         has_smi[0x1];
2868         u8         has_raw[0x1];
2869         u8         grh_required[0x1];
2870         u8         reserved_at_104[0xc];
2871         u8         port_physical_state[0x4];
2872         u8         vport_state_policy[0x4];
2873         u8         port_state[0x4];
2874         u8         vport_state[0x4];
2875
2876         u8         reserved_at_120[0x20];
2877
2878         u8         system_image_guid[0x40];
2879
2880         u8         port_guid[0x40];
2881
2882         u8         node_guid[0x40];
2883
2884         u8         cap_mask1[0x20];
2885
2886         u8         cap_mask1_field_select[0x20];
2887
2888         u8         cap_mask2[0x20];
2889
2890         u8         cap_mask2_field_select[0x20];
2891
2892         u8         reserved_at_280[0x80];
2893
2894         u8         lid[0x10];
2895         u8         reserved_at_310[0x4];
2896         u8         init_type_reply[0x4];
2897         u8         lmc[0x3];
2898         u8         subnet_timeout[0x5];
2899
2900         u8         sm_lid[0x10];
2901         u8         sm_sl[0x4];
2902         u8         reserved_at_334[0xc];
2903
2904         u8         qkey_violation_counter[0x10];
2905         u8         pkey_violation_counter[0x10];
2906
2907         u8         reserved_at_360[0xca0];
2908 };
2909
2910 struct mlx5_ifc_esw_vport_context_bits {
2911         u8         reserved_at_0[0x3];
2912         u8         vport_svlan_strip[0x1];
2913         u8         vport_cvlan_strip[0x1];
2914         u8         vport_svlan_insert[0x1];
2915         u8         vport_cvlan_insert[0x2];
2916         u8         reserved_at_8[0x18];
2917
2918         u8         reserved_at_20[0x20];
2919
2920         u8         svlan_cfi[0x1];
2921         u8         svlan_pcp[0x3];
2922         u8         svlan_id[0xc];
2923         u8         cvlan_cfi[0x1];
2924         u8         cvlan_pcp[0x3];
2925         u8         cvlan_id[0xc];
2926
2927         u8         reserved_at_60[0x7a0];
2928 };
2929
2930 enum {
2931         MLX5_EQC_STATUS_OK                = 0x0,
2932         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2933 };
2934
2935 enum {
2936         MLX5_EQC_ST_ARMED  = 0x9,
2937         MLX5_EQC_ST_FIRED  = 0xa,
2938 };
2939
2940 struct mlx5_ifc_eqc_bits {
2941         u8         status[0x4];
2942         u8         reserved_at_4[0x9];
2943         u8         ec[0x1];
2944         u8         oi[0x1];
2945         u8         reserved_at_f[0x5];
2946         u8         st[0x4];
2947         u8         reserved_at_18[0x8];
2948
2949         u8         reserved_at_20[0x20];
2950
2951         u8         reserved_at_40[0x14];
2952         u8         page_offset[0x6];
2953         u8         reserved_at_5a[0x6];
2954
2955         u8         reserved_at_60[0x3];
2956         u8         log_eq_size[0x5];
2957         u8         uar_page[0x18];
2958
2959         u8         reserved_at_80[0x20];
2960
2961         u8         reserved_at_a0[0x18];
2962         u8         intr[0x8];
2963
2964         u8         reserved_at_c0[0x3];
2965         u8         log_page_size[0x5];
2966         u8         reserved_at_c8[0x18];
2967
2968         u8         reserved_at_e0[0x60];
2969
2970         u8         reserved_at_140[0x8];
2971         u8         consumer_counter[0x18];
2972
2973         u8         reserved_at_160[0x8];
2974         u8         producer_counter[0x18];
2975
2976         u8         reserved_at_180[0x80];
2977 };
2978
2979 enum {
2980         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2981         MLX5_DCTC_STATE_DRAINING  = 0x1,
2982         MLX5_DCTC_STATE_DRAINED   = 0x2,
2983 };
2984
2985 enum {
2986         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2987         MLX5_DCTC_CS_RES_NA         = 0x1,
2988         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2989 };
2990
2991 enum {
2992         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2993         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2994         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2995         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2996         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2997 };
2998
2999 struct mlx5_ifc_dctc_bits {
3000         u8         reserved_at_0[0x4];
3001         u8         state[0x4];
3002         u8         reserved_at_8[0x18];
3003
3004         u8         reserved_at_20[0x8];
3005         u8         user_index[0x18];
3006
3007         u8         reserved_at_40[0x8];
3008         u8         cqn[0x18];
3009
3010         u8         counter_set_id[0x8];
3011         u8         atomic_mode[0x4];
3012         u8         rre[0x1];
3013         u8         rwe[0x1];
3014         u8         rae[0x1];
3015         u8         atomic_like_write_en[0x1];
3016         u8         latency_sensitive[0x1];
3017         u8         rlky[0x1];
3018         u8         free_ar[0x1];
3019         u8         reserved_at_73[0xd];
3020
3021         u8         reserved_at_80[0x8];
3022         u8         cs_res[0x8];
3023         u8         reserved_at_90[0x3];
3024         u8         min_rnr_nak[0x5];
3025         u8         reserved_at_98[0x8];
3026
3027         u8         reserved_at_a0[0x8];
3028         u8         srqn_xrqn[0x18];
3029
3030         u8         reserved_at_c0[0x8];
3031         u8         pd[0x18];
3032
3033         u8         tclass[0x8];
3034         u8         reserved_at_e8[0x4];
3035         u8         flow_label[0x14];
3036
3037         u8         dc_access_key[0x40];
3038
3039         u8         reserved_at_140[0x5];
3040         u8         mtu[0x3];
3041         u8         port[0x8];
3042         u8         pkey_index[0x10];
3043
3044         u8         reserved_at_160[0x8];
3045         u8         my_addr_index[0x8];
3046         u8         reserved_at_170[0x8];
3047         u8         hop_limit[0x8];
3048
3049         u8         dc_access_key_violation_count[0x20];
3050
3051         u8         reserved_at_1a0[0x14];
3052         u8         dei_cfi[0x1];
3053         u8         eth_prio[0x3];
3054         u8         ecn[0x2];
3055         u8         dscp[0x6];
3056
3057         u8         reserved_at_1c0[0x40];
3058 };
3059
3060 enum {
3061         MLX5_CQC_STATUS_OK             = 0x0,
3062         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3063         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3064 };
3065
3066 enum {
3067         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3068         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3069 };
3070
3071 enum {
3072         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3073         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3074         MLX5_CQC_ST_FIRED                                 = 0xa,
3075 };
3076
3077 enum {
3078         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3079         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3080         MLX5_CQ_PERIOD_NUM_MODES
3081 };
3082
3083 struct mlx5_ifc_cqc_bits {
3084         u8         status[0x4];
3085         u8         reserved_at_4[0x4];
3086         u8         cqe_sz[0x3];
3087         u8         cc[0x1];
3088         u8         reserved_at_c[0x1];
3089         u8         scqe_break_moderation_en[0x1];
3090         u8         oi[0x1];
3091         u8         cq_period_mode[0x2];
3092         u8         cqe_comp_en[0x1];
3093         u8         mini_cqe_res_format[0x2];
3094         u8         st[0x4];
3095         u8         reserved_at_18[0x8];
3096
3097         u8         reserved_at_20[0x20];
3098
3099         u8         reserved_at_40[0x14];
3100         u8         page_offset[0x6];
3101         u8         reserved_at_5a[0x6];
3102
3103         u8         reserved_at_60[0x3];
3104         u8         log_cq_size[0x5];
3105         u8         uar_page[0x18];
3106
3107         u8         reserved_at_80[0x4];
3108         u8         cq_period[0xc];
3109         u8         cq_max_count[0x10];
3110
3111         u8         reserved_at_a0[0x18];
3112         u8         c_eqn[0x8];
3113
3114         u8         reserved_at_c0[0x3];
3115         u8         log_page_size[0x5];
3116         u8         reserved_at_c8[0x18];
3117
3118         u8         reserved_at_e0[0x20];
3119
3120         u8         reserved_at_100[0x8];
3121         u8         last_notified_index[0x18];
3122
3123         u8         reserved_at_120[0x8];
3124         u8         last_solicit_index[0x18];
3125
3126         u8         reserved_at_140[0x8];
3127         u8         consumer_counter[0x18];
3128
3129         u8         reserved_at_160[0x8];
3130         u8         producer_counter[0x18];
3131
3132         u8         reserved_at_180[0x40];
3133
3134         u8         dbr_addr[0x40];
3135 };
3136
3137 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3138         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3139         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3140         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3141         u8         reserved_at_0[0x800];
3142 };
3143
3144 struct mlx5_ifc_query_adapter_param_block_bits {
3145         u8         reserved_at_0[0xc0];
3146
3147         u8         reserved_at_c0[0x8];
3148         u8         ieee_vendor_id[0x18];
3149
3150         u8         reserved_at_e0[0x10];
3151         u8         vsd_vendor_id[0x10];
3152
3153         u8         vsd[208][0x8];
3154
3155         u8         vsd_contd_psid[16][0x8];
3156 };
3157
3158 enum {
3159         MLX5_XRQC_STATE_GOOD   = 0x0,
3160         MLX5_XRQC_STATE_ERROR  = 0x1,
3161 };
3162
3163 enum {
3164         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3165         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3166 };
3167
3168 enum {
3169         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3170 };
3171
3172 struct mlx5_ifc_tag_matching_topology_context_bits {
3173         u8         log_matching_list_sz[0x4];
3174         u8         reserved_at_4[0xc];
3175         u8         append_next_index[0x10];
3176
3177         u8         sw_phase_cnt[0x10];
3178         u8         hw_phase_cnt[0x10];
3179
3180         u8         reserved_at_40[0x40];
3181 };
3182
3183 struct mlx5_ifc_xrqc_bits {
3184         u8         state[0x4];
3185         u8         rlkey[0x1];
3186         u8         reserved_at_5[0xf];
3187         u8         topology[0x4];
3188         u8         reserved_at_18[0x4];
3189         u8         offload[0x4];
3190
3191         u8         reserved_at_20[0x8];
3192         u8         user_index[0x18];
3193
3194         u8         reserved_at_40[0x8];
3195         u8         cqn[0x18];
3196
3197         u8         reserved_at_60[0xa0];
3198
3199         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3200
3201         u8         reserved_at_180[0x280];
3202
3203         struct mlx5_ifc_wq_bits wq;
3204 };
3205
3206 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3207         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3208         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3209         u8         reserved_at_0[0x20];
3210 };
3211
3212 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3213         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3214         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3215         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3216         u8         reserved_at_0[0x20];
3217 };
3218
3219 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3220         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3221         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3222         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3223         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3224         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3225         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3226         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3227         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3228         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3229         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3230         u8         reserved_at_0[0x7c0];
3231 };
3232
3233 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3234         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3235         u8         reserved_at_0[0x7c0];
3236 };
3237
3238 union mlx5_ifc_event_auto_bits {
3239         struct mlx5_ifc_comp_event_bits comp_event;
3240         struct mlx5_ifc_dct_events_bits dct_events;
3241         struct mlx5_ifc_qp_events_bits qp_events;
3242         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3243         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3244         struct mlx5_ifc_cq_error_bits cq_error;
3245         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3246         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3247         struct mlx5_ifc_gpio_event_bits gpio_event;
3248         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3249         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3250         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3251         u8         reserved_at_0[0xe0];
3252 };
3253
3254 struct mlx5_ifc_health_buffer_bits {
3255         u8         reserved_at_0[0x100];
3256
3257         u8         assert_existptr[0x20];
3258
3259         u8         assert_callra[0x20];
3260
3261         u8         reserved_at_140[0x40];
3262
3263         u8         fw_version[0x20];
3264
3265         u8         hw_id[0x20];
3266
3267         u8         reserved_at_1c0[0x20];
3268
3269         u8         irisc_index[0x8];
3270         u8         synd[0x8];
3271         u8         ext_synd[0x10];
3272 };
3273
3274 struct mlx5_ifc_register_loopback_control_bits {
3275         u8         no_lb[0x1];
3276         u8         reserved_at_1[0x7];
3277         u8         port[0x8];
3278         u8         reserved_at_10[0x10];
3279
3280         u8         reserved_at_20[0x60];
3281 };
3282
3283 struct mlx5_ifc_vport_tc_element_bits {
3284         u8         traffic_class[0x4];
3285         u8         reserved_at_4[0xc];
3286         u8         vport_number[0x10];
3287 };
3288
3289 struct mlx5_ifc_vport_element_bits {
3290         u8         reserved_at_0[0x10];
3291         u8         vport_number[0x10];
3292 };
3293
3294 enum {
3295         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3296         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3297         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3298 };
3299
3300 struct mlx5_ifc_tsar_element_bits {
3301         u8         reserved_at_0[0x8];
3302         u8         tsar_type[0x8];
3303         u8         reserved_at_10[0x10];
3304 };
3305
3306 enum {
3307         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3308         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3309 };
3310
3311 struct mlx5_ifc_teardown_hca_out_bits {
3312         u8         status[0x8];
3313         u8         reserved_at_8[0x18];
3314
3315         u8         syndrome[0x20];
3316
3317         u8         reserved_at_40[0x3f];
3318
3319         u8         force_state[0x1];
3320 };
3321
3322 enum {
3323         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3324         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3325 };
3326
3327 struct mlx5_ifc_teardown_hca_in_bits {
3328         u8         opcode[0x10];
3329         u8         reserved_at_10[0x10];
3330
3331         u8         reserved_at_20[0x10];
3332         u8         op_mod[0x10];
3333
3334         u8         reserved_at_40[0x10];
3335         u8         profile[0x10];
3336
3337         u8         reserved_at_60[0x20];
3338 };
3339
3340 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3341         u8         status[0x8];
3342         u8         reserved_at_8[0x18];
3343
3344         u8         syndrome[0x20];
3345
3346         u8         reserved_at_40[0x40];
3347 };
3348
3349 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3350         u8         opcode[0x10];
3351         u8         reserved_at_10[0x10];
3352
3353         u8         reserved_at_20[0x10];
3354         u8         op_mod[0x10];
3355
3356         u8         reserved_at_40[0x8];
3357         u8         qpn[0x18];
3358
3359         u8         reserved_at_60[0x20];
3360
3361         u8         opt_param_mask[0x20];
3362
3363         u8         reserved_at_a0[0x20];
3364
3365         struct mlx5_ifc_qpc_bits qpc;
3366
3367         u8         reserved_at_800[0x80];
3368 };
3369
3370 struct mlx5_ifc_sqd2rts_qp_out_bits {
3371         u8         status[0x8];
3372         u8         reserved_at_8[0x18];
3373
3374         u8         syndrome[0x20];
3375
3376         u8         reserved_at_40[0x40];
3377 };
3378
3379 struct mlx5_ifc_sqd2rts_qp_in_bits {
3380         u8         opcode[0x10];
3381         u8         reserved_at_10[0x10];
3382
3383         u8         reserved_at_20[0x10];
3384         u8         op_mod[0x10];
3385
3386         u8         reserved_at_40[0x8];
3387         u8         qpn[0x18];
3388
3389         u8         reserved_at_60[0x20];
3390
3391         u8         opt_param_mask[0x20];
3392
3393         u8         reserved_at_a0[0x20];
3394
3395         struct mlx5_ifc_qpc_bits qpc;
3396
3397         u8         reserved_at_800[0x80];
3398 };
3399
3400 struct mlx5_ifc_set_roce_address_out_bits {
3401         u8         status[0x8];
3402         u8         reserved_at_8[0x18];
3403
3404         u8         syndrome[0x20];
3405
3406         u8         reserved_at_40[0x40];
3407 };
3408
3409 struct mlx5_ifc_set_roce_address_in_bits {
3410         u8         opcode[0x10];
3411         u8         reserved_at_10[0x10];
3412
3413         u8         reserved_at_20[0x10];
3414         u8         op_mod[0x10];
3415
3416         u8         roce_address_index[0x10];
3417         u8         reserved_at_50[0xc];
3418         u8         vhca_port_num[0x4];
3419
3420         u8         reserved_at_60[0x20];
3421
3422         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3423 };
3424
3425 struct mlx5_ifc_set_mad_demux_out_bits {
3426         u8         status[0x8];
3427         u8         reserved_at_8[0x18];
3428
3429         u8         syndrome[0x20];
3430
3431         u8         reserved_at_40[0x40];
3432 };
3433
3434 enum {
3435         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3436         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3437 };
3438
3439 struct mlx5_ifc_set_mad_demux_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_at_10[0x10];
3442
3443         u8         reserved_at_20[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         reserved_at_40[0x20];
3447
3448         u8         reserved_at_60[0x6];
3449         u8         demux_mode[0x2];
3450         u8         reserved_at_68[0x18];
3451 };
3452
3453 struct mlx5_ifc_set_l2_table_entry_out_bits {
3454         u8         status[0x8];
3455         u8         reserved_at_8[0x18];
3456
3457         u8         syndrome[0x20];
3458
3459         u8         reserved_at_40[0x40];
3460 };
3461
3462 struct mlx5_ifc_set_l2_table_entry_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_at_40[0x60];
3470
3471         u8         reserved_at_a0[0x8];
3472         u8         table_index[0x18];
3473
3474         u8         reserved_at_c0[0x20];
3475
3476         u8         reserved_at_e0[0x13];
3477         u8         vlan_valid[0x1];
3478         u8         vlan[0xc];
3479
3480         struct mlx5_ifc_mac_address_layout_bits mac_address;
3481
3482         u8         reserved_at_140[0xc0];
3483 };
3484
3485 struct mlx5_ifc_set_issi_out_bits {
3486         u8         status[0x8];
3487         u8         reserved_at_8[0x18];
3488
3489         u8         syndrome[0x20];
3490
3491         u8         reserved_at_40[0x40];
3492 };
3493
3494 struct mlx5_ifc_set_issi_in_bits {
3495         u8         opcode[0x10];
3496         u8         reserved_at_10[0x10];
3497
3498         u8         reserved_at_20[0x10];
3499         u8         op_mod[0x10];
3500
3501         u8         reserved_at_40[0x10];
3502         u8         current_issi[0x10];
3503
3504         u8         reserved_at_60[0x20];
3505 };
3506
3507 struct mlx5_ifc_set_hca_cap_out_bits {
3508         u8         status[0x8];
3509         u8         reserved_at_8[0x18];
3510
3511         u8         syndrome[0x20];
3512
3513         u8         reserved_at_40[0x40];
3514 };
3515
3516 struct mlx5_ifc_set_hca_cap_in_bits {
3517         u8         opcode[0x10];
3518         u8         reserved_at_10[0x10];
3519
3520         u8         reserved_at_20[0x10];
3521         u8         op_mod[0x10];
3522
3523         u8         reserved_at_40[0x40];
3524
3525         union mlx5_ifc_hca_cap_union_bits capability;
3526 };
3527
3528 enum {
3529         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3530         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3531         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3532         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3533 };
3534
3535 struct mlx5_ifc_set_fte_out_bits {
3536         u8         status[0x8];
3537         u8         reserved_at_8[0x18];
3538
3539         u8         syndrome[0x20];
3540
3541         u8         reserved_at_40[0x40];
3542 };
3543
3544 struct mlx5_ifc_set_fte_in_bits {
3545         u8         opcode[0x10];
3546         u8         reserved_at_10[0x10];
3547
3548         u8         reserved_at_20[0x10];
3549         u8         op_mod[0x10];
3550
3551         u8         other_vport[0x1];
3552         u8         reserved_at_41[0xf];
3553         u8         vport_number[0x10];
3554
3555         u8         reserved_at_60[0x20];
3556
3557         u8         table_type[0x8];
3558         u8         reserved_at_88[0x18];
3559
3560         u8         reserved_at_a0[0x8];
3561         u8         table_id[0x18];
3562
3563         u8         reserved_at_c0[0x18];
3564         u8         modify_enable_mask[0x8];
3565
3566         u8         reserved_at_e0[0x20];
3567
3568         u8         flow_index[0x20];
3569
3570         u8         reserved_at_120[0xe0];
3571
3572         struct mlx5_ifc_flow_context_bits flow_context;
3573 };
3574
3575 struct mlx5_ifc_rts2rts_qp_out_bits {
3576         u8         status[0x8];
3577         u8         reserved_at_8[0x18];
3578
3579         u8         syndrome[0x20];
3580
3581         u8         reserved_at_40[0x40];
3582 };
3583
3584 struct mlx5_ifc_rts2rts_qp_in_bits {
3585         u8         opcode[0x10];
3586         u8         reserved_at_10[0x10];
3587
3588         u8         reserved_at_20[0x10];
3589         u8         op_mod[0x10];
3590
3591         u8         reserved_at_40[0x8];
3592         u8         qpn[0x18];
3593
3594         u8         reserved_at_60[0x20];
3595
3596         u8         opt_param_mask[0x20];
3597
3598         u8         reserved_at_a0[0x20];
3599
3600         struct mlx5_ifc_qpc_bits qpc;
3601
3602         u8         reserved_at_800[0x80];
3603 };
3604
3605 struct mlx5_ifc_rtr2rts_qp_out_bits {
3606         u8         status[0x8];
3607         u8         reserved_at_8[0x18];
3608
3609         u8         syndrome[0x20];
3610
3611         u8         reserved_at_40[0x40];
3612 };
3613
3614 struct mlx5_ifc_rtr2rts_qp_in_bits {
3615         u8         opcode[0x10];
3616         u8         reserved_at_10[0x10];
3617
3618         u8         reserved_at_20[0x10];
3619         u8         op_mod[0x10];
3620
3621         u8         reserved_at_40[0x8];
3622         u8         qpn[0x18];
3623
3624         u8         reserved_at_60[0x20];
3625
3626         u8         opt_param_mask[0x20];
3627
3628         u8         reserved_at_a0[0x20];
3629
3630         struct mlx5_ifc_qpc_bits qpc;
3631
3632         u8         reserved_at_800[0x80];
3633 };
3634
3635 struct mlx5_ifc_rst2init_qp_out_bits {
3636         u8         status[0x8];
3637         u8         reserved_at_8[0x18];
3638
3639         u8         syndrome[0x20];
3640
3641         u8         reserved_at_40[0x40];
3642 };
3643
3644 struct mlx5_ifc_rst2init_qp_in_bits {
3645         u8         opcode[0x10];
3646         u8         reserved_at_10[0x10];
3647
3648         u8         reserved_at_20[0x10];
3649         u8         op_mod[0x10];
3650
3651         u8         reserved_at_40[0x8];
3652         u8         qpn[0x18];
3653
3654         u8         reserved_at_60[0x20];
3655
3656         u8         opt_param_mask[0x20];
3657
3658         u8         reserved_at_a0[0x20];
3659
3660         struct mlx5_ifc_qpc_bits qpc;
3661
3662         u8         reserved_at_800[0x80];
3663 };
3664
3665 struct mlx5_ifc_query_xrq_out_bits {
3666         u8         status[0x8];
3667         u8         reserved_at_8[0x18];
3668
3669         u8         syndrome[0x20];
3670
3671         u8         reserved_at_40[0x40];
3672
3673         struct mlx5_ifc_xrqc_bits xrq_context;
3674 };
3675
3676 struct mlx5_ifc_query_xrq_in_bits {
3677         u8         opcode[0x10];
3678         u8         reserved_at_10[0x10];
3679
3680         u8         reserved_at_20[0x10];
3681         u8         op_mod[0x10];
3682
3683         u8         reserved_at_40[0x8];
3684         u8         xrqn[0x18];
3685
3686         u8         reserved_at_60[0x20];
3687 };
3688
3689 struct mlx5_ifc_query_xrc_srq_out_bits {
3690         u8         status[0x8];
3691         u8         reserved_at_8[0x18];
3692
3693         u8         syndrome[0x20];
3694
3695         u8         reserved_at_40[0x40];
3696
3697         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3698
3699         u8         reserved_at_280[0x600];
3700
3701         u8         pas[0][0x40];
3702 };
3703
3704 struct mlx5_ifc_query_xrc_srq_in_bits {
3705         u8         opcode[0x10];
3706         u8         reserved_at_10[0x10];
3707
3708         u8         reserved_at_20[0x10];
3709         u8         op_mod[0x10];
3710
3711         u8         reserved_at_40[0x8];
3712         u8         xrc_srqn[0x18];
3713
3714         u8         reserved_at_60[0x20];
3715 };
3716
3717 enum {
3718         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3719         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3720 };
3721
3722 struct mlx5_ifc_query_vport_state_out_bits {
3723         u8         status[0x8];
3724         u8         reserved_at_8[0x18];
3725
3726         u8         syndrome[0x20];
3727
3728         u8         reserved_at_40[0x20];
3729
3730         u8         reserved_at_60[0x18];
3731         u8         admin_state[0x4];
3732         u8         state[0x4];
3733 };
3734
3735 enum {
3736         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3737         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3738 };
3739
3740 struct mlx5_ifc_query_vport_state_in_bits {
3741         u8         opcode[0x10];
3742         u8         reserved_at_10[0x10];
3743
3744         u8         reserved_at_20[0x10];
3745         u8         op_mod[0x10];
3746
3747         u8         other_vport[0x1];
3748         u8         reserved_at_41[0xf];
3749         u8         vport_number[0x10];
3750
3751         u8         reserved_at_60[0x20];
3752 };
3753
3754 struct mlx5_ifc_query_vnic_env_out_bits {
3755         u8         status[0x8];
3756         u8         reserved_at_8[0x18];
3757
3758         u8         syndrome[0x20];
3759
3760         u8         reserved_at_40[0x40];
3761
3762         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3763 };
3764
3765 enum {
3766         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3767 };
3768
3769 struct mlx5_ifc_query_vnic_env_in_bits {
3770         u8         opcode[0x10];
3771         u8         reserved_at_10[0x10];
3772
3773         u8         reserved_at_20[0x10];
3774         u8         op_mod[0x10];
3775
3776         u8         other_vport[0x1];
3777         u8         reserved_at_41[0xf];
3778         u8         vport_number[0x10];
3779
3780         u8         reserved_at_60[0x20];
3781 };
3782
3783 struct mlx5_ifc_query_vport_counter_out_bits {
3784         u8         status[0x8];
3785         u8         reserved_at_8[0x18];
3786
3787         u8         syndrome[0x20];
3788
3789         u8         reserved_at_40[0x40];
3790
3791         struct mlx5_ifc_traffic_counter_bits received_errors;
3792
3793         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3794
3795         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3796
3797         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3798
3799         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3800
3801         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3802
3803         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3804
3805         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3806
3807         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3808
3809         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3810
3811         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3812
3813         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3814
3815         u8         reserved_at_680[0xa00];
3816<