1f3483d40055f84b0b063d2503bc521db540412c
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64
65 enum {
66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71
72 enum {
73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76
77 enum {
78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
146         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
147         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
148         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
149         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
150         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
151         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
152         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
153         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
154         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
155         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
156         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
157         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
158         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
159         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
160         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
161         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
162         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
163         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
164         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
165         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
166         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
167         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
168         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
169         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
170         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
171         MLX5_CMD_OP_NOP                           = 0x80d,
172         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
173         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
174         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
175         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
176         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
177         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
178         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
179         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
180         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
181         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
182         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
183         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
184         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
185         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
186         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
187         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
188         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
189         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
190         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
191         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
192         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
193         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
194         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
195         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
196         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
197         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
198         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
199         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
200         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
201         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
202         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
203         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
204         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
205         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
206         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
207         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
208         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
209         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
210         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
211         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
212         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
213         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
214         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
215         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
216         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
217         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
218         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
219         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
220         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
221         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
222         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
223         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
224         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
225         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
226         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
227         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
228         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
229         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
230         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
231         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
232         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
233         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
234         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
235         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
236         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
237         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
238         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
239         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
240         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
241         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
242         MLX5_CMD_OP_MAX
243 };
244
245 struct mlx5_ifc_flow_table_fields_supported_bits {
246         u8         outer_dmac[0x1];
247         u8         outer_smac[0x1];
248         u8         outer_ether_type[0x1];
249         u8         outer_ip_version[0x1];
250         u8         outer_first_prio[0x1];
251         u8         outer_first_cfi[0x1];
252         u8         outer_first_vid[0x1];
253         u8         outer_ipv4_ttl[0x1];
254         u8         outer_second_prio[0x1];
255         u8         outer_second_cfi[0x1];
256         u8         outer_second_vid[0x1];
257         u8         reserved_at_b[0x1];
258         u8         outer_sip[0x1];
259         u8         outer_dip[0x1];
260         u8         outer_frag[0x1];
261         u8         outer_ip_protocol[0x1];
262         u8         outer_ip_ecn[0x1];
263         u8         outer_ip_dscp[0x1];
264         u8         outer_udp_sport[0x1];
265         u8         outer_udp_dport[0x1];
266         u8         outer_tcp_sport[0x1];
267         u8         outer_tcp_dport[0x1];
268         u8         outer_tcp_flags[0x1];
269         u8         outer_gre_protocol[0x1];
270         u8         outer_gre_key[0x1];
271         u8         outer_vxlan_vni[0x1];
272         u8         reserved_at_1a[0x5];
273         u8         source_eswitch_port[0x1];
274
275         u8         inner_dmac[0x1];
276         u8         inner_smac[0x1];
277         u8         inner_ether_type[0x1];
278         u8         inner_ip_version[0x1];
279         u8         inner_first_prio[0x1];
280         u8         inner_first_cfi[0x1];
281         u8         inner_first_vid[0x1];
282         u8         reserved_at_27[0x1];
283         u8         inner_second_prio[0x1];
284         u8         inner_second_cfi[0x1];
285         u8         inner_second_vid[0x1];
286         u8         reserved_at_2b[0x1];
287         u8         inner_sip[0x1];
288         u8         inner_dip[0x1];
289         u8         inner_frag[0x1];
290         u8         inner_ip_protocol[0x1];
291         u8         inner_ip_ecn[0x1];
292         u8         inner_ip_dscp[0x1];
293         u8         inner_udp_sport[0x1];
294         u8         inner_udp_dport[0x1];
295         u8         inner_tcp_sport[0x1];
296         u8         inner_tcp_dport[0x1];
297         u8         inner_tcp_flags[0x1];
298         u8         reserved_at_37[0x9];
299         u8         reserved_at_40[0x17];
300         u8         outer_esp_spi[0x1];
301         u8         reserved_at_58[0x2];
302         u8         bth_dst_qp[0x1];
303
304         u8         reserved_at_5b[0x25];
305 };
306
307 struct mlx5_ifc_flow_table_prop_layout_bits {
308         u8         ft_support[0x1];
309         u8         reserved_at_1[0x1];
310         u8         flow_counter[0x1];
311         u8         flow_modify_en[0x1];
312         u8         modify_root[0x1];
313         u8         identified_miss_table_mode[0x1];
314         u8         flow_table_modify[0x1];
315         u8         encap[0x1];
316         u8         decap[0x1];
317         u8         reserved_at_9[0x17];
318
319         u8         reserved_at_20[0x2];
320         u8         log_max_ft_size[0x6];
321         u8         log_max_modify_header_context[0x8];
322         u8         max_modify_header_actions[0x8];
323         u8         max_ft_level[0x8];
324
325         u8         reserved_at_40[0x20];
326
327         u8         reserved_at_60[0x18];
328         u8         log_max_ft_num[0x8];
329
330         u8         reserved_at_80[0x18];
331         u8         log_max_destination[0x8];
332
333         u8         log_max_flow_counter[0x8];
334         u8         reserved_at_a8[0x10];
335         u8         log_max_flow[0x8];
336
337         u8         reserved_at_c0[0x40];
338
339         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
340
341         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
342 };
343
344 struct mlx5_ifc_odp_per_transport_service_cap_bits {
345         u8         send[0x1];
346         u8         receive[0x1];
347         u8         write[0x1];
348         u8         read[0x1];
349         u8         atomic[0x1];
350         u8         srq_receive[0x1];
351         u8         reserved_at_6[0x1a];
352 };
353
354 struct mlx5_ifc_ipv4_layout_bits {
355         u8         reserved_at_0[0x60];
356
357         u8         ipv4[0x20];
358 };
359
360 struct mlx5_ifc_ipv6_layout_bits {
361         u8         ipv6[16][0x8];
362 };
363
364 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
365         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
366         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
367         u8         reserved_at_0[0x80];
368 };
369
370 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
371         u8         smac_47_16[0x20];
372
373         u8         smac_15_0[0x10];
374         u8         ethertype[0x10];
375
376         u8         dmac_47_16[0x20];
377
378         u8         dmac_15_0[0x10];
379         u8         first_prio[0x3];
380         u8         first_cfi[0x1];
381         u8         first_vid[0xc];
382
383         u8         ip_protocol[0x8];
384         u8         ip_dscp[0x6];
385         u8         ip_ecn[0x2];
386         u8         cvlan_tag[0x1];
387         u8         svlan_tag[0x1];
388         u8         frag[0x1];
389         u8         ip_version[0x4];
390         u8         tcp_flags[0x9];
391
392         u8         tcp_sport[0x10];
393         u8         tcp_dport[0x10];
394
395         u8         reserved_at_c0[0x18];
396         u8         ttl_hoplimit[0x8];
397
398         u8         udp_sport[0x10];
399         u8         udp_dport[0x10];
400
401         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
402
403         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
404 };
405
406 struct mlx5_ifc_fte_match_set_misc_bits {
407         u8         reserved_at_0[0x8];
408         u8         source_sqn[0x18];
409
410         u8         reserved_at_20[0x10];
411         u8         source_port[0x10];
412
413         u8         outer_second_prio[0x3];
414         u8         outer_second_cfi[0x1];
415         u8         outer_second_vid[0xc];
416         u8         inner_second_prio[0x3];
417         u8         inner_second_cfi[0x1];
418         u8         inner_second_vid[0xc];
419
420         u8         outer_second_cvlan_tag[0x1];
421         u8         inner_second_cvlan_tag[0x1];
422         u8         outer_second_svlan_tag[0x1];
423         u8         inner_second_svlan_tag[0x1];
424         u8         reserved_at_64[0xc];
425         u8         gre_protocol[0x10];
426
427         u8         gre_key_h[0x18];
428         u8         gre_key_l[0x8];
429
430         u8         vxlan_vni[0x18];
431         u8         reserved_at_b8[0x8];
432
433         u8         reserved_at_c0[0x20];
434
435         u8         reserved_at_e0[0xc];
436         u8         outer_ipv6_flow_label[0x14];
437
438         u8         reserved_at_100[0xc];
439         u8         inner_ipv6_flow_label[0x14];
440
441         u8         reserved_at_120[0x28];
442         u8         bth_dst_qp[0x18];
443         u8         reserved_at_160[0x20];
444         u8         outer_esp_spi[0x20];
445         u8         reserved_at_1a0[0x60];
446 };
447
448 struct mlx5_ifc_cmd_pas_bits {
449         u8         pa_h[0x20];
450
451         u8         pa_l[0x14];
452         u8         reserved_at_34[0xc];
453 };
454
455 struct mlx5_ifc_uint64_bits {
456         u8         hi[0x20];
457
458         u8         lo[0x20];
459 };
460
461 enum {
462         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
463         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
464         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
465         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
466         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
467         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
468         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
469         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
470         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
471         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
472 };
473
474 struct mlx5_ifc_ads_bits {
475         u8         fl[0x1];
476         u8         free_ar[0x1];
477         u8         reserved_at_2[0xe];
478         u8         pkey_index[0x10];
479
480         u8         reserved_at_20[0x8];
481         u8         grh[0x1];
482         u8         mlid[0x7];
483         u8         rlid[0x10];
484
485         u8         ack_timeout[0x5];
486         u8         reserved_at_45[0x3];
487         u8         src_addr_index[0x8];
488         u8         reserved_at_50[0x4];
489         u8         stat_rate[0x4];
490         u8         hop_limit[0x8];
491
492         u8         reserved_at_60[0x4];
493         u8         tclass[0x8];
494         u8         flow_label[0x14];
495
496         u8         rgid_rip[16][0x8];
497
498         u8         reserved_at_100[0x4];
499         u8         f_dscp[0x1];
500         u8         f_ecn[0x1];
501         u8         reserved_at_106[0x1];
502         u8         f_eth_prio[0x1];
503         u8         ecn[0x2];
504         u8         dscp[0x6];
505         u8         udp_sport[0x10];
506
507         u8         dei_cfi[0x1];
508         u8         eth_prio[0x3];
509         u8         sl[0x4];
510         u8         vhca_port_num[0x8];
511         u8         rmac_47_32[0x10];
512
513         u8         rmac_31_0[0x20];
514 };
515
516 struct mlx5_ifc_flow_table_nic_cap_bits {
517         u8         nic_rx_multi_path_tirs[0x1];
518         u8         nic_rx_multi_path_tirs_fts[0x1];
519         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
520         u8         reserved_at_3[0x1fd];
521
522         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
523
524         u8         reserved_at_400[0x200];
525
526         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
527
528         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
529
530         u8         reserved_at_a00[0x200];
531
532         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
533
534         u8         reserved_at_e00[0x7200];
535 };
536
537 struct mlx5_ifc_flow_table_eswitch_cap_bits {
538         u8     reserved_at_0[0x200];
539
540         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
541
542         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
543
544         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
545
546         u8      reserved_at_800[0x7800];
547 };
548
549 struct mlx5_ifc_e_switch_cap_bits {
550         u8         vport_svlan_strip[0x1];
551         u8         vport_cvlan_strip[0x1];
552         u8         vport_svlan_insert[0x1];
553         u8         vport_cvlan_insert_if_not_exist[0x1];
554         u8         vport_cvlan_insert_overwrite[0x1];
555         u8         reserved_at_5[0x19];
556         u8         nic_vport_node_guid_modify[0x1];
557         u8         nic_vport_port_guid_modify[0x1];
558
559         u8         vxlan_encap_decap[0x1];
560         u8         nvgre_encap_decap[0x1];
561         u8         reserved_at_22[0x9];
562         u8         log_max_encap_headers[0x5];
563         u8         reserved_2b[0x6];
564         u8         max_encap_header_size[0xa];
565
566         u8         reserved_40[0x7c0];
567
568 };
569
570 struct mlx5_ifc_qos_cap_bits {
571         u8         packet_pacing[0x1];
572         u8         esw_scheduling[0x1];
573         u8         esw_bw_share[0x1];
574         u8         esw_rate_limit[0x1];
575         u8         reserved_at_4[0x1c];
576
577         u8         reserved_at_20[0x20];
578
579         u8         packet_pacing_max_rate[0x20];
580
581         u8         packet_pacing_min_rate[0x20];
582
583         u8         reserved_at_80[0x10];
584         u8         packet_pacing_rate_table_size[0x10];
585
586         u8         esw_element_type[0x10];
587         u8         esw_tsar_type[0x10];
588
589         u8         reserved_at_c0[0x10];
590         u8         max_qos_para_vport[0x10];
591
592         u8         max_tsar_bw_share[0x20];
593
594         u8         reserved_at_100[0x700];
595 };
596
597 struct mlx5_ifc_debug_cap_bits {
598         u8         reserved_at_0[0x20];
599
600         u8         reserved_at_20[0x2];
601         u8         stall_detect[0x1];
602         u8         reserved_at_23[0x1d];
603
604         u8         reserved_at_40[0x7c0];
605 };
606
607 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
608         u8         csum_cap[0x1];
609         u8         vlan_cap[0x1];
610         u8         lro_cap[0x1];
611         u8         lro_psh_flag[0x1];
612         u8         lro_time_stamp[0x1];
613         u8         reserved_at_5[0x2];
614         u8         wqe_vlan_insert[0x1];
615         u8         self_lb_en_modifiable[0x1];
616         u8         reserved_at_9[0x2];
617         u8         max_lso_cap[0x5];
618         u8         multi_pkt_send_wqe[0x2];
619         u8         wqe_inline_mode[0x2];
620         u8         rss_ind_tbl_cap[0x4];
621         u8         reg_umr_sq[0x1];
622         u8         scatter_fcs[0x1];
623         u8         enhanced_multi_pkt_send_wqe[0x1];
624         u8         tunnel_lso_const_out_ip_id[0x1];
625         u8         reserved_at_1c[0x2];
626         u8         tunnel_stateless_gre[0x1];
627         u8         tunnel_stateless_vxlan[0x1];
628
629         u8         swp[0x1];
630         u8         swp_csum[0x1];
631         u8         swp_lso[0x1];
632         u8         reserved_at_23[0x1b];
633         u8         max_geneve_opt_len[0x1];
634         u8         tunnel_stateless_geneve_rx[0x1];
635
636         u8         reserved_at_40[0x10];
637         u8         lro_min_mss_size[0x10];
638
639         u8         reserved_at_60[0x120];
640
641         u8         lro_timer_supported_periods[4][0x20];
642
643         u8         reserved_at_200[0x600];
644 };
645
646 struct mlx5_ifc_roce_cap_bits {
647         u8         roce_apm[0x1];
648         u8         reserved_at_1[0x1f];
649
650         u8         reserved_at_20[0x60];
651
652         u8         reserved_at_80[0xc];
653         u8         l3_type[0x4];
654         u8         reserved_at_90[0x8];
655         u8         roce_version[0x8];
656
657         u8         reserved_at_a0[0x10];
658         u8         r_roce_dest_udp_port[0x10];
659
660         u8         r_roce_max_src_udp_port[0x10];
661         u8         r_roce_min_src_udp_port[0x10];
662
663         u8         reserved_at_e0[0x10];
664         u8         roce_address_table_size[0x10];
665
666         u8         reserved_at_100[0x700];
667 };
668
669 enum {
670         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
671         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
672         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
674         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
675         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
676         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
677         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
678         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
679 };
680
681 enum {
682         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
683         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
684         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
685         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
686         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
687         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
688         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
689         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
690         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
691 };
692
693 struct mlx5_ifc_atomic_caps_bits {
694         u8         reserved_at_0[0x40];
695
696         u8         atomic_req_8B_endianness_mode[0x2];
697         u8         reserved_at_42[0x4];
698         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
699
700         u8         reserved_at_47[0x19];
701
702         u8         reserved_at_60[0x20];
703
704         u8         reserved_at_80[0x10];
705         u8         atomic_operations[0x10];
706
707         u8         reserved_at_a0[0x10];
708         u8         atomic_size_qp[0x10];
709
710         u8         reserved_at_c0[0x10];
711         u8         atomic_size_dc[0x10];
712
713         u8         reserved_at_e0[0x720];
714 };
715
716 struct mlx5_ifc_odp_cap_bits {
717         u8         reserved_at_0[0x40];
718
719         u8         sig[0x1];
720         u8         reserved_at_41[0x1f];
721
722         u8         reserved_at_60[0x20];
723
724         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
725
726         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
727
728         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
729
730         u8         reserved_at_e0[0x720];
731 };
732
733 struct mlx5_ifc_calc_op {
734         u8        reserved_at_0[0x10];
735         u8        reserved_at_10[0x9];
736         u8        op_swap_endianness[0x1];
737         u8        op_min[0x1];
738         u8        op_xor[0x1];
739         u8        op_or[0x1];
740         u8        op_and[0x1];
741         u8        op_max[0x1];
742         u8        op_add[0x1];
743 };
744
745 struct mlx5_ifc_vector_calc_cap_bits {
746         u8         calc_matrix[0x1];
747         u8         reserved_at_1[0x1f];
748         u8         reserved_at_20[0x8];
749         u8         max_vec_count[0x8];
750         u8         reserved_at_30[0xd];
751         u8         max_chunk_size[0x3];
752         struct mlx5_ifc_calc_op calc0;
753         struct mlx5_ifc_calc_op calc1;
754         struct mlx5_ifc_calc_op calc2;
755         struct mlx5_ifc_calc_op calc3;
756
757         u8         reserved_at_e0[0x720];
758 };
759
760 enum {
761         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
762         MLX5_WQ_TYPE_CYCLIC       = 0x1,
763         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
764         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
765 };
766
767 enum {
768         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
769         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
770 };
771
772 enum {
773         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
774         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
775         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
776         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
777         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
778 };
779
780 enum {
781         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
782         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
783         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
784         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
785         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
786         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
787 };
788
789 enum {
790         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
791         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
792 };
793
794 enum {
795         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
796         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
797         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
798 };
799
800 enum {
801         MLX5_CAP_PORT_TYPE_IB  = 0x0,
802         MLX5_CAP_PORT_TYPE_ETH = 0x1,
803 };
804
805 enum {
806         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
807         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
808         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
809 };
810
811 struct mlx5_ifc_cmd_hca_cap_bits {
812         u8         reserved_at_0[0x30];
813         u8         vhca_id[0x10];
814
815         u8         reserved_at_40[0x40];
816
817         u8         log_max_srq_sz[0x8];
818         u8         log_max_qp_sz[0x8];
819         u8         reserved_at_90[0xb];
820         u8         log_max_qp[0x5];
821
822         u8         reserved_at_a0[0xb];
823         u8         log_max_srq[0x5];
824         u8         reserved_at_b0[0x10];
825
826         u8         reserved_at_c0[0x8];
827         u8         log_max_cq_sz[0x8];
828         u8         reserved_at_d0[0xb];
829         u8         log_max_cq[0x5];
830
831         u8         log_max_eq_sz[0x8];
832         u8         reserved_at_e8[0x2];
833         u8         log_max_mkey[0x6];
834         u8         reserved_at_f0[0xc];
835         u8         log_max_eq[0x4];
836
837         u8         max_indirection[0x8];
838         u8         fixed_buffer_size[0x1];
839         u8         log_max_mrw_sz[0x7];
840         u8         force_teardown[0x1];
841         u8         reserved_at_111[0x1];
842         u8         log_max_bsf_list_size[0x6];
843         u8         umr_extended_translation_offset[0x1];
844         u8         null_mkey[0x1];
845         u8         log_max_klm_list_size[0x6];
846
847         u8         reserved_at_120[0xa];
848         u8         log_max_ra_req_dc[0x6];
849         u8         reserved_at_130[0xa];
850         u8         log_max_ra_res_dc[0x6];
851
852         u8         reserved_at_140[0xa];
853         u8         log_max_ra_req_qp[0x6];
854         u8         reserved_at_150[0xa];
855         u8         log_max_ra_res_qp[0x6];
856
857         u8         end_pad[0x1];
858         u8         cc_query_allowed[0x1];
859         u8         cc_modify_allowed[0x1];
860         u8         start_pad[0x1];
861         u8         cache_line_128byte[0x1];
862         u8         reserved_at_165[0xa];
863         u8         qcam_reg[0x1];
864         u8         gid_table_size[0x10];
865
866         u8         out_of_seq_cnt[0x1];
867         u8         vport_counters[0x1];
868         u8         retransmission_q_counters[0x1];
869         u8         debug[0x1];
870         u8         modify_rq_counter_set_id[0x1];
871         u8         rq_delay_drop[0x1];
872         u8         max_qp_cnt[0xa];
873         u8         pkey_table_size[0x10];
874
875         u8         vport_group_manager[0x1];
876         u8         vhca_group_manager[0x1];
877         u8         ib_virt[0x1];
878         u8         eth_virt[0x1];
879         u8         vnic_env_queue_counters[0x1];
880         u8         ets[0x1];
881         u8         nic_flow_table[0x1];
882         u8         eswitch_flow_table[0x1];
883         u8         early_vf_enable[0x1];
884         u8         mcam_reg[0x1];
885         u8         pcam_reg[0x1];
886         u8         local_ca_ack_delay[0x5];
887         u8         port_module_event[0x1];
888         u8         enhanced_error_q_counters[0x1];
889         u8         ports_check[0x1];
890         u8         reserved_at_1b3[0x1];
891         u8         disable_link_up[0x1];
892         u8         beacon_led[0x1];
893         u8         port_type[0x2];
894         u8         num_ports[0x8];
895
896         u8         reserved_at_1c0[0x1];
897         u8         pps[0x1];
898         u8         pps_modify[0x1];
899         u8         log_max_msg[0x5];
900         u8         reserved_at_1c8[0x4];
901         u8         max_tc[0x4];
902         u8         reserved_at_1d0[0x1];
903         u8         dcbx[0x1];
904         u8         general_notification_event[0x1];
905         u8         reserved_at_1d3[0x2];
906         u8         fpga[0x1];
907         u8         rol_s[0x1];
908         u8         rol_g[0x1];
909         u8         reserved_at_1d8[0x1];
910         u8         wol_s[0x1];
911         u8         wol_g[0x1];
912         u8         wol_a[0x1];
913         u8         wol_b[0x1];
914         u8         wol_m[0x1];
915         u8         wol_u[0x1];
916         u8         wol_p[0x1];
917
918         u8         stat_rate_support[0x10];
919         u8         reserved_at_1f0[0xc];
920         u8         cqe_version[0x4];
921
922         u8         compact_address_vector[0x1];
923         u8         striding_rq[0x1];
924         u8         reserved_at_202[0x1];
925         u8         ipoib_enhanced_offloads[0x1];
926         u8         ipoib_basic_offloads[0x1];
927         u8         reserved_at_205[0x5];
928         u8         umr_fence[0x2];
929         u8         reserved_at_20c[0x3];
930         u8         drain_sigerr[0x1];
931         u8         cmdif_checksum[0x2];
932         u8         sigerr_cqe[0x1];
933         u8         reserved_at_213[0x1];
934         u8         wq_signature[0x1];
935         u8         sctr_data_cqe[0x1];
936         u8         reserved_at_216[0x1];
937         u8         sho[0x1];
938         u8         tph[0x1];
939         u8         rf[0x1];
940         u8         dct[0x1];
941         u8         qos[0x1];
942         u8         eth_net_offloads[0x1];
943         u8         roce[0x1];
944         u8         atomic[0x1];
945         u8         reserved_at_21f[0x1];
946
947         u8         cq_oi[0x1];
948         u8         cq_resize[0x1];
949         u8         cq_moderation[0x1];
950         u8         reserved_at_223[0x3];
951         u8         cq_eq_remap[0x1];
952         u8         pg[0x1];
953         u8         block_lb_mc[0x1];
954         u8         reserved_at_229[0x1];
955         u8         scqe_break_moderation[0x1];
956         u8         cq_period_start_from_cqe[0x1];
957         u8         cd[0x1];
958         u8         reserved_at_22d[0x1];
959         u8         apm[0x1];
960         u8         vector_calc[0x1];
961         u8         umr_ptr_rlky[0x1];
962         u8         imaicl[0x1];
963         u8         reserved_at_232[0x4];
964         u8         qkv[0x1];
965         u8         pkv[0x1];
966         u8         set_deth_sqpn[0x1];
967         u8         reserved_at_239[0x3];
968         u8         xrc[0x1];
969         u8         ud[0x1];
970         u8         uc[0x1];
971         u8         rc[0x1];
972
973         u8         uar_4k[0x1];
974         u8         reserved_at_241[0x9];
975         u8         uar_sz[0x6];
976         u8         reserved_at_250[0x8];
977         u8         log_pg_sz[0x8];
978
979         u8         bf[0x1];
980         u8         driver_version[0x1];
981         u8         pad_tx_eth_packet[0x1];
982         u8         reserved_at_263[0x8];
983         u8         log_bf_reg_size[0x5];
984
985         u8         reserved_at_270[0xb];
986         u8         lag_master[0x1];
987         u8         num_lag_ports[0x4];
988
989         u8         reserved_at_280[0x10];
990         u8         max_wqe_sz_sq[0x10];
991
992         u8         reserved_at_2a0[0x10];
993         u8         max_wqe_sz_rq[0x10];
994
995         u8         max_flow_counter_31_16[0x10];
996         u8         max_wqe_sz_sq_dc[0x10];
997
998         u8         reserved_at_2e0[0x7];
999         u8         max_qp_mcg[0x19];
1000
1001         u8         reserved_at_300[0x18];
1002         u8         log_max_mcg[0x8];
1003
1004         u8         reserved_at_320[0x3];
1005         u8         log_max_transport_domain[0x5];
1006         u8         reserved_at_328[0x3];
1007         u8         log_max_pd[0x5];
1008         u8         reserved_at_330[0xb];
1009         u8         log_max_xrcd[0x5];
1010
1011         u8         nic_receive_steering_discard[0x1];
1012         u8         receive_discard_vport_down[0x1];
1013         u8         transmit_discard_vport_down[0x1];
1014         u8         reserved_at_343[0x5];
1015         u8         log_max_flow_counter_bulk[0x8];
1016         u8         max_flow_counter_15_0[0x10];
1017
1018
1019         u8         reserved_at_360[0x3];
1020         u8         log_max_rq[0x5];
1021         u8         reserved_at_368[0x3];
1022         u8         log_max_sq[0x5];
1023         u8         reserved_at_370[0x3];
1024         u8         log_max_tir[0x5];
1025         u8         reserved_at_378[0x3];
1026         u8         log_max_tis[0x5];
1027
1028         u8         basic_cyclic_rcv_wqe[0x1];
1029         u8         reserved_at_381[0x2];
1030         u8         log_max_rmp[0x5];
1031         u8         reserved_at_388[0x3];
1032         u8         log_max_rqt[0x5];
1033         u8         reserved_at_390[0x3];
1034         u8         log_max_rqt_size[0x5];
1035         u8         reserved_at_398[0x3];
1036         u8         log_max_tis_per_sq[0x5];
1037
1038         u8         reserved_at_3a0[0x3];
1039         u8         log_max_stride_sz_rq[0x5];
1040         u8         reserved_at_3a8[0x3];
1041         u8         log_min_stride_sz_rq[0x5];
1042         u8         reserved_at_3b0[0x3];
1043         u8         log_max_stride_sz_sq[0x5];
1044         u8         reserved_at_3b8[0x3];
1045         u8         log_min_stride_sz_sq[0x5];
1046
1047         u8         hairpin[0x1];
1048         u8         reserved_at_3c1[0x2];
1049         u8         log_max_hairpin_queues[0x5];
1050         u8         reserved_at_3c8[0x3];
1051         u8         log_max_hairpin_wq_data_sz[0x5];
1052         u8         reserved_at_3d0[0x3];
1053         u8         log_max_hairpin_num_packets[0x5];
1054         u8         reserved_at_3d8[0x3];
1055         u8         log_max_wq_sz[0x5];
1056
1057         u8         nic_vport_change_event[0x1];
1058         u8         disable_local_lb_uc[0x1];
1059         u8         disable_local_lb_mc[0x1];
1060         u8         log_min_hairpin_wq_data_sz[0x5];
1061         u8         reserved_at_3e8[0x3];
1062         u8         log_max_vlan_list[0x5];
1063         u8         reserved_at_3f0[0x3];
1064         u8         log_max_current_mc_list[0x5];
1065         u8         reserved_at_3f8[0x3];
1066         u8         log_max_current_uc_list[0x5];
1067
1068         u8         reserved_at_400[0x80];
1069
1070         u8         reserved_at_480[0x3];
1071         u8         log_max_l2_table[0x5];
1072         u8         reserved_at_488[0x8];
1073         u8         log_uar_page_sz[0x10];
1074
1075         u8         reserved_at_4a0[0x20];
1076         u8         device_frequency_mhz[0x20];
1077         u8         device_frequency_khz[0x20];
1078
1079         u8         reserved_at_500[0x20];
1080         u8         num_of_uars_per_page[0x20];
1081         u8         reserved_at_540[0x40];
1082
1083         u8         reserved_at_580[0x3d];
1084         u8         cqe_128_always[0x1];
1085         u8         cqe_compression_128[0x1];
1086         u8         cqe_compression[0x1];
1087
1088         u8         cqe_compression_timeout[0x10];
1089         u8         cqe_compression_max_num[0x10];
1090
1091         u8         reserved_at_5e0[0x10];
1092         u8         tag_matching[0x1];
1093         u8         rndv_offload_rc[0x1];
1094         u8         rndv_offload_dc[0x1];
1095         u8         log_tag_matching_list_sz[0x5];
1096         u8         reserved_at_5f8[0x3];
1097         u8         log_max_xrq[0x5];
1098
1099         u8         affiliate_nic_vport_criteria[0x8];
1100         u8         native_port_num[0x8];
1101         u8         num_vhca_ports[0x8];
1102         u8         reserved_at_618[0x6];
1103         u8         sw_owner_id[0x1];
1104         u8         reserved_at_61f[0x1e1];
1105 };
1106
1107 enum mlx5_flow_destination_type {
1108         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1109         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1110         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1111
1112         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1113         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1114 };
1115
1116 struct mlx5_ifc_dest_format_struct_bits {
1117         u8         destination_type[0x8];
1118         u8         destination_id[0x18];
1119
1120         u8         reserved_at_20[0x20];
1121 };
1122
1123 struct mlx5_ifc_flow_counter_list_bits {
1124         u8         flow_counter_id[0x20];
1125
1126         u8         reserved_at_20[0x20];
1127 };
1128
1129 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1130         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1131         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1132         u8         reserved_at_0[0x40];
1133 };
1134
1135 struct mlx5_ifc_fte_match_param_bits {
1136         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1137
1138         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1139
1140         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1141
1142         u8         reserved_at_600[0xa00];
1143 };
1144
1145 enum {
1146         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1147         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1148         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1149         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1150         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1151 };
1152
1153 struct mlx5_ifc_rx_hash_field_select_bits {
1154         u8         l3_prot_type[0x1];
1155         u8         l4_prot_type[0x1];
1156         u8         selected_fields[0x1e];
1157 };
1158
1159 enum {
1160         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1161         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1162 };
1163
1164 enum {
1165         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1166         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1167 };
1168
1169 struct mlx5_ifc_wq_bits {
1170         u8         wq_type[0x4];
1171         u8         wq_signature[0x1];
1172         u8         end_padding_mode[0x2];
1173         u8         cd_slave[0x1];
1174         u8         reserved_at_8[0x18];
1175
1176         u8         hds_skip_first_sge[0x1];
1177         u8         log2_hds_buf_size[0x3];
1178         u8         reserved_at_24[0x7];
1179         u8         page_offset[0x5];
1180         u8         lwm[0x10];
1181
1182         u8         reserved_at_40[0x8];
1183         u8         pd[0x18];
1184
1185         u8         reserved_at_60[0x8];
1186         u8         uar_page[0x18];
1187
1188         u8         dbr_addr[0x40];
1189
1190         u8         hw_counter[0x20];
1191
1192         u8         sw_counter[0x20];
1193
1194         u8         reserved_at_100[0xc];
1195         u8         log_wq_stride[0x4];
1196         u8         reserved_at_110[0x3];
1197         u8         log_wq_pg_sz[0x5];
1198         u8         reserved_at_118[0x3];
1199         u8         log_wq_sz[0x5];
1200
1201         u8         reserved_at_120[0x3];
1202         u8         log_hairpin_num_packets[0x5];
1203         u8         reserved_at_128[0x3];
1204         u8         log_hairpin_data_sz[0x5];
1205         u8         reserved_at_130[0x5];
1206
1207         u8         log_wqe_num_of_strides[0x3];
1208         u8         two_byte_shift_en[0x1];
1209         u8         reserved_at_139[0x4];
1210         u8         log_wqe_stride_size[0x3];
1211
1212         u8         reserved_at_140[0x4c0];
1213
1214         struct mlx5_ifc_cmd_pas_bits pas[0];
1215 };
1216
1217 struct mlx5_ifc_rq_num_bits {
1218         u8         reserved_at_0[0x8];
1219         u8         rq_num[0x18];
1220 };
1221
1222 struct mlx5_ifc_mac_address_layout_bits {
1223         u8         reserved_at_0[0x10];
1224         u8         mac_addr_47_32[0x10];
1225
1226         u8         mac_addr_31_0[0x20];
1227 };
1228
1229 struct mlx5_ifc_vlan_layout_bits {
1230         u8         reserved_at_0[0x14];
1231         u8         vlan[0x0c];
1232
1233         u8         reserved_at_20[0x20];
1234 };
1235
1236 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1237         u8         reserved_at_0[0xa0];
1238
1239         u8         min_time_between_cnps[0x20];
1240
1241         u8         reserved_at_c0[0x12];
1242         u8         cnp_dscp[0x6];
1243         u8         reserved_at_d8[0x4];
1244         u8         cnp_prio_mode[0x1];
1245         u8         cnp_802p_prio[0x3];
1246
1247         u8         reserved_at_e0[0x720];
1248 };
1249
1250 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1251         u8         reserved_at_0[0x60];
1252
1253         u8         reserved_at_60[0x4];
1254         u8         clamp_tgt_rate[0x1];
1255         u8         reserved_at_65[0x3];
1256         u8         clamp_tgt_rate_after_time_inc[0x1];
1257         u8         reserved_at_69[0x17];
1258
1259         u8         reserved_at_80[0x20];
1260
1261         u8         rpg_time_reset[0x20];
1262
1263         u8         rpg_byte_reset[0x20];
1264
1265         u8         rpg_threshold[0x20];
1266
1267         u8         rpg_max_rate[0x20];
1268
1269         u8         rpg_ai_rate[0x20];
1270
1271         u8         rpg_hai_rate[0x20];
1272
1273         u8         rpg_gd[0x20];
1274
1275         u8         rpg_min_dec_fac[0x20];
1276
1277         u8         rpg_min_rate[0x20];
1278
1279         u8         reserved_at_1c0[0xe0];
1280
1281         u8         rate_to_set_on_first_cnp[0x20];
1282
1283         u8         dce_tcp_g[0x20];
1284
1285         u8         dce_tcp_rtt[0x20];
1286
1287         u8         rate_reduce_monitor_period[0x20];
1288
1289         u8         reserved_at_320[0x20];
1290
1291         u8         initial_alpha_value[0x20];
1292
1293         u8         reserved_at_360[0x4a0];
1294 };
1295
1296 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1297         u8         reserved_at_0[0x80];
1298
1299         u8         rppp_max_rps[0x20];
1300
1301         u8         rpg_time_reset[0x20];
1302
1303         u8         rpg_byte_reset[0x20];
1304
1305         u8         rpg_threshold[0x20];
1306
1307         u8         rpg_max_rate[0x20];
1308
1309         u8         rpg_ai_rate[0x20];
1310
1311         u8         rpg_hai_rate[0x20];
1312
1313         u8         rpg_gd[0x20];
1314
1315         u8         rpg_min_dec_fac[0x20];
1316
1317         u8         rpg_min_rate[0x20];
1318
1319         u8         reserved_at_1c0[0x640];
1320 };
1321
1322 enum {
1323         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1324         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1325         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1326 };
1327
1328 struct mlx5_ifc_resize_field_select_bits {
1329         u8         resize_field_select[0x20];
1330 };
1331
1332 enum {
1333         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1334         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1335         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1336         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1337 };
1338
1339 struct mlx5_ifc_modify_field_select_bits {
1340         u8         modify_field_select[0x20];
1341 };
1342
1343 struct mlx5_ifc_field_select_r_roce_np_bits {
1344         u8         field_select_r_roce_np[0x20];
1345 };
1346
1347 struct mlx5_ifc_field_select_r_roce_rp_bits {
1348         u8         field_select_r_roce_rp[0x20];
1349 };
1350
1351 enum {
1352         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1353         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1354         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1355         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1356         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1357         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1358         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1359         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1360         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1361         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1362 };
1363
1364 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1365         u8         field_select_8021qaurp[0x20];
1366 };
1367
1368 struct mlx5_ifc_phys_layer_cntrs_bits {
1369         u8         time_since_last_clear_high[0x20];
1370
1371         u8         time_since_last_clear_low[0x20];
1372
1373         u8         symbol_errors_high[0x20];
1374
1375         u8         symbol_errors_low[0x20];
1376
1377         u8         sync_headers_errors_high[0x20];
1378
1379         u8         sync_headers_errors_low[0x20];
1380
1381         u8         edpl_bip_errors_lane0_high[0x20];
1382
1383         u8         edpl_bip_errors_lane0_low[0x20];
1384
1385         u8         edpl_bip_errors_lane1_high[0x20];
1386
1387         u8         edpl_bip_errors_lane1_low[0x20];
1388
1389         u8         edpl_bip_errors_lane2_high[0x20];
1390
1391         u8         edpl_bip_errors_lane2_low[0x20];
1392
1393         u8         edpl_bip_errors_lane3_high[0x20];
1394
1395         u8         edpl_bip_errors_lane3_low[0x20];
1396
1397         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1398
1399         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1400
1401         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1402
1403         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1404
1405         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1406
1407         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1408
1409         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1410
1411         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1412
1413         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1414
1415         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1416
1417         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1418
1419         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1420
1421         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1422
1423         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1424
1425         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1426
1427         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1428
1429         u8         rs_fec_corrected_blocks_high[0x20];
1430
1431         u8         rs_fec_corrected_blocks_low[0x20];
1432
1433         u8         rs_fec_uncorrectable_blocks_high[0x20];
1434
1435         u8         rs_fec_uncorrectable_blocks_low[0x20];
1436
1437         u8         rs_fec_no_errors_blocks_high[0x20];
1438
1439         u8         rs_fec_no_errors_blocks_low[0x20];
1440
1441         u8         rs_fec_single_error_blocks_high[0x20];
1442
1443         u8         rs_fec_single_error_blocks_low[0x20];
1444
1445         u8         rs_fec_corrected_symbols_total_high[0x20];
1446
1447         u8         rs_fec_corrected_symbols_total_low[0x20];
1448
1449         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1450
1451         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1452
1453         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1454
1455         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1456
1457         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1458
1459         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1460
1461         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1462
1463         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1464
1465         u8         link_down_events[0x20];
1466
1467         u8         successful_recovery_events[0x20];
1468
1469         u8         reserved_at_640[0x180];
1470 };
1471
1472 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1473         u8         time_since_last_clear_high[0x20];
1474
1475         u8         time_since_last_clear_low[0x20];
1476
1477         u8         phy_received_bits_high[0x20];
1478
1479         u8         phy_received_bits_low[0x20];
1480
1481         u8         phy_symbol_errors_high[0x20];
1482
1483         u8         phy_symbol_errors_low[0x20];
1484
1485         u8         phy_corrected_bits_high[0x20];
1486
1487         u8         phy_corrected_bits_low[0x20];
1488
1489         u8         phy_corrected_bits_lane0_high[0x20];
1490
1491         u8         phy_corrected_bits_lane0_low[0x20];
1492
1493         u8         phy_corrected_bits_lane1_high[0x20];
1494
1495         u8         phy_corrected_bits_lane1_low[0x20];
1496
1497         u8         phy_corrected_bits_lane2_high[0x20];
1498
1499         u8         phy_corrected_bits_lane2_low[0x20];
1500
1501         u8         phy_corrected_bits_lane3_high[0x20];
1502
1503         u8         phy_corrected_bits_lane3_low[0x20];
1504
1505         u8         reserved_at_200[0x5c0];
1506 };
1507
1508 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1509         u8         symbol_error_counter[0x10];
1510
1511         u8         link_error_recovery_counter[0x8];
1512
1513         u8         link_downed_counter[0x8];
1514
1515         u8         port_rcv_errors[0x10];
1516
1517         u8         port_rcv_remote_physical_errors[0x10];
1518
1519         u8         port_rcv_switch_relay_errors[0x10];
1520
1521         u8         port_xmit_discards[0x10];
1522
1523         u8         port_xmit_constraint_errors[0x8];
1524
1525         u8         port_rcv_constraint_errors[0x8];
1526
1527         u8         reserved_at_70[0x8];
1528
1529         u8         link_overrun_errors[0x8];
1530
1531         u8         reserved_at_80[0x10];
1532
1533         u8         vl_15_dropped[0x10];
1534
1535         u8         reserved_at_a0[0x80];
1536
1537         u8         port_xmit_wait[0x20];
1538 };
1539
1540 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1541         u8         transmit_queue_high[0x20];
1542
1543         u8         transmit_queue_low[0x20];
1544
1545         u8         reserved_at_40[0x780];
1546 };
1547
1548 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1549         u8         rx_octets_high[0x20];
1550
1551         u8         rx_octets_low[0x20];
1552
1553         u8         reserved_at_40[0xc0];
1554
1555         u8         rx_frames_high[0x20];
1556
1557         u8         rx_frames_low[0x20];
1558
1559         u8         tx_octets_high[0x20];
1560
1561         u8         tx_octets_low[0x20];
1562
1563         u8         reserved_at_180[0xc0];
1564
1565         u8         tx_frames_high[0x20];
1566
1567         u8         tx_frames_low[0x20];
1568
1569         u8         rx_pause_high[0x20];
1570
1571         u8         rx_pause_low[0x20];
1572
1573         u8         rx_pause_duration_high[0x20];
1574
1575         u8         rx_pause_duration_low[0x20];
1576
1577         u8         tx_pause_high[0x20];
1578
1579         u8         tx_pause_low[0x20];
1580
1581         u8         tx_pause_duration_high[0x20];
1582
1583         u8         tx_pause_duration_low[0x20];
1584
1585         u8         rx_pause_transition_high[0x20];
1586
1587         u8         rx_pause_transition_low[0x20];
1588
1589         u8         reserved_at_3c0[0x40];
1590
1591         u8         device_stall_minor_watermark_cnt_high[0x20];
1592
1593         u8         device_stall_minor_watermark_cnt_low[0x20];
1594
1595         u8         device_stall_critical_watermark_cnt_high[0x20];
1596
1597         u8         device_stall_critical_watermark_cnt_low[0x20];
1598
1599         u8         reserved_at_480[0x340];
1600 };
1601
1602 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1603         u8         port_transmit_wait_high[0x20];
1604
1605         u8         port_transmit_wait_low[0x20];
1606
1607         u8         reserved_at_40[0x100];
1608
1609         u8         rx_buffer_almost_full_high[0x20];
1610
1611         u8         rx_buffer_almost_full_low[0x20];
1612
1613         u8         rx_buffer_full_high[0x20];
1614
1615         u8         rx_buffer_full_low[0x20];
1616
1617         u8         reserved_at_1c0[0x600];
1618 };
1619
1620 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1621         u8         dot3stats_alignment_errors_high[0x20];
1622
1623         u8         dot3stats_alignment_errors_low[0x20];
1624
1625         u8         dot3stats_fcs_errors_high[0x20];
1626
1627         u8         dot3stats_fcs_errors_low[0x20];
1628
1629         u8         dot3stats_single_collision_frames_high[0x20];
1630
1631         u8         dot3stats_single_collision_frames_low[0x20];
1632
1633         u8         dot3stats_multiple_collision_frames_high[0x20];
1634
1635         u8         dot3stats_multiple_collision_frames_low[0x20];
1636
1637         u8         dot3stats_sqe_test_errors_high[0x20];
1638
1639         u8         dot3stats_sqe_test_errors_low[0x20];
1640
1641         u8         dot3stats_deferred_transmissions_high[0x20];
1642
1643         u8         dot3stats_deferred_transmissions_low[0x20];
1644
1645         u8         dot3stats_late_collisions_high[0x20];
1646
1647         u8         dot3stats_late_collisions_low[0x20];
1648
1649         u8         dot3stats_excessive_collisions_high[0x20];
1650
1651         u8         dot3stats_excessive_collisions_low[0x20];
1652
1653         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1654
1655         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1656
1657         u8         dot3stats_carrier_sense_errors_high[0x20];
1658
1659         u8         dot3stats_carrier_sense_errors_low[0x20];
1660
1661         u8         dot3stats_frame_too_longs_high[0x20];
1662
1663         u8         dot3stats_frame_too_longs_low[0x20];
1664
1665         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1666
1667         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1668
1669         u8         dot3stats_symbol_errors_high[0x20];
1670
1671         u8         dot3stats_symbol_errors_low[0x20];
1672
1673         u8         dot3control_in_unknown_opcodes_high[0x20];
1674
1675         u8         dot3control_in_unknown_opcodes_low[0x20];
1676
1677         u8         dot3in_pause_frames_high[0x20];
1678
1679         u8         dot3in_pause_frames_low[0x20];
1680
1681         u8         dot3out_pause_frames_high[0x20];
1682
1683         u8         dot3out_pause_frames_low[0x20];
1684
1685         u8         reserved_at_400[0x3c0];
1686 };
1687
1688 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1689         u8         ether_stats_drop_events_high[0x20];
1690
1691         u8         ether_stats_drop_events_low[0x20];
1692
1693         u8         ether_stats_octets_high[0x20];
1694
1695         u8         ether_stats_octets_low[0x20];
1696
1697         u8         ether_stats_pkts_high[0x20];
1698
1699         u8         ether_stats_pkts_low[0x20];
1700
1701         u8         ether_stats_broadcast_pkts_high[0x20];
1702
1703         u8         ether_stats_broadcast_pkts_low[0x20];
1704
1705         u8         ether_stats_multicast_pkts_high[0x20];
1706
1707         u8         ether_stats_multicast_pkts_low[0x20];
1708
1709         u8         ether_stats_crc_align_errors_high[0x20];
1710
1711         u8         ether_stats_crc_align_errors_low[0x20];
1712
1713         u8         ether_stats_undersize_pkts_high[0x20];
1714
1715         u8         ether_stats_undersize_pkts_low[0x20];
1716
1717         u8         ether_stats_oversize_pkts_high[0x20];
1718
1719         u8         ether_stats_oversize_pkts_low[0x20];
1720
1721         u8         ether_stats_fragments_high[0x20];
1722
1723         u8         ether_stats_fragments_low[0x20];
1724
1725         u8         ether_stats_jabbers_high[0x20];
1726
1727         u8         ether_stats_jabbers_low[0x20];
1728
1729         u8         ether_stats_collisions_high[0x20];
1730
1731         u8         ether_stats_collisions_low[0x20];
1732
1733         u8         ether_stats_pkts64octets_high[0x20];
1734
1735         u8         ether_stats_pkts64octets_low[0x20];
1736
1737         u8         ether_stats_pkts65to127octets_high[0x20];
1738
1739         u8         ether_stats_pkts65to127octets_low[0x20];
1740
1741         u8         ether_stats_pkts128to255octets_high[0x20];
1742
1743         u8         ether_stats_pkts128to255octets_low[0x20];
1744
1745         u8         ether_stats_pkts256to511octets_high[0x20];
1746
1747         u8         ether_stats_pkts256to511octets_low[0x20];
1748
1749         u8         ether_stats_pkts512to1023octets_high[0x20];
1750
1751         u8         ether_stats_pkts512to1023octets_low[0x20];
1752
1753         u8         ether_stats_pkts1024to1518octets_high[0x20];
1754
1755         u8         ether_stats_pkts1024to1518octets_low[0x20];
1756
1757         u8         ether_stats_pkts1519to2047octets_high[0x20];
1758
1759         u8         ether_stats_pkts1519to2047octets_low[0x20];
1760
1761         u8         ether_stats_pkts2048to4095octets_high[0x20];
1762
1763         u8         ether_stats_pkts2048to4095octets_low[0x20];
1764
1765         u8         ether_stats_pkts4096to8191octets_high[0x20];
1766
1767         u8         ether_stats_pkts4096to8191octets_low[0x20];
1768
1769         u8         ether_stats_pkts8192to10239octets_high[0x20];
1770
1771         u8         ether_stats_pkts8192to10239octets_low[0x20];
1772
1773         u8         reserved_at_540[0x280];
1774 };
1775
1776 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1777         u8         if_in_octets_high[0x20];
1778
1779         u8         if_in_octets_low[0x20];
1780
1781         u8         if_in_ucast_pkts_high[0x20];
1782
1783         u8         if_in_ucast_pkts_low[0x20];
1784
1785         u8         if_in_discards_high[0x20];
1786
1787         u8         if_in_discards_low[0x20];
1788
1789         u8         if_in_errors_high[0x20];
1790
1791         u8         if_in_errors_low[0x20];
1792
1793         u8         if_in_unknown_protos_high[0x20];
1794
1795         u8         if_in_unknown_protos_low[0x20];
1796
1797         u8         if_out_octets_high[0x20];
1798
1799         u8         if_out_octets_low[0x20];
1800
1801         u8         if_out_ucast_pkts_high[0x20];
1802
1803         u8         if_out_ucast_pkts_low[0x20];
1804
1805         u8         if_out_discards_high[0x20];
1806
1807         u8         if_out_discards_low[0x20];
1808
1809         u8         if_out_errors_high[0x20];
1810
1811         u8         if_out_errors_low[0x20];
1812
1813         u8         if_in_multicast_pkts_high[0x20];
1814
1815         u8         if_in_multicast_pkts_low[0x20];
1816
1817         u8         if_in_broadcast_pkts_high[0x20];
1818
1819         u8         if_in_broadcast_pkts_low[0x20];
1820
1821         u8         if_out_multicast_pkts_high[0x20];
1822
1823         u8         if_out_multicast_pkts_low[0x20];
1824
1825         u8         if_out_broadcast_pkts_high[0x20];
1826
1827         u8         if_out_broadcast_pkts_low[0x20];
1828
1829         u8         reserved_at_340[0x480];
1830 };
1831
1832 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1833         u8         a_frames_transmitted_ok_high[0x20];
1834
1835         u8         a_frames_transmitted_ok_low[0x20];
1836
1837         u8         a_frames_received_ok_high[0x20];
1838
1839         u8         a_frames_received_ok_low[0x20];
1840
1841         u8         a_frame_check_sequence_errors_high[0x20];
1842
1843         u8         a_frame_check_sequence_errors_low[0x20];
1844
1845         u8         a_alignment_errors_high[0x20];
1846
1847         u8         a_alignment_errors_low[0x20];
1848
1849         u8         a_octets_transmitted_ok_high[0x20];
1850
1851         u8         a_octets_transmitted_ok_low[0x20];
1852
1853         u8         a_octets_received_ok_high[0x20];
1854
1855         u8         a_octets_received_ok_low[0x20];
1856
1857         u8         a_multicast_frames_xmitted_ok_high[0x20];
1858
1859         u8         a_multicast_frames_xmitted_ok_low[0x20];
1860
1861         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1862
1863         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1864
1865         u8         a_multicast_frames_received_ok_high[0x20];
1866
1867         u8         a_multicast_frames_received_ok_low[0x20];
1868
1869         u8         a_broadcast_frames_received_ok_high[0x20];
1870
1871         u8         a_broadcast_frames_received_ok_low[0x20];
1872
1873         u8         a_in_range_length_errors_high[0x20];
1874
1875         u8         a_in_range_length_errors_low[0x20];
1876
1877         u8         a_out_of_range_length_field_high[0x20];
1878
1879         u8         a_out_of_range_length_field_low[0x20];
1880
1881         u8         a_frame_too_long_errors_high[0x20];
1882
1883         u8         a_frame_too_long_errors_low[0x20];
1884
1885         u8         a_symbol_error_during_carrier_high[0x20];
1886
1887         u8         a_symbol_error_during_carrier_low[0x20];
1888
1889         u8         a_mac_control_frames_transmitted_high[0x20];
1890
1891         u8         a_mac_control_frames_transmitted_low[0x20];
1892
1893         u8         a_mac_control_frames_received_high[0x20];
1894
1895         u8         a_mac_control_frames_received_low[0x20];
1896
1897         u8         a_unsupported_opcodes_received_high[0x20];
1898
1899         u8         a_unsupported_opcodes_received_low[0x20];
1900
1901         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1902
1903         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1904
1905         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1906
1907         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1908
1909         u8         reserved_at_4c0[0x300];
1910 };
1911
1912 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1913         u8         life_time_counter_high[0x20];
1914
1915         u8         life_time_counter_low[0x20];
1916
1917         u8         rx_errors[0x20];
1918
1919         u8         tx_errors[0x20];
1920
1921         u8         l0_to_recovery_eieos[0x20];
1922
1923         u8         l0_to_recovery_ts[0x20];
1924
1925         u8         l0_to_recovery_framing[0x20];
1926
1927         u8         l0_to_recovery_retrain[0x20];
1928
1929         u8         crc_error_dllp[0x20];
1930
1931         u8         crc_error_tlp[0x20];
1932
1933         u8         tx_overflow_buffer_pkt_high[0x20];
1934
1935         u8         tx_overflow_buffer_pkt_low[0x20];
1936
1937         u8         outbound_stalled_reads[0x20];
1938
1939         u8         outbound_stalled_writes[0x20];
1940
1941         u8         outbound_stalled_reads_events[0x20];
1942
1943         u8         outbound_stalled_writes_events[0x20];
1944
1945         u8         reserved_at_200[0x5c0];
1946 };
1947
1948 struct mlx5_ifc_cmd_inter_comp_event_bits {
1949         u8         command_completion_vector[0x20];
1950
1951         u8         reserved_at_20[0xc0];
1952 };
1953
1954 struct mlx5_ifc_stall_vl_event_bits {
1955         u8         reserved_at_0[0x18];
1956         u8         port_num[0x1];
1957         u8         reserved_at_19[0x3];
1958         u8         vl[0x4];
1959
1960         u8         reserved_at_20[0xa0];
1961 };
1962
1963 struct mlx5_ifc_db_bf_congestion_event_bits {
1964         u8         event_subtype[0x8];
1965         u8         reserved_at_8[0x8];
1966         u8         congestion_level[0x8];
1967         u8         reserved_at_18[0x8];
1968
1969         u8         reserved_at_20[0xa0];
1970 };
1971
1972 struct mlx5_ifc_gpio_event_bits {
1973         u8         reserved_at_0[0x60];
1974
1975         u8         gpio_event_hi[0x20];
1976
1977         u8         gpio_event_lo[0x20];
1978
1979         u8         reserved_at_a0[0x40];
1980 };
1981
1982 struct mlx5_ifc_port_state_change_event_bits {
1983         u8         reserved_at_0[0x40];
1984
1985         u8         port_num[0x4];
1986         u8         reserved_at_44[0x1c];
1987
1988         u8         reserved_at_60[0x80];
1989 };
1990
1991 struct mlx5_ifc_dropped_packet_logged_bits {
1992         u8         reserved_at_0[0xe0];
1993 };
1994
1995 enum {
1996         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1997         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1998 };
1999
2000 struct mlx5_ifc_cq_error_bits {
2001         u8         reserved_at_0[0x8];
2002         u8         cqn[0x18];
2003
2004         u8         reserved_at_20[0x20];
2005
2006         u8         reserved_at_40[0x18];
2007         u8         syndrome[0x8];
2008
2009         u8         reserved_at_60[0x80];
2010 };
2011
2012 struct mlx5_ifc_rdma_page_fault_event_bits {
2013         u8         bytes_committed[0x20];
2014
2015         u8         r_key[0x20];
2016
2017         u8         reserved_at_40[0x10];
2018         u8         packet_len[0x10];
2019
2020         u8         rdma_op_len[0x20];
2021
2022         u8         rdma_va[0x40];
2023
2024         u8         reserved_at_c0[0x5];
2025         u8         rdma[0x1];
2026         u8         write[0x1];
2027         u8         requestor[0x1];
2028         u8         qp_number[0x18];
2029 };
2030
2031 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2032         u8         bytes_committed[0x20];
2033
2034         u8         reserved_at_20[0x10];
2035         u8         wqe_index[0x10];
2036
2037         u8         reserved_at_40[0x10];
2038         u8         len[0x10];
2039
2040         u8         reserved_at_60[0x60];
2041
2042         u8         reserved_at_c0[0x5];
2043         u8         rdma[0x1];
2044         u8         write_read[0x1];
2045         u8         requestor[0x1];
2046         u8         qpn[0x18];
2047 };
2048
2049 struct mlx5_ifc_qp_events_bits {
2050         u8         reserved_at_0[0xa0];
2051
2052         u8         type[0x8];
2053         u8         reserved_at_a8[0x18];
2054
2055         u8         reserved_at_c0[0x8];
2056         u8         qpn_rqn_sqn[0x18];
2057 };
2058
2059 struct mlx5_ifc_dct_events_bits {
2060         u8         reserved_at_0[0xc0];
2061
2062         u8         reserved_at_c0[0x8];
2063         u8         dct_number[0x18];
2064 };
2065
2066 struct mlx5_ifc_comp_event_bits {
2067         u8         reserved_at_0[0xc0];
2068
2069         u8         reserved_at_c0[0x8];
2070         u8         cq_number[0x18];
2071 };
2072
2073 enum {
2074         MLX5_QPC_STATE_RST        = 0x0,
2075         MLX5_QPC_STATE_INIT       = 0x1,
2076         MLX5_QPC_STATE_RTR        = 0x2,
2077         MLX5_QPC_STATE_RTS        = 0x3,
2078         MLX5_QPC_STATE_SQER       = 0x4,
2079         MLX5_QPC_STATE_ERR        = 0x6,
2080         MLX5_QPC_STATE_SQD        = 0x7,
2081         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2082 };
2083
2084 enum {
2085         MLX5_QPC_ST_RC            = 0x0,
2086         MLX5_QPC_ST_UC            = 0x1,
2087         MLX5_QPC_ST_UD            = 0x2,
2088         MLX5_QPC_ST_XRC           = 0x3,
2089         MLX5_QPC_ST_DCI           = 0x5,
2090         MLX5_QPC_ST_QP0           = 0x7,
2091         MLX5_QPC_ST_QP1           = 0x8,
2092         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2093         MLX5_QPC_ST_REG_UMR       = 0xc,
2094 };
2095
2096 enum {
2097         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2098         MLX5_QPC_PM_STATE_REARM     = 0x1,
2099         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2100         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2101 };
2102
2103 enum {
2104         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2105 };
2106
2107 enum {
2108         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2109         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2110 };
2111
2112 enum {
2113         MLX5_QPC_MTU_256_BYTES        = 0x1,
2114         MLX5_QPC_MTU_512_BYTES        = 0x2,
2115         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2116         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2117         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2118         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2119 };
2120
2121 enum {
2122         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2123         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2124         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2125         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2126         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2127         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2128         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2129         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2130 };
2131
2132 enum {
2133         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2134         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2135         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2136 };
2137
2138 enum {
2139         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2140         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2141         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2142 };
2143
2144 struct mlx5_ifc_qpc_bits {
2145         u8         state[0x4];
2146         u8         lag_tx_port_affinity[0x4];
2147         u8         st[0x8];
2148         u8         reserved_at_10[0x3];
2149         u8         pm_state[0x2];
2150         u8         reserved_at_15[0x3];
2151         u8         offload_type[0x4];
2152         u8         end_padding_mode[0x2];
2153         u8         reserved_at_1e[0x2];
2154
2155         u8         wq_signature[0x1];
2156         u8         block_lb_mc[0x1];
2157         u8         atomic_like_write_en[0x1];
2158         u8         latency_sensitive[0x1];
2159         u8         reserved_at_24[0x1];
2160         u8         drain_sigerr[0x1];
2161         u8         reserved_at_26[0x2];
2162         u8         pd[0x18];
2163
2164         u8         mtu[0x3];
2165         u8         log_msg_max[0x5];
2166         u8         reserved_at_48[0x1];
2167         u8         log_rq_size[0x4];
2168         u8         log_rq_stride[0x3];
2169         u8         no_sq[0x1];
2170         u8         log_sq_size[0x4];
2171         u8         reserved_at_55[0x6];
2172         u8         rlky[0x1];
2173         u8         ulp_stateless_offload_mode[0x4];
2174
2175         u8         counter_set_id[0x8];
2176         u8         uar_page[0x18];
2177
2178         u8         reserved_at_80[0x8];
2179         u8         user_index[0x18];
2180
2181         u8         reserved_at_a0[0x3];
2182         u8         log_page_size[0x5];
2183         u8         remote_qpn[0x18];
2184
2185         struct mlx5_ifc_ads_bits primary_address_path;
2186
2187         struct mlx5_ifc_ads_bits secondary_address_path;
2188
2189         u8         log_ack_req_freq[0x4];
2190         u8         reserved_at_384[0x4];
2191         u8         log_sra_max[0x3];
2192         u8         reserved_at_38b[0x2];
2193         u8         retry_count[0x3];
2194         u8         rnr_retry[0x3];
2195         u8         reserved_at_393[0x1];
2196         u8         fre[0x1];
2197         u8         cur_rnr_retry[0x3];
2198         u8         cur_retry_count[0x3];
2199         u8         reserved_at_39b[0x5];
2200
2201         u8         reserved_at_3a0[0x20];
2202
2203         u8         reserved_at_3c0[0x8];
2204         u8         next_send_psn[0x18];
2205
2206         u8         reserved_at_3e0[0x8];
2207         u8         cqn_snd[0x18];
2208
2209         u8         reserved_at_400[0x8];
2210         u8         deth_sqpn[0x18];
2211
2212         u8         reserved_at_420[0x20];
2213
2214         u8         reserved_at_440[0x8];
2215         u8         last_acked_psn[0x18];
2216
2217         u8         reserved_at_460[0x8];
2218         u8         ssn[0x18];
2219
2220         u8         reserved_at_480[0x8];
2221         u8         log_rra_max[0x3];
2222         u8         reserved_at_48b[0x1];
2223         u8         atomic_mode[0x4];
2224         u8         rre[0x1];
2225         u8         rwe[0x1];
2226         u8         rae[0x1];
2227         u8         reserved_at_493[0x1];
2228         u8         page_offset[0x6];
2229         u8         reserved_at_49a[0x3];
2230         u8         cd_slave_receive[0x1];
2231         u8         cd_slave_send[0x1];
2232         u8         cd_master[0x1];
2233
2234         u8         reserved_at_4a0[0x3];
2235         u8         min_rnr_nak[0x5];
2236         u8         next_rcv_psn[0x18];
2237
2238         u8         reserved_at_4c0[0x8];
2239         u8         xrcd[0x18];
2240
2241         u8         reserved_at_4e0[0x8];
2242         u8         cqn_rcv[0x18];
2243
2244         u8         dbr_addr[0x40];
2245
2246         u8         q_key[0x20];
2247
2248         u8         reserved_at_560[0x5];
2249         u8         rq_type[0x3];
2250         u8         srqn_rmpn_xrqn[0x18];
2251
2252         u8         reserved_at_580[0x8];
2253         u8         rmsn[0x18];
2254
2255         u8         hw_sq_wqebb_counter[0x10];
2256         u8         sw_sq_wqebb_counter[0x10];
2257
2258         u8         hw_rq_counter[0x20];
2259
2260         u8         sw_rq_counter[0x20];
2261
2262         u8         reserved_at_600[0x20];
2263
2264         u8         reserved_at_620[0xf];
2265         u8         cgs[0x1];
2266         u8         cs_req[0x8];
2267         u8         cs_res[0x8];
2268
2269         u8         dc_access_key[0x40];
2270
2271         u8         reserved_at_680[0xc0];
2272 };
2273
2274 struct mlx5_ifc_roce_addr_layout_bits {
2275         u8         source_l3_address[16][0x8];
2276
2277         u8         reserved_at_80[0x3];
2278         u8         vlan_valid[0x1];
2279         u8         vlan_id[0xc];
2280         u8         source_mac_47_32[0x10];
2281
2282         u8         source_mac_31_0[0x20];
2283
2284         u8         reserved_at_c0[0x14];
2285         u8         roce_l3_type[0x4];
2286         u8         roce_version[0x8];
2287
2288         u8         reserved_at_e0[0x20];
2289 };
2290
2291 union mlx5_ifc_hca_cap_union_bits {
2292         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2293         struct mlx5_ifc_odp_cap_bits odp_cap;
2294         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2295         struct mlx5_ifc_roce_cap_bits roce_cap;
2296         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2297         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2298         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2299         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2300         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2301         struct mlx5_ifc_qos_cap_bits qos_cap;
2302         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2303         u8         reserved_at_0[0x8000];
2304 };
2305
2306 enum {
2307         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2308         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2309         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2310         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2311         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2312         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2313         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2314 };
2315
2316 struct mlx5_ifc_flow_context_bits {
2317         u8         reserved_at_0[0x20];
2318
2319         u8         group_id[0x20];
2320
2321         u8         reserved_at_40[0x8];
2322         u8         flow_tag[0x18];
2323
2324         u8         reserved_at_60[0x10];
2325         u8         action[0x10];
2326
2327         u8         reserved_at_80[0x8];
2328         u8         destination_list_size[0x18];
2329
2330         u8         reserved_at_a0[0x8];
2331         u8         flow_counter_list_size[0x18];
2332
2333         u8         encap_id[0x20];
2334
2335         u8         modify_header_id[0x20];
2336
2337         u8         reserved_at_100[0x100];
2338
2339         struct mlx5_ifc_fte_match_param_bits match_value;
2340
2341         u8         reserved_at_1200[0x600];
2342
2343         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2344 };
2345
2346 enum {
2347         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2348         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2349 };
2350
2351 struct mlx5_ifc_xrc_srqc_bits {
2352         u8         state[0x4];
2353         u8         log_xrc_srq_size[0x4];
2354         u8         reserved_at_8[0x18];
2355
2356         u8         wq_signature[0x1];
2357         u8         cont_srq[0x1];
2358         u8         reserved_at_22[0x1];
2359         u8         rlky[0x1];
2360         u8         basic_cyclic_rcv_wqe[0x1];
2361         u8         log_rq_stride[0x3];
2362         u8         xrcd[0x18];
2363
2364         u8         page_offset[0x6];
2365         u8         reserved_at_46[0x2];
2366         u8         cqn[0x18];
2367
2368         u8         reserved_at_60[0x20];
2369
2370         u8         user_index_equal_xrc_srqn[0x1];
2371         u8         reserved_at_81[0x1];
2372         u8         log_page_size[0x6];
2373         u8         user_index[0x18];
2374
2375         u8         reserved_at_a0[0x20];
2376
2377         u8         reserved_at_c0[0x8];
2378         u8         pd[0x18];
2379
2380         u8         lwm[0x10];
2381         u8         wqe_cnt[0x10];
2382
2383         u8         reserved_at_100[0x40];
2384
2385         u8         db_record_addr_h[0x20];
2386
2387         u8         db_record_addr_l[0x1e];
2388         u8         reserved_at_17e[0x2];
2389
2390         u8         reserved_at_180[0x80];
2391 };
2392
2393 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2394         u8         counter_error_queues[0x20];
2395
2396         u8         total_error_queues[0x20];
2397
2398         u8         send_queue_priority_update_flow[0x20];
2399
2400         u8         reserved_at_60[0x20];
2401
2402         u8         nic_receive_steering_discard[0x40];
2403
2404         u8         receive_discard_vport_down[0x40];
2405
2406         u8         transmit_discard_vport_down[0x40];
2407
2408         u8         reserved_at_140[0xec0];
2409 };
2410
2411 struct mlx5_ifc_traffic_counter_bits {
2412         u8         packets[0x40];
2413
2414         u8         octets[0x40];
2415 };
2416
2417 struct mlx5_ifc_tisc_bits {
2418         u8         strict_lag_tx_port_affinity[0x1];
2419         u8         reserved_at_1[0x3];
2420         u8         lag_tx_port_affinity[0x04];
2421
2422         u8         reserved_at_8[0x4];
2423         u8         prio[0x4];
2424         u8         reserved_at_10[0x10];
2425
2426         u8         reserved_at_20[0x100];
2427
2428         u8         reserved_at_120[0x8];
2429         u8         transport_domain[0x18];
2430
2431         u8         reserved_at_140[0x8];
2432         u8         underlay_qpn[0x18];
2433         u8         reserved_at_160[0x3a0];
2434 };
2435
2436 enum {
2437         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2438         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2439 };
2440
2441 enum {
2442         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2443         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2444 };
2445
2446 enum {
2447         MLX5_RX_HASH_FN_NONE           = 0x0,
2448         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2449         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2450 };
2451
2452 enum {
2453         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2454         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2455 };
2456
2457 struct mlx5_ifc_tirc_bits {
2458         u8         reserved_at_0[0x20];
2459
2460         u8         disp_type[0x4];
2461         u8         reserved_at_24[0x1c];
2462
2463         u8         reserved_at_40[0x40];
2464
2465         u8         reserved_at_80[0x4];
2466         u8         lro_timeout_period_usecs[0x10];
2467         u8         lro_enable_mask[0x4];
2468         u8         lro_max_ip_payload_size[0x8];
2469
2470         u8         reserved_at_a0[0x40];
2471
2472         u8         reserved_at_e0[0x8];
2473         u8         inline_rqn[0x18];
2474
2475         u8         rx_hash_symmetric[0x1];
2476         u8         reserved_at_101[0x1];
2477         u8         tunneled_offload_en[0x1];
2478         u8         reserved_at_103[0x5];
2479         u8         indirect_table[0x18];
2480
2481         u8         rx_hash_fn[0x4];
2482         u8         reserved_at_124[0x2];
2483         u8         self_lb_block[0x2];
2484         u8         transport_domain[0x18];
2485
2486         u8         rx_hash_toeplitz_key[10][0x20];
2487
2488         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2489
2490         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2491
2492         u8         reserved_at_2c0[0x4c0];
2493 };
2494
2495 enum {
2496         MLX5_SRQC_STATE_GOOD   = 0x0,
2497         MLX5_SRQC_STATE_ERROR  = 0x1,
2498 };
2499
2500 struct mlx5_ifc_srqc_bits {
2501         u8         state[0x4];
2502         u8         log_srq_size[0x4];
2503         u8         reserved_at_8[0x18];
2504
2505         u8         wq_signature[0x1];
2506         u8         cont_srq[0x1];
2507         u8         reserved_at_22[0x1];
2508         u8         rlky[0x1];
2509         u8         reserved_at_24[0x1];
2510         u8         log_rq_stride[0x3];
2511         u8         xrcd[0x18];
2512
2513         u8         page_offset[0x6];
2514         u8         reserved_at_46[0x2];
2515         u8         cqn[0x18];
2516
2517         u8         reserved_at_60[0x20];
2518
2519         u8         reserved_at_80[0x2];
2520         u8         log_page_size[0x6];
2521         u8         reserved_at_88[0x18];
2522
2523         u8         reserved_at_a0[0x20];
2524
2525         u8         reserved_at_c0[0x8];
2526         u8         pd[0x18];
2527
2528         u8         lwm[0x10];
2529         u8         wqe_cnt[0x10];
2530
2531         u8         reserved_at_100[0x40];
2532
2533         u8         dbr_addr[0x40];
2534
2535         u8         reserved_at_180[0x80];
2536 };
2537
2538 enum {
2539         MLX5_SQC_STATE_RST  = 0x0,
2540         MLX5_SQC_STATE_RDY  = 0x1,
2541         MLX5_SQC_STATE_ERR  = 0x3,
2542 };
2543
2544 struct mlx5_ifc_sqc_bits {
2545         u8         rlky[0x1];
2546         u8         cd_master[0x1];
2547         u8         fre[0x1];
2548         u8         flush_in_error_en[0x1];
2549         u8         allow_multi_pkt_send_wqe[0x1];
2550         u8         min_wqe_inline_mode[0x3];
2551         u8         state[0x4];
2552         u8         reg_umr[0x1];
2553         u8         allow_swp[0x1];
2554         u8         hairpin[0x1];
2555         u8         reserved_at_f[0x11];
2556
2557         u8         reserved_at_20[0x8];
2558         u8         user_index[0x18];
2559
2560         u8         reserved_at_40[0x8];
2561         u8         cqn[0x18];
2562
2563         u8         reserved_at_60[0x8];
2564         u8         hairpin_peer_rq[0x18];
2565
2566         u8         reserved_at_80[0x10];
2567         u8         hairpin_peer_vhca[0x10];
2568
2569         u8         reserved_at_a0[0x50];
2570
2571         u8         packet_pacing_rate_limit_index[0x10];
2572         u8         tis_lst_sz[0x10];
2573         u8         reserved_at_110[0x10];
2574
2575         u8         reserved_at_120[0x40];
2576
2577         u8         reserved_at_160[0x8];
2578         u8         tis_num_0[0x18];
2579
2580         struct mlx5_ifc_wq_bits wq;
2581 };
2582
2583 enum {
2584         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2585         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2586         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2587         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2588 };
2589
2590 struct mlx5_ifc_scheduling_context_bits {
2591         u8         element_type[0x8];
2592         u8         reserved_at_8[0x18];
2593
2594         u8         element_attributes[0x20];
2595
2596         u8         parent_element_id[0x20];
2597
2598         u8         reserved_at_60[0x40];
2599
2600         u8         bw_share[0x20];
2601
2602         u8         max_average_bw[0x20];
2603
2604         u8         reserved_at_e0[0x120];
2605 };
2606
2607 struct mlx5_ifc_rqtc_bits {
2608         u8         reserved_at_0[0xa0];
2609
2610         u8         reserved_at_a0[0x10];
2611         u8         rqt_max_size[0x10];
2612
2613         u8         reserved_at_c0[0x10];
2614         u8         rqt_actual_size[0x10];
2615
2616         u8         reserved_at_e0[0x6a0];
2617
2618         struct mlx5_ifc_rq_num_bits rq_num[0];
2619 };
2620
2621 enum {
2622         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2623         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2624 };
2625
2626 enum {
2627         MLX5_RQC_STATE_RST  = 0x0,
2628         MLX5_RQC_STATE_RDY  = 0x1,
2629         MLX5_RQC_STATE_ERR  = 0x3,
2630 };
2631
2632 struct mlx5_ifc_rqc_bits {
2633         u8         rlky[0x1];
2634         u8         delay_drop_en[0x1];
2635         u8         scatter_fcs[0x1];
2636         u8         vsd[0x1];
2637         u8         mem_rq_type[0x4];
2638         u8         state[0x4];
2639         u8         reserved_at_c[0x1];
2640         u8         flush_in_error_en[0x1];
2641         u8         hairpin[0x1];
2642         u8         reserved_at_f[0x11];
2643
2644         u8         reserved_at_20[0x8];
2645         u8         user_index[0x18];
2646
2647         u8         reserved_at_40[0x8];
2648         u8         cqn[0x18];
2649
2650         u8         counter_set_id[0x8];
2651         u8         reserved_at_68[0x18];
2652
2653         u8         reserved_at_80[0x8];
2654         u8         rmpn[0x18];
2655
2656         u8         reserved_at_a0[0x8];
2657         u8         hairpin_peer_sq[0x18];
2658
2659         u8         reserved_at_c0[0x10];
2660         u8         hairpin_peer_vhca[0x10];
2661
2662         u8         reserved_at_e0[0xa0];
2663
2664         struct mlx5_ifc_wq_bits wq;
2665 };
2666
2667 enum {
2668         MLX5_RMPC_STATE_RDY  = 0x1,
2669         MLX5_RMPC_STATE_ERR  = 0x3,
2670 };
2671
2672 struct mlx5_ifc_rmpc_bits {
2673         u8         reserved_at_0[0x8];
2674         u8         state[0x4];
2675         u8         reserved_at_c[0x14];
2676
2677         u8         basic_cyclic_rcv_wqe[0x1];
2678         u8         reserved_at_21[0x1f];
2679
2680         u8         reserved_at_40[0x140];
2681
2682         struct mlx5_ifc_wq_bits wq;
2683 };
2684
2685 struct mlx5_ifc_nic_vport_context_bits {
2686         u8         reserved_at_0[0x5];
2687         u8         min_wqe_inline_mode[0x3];
2688         u8         reserved_at_8[0x15];
2689         u8         disable_mc_local_lb[0x1];
2690         u8         disable_uc_local_lb[0x1];
2691         u8         roce_en[0x1];
2692
2693         u8         arm_change_event[0x1];
2694         u8         reserved_at_21[0x1a];
2695         u8         event_on_mtu[0x1];
2696         u8         event_on_promisc_change[0x1];
2697         u8         event_on_vlan_change[0x1];
2698         u8         event_on_mc_address_change[0x1];
2699         u8         event_on_uc_address_change[0x1];
2700
2701         u8         reserved_at_40[0xc];
2702
2703         u8         affiliation_criteria[0x4];
2704         u8         affiliated_vhca_id[0x10];
2705
2706         u8         reserved_at_60[0xd0];
2707
2708         u8         mtu[0x10];
2709
2710         u8         system_image_guid[0x40];
2711         u8         port_guid[0x40];
2712         u8         node_guid[0x40];
2713
2714         u8         reserved_at_200[0x140];
2715         u8         qkey_violation_counter[0x10];
2716         u8         reserved_at_350[0x430];
2717
2718         u8         promisc_uc[0x1];
2719         u8         promisc_mc[0x1];
2720         u8         promisc_all[0x1];
2721         u8         reserved_at_783[0x2];
2722         u8         allowed_list_type[0x3];
2723         u8         reserved_at_788[0xc];
2724         u8         allowed_list_size[0xc];
2725
2726         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2727
2728         u8         reserved_at_7e0[0x20];
2729
2730         u8         current_uc_mac_address[0][0x40];
2731 };
2732
2733 enum {
2734         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2735         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2736         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2737         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2738 };
2739
2740 struct mlx5_ifc_mkc_bits {
2741         u8         reserved_at_0[0x1];
2742         u8         free[0x1];
2743         u8         reserved_at_2[0xd];
2744         u8         small_fence_on_rdma_read_response[0x1];
2745         u8         umr_en[0x1];
2746         u8         a[0x1];
2747         u8         rw[0x1];
2748         u8         rr[0x1];
2749         u8         lw[0x1];
2750         u8         lr[0x1];
2751         u8         access_mode[0x2];
2752         u8         reserved_at_18[0x8];
2753
2754         u8         qpn[0x18];
2755         u8         mkey_7_0[0x8];
2756
2757         u8         reserved_at_40[0x20];
2758
2759         u8         length64[0x1];
2760         u8         bsf_en[0x1];
2761         u8         sync_umr[0x1];
2762         u8         reserved_at_63[0x2];
2763         u8         expected_sigerr_count[0x1];
2764         u8         reserved_at_66[0x1];
2765         u8         en_rinval[0x1];
2766         u8         pd[0x18];
2767
2768         u8         start_addr[0x40];
2769
2770         u8         len[0x40];
2771
2772         u8         bsf_octword_size[0x20];
2773
2774         u8         reserved_at_120[0x80];
2775
2776         u8         translations_octword_size[0x20];
2777
2778         u8         reserved_at_1c0[0x1b];
2779         u8         log_page_size[0x5];
2780
2781         u8         reserved_at_1e0[0x20];
2782 };
2783
2784 struct mlx5_ifc_pkey_bits {
2785         u8         reserved_at_0[0x10];
2786         u8         pkey[0x10];
2787 };
2788
2789 struct mlx5_ifc_array128_auto_bits {
2790         u8         array128_auto[16][0x8];
2791 };
2792
2793 struct mlx5_ifc_hca_vport_context_bits {
2794         u8         field_select[0x20];
2795
2796         u8         reserved_at_20[0xe0];
2797
2798         u8         sm_virt_aware[0x1];
2799         u8         has_smi[0x1];
2800         u8         has_raw[0x1];
2801         u8         grh_required[0x1];
2802         u8         reserved_at_104[0xc];
2803         u8         port_physical_state[0x4];
2804         u8         vport_state_policy[0x4];
2805         u8         port_state[0x4];
2806         u8         vport_state[0x4];
2807
2808         u8         reserved_at_120[0x20];
2809
2810         u8         system_image_guid[0x40];
2811
2812         u8         port_guid[0x40];
2813
2814         u8         node_guid[0x40];
2815
2816         u8         cap_mask1[0x20];
2817
2818         u8         cap_mask1_field_select[0x20];
2819
2820         u8         cap_mask2[0x20];
2821
2822         u8         cap_mask2_field_select[0x20];
2823
2824         u8         reserved_at_280[0x80];
2825
2826         u8         lid[0x10];
2827         u8         reserved_at_310[0x4];
2828         u8         init_type_reply[0x4];
2829         u8         lmc[0x3];
2830         u8         subnet_timeout[0x5];
2831
2832         u8         sm_lid[0x10];
2833         u8         sm_sl[0x4];
2834         u8         reserved_at_334[0xc];
2835
2836         u8         qkey_violation_counter[0x10];
2837         u8         pkey_violation_counter[0x10];
2838
2839         u8         reserved_at_360[0xca0];
2840 };
2841
2842 struct mlx5_ifc_esw_vport_context_bits {
2843         u8         reserved_at_0[0x3];
2844         u8         vport_svlan_strip[0x1];
2845         u8         vport_cvlan_strip[0x1];
2846         u8         vport_svlan_insert[0x1];
2847         u8         vport_cvlan_insert[0x2];
2848         u8         reserved_at_8[0x18];
2849
2850         u8         reserved_at_20[0x20];
2851
2852         u8         svlan_cfi[0x1];
2853         u8         svlan_pcp[0x3];
2854         u8         svlan_id[0xc];
2855         u8         cvlan_cfi[0x1];
2856         u8         cvlan_pcp[0x3];
2857         u8         cvlan_id[0xc];
2858
2859         u8         reserved_at_60[0x7a0];
2860 };
2861
2862 enum {
2863         MLX5_EQC_STATUS_OK                = 0x0,
2864         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2865 };
2866
2867 enum {
2868         MLX5_EQC_ST_ARMED  = 0x9,
2869         MLX5_EQC_ST_FIRED  = 0xa,
2870 };
2871
2872 struct mlx5_ifc_eqc_bits {
2873         u8         status[0x4];
2874         u8         reserved_at_4[0x9];
2875         u8         ec[0x1];
2876         u8         oi[0x1];
2877         u8         reserved_at_f[0x5];
2878         u8         st[0x4];
2879         u8         reserved_at_18[0x8];
2880
2881         u8         reserved_at_20[0x20];
2882
2883         u8         reserved_at_40[0x14];
2884         u8         page_offset[0x6];
2885         u8         reserved_at_5a[0x6];
2886
2887         u8         reserved_at_60[0x3];
2888         u8         log_eq_size[0x5];
2889         u8         uar_page[0x18];
2890
2891         u8         reserved_at_80[0x20];
2892
2893         u8         reserved_at_a0[0x18];
2894         u8         intr[0x8];
2895
2896         u8         reserved_at_c0[0x3];
2897         u8         log_page_size[0x5];
2898         u8         reserved_at_c8[0x18];
2899
2900         u8         reserved_at_e0[0x60];
2901
2902         u8         reserved_at_140[0x8];
2903         u8         consumer_counter[0x18];
2904
2905         u8         reserved_at_160[0x8];
2906         u8         producer_counter[0x18];
2907
2908         u8         reserved_at_180[0x80];
2909 };
2910
2911 enum {
2912         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2913         MLX5_DCTC_STATE_DRAINING  = 0x1,
2914         MLX5_DCTC_STATE_DRAINED   = 0x2,
2915 };
2916
2917 enum {
2918         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2919         MLX5_DCTC_CS_RES_NA         = 0x1,
2920         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2921 };
2922
2923 enum {
2924         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2925         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2926         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2927         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2928         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2929 };
2930
2931 struct mlx5_ifc_dctc_bits {
2932         u8         reserved_at_0[0x4];
2933         u8         state[0x4];
2934         u8         reserved_at_8[0x18];
2935
2936         u8         reserved_at_20[0x8];
2937         u8         user_index[0x18];
2938
2939         u8         reserved_at_40[0x8];
2940         u8         cqn[0x18];
2941
2942         u8         counter_set_id[0x8];
2943         u8         atomic_mode[0x4];
2944         u8         rre[0x1];
2945         u8         rwe[0x1];
2946         u8         rae[0x1];
2947         u8         atomic_like_write_en[0x1];
2948         u8         latency_sensitive[0x1];
2949         u8         rlky[0x1];
2950         u8         free_ar[0x1];
2951         u8         reserved_at_73[0xd];
2952
2953         u8         reserved_at_80[0x8];
2954         u8         cs_res[0x8];
2955         u8         reserved_at_90[0x3];
2956         u8         min_rnr_nak[0x5];
2957         u8         reserved_at_98[0x8];
2958
2959         u8         reserved_at_a0[0x8];
2960         u8         srqn_xrqn[0x18];
2961
2962         u8         reserved_at_c0[0x8];
2963         u8         pd[0x18];
2964
2965         u8         tclass[0x8];
2966         u8         reserved_at_e8[0x4];
2967         u8         flow_label[0x14];
2968
2969         u8         dc_access_key[0x40];
2970
2971         u8         reserved_at_140[0x5];
2972         u8         mtu[0x3];
2973         u8         port[0x8];
2974         u8         pkey_index[0x10];
2975
2976         u8         reserved_at_160[0x8];
2977         u8         my_addr_index[0x8];
2978         u8         reserved_at_170[0x8];
2979         u8         hop_limit[0x8];
2980
2981         u8         dc_access_key_violation_count[0x20];
2982
2983         u8         reserved_at_1a0[0x14];
2984         u8         dei_cfi[0x1];
2985         u8         eth_prio[0x3];
2986         u8         ecn[0x2];
2987         u8         dscp[0x6];
2988
2989         u8         reserved_at_1c0[0x40];
2990 };
2991
2992 enum {
2993         MLX5_CQC_STATUS_OK             = 0x0,
2994         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2995         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2996 };
2997
2998 enum {
2999         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3000         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3001 };
3002
3003 enum {
3004         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3005         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3006         MLX5_CQC_ST_FIRED                                 = 0xa,
3007 };
3008
3009 enum {
3010         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3011         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3012         MLX5_CQ_PERIOD_NUM_MODES
3013 };
3014
3015 struct mlx5_ifc_cqc_bits {
3016         u8         status[0x4];
3017         u8         reserved_at_4[0x4];
3018         u8         cqe_sz[0x3];
3019         u8         cc[0x1];
3020         u8         reserved_at_c[0x1];
3021         u8         scqe_break_moderation_en[0x1];
3022         u8         oi[0x1];
3023         u8         cq_period_mode[0x2];
3024         u8         cqe_comp_en[0x1];
3025         u8         mini_cqe_res_format[0x2];
3026         u8         st[0x4];
3027         u8         reserved_at_18[0x8];
3028
3029         u8         reserved_at_20[0x20];
3030
3031         u8         reserved_at_40[0x14];
3032         u8         page_offset[0x6];
3033         u8         reserved_at_5a[0x6];
3034
3035         u8         reserved_at_60[0x3];
3036         u8         log_cq_size[0x5];
3037         u8         uar_page[0x18];
3038
3039         u8         reserved_at_80[0x4];
3040         u8         cq_period[0xc];
3041         u8         cq_max_count[0x10];
3042
3043         u8         reserved_at_a0[0x18];
3044         u8         c_eqn[0x8];
3045
3046         u8         reserved_at_c0[0x3];
3047         u8         log_page_size[0x5];
3048         u8         reserved_at_c8[0x18];
3049
3050         u8         reserved_at_e0[0x20];
3051
3052         u8         reserved_at_100[0x8];
3053         u8         last_notified_index[0x18];
3054
3055         u8         reserved_at_120[0x8];
3056         u8         last_solicit_index[0x18];
3057
3058         u8         reserved_at_140[0x8];
3059         u8         consumer_counter[0x18];
3060
3061         u8         reserved_at_160[0x8];
3062         u8         producer_counter[0x18];
3063
3064         u8         reserved_at_180[0x40];
3065
3066         u8         dbr_addr[0x40];
3067 };
3068
3069 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3070         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3071         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3072         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3073         u8         reserved_at_0[0x800];
3074 };
3075
3076 struct mlx5_ifc_query_adapter_param_block_bits {
3077         u8         reserved_at_0[0xc0];
3078
3079         u8         reserved_at_c0[0x8];
3080         u8         ieee_vendor_id[0x18];
3081
3082         u8         reserved_at_e0[0x10];
3083         u8         vsd_vendor_id[0x10];
3084
3085         u8         vsd[208][0x8];
3086
3087         u8         vsd_contd_psid[16][0x8];
3088 };
3089
3090 enum {
3091         MLX5_XRQC_STATE_GOOD   = 0x0,
3092         MLX5_XRQC_STATE_ERROR  = 0x1,
3093 };
3094
3095 enum {
3096         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3097         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3098 };
3099
3100 enum {
3101         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3102 };
3103
3104 struct mlx5_ifc_tag_matching_topology_context_bits {
3105         u8         log_matching_list_sz[0x4];
3106         u8         reserved_at_4[0xc];
3107         u8         append_next_index[0x10];
3108
3109         u8         sw_phase_cnt[0x10];
3110         u8         hw_phase_cnt[0x10];
3111
3112         u8         reserved_at_40[0x40];
3113 };
3114
3115 struct mlx5_ifc_xrqc_bits {
3116         u8         state[0x4];
3117         u8         rlkey[0x1];
3118         u8         reserved_at_5[0xf];
3119         u8         topology[0x4];
3120         u8         reserved_at_18[0x4];
3121         u8         offload[0x4];
3122
3123         u8         reserved_at_20[0x8];
3124         u8         user_index[0x18];
3125
3126         u8         reserved_at_40[0x8];
3127         u8         cqn[0x18];
3128
3129         u8         reserved_at_60[0xa0];
3130
3131         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3132
3133         u8         reserved_at_180[0x280];
3134
3135         struct mlx5_ifc_wq_bits wq;
3136 };
3137
3138 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3139         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3140         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3141         u8         reserved_at_0[0x20];
3142 };
3143
3144 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3145         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3146         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3147         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3148         u8         reserved_at_0[0x20];
3149 };
3150
3151 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3152         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3153         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3154         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3155         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3156         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3157         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3158         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3159         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3160         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3161         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3162         u8         reserved_at_0[0x7c0];
3163 };
3164
3165 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3166         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3167         u8         reserved_at_0[0x7c0];
3168 };
3169
3170 union mlx5_ifc_event_auto_bits {
3171         struct mlx5_ifc_comp_event_bits comp_event;
3172         struct mlx5_ifc_dct_events_bits dct_events;
3173         struct mlx5_ifc_qp_events_bits qp_events;
3174         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3175         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3176         struct mlx5_ifc_cq_error_bits cq_error;
3177         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3178         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3179         struct mlx5_ifc_gpio_event_bits gpio_event;
3180         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3181         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3182         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3183         u8         reserved_at_0[0xe0];
3184 };
3185
3186 struct mlx5_ifc_health_buffer_bits {
3187         u8         reserved_at_0[0x100];
3188
3189         u8         assert_existptr[0x20];
3190
3191         u8         assert_callra[0x20];
3192
3193         u8         reserved_at_140[0x40];
3194
3195         u8         fw_version[0x20];
3196
3197         u8         hw_id[0x20];
3198
3199         u8         reserved_at_1c0[0x20];
3200
3201         u8         irisc_index[0x8];
3202         u8         synd[0x8];
3203         u8         ext_synd[0x10];
3204 };
3205
3206 struct mlx5_ifc_register_loopback_control_bits {
3207         u8         no_lb[0x1];
3208         u8         reserved_at_1[0x7];
3209         u8         port[0x8];
3210         u8         reserved_at_10[0x10];
3211
3212         u8         reserved_at_20[0x60];
3213 };
3214
3215 struct mlx5_ifc_vport_tc_element_bits {
3216         u8         traffic_class[0x4];
3217         u8         reserved_at_4[0xc];
3218         u8         vport_number[0x10];
3219 };
3220
3221 struct mlx5_ifc_vport_element_bits {
3222         u8         reserved_at_0[0x10];
3223         u8         vport_number[0x10];
3224 };
3225
3226 enum {
3227         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3228         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3229         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3230 };
3231
3232 struct mlx5_ifc_tsar_element_bits {
3233         u8         reserved_at_0[0x8];
3234         u8         tsar_type[0x8];
3235         u8         reserved_at_10[0x10];
3236 };
3237
3238 enum {
3239         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3240         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3241 };
3242
3243 struct mlx5_ifc_teardown_hca_out_bits {
3244         u8         status[0x8];
3245         u8         reserved_at_8[0x18];
3246
3247         u8         syndrome[0x20];
3248
3249         u8         reserved_at_40[0x3f];
3250
3251         u8         force_state[0x1];
3252 };
3253
3254 enum {
3255         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3256         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3257 };
3258
3259 struct mlx5_ifc_teardown_hca_in_bits {
3260         u8         opcode[0x10];
3261         u8         reserved_at_10[0x10];
3262
3263         u8         reserved_at_20[0x10];
3264         u8         op_mod[0x10];
3265
3266         u8         reserved_at_40[0x10];
3267         u8         profile[0x10];
3268
3269         u8         reserved_at_60[0x20];
3270 };
3271
3272 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3273         u8         status[0x8];
3274         u8         reserved_at_8[0x18];
3275
3276         u8         syndrome[0x20];
3277
3278         u8         reserved_at_40[0x40];
3279 };
3280
3281 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3282         u8         opcode[0x10];
3283         u8         reserved_at_10[0x10];
3284
3285         u8         reserved_at_20[0x10];
3286         u8         op_mod[0x10];
3287
3288         u8         reserved_at_40[0x8];
3289         u8         qpn[0x18];
3290
3291         u8         reserved_at_60[0x20];
3292
3293         u8         opt_param_mask[0x20];
3294
3295         u8         reserved_at_a0[0x20];
3296
3297         struct mlx5_ifc_qpc_bits qpc;
3298
3299         u8         reserved_at_800[0x80];
3300 };
3301
3302 struct mlx5_ifc_sqd2rts_qp_out_bits {
3303         u8         status[0x8];
3304         u8         reserved_at_8[0x18];
3305
3306         u8         syndrome[0x20];
3307
3308         u8         reserved_at_40[0x40];
3309 };
3310
3311 struct mlx5_ifc_sqd2rts_qp_in_bits {
3312         u8         opcode[0x10];
3313         u8         reserved_at_10[0x10];
3314
3315         u8         reserved_at_20[0x10];
3316         u8         op_mod[0x10];
3317
3318         u8         reserved_at_40[0x8];
3319         u8         qpn[0x18];
3320
3321         u8         reserved_at_60[0x20];
3322
3323         u8         opt_param_mask[0x20];
3324
3325         u8         reserved_at_a0[0x20];
3326
3327         struct mlx5_ifc_qpc_bits qpc;
3328
3329         u8         reserved_at_800[0x80];
3330 };
3331
3332 struct mlx5_ifc_set_roce_address_out_bits {
3333         u8         status[0x8];
3334         u8         reserved_at_8[0x18];
3335
3336         u8         syndrome[0x20];
3337
3338         u8         reserved_at_40[0x40];
3339 };
3340
3341 struct mlx5_ifc_set_roce_address_in_bits {
3342         u8         opcode[0x10];
3343         u8         reserved_at_10[0x10];
3344
3345         u8         reserved_at_20[0x10];
3346         u8         op_mod[0x10];
3347
3348         u8         roce_address_index[0x10];
3349         u8         reserved_at_50[0xc];
3350         u8         vhca_port_num[0x4];
3351
3352         u8         reserved_at_60[0x20];
3353
3354         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3355 };
3356
3357 struct mlx5_ifc_set_mad_demux_out_bits {
3358         u8         status[0x8];
3359         u8         reserved_at_8[0x18];
3360
3361         u8         syndrome[0x20];
3362
3363         u8         reserved_at_40[0x40];
3364 };
3365
3366 enum {
3367         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3368         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3369 };
3370
3371 struct mlx5_ifc_set_mad_demux_in_bits {
3372         u8         opcode[0x10];
3373         u8         reserved_at_10[0x10];
3374
3375         u8         reserved_at_20[0x10];
3376         u8         op_mod[0x10];
3377
3378         u8         reserved_at_40[0x20];
3379
3380         u8         reserved_at_60[0x6];
3381         u8         demux_mode[0x2];
3382         u8         reserved_at_68[0x18];
3383 };
3384
3385 struct mlx5_ifc_set_l2_table_entry_out_bits {
3386         u8         status[0x8];
3387         u8         reserved_at_8[0x18];
3388
3389         u8         syndrome[0x20];
3390
3391         u8         reserved_at_40[0x40];
3392 };
3393
3394 struct mlx5_ifc_set_l2_table_entry_in_bits {
3395         u8         opcode[0x10];
3396         u8         reserved_at_10[0x10];
3397
3398         u8         reserved_at_20[0x10];
3399         u8         op_mod[0x10];
3400
3401         u8         reserved_at_40[0x60];
3402
3403         u8         reserved_at_a0[0x8];
3404         u8         table_index[0x18];
3405
3406         u8         reserved_at_c0[0x20];
3407
3408         u8         reserved_at_e0[0x13];
3409         u8         vlan_valid[0x1];
3410         u8         vlan[0xc];
3411
3412         struct mlx5_ifc_mac_address_layout_bits mac_address;
3413
3414         u8         reserved_at_140[0xc0];
3415 };
3416
3417 struct mlx5_ifc_set_issi_out_bits {
3418         u8         status[0x8];
3419         u8         reserved_at_8[0x18];
3420
3421         u8         syndrome[0x20];
3422
3423         u8         reserved_at_40[0x40];
3424 };
3425
3426 struct mlx5_ifc_set_issi_in_bits {
3427         u8         opcode[0x10];
3428         u8         reserved_at_10[0x10];
3429
3430         u8         reserved_at_20[0x10];
3431         u8         op_mod[0x10];
3432
3433         u8         reserved_at_40[0x10];
3434         u8         current_issi[0x10];
3435
3436         u8         reserved_at_60[0x20];
3437 };
3438
3439 struct mlx5_ifc_set_hca_cap_out_bits {
3440         u8         status[0x8];
3441         u8         reserved_at_8[0x18];
3442
3443         u8         syndrome[0x20];
3444
3445         u8         reserved_at_40[0x40];
3446 };
3447
3448 struct mlx5_ifc_set_hca_cap_in_bits {
3449         u8         opcode[0x10];
3450         u8         reserved_at_10[0x10];
3451
3452         u8         reserved_at_20[0x10];
3453         u8         op_mod[0x10];
3454
3455         u8         reserved_at_40[0x40];
3456
3457         union mlx5_ifc_hca_cap_union_bits capability;
3458 };
3459
3460 enum {
3461         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3462         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3463         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3464         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3465 };
3466
3467 struct mlx5_ifc_set_fte_out_bits {
3468         u8         status[0x8];
3469         u8         reserved_at_8[0x18];
3470
3471         u8         syndrome[0x20];
3472
3473         u8         reserved_at_40[0x40];
3474 };
3475
3476 struct mlx5_ifc_set_fte_in_bits {
3477         u8         opcode[0x10];
3478         u8         reserved_at_10[0x10];
3479
3480         u8         reserved_at_20[0x10];
3481         u8         op_mod[0x10];
3482
3483         u8         other_vport[0x1];
3484         u8         reserved_at_41[0xf];
3485         u8         vport_number[0x10];
3486
3487         u8         reserved_at_60[0x20];
3488
3489         u8         table_type[0x8];
3490         u8         reserved_at_88[0x18];
3491
3492         u8         reserved_at_a0[0x8];
3493         u8         table_id[0x18];
3494
3495         u8         reserved_at_c0[0x18];
3496         u8         modify_enable_mask[0x8];
3497
3498         u8         reserved_at_e0[0x20];
3499
3500         u8         flow_index[0x20];
3501
3502         u8         reserved_at_120[0xe0];
3503
3504         struct mlx5_ifc_flow_context_bits flow_context;
3505 };
3506
3507 struct mlx5_ifc_rts2rts_qp_out_bits {
3508         u8         status[0x8];
3509         u8         reserved_at_8[0x18];
3510
3511         u8         syndrome[0x20];
3512
3513         u8         reserved_at_40[0x40];
3514 };
3515
3516 struct mlx5_ifc_rts2rts_qp_in_bits {
3517         u8         opcode[0x10];
3518         u8         reserved_at_10[0x10];
3519
3520         u8         reserved_at_20[0x10];
3521         u8         op_mod[0x10];
3522
3523         u8         reserved_at_40[0x8];
3524         u8         qpn[0x18];
3525
3526         u8         reserved_at_60[0x20];
3527
3528         u8         opt_param_mask[0x20];
3529
3530         u8         reserved_at_a0[0x20];
3531
3532         struct mlx5_ifc_qpc_bits qpc;
3533
3534         u8         reserved_at_800[0x80];
3535 };
3536
3537 struct mlx5_ifc_rtr2rts_qp_out_bits {
3538         u8         status[0x8];
3539         u8         reserved_at_8[0x18];
3540
3541         u8         syndrome[0x20];
3542
3543         u8         reserved_at_40[0x40];
3544 };
3545
3546 struct mlx5_ifc_rtr2rts_qp_in_bits {
3547         u8         opcode[0x10];
3548         u8         reserved_at_10[0x10];
3549
3550         u8         reserved_at_20[0x10];
3551         u8         op_mod[0x10];
3552
3553         u8         reserved_at_40[0x8];
3554         u8         qpn[0x18];
3555
3556         u8         reserved_at_60[0x20];
3557
3558         u8         opt_param_mask[0x20];
3559
3560         u8         reserved_at_a0[0x20];
3561
3562         struct mlx5_ifc_qpc_bits qpc;
3563
3564         u8         reserved_at_800[0x80];
3565 };
3566
3567 struct mlx5_ifc_rst2init_qp_out_bits {
3568         u8         status[0x8];
3569         u8         reserved_at_8[0x18];
3570
3571         u8         syndrome[0x20];
3572
3573         u8         reserved_at_40[0x40];
3574 };
3575
3576 struct mlx5_ifc_rst2init_qp_in_bits {
3577         u8         opcode[0x10];
3578         u8         reserved_at_10[0x10];
3579
3580         u8         reserved_at_20[0x10];
3581         u8         op_mod[0x10];
3582
3583         u8         reserved_at_40[0x8];
3584         u8         qpn[0x18];
3585
3586         u8         reserved_at_60[0x20];
3587
3588         u8         opt_param_mask[0x20];
3589
3590         u8         reserved_at_a0[0x20];
3591
3592         struct mlx5_ifc_qpc_bits qpc;
3593
3594         u8         reserved_at_800[0x80];
3595 };
3596
3597 struct mlx5_ifc_query_xrq_out_bits {
3598         u8         status[0x8];
3599         u8         reserved_at_8[0x18];
3600
3601         u8         syndrome[0x20];
3602
3603         u8         reserved_at_40[0x40];
3604
3605         struct mlx5_ifc_xrqc_bits xrq_context;
3606 };
3607
3608 struct mlx5_ifc_query_xrq_in_bits {
3609         u8         opcode[0x10];
3610         u8         reserved_at_10[0x10];
3611
3612         u8         reserved_at_20[0x10];
3613         u8         op_mod[0x10];
3614
3615         u8         reserved_at_40[0x8];
3616         u8         xrqn[0x18];
3617
3618         u8         reserved_at_60[0x20];
3619 };
3620
3621 struct mlx5_ifc_query_xrc_srq_out_bits {
3622         u8         status[0x8];
3623         u8         reserved_at_8[0x18];
3624
3625         u8         syndrome[0x20];
3626
3627         u8         reserved_at_40[0x40];
3628
3629         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3630
3631         u8         reserved_at_280[0x600];
3632
3633         u8         pas[0][0x40];
3634 };
3635
3636 struct mlx5_ifc_query_xrc_srq_in_bits {
3637         u8         opcode[0x10];
3638         u8         reserved_at_10[0x10];
3639
3640         u8         reserved_at_20[0x10];
3641         u8         op_mod[0x10];
3642
3643         u8         reserved_at_40[0x8];
3644         u8         xrc_srqn[0x18];
3645
3646         u8         reserved_at_60[0x20];
3647 };
3648
3649 enum {
3650         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3651         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3652 };
3653
3654 struct mlx5_ifc_query_vport_state_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_at_8[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_at_40[0x20];
3661
3662         u8         reserved_at_60[0x18];
3663         u8         admin_state[0x4];
3664         u8         state[0x4];
3665 };
3666
3667 enum {
3668         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3669         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3670 };
3671
3672 struct mlx5_ifc_query_vport_state_in_bits {
3673         u8         opcode[0x10];
3674         u8         reserved_at_10[0x10];
3675
3676         u8         reserved_at_20[0x10];
3677         u8         op_mod[0x10];
3678
3679         u8         other_vport[0x1];
3680         u8         reserved_at_41[0xf];
3681         u8         vport_number[0x10];
3682
3683         u8         reserved_at_60[0x20];
3684 };
3685
3686 struct mlx5_ifc_query_vnic_env_out_bits {
3687         u8         status[0x8];
3688         u8         reserved_at_8[0x18];
3689
3690         u8         syndrome[0x20];
3691
3692         u8         reserved_at_40[0x40];
3693
3694         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3695 };
3696
3697 enum {
3698         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3699 };
3700
3701 struct mlx5_ifc_query_vnic_env_in_bits {
3702         u8         opcode[0x10];
3703         u8         reserved_at_10[0x10];
3704
3705         u8         reserved_at_20[0x10];
3706         u8         op_mod[0x10];
3707
3708         u8         other_vport[0x1];
3709         u8         reserved_at_41[0xf];
3710         u8         vport_number[0x10];
3711
3712         u8         reserved_at_60[0x20];
3713 };
3714
3715 struct mlx5_ifc_query_vport_counter_out_bits {
3716         u8         status[0x8];
3717         u8         reserved_at_8[0x18];
3718
3719         u8         syndrome[0x20];
3720
3721         u8         reserved_at_40[0x40];
3722
3723         struct mlx5_ifc_traffic_counter_bits received_errors;
3724
3725         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3726
3727         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3728
3729         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3730
3731         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3732
3733         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3734
3735         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3736
3737         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3738
3739         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3740
3741         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3742
3743         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3744
3745         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3746
3747         u8         reserved_at_680[0xa00];
3748 };
3749
3750 enum {
3751         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3752 };
3753
3754 struct mlx5_ifc_query_vport_counter_in_bits {
3755         u8         opcode[0x10];
3756         u8         reserved_at_10[0x10];
3757
3758         u8         reserved_at_20[0x10];
3759         u8         op_mod[0x10];
3760
3761         u8         other_vport[0x1];
3762         u8         reserved_at_41[0xb];
3763         u8         port_num[0x4];
3764         u8         vport_number[0x10];
3765
3766         u8         reserved_at_60[0x60];
3767
3768         u8         clear[0x1];
3769         u8         reserved_at_c1[0x1f];
3770
3771         u8         reserved_at_e0[0x20];
3772 };
3773
3774 struct mlx5_ifc_query_tis_out_bits {
3775         u8         status[0x8];
3776         u8         reserved_at_8[0x18];
3777
3778         u8         syndrome[0x20];
3779
3780         u8         reserved_at_40[0x40];
3781
3782         struct mlx5_ifc_tisc_bits tis_context;
3783 };
3784
3785 struct mlx5_ifc_query_tis_in_bits {
3786         u8         opcode[0x10];
3787         u8         reserved_at_10[0x10];
3788
3789         u8         reserved_at_20[0x10];
3790         u8         op_mod[0x10];
3791
3792         u8         reserved_at_40[0x8];
3793         u8         tisn[0x18];
3794
3795         u8         reserved_at_60[0x20];
3796 };
3797
3798 struct mlx5_ifc_query_tir_out_bits {
3799         u8         status[0x8];
3800         u8         reserved_at_8[0x18];
3801
3802         u8         syndrome[0x20];
3803
3804         u8         reserved_at_40[0xc0];
3805
3806         struct mlx5_ifc_tirc_bits tir_context;
3807 };
3808
3809 struct mlx5_ifc_query_tir_in_bits {
3810         u8         opcode[0x10];
3811         u8         reserved_at_10[0x10];
3812
3813         u8         reserved_at_20[0x10];
3814         u8         op_mod[0x10];
3815
3816         u8         reserved_at_40[0x8];
3817         u8         tirn[0x18];
3818
3819         u8         reserved_at_60[0x20];
3820 };
3821
3822 struct mlx5_ifc_query_srq_out_bits {
3823         u8         status[0x8];
3824         u8         reserved_at_8[0x18];
3825