1853e7fd6924ab37b4f1df162ee023b63ba5b3e1
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65
66 enum {
67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72
73 enum {
74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
76 };
77
78 enum {
79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
81 };
82
83 enum {
84         MLX5_OBJ_TYPE_UCTX = 0x0004,
85 };
86
87 enum {
88         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
89         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
90         MLX5_CMD_OP_INIT_HCA                      = 0x102,
91         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
92         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
93         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
94         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
95         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
96         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
97         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
98         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
99         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
100         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
101         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
102         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
103         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
104         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
105         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
106         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
107         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
108         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
109         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
110         MLX5_CMD_OP_GEN_EQE                       = 0x304,
111         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
112         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
113         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
114         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
115         MLX5_CMD_OP_CREATE_QP                     = 0x500,
116         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
117         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
118         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
119         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
120         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
121         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
122         MLX5_CMD_OP_2ERR_QP                       = 0x507,
123         MLX5_CMD_OP_2RST_QP                       = 0x50a,
124         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
125         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
126         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
127         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
128         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
129         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
130         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
131         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
132         MLX5_CMD_OP_ARM_RQ                        = 0x703,
133         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
134         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
135         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
136         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
137         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
138         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
139         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
140         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
141         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
142         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
143         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
144         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
145         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
146         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
147         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
148         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
149         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
150         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
151         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
152         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
153         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
154         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
155         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
156         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
157         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
158         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
159         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
160         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
161         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
162         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
163         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
164         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
165         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
166         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
167         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
168         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
169         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
170         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
171         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
172         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
173         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
174         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
175         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
176         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
177         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
178         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
179         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
180         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
181         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
182         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
183         MLX5_CMD_OP_NOP                           = 0x80d,
184         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
185         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
186         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
187         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
188         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
189         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
190         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
191         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
192         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
193         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
194         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
195         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
196         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
197         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
198         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
199         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
200         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
201         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
202         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
203         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
204         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
205         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
206         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
207         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
208         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
209         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
210         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
211         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
212         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
213         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
214         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
215         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
216         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
217         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
218         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
219         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
220         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
221         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
222         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
223         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
224         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
225         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
226         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
227         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
228         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
229         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
230         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
231         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
232         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
233         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
234         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
235         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
236         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
237         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
238         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
239         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
240         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
241         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
242         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
243         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
244         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
245         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
246         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
247         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
248         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
249         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
250         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
251         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
252         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
253         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
254         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
255         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
256         MLX5_CMD_OP_MAX
257 };
258
259 struct mlx5_ifc_flow_table_fields_supported_bits {
260         u8         outer_dmac[0x1];
261         u8         outer_smac[0x1];
262         u8         outer_ether_type[0x1];
263         u8         outer_ip_version[0x1];
264         u8         outer_first_prio[0x1];
265         u8         outer_first_cfi[0x1];
266         u8         outer_first_vid[0x1];
267         u8         outer_ipv4_ttl[0x1];
268         u8         outer_second_prio[0x1];
269         u8         outer_second_cfi[0x1];
270         u8         outer_second_vid[0x1];
271         u8         reserved_at_b[0x1];
272         u8         outer_sip[0x1];
273         u8         outer_dip[0x1];
274         u8         outer_frag[0x1];
275         u8         outer_ip_protocol[0x1];
276         u8         outer_ip_ecn[0x1];
277         u8         outer_ip_dscp[0x1];
278         u8         outer_udp_sport[0x1];
279         u8         outer_udp_dport[0x1];
280         u8         outer_tcp_sport[0x1];
281         u8         outer_tcp_dport[0x1];
282         u8         outer_tcp_flags[0x1];
283         u8         outer_gre_protocol[0x1];
284         u8         outer_gre_key[0x1];
285         u8         outer_vxlan_vni[0x1];
286         u8         reserved_at_1a[0x5];
287         u8         source_eswitch_port[0x1];
288
289         u8         inner_dmac[0x1];
290         u8         inner_smac[0x1];
291         u8         inner_ether_type[0x1];
292         u8         inner_ip_version[0x1];
293         u8         inner_first_prio[0x1];
294         u8         inner_first_cfi[0x1];
295         u8         inner_first_vid[0x1];
296         u8         reserved_at_27[0x1];
297         u8         inner_second_prio[0x1];
298         u8         inner_second_cfi[0x1];
299         u8         inner_second_vid[0x1];
300         u8         reserved_at_2b[0x1];
301         u8         inner_sip[0x1];
302         u8         inner_dip[0x1];
303         u8         inner_frag[0x1];
304         u8         inner_ip_protocol[0x1];
305         u8         inner_ip_ecn[0x1];
306         u8         inner_ip_dscp[0x1];
307         u8         inner_udp_sport[0x1];
308         u8         inner_udp_dport[0x1];
309         u8         inner_tcp_sport[0x1];
310         u8         inner_tcp_dport[0x1];
311         u8         inner_tcp_flags[0x1];
312         u8         reserved_at_37[0x9];
313
314         u8         reserved_at_40[0x5];
315         u8         outer_first_mpls_over_udp[0x4];
316         u8         outer_first_mpls_over_gre[0x4];
317         u8         inner_first_mpls[0x4];
318         u8         outer_first_mpls[0x4];
319         u8         reserved_at_55[0x2];
320         u8         outer_esp_spi[0x1];
321         u8         reserved_at_58[0x2];
322         u8         bth_dst_qp[0x1];
323
324         u8         reserved_at_5b[0x25];
325 };
326
327 struct mlx5_ifc_flow_table_prop_layout_bits {
328         u8         ft_support[0x1];
329         u8         reserved_at_1[0x1];
330         u8         flow_counter[0x1];
331         u8         flow_modify_en[0x1];
332         u8         modify_root[0x1];
333         u8         identified_miss_table_mode[0x1];
334         u8         flow_table_modify[0x1];
335         u8         encap[0x1];
336         u8         decap[0x1];
337         u8         reserved_at_9[0x1];
338         u8         pop_vlan[0x1];
339         u8         push_vlan[0x1];
340         u8         reserved_at_c[0x14];
341
342         u8         reserved_at_20[0x2];
343         u8         log_max_ft_size[0x6];
344         u8         log_max_modify_header_context[0x8];
345         u8         max_modify_header_actions[0x8];
346         u8         max_ft_level[0x8];
347
348         u8         reserved_at_40[0x20];
349
350         u8         reserved_at_60[0x18];
351         u8         log_max_ft_num[0x8];
352
353         u8         reserved_at_80[0x18];
354         u8         log_max_destination[0x8];
355
356         u8         log_max_flow_counter[0x8];
357         u8         reserved_at_a8[0x10];
358         u8         log_max_flow[0x8];
359
360         u8         reserved_at_c0[0x40];
361
362         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
363
364         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
365 };
366
367 struct mlx5_ifc_odp_per_transport_service_cap_bits {
368         u8         send[0x1];
369         u8         receive[0x1];
370         u8         write[0x1];
371         u8         read[0x1];
372         u8         atomic[0x1];
373         u8         srq_receive[0x1];
374         u8         reserved_at_6[0x1a];
375 };
376
377 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
378         u8         smac_47_16[0x20];
379
380         u8         smac_15_0[0x10];
381         u8         ethertype[0x10];
382
383         u8         dmac_47_16[0x20];
384
385         u8         dmac_15_0[0x10];
386         u8         first_prio[0x3];
387         u8         first_cfi[0x1];
388         u8         first_vid[0xc];
389
390         u8         ip_protocol[0x8];
391         u8         ip_dscp[0x6];
392         u8         ip_ecn[0x2];
393         u8         cvlan_tag[0x1];
394         u8         svlan_tag[0x1];
395         u8         frag[0x1];
396         u8         ip_version[0x4];
397         u8         tcp_flags[0x9];
398
399         u8         tcp_sport[0x10];
400         u8         tcp_dport[0x10];
401
402         u8         reserved_at_c0[0x18];
403         u8         ttl_hoplimit[0x8];
404
405         u8         udp_sport[0x10];
406         u8         udp_dport[0x10];
407
408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
409
410         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
411 };
412
413 struct mlx5_ifc_fte_match_set_misc_bits {
414         u8         reserved_at_0[0x8];
415         u8         source_sqn[0x18];
416
417         u8         source_eswitch_owner_vhca_id[0x10];
418         u8         source_port[0x10];
419
420         u8         outer_second_prio[0x3];
421         u8         outer_second_cfi[0x1];
422         u8         outer_second_vid[0xc];
423         u8         inner_second_prio[0x3];
424         u8         inner_second_cfi[0x1];
425         u8         inner_second_vid[0xc];
426
427         u8         outer_second_cvlan_tag[0x1];
428         u8         inner_second_cvlan_tag[0x1];
429         u8         outer_second_svlan_tag[0x1];
430         u8         inner_second_svlan_tag[0x1];
431         u8         reserved_at_64[0xc];
432         u8         gre_protocol[0x10];
433
434         u8         gre_key_h[0x18];
435         u8         gre_key_l[0x8];
436
437         u8         vxlan_vni[0x18];
438         u8         reserved_at_b8[0x8];
439
440         u8         reserved_at_c0[0x20];
441
442         u8         reserved_at_e0[0xc];
443         u8         outer_ipv6_flow_label[0x14];
444
445         u8         reserved_at_100[0xc];
446         u8         inner_ipv6_flow_label[0x14];
447
448         u8         reserved_at_120[0x28];
449         u8         bth_dst_qp[0x18];
450         u8         reserved_at_160[0x20];
451         u8         outer_esp_spi[0x20];
452         u8         reserved_at_1a0[0x60];
453 };
454
455 struct mlx5_ifc_fte_match_mpls_bits {
456         u8         mpls_label[0x14];
457         u8         mpls_exp[0x3];
458         u8         mpls_s_bos[0x1];
459         u8         mpls_ttl[0x8];
460 };
461
462 struct mlx5_ifc_fte_match_set_misc2_bits {
463         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
464
465         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
466
467         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
468
469         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
470
471         u8         reserved_at_80[0x100];
472
473         u8         metadata_reg_a[0x20];
474
475         u8         reserved_at_1a0[0x60];
476 };
477
478 struct mlx5_ifc_cmd_pas_bits {
479         u8         pa_h[0x20];
480
481         u8         pa_l[0x14];
482         u8         reserved_at_34[0xc];
483 };
484
485 struct mlx5_ifc_uint64_bits {
486         u8         hi[0x20];
487
488         u8         lo[0x20];
489 };
490
491 enum {
492         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
493         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
494         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
495         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
496         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
497         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
498         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
499         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
500         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
501         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
502 };
503
504 struct mlx5_ifc_ads_bits {
505         u8         fl[0x1];
506         u8         free_ar[0x1];
507         u8         reserved_at_2[0xe];
508         u8         pkey_index[0x10];
509
510         u8         reserved_at_20[0x8];
511         u8         grh[0x1];
512         u8         mlid[0x7];
513         u8         rlid[0x10];
514
515         u8         ack_timeout[0x5];
516         u8         reserved_at_45[0x3];
517         u8         src_addr_index[0x8];
518         u8         reserved_at_50[0x4];
519         u8         stat_rate[0x4];
520         u8         hop_limit[0x8];
521
522         u8         reserved_at_60[0x4];
523         u8         tclass[0x8];
524         u8         flow_label[0x14];
525
526         u8         rgid_rip[16][0x8];
527
528         u8         reserved_at_100[0x4];
529         u8         f_dscp[0x1];
530         u8         f_ecn[0x1];
531         u8         reserved_at_106[0x1];
532         u8         f_eth_prio[0x1];
533         u8         ecn[0x2];
534         u8         dscp[0x6];
535         u8         udp_sport[0x10];
536
537         u8         dei_cfi[0x1];
538         u8         eth_prio[0x3];
539         u8         sl[0x4];
540         u8         vhca_port_num[0x8];
541         u8         rmac_47_32[0x10];
542
543         u8         rmac_31_0[0x20];
544 };
545
546 struct mlx5_ifc_flow_table_nic_cap_bits {
547         u8         nic_rx_multi_path_tirs[0x1];
548         u8         nic_rx_multi_path_tirs_fts[0x1];
549         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
550         u8         reserved_at_3[0x1fd];
551
552         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
553
554         u8         reserved_at_400[0x200];
555
556         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
557
558         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
559
560         u8         reserved_at_a00[0x200];
561
562         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
563
564         u8         reserved_at_e00[0x7200];
565 };
566
567 struct mlx5_ifc_flow_table_eswitch_cap_bits {
568         u8      reserved_at_0[0x1c];
569         u8      fdb_multi_path_to_table[0x1];
570         u8      reserved_at_1d[0x1e3];
571
572         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
573
574         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
575
576         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
577
578         u8      reserved_at_800[0x7800];
579 };
580
581 struct mlx5_ifc_e_switch_cap_bits {
582         u8         vport_svlan_strip[0x1];
583         u8         vport_cvlan_strip[0x1];
584         u8         vport_svlan_insert[0x1];
585         u8         vport_cvlan_insert_if_not_exist[0x1];
586         u8         vport_cvlan_insert_overwrite[0x1];
587         u8         reserved_at_5[0x18];
588         u8         merged_eswitch[0x1];
589         u8         nic_vport_node_guid_modify[0x1];
590         u8         nic_vport_port_guid_modify[0x1];
591
592         u8         vxlan_encap_decap[0x1];
593         u8         nvgre_encap_decap[0x1];
594         u8         reserved_at_22[0x9];
595         u8         log_max_encap_headers[0x5];
596         u8         reserved_2b[0x6];
597         u8         max_encap_header_size[0xa];
598
599         u8         reserved_40[0x7c0];
600
601 };
602
603 struct mlx5_ifc_qos_cap_bits {
604         u8         packet_pacing[0x1];
605         u8         esw_scheduling[0x1];
606         u8         esw_bw_share[0x1];
607         u8         esw_rate_limit[0x1];
608         u8         reserved_at_4[0x1];
609         u8         packet_pacing_burst_bound[0x1];
610         u8         packet_pacing_typical_size[0x1];
611         u8         reserved_at_7[0x19];
612
613         u8         reserved_at_20[0x20];
614
615         u8         packet_pacing_max_rate[0x20];
616
617         u8         packet_pacing_min_rate[0x20];
618
619         u8         reserved_at_80[0x10];
620         u8         packet_pacing_rate_table_size[0x10];
621
622         u8         esw_element_type[0x10];
623         u8         esw_tsar_type[0x10];
624
625         u8         reserved_at_c0[0x10];
626         u8         max_qos_para_vport[0x10];
627
628         u8         max_tsar_bw_share[0x20];
629
630         u8         reserved_at_100[0x700];
631 };
632
633 struct mlx5_ifc_debug_cap_bits {
634         u8         reserved_at_0[0x20];
635
636         u8         reserved_at_20[0x2];
637         u8         stall_detect[0x1];
638         u8         reserved_at_23[0x1d];
639
640         u8         reserved_at_40[0x7c0];
641 };
642
643 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
644         u8         csum_cap[0x1];
645         u8         vlan_cap[0x1];
646         u8         lro_cap[0x1];
647         u8         lro_psh_flag[0x1];
648         u8         lro_time_stamp[0x1];
649         u8         reserved_at_5[0x2];
650         u8         wqe_vlan_insert[0x1];
651         u8         self_lb_en_modifiable[0x1];
652         u8         reserved_at_9[0x2];
653         u8         max_lso_cap[0x5];
654         u8         multi_pkt_send_wqe[0x2];
655         u8         wqe_inline_mode[0x2];
656         u8         rss_ind_tbl_cap[0x4];
657         u8         reg_umr_sq[0x1];
658         u8         scatter_fcs[0x1];
659         u8         enhanced_multi_pkt_send_wqe[0x1];
660         u8         tunnel_lso_const_out_ip_id[0x1];
661         u8         reserved_at_1c[0x2];
662         u8         tunnel_stateless_gre[0x1];
663         u8         tunnel_stateless_vxlan[0x1];
664
665         u8         swp[0x1];
666         u8         swp_csum[0x1];
667         u8         swp_lso[0x1];
668         u8         reserved_at_23[0x1b];
669         u8         max_geneve_opt_len[0x1];
670         u8         tunnel_stateless_geneve_rx[0x1];
671
672         u8         reserved_at_40[0x10];
673         u8         lro_min_mss_size[0x10];
674
675         u8         reserved_at_60[0x120];
676
677         u8         lro_timer_supported_periods[4][0x20];
678
679         u8         reserved_at_200[0x600];
680 };
681
682 struct mlx5_ifc_roce_cap_bits {
683         u8         roce_apm[0x1];
684         u8         reserved_at_1[0x1f];
685
686         u8         reserved_at_20[0x60];
687
688         u8         reserved_at_80[0xc];
689         u8         l3_type[0x4];
690         u8         reserved_at_90[0x8];
691         u8         roce_version[0x8];
692
693         u8         reserved_at_a0[0x10];
694         u8         r_roce_dest_udp_port[0x10];
695
696         u8         r_roce_max_src_udp_port[0x10];
697         u8         r_roce_min_src_udp_port[0x10];
698
699         u8         reserved_at_e0[0x10];
700         u8         roce_address_table_size[0x10];
701
702         u8         reserved_at_100[0x700];
703 };
704
705 struct mlx5_ifc_device_mem_cap_bits {
706         u8         memic[0x1];
707         u8         reserved_at_1[0x1f];
708
709         u8         reserved_at_20[0xb];
710         u8         log_min_memic_alloc_size[0x5];
711         u8         reserved_at_30[0x8];
712         u8         log_max_memic_addr_alignment[0x8];
713
714         u8         memic_bar_start_addr[0x40];
715
716         u8         memic_bar_size[0x20];
717
718         u8         max_memic_size[0x20];
719
720         u8         reserved_at_c0[0x740];
721 };
722
723 enum {
724         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
725         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
726         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
727         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
728         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
729         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
730         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
733 };
734
735 enum {
736         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
737         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
738         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
739         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
740         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
741         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
742         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
745 };
746
747 struct mlx5_ifc_atomic_caps_bits {
748         u8         reserved_at_0[0x40];
749
750         u8         atomic_req_8B_endianness_mode[0x2];
751         u8         reserved_at_42[0x4];
752         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
753
754         u8         reserved_at_47[0x19];
755
756         u8         reserved_at_60[0x20];
757
758         u8         reserved_at_80[0x10];
759         u8         atomic_operations[0x10];
760
761         u8         reserved_at_a0[0x10];
762         u8         atomic_size_qp[0x10];
763
764         u8         reserved_at_c0[0x10];
765         u8         atomic_size_dc[0x10];
766
767         u8         reserved_at_e0[0x720];
768 };
769
770 struct mlx5_ifc_odp_cap_bits {
771         u8         reserved_at_0[0x40];
772
773         u8         sig[0x1];
774         u8         reserved_at_41[0x1f];
775
776         u8         reserved_at_60[0x20];
777
778         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
779
780         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
781
782         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
783
784         u8         reserved_at_e0[0x720];
785 };
786
787 struct mlx5_ifc_calc_op {
788         u8        reserved_at_0[0x10];
789         u8        reserved_at_10[0x9];
790         u8        op_swap_endianness[0x1];
791         u8        op_min[0x1];
792         u8        op_xor[0x1];
793         u8        op_or[0x1];
794         u8        op_and[0x1];
795         u8        op_max[0x1];
796         u8        op_add[0x1];
797 };
798
799 struct mlx5_ifc_vector_calc_cap_bits {
800         u8         calc_matrix[0x1];
801         u8         reserved_at_1[0x1f];
802         u8         reserved_at_20[0x8];
803         u8         max_vec_count[0x8];
804         u8         reserved_at_30[0xd];
805         u8         max_chunk_size[0x3];
806         struct mlx5_ifc_calc_op calc0;
807         struct mlx5_ifc_calc_op calc1;
808         struct mlx5_ifc_calc_op calc2;
809         struct mlx5_ifc_calc_op calc3;
810
811         u8         reserved_at_e0[0x720];
812 };
813
814 enum {
815         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
816         MLX5_WQ_TYPE_CYCLIC       = 0x1,
817         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
818         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
819 };
820
821 enum {
822         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
823         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
824 };
825
826 enum {
827         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
828         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
829         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
830         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
831         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
832 };
833
834 enum {
835         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
836         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
837         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
838         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
839         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
840         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
841 };
842
843 enum {
844         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
845         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
846 };
847
848 enum {
849         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
850         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
851         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
852 };
853
854 enum {
855         MLX5_CAP_PORT_TYPE_IB  = 0x0,
856         MLX5_CAP_PORT_TYPE_ETH = 0x1,
857 };
858
859 enum {
860         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
861         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
862         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
863 };
864
865 struct mlx5_ifc_cmd_hca_cap_bits {
866         u8         reserved_at_0[0x30];
867         u8         vhca_id[0x10];
868
869         u8         reserved_at_40[0x40];
870
871         u8         log_max_srq_sz[0x8];
872         u8         log_max_qp_sz[0x8];
873         u8         reserved_at_90[0xb];
874         u8         log_max_qp[0x5];
875
876         u8         reserved_at_a0[0xb];
877         u8         log_max_srq[0x5];
878         u8         reserved_at_b0[0x10];
879
880         u8         reserved_at_c0[0x8];
881         u8         log_max_cq_sz[0x8];
882         u8         reserved_at_d0[0xb];
883         u8         log_max_cq[0x5];
884
885         u8         log_max_eq_sz[0x8];
886         u8         reserved_at_e8[0x2];
887         u8         log_max_mkey[0x6];
888         u8         reserved_at_f0[0x8];
889         u8         dump_fill_mkey[0x1];
890         u8         reserved_at_f9[0x3];
891         u8         log_max_eq[0x4];
892
893         u8         max_indirection[0x8];
894         u8         fixed_buffer_size[0x1];
895         u8         log_max_mrw_sz[0x7];
896         u8         force_teardown[0x1];
897         u8         reserved_at_111[0x1];
898         u8         log_max_bsf_list_size[0x6];
899         u8         umr_extended_translation_offset[0x1];
900         u8         null_mkey[0x1];
901         u8         log_max_klm_list_size[0x6];
902
903         u8         reserved_at_120[0xa];
904         u8         log_max_ra_req_dc[0x6];
905         u8         reserved_at_130[0xa];
906         u8         log_max_ra_res_dc[0x6];
907
908         u8         reserved_at_140[0xa];
909         u8         log_max_ra_req_qp[0x6];
910         u8         reserved_at_150[0xa];
911         u8         log_max_ra_res_qp[0x6];
912
913         u8         end_pad[0x1];
914         u8         cc_query_allowed[0x1];
915         u8         cc_modify_allowed[0x1];
916         u8         start_pad[0x1];
917         u8         cache_line_128byte[0x1];
918         u8         reserved_at_165[0xa];
919         u8         qcam_reg[0x1];
920         u8         gid_table_size[0x10];
921
922         u8         out_of_seq_cnt[0x1];
923         u8         vport_counters[0x1];
924         u8         retransmission_q_counters[0x1];
925         u8         debug[0x1];
926         u8         modify_rq_counter_set_id[0x1];
927         u8         rq_delay_drop[0x1];
928         u8         max_qp_cnt[0xa];
929         u8         pkey_table_size[0x10];
930
931         u8         vport_group_manager[0x1];
932         u8         vhca_group_manager[0x1];
933         u8         ib_virt[0x1];
934         u8         eth_virt[0x1];
935         u8         vnic_env_queue_counters[0x1];
936         u8         ets[0x1];
937         u8         nic_flow_table[0x1];
938         u8         eswitch_flow_table[0x1];
939         u8         device_memory[0x1];
940         u8         mcam_reg[0x1];
941         u8         pcam_reg[0x1];
942         u8         local_ca_ack_delay[0x5];
943         u8         port_module_event[0x1];
944         u8         enhanced_error_q_counters[0x1];
945         u8         ports_check[0x1];
946         u8         reserved_at_1b3[0x1];
947         u8         disable_link_up[0x1];
948         u8         beacon_led[0x1];
949         u8         port_type[0x2];
950         u8         num_ports[0x8];
951
952         u8         reserved_at_1c0[0x1];
953         u8         pps[0x1];
954         u8         pps_modify[0x1];
955         u8         log_max_msg[0x5];
956         u8         reserved_at_1c8[0x4];
957         u8         max_tc[0x4];
958         u8         temp_warn_event[0x1];
959         u8         dcbx[0x1];
960         u8         general_notification_event[0x1];
961         u8         reserved_at_1d3[0x2];
962         u8         fpga[0x1];
963         u8         rol_s[0x1];
964         u8         rol_g[0x1];
965         u8         reserved_at_1d8[0x1];
966         u8         wol_s[0x1];
967         u8         wol_g[0x1];
968         u8         wol_a[0x1];
969         u8         wol_b[0x1];
970         u8         wol_m[0x1];
971         u8         wol_u[0x1];
972         u8         wol_p[0x1];
973
974         u8         stat_rate_support[0x10];
975         u8         reserved_at_1f0[0xc];
976         u8         cqe_version[0x4];
977
978         u8         compact_address_vector[0x1];
979         u8         striding_rq[0x1];
980         u8         reserved_at_202[0x1];
981         u8         ipoib_enhanced_offloads[0x1];
982         u8         ipoib_basic_offloads[0x1];
983         u8         reserved_at_205[0x1];
984         u8         repeated_block_disabled[0x1];
985         u8         umr_modify_entity_size_disabled[0x1];
986         u8         umr_modify_atomic_disabled[0x1];
987         u8         umr_indirect_mkey_disabled[0x1];
988         u8         umr_fence[0x2];
989         u8         reserved_at_20c[0x3];
990         u8         drain_sigerr[0x1];
991         u8         cmdif_checksum[0x2];
992         u8         sigerr_cqe[0x1];
993         u8         reserved_at_213[0x1];
994         u8         wq_signature[0x1];
995         u8         sctr_data_cqe[0x1];
996         u8         reserved_at_216[0x1];
997         u8         sho[0x1];
998         u8         tph[0x1];
999         u8         rf[0x1];
1000         u8         dct[0x1];
1001         u8         qos[0x1];
1002         u8         eth_net_offloads[0x1];
1003         u8         roce[0x1];
1004         u8         atomic[0x1];
1005         u8         reserved_at_21f[0x1];
1006
1007         u8         cq_oi[0x1];
1008         u8         cq_resize[0x1];
1009         u8         cq_moderation[0x1];
1010         u8         reserved_at_223[0x3];
1011         u8         cq_eq_remap[0x1];
1012         u8         pg[0x1];
1013         u8         block_lb_mc[0x1];
1014         u8         reserved_at_229[0x1];
1015         u8         scqe_break_moderation[0x1];
1016         u8         cq_period_start_from_cqe[0x1];
1017         u8         cd[0x1];
1018         u8         reserved_at_22d[0x1];
1019         u8         apm[0x1];
1020         u8         vector_calc[0x1];
1021         u8         umr_ptr_rlky[0x1];
1022         u8         imaicl[0x1];
1023         u8         reserved_at_232[0x4];
1024         u8         qkv[0x1];
1025         u8         pkv[0x1];
1026         u8         set_deth_sqpn[0x1];
1027         u8         reserved_at_239[0x3];
1028         u8         xrc[0x1];
1029         u8         ud[0x1];
1030         u8         uc[0x1];
1031         u8         rc[0x1];
1032
1033         u8         uar_4k[0x1];
1034         u8         reserved_at_241[0x9];
1035         u8         uar_sz[0x6];
1036         u8         reserved_at_250[0x8];
1037         u8         log_pg_sz[0x8];
1038
1039         u8         bf[0x1];
1040         u8         driver_version[0x1];
1041         u8         pad_tx_eth_packet[0x1];
1042         u8         reserved_at_263[0x8];
1043         u8         log_bf_reg_size[0x5];
1044
1045         u8         reserved_at_270[0xb];
1046         u8         lag_master[0x1];
1047         u8         num_lag_ports[0x4];
1048
1049         u8         reserved_at_280[0x10];
1050         u8         max_wqe_sz_sq[0x10];
1051
1052         u8         reserved_at_2a0[0x10];
1053         u8         max_wqe_sz_rq[0x10];
1054
1055         u8         max_flow_counter_31_16[0x10];
1056         u8         max_wqe_sz_sq_dc[0x10];
1057
1058         u8         reserved_at_2e0[0x7];
1059         u8         max_qp_mcg[0x19];
1060
1061         u8         reserved_at_300[0x18];
1062         u8         log_max_mcg[0x8];
1063
1064         u8         reserved_at_320[0x3];
1065         u8         log_max_transport_domain[0x5];
1066         u8         reserved_at_328[0x3];
1067         u8         log_max_pd[0x5];
1068         u8         reserved_at_330[0xb];
1069         u8         log_max_xrcd[0x5];
1070
1071         u8         nic_receive_steering_discard[0x1];
1072         u8         receive_discard_vport_down[0x1];
1073         u8         transmit_discard_vport_down[0x1];
1074         u8         reserved_at_343[0x5];
1075         u8         log_max_flow_counter_bulk[0x8];
1076         u8         max_flow_counter_15_0[0x10];
1077
1078
1079         u8         reserved_at_360[0x3];
1080         u8         log_max_rq[0x5];
1081         u8         reserved_at_368[0x3];
1082         u8         log_max_sq[0x5];
1083         u8         reserved_at_370[0x3];
1084         u8         log_max_tir[0x5];
1085         u8         reserved_at_378[0x3];
1086         u8         log_max_tis[0x5];
1087
1088         u8         basic_cyclic_rcv_wqe[0x1];
1089         u8         reserved_at_381[0x2];
1090         u8         log_max_rmp[0x5];
1091         u8         reserved_at_388[0x3];
1092         u8         log_max_rqt[0x5];
1093         u8         reserved_at_390[0x3];
1094         u8         log_max_rqt_size[0x5];
1095         u8         reserved_at_398[0x3];
1096         u8         log_max_tis_per_sq[0x5];
1097
1098         u8         ext_stride_num_range[0x1];
1099         u8         reserved_at_3a1[0x2];
1100         u8         log_max_stride_sz_rq[0x5];
1101         u8         reserved_at_3a8[0x3];
1102         u8         log_min_stride_sz_rq[0x5];
1103         u8         reserved_at_3b0[0x3];
1104         u8         log_max_stride_sz_sq[0x5];
1105         u8         reserved_at_3b8[0x3];
1106         u8         log_min_stride_sz_sq[0x5];
1107
1108         u8         hairpin[0x1];
1109         u8         reserved_at_3c1[0x2];
1110         u8         log_max_hairpin_queues[0x5];
1111         u8         reserved_at_3c8[0x3];
1112         u8         log_max_hairpin_wq_data_sz[0x5];
1113         u8         reserved_at_3d0[0x3];
1114         u8         log_max_hairpin_num_packets[0x5];
1115         u8         reserved_at_3d8[0x3];
1116         u8         log_max_wq_sz[0x5];
1117
1118         u8         nic_vport_change_event[0x1];
1119         u8         disable_local_lb_uc[0x1];
1120         u8         disable_local_lb_mc[0x1];
1121         u8         log_min_hairpin_wq_data_sz[0x5];
1122         u8         reserved_at_3e8[0x3];
1123         u8         log_max_vlan_list[0x5];
1124         u8         reserved_at_3f0[0x3];
1125         u8         log_max_current_mc_list[0x5];
1126         u8         reserved_at_3f8[0x3];
1127         u8         log_max_current_uc_list[0x5];
1128
1129         u8         general_obj_types[0x40];
1130
1131         u8         reserved_at_440[0x40];
1132
1133         u8         reserved_at_480[0x3];
1134         u8         log_max_l2_table[0x5];
1135         u8         reserved_at_488[0x8];
1136         u8         log_uar_page_sz[0x10];
1137
1138         u8         reserved_at_4a0[0x20];
1139         u8         device_frequency_mhz[0x20];
1140         u8         device_frequency_khz[0x20];
1141
1142         u8         reserved_at_500[0x20];
1143         u8         num_of_uars_per_page[0x20];
1144
1145         u8         flex_parser_protocols[0x20];
1146         u8         reserved_at_560[0x20];
1147
1148         u8         reserved_at_580[0x3c];
1149         u8         mini_cqe_resp_stride_index[0x1];
1150         u8         cqe_128_always[0x1];
1151         u8         cqe_compression_128[0x1];
1152         u8         cqe_compression[0x1];
1153
1154         u8         cqe_compression_timeout[0x10];
1155         u8         cqe_compression_max_num[0x10];
1156
1157         u8         reserved_at_5e0[0x10];
1158         u8         tag_matching[0x1];
1159         u8         rndv_offload_rc[0x1];
1160         u8         rndv_offload_dc[0x1];
1161         u8         log_tag_matching_list_sz[0x5];
1162         u8         reserved_at_5f8[0x3];
1163         u8         log_max_xrq[0x5];
1164
1165         u8         affiliate_nic_vport_criteria[0x8];
1166         u8         native_port_num[0x8];
1167         u8         num_vhca_ports[0x8];
1168         u8         reserved_at_618[0x6];
1169         u8         sw_owner_id[0x1];
1170         u8         reserved_at_61f[0x1e1];
1171 };
1172
1173 enum mlx5_flow_destination_type {
1174         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1175         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1176         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1177
1178         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1179         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1180 };
1181
1182 struct mlx5_ifc_dest_format_struct_bits {
1183         u8         destination_type[0x8];
1184         u8         destination_id[0x18];
1185         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1186         u8         reserved_at_21[0xf];
1187         u8         destination_eswitch_owner_vhca_id[0x10];
1188 };
1189
1190 struct mlx5_ifc_flow_counter_list_bits {
1191         u8         flow_counter_id[0x20];
1192
1193         u8         reserved_at_20[0x20];
1194 };
1195
1196 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1197         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1198         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1199         u8         reserved_at_0[0x40];
1200 };
1201
1202 struct mlx5_ifc_fte_match_param_bits {
1203         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1204
1205         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1206
1207         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1208
1209         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1210
1211         u8         reserved_at_800[0x800];
1212 };
1213
1214 enum {
1215         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1216         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1217         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1218         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1219         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1220 };
1221
1222 struct mlx5_ifc_rx_hash_field_select_bits {
1223         u8         l3_prot_type[0x1];
1224         u8         l4_prot_type[0x1];
1225         u8         selected_fields[0x1e];
1226 };
1227
1228 enum {
1229         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1230         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1231 };
1232
1233 enum {
1234         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1235         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1236 };
1237
1238 struct mlx5_ifc_wq_bits {
1239         u8         wq_type[0x4];
1240         u8         wq_signature[0x1];
1241         u8         end_padding_mode[0x2];
1242         u8         cd_slave[0x1];
1243         u8         reserved_at_8[0x18];
1244
1245         u8         hds_skip_first_sge[0x1];
1246         u8         log2_hds_buf_size[0x3];
1247         u8         reserved_at_24[0x7];
1248         u8         page_offset[0x5];
1249         u8         lwm[0x10];
1250
1251         u8         reserved_at_40[0x8];
1252         u8         pd[0x18];
1253
1254         u8         reserved_at_60[0x8];
1255         u8         uar_page[0x18];
1256
1257         u8         dbr_addr[0x40];
1258
1259         u8         hw_counter[0x20];
1260
1261         u8         sw_counter[0x20];
1262
1263         u8         reserved_at_100[0xc];
1264         u8         log_wq_stride[0x4];
1265         u8         reserved_at_110[0x3];
1266         u8         log_wq_pg_sz[0x5];
1267         u8         reserved_at_118[0x3];
1268         u8         log_wq_sz[0x5];
1269
1270         u8         reserved_at_120[0x3];
1271         u8         log_hairpin_num_packets[0x5];
1272         u8         reserved_at_128[0x3];
1273         u8         log_hairpin_data_sz[0x5];
1274
1275         u8         reserved_at_130[0x4];
1276         u8         log_wqe_num_of_strides[0x4];
1277         u8         two_byte_shift_en[0x1];
1278         u8         reserved_at_139[0x4];
1279         u8         log_wqe_stride_size[0x3];
1280
1281         u8         reserved_at_140[0x4c0];
1282
1283         struct mlx5_ifc_cmd_pas_bits pas[0];
1284 };
1285
1286 struct mlx5_ifc_rq_num_bits {
1287         u8         reserved_at_0[0x8];
1288         u8         rq_num[0x18];
1289 };
1290
1291 struct mlx5_ifc_mac_address_layout_bits {
1292         u8         reserved_at_0[0x10];
1293         u8         mac_addr_47_32[0x10];
1294
1295         u8         mac_addr_31_0[0x20];
1296 };
1297
1298 struct mlx5_ifc_vlan_layout_bits {
1299         u8         reserved_at_0[0x14];
1300         u8         vlan[0x0c];
1301
1302         u8         reserved_at_20[0x20];
1303 };
1304
1305 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1306         u8         reserved_at_0[0xa0];
1307
1308         u8         min_time_between_cnps[0x20];
1309
1310         u8         reserved_at_c0[0x12];
1311         u8         cnp_dscp[0x6];
1312         u8         reserved_at_d8[0x4];
1313         u8         cnp_prio_mode[0x1];
1314         u8         cnp_802p_prio[0x3];
1315
1316         u8         reserved_at_e0[0x720];
1317 };
1318
1319 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1320         u8         reserved_at_0[0x60];
1321
1322         u8         reserved_at_60[0x4];
1323         u8         clamp_tgt_rate[0x1];
1324         u8         reserved_at_65[0x3];
1325         u8         clamp_tgt_rate_after_time_inc[0x1];
1326         u8         reserved_at_69[0x17];
1327
1328         u8         reserved_at_80[0x20];
1329
1330         u8         rpg_time_reset[0x20];
1331
1332         u8         rpg_byte_reset[0x20];
1333
1334         u8         rpg_threshold[0x20];
1335
1336         u8         rpg_max_rate[0x20];
1337
1338         u8         rpg_ai_rate[0x20];
1339
1340         u8         rpg_hai_rate[0x20];
1341
1342         u8         rpg_gd[0x20];
1343
1344         u8         rpg_min_dec_fac[0x20];
1345
1346         u8         rpg_min_rate[0x20];
1347
1348         u8         reserved_at_1c0[0xe0];
1349
1350         u8         rate_to_set_on_first_cnp[0x20];
1351
1352         u8         dce_tcp_g[0x20];
1353
1354         u8         dce_tcp_rtt[0x20];
1355
1356         u8         rate_reduce_monitor_period[0x20];
1357
1358         u8         reserved_at_320[0x20];
1359
1360         u8         initial_alpha_value[0x20];
1361
1362         u8         reserved_at_360[0x4a0];
1363 };
1364
1365 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1366         u8         reserved_at_0[0x80];
1367
1368         u8         rppp_max_rps[0x20];
1369
1370         u8         rpg_time_reset[0x20];
1371
1372         u8         rpg_byte_reset[0x20];
1373
1374         u8         rpg_threshold[0x20];
1375
1376         u8         rpg_max_rate[0x20];
1377
1378         u8         rpg_ai_rate[0x20];
1379
1380         u8         rpg_hai_rate[0x20];
1381
1382         u8         rpg_gd[0x20];
1383
1384         u8         rpg_min_dec_fac[0x20];
1385
1386         u8         rpg_min_rate[0x20];
1387
1388         u8         reserved_at_1c0[0x640];
1389 };
1390
1391 enum {
1392         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1393         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1394         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1395 };
1396
1397 struct mlx5_ifc_resize_field_select_bits {
1398         u8         resize_field_select[0x20];
1399 };
1400
1401 enum {
1402         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1403         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1404         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1405         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1406 };
1407
1408 struct mlx5_ifc_modify_field_select_bits {
1409         u8         modify_field_select[0x20];
1410 };
1411
1412 struct mlx5_ifc_field_select_r_roce_np_bits {
1413         u8         field_select_r_roce_np[0x20];
1414 };
1415
1416 struct mlx5_ifc_field_select_r_roce_rp_bits {
1417         u8         field_select_r_roce_rp[0x20];
1418 };
1419
1420 enum {
1421         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1422         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1423         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1424         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1425         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1426         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1427         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1428         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1429         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1430         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1431 };
1432
1433 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1434         u8         field_select_8021qaurp[0x20];
1435 };
1436
1437 struct mlx5_ifc_phys_layer_cntrs_bits {
1438         u8         time_since_last_clear_high[0x20];
1439
1440         u8         time_since_last_clear_low[0x20];
1441
1442         u8         symbol_errors_high[0x20];
1443
1444         u8         symbol_errors_low[0x20];
1445
1446         u8         sync_headers_errors_high[0x20];
1447
1448         u8         sync_headers_errors_low[0x20];
1449
1450         u8         edpl_bip_errors_lane0_high[0x20];
1451
1452         u8         edpl_bip_errors_lane0_low[0x20];
1453
1454         u8         edpl_bip_errors_lane1_high[0x20];
1455
1456         u8         edpl_bip_errors_lane1_low[0x20];
1457
1458         u8         edpl_bip_errors_lane2_high[0x20];
1459
1460         u8         edpl_bip_errors_lane2_low[0x20];
1461
1462         u8         edpl_bip_errors_lane3_high[0x20];
1463
1464         u8         edpl_bip_errors_lane3_low[0x20];
1465
1466         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1467
1468         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1469
1470         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1471
1472         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1473
1474         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1475
1476         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1477
1478         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1479
1480         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1481
1482         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1483
1484         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1485
1486         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1487
1488         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1489
1490         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1491
1492         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1493
1494         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1495
1496         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1497
1498         u8         rs_fec_corrected_blocks_high[0x20];
1499
1500         u8         rs_fec_corrected_blocks_low[0x20];
1501
1502         u8         rs_fec_uncorrectable_blocks_high[0x20];
1503
1504         u8         rs_fec_uncorrectable_blocks_low[0x20];
1505
1506         u8         rs_fec_no_errors_blocks_high[0x20];
1507
1508         u8         rs_fec_no_errors_blocks_low[0x20];
1509
1510         u8         rs_fec_single_error_blocks_high[0x20];
1511
1512         u8         rs_fec_single_error_blocks_low[0x20];
1513
1514         u8         rs_fec_corrected_symbols_total_high[0x20];
1515
1516         u8         rs_fec_corrected_symbols_total_low[0x20];
1517
1518         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1519
1520         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1521
1522         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1523
1524         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1525
1526         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1527
1528         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1529
1530         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1531
1532         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1533
1534         u8         link_down_events[0x20];
1535
1536         u8         successful_recovery_events[0x20];
1537
1538         u8         reserved_at_640[0x180];
1539 };
1540
1541 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1542         u8         time_since_last_clear_high[0x20];
1543
1544         u8         time_since_last_clear_low[0x20];
1545
1546         u8         phy_received_bits_high[0x20];
1547
1548         u8         phy_received_bits_low[0x20];
1549
1550         u8         phy_symbol_errors_high[0x20];
1551
1552         u8         phy_symbol_errors_low[0x20];
1553
1554         u8         phy_corrected_bits_high[0x20];
1555
1556         u8         phy_corrected_bits_low[0x20];
1557
1558         u8         phy_corrected_bits_lane0_high[0x20];
1559
1560         u8         phy_corrected_bits_lane0_low[0x20];
1561
1562         u8         phy_corrected_bits_lane1_high[0x20];
1563
1564         u8         phy_corrected_bits_lane1_low[0x20];
1565
1566         u8         phy_corrected_bits_lane2_high[0x20];
1567
1568         u8         phy_corrected_bits_lane2_low[0x20];
1569
1570         u8         phy_corrected_bits_lane3_high[0x20];
1571
1572         u8         phy_corrected_bits_lane3_low[0x20];
1573
1574         u8         reserved_at_200[0x5c0];
1575 };
1576
1577 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1578         u8         symbol_error_counter[0x10];
1579
1580         u8         link_error_recovery_counter[0x8];
1581
1582         u8         link_downed_counter[0x8];
1583
1584         u8         port_rcv_errors[0x10];
1585
1586         u8         port_rcv_remote_physical_errors[0x10];
1587
1588         u8         port_rcv_switch_relay_errors[0x10];
1589
1590         u8         port_xmit_discards[0x10];
1591
1592         u8         port_xmit_constraint_errors[0x8];
1593
1594         u8         port_rcv_constraint_errors[0x8];
1595
1596         u8         reserved_at_70[0x8];
1597
1598         u8         link_overrun_errors[0x8];
1599
1600         u8         reserved_at_80[0x10];
1601
1602         u8         vl_15_dropped[0x10];
1603
1604         u8         reserved_at_a0[0x80];
1605
1606         u8         port_xmit_wait[0x20];
1607 };
1608
1609 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1610         u8         transmit_queue_high[0x20];
1611
1612         u8         transmit_queue_low[0x20];
1613
1614         u8         reserved_at_40[0x780];
1615 };
1616
1617 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1618         u8         rx_octets_high[0x20];
1619
1620         u8         rx_octets_low[0x20];
1621
1622         u8         reserved_at_40[0xc0];
1623
1624         u8         rx_frames_high[0x20];
1625
1626         u8         rx_frames_low[0x20];
1627
1628         u8         tx_octets_high[0x20];
1629
1630         u8         tx_octets_low[0x20];
1631
1632         u8         reserved_at_180[0xc0];
1633
1634         u8         tx_frames_high[0x20];
1635
1636         u8         tx_frames_low[0x20];
1637
1638         u8         rx_pause_high[0x20];
1639
1640         u8         rx_pause_low[0x20];
1641
1642         u8         rx_pause_duration_high[0x20];
1643
1644         u8         rx_pause_duration_low[0x20];
1645
1646         u8         tx_pause_high[0x20];
1647
1648         u8         tx_pause_low[0x20];
1649
1650         u8         tx_pause_duration_high[0x20];
1651
1652         u8         tx_pause_duration_low[0x20];
1653
1654         u8         rx_pause_transition_high[0x20];
1655
1656         u8         rx_pause_transition_low[0x20];
1657
1658         u8         reserved_at_3c0[0x40];
1659
1660         u8         device_stall_minor_watermark_cnt_high[0x20];
1661
1662         u8         device_stall_minor_watermark_cnt_low[0x20];
1663
1664         u8         device_stall_critical_watermark_cnt_high[0x20];
1665
1666         u8         device_stall_critical_watermark_cnt_low[0x20];
1667
1668         u8         reserved_at_480[0x340];
1669 };
1670
1671 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1672         u8         port_transmit_wait_high[0x20];
1673
1674         u8         port_transmit_wait_low[0x20];
1675
1676         u8         reserved_at_40[0x100];
1677
1678         u8         rx_buffer_almost_full_high[0x20];
1679
1680         u8         rx_buffer_almost_full_low[0x20];
1681
1682         u8         rx_buffer_full_high[0x20];
1683
1684         u8         rx_buffer_full_low[0x20];
1685
1686         u8         rx_icrc_encapsulated_high[0x20];
1687
1688         u8         rx_icrc_encapsulated_low[0x20];
1689
1690         u8         reserved_at_200[0x5c0];
1691 };
1692
1693 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1694         u8         dot3stats_alignment_errors_high[0x20];
1695
1696         u8         dot3stats_alignment_errors_low[0x20];
1697
1698         u8         dot3stats_fcs_errors_high[0x20];
1699
1700         u8         dot3stats_fcs_errors_low[0x20];
1701
1702         u8         dot3stats_single_collision_frames_high[0x20];
1703
1704         u8         dot3stats_single_collision_frames_low[0x20];
1705
1706         u8         dot3stats_multiple_collision_frames_high[0x20];
1707
1708         u8         dot3stats_multiple_collision_frames_low[0x20];
1709
1710         u8         dot3stats_sqe_test_errors_high[0x20];
1711
1712         u8         dot3stats_sqe_test_errors_low[0x20];
1713
1714         u8         dot3stats_deferred_transmissions_high[0x20];
1715
1716         u8         dot3stats_deferred_transmissions_low[0x20];
1717
1718         u8         dot3stats_late_collisions_high[0x20];
1719
1720         u8         dot3stats_late_collisions_low[0x20];
1721
1722         u8         dot3stats_excessive_collisions_high[0x20];
1723
1724         u8         dot3stats_excessive_collisions_low[0x20];
1725
1726         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1727
1728         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1729
1730         u8         dot3stats_carrier_sense_errors_high[0x20];
1731
1732         u8         dot3stats_carrier_sense_errors_low[0x20];
1733
1734         u8         dot3stats_frame_too_longs_high[0x20];
1735
1736         u8         dot3stats_frame_too_longs_low[0x20];
1737
1738         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1739
1740         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1741
1742         u8         dot3stats_symbol_errors_high[0x20];
1743
1744         u8         dot3stats_symbol_errors_low[0x20];
1745
1746         u8         dot3control_in_unknown_opcodes_high[0x20];
1747
1748         u8         dot3control_in_unknown_opcodes_low[0x20];
1749
1750         u8         dot3in_pause_frames_high[0x20];
1751
1752         u8         dot3in_pause_frames_low[0x20];
1753
1754         u8         dot3out_pause_frames_high[0x20];
1755
1756         u8         dot3out_pause_frames_low[0x20];
1757
1758         u8         reserved_at_400[0x3c0];
1759 };
1760
1761 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1762         u8         ether_stats_drop_events_high[0x20];
1763
1764         u8         ether_stats_drop_events_low[0x20];
1765
1766         u8         ether_stats_octets_high[0x20];
1767
1768         u8         ether_stats_octets_low[0x20];
1769
1770         u8         ether_stats_pkts_high[0x20];
1771
1772         u8         ether_stats_pkts_low[0x20];
1773
1774         u8         ether_stats_broadcast_pkts_high[0x20];
1775
1776         u8         ether_stats_broadcast_pkts_low[0x20];
1777
1778         u8         ether_stats_multicast_pkts_high[0x20];
1779
1780         u8         ether_stats_multicast_pkts_low[0x20];
1781
1782         u8         ether_stats_crc_align_errors_high[0x20];
1783
1784         u8         ether_stats_crc_align_errors_low[0x20];
1785
1786         u8         ether_stats_undersize_pkts_high[0x20];
1787
1788         u8         ether_stats_undersize_pkts_low[0x20];
1789
1790         u8         ether_stats_oversize_pkts_high[0x20];
1791
1792         u8         ether_stats_oversize_pkts_low[0x20];
1793
1794         u8         ether_stats_fragments_high[0x20];
1795
1796         u8         ether_stats_fragments_low[0x20];
1797
1798         u8         ether_stats_jabbers_high[0x20];
1799
1800         u8         ether_stats_jabbers_low[0x20];
1801
1802         u8         ether_stats_collisions_high[0x20];
1803
1804         u8         ether_stats_collisions_low[0x20];
1805
1806         u8         ether_stats_pkts64octets_high[0x20];
1807
1808         u8         ether_stats_pkts64octets_low[0x20];
1809
1810         u8         ether_stats_pkts65to127octets_high[0x20];
1811
1812         u8         ether_stats_pkts65to127octets_low[0x20];
1813
1814         u8         ether_stats_pkts128to255octets_high[0x20];
1815
1816         u8         ether_stats_pkts128to255octets_low[0x20];
1817
1818         u8         ether_stats_pkts256to511octets_high[0x20];
1819
1820         u8         ether_stats_pkts256to511octets_low[0x20];
1821
1822         u8         ether_stats_pkts512to1023octets_high[0x20];
1823
1824         u8         ether_stats_pkts512to1023octets_low[0x20];
1825
1826         u8         ether_stats_pkts1024to1518octets_high[0x20];
1827
1828         u8         ether_stats_pkts1024to1518octets_low[0x20];
1829
1830         u8         ether_stats_pkts1519to2047octets_high[0x20];
1831
1832         u8         ether_stats_pkts1519to2047octets_low[0x20];
1833
1834         u8         ether_stats_pkts2048to4095octets_high[0x20];
1835
1836         u8         ether_stats_pkts2048to4095octets_low[0x20];
1837
1838         u8         ether_stats_pkts4096to8191octets_high[0x20];
1839
1840         u8         ether_stats_pkts4096to8191octets_low[0x20];
1841
1842         u8         ether_stats_pkts8192to10239octets_high[0x20];
1843
1844         u8         ether_stats_pkts8192to10239octets_low[0x20];
1845
1846         u8         reserved_at_540[0x280];
1847 };
1848
1849 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1850         u8         if_in_octets_high[0x20];
1851
1852         u8         if_in_octets_low[0x20];
1853
1854         u8         if_in_ucast_pkts_high[0x20];
1855
1856         u8         if_in_ucast_pkts_low[0x20];
1857
1858         u8         if_in_discards_high[0x20];
1859
1860         u8         if_in_discards_low[0x20];
1861
1862         u8         if_in_errors_high[0x20];
1863
1864         u8         if_in_errors_low[0x20];
1865
1866         u8         if_in_unknown_protos_high[0x20];
1867
1868         u8         if_in_unknown_protos_low[0x20];
1869
1870         u8         if_out_octets_high[0x20];
1871
1872         u8         if_out_octets_low[0x20];
1873
1874         u8         if_out_ucast_pkts_high[0x20];
1875
1876         u8         if_out_ucast_pkts_low[0x20];
1877
1878         u8         if_out_discards_high[0x20];
1879
1880         u8         if_out_discards_low[0x20];
1881
1882         u8         if_out_errors_high[0x20];
1883
1884         u8         if_out_errors_low[0x20];
1885
1886         u8         if_in_multicast_pkts_high[0x20];
1887
1888         u8         if_in_multicast_pkts_low[0x20];
1889
1890         u8         if_in_broadcast_pkts_high[0x20];
1891
1892         u8         if_in_broadcast_pkts_low[0x20];
1893
1894         u8         if_out_multicast_pkts_high[0x20];
1895
1896         u8         if_out_multicast_pkts_low[0x20];
1897
1898         u8         if_out_broadcast_pkts_high[0x20];
1899
1900         u8         if_out_broadcast_pkts_low[0x20];
1901
1902         u8         reserved_at_340[0x480];
1903 };
1904
1905 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1906         u8         a_frames_transmitted_ok_high[0x20];
1907
1908         u8         a_frames_transmitted_ok_low[0x20];
1909
1910         u8         a_frames_received_ok_high[0x20];
1911
1912         u8         a_frames_received_ok_low[0x20];
1913
1914         u8         a_frame_check_sequence_errors_high[0x20];
1915
1916         u8         a_frame_check_sequence_errors_low[0x20];
1917
1918         u8         a_alignment_errors_high[0x20];
1919
1920         u8         a_alignment_errors_low[0x20];
1921
1922         u8         a_octets_transmitted_ok_high[0x20];
1923
1924         u8         a_octets_transmitted_ok_low[0x20];
1925
1926         u8         a_octets_received_ok_high[0x20];
1927
1928         u8         a_octets_received_ok_low[0x20];
1929
1930         u8         a_multicast_frames_xmitted_ok_high[0x20];
1931
1932         u8         a_multicast_frames_xmitted_ok_low[0x20];
1933
1934         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1935
1936         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1937
1938         u8         a_multicast_frames_received_ok_high[0x20];
1939
1940         u8         a_multicast_frames_received_ok_low[0x20];
1941
1942         u8         a_broadcast_frames_received_ok_high[0x20];
1943
1944         u8         a_broadcast_frames_received_ok_low[0x20];
1945
1946         u8         a_in_range_length_errors_high[0x20];
1947
1948         u8         a_in_range_length_errors_low[0x20];
1949
1950         u8         a_out_of_range_length_field_high[0x20];
1951
1952         u8         a_out_of_range_length_field_low[0x20];
1953
1954         u8         a_frame_too_long_errors_high[0x20];
1955
1956         u8         a_frame_too_long_errors_low[0x20];
1957
1958         u8         a_symbol_error_during_carrier_high[0x20];
1959
1960         u8         a_symbol_error_during_carrier_low[0x20];
1961
1962         u8         a_mac_control_frames_transmitted_high[0x20];
1963
1964         u8         a_mac_control_frames_transmitted_low[0x20];
1965
1966         u8         a_mac_control_frames_received_high[0x20];
1967
1968         u8         a_mac_control_frames_received_low[0x20];
1969
1970         u8         a_unsupported_opcodes_received_high[0x20];
1971
1972         u8         a_unsupported_opcodes_received_low[0x20];
1973
1974         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1975
1976         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1977
1978         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1979
1980         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1981
1982         u8         reserved_at_4c0[0x300];
1983 };
1984
1985 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1986         u8         life_time_counter_high[0x20];
1987
1988         u8         life_time_counter_low[0x20];
1989
1990         u8         rx_errors[0x20];
1991
1992         u8         tx_errors[0x20];
1993
1994         u8         l0_to_recovery_eieos[0x20];
1995
1996         u8         l0_to_recovery_ts[0x20];
1997
1998         u8         l0_to_recovery_framing[0x20];
1999
2000         u8         l0_to_recovery_retrain[0x20];
2001
2002         u8         crc_error_dllp[0x20];
2003
2004         u8         crc_error_tlp[0x20];
2005
2006         u8         tx_overflow_buffer_pkt_high[0x20];
2007
2008         u8         tx_overflow_buffer_pkt_low[0x20];
2009
2010         u8         outbound_stalled_reads[0x20];
2011
2012         u8         outbound_stalled_writes[0x20];
2013
2014         u8         outbound_stalled_reads_events[0x20];
2015
2016         u8         outbound_stalled_writes_events[0x20];
2017
2018         u8         reserved_at_200[0x5c0];
2019 };
2020
2021 struct mlx5_ifc_cmd_inter_comp_event_bits {
2022         u8         command_completion_vector[0x20];
2023
2024         u8         reserved_at_20[0xc0];
2025 };
2026
2027 struct mlx5_ifc_stall_vl_event_bits {
2028         u8         reserved_at_0[0x18];
2029         u8         port_num[0x1];
2030         u8         reserved_at_19[0x3];
2031         u8         vl[0x4];
2032
2033         u8         reserved_at_20[0xa0];
2034 };
2035
2036 struct mlx5_ifc_db_bf_congestion_event_bits {
2037         u8         event_subtype[0x8];
2038         u8         reserved_at_8[0x8];
2039         u8         congestion_level[0x8];
2040         u8         reserved_at_18[0x8];
2041
2042         u8         reserved_at_20[0xa0];
2043 };
2044
2045 struct mlx5_ifc_gpio_event_bits {
2046         u8         reserved_at_0[0x60];
2047
2048         u8         gpio_event_hi[0x20];
2049
2050         u8         gpio_event_lo[0x20];
2051
2052         u8         reserved_at_a0[0x40];
2053 };
2054
2055 struct mlx5_ifc_port_state_change_event_bits {
2056         u8         reserved_at_0[0x40];
2057
2058         u8         port_num[0x4];
2059         u8         reserved_at_44[0x1c];
2060
2061         u8         reserved_at_60[0x80];
2062 };
2063
2064 struct mlx5_ifc_dropped_packet_logged_bits {
2065         u8         reserved_at_0[0xe0];
2066 };
2067
2068 enum {
2069         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2070         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2071 };
2072
2073 struct mlx5_ifc_cq_error_bits {
2074         u8         reserved_at_0[0x8];
2075         u8         cqn[0x18];
2076
2077         u8         reserved_at_20[0x20];
2078
2079         u8         reserved_at_40[0x18];
2080         u8         syndrome[0x8];
2081
2082         u8         reserved_at_60[0x80];
2083 };
2084
2085 struct mlx5_ifc_rdma_page_fault_event_bits {
2086         u8         bytes_committed[0x20];
2087
2088         u8         r_key[0x20];
2089
2090         u8         reserved_at_40[0x10];
2091         u8         packet_len[0x10];
2092
2093         u8         rdma_op_len[0x20];
2094
2095         u8         rdma_va[0x40];
2096
2097         u8         reserved_at_c0[0x5];
2098         u8         rdma[0x1];
2099         u8         write[0x1];
2100         u8         requestor[0x1];
2101         u8         qp_number[0x18];
2102 };
2103
2104 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2105         u8         bytes_committed[0x20];
2106
2107         u8         reserved_at_20[0x10];
2108         u8         wqe_index[0x10];
2109
2110         u8         reserved_at_40[0x10];
2111         u8         len[0x10];
2112
2113         u8         reserved_at_60[0x60];
2114
2115         u8         reserved_at_c0[0x5];
2116         u8         rdma[0x1];
2117         u8         write_read[0x1];
2118         u8         requestor[0x1];
2119         u8         qpn[0x18];
2120 };
2121
2122 struct mlx5_ifc_qp_events_bits {
2123         u8         reserved_at_0[0xa0];
2124
2125         u8         type[0x8];
2126         u8         reserved_at_a8[0x18];
2127
2128         u8         reserved_at_c0[0x8];
2129         u8         qpn_rqn_sqn[0x18];
2130 };
2131
2132 struct mlx5_ifc_dct_events_bits {
2133         u8         reserved_at_0[0xc0];
2134
2135         u8         reserved_at_c0[0x8];
2136         u8         dct_number[0x18];
2137 };
2138
2139 struct mlx5_ifc_comp_event_bits {
2140         u8         reserved_at_0[0xc0];
2141
2142         u8         reserved_at_c0[0x8];
2143         u8         cq_number[0x18];
2144 };
2145
2146 enum {
2147         MLX5_QPC_STATE_RST        = 0x0,
2148         MLX5_QPC_STATE_INIT       = 0x1,
2149         MLX5_QPC_STATE_RTR        = 0x2,
2150         MLX5_QPC_STATE_RTS        = 0x3,
2151         MLX5_QPC_STATE_SQER       = 0x4,
2152         MLX5_QPC_STATE_ERR        = 0x6,
2153         MLX5_QPC_STATE_SQD        = 0x7,
2154         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2155 };
2156
2157 enum {
2158         MLX5_QPC_ST_RC            = 0x0,
2159         MLX5_QPC_ST_UC            = 0x1,
2160         MLX5_QPC_ST_UD            = 0x2,
2161         MLX5_QPC_ST_XRC           = 0x3,
2162         MLX5_QPC_ST_DCI           = 0x5,
2163         MLX5_QPC_ST_QP0           = 0x7,
2164         MLX5_QPC_ST_QP1           = 0x8,
2165         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2166         MLX5_QPC_ST_REG_UMR       = 0xc,
2167 };
2168
2169 enum {
2170         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2171         MLX5_QPC_PM_STATE_REARM     = 0x1,
2172         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2173         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2174 };
2175
2176 enum {
2177         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2178 };
2179
2180 enum {
2181         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2182         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2183 };
2184
2185 enum {
2186         MLX5_QPC_MTU_256_BYTES        = 0x1,
2187         MLX5_QPC_MTU_512_BYTES        = 0x2,
2188         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2189         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2190         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2191         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2192 };
2193
2194 enum {
2195         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2196         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2197         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2198         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2199         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2200         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2201         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2202         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2203 };
2204
2205 enum {
2206         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2207         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2208         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2209 };
2210
2211 enum {
2212         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2213         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2214         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2215 };
2216
2217 struct mlx5_ifc_qpc_bits {
2218         u8         state[0x4];
2219         u8         lag_tx_port_affinity[0x4];
2220         u8         st[0x8];
2221         u8         reserved_at_10[0x3];
2222         u8         pm_state[0x2];
2223         u8         reserved_at_15[0x3];
2224         u8         offload_type[0x4];
2225         u8         end_padding_mode[0x2];
2226         u8         reserved_at_1e[0x2];
2227
2228         u8         wq_signature[0x1];
2229         u8         block_lb_mc[0x1];
2230         u8         atomic_like_write_en[0x1];
2231         u8         latency_sensitive[0x1];
2232         u8         reserved_at_24[0x1];
2233         u8         drain_sigerr[0x1];
2234         u8         reserved_at_26[0x2];
2235         u8         pd[0x18];
2236
2237         u8         mtu[0x3];
2238         u8         log_msg_max[0x5];
2239         u8         reserved_at_48[0x1];
2240         u8         log_rq_size[0x4];
2241         u8         log_rq_stride[0x3];
2242         u8         no_sq[0x1];
2243         u8         log_sq_size[0x4];
2244         u8         reserved_at_55[0x6];
2245         u8         rlky[0x1];
2246         u8         ulp_stateless_offload_mode[0x4];
2247
2248         u8         counter_set_id[0x8];
2249         u8         uar_page[0x18];
2250
2251         u8         reserved_at_80[0x8];
2252         u8         user_index[0x18];
2253
2254         u8         reserved_at_a0[0x3];
2255         u8         log_page_size[0x5];
2256         u8         remote_qpn[0x18];
2257
2258         struct mlx5_ifc_ads_bits primary_address_path;
2259
2260         struct mlx5_ifc_ads_bits secondary_address_path;
2261
2262         u8         log_ack_req_freq[0x4];
2263         u8         reserved_at_384[0x4];
2264         u8         log_sra_max[0x3];
2265         u8         reserved_at_38b[0x2];
2266         u8         retry_count[0x3];
2267         u8         rnr_retry[0x3];
2268         u8         reserved_at_393[0x1];
2269         u8         fre[0x1];
2270         u8         cur_rnr_retry[0x3];
2271         u8         cur_retry_count[0x3];
2272         u8         reserved_at_39b[0x5];
2273
2274         u8         reserved_at_3a0[0x20];
2275
2276         u8         reserved_at_3c0[0x8];
2277         u8         next_send_psn[0x18];
2278
2279         u8         reserved_at_3e0[0x8];
2280         u8         cqn_snd[0x18];
2281
2282         u8         reserved_at_400[0x8];
2283         u8         deth_sqpn[0x18];
2284
2285         u8         reserved_at_420[0x20];
2286
2287         u8         reserved_at_440[0x8];
2288         u8         last_acked_psn[0x18];
2289
2290         u8         reserved_at_460[0x8];
2291         u8         ssn[0x18];
2292
2293         u8         reserved_at_480[0x8];
2294         u8         log_rra_max[0x3];
2295         u8         reserved_at_48b[0x1];
2296         u8         atomic_mode[0x4];
2297         u8         rre[0x1];
2298         u8         rwe[0x1];
2299         u8         rae[0x1];
2300         u8         reserved_at_493[0x1];
2301         u8         page_offset[0x6];
2302         u8         reserved_at_49a[0x3];
2303         u8         cd_slave_receive[0x1];
2304         u8         cd_slave_send[0x1];
2305         u8         cd_master[0x1];
2306
2307         u8         reserved_at_4a0[0x3];
2308         u8         min_rnr_nak[0x5];
2309         u8         next_rcv_psn[0x18];
2310
2311         u8         reserved_at_4c0[0x8];
2312         u8         xrcd[0x18];
2313
2314         u8         reserved_at_4e0[0x8];
2315         u8         cqn_rcv[0x18];
2316
2317         u8         dbr_addr[0x40];
2318
2319         u8         q_key[0x20];
2320
2321         u8         reserved_at_560[0x5];
2322         u8         rq_type[0x3];
2323         u8         srqn_rmpn_xrqn[0x18];
2324
2325         u8         reserved_at_580[0x8];
2326         u8         rmsn[0x18];
2327
2328         u8         hw_sq_wqebb_counter[0x10];
2329         u8         sw_sq_wqebb_counter[0x10];
2330
2331         u8         hw_rq_counter[0x20];
2332
2333         u8         sw_rq_counter[0x20];
2334
2335         u8         reserved_at_600[0x20];
2336
2337         u8         reserved_at_620[0xf];
2338         u8         cgs[0x1];
2339         u8         cs_req[0x8];
2340         u8         cs_res[0x8];
2341
2342         u8         dc_access_key[0x40];
2343
2344         u8         reserved_at_680[0xc0];
2345 };
2346
2347 struct mlx5_ifc_roce_addr_layout_bits {
2348         u8         source_l3_address[16][0x8];
2349
2350         u8         reserved_at_80[0x3];
2351         u8         vlan_valid[0x1];
2352         u8         vlan_id[0xc];
2353         u8         source_mac_47_32[0x10];
2354
2355         u8         source_mac_31_0[0x20];
2356
2357         u8         reserved_at_c0[0x14];
2358         u8         roce_l3_type[0x4];
2359         u8         roce_version[0x8];
2360
2361         u8         reserved_at_e0[0x20];
2362 };
2363
2364 union mlx5_ifc_hca_cap_union_bits {
2365         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2366         struct mlx5_ifc_odp_cap_bits odp_cap;
2367         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2368         struct mlx5_ifc_roce_cap_bits roce_cap;
2369         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2370         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2371         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2372         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2373         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2374         struct mlx5_ifc_qos_cap_bits qos_cap;
2375         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2376         u8         reserved_at_0[0x8000];
2377 };
2378
2379 enum {
2380         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2381         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2382         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2383         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2384         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2385         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2386         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2387         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2388         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2389 };
2390
2391 struct mlx5_ifc_vlan_bits {
2392         u8         ethtype[0x10];
2393         u8         prio[0x3];
2394         u8         cfi[0x1];
2395         u8         vid[0xc];
2396 };
2397
2398 struct mlx5_ifc_flow_context_bits {
2399         struct mlx5_ifc_vlan_bits push_vlan;
2400
2401         u8         group_id[0x20];
2402
2403         u8         reserved_at_40[0x8];
2404         u8         flow_tag[0x18];
2405
2406         u8         reserved_at_60[0x10];
2407         u8         action[0x10];
2408
2409         u8         reserved_at_80[0x8];
2410         u8         destination_list_size[0x18];
2411
2412         u8         reserved_at_a0[0x8];
2413         u8         flow_counter_list_size[0x18];
2414
2415         u8         encap_id[0x20];
2416
2417         u8         modify_header_id[0x20];
2418
2419         u8         reserved_at_100[0x100];
2420
2421         struct mlx5_ifc_fte_match_param_bits match_value;
2422
2423         u8         reserved_at_1200[0x600];
2424
2425         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2426 };
2427
2428 enum {
2429         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2430         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2431 };
2432
2433 struct mlx5_ifc_xrc_srqc_bits {
2434         u8         state[0x4];
2435         u8         log_xrc_srq_size[0x4];
2436         u8         reserved_at_8[0x18];
2437
2438         u8         wq_signature[0x1];
2439         u8         cont_srq[0x1];
2440         u8         reserved_at_22[0x1];
2441         u8         rlky[0x1];
2442         u8         basic_cyclic_rcv_wqe[0x1];
2443         u8         log_rq_stride[0x3];
2444         u8         xrcd[0x18];
2445
2446         u8         page_offset[0x6];
2447         u8         reserved_at_46[0x2];
2448         u8         cqn[0x18];
2449
2450         u8         reserved_at_60[0x20];
2451
2452         u8         user_index_equal_xrc_srqn[0x1];
2453         u8         reserved_at_81[0x1];
2454         u8         log_page_size[0x6];
2455         u8         user_index[0x18];
2456
2457         u8         reserved_at_a0[0x20];
2458
2459         u8         reserved_at_c0[0x8];
2460         u8         pd[0x18];
2461
2462         u8         lwm[0x10];
2463         u8         wqe_cnt[0x10];
2464
2465         u8         reserved_at_100[0x40];
2466
2467         u8         db_record_addr_h[0x20];
2468
2469         u8         db_record_addr_l[0x1e];
2470         u8         reserved_at_17e[0x2];
2471
2472         u8         reserved_at_180[0x80];
2473 };
2474
2475 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2476         u8         counter_error_queues[0x20];
2477
2478         u8         total_error_queues[0x20];
2479
2480         u8         send_queue_priority_update_flow[0x20];
2481
2482         u8         reserved_at_60[0x20];
2483
2484         u8         nic_receive_steering_discard[0x40];
2485
2486         u8         receive_discard_vport_down[0x40];
2487
2488         u8         transmit_discard_vport_down[0x40];
2489
2490         u8         reserved_at_140[0xec0];
2491 };
2492
2493 struct mlx5_ifc_traffic_counter_bits {
2494         u8         packets[0x40];
2495
2496         u8         octets[0x40];
2497 };
2498
2499 struct mlx5_ifc_tisc_bits {
2500         u8         strict_lag_tx_port_affinity[0x1];
2501         u8         reserved_at_1[0x3];
2502         u8         lag_tx_port_affinity[0x04];
2503
2504         u8         reserved_at_8[0x4];
2505         u8         prio[0x4];
2506         u8         reserved_at_10[0x10];
2507
2508         u8         reserved_at_20[0x100];
2509
2510         u8         reserved_at_120[0x8];
2511         u8         transport_domain[0x18];
2512
2513         u8         reserved_at_140[0x8];
2514         u8         underlay_qpn[0x18];
2515         u8         reserved_at_160[0x3a0];
2516 };
2517
2518 enum {
2519         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2520         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2521 };
2522
2523 enum {
2524         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2525         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2526 };
2527
2528 enum {
2529         MLX5_RX_HASH_FN_NONE           = 0x0,
2530         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2531         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2532 };
2533
2534 enum {
2535         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2536         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2537 };
2538
2539 struct mlx5_ifc_tirc_bits {
2540         u8         reserved_at_0[0x20];
2541
2542         u8         disp_type[0x4];
2543         u8         reserved_at_24[0x1c];
2544
2545         u8         reserved_at_40[0x40];
2546
2547         u8         reserved_at_80[0x4];
2548         u8         lro_timeout_period_usecs[0x10];
2549         u8         lro_enable_mask[0x4];
2550         u8         lro_max_ip_payload_size[0x8];
2551
2552         u8         reserved_at_a0[0x40];
2553
2554         u8         reserved_at_e0[0x8];
2555         u8         inline_rqn[0x18];
2556
2557         u8         rx_hash_symmetric[0x1];
2558         u8         reserved_at_101[0x1];
2559         u8         tunneled_offload_en[0x1];
2560         u8         reserved_at_103[0x5];
2561         u8         indirect_table[0x18];
2562
2563         u8         rx_hash_fn[0x4];
2564         u8         reserved_at_124[0x2];
2565         u8         self_lb_block[0x2];
2566         u8         transport_domain[0x18];
2567
2568         u8         rx_hash_toeplitz_key[10][0x20];
2569
2570         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2571
2572         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2573
2574         u8         reserved_at_2c0[0x4c0];
2575 };
2576
2577 enum {
2578         MLX5_SRQC_STATE_GOOD   = 0x0,
2579         MLX5_SRQC_STATE_ERROR  = 0x1,
2580 };
2581
2582 struct mlx5_ifc_srqc_bits {
2583         u8         state[0x4];
2584         u8         log_srq_size[0x4];
2585         u8         reserved_at_8[0x18];
2586
2587         u8         wq_signature[0x1];
2588         u8         cont_srq[0x1];
2589         u8         reserved_at_22[0x1];
2590         u8         rlky[0x1];
2591         u8         reserved_at_24[0x1];
2592         u8         log_rq_stride[0x3];
2593         u8         xrcd[0x18];
2594
2595         u8         page_offset[0x6];
2596         u8         reserved_at_46[0x2];
2597         u8         cqn[0x18];
2598
2599         u8         reserved_at_60[0x20];
2600
2601         u8         reserved_at_80[0x2];
2602         u8         log_page_size[0x6];
2603         u8         reserved_at_88[0x18];
2604
2605         u8         reserved_at_a0[0x20];
2606
2607         u8         reserved_at_c0[0x8];
2608         u8         pd[0x18];
2609
2610         u8         lwm[0x10];
2611         u8         wqe_cnt[0x10];
2612
2613         u8         reserved_at_100[0x40];
2614
2615         u8         dbr_addr[0x40];
2616
2617         u8         reserved_at_180[0x80];
2618 };
2619
2620 enum {
2621         MLX5_SQC_STATE_RST  = 0x0,
2622         MLX5_SQC_STATE_RDY  = 0x1,
2623         MLX5_SQC_STATE_ERR  = 0x3,
2624 };
2625
2626 struct mlx5_ifc_sqc_bits {
2627         u8         rlky[0x1];
2628         u8         cd_master[0x1];
2629         u8         fre[0x1];
2630         u8         flush_in_error_en[0x1];
2631         u8         allow_multi_pkt_send_wqe[0x1];
2632         u8         min_wqe_inline_mode[0x3];
2633         u8         state[0x4];
2634         u8         reg_umr[0x1];
2635         u8         allow_swp[0x1];
2636         u8         hairpin[0x1];
2637         u8         reserved_at_f[0x11];
2638
2639         u8         reserved_at_20[0x8];
2640         u8         user_index[0x18];
2641
2642         u8         reserved_at_40[0x8];
2643         u8         cqn[0x18];
2644
2645         u8         reserved_at_60[0x8];
2646         u8         hairpin_peer_rq[0x18];
2647
2648         u8         reserved_at_80[0x10];
2649         u8         hairpin_peer_vhca[0x10];
2650
2651         u8         reserved_at_a0[0x50];
2652
2653         u8         packet_pacing_rate_limit_index[0x10];
2654         u8         tis_lst_sz[0x10];
2655         u8         reserved_at_110[0x10];
2656
2657         u8         reserved_at_120[0x40];
2658
2659         u8         reserved_at_160[0x8];
2660         u8         tis_num_0[0x18];
2661
2662         struct mlx5_ifc_wq_bits wq;
2663 };
2664
2665 enum {
2666         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2667         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2668         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2669         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2670 };
2671
2672 struct mlx5_ifc_scheduling_context_bits {
2673         u8         element_type[0x8];
2674         u8         reserved_at_8[0x18];
2675
2676         u8         element_attributes[0x20];
2677
2678         u8         parent_element_id[0x20];
2679
2680         u8         reserved_at_60[0x40];
2681
2682         u8         bw_share[0x20];
2683
2684         u8         max_average_bw[0x20];
2685
2686         u8         reserved_at_e0[0x120];
2687 };
2688
2689 struct mlx5_ifc_rqtc_bits {
2690         u8         reserved_at_0[0xa0];
2691
2692         u8         reserved_at_a0[0x10];
2693         u8         rqt_max_size[0x10];
2694
2695         u8         reserved_at_c0[0x10];
2696         u8         rqt_actual_size[0x10];
2697
2698         u8         reserved_at_e0[0x6a0];
2699
2700         struct mlx5_ifc_rq_num_bits rq_num[0];
2701 };
2702
2703 enum {
2704         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2705         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2706 };
2707
2708 enum {
2709         MLX5_RQC_STATE_RST  = 0x0,
2710         MLX5_RQC_STATE_RDY  = 0x1,
2711         MLX5_RQC_STATE_ERR  = 0x3,
2712 };
2713
2714 struct mlx5_ifc_rqc_bits {
2715         u8         rlky[0x1];
2716         u8         delay_drop_en[0x1];
2717         u8         scatter_fcs[0x1];
2718         u8         vsd[0x1];
2719         u8         mem_rq_type[0x4];
2720         u8         state[0x4];
2721         u8         reserved_at_c[0x1];
2722         u8         flush_in_error_en[0x1];
2723         u8         hairpin[0x1];
2724         u8         reserved_at_f[0x11];
2725
2726         u8         reserved_at_20[0x8];
2727         u8         user_index[0x18];
2728
2729         u8         reserved_at_40[0x8];
2730         u8         cqn[0x18];
2731
2732         u8         counter_set_id[0x8];
2733         u8         reserved_at_68[0x18];
2734
2735         u8         reserved_at_80[0x8];
2736         u8         rmpn[0x18];
2737
2738         u8         reserved_at_a0[0x8];
2739         u8         hairpin_peer_sq[0x18];
2740
2741         u8         reserved_at_c0[0x10];
2742         u8         hairpin_peer_vhca[0x10];
2743
2744         u8         reserved_at_e0[0xa0];
2745
2746         struct mlx5_ifc_wq_bits wq;
2747 };
2748
2749 enum {
2750         MLX5_RMPC_STATE_RDY  = 0x1,
2751         MLX5_RMPC_STATE_ERR  = 0x3,
2752 };
2753
2754 struct mlx5_ifc_rmpc_bits {
2755         u8         reserved_at_0[0x8];
2756         u8         state[0x4];
2757         u8         reserved_at_c[0x14];
2758
2759         u8         basic_cyclic_rcv_wqe[0x1];
2760         u8         reserved_at_21[0x1f];
2761
2762         u8         reserved_at_40[0x140];
2763
2764         struct mlx5_ifc_wq_bits wq;
2765 };
2766
2767 struct mlx5_ifc_nic_vport_context_bits {
2768         u8         reserved_at_0[0x5];
2769         u8         min_wqe_inline_mode[0x3];
2770         u8         reserved_at_8[0x15];
2771         u8         disable_mc_local_lb[0x1];
2772         u8         disable_uc_local_lb[0x1];
2773         u8         roce_en[0x1];
2774
2775         u8         arm_change_event[0x1];
2776         u8         reserved_at_21[0x1a];
2777         u8         event_on_mtu[0x1];
2778         u8         event_on_promisc_change[0x1];
2779         u8         event_on_vlan_change[0x1];
2780         u8         event_on_mc_address_change[0x1];
2781         u8         event_on_uc_address_change[0x1];
2782
2783         u8         reserved_at_40[0xc];
2784
2785         u8         affiliation_criteria[0x4];
2786         u8         affiliated_vhca_id[0x10];
2787
2788         u8         reserved_at_60[0xd0];
2789
2790         u8         mtu[0x10];
2791
2792         u8         system_image_guid[0x40];
2793         u8         port_guid[0x40];
2794         u8         node_guid[0x40];
2795
2796         u8         reserved_at_200[0x140];
2797         u8         qkey_violation_counter[0x10];
2798         u8         reserved_at_350[0x430];
2799
2800         u8         promisc_uc[0x1];
2801         u8         promisc_mc[0x1];
2802         u8         promisc_all[0x1];
2803         u8         reserved_at_783[0x2];
2804         u8         allowed_list_type[0x3];
2805         u8         reserved_at_788[0xc];
2806         u8         allowed_list_size[0xc];
2807
2808         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2809
2810         u8         reserved_at_7e0[0x20];
2811
2812         u8         current_uc_mac_address[0][0x40];
2813 };
2814
2815 enum {
2816         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2817         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2818         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2819         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2820         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2821 };
2822
2823 struct mlx5_ifc_mkc_bits {
2824         u8         reserved_at_0[0x1];
2825         u8         free[0x1];
2826         u8         reserved_at_2[0x1];
2827         u8         access_mode_4_2[0x3];
2828         u8         reserved_at_6[0x7];
2829         u8         relaxed_ordering_write[0x1];
2830         u8         reserved_at_e[0x1];
2831         u8         small_fence_on_rdma_read_response[0x1];
2832         u8         umr_en[0x1];
2833         u8         a[0x1];
2834         u8         rw[0x1];
2835         u8         rr[0x1];
2836         u8         lw[0x1];
2837         u8         lr[0x1];
2838         u8         access_mode_1_0[0x2];
2839         u8         reserved_at_18[0x8];
2840
2841         u8         qpn[0x18];
2842         u8         mkey_7_0[0x8];
2843
2844         u8         reserved_at_40[0x20];
2845
2846         u8         length64[0x1];
2847         u8         bsf_en[0x1];
2848         u8         sync_umr[0x1];
2849         u8         reserved_at_63[0x2];
2850         u8         expected_sigerr_count[0x1];
2851         u8         reserved_at_66[0x1];
2852         u8         en_rinval[0x1];
2853         u8         pd[0x18];
2854
2855         u8         start_addr[0x40];
2856
2857         u8         len[0x40];
2858
2859         u8         bsf_octword_size[0x20];
2860
2861         u8         reserved_at_120[0x80];
2862
2863         u8         translations_octword_size[0x20];
2864
2865         u8         reserved_at_1c0[0x1b];
2866         u8         log_page_size[0x5];
2867
2868         u8         reserved_at_1e0[0x20];
2869 };
2870
2871 struct mlx5_ifc_pkey_bits {
2872         u8         reserved_at_0[0x10];
2873         u8         pkey[0x10];
2874 };
2875
2876 struct mlx5_ifc_array128_auto_bits {
2877         u8         array128_auto[16][0x8];
2878 };
2879
2880 struct mlx5_ifc_hca_vport_context_bits {
2881         u8         field_select[0x20];
2882
2883         u8         reserved_at_20[0xe0];
2884
2885         u8         sm_virt_aware[0x1];
2886         u8         has_smi[0x1];
2887         u8         has_raw[0x1];
2888         u8         grh_required[0x1];
2889         u8         reserved_at_104[0xc];
2890         u8         port_physical_state[0x4];
2891         u8         vport_state_policy[0x4];
2892         u8         port_state[0x4];
2893         u8         vport_state[0x4];
2894
2895         u8         reserved_at_120[0x20];
2896
2897         u8         system_image_guid[0x40];
2898
2899         u8         port_guid[0x40];
2900
2901         u8         node_guid[0x40];
2902
2903         u8         cap_mask1[0x20];
2904
2905         u8         cap_mask1_field_select[0x20];
2906
2907         u8         cap_mask2[0x20];
2908
2909         u8         cap_mask2_field_select[0x20];
2910
2911         u8         reserved_at_280[0x80];
2912
2913         u8         lid[0x10];
2914         u8         reserved_at_310[0x4];
2915         u8         init_type_reply[0x4];
2916         u8         lmc[0x3];
2917         u8         subnet_timeout[0x5];
2918
2919         u8         sm_lid[0x10];
2920         u8         sm_sl[0x4];
2921         u8         reserved_at_334[0xc];
2922
2923         u8         qkey_violation_counter[0x10];
2924         u8         pkey_violation_counter[0x10];
2925
2926         u8         reserved_at_360[0xca0];
2927 };
2928
2929 struct mlx5_ifc_esw_vport_context_bits {
2930         u8         reserved_at_0[0x3];
2931         u8         vport_svlan_strip[0x1];
2932         u8         vport_cvlan_strip[0x1];
2933         u8         vport_svlan_insert[0x1];
2934         u8         vport_cvlan_insert[0x2];
2935         u8         reserved_at_8[0x18];
2936
2937         u8         reserved_at_20[0x20];
2938
2939         u8         svlan_cfi[0x1];
2940         u8         svlan_pcp[0x3];
2941         u8         svlan_id[0xc];
2942         u8         cvlan_cfi[0x1];
2943         u8         cvlan_pcp[0x3];
2944         u8         cvlan_id[0xc];
2945
2946         u8         reserved_at_60[0x7a0];
2947 };
2948
2949 enum {
2950         MLX5_EQC_STATUS_OK                = 0x0,
2951         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2952 };
2953
2954 enum {
2955         MLX5_EQC_ST_ARMED  = 0x9,
2956         MLX5_EQC_ST_FIRED  = 0xa,
2957 };
2958
2959 struct mlx5_ifc_eqc_bits {
2960         u8         status[0x4];
2961         u8         reserved_at_4[0x9];
2962         u8         ec[0x1];
2963         u8         oi[0x1];
2964         u8         reserved_at_f[0x5];
2965         u8         st[0x4];
2966         u8         reserved_at_18[0x8];
2967
2968         u8         reserved_at_20[0x20];
2969
2970         u8         reserved_at_40[0x14];
2971         u8         page_offset[0x6];
2972         u8         reserved_at_5a[0x6];
2973
2974         u8         reserved_at_60[0x3];
2975         u8         log_eq_size[0x5];
2976         u8         uar_page[0x18];
2977
2978         u8         reserved_at_80[0x20];
2979
2980         u8         reserved_at_a0[0x18];
2981         u8         intr[0x8];
2982
2983         u8         reserved_at_c0[0x3];
2984         u8         log_page_size[0x5];
2985         u8         reserved_at_c8[0x18];
2986
2987         u8         reserved_at_e0[0x60];
2988
2989         u8         reserved_at_140[0x8];
2990         u8         consumer_counter[0x18];
2991
2992         u8         reserved_at_160[0x8];
2993         u8         producer_counter[0x18];
2994
2995         u8         reserved_at_180[0x80];
2996 };
2997
2998 enum {
2999         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3000         MLX5_DCTC_STATE_DRAINING  = 0x1,
3001         MLX5_DCTC_STATE_DRAINED   = 0x2,
3002 };
3003
3004 enum {
3005         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3006         MLX5_DCTC_CS_RES_NA         = 0x1,
3007         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3008 };
3009
3010 enum {
3011         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3012         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3013         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3014         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3015         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3016 };
3017
3018 struct mlx5_ifc_dctc_bits {
3019         u8         reserved_at_0[0x4];
3020         u8         state[0x4];
3021         u8         reserved_at_8[0x18];
3022
3023         u8         reserved_at_20[0x8];
3024         u8         user_index[0x18];
3025
3026         u8         reserved_at_40[0x8];
3027         u8         cqn[0x18];
3028
3029         u8         counter_set_id[0x8];
3030         u8         atomic_mode[0x4];
3031         u8         rre[0x1];
3032         u8         rwe[0x1];
3033         u8         rae[0x1];
3034         u8         atomic_like_write_en[0x1];
3035         u8         latency_sensitive[0x1];
3036         u8         rlky[0x1];
3037         u8         free_ar[0x1];
3038         u8         reserved_at_73[0xd];
3039
3040         u8         reserved_at_80[0x8];
3041         u8         cs_res[0x8];
3042         u8         reserved_at_90[0x3];
3043         u8         min_rnr_nak[0x5];
3044         u8         reserved_at_98[0x8];
3045
3046         u8         reserved_at_a0[0x8];
3047         u8         srqn_xrqn[0x18];
3048
3049         u8         reserved_at_c0[0x8];
3050         u8         pd[0x18];
3051
3052         u8         tclass[0x8];
3053         u8         reserved_at_e8[0x4];
3054         u8         flow_label[0x14];
3055
3056         u8         dc_access_key[0x40];
3057
3058         u8         reserved_at_140[0x5];
3059         u8         mtu[0x3];
3060         u8         port[0x8];
3061         u8         pkey_index[0x10];
3062
3063         u8         reserved_at_160[0x8];
3064         u8         my_addr_index[0x8];
3065         u8         reserved_at_170[0x8];
3066         u8         hop_limit[0x8];
3067
3068         u8         dc_access_key_violation_count[0x20];
3069
3070         u8         reserved_at_1a0[0x14];
3071         u8         dei_cfi[0x1];
3072         u8         eth_prio[0x3];
3073         u8         ecn[0x2];
3074         u8         dscp[0x6];
3075
3076         u8         reserved_at_1c0[0x40];
3077 };
3078
3079 enum {
3080         MLX5_CQC_STATUS_OK             = 0x0,
3081         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3082         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3083 };
3084
3085 enum {
3086         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3087         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3088 };
3089
3090 enum {
3091         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3092         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3093         MLX5_CQC_ST_FIRED                                 = 0xa,
3094 };
3095
3096 enum {
3097         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3098         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3099         MLX5_CQ_PERIOD_NUM_MODES
3100 };
3101
3102 struct mlx5_ifc_cqc_bits {
3103         u8         status[0x4];
3104         u8         reserved_at_4[0x4];
3105         u8         cqe_sz[0x3];
3106         u8         cc[0x1];
3107         u8         reserved_at_c[0x1];
3108         u8         scqe_break_moderation_en[0x1];
3109         u8         oi[0x1];
3110         u8         cq_period_mode[0x2];
3111         u8         cqe_comp_en[0x1];
3112         u8         mini_cqe_res_format[0x2];
3113         u8         st[0x4];
3114         u8         reserved_at_18[0x8];
3115
3116         u8         reserved_at_20[0x20];
3117
3118         u8         reserved_at_40[0x14];
3119         u8         page_offset[0x6];
3120         u8         reserved_at_5a[0x6];
3121
3122         u8         reserved_at_60[0x3];
3123         u8         log_cq_size[0x5];
3124         u8         uar_page[0x18];
3125
3126         u8         reserved_at_80[0x4];
3127         u8         cq_period[0xc];
3128         u8         cq_max_count[0x10];
3129
3130         u8         reserved_at_a0[0x18];
3131         u8         c_eqn[0x8];
3132
3133         u8         reserved_at_c0[0x3];
3134         u8         log_page_size[0x5];
3135         u8         reserved_at_c8[0x18];
3136
3137         u8         reserved_at_e0[0x20];
3138
3139         u8         reserved_at_100[0x8];
3140         u8         last_notified_index[0x18];
3141
3142         u8         reserved_at_120[0x8];
3143         u8         last_solicit_index[0x18];
3144
3145         u8         reserved_at_140[0x8];
3146         u8         consumer_counter[0x18];
3147
3148         u8         reserved_at_160[0x8];
3149         u8         producer_counter[0x18];
3150
3151         u8         reserved_at_180[0x40];
3152
3153         u8         dbr_addr[0x40];
3154 };
3155
3156 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3157         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3158         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3159         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3160         u8         reserved_at_0[0x800];
3161 };
3162
3163 struct mlx5_ifc_query_adapter_param_block_bits {
3164         u8         reserved_at_0[0xc0];
3165
3166         u8         reserved_at_c0[0x8];
3167         u8         ieee_vendor_id[0x18];
3168
3169         u8         reserved_at_e0[0x10];
3170         u8         vsd_vendor_id[0x10];
3171
3172         u8         vsd[208][0x8];
3173
3174         u8         vsd_contd_psid[16][0x8];
3175 };
3176
3177 enum {
3178         MLX5_XRQC_STATE_GOOD   = 0x0,
3179         MLX5_XRQC_STATE_ERROR  = 0x1,
3180 };
3181
3182 enum {
3183         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3184         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3185 };
3186
3187 enum {
3188         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3189 };
3190
3191 struct mlx5_ifc_tag_matching_topology_context_bits {
3192         u8         log_matching_list_sz[0x4];
3193         u8         reserved_at_4[0xc];
3194         u8         append_next_index[0x10];
3195
3196         u8         sw_phase_cnt[0x10];
3197         u8         hw_phase_cnt[0x10];
3198
3199         u8         reserved_at_40[0x40];
3200 };
3201
3202 struct mlx5_ifc_xrqc_bits {
3203         u8         state[0x4];
3204         u8         rlkey[0x1];
3205         u8         reserved_at_5[0xf];
3206         u8         topology[0x4];
3207         u8         reserved_at_18[0x4];
3208         u8         offload[0x4];
3209
3210         u8         reserved_at_20[0x8];
3211         u8         user_index[0x18];
3212
3213         u8         reserved_at_40[0x8];
3214         u8         cqn[0x18];
3215
3216         u8         reserved_at_60[0xa0];
3217
3218         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3219
3220         u8         reserved_at_180[0x280];
3221
3222         struct mlx5_ifc_wq_bits wq;
3223 };
3224
3225 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3226         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3227         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3228         u8         reserved_at_0[0x20];
3229 };
3230
3231 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3232         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3233         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3234         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3235         u8         reserved_at_0[0x20];
3236 };
3237
3238 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3239         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3240         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3241         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3242         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3243         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3244         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3245         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3246         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3247         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3248         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3249         u8         reserved_at_0[0x7c0];
3250 };
3251
3252 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3253         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3254         u8         reserved_at_0[0x7c0];
3255 };
3256
3257 union mlx5_ifc_event_auto_bits {
3258         struct mlx5_ifc_comp_event_bits comp_event;
3259         struct mlx5_ifc_dct_events_bits dct_events;
3260         struct mlx5_ifc_qp_events_bits qp_events;
3261         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3262         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3263         struct mlx5_ifc_cq_error_bits cq_error;
3264         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3265         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3266         struct mlx5_ifc_gpio_event_bits gpio_event;
3267         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3268         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3269         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3270         u8         reserved_at_0[0xe0];
3271 };
3272
3273 struct mlx5_ifc_health_buffer_bits {
3274         u8         reserved_at_0[0x100];
3275
3276         u8         assert_existptr[0x20];
3277
3278         u8         assert_callra[0x20];
3279
3280         u8         reserved_at_140[0x40];
3281
3282         u8         fw_version[0x20];
3283
3284         u8         hw_id[0x20];
3285
3286         u8         reserved_at_1c0[0x20];
3287
3288         u8         irisc_index[0x8];
3289         u8         synd[0x8];
3290         u8         ext_synd[0x10];
3291 };
3292
3293 struct mlx5_ifc_register_loopback_control_bits {
3294         u8         no_lb[0x1];
3295         u8         reserved_at_1[0x7];
3296         u8         port[0x8];
3297         u8         reserved_at_10[0x10];
3298
3299         u8         reserved_at_20[0x60];
3300 };
3301
3302 struct mlx5_ifc_vport_tc_element_bits {
3303         u8         traffic_class[0x4];
3304         u8         reserved_at_4[0xc];
3305         u8         vport_number[0x10];
3306 };
3307
3308 struct mlx5_ifc_vport_element_bits {
3309         u8         reserved_at_0[0x10];
3310         u8         vport_number[0x10];
3311 };
3312
3313 enum {
3314         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3315         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3316         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3317 };
3318
3319 struct mlx5_ifc_tsar_element_bits {
3320         u8         reserved_at_0[0x8];
3321         u8         tsar_type[0x8];
3322         u8         reserved_at_10[0x10];
3323 };
3324
3325 enum {
3326         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3327         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3328 };
3329
3330 struct mlx5_ifc_teardown_hca_out_bits {
3331         u8         status[0x8];
3332         u8         reserved_at_8[0x18];
3333
3334         u8         syndrome[0x20];
3335
3336         u8         reserved_at_40[0x3f];
3337
3338         u8         force_state[0x1];
3339 };
3340
3341 enum {
3342         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3343         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3344 };
3345
3346 struct mlx5_ifc_teardown_hca_in_bits {
3347         u8         opcode[0x10];
3348         u8         reserved_at_10[0x10];
3349
3350         u8         reserved_at_20[0x10];
3351         u8         op_mod[0x10];
3352
3353         u8         reserved_at_40[0x10];
3354         u8         profile[0x10];
3355
3356         u8         reserved_at_60[0x20];
3357 };
3358
3359 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3360         u8         status[0x8];
3361         u8         reserved_at_8[0x18];
3362
3363         u8         syndrome[0x20];
3364
3365         u8         reserved_at_40[0x40];
3366 };
3367
3368 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3369         u8         opcode[0x10];
3370         u8         reserved_at_10[0x10];
3371
3372         u8         reserved_at_20[0x10];
3373         u8         op_mod[0x10];
3374
3375         u8         reserved_at_40[0x8];
3376         u8         qpn[0x18];
3377
3378         u8         reserved_at_60[0x20];
3379
3380         u8         opt_param_mask[0x20];
3381
3382         u8         reserved_at_a0[0x20];
3383
3384         struct mlx5_ifc_qpc_bits qpc;
3385
3386         u8         reserved_at_800[0x80];
3387 };
3388
3389 struct mlx5_ifc_sqd2rts_qp_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_at_8[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_at_40[0x40];
3396 };
3397
3398 struct mlx5_ifc_sqd2rts_qp_in_bits {
3399         u8         opcode[0x10];
3400         u8         reserved_at_10[0x10];
3401
3402         u8         reserved_at_20[0x10];
3403         u8         op_mod[0x10];
3404
3405         u8         reserved_at_40[0x8];
3406         u8         qpn[0x18];
3407
3408         u8         reserved_at_60[0x20];
3409
3410         u8         opt_param_mask[0x20];
3411
3412         u8         reserved_at_a0[0x20];
3413
3414         struct mlx5_ifc_qpc_bits qpc;
3415
3416         u8         reserved_at_800[0x80];
3417 };
3418
3419 struct mlx5_ifc_set_roce_address_out_bits {
3420         u8         status[0x8];
3421         u8         reserved_at_8[0x18];
3422
3423         u8         syndrome[0x20];
3424
3425         u8         reserved_at_40[0x40];
3426 };
3427
3428 struct mlx5_ifc_set_roce_address_in_bits {
3429         u8         opcode[0x10];
3430         u8         reserved_at_10[0x10];
3431
3432         u8         reserved_at_20[0x10];
3433         u8         op_mod[0x10];
3434
3435         u8         roce_address_index[0x10];
3436         u8         reserved_at_50[0xc];
3437         u8         vhca_port_num[0x4];
3438
3439         u8         reserved_at_60[0x20];
3440
3441         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3442 };
3443
3444 struct mlx5_ifc_set_mad_demux_out_bits {
3445         u8         status[0x8];
3446         u8         reserved_at_8[0x18];
3447
3448         u8         syndrome[0x20];
3449
3450         u8         reserved_at_40[0x40];
3451 };
3452
3453 enum {
3454         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3455         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3456 };
3457
3458 struct mlx5_ifc_set_mad_demux_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_at_10[0x10];
3461
3462         u8         reserved_at_20[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_at_40[0x20];
3466
3467         u8         reserved_at_60[0x6];
3468         u8         demux_mode[0x2];
3469         u8         reserved_at_68[0x18];
3470 };
3471
3472 struct mlx5_ifc_set_l2_table_entry_out_bits {
3473         u8         status[0x8];
3474         u8         reserved_at_8[0x18];
3475
3476         u8         syndrome[0x20];
3477
3478         u8         reserved_at_40[0x40];
3479 };
3480
3481 struct mlx5_ifc_set_l2_table_entry_in_bits {
3482         u8         opcode[0x10];
3483         u8         reserved_at_10[0x10];
3484
3485         u8         reserved_at_20[0x10];
3486         u8         op_mod[0x10];
3487
3488         u8         reserved_at_40[0x60];
3489
3490         u8         reserved_at_a0[0x8];
3491         u8         table_index[0x18];
3492
3493         u8         reserved_at_c0[0x20];
3494
3495         u8         reserved_at_e0[0x13];
3496         u8         vlan_valid[0x1];
3497         u8         vlan[0xc];
3498
3499         struct mlx5_ifc_mac_address_layout_bits mac_address;
3500
3501         u8         reserved_at_140[0xc0];
3502 };
3503
3504 struct mlx5_ifc_set_issi_out_bits {
3505         u8         status[0x8];
3506         u8         reserved_at_8[0x18];
3507
3508         u8         syndrome[0x20];
3509
3510         u8         reserved_at_40[0x40];
3511 };
3512
3513 struct mlx5_ifc_set_issi_in_bits {
3514         u8         opcode[0x10];
3515         u8         reserved_at_10[0x10];
3516
3517         u8         reserved_at_20[0x10];
3518         u8         op_mod[0x10];
3519
3520         u8         reserved_at_40[0x10];
3521         u8         current_issi[0x10];
3522
3523         u8         reserved_at_60[0x20];
3524 };
3525
3526 struct mlx5_ifc_set_hca_cap_out_bits {
3527         u8         status[0x8];
3528         u8         reserved_at_8[0x18];
3529
3530         u8         syndrome[0x20];
3531
3532         u8         reserved_at_40[0x40];
3533 };
3534
3535 struct mlx5_ifc_set_hca_cap_in_bits {
3536         u8         opcode[0x10];
3537         u8         reserved_at_10[0x10];
3538
3539         u8         reserved_at_20[0x10];
3540         u8         op_mod[0x10];
3541
3542         u8         reserved_at_40[0x40];
3543
3544         union mlx5_ifc_hca_cap_union_bits capability;
3545 };
3546
3547 enum {
3548         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3549         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3550         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3551         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3552 };
3553
3554 struct mlx5_ifc_set_fte_out_bits {
3555         u8         status[0x8];
3556         u8         reserved_at_8[0x18];
3557
3558         u8         syndrome[0x20];
3559
3560         u8         reserved_at_40[0x40];
3561 };
3562
3563 struct mlx5_ifc_set_fte_in_bits {
3564         u8         opcode[0x10];
3565         u8         reserved_at_10[0x10];
3566
3567         u8         reserved_at_20[0x10];
3568         u8         op_mod[0x10];
3569
3570         u8         other_vport[0x1];
3571         u8         reserved_at_41[0xf];
3572         u8         vport_number[0x10];
3573
3574         u8         reserved_at_60[0x20];
3575
3576         u8         table_type[0x8];
3577         u8         reserved_at_88[0x18];
3578
3579         u8         reserved_at_a0[0x8];
3580         u8         table_id[0x18];
3581
3582         u8         reserved_at_c0[0x18];
3583         u8         modify_enable_mask[0x8];
3584
3585         u8         reserved_at_e0[0x20];
3586
3587         u8         flow_index[0x20];
3588
3589         u8         reserved_at_120[0xe0];
3590
3591         struct mlx5_ifc_flow_context_bits flow_context;
3592 };
3593
3594 struct mlx5_ifc_rts2rts_qp_out_bits {
3595         u8         status[0x8];
3596         u8         reserved_at_8[0x18];
3597
3598         u8         syndrome[0x20];
3599
3600         u8         reserved_at_40[0x40];
3601 };
3602
3603 struct mlx5_ifc_rts2rts_qp_in_bits {
3604         u8         opcode[0x10];
3605         u8         reserved_at_10[0x10];
3606
3607         u8         reserved_at_20[0x10];
3608         u8         op_mod[0x10];
3609
3610         u8         reserved_at_40[0x8];
3611         u8         qpn[0x18];
3612
3613         u8         reserved_at_60[0x20];
3614
3615         u8         opt_param_mask[0x20];
3616
3617         u8         reserved_at_a0[0x20];
3618
3619         struct mlx5_ifc_qpc_bits qpc;
3620
3621         u8         reserved_at_800[0x80];
3622 };
3623
3624 struct mlx5_ifc_rtr2rts_qp_out_bits {
3625         u8         status[0x8];
3626         u8         reserved_at_8[0x18];
3627
3628         u8         syndrome[0x20];
3629
3630         u8         reserved_at_40[0x40];
3631 };
3632
3633 struct mlx5_ifc_rtr2rts_qp_in_bits {
3634         u8         opcode[0x10];
3635         u8         reserved_at_10[0x10];
3636
3637         u8         reserved_at_20[0x10];
3638         u8         op_mod[0x10];
3639
3640         u8         reserved_at_40[0x8];
3641         u8         qpn[0x18];
3642
3643         u8         reserved_at_60[0x20];
3644
3645         u8         opt_param_mask[0x20];
3646
3647         u8         reserved_at_a0[0x20];
3648
3649         struct mlx5_ifc_qpc_bits qpc;
3650
3651         u8         reserved_at_800[0x80];
3652 };
3653
3654 struct mlx5_ifc_rst2init_qp_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_at_8[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_at_40[0x40];
3661 };
3662
3663 struct mlx5_ifc_rst2init_qp_in_bits {
3664         u8         opcode[0x10];
3665         u8         reserved_at_10[0x10];
3666
3667         u8         reserved_at_20[0x10];
3668         u8         op_mod[0x10];
3669
3670         u8         reserved_at_40[0x8];
3671         u8         qpn[0x18];
3672
3673         u8         reserved_at_60[0x20];
3674
3675         u8         opt_param_mask[0x20];
3676
3677         u8         reserved_at_a0[0x20];
3678
3679         struct mlx5_ifc_qpc_bits qpc;
3680
3681         u8         reserved_at_800[0x80];
3682 };
3683
3684 struct mlx5_ifc_query_xrq_out_bits {
3685         u8         status[0x8];
3686         u8         reserved_at_8[0x18];
3687
3688         u8         syndrome[0x20];
3689
3690         u8         reserved_at_40[0x40];
3691
3692         struct mlx5_ifc_xrqc_bits xrq_context;
3693 };
3694
3695 struct mlx5_ifc_query_xrq_in_bits {
3696         u8         opcode[0x10];
3697         u8         reserved_at_10[0x10];
3698
3699         u8         reserved_at_20[0x10];
3700         u8         op_mod[0x10];
3701
3702         u8         reserved_at_40[0x8];
3703         u8         xrqn[0x18];
3704
3705         u8         reserved_at_60[0x20];
3706 };
3707
3708 struct mlx5_ifc_query_xrc_srq_out_bits {
3709         u8         status[0x8];
3710         u8         reserved_at_8[0x18];
3711
3712         u8         syndrome[0x20];
3713
3714         u8         reserved_at_40[0x40];
3715
3716         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3717
3718         u8         reserved_at_280[0x600];
3719
3720         u8         pas[0][0x40];
3721 };
3722
3723 struct mlx5_ifc_query_xrc_srq_in_bits {
3724         u8         opcode[0x10];
3725         u8         reserved_at_10[0x10];
3726
3727         u8         reserved_at_20[0x10];
3728         u8         op_mod[0x10];
3729
3730         u8         reserved_at_40[0x8];
3731         u8         xrc_srqn[0x18];
3732
3733         u8         reserved_at_60[0x20];
3734 };
3735
3736 enum {
3737         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3738         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3739 };
3740
3741 struct mlx5_ifc_query_vport_state_out_bits {
3742         u8         status[0x8];
3743         u8         reserved_at_8[0x18];
3744
3745         u8         syndrome[0x20];
3746
3747         u8         reserved_at_40[0x20];
3748
3749         u8         reserved_at_60[0x18];
3750         u8         admin_state[0x4];
3751         u8         state[0x4];
3752 };
3753
3754 enum {
3755         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3756         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3757 };
3758
3759 struct mlx5_ifc_query_vport_state_in_bits {
3760         u8         opcode[0x10];
3761         u8         reserved_at_10[0x10];
3762
3763         u8         reserved_at_20[0x10];
3764         u8         op_mod[0x10];
3765
3766         u8         other_vport[0x1];
3767         u8         reserved_at_41[0xf];
3768         u8         vport_number[0x10];
3769
3770         u8         reserved_at_60[0x20];
3771 };
3772
3773 struct mlx5_ifc_query_vnic_env_out_bits {
3774         u8         status[0x8];
3775         u8         reserved_at_8[0x18];
3776
3777         u8         syndrome[0x20];
3778
3779         u8         reserved_at_40[0x40];
3780
3781         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3782 };
3783
3784 enum {
3785         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3786 };
3787
3788 struct mlx5_ifc_query_vnic_env_in_bits {
3789         u8         opcode[0x10];
3790         u8         reserved_at_10[0x10];
3791
3792         u8         reserved_at_20[0x10];
3793         u8         op_mod[0x10];
3794
3795         u8         other_vport[0x1];
3796         u8         reserved_at_41[0xf];
3797         u8         vport_number[0x10];
3798
3799         u8         reserved_at_60[0x20];
3800 };
3801
3802 struct mlx5_ifc_query_vport_counter_out_bits {
3803         u8         status[0x8];
3804         u8         reserved_at_8[0x18];
3805
3806         u8         syndrome[0x20];
3807
3808         u8         reserved_at_40[0x40];
3809
3810         struct mlx5_ifc_traffic_counter_bits received_errors;
3811
3812         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3813
3814         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3815