Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65
66 enum {
67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72
73 enum {
74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
76 };
77
78 enum {
79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
81 };
82
83 enum {
84         MLX5_OBJ_TYPE_UCTX = 0x0004,
85         MLX5_OBJ_TYPE_UMEM = 0x0005,
86 };
87
88 enum {
89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
184         MLX5_CMD_OP_NOP                           = 0x80d,
185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
246         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
247         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
260         MLX5_CMD_OP_MAX
261 };
262
263 struct mlx5_ifc_flow_table_fields_supported_bits {
264         u8         outer_dmac[0x1];
265         u8         outer_smac[0x1];
266         u8         outer_ether_type[0x1];
267         u8         outer_ip_version[0x1];
268         u8         outer_first_prio[0x1];
269         u8         outer_first_cfi[0x1];
270         u8         outer_first_vid[0x1];
271         u8         outer_ipv4_ttl[0x1];
272         u8         outer_second_prio[0x1];
273         u8         outer_second_cfi[0x1];
274         u8         outer_second_vid[0x1];
275         u8         reserved_at_b[0x1];
276         u8         outer_sip[0x1];
277         u8         outer_dip[0x1];
278         u8         outer_frag[0x1];
279         u8         outer_ip_protocol[0x1];
280         u8         outer_ip_ecn[0x1];
281         u8         outer_ip_dscp[0x1];
282         u8         outer_udp_sport[0x1];
283         u8         outer_udp_dport[0x1];
284         u8         outer_tcp_sport[0x1];
285         u8         outer_tcp_dport[0x1];
286         u8         outer_tcp_flags[0x1];
287         u8         outer_gre_protocol[0x1];
288         u8         outer_gre_key[0x1];
289         u8         outer_vxlan_vni[0x1];
290         u8         reserved_at_1a[0x5];
291         u8         source_eswitch_port[0x1];
292
293         u8         inner_dmac[0x1];
294         u8         inner_smac[0x1];
295         u8         inner_ether_type[0x1];
296         u8         inner_ip_version[0x1];
297         u8         inner_first_prio[0x1];
298         u8         inner_first_cfi[0x1];
299         u8         inner_first_vid[0x1];
300         u8         reserved_at_27[0x1];
301         u8         inner_second_prio[0x1];
302         u8         inner_second_cfi[0x1];
303         u8         inner_second_vid[0x1];
304         u8         reserved_at_2b[0x1];
305         u8         inner_sip[0x1];
306         u8         inner_dip[0x1];
307         u8         inner_frag[0x1];
308         u8         inner_ip_protocol[0x1];
309         u8         inner_ip_ecn[0x1];
310         u8         inner_ip_dscp[0x1];
311         u8         inner_udp_sport[0x1];
312         u8         inner_udp_dport[0x1];
313         u8         inner_tcp_sport[0x1];
314         u8         inner_tcp_dport[0x1];
315         u8         inner_tcp_flags[0x1];
316         u8         reserved_at_37[0x9];
317
318         u8         reserved_at_40[0x5];
319         u8         outer_first_mpls_over_udp[0x4];
320         u8         outer_first_mpls_over_gre[0x4];
321         u8         inner_first_mpls[0x4];
322         u8         outer_first_mpls[0x4];
323         u8         reserved_at_55[0x2];
324         u8         outer_esp_spi[0x1];
325         u8         reserved_at_58[0x2];
326         u8         bth_dst_qp[0x1];
327
328         u8         reserved_at_5b[0x25];
329 };
330
331 struct mlx5_ifc_flow_table_prop_layout_bits {
332         u8         ft_support[0x1];
333         u8         reserved_at_1[0x1];
334         u8         flow_counter[0x1];
335         u8         flow_modify_en[0x1];
336         u8         modify_root[0x1];
337         u8         identified_miss_table_mode[0x1];
338         u8         flow_table_modify[0x1];
339         u8         reformat[0x1];
340         u8         decap[0x1];
341         u8         reserved_at_9[0x1];
342         u8         pop_vlan[0x1];
343         u8         push_vlan[0x1];
344         u8         reserved_at_c[0x1];
345         u8         pop_vlan_2[0x1];
346         u8         push_vlan_2[0x1];
347         u8         reformat_and_vlan_action[0x1];
348         u8         reserved_at_10[0x2];
349         u8         reformat_l3_tunnel_to_l2[0x1];
350         u8         reformat_l2_to_l3_tunnel[0x1];
351         u8         reformat_and_modify_action[0x1];
352         u8         reserved_at_14[0xb];
353         u8         reserved_at_20[0x2];
354         u8         log_max_ft_size[0x6];
355         u8         log_max_modify_header_context[0x8];
356         u8         max_modify_header_actions[0x8];
357         u8         max_ft_level[0x8];
358
359         u8         reserved_at_40[0x20];
360
361         u8         reserved_at_60[0x18];
362         u8         log_max_ft_num[0x8];
363
364         u8         reserved_at_80[0x18];
365         u8         log_max_destination[0x8];
366
367         u8         log_max_flow_counter[0x8];
368         u8         reserved_at_a8[0x10];
369         u8         log_max_flow[0x8];
370
371         u8         reserved_at_c0[0x40];
372
373         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
374
375         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
376 };
377
378 struct mlx5_ifc_odp_per_transport_service_cap_bits {
379         u8         send[0x1];
380         u8         receive[0x1];
381         u8         write[0x1];
382         u8         read[0x1];
383         u8         atomic[0x1];
384         u8         srq_receive[0x1];
385         u8         reserved_at_6[0x1a];
386 };
387
388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
389         u8         smac_47_16[0x20];
390
391         u8         smac_15_0[0x10];
392         u8         ethertype[0x10];
393
394         u8         dmac_47_16[0x20];
395
396         u8         dmac_15_0[0x10];
397         u8         first_prio[0x3];
398         u8         first_cfi[0x1];
399         u8         first_vid[0xc];
400
401         u8         ip_protocol[0x8];
402         u8         ip_dscp[0x6];
403         u8         ip_ecn[0x2];
404         u8         cvlan_tag[0x1];
405         u8         svlan_tag[0x1];
406         u8         frag[0x1];
407         u8         ip_version[0x4];
408         u8         tcp_flags[0x9];
409
410         u8         tcp_sport[0x10];
411         u8         tcp_dport[0x10];
412
413         u8         reserved_at_c0[0x18];
414         u8         ttl_hoplimit[0x8];
415
416         u8         udp_sport[0x10];
417         u8         udp_dport[0x10];
418
419         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
420
421         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
422 };
423
424 struct mlx5_ifc_fte_match_set_misc_bits {
425         u8         reserved_at_0[0x8];
426         u8         source_sqn[0x18];
427
428         u8         source_eswitch_owner_vhca_id[0x10];
429         u8         source_port[0x10];
430
431         u8         outer_second_prio[0x3];
432         u8         outer_second_cfi[0x1];
433         u8         outer_second_vid[0xc];
434         u8         inner_second_prio[0x3];
435         u8         inner_second_cfi[0x1];
436         u8         inner_second_vid[0xc];
437
438         u8         outer_second_cvlan_tag[0x1];
439         u8         inner_second_cvlan_tag[0x1];
440         u8         outer_second_svlan_tag[0x1];
441         u8         inner_second_svlan_tag[0x1];
442         u8         reserved_at_64[0xc];
443         u8         gre_protocol[0x10];
444
445         u8         gre_key_h[0x18];
446         u8         gre_key_l[0x8];
447
448         u8         vxlan_vni[0x18];
449         u8         reserved_at_b8[0x8];
450
451         u8         reserved_at_c0[0x20];
452
453         u8         reserved_at_e0[0xc];
454         u8         outer_ipv6_flow_label[0x14];
455
456         u8         reserved_at_100[0xc];
457         u8         inner_ipv6_flow_label[0x14];
458
459         u8         reserved_at_120[0x28];
460         u8         bth_dst_qp[0x18];
461         u8         reserved_at_160[0x20];
462         u8         outer_esp_spi[0x20];
463         u8         reserved_at_1a0[0x60];
464 };
465
466 struct mlx5_ifc_fte_match_mpls_bits {
467         u8         mpls_label[0x14];
468         u8         mpls_exp[0x3];
469         u8         mpls_s_bos[0x1];
470         u8         mpls_ttl[0x8];
471 };
472
473 struct mlx5_ifc_fte_match_set_misc2_bits {
474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
475
476         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
477
478         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
479
480         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
481
482         u8         reserved_at_80[0x100];
483
484         u8         metadata_reg_a[0x20];
485
486         u8         reserved_at_1a0[0x60];
487 };
488
489 struct mlx5_ifc_cmd_pas_bits {
490         u8         pa_h[0x20];
491
492         u8         pa_l[0x14];
493         u8         reserved_at_34[0xc];
494 };
495
496 struct mlx5_ifc_uint64_bits {
497         u8         hi[0x20];
498
499         u8         lo[0x20];
500 };
501
502 enum {
503         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
504         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
505         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
506         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
507         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
508         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
509         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
510         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
511         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
512         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
513 };
514
515 struct mlx5_ifc_ads_bits {
516         u8         fl[0x1];
517         u8         free_ar[0x1];
518         u8         reserved_at_2[0xe];
519         u8         pkey_index[0x10];
520
521         u8         reserved_at_20[0x8];
522         u8         grh[0x1];
523         u8         mlid[0x7];
524         u8         rlid[0x10];
525
526         u8         ack_timeout[0x5];
527         u8         reserved_at_45[0x3];
528         u8         src_addr_index[0x8];
529         u8         reserved_at_50[0x4];
530         u8         stat_rate[0x4];
531         u8         hop_limit[0x8];
532
533         u8         reserved_at_60[0x4];
534         u8         tclass[0x8];
535         u8         flow_label[0x14];
536
537         u8         rgid_rip[16][0x8];
538
539         u8         reserved_at_100[0x4];
540         u8         f_dscp[0x1];
541         u8         f_ecn[0x1];
542         u8         reserved_at_106[0x1];
543         u8         f_eth_prio[0x1];
544         u8         ecn[0x2];
545         u8         dscp[0x6];
546         u8         udp_sport[0x10];
547
548         u8         dei_cfi[0x1];
549         u8         eth_prio[0x3];
550         u8         sl[0x4];
551         u8         vhca_port_num[0x8];
552         u8         rmac_47_32[0x10];
553
554         u8         rmac_31_0[0x20];
555 };
556
557 struct mlx5_ifc_flow_table_nic_cap_bits {
558         u8         nic_rx_multi_path_tirs[0x1];
559         u8         nic_rx_multi_path_tirs_fts[0x1];
560         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
561         u8         reserved_at_3[0x1d];
562         u8         encap_general_header[0x1];
563         u8         reserved_at_21[0xa];
564         u8         log_max_packet_reformat_context[0x5];
565         u8         reserved_at_30[0x6];
566         u8         max_encap_header_size[0xa];
567         u8         reserved_at_40[0x1c0];
568
569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
570
571         u8         reserved_at_400[0x200];
572
573         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
574
575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
576
577         u8         reserved_at_a00[0x200];
578
579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
580
581         u8         reserved_at_e00[0x7200];
582 };
583
584 struct mlx5_ifc_flow_table_eswitch_cap_bits {
585         u8      reserved_at_0[0x1c];
586         u8      fdb_multi_path_to_table[0x1];
587         u8      reserved_at_1d[0x1e3];
588
589         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
590
591         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
592
593         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
594
595         u8      reserved_at_800[0x7800];
596 };
597
598 struct mlx5_ifc_e_switch_cap_bits {
599         u8         vport_svlan_strip[0x1];
600         u8         vport_cvlan_strip[0x1];
601         u8         vport_svlan_insert[0x1];
602         u8         vport_cvlan_insert_if_not_exist[0x1];
603         u8         vport_cvlan_insert_overwrite[0x1];
604         u8         reserved_at_5[0x18];
605         u8         merged_eswitch[0x1];
606         u8         nic_vport_node_guid_modify[0x1];
607         u8         nic_vport_port_guid_modify[0x1];
608
609         u8         vxlan_encap_decap[0x1];
610         u8         nvgre_encap_decap[0x1];
611         u8         reserved_at_22[0x9];
612         u8         log_max_packet_reformat_context[0x5];
613         u8         reserved_2b[0x6];
614         u8         max_encap_header_size[0xa];
615
616         u8         reserved_40[0x7c0];
617
618 };
619
620 struct mlx5_ifc_qos_cap_bits {
621         u8         packet_pacing[0x1];
622         u8         esw_scheduling[0x1];
623         u8         esw_bw_share[0x1];
624         u8         esw_rate_limit[0x1];
625         u8         reserved_at_4[0x1];
626         u8         packet_pacing_burst_bound[0x1];
627         u8         packet_pacing_typical_size[0x1];
628         u8         reserved_at_7[0x19];
629
630         u8         reserved_at_20[0x20];
631
632         u8         packet_pacing_max_rate[0x20];
633
634         u8         packet_pacing_min_rate[0x20];
635
636         u8         reserved_at_80[0x10];
637         u8         packet_pacing_rate_table_size[0x10];
638
639         u8         esw_element_type[0x10];
640         u8         esw_tsar_type[0x10];
641
642         u8         reserved_at_c0[0x10];
643         u8         max_qos_para_vport[0x10];
644
645         u8         max_tsar_bw_share[0x20];
646
647         u8         reserved_at_100[0x700];
648 };
649
650 struct mlx5_ifc_debug_cap_bits {
651         u8         reserved_at_0[0x20];
652
653         u8         reserved_at_20[0x2];
654         u8         stall_detect[0x1];
655         u8         reserved_at_23[0x1d];
656
657         u8         reserved_at_40[0x7c0];
658 };
659
660 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
661         u8         csum_cap[0x1];
662         u8         vlan_cap[0x1];
663         u8         lro_cap[0x1];
664         u8         lro_psh_flag[0x1];
665         u8         lro_time_stamp[0x1];
666         u8         reserved_at_5[0x2];
667         u8         wqe_vlan_insert[0x1];
668         u8         self_lb_en_modifiable[0x1];
669         u8         reserved_at_9[0x2];
670         u8         max_lso_cap[0x5];
671         u8         multi_pkt_send_wqe[0x2];
672         u8         wqe_inline_mode[0x2];
673         u8         rss_ind_tbl_cap[0x4];
674         u8         reg_umr_sq[0x1];
675         u8         scatter_fcs[0x1];
676         u8         enhanced_multi_pkt_send_wqe[0x1];
677         u8         tunnel_lso_const_out_ip_id[0x1];
678         u8         reserved_at_1c[0x2];
679         u8         tunnel_stateless_gre[0x1];
680         u8         tunnel_stateless_vxlan[0x1];
681
682         u8         swp[0x1];
683         u8         swp_csum[0x1];
684         u8         swp_lso[0x1];
685         u8         reserved_at_23[0xd];
686         u8         max_vxlan_udp_ports[0x8];
687         u8         reserved_at_38[0x6];
688         u8         max_geneve_opt_len[0x1];
689         u8         tunnel_stateless_geneve_rx[0x1];
690
691         u8         reserved_at_40[0x10];
692         u8         lro_min_mss_size[0x10];
693
694         u8         reserved_at_60[0x120];
695
696         u8         lro_timer_supported_periods[4][0x20];
697
698         u8         reserved_at_200[0x600];
699 };
700
701 struct mlx5_ifc_roce_cap_bits {
702         u8         roce_apm[0x1];
703         u8         reserved_at_1[0x1f];
704
705         u8         reserved_at_20[0x60];
706
707         u8         reserved_at_80[0xc];
708         u8         l3_type[0x4];
709         u8         reserved_at_90[0x8];
710         u8         roce_version[0x8];
711
712         u8         reserved_at_a0[0x10];
713         u8         r_roce_dest_udp_port[0x10];
714
715         u8         r_roce_max_src_udp_port[0x10];
716         u8         r_roce_min_src_udp_port[0x10];
717
718         u8         reserved_at_e0[0x10];
719         u8         roce_address_table_size[0x10];
720
721         u8         reserved_at_100[0x700];
722 };
723
724 struct mlx5_ifc_device_mem_cap_bits {
725         u8         memic[0x1];
726         u8         reserved_at_1[0x1f];
727
728         u8         reserved_at_20[0xb];
729         u8         log_min_memic_alloc_size[0x5];
730         u8         reserved_at_30[0x8];
731         u8         log_max_memic_addr_alignment[0x8];
732
733         u8         memic_bar_start_addr[0x40];
734
735         u8         memic_bar_size[0x20];
736
737         u8         max_memic_size[0x20];
738
739         u8         reserved_at_c0[0x740];
740 };
741
742 enum {
743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
752 };
753
754 enum {
755         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
756         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
757         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
758         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
759         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
760         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
761         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
762         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
763         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
764 };
765
766 struct mlx5_ifc_atomic_caps_bits {
767         u8         reserved_at_0[0x40];
768
769         u8         atomic_req_8B_endianness_mode[0x2];
770         u8         reserved_at_42[0x4];
771         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
772
773         u8         reserved_at_47[0x19];
774
775         u8         reserved_at_60[0x20];
776
777         u8         reserved_at_80[0x10];
778         u8         atomic_operations[0x10];
779
780         u8         reserved_at_a0[0x10];
781         u8         atomic_size_qp[0x10];
782
783         u8         reserved_at_c0[0x10];
784         u8         atomic_size_dc[0x10];
785
786         u8         reserved_at_e0[0x720];
787 };
788
789 struct mlx5_ifc_odp_cap_bits {
790         u8         reserved_at_0[0x40];
791
792         u8         sig[0x1];
793         u8         reserved_at_41[0x1f];
794
795         u8         reserved_at_60[0x20];
796
797         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
798
799         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
800
801         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
802
803         u8         reserved_at_e0[0x720];
804 };
805
806 struct mlx5_ifc_calc_op {
807         u8        reserved_at_0[0x10];
808         u8        reserved_at_10[0x9];
809         u8        op_swap_endianness[0x1];
810         u8        op_min[0x1];
811         u8        op_xor[0x1];
812         u8        op_or[0x1];
813         u8        op_and[0x1];
814         u8        op_max[0x1];
815         u8        op_add[0x1];
816 };
817
818 struct mlx5_ifc_vector_calc_cap_bits {
819         u8         calc_matrix[0x1];
820         u8         reserved_at_1[0x1f];
821         u8         reserved_at_20[0x8];
822         u8         max_vec_count[0x8];
823         u8         reserved_at_30[0xd];
824         u8         max_chunk_size[0x3];
825         struct mlx5_ifc_calc_op calc0;
826         struct mlx5_ifc_calc_op calc1;
827         struct mlx5_ifc_calc_op calc2;
828         struct mlx5_ifc_calc_op calc3;
829
830         u8         reserved_at_e0[0x720];
831 };
832
833 enum {
834         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
835         MLX5_WQ_TYPE_CYCLIC       = 0x1,
836         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
837         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
838 };
839
840 enum {
841         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
842         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
843 };
844
845 enum {
846         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
847         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
848         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
849         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
850         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
851 };
852
853 enum {
854         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
855         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
856         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
857         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
858         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
859         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
860 };
861
862 enum {
863         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
864         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
865 };
866
867 enum {
868         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
869         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
870         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
871 };
872
873 enum {
874         MLX5_CAP_PORT_TYPE_IB  = 0x0,
875         MLX5_CAP_PORT_TYPE_ETH = 0x1,
876 };
877
878 enum {
879         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
880         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
881         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
882 };
883
884 struct mlx5_ifc_cmd_hca_cap_bits {
885         u8         reserved_at_0[0x30];
886         u8         vhca_id[0x10];
887
888         u8         reserved_at_40[0x40];
889
890         u8         log_max_srq_sz[0x8];
891         u8         log_max_qp_sz[0x8];
892         u8         reserved_at_90[0xb];
893         u8         log_max_qp[0x5];
894
895         u8         reserved_at_a0[0xb];
896         u8         log_max_srq[0x5];
897         u8         reserved_at_b0[0x10];
898
899         u8         reserved_at_c0[0x8];
900         u8         log_max_cq_sz[0x8];
901         u8         reserved_at_d0[0xb];
902         u8         log_max_cq[0x5];
903
904         u8         log_max_eq_sz[0x8];
905         u8         reserved_at_e8[0x2];
906         u8         log_max_mkey[0x6];
907         u8         reserved_at_f0[0x8];
908         u8         dump_fill_mkey[0x1];
909         u8         reserved_at_f9[0x2];
910         u8         fast_teardown[0x1];
911         u8         log_max_eq[0x4];
912
913         u8         max_indirection[0x8];
914         u8         fixed_buffer_size[0x1];
915         u8         log_max_mrw_sz[0x7];
916         u8         force_teardown[0x1];
917         u8         reserved_at_111[0x1];
918         u8         log_max_bsf_list_size[0x6];
919         u8         umr_extended_translation_offset[0x1];
920         u8         null_mkey[0x1];
921         u8         log_max_klm_list_size[0x6];
922
923         u8         reserved_at_120[0xa];
924         u8         log_max_ra_req_dc[0x6];
925         u8         reserved_at_130[0xa];
926         u8         log_max_ra_res_dc[0x6];
927
928         u8         reserved_at_140[0xa];
929         u8         log_max_ra_req_qp[0x6];
930         u8         reserved_at_150[0xa];
931         u8         log_max_ra_res_qp[0x6];
932
933         u8         end_pad[0x1];
934         u8         cc_query_allowed[0x1];
935         u8         cc_modify_allowed[0x1];
936         u8         start_pad[0x1];
937         u8         cache_line_128byte[0x1];
938         u8         reserved_at_165[0xa];
939         u8         qcam_reg[0x1];
940         u8         gid_table_size[0x10];
941
942         u8         out_of_seq_cnt[0x1];
943         u8         vport_counters[0x1];
944         u8         retransmission_q_counters[0x1];
945         u8         debug[0x1];
946         u8         modify_rq_counter_set_id[0x1];
947         u8         rq_delay_drop[0x1];
948         u8         max_qp_cnt[0xa];
949         u8         pkey_table_size[0x10];
950
951         u8         vport_group_manager[0x1];
952         u8         vhca_group_manager[0x1];
953         u8         ib_virt[0x1];
954         u8         eth_virt[0x1];
955         u8         vnic_env_queue_counters[0x1];
956         u8         ets[0x1];
957         u8         nic_flow_table[0x1];
958         u8         eswitch_manager[0x1];
959         u8         device_memory[0x1];
960         u8         mcam_reg[0x1];
961         u8         pcam_reg[0x1];
962         u8         local_ca_ack_delay[0x5];
963         u8         port_module_event[0x1];
964         u8         enhanced_error_q_counters[0x1];
965         u8         ports_check[0x1];
966         u8         reserved_at_1b3[0x1];
967         u8         disable_link_up[0x1];
968         u8         beacon_led[0x1];
969         u8         port_type[0x2];
970         u8         num_ports[0x8];
971
972         u8         reserved_at_1c0[0x1];
973         u8         pps[0x1];
974         u8         pps_modify[0x1];
975         u8         log_max_msg[0x5];
976         u8         reserved_at_1c8[0x4];
977         u8         max_tc[0x4];
978         u8         temp_warn_event[0x1];
979         u8         dcbx[0x1];
980         u8         general_notification_event[0x1];
981         u8         reserved_at_1d3[0x2];
982         u8         fpga[0x1];
983         u8         rol_s[0x1];
984         u8         rol_g[0x1];
985         u8         reserved_at_1d8[0x1];
986         u8         wol_s[0x1];
987         u8         wol_g[0x1];
988         u8         wol_a[0x1];
989         u8         wol_b[0x1];
990         u8         wol_m[0x1];
991         u8         wol_u[0x1];
992         u8         wol_p[0x1];
993
994         u8         stat_rate_support[0x10];
995         u8         reserved_at_1f0[0xc];
996         u8         cqe_version[0x4];
997
998         u8         compact_address_vector[0x1];
999         u8         striding_rq[0x1];
1000         u8         reserved_at_202[0x1];
1001         u8         ipoib_enhanced_offloads[0x1];
1002         u8         ipoib_basic_offloads[0x1];
1003         u8         reserved_at_205[0x1];
1004         u8         repeated_block_disabled[0x1];
1005         u8         umr_modify_entity_size_disabled[0x1];
1006         u8         umr_modify_atomic_disabled[0x1];
1007         u8         umr_indirect_mkey_disabled[0x1];
1008         u8         umr_fence[0x2];
1009         u8         dc_req_scat_data_cqe[0x1];
1010         u8         reserved_at_20d[0x2];
1011         u8         drain_sigerr[0x1];
1012         u8         cmdif_checksum[0x2];
1013         u8         sigerr_cqe[0x1];
1014         u8         reserved_at_213[0x1];
1015         u8         wq_signature[0x1];
1016         u8         sctr_data_cqe[0x1];
1017         u8         reserved_at_216[0x1];
1018         u8         sho[0x1];
1019         u8         tph[0x1];
1020         u8         rf[0x1];
1021         u8         dct[0x1];
1022         u8         qos[0x1];
1023         u8         eth_net_offloads[0x1];
1024         u8         roce[0x1];
1025         u8         atomic[0x1];
1026         u8         reserved_at_21f[0x1];
1027
1028         u8         cq_oi[0x1];
1029         u8         cq_resize[0x1];
1030         u8         cq_moderation[0x1];
1031         u8         reserved_at_223[0x3];
1032         u8         cq_eq_remap[0x1];
1033         u8         pg[0x1];
1034         u8         block_lb_mc[0x1];
1035         u8         reserved_at_229[0x1];
1036         u8         scqe_break_moderation[0x1];
1037         u8         cq_period_start_from_cqe[0x1];
1038         u8         cd[0x1];
1039         u8         reserved_at_22d[0x1];
1040         u8         apm[0x1];
1041         u8         vector_calc[0x1];
1042         u8         umr_ptr_rlky[0x1];
1043         u8         imaicl[0x1];
1044         u8         reserved_at_232[0x4];
1045         u8         qkv[0x1];
1046         u8         pkv[0x1];
1047         u8         set_deth_sqpn[0x1];
1048         u8         reserved_at_239[0x3];
1049         u8         xrc[0x1];
1050         u8         ud[0x1];
1051         u8         uc[0x1];
1052         u8         rc[0x1];
1053
1054         u8         uar_4k[0x1];
1055         u8         reserved_at_241[0x9];
1056         u8         uar_sz[0x6];
1057         u8         reserved_at_250[0x8];
1058         u8         log_pg_sz[0x8];
1059
1060         u8         bf[0x1];
1061         u8         driver_version[0x1];
1062         u8         pad_tx_eth_packet[0x1];
1063         u8         reserved_at_263[0x8];
1064         u8         log_bf_reg_size[0x5];
1065
1066         u8         reserved_at_270[0xb];
1067         u8         lag_master[0x1];
1068         u8         num_lag_ports[0x4];
1069
1070         u8         reserved_at_280[0x10];
1071         u8         max_wqe_sz_sq[0x10];
1072
1073         u8         reserved_at_2a0[0x10];
1074         u8         max_wqe_sz_rq[0x10];
1075
1076         u8         max_flow_counter_31_16[0x10];
1077         u8         max_wqe_sz_sq_dc[0x10];
1078
1079         u8         reserved_at_2e0[0x7];
1080         u8         max_qp_mcg[0x19];
1081
1082         u8         reserved_at_300[0x18];
1083         u8         log_max_mcg[0x8];
1084
1085         u8         reserved_at_320[0x3];
1086         u8         log_max_transport_domain[0x5];
1087         u8         reserved_at_328[0x3];
1088         u8         log_max_pd[0x5];
1089         u8         reserved_at_330[0xb];
1090         u8         log_max_xrcd[0x5];
1091
1092         u8         nic_receive_steering_discard[0x1];
1093         u8         receive_discard_vport_down[0x1];
1094         u8         transmit_discard_vport_down[0x1];
1095         u8         reserved_at_343[0x5];
1096         u8         log_max_flow_counter_bulk[0x8];
1097         u8         max_flow_counter_15_0[0x10];
1098
1099
1100         u8         reserved_at_360[0x3];
1101         u8         log_max_rq[0x5];
1102         u8         reserved_at_368[0x3];
1103         u8         log_max_sq[0x5];
1104         u8         reserved_at_370[0x3];
1105         u8         log_max_tir[0x5];
1106         u8         reserved_at_378[0x3];
1107         u8         log_max_tis[0x5];
1108
1109         u8         basic_cyclic_rcv_wqe[0x1];
1110         u8         reserved_at_381[0x2];
1111         u8         log_max_rmp[0x5];
1112         u8         reserved_at_388[0x3];
1113         u8         log_max_rqt[0x5];
1114         u8         reserved_at_390[0x3];
1115         u8         log_max_rqt_size[0x5];
1116         u8         reserved_at_398[0x3];
1117         u8         log_max_tis_per_sq[0x5];
1118
1119         u8         ext_stride_num_range[0x1];
1120         u8         reserved_at_3a1[0x2];
1121         u8         log_max_stride_sz_rq[0x5];
1122         u8         reserved_at_3a8[0x3];
1123         u8         log_min_stride_sz_rq[0x5];
1124         u8         reserved_at_3b0[0x3];
1125         u8         log_max_stride_sz_sq[0x5];
1126         u8         reserved_at_3b8[0x3];
1127         u8         log_min_stride_sz_sq[0x5];
1128
1129         u8         hairpin[0x1];
1130         u8         reserved_at_3c1[0x2];
1131         u8         log_max_hairpin_queues[0x5];
1132         u8         reserved_at_3c8[0x3];
1133         u8         log_max_hairpin_wq_data_sz[0x5];
1134         u8         reserved_at_3d0[0x3];
1135         u8         log_max_hairpin_num_packets[0x5];
1136         u8         reserved_at_3d8[0x3];
1137         u8         log_max_wq_sz[0x5];
1138
1139         u8         nic_vport_change_event[0x1];
1140         u8         disable_local_lb_uc[0x1];
1141         u8         disable_local_lb_mc[0x1];
1142         u8         log_min_hairpin_wq_data_sz[0x5];
1143         u8         reserved_at_3e8[0x3];
1144         u8         log_max_vlan_list[0x5];
1145         u8         reserved_at_3f0[0x3];
1146         u8         log_max_current_mc_list[0x5];
1147         u8         reserved_at_3f8[0x3];
1148         u8         log_max_current_uc_list[0x5];
1149
1150         u8         general_obj_types[0x40];
1151
1152         u8         reserved_at_440[0x20];
1153
1154         u8         reserved_at_460[0x10];
1155         u8         max_num_eqs[0x10];
1156
1157         u8         reserved_at_480[0x3];
1158         u8         log_max_l2_table[0x5];
1159         u8         reserved_at_488[0x8];
1160         u8         log_uar_page_sz[0x10];
1161
1162         u8         reserved_at_4a0[0x20];
1163         u8         device_frequency_mhz[0x20];
1164         u8         device_frequency_khz[0x20];
1165
1166         u8         reserved_at_500[0x20];
1167         u8         num_of_uars_per_page[0x20];
1168
1169         u8         flex_parser_protocols[0x20];
1170         u8         reserved_at_560[0x20];
1171
1172         u8         reserved_at_580[0x3c];
1173         u8         mini_cqe_resp_stride_index[0x1];
1174         u8         cqe_128_always[0x1];
1175         u8         cqe_compression_128[0x1];
1176         u8         cqe_compression[0x1];
1177
1178         u8         cqe_compression_timeout[0x10];
1179         u8         cqe_compression_max_num[0x10];
1180
1181         u8         reserved_at_5e0[0x10];
1182         u8         tag_matching[0x1];
1183         u8         rndv_offload_rc[0x1];
1184         u8         rndv_offload_dc[0x1];
1185         u8         log_tag_matching_list_sz[0x5];
1186         u8         reserved_at_5f8[0x3];
1187         u8         log_max_xrq[0x5];
1188
1189         u8         affiliate_nic_vport_criteria[0x8];
1190         u8         native_port_num[0x8];
1191         u8         num_vhca_ports[0x8];
1192         u8         reserved_at_618[0x6];
1193         u8         sw_owner_id[0x1];
1194         u8         reserved_at_61f[0x1e1];
1195 };
1196
1197 enum mlx5_flow_destination_type {
1198         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1199         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1200         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1201
1202         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1203         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1204         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1205 };
1206
1207 struct mlx5_ifc_dest_format_struct_bits {
1208         u8         destination_type[0x8];
1209         u8         destination_id[0x18];
1210         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1211         u8         reserved_at_21[0xf];
1212         u8         destination_eswitch_owner_vhca_id[0x10];
1213 };
1214
1215 struct mlx5_ifc_flow_counter_list_bits {
1216         u8         flow_counter_id[0x20];
1217
1218         u8         reserved_at_20[0x20];
1219 };
1220
1221 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1222         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1223         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1224         u8         reserved_at_0[0x40];
1225 };
1226
1227 struct mlx5_ifc_fte_match_param_bits {
1228         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1229
1230         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1231
1232         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1233
1234         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1235
1236         u8         reserved_at_800[0x800];
1237 };
1238
1239 enum {
1240         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1241         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1242         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1243         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1244         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1245 };
1246
1247 struct mlx5_ifc_rx_hash_field_select_bits {
1248         u8         l3_prot_type[0x1];
1249         u8         l4_prot_type[0x1];
1250         u8         selected_fields[0x1e];
1251 };
1252
1253 enum {
1254         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1255         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1256 };
1257
1258 enum {
1259         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1260         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1261 };
1262
1263 struct mlx5_ifc_wq_bits {
1264         u8         wq_type[0x4];
1265         u8         wq_signature[0x1];
1266         u8         end_padding_mode[0x2];
1267         u8         cd_slave[0x1];
1268         u8         reserved_at_8[0x18];
1269
1270         u8         hds_skip_first_sge[0x1];
1271         u8         log2_hds_buf_size[0x3];
1272         u8         reserved_at_24[0x7];
1273         u8         page_offset[0x5];
1274         u8         lwm[0x10];
1275
1276         u8         reserved_at_40[0x8];
1277         u8         pd[0x18];
1278
1279         u8         reserved_at_60[0x8];
1280         u8         uar_page[0x18];
1281
1282         u8         dbr_addr[0x40];
1283
1284         u8         hw_counter[0x20];
1285
1286         u8         sw_counter[0x20];
1287
1288         u8         reserved_at_100[0xc];
1289         u8         log_wq_stride[0x4];
1290         u8         reserved_at_110[0x3];
1291         u8         log_wq_pg_sz[0x5];
1292         u8         reserved_at_118[0x3];
1293         u8         log_wq_sz[0x5];
1294
1295         u8         dbr_umem_valid[0x1];
1296         u8         wq_umem_valid[0x1];
1297         u8         reserved_at_122[0x1];
1298         u8         log_hairpin_num_packets[0x5];
1299         u8         reserved_at_128[0x3];
1300         u8         log_hairpin_data_sz[0x5];
1301
1302         u8         reserved_at_130[0x4];
1303         u8         log_wqe_num_of_strides[0x4];
1304         u8         two_byte_shift_en[0x1];
1305         u8         reserved_at_139[0x4];
1306         u8         log_wqe_stride_size[0x3];
1307
1308         u8         reserved_at_140[0x4c0];
1309
1310         struct mlx5_ifc_cmd_pas_bits pas[0];
1311 };
1312
1313 struct mlx5_ifc_rq_num_bits {
1314         u8         reserved_at_0[0x8];
1315         u8         rq_num[0x18];
1316 };
1317
1318 struct mlx5_ifc_mac_address_layout_bits {
1319         u8         reserved_at_0[0x10];
1320         u8         mac_addr_47_32[0x10];
1321
1322         u8         mac_addr_31_0[0x20];
1323 };
1324
1325 struct mlx5_ifc_vlan_layout_bits {
1326         u8         reserved_at_0[0x14];
1327         u8         vlan[0x0c];
1328
1329         u8         reserved_at_20[0x20];
1330 };
1331
1332 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1333         u8         reserved_at_0[0xa0];
1334
1335         u8         min_time_between_cnps[0x20];
1336
1337         u8         reserved_at_c0[0x12];
1338         u8         cnp_dscp[0x6];
1339         u8         reserved_at_d8[0x4];
1340         u8         cnp_prio_mode[0x1];
1341         u8         cnp_802p_prio[0x3];
1342
1343         u8         reserved_at_e0[0x720];
1344 };
1345
1346 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1347         u8         reserved_at_0[0x60];
1348
1349         u8         reserved_at_60[0x4];
1350         u8         clamp_tgt_rate[0x1];
1351         u8         reserved_at_65[0x3];
1352         u8         clamp_tgt_rate_after_time_inc[0x1];
1353         u8         reserved_at_69[0x17];
1354
1355         u8         reserved_at_80[0x20];
1356
1357         u8         rpg_time_reset[0x20];
1358
1359         u8         rpg_byte_reset[0x20];
1360
1361         u8         rpg_threshold[0x20];
1362
1363         u8         rpg_max_rate[0x20];
1364
1365         u8         rpg_ai_rate[0x20];
1366
1367         u8         rpg_hai_rate[0x20];
1368
1369         u8         rpg_gd[0x20];
1370
1371         u8         rpg_min_dec_fac[0x20];
1372
1373         u8         rpg_min_rate[0x20];
1374
1375         u8         reserved_at_1c0[0xe0];
1376
1377         u8         rate_to_set_on_first_cnp[0x20];
1378
1379         u8         dce_tcp_g[0x20];
1380
1381         u8         dce_tcp_rtt[0x20];
1382
1383         u8         rate_reduce_monitor_period[0x20];
1384
1385         u8         reserved_at_320[0x20];
1386
1387         u8         initial_alpha_value[0x20];
1388
1389         u8         reserved_at_360[0x4a0];
1390 };
1391
1392 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1393         u8         reserved_at_0[0x80];
1394
1395         u8         rppp_max_rps[0x20];
1396
1397         u8         rpg_time_reset[0x20];
1398
1399         u8         rpg_byte_reset[0x20];
1400
1401         u8         rpg_threshold[0x20];
1402
1403         u8         rpg_max_rate[0x20];
1404
1405         u8         rpg_ai_rate[0x20];
1406
1407         u8         rpg_hai_rate[0x20];
1408
1409         u8         rpg_gd[0x20];
1410
1411         u8         rpg_min_dec_fac[0x20];
1412
1413         u8         rpg_min_rate[0x20];
1414
1415         u8         reserved_at_1c0[0x640];
1416 };
1417
1418 enum {
1419         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1420         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1421         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1422 };
1423
1424 struct mlx5_ifc_resize_field_select_bits {
1425         u8         resize_field_select[0x20];
1426 };
1427
1428 enum {
1429         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1430         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1431         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1432         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1433 };
1434
1435 struct mlx5_ifc_modify_field_select_bits {
1436         u8         modify_field_select[0x20];
1437 };
1438
1439 struct mlx5_ifc_field_select_r_roce_np_bits {
1440         u8         field_select_r_roce_np[0x20];
1441 };
1442
1443 struct mlx5_ifc_field_select_r_roce_rp_bits {
1444         u8         field_select_r_roce_rp[0x20];
1445 };
1446
1447 enum {
1448         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1449         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1450         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1451         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1452         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1453         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1454         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1455         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1456         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1457         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1458 };
1459
1460 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1461         u8         field_select_8021qaurp[0x20];
1462 };
1463
1464 struct mlx5_ifc_phys_layer_cntrs_bits {
1465         u8         time_since_last_clear_high[0x20];
1466
1467         u8         time_since_last_clear_low[0x20];
1468
1469         u8         symbol_errors_high[0x20];
1470
1471         u8         symbol_errors_low[0x20];
1472
1473         u8         sync_headers_errors_high[0x20];
1474
1475         u8         sync_headers_errors_low[0x20];
1476
1477         u8         edpl_bip_errors_lane0_high[0x20];
1478
1479         u8         edpl_bip_errors_lane0_low[0x20];
1480
1481         u8         edpl_bip_errors_lane1_high[0x20];
1482
1483         u8         edpl_bip_errors_lane1_low[0x20];
1484
1485         u8         edpl_bip_errors_lane2_high[0x20];
1486
1487         u8         edpl_bip_errors_lane2_low[0x20];
1488
1489         u8         edpl_bip_errors_lane3_high[0x20];
1490
1491         u8         edpl_bip_errors_lane3_low[0x20];
1492
1493         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1494
1495         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1496
1497         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1498
1499         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1500
1501         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1502
1503         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1504
1505         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1506
1507         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1508
1509         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1510
1511         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1512
1513         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1514
1515         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1516
1517         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1518
1519         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1520
1521         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1522
1523         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1524
1525         u8         rs_fec_corrected_blocks_high[0x20];
1526
1527         u8         rs_fec_corrected_blocks_low[0x20];
1528
1529         u8         rs_fec_uncorrectable_blocks_high[0x20];
1530
1531         u8         rs_fec_uncorrectable_blocks_low[0x20];
1532
1533         u8         rs_fec_no_errors_blocks_high[0x20];
1534
1535         u8         rs_fec_no_errors_blocks_low[0x20];
1536
1537         u8         rs_fec_single_error_blocks_high[0x20];
1538
1539         u8         rs_fec_single_error_blocks_low[0x20];
1540
1541         u8         rs_fec_corrected_symbols_total_high[0x20];
1542
1543         u8         rs_fec_corrected_symbols_total_low[0x20];
1544
1545         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1546
1547         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1548
1549         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1550
1551         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1552
1553         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1554
1555         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1556
1557         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1558
1559         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1560
1561         u8         link_down_events[0x20];
1562
1563         u8         successful_recovery_events[0x20];
1564
1565         u8         reserved_at_640[0x180];
1566 };
1567
1568 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1569         u8         time_since_last_clear_high[0x20];
1570
1571         u8         time_since_last_clear_low[0x20];
1572
1573         u8         phy_received_bits_high[0x20];
1574
1575         u8         phy_received_bits_low[0x20];
1576
1577         u8         phy_symbol_errors_high[0x20];
1578
1579         u8         phy_symbol_errors_low[0x20];
1580
1581         u8         phy_corrected_bits_high[0x20];
1582
1583         u8         phy_corrected_bits_low[0x20];
1584
1585         u8         phy_corrected_bits_lane0_high[0x20];
1586
1587         u8         phy_corrected_bits_lane0_low[0x20];
1588
1589         u8         phy_corrected_bits_lane1_high[0x20];
1590
1591         u8         phy_corrected_bits_lane1_low[0x20];
1592
1593         u8         phy_corrected_bits_lane2_high[0x20];
1594
1595         u8         phy_corrected_bits_lane2_low[0x20];
1596
1597         u8         phy_corrected_bits_lane3_high[0x20];
1598
1599         u8         phy_corrected_bits_lane3_low[0x20];
1600
1601         u8         reserved_at_200[0x5c0];
1602 };
1603
1604 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1605         u8         symbol_error_counter[0x10];
1606
1607         u8         link_error_recovery_counter[0x8];
1608
1609         u8         link_downed_counter[0x8];
1610
1611         u8         port_rcv_errors[0x10];
1612
1613         u8         port_rcv_remote_physical_errors[0x10];
1614
1615         u8         port_rcv_switch_relay_errors[0x10];
1616
1617         u8         port_xmit_discards[0x10];
1618
1619         u8         port_xmit_constraint_errors[0x8];
1620
1621         u8         port_rcv_constraint_errors[0x8];
1622
1623         u8         reserved_at_70[0x8];
1624
1625         u8         link_overrun_errors[0x8];
1626
1627         u8         reserved_at_80[0x10];
1628
1629         u8         vl_15_dropped[0x10];
1630
1631         u8         reserved_at_a0[0x80];
1632
1633         u8         port_xmit_wait[0x20];
1634 };
1635
1636 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1637         u8         transmit_queue_high[0x20];
1638
1639         u8         transmit_queue_low[0x20];
1640
1641         u8         reserved_at_40[0x780];
1642 };
1643
1644 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1645         u8         rx_octets_high[0x20];
1646
1647         u8         rx_octets_low[0x20];
1648
1649         u8         reserved_at_40[0xc0];
1650
1651         u8         rx_frames_high[0x20];
1652
1653         u8         rx_frames_low[0x20];
1654
1655         u8         tx_octets_high[0x20];
1656
1657         u8         tx_octets_low[0x20];
1658
1659         u8         reserved_at_180[0xc0];
1660
1661         u8         tx_frames_high[0x20];
1662
1663         u8         tx_frames_low[0x20];
1664
1665         u8         rx_pause_high[0x20];
1666
1667         u8         rx_pause_low[0x20];
1668
1669         u8         rx_pause_duration_high[0x20];
1670
1671         u8         rx_pause_duration_low[0x20];
1672
1673         u8         tx_pause_high[0x20];
1674
1675         u8         tx_pause_low[0x20];
1676
1677         u8         tx_pause_duration_high[0x20];
1678
1679         u8         tx_pause_duration_low[0x20];
1680
1681         u8         rx_pause_transition_high[0x20];
1682
1683         u8         rx_pause_transition_low[0x20];
1684
1685         u8         reserved_at_3c0[0x40];
1686
1687         u8         device_stall_minor_watermark_cnt_high[0x20];
1688
1689         u8         device_stall_minor_watermark_cnt_low[0x20];
1690
1691         u8         device_stall_critical_watermark_cnt_high[0x20];
1692
1693         u8         device_stall_critical_watermark_cnt_low[0x20];
1694
1695         u8         reserved_at_480[0x340];
1696 };
1697
1698 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1699         u8         port_transmit_wait_high[0x20];
1700
1701         u8         port_transmit_wait_low[0x20];
1702
1703         u8         reserved_at_40[0x100];
1704
1705         u8         rx_buffer_almost_full_high[0x20];
1706
1707         u8         rx_buffer_almost_full_low[0x20];
1708
1709         u8         rx_buffer_full_high[0x20];
1710
1711         u8         rx_buffer_full_low[0x20];
1712
1713         u8         rx_icrc_encapsulated_high[0x20];
1714
1715         u8         rx_icrc_encapsulated_low[0x20];
1716
1717         u8         reserved_at_200[0x5c0];
1718 };
1719
1720 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1721         u8         dot3stats_alignment_errors_high[0x20];
1722
1723         u8         dot3stats_alignment_errors_low[0x20];
1724
1725         u8         dot3stats_fcs_errors_high[0x20];
1726
1727         u8         dot3stats_fcs_errors_low[0x20];
1728
1729         u8         dot3stats_single_collision_frames_high[0x20];
1730
1731         u8         dot3stats_single_collision_frames_low[0x20];
1732
1733         u8         dot3stats_multiple_collision_frames_high[0x20];
1734
1735         u8         dot3stats_multiple_collision_frames_low[0x20];
1736
1737         u8         dot3stats_sqe_test_errors_high[0x20];
1738
1739         u8         dot3stats_sqe_test_errors_low[0x20];
1740
1741         u8         dot3stats_deferred_transmissions_high[0x20];
1742
1743         u8         dot3stats_deferred_transmissions_low[0x20];
1744
1745         u8         dot3stats_late_collisions_high[0x20];
1746
1747         u8         dot3stats_late_collisions_low[0x20];
1748
1749         u8         dot3stats_excessive_collisions_high[0x20];
1750
1751         u8         dot3stats_excessive_collisions_low[0x20];
1752
1753         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1754
1755         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1756
1757         u8         dot3stats_carrier_sense_errors_high[0x20];
1758
1759         u8         dot3stats_carrier_sense_errors_low[0x20];
1760
1761         u8         dot3stats_frame_too_longs_high[0x20];
1762
1763         u8         dot3stats_frame_too_longs_low[0x20];
1764
1765         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1766
1767         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1768
1769         u8         dot3stats_symbol_errors_high[0x20];
1770
1771         u8         dot3stats_symbol_errors_low[0x20];
1772
1773         u8         dot3control_in_unknown_opcodes_high[0x20];
1774
1775         u8         dot3control_in_unknown_opcodes_low[0x20];
1776
1777         u8         dot3in_pause_frames_high[0x20];
1778
1779         u8         dot3in_pause_frames_low[0x20];
1780
1781         u8         dot3out_pause_frames_high[0x20];
1782
1783         u8         dot3out_pause_frames_low[0x20];
1784
1785         u8         reserved_at_400[0x3c0];
1786 };
1787
1788 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1789         u8         ether_stats_drop_events_high[0x20];
1790
1791         u8         ether_stats_drop_events_low[0x20];
1792
1793         u8         ether_stats_octets_high[0x20];
1794
1795         u8         ether_stats_octets_low[0x20];
1796
1797         u8         ether_stats_pkts_high[0x20];
1798
1799         u8         ether_stats_pkts_low[0x20];
1800
1801         u8         ether_stats_broadcast_pkts_high[0x20];
1802
1803         u8         ether_stats_broadcast_pkts_low[0x20];
1804
1805         u8         ether_stats_multicast_pkts_high[0x20];
1806
1807         u8         ether_stats_multicast_pkts_low[0x20];
1808
1809         u8         ether_stats_crc_align_errors_high[0x20];
1810
1811         u8         ether_stats_crc_align_errors_low[0x20];
1812
1813         u8         ether_stats_undersize_pkts_high[0x20];
1814
1815         u8         ether_stats_undersize_pkts_low[0x20];
1816
1817         u8         ether_stats_oversize_pkts_high[0x20];
1818
1819         u8         ether_stats_oversize_pkts_low[0x20];
1820
1821         u8         ether_stats_fragments_high[0x20];
1822
1823         u8         ether_stats_fragments_low[0x20];
1824
1825         u8         ether_stats_jabbers_high[0x20];
1826
1827         u8         ether_stats_jabbers_low[0x20];
1828
1829         u8         ether_stats_collisions_high[0x20];
1830
1831         u8         ether_stats_collisions_low[0x20];
1832
1833         u8         ether_stats_pkts64octets_high[0x20];
1834
1835         u8         ether_stats_pkts64octets_low[0x20];
1836
1837         u8         ether_stats_pkts65to127octets_high[0x20];
1838
1839         u8         ether_stats_pkts65to127octets_low[0x20];
1840
1841         u8         ether_stats_pkts128to255octets_high[0x20];
1842
1843         u8         ether_stats_pkts128to255octets_low[0x20];
1844
1845         u8         ether_stats_pkts256to511octets_high[0x20];
1846
1847         u8         ether_stats_pkts256to511octets_low[0x20];
1848
1849         u8         ether_stats_pkts512to1023octets_high[0x20];
1850
1851         u8         ether_stats_pkts512to1023octets_low[0x20];
1852
1853         u8         ether_stats_pkts1024to1518octets_high[0x20];
1854
1855         u8         ether_stats_pkts1024to1518octets_low[0x20];
1856
1857         u8         ether_stats_pkts1519to2047octets_high[0x20];
1858
1859         u8         ether_stats_pkts1519to2047octets_low[0x20];
1860
1861         u8         ether_stats_pkts2048to4095octets_high[0x20];
1862
1863         u8         ether_stats_pkts2048to4095octets_low[0x20];
1864
1865         u8         ether_stats_pkts4096to8191octets_high[0x20];
1866
1867         u8         ether_stats_pkts4096to8191octets_low[0x20];
1868
1869         u8         ether_stats_pkts8192to10239octets_high[0x20];
1870
1871         u8         ether_stats_pkts8192to10239octets_low[0x20];
1872
1873         u8         reserved_at_540[0x280];
1874 };
1875
1876 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1877         u8         if_in_octets_high[0x20];
1878
1879         u8         if_in_octets_low[0x20];
1880
1881         u8         if_in_ucast_pkts_high[0x20];
1882
1883         u8         if_in_ucast_pkts_low[0x20];
1884
1885         u8         if_in_discards_high[0x20];
1886
1887         u8         if_in_discards_low[0x20];
1888
1889         u8         if_in_errors_high[0x20];
1890
1891         u8         if_in_errors_low[0x20];
1892
1893         u8         if_in_unknown_protos_high[0x20];
1894
1895         u8         if_in_unknown_protos_low[0x20];
1896
1897         u8         if_out_octets_high[0x20];
1898
1899         u8         if_out_octets_low[0x20];
1900
1901         u8         if_out_ucast_pkts_high[0x20];
1902
1903         u8         if_out_ucast_pkts_low[0x20];
1904
1905         u8         if_out_discards_high[0x20];
1906
1907         u8         if_out_discards_low[0x20];
1908
1909         u8         if_out_errors_high[0x20];
1910
1911         u8         if_out_errors_low[0x20];
1912
1913         u8         if_in_multicast_pkts_high[0x20];
1914
1915         u8         if_in_multicast_pkts_low[0x20];
1916
1917         u8         if_in_broadcast_pkts_high[0x20];
1918
1919         u8         if_in_broadcast_pkts_low[0x20];
1920
1921         u8         if_out_multicast_pkts_high[0x20];
1922
1923         u8         if_out_multicast_pkts_low[0x20];
1924
1925         u8         if_out_broadcast_pkts_high[0x20];
1926
1927         u8         if_out_broadcast_pkts_low[0x20];
1928
1929         u8         reserved_at_340[0x480];
1930 };
1931
1932 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1933         u8         a_frames_transmitted_ok_high[0x20];
1934
1935         u8         a_frames_transmitted_ok_low[0x20];
1936
1937         u8         a_frames_received_ok_high[0x20];
1938
1939         u8         a_frames_received_ok_low[0x20];
1940
1941         u8         a_frame_check_sequence_errors_high[0x20];
1942
1943         u8         a_frame_check_sequence_errors_low[0x20];
1944
1945         u8         a_alignment_errors_high[0x20];
1946
1947         u8         a_alignment_errors_low[0x20];
1948
1949         u8         a_octets_transmitted_ok_high[0x20];
1950
1951         u8         a_octets_transmitted_ok_low[0x20];
1952
1953         u8         a_octets_received_ok_high[0x20];
1954
1955         u8         a_octets_received_ok_low[0x20];
1956
1957         u8         a_multicast_frames_xmitted_ok_high[0x20];
1958
1959         u8         a_multicast_frames_xmitted_ok_low[0x20];
1960
1961         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1962
1963         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1964
1965         u8         a_multicast_frames_received_ok_high[0x20];
1966
1967         u8         a_multicast_frames_received_ok_low[0x20];
1968
1969         u8         a_broadcast_frames_received_ok_high[0x20];
1970
1971         u8         a_broadcast_frames_received_ok_low[0x20];
1972
1973         u8         a_in_range_length_errors_high[0x20];
1974
1975         u8         a_in_range_length_errors_low[0x20];
1976
1977         u8         a_out_of_range_length_field_high[0x20];
1978
1979         u8         a_out_of_range_length_field_low[0x20];
1980
1981         u8         a_frame_too_long_errors_high[0x20];
1982
1983         u8         a_frame_too_long_errors_low[0x20];
1984
1985         u8         a_symbol_error_during_carrier_high[0x20];
1986
1987         u8         a_symbol_error_during_carrier_low[0x20];
1988
1989         u8         a_mac_control_frames_transmitted_high[0x20];
1990
1991         u8         a_mac_control_frames_transmitted_low[0x20];
1992
1993         u8         a_mac_control_frames_received_high[0x20];
1994
1995         u8         a_mac_control_frames_received_low[0x20];
1996
1997         u8         a_unsupported_opcodes_received_high[0x20];
1998
1999         u8         a_unsupported_opcodes_received_low[0x20];
2000
2001         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2002
2003         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2004
2005         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2006
2007         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2008
2009         u8         reserved_at_4c0[0x300];
2010 };
2011
2012 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2013         u8         life_time_counter_high[0x20];
2014
2015         u8         life_time_counter_low[0x20];
2016
2017         u8         rx_errors[0x20];
2018
2019         u8         tx_errors[0x20];
2020
2021         u8         l0_to_recovery_eieos[0x20];
2022
2023         u8         l0_to_recovery_ts[0x20];
2024
2025         u8         l0_to_recovery_framing[0x20];
2026
2027         u8         l0_to_recovery_retrain[0x20];
2028
2029         u8         crc_error_dllp[0x20];
2030
2031         u8         crc_error_tlp[0x20];
2032
2033         u8         tx_overflow_buffer_pkt_high[0x20];
2034
2035         u8         tx_overflow_buffer_pkt_low[0x20];
2036
2037         u8         outbound_stalled_reads[0x20];
2038
2039         u8         outbound_stalled_writes[0x20];
2040
2041         u8         outbound_stalled_reads_events[0x20];
2042
2043         u8         outbound_stalled_writes_events[0x20];
2044
2045         u8         reserved_at_200[0x5c0];
2046 };
2047
2048 struct mlx5_ifc_cmd_inter_comp_event_bits {
2049         u8         command_completion_vector[0x20];
2050
2051         u8         reserved_at_20[0xc0];
2052 };
2053
2054 struct mlx5_ifc_stall_vl_event_bits {
2055         u8         reserved_at_0[0x18];
2056         u8         port_num[0x1];
2057         u8         reserved_at_19[0x3];
2058         u8         vl[0x4];
2059
2060         u8         reserved_at_20[0xa0];
2061 };
2062
2063 struct mlx5_ifc_db_bf_congestion_event_bits {
2064         u8         event_subtype[0x8];
2065         u8         reserved_at_8[0x8];
2066         u8         congestion_level[0x8];
2067         u8         reserved_at_18[0x8];
2068
2069         u8         reserved_at_20[0xa0];
2070 };
2071
2072 struct mlx5_ifc_gpio_event_bits {
2073         u8         reserved_at_0[0x60];
2074
2075         u8         gpio_event_hi[0x20];
2076
2077         u8         gpio_event_lo[0x20];
2078
2079         u8         reserved_at_a0[0x40];
2080 };
2081
2082 struct mlx5_ifc_port_state_change_event_bits {
2083         u8         reserved_at_0[0x40];
2084
2085         u8         port_num[0x4];
2086         u8         reserved_at_44[0x1c];
2087
2088         u8         reserved_at_60[0x80];
2089 };
2090
2091 struct mlx5_ifc_dropped_packet_logged_bits {
2092         u8         reserved_at_0[0xe0];
2093 };
2094
2095 enum {
2096         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2097         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2098 };
2099
2100 struct mlx5_ifc_cq_error_bits {
2101         u8         reserved_at_0[0x8];
2102         u8         cqn[0x18];
2103
2104         u8         reserved_at_20[0x20];
2105
2106         u8         reserved_at_40[0x18];
2107         u8         syndrome[0x8];
2108
2109         u8         reserved_at_60[0x80];
2110 };
2111
2112 struct mlx5_ifc_rdma_page_fault_event_bits {
2113         u8         bytes_committed[0x20];
2114
2115         u8         r_key[0x20];
2116
2117         u8         reserved_at_40[0x10];
2118         u8         packet_len[0x10];
2119
2120         u8         rdma_op_len[0x20];
2121
2122         u8         rdma_va[0x40];
2123
2124         u8         reserved_at_c0[0x5];
2125         u8         rdma[0x1];
2126         u8         write[0x1];
2127         u8         requestor[0x1];
2128         u8         qp_number[0x18];
2129 };
2130
2131 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2132         u8         bytes_committed[0x20];
2133
2134         u8         reserved_at_20[0x10];
2135         u8         wqe_index[0x10];
2136
2137         u8         reserved_at_40[0x10];
2138         u8         len[0x10];
2139
2140         u8         reserved_at_60[0x60];
2141
2142         u8         reserved_at_c0[0x5];
2143         u8         rdma[0x1];
2144         u8         write_read[0x1];
2145         u8         requestor[0x1];
2146         u8         qpn[0x18];
2147 };
2148
2149 struct mlx5_ifc_qp_events_bits {
2150         u8         reserved_at_0[0xa0];
2151
2152         u8         type[0x8];
2153         u8         reserved_at_a8[0x18];
2154
2155         u8         reserved_at_c0[0x8];
2156         u8         qpn_rqn_sqn[0x18];
2157 };
2158
2159 struct mlx5_ifc_dct_events_bits {
2160         u8         reserved_at_0[0xc0];
2161
2162         u8         reserved_at_c0[0x8];
2163         u8         dct_number[0x18];
2164 };
2165
2166 struct mlx5_ifc_comp_event_bits {
2167         u8         reserved_at_0[0xc0];
2168
2169         u8         reserved_at_c0[0x8];
2170         u8         cq_number[0x18];
2171 };
2172
2173 enum {
2174         MLX5_QPC_STATE_RST        = 0x0,
2175         MLX5_QPC_STATE_INIT       = 0x1,
2176         MLX5_QPC_STATE_RTR        = 0x2,
2177         MLX5_QPC_STATE_RTS        = 0x3,
2178         MLX5_QPC_STATE_SQER       = 0x4,
2179         MLX5_QPC_STATE_ERR        = 0x6,
2180         MLX5_QPC_STATE_SQD        = 0x7,
2181         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2182 };
2183
2184 enum {
2185         MLX5_QPC_ST_RC            = 0x0,
2186         MLX5_QPC_ST_UC            = 0x1,
2187         MLX5_QPC_ST_UD            = 0x2,
2188         MLX5_QPC_ST_XRC           = 0x3,
2189         MLX5_QPC_ST_DCI           = 0x5,
2190         MLX5_QPC_ST_QP0           = 0x7,
2191         MLX5_QPC_ST_QP1           = 0x8,
2192         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2193         MLX5_QPC_ST_REG_UMR       = 0xc,
2194 };
2195
2196 enum {
2197         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2198         MLX5_QPC_PM_STATE_REARM     = 0x1,
2199         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2200         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2201 };
2202
2203 enum {
2204         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2205 };
2206
2207 enum {
2208         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2209         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2210 };
2211
2212 enum {
2213         MLX5_QPC_MTU_256_BYTES        = 0x1,
2214         MLX5_QPC_MTU_512_BYTES        = 0x2,
2215         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2216         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2217         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2218         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2219 };
2220
2221 enum {
2222         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2223         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2224         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2225         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2226         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2227         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2228         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2229         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2230 };
2231
2232 enum {
2233         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2234         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2235         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2236 };
2237
2238 enum {
2239         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2240         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2241         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2242 };
2243
2244 struct mlx5_ifc_qpc_bits {
2245         u8         state[0x4];
2246         u8         lag_tx_port_affinity[0x4];
2247         u8         st[0x8];
2248         u8         reserved_at_10[0x3];
2249         u8         pm_state[0x2];
2250         u8         reserved_at_15[0x3];
2251         u8         offload_type[0x4];
2252         u8         end_padding_mode[0x2];
2253         u8         reserved_at_1e[0x2];
2254
2255         u8         wq_signature[0x1];
2256         u8         block_lb_mc[0x1];
2257         u8         atomic_like_write_en[0x1];
2258         u8         latency_sensitive[0x1];
2259         u8         reserved_at_24[0x1];
2260         u8         drain_sigerr[0x1];
2261         u8         reserved_at_26[0x2];
2262         u8         pd[0x18];
2263
2264         u8         mtu[0x3];
2265         u8         log_msg_max[0x5];
2266         u8         reserved_at_48[0x1];
2267         u8         log_rq_size[0x4];
2268         u8         log_rq_stride[0x3];
2269         u8         no_sq[0x1];
2270         u8         log_sq_size[0x4];
2271         u8         reserved_at_55[0x6];
2272         u8         rlky[0x1];
2273         u8         ulp_stateless_offload_mode[0x4];
2274
2275         u8         counter_set_id[0x8];
2276         u8         uar_page[0x18];
2277
2278         u8         reserved_at_80[0x8];
2279         u8         user_index[0x18];
2280
2281         u8         reserved_at_a0[0x3];
2282         u8         log_page_size[0x5];
2283         u8         remote_qpn[0x18];
2284
2285         struct mlx5_ifc_ads_bits primary_address_path;
2286
2287         struct mlx5_ifc_ads_bits secondary_address_path;
2288
2289         u8         log_ack_req_freq[0x4];
2290         u8         reserved_at_384[0x4];
2291         u8         log_sra_max[0x3];
2292         u8         reserved_at_38b[0x2];
2293         u8         retry_count[0x3];
2294         u8         rnr_retry[0x3];
2295         u8         reserved_at_393[0x1];
2296         u8         fre[0x1];
2297         u8         cur_rnr_retry[0x3];
2298         u8         cur_retry_count[0x3];
2299         u8         reserved_at_39b[0x5];
2300
2301         u8         reserved_at_3a0[0x20];
2302
2303         u8         reserved_at_3c0[0x8];
2304         u8         next_send_psn[0x18];
2305
2306         u8         reserved_at_3e0[0x8];
2307         u8         cqn_snd[0x18];
2308
2309         u8         reserved_at_400[0x8];
2310         u8         deth_sqpn[0x18];
2311
2312         u8         reserved_at_420[0x20];
2313
2314         u8         reserved_at_440[0x8];
2315         u8         last_acked_psn[0x18];
2316
2317         u8         reserved_at_460[0x8];
2318         u8         ssn[0x18];
2319
2320         u8         reserved_at_480[0x8];
2321         u8         log_rra_max[0x3];
2322         u8         reserved_at_48b[0x1];
2323         u8         atomic_mode[0x4];
2324         u8         rre[0x1];
2325         u8         rwe[0x1];
2326         u8         rae[0x1];
2327         u8         reserved_at_493[0x1];
2328         u8         page_offset[0x6];
2329         u8         reserved_at_49a[0x3];
2330         u8         cd_slave_receive[0x1];
2331         u8         cd_slave_send[0x1];
2332         u8         cd_master[0x1];
2333
2334         u8         reserved_at_4a0[0x3];
2335         u8         min_rnr_nak[0x5];
2336         u8         next_rcv_psn[0x18];
2337
2338         u8         reserved_at_4c0[0x8];
2339         u8         xrcd[0x18];
2340
2341         u8         reserved_at_4e0[0x8];
2342         u8         cqn_rcv[0x18];
2343
2344         u8         dbr_addr[0x40];
2345
2346         u8         q_key[0x20];
2347
2348         u8         reserved_at_560[0x5];
2349         u8         rq_type[0x3];
2350         u8         srqn_rmpn_xrqn[0x18];
2351
2352         u8         reserved_at_580[0x8];
2353         u8         rmsn[0x18];
2354
2355         u8         hw_sq_wqebb_counter[0x10];
2356         u8         sw_sq_wqebb_counter[0x10];
2357
2358         u8         hw_rq_counter[0x20];
2359
2360         u8         sw_rq_counter[0x20];
2361
2362         u8         reserved_at_600[0x20];
2363
2364         u8         reserved_at_620[0xf];
2365         u8         cgs[0x1];
2366         u8         cs_req[0x8];
2367         u8         cs_res[0x8];
2368
2369         u8         dc_access_key[0x40];
2370
2371         u8         reserved_at_680[0x3];
2372         u8         dbr_umem_valid[0x1];
2373
2374         u8         reserved_at_684[0xbc];
2375 };
2376
2377 struct mlx5_ifc_roce_addr_layout_bits {
2378         u8         source_l3_address[16][0x8];
2379
2380         u8         reserved_at_80[0x3];
2381         u8         vlan_valid[0x1];
2382         u8         vlan_id[0xc];
2383         u8         source_mac_47_32[0x10];
2384
2385         u8         source_mac_31_0[0x20];
2386
2387         u8         reserved_at_c0[0x14];
2388         u8         roce_l3_type[0x4];
2389         u8         roce_version[0x8];
2390
2391         u8         reserved_at_e0[0x20];
2392 };
2393
2394 union mlx5_ifc_hca_cap_union_bits {
2395         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2396         struct mlx5_ifc_odp_cap_bits odp_cap;
2397         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2398         struct mlx5_ifc_roce_cap_bits roce_cap;
2399         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2400         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2401         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2402         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2403         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2404         struct mlx5_ifc_qos_cap_bits qos_cap;
2405         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2406         u8         reserved_at_0[0x8000];
2407 };
2408
2409 enum {
2410         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2411         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2412         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2413         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2414         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2415         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2416         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2417         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2418         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2419         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2420         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2421 };
2422
2423 struct mlx5_ifc_vlan_bits {
2424         u8         ethtype[0x10];
2425         u8         prio[0x3];
2426         u8         cfi[0x1];
2427         u8         vid[0xc];
2428 };
2429
2430 struct mlx5_ifc_flow_context_bits {
2431         struct mlx5_ifc_vlan_bits push_vlan;
2432
2433         u8         group_id[0x20];
2434
2435         u8         reserved_at_40[0x8];
2436         u8         flow_tag[0x18];
2437
2438         u8         reserved_at_60[0x10];
2439         u8         action[0x10];
2440
2441         u8         reserved_at_80[0x8];
2442         u8         destination_list_size[0x18];
2443
2444         u8         reserved_at_a0[0x8];
2445         u8         flow_counter_list_size[0x18];
2446
2447         u8         packet_reformat_id[0x20];
2448
2449         u8         modify_header_id[0x20];
2450
2451         struct mlx5_ifc_vlan_bits push_vlan_2;
2452
2453         u8         reserved_at_120[0xe0];
2454
2455         struct mlx5_ifc_fte_match_param_bits match_value;
2456
2457         u8         reserved_at_1200[0x600];
2458
2459         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2460 };
2461
2462 enum {
2463         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2464         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2465 };
2466
2467 struct mlx5_ifc_xrc_srqc_bits {
2468         u8         state[0x4];
2469         u8         log_xrc_srq_size[0x4];
2470         u8         reserved_at_8[0x18];
2471
2472         u8         wq_signature[0x1];
2473         u8         cont_srq[0x1];
2474         u8         dbr_umem_valid[0x1];
2475         u8         rlky[0x1];
2476         u8         basic_cyclic_rcv_wqe[0x1];
2477         u8         log_rq_stride[0x3];
2478         u8         xrcd[0x18];
2479
2480         u8         page_offset[0x6];
2481         u8         reserved_at_46[0x2];
2482         u8         cqn[0x18];
2483
2484         u8         reserved_at_60[0x20];
2485
2486         u8         user_index_equal_xrc_srqn[0x1];
2487         u8         reserved_at_81[0x1];
2488         u8         log_page_size[0x6];
2489         u8         user_index[0x18];
2490
2491         u8         reserved_at_a0[0x20];
2492
2493         u8         reserved_at_c0[0x8];
2494         u8         pd[0x18];
2495
2496         u8         lwm[0x10];
2497         u8         wqe_cnt[0x10];
2498
2499         u8         reserved_at_100[0x40];
2500
2501         u8         db_record_addr_h[0x20];
2502
2503         u8         db_record_addr_l[0x1e];
2504         u8         reserved_at_17e[0x2];
2505
2506         u8         reserved_at_180[0x80];
2507 };
2508
2509 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2510         u8         counter_error_queues[0x20];
2511
2512         u8         total_error_queues[0x20];
2513
2514         u8         send_queue_priority_update_flow[0x20];
2515
2516         u8         reserved_at_60[0x20];
2517
2518         u8         nic_receive_steering_discard[0x40];
2519
2520         u8         receive_discard_vport_down[0x40];
2521
2522         u8         transmit_discard_vport_down[0x40];
2523
2524         u8         reserved_at_140[0xec0];
2525 };
2526
2527 struct mlx5_ifc_traffic_counter_bits {
2528         u8         packets[0x40];
2529
2530         u8         octets[0x40];
2531 };
2532
2533 struct mlx5_ifc_tisc_bits {
2534         u8         strict_lag_tx_port_affinity[0x1];
2535         u8         reserved_at_1[0x3];
2536         u8         lag_tx_port_affinity[0x04];
2537
2538         u8         reserved_at_8[0x4];
2539         u8         prio[0x4];
2540         u8         reserved_at_10[0x10];
2541
2542         u8         reserved_at_20[0x100];
2543
2544         u8         reserved_at_120[0x8];
2545         u8         transport_domain[0x18];
2546
2547         u8         reserved_at_140[0x8];
2548         u8         underlay_qpn[0x18];
2549         u8         reserved_at_160[0x3a0];
2550 };
2551
2552 enum {
2553         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2554         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2555 };
2556
2557 enum {
2558         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2559         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2560 };
2561
2562 enum {
2563         MLX5_RX_HASH_FN_NONE           = 0x0,
2564         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2565         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2566 };
2567
2568 enum {
2569         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2570         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2571 };
2572
2573 struct mlx5_ifc_tirc_bits {
2574         u8         reserved_at_0[0x20];
2575
2576         u8         disp_type[0x4];
2577         u8         reserved_at_24[0x1c];
2578
2579         u8         reserved_at_40[0x40];
2580
2581         u8         reserved_at_80[0x4];
2582         u8         lro_timeout_period_usecs[0x10];
2583         u8         lro_enable_mask[0x4];
2584         u8         lro_max_ip_payload_size[0x8];
2585
2586         u8         reserved_at_a0[0x40];
2587
2588         u8         reserved_at_e0[0x8];
2589         u8         inline_rqn[0x18];
2590
2591         u8         rx_hash_symmetric[0x1];
2592         u8         reserved_at_101[0x1];
2593         u8         tunneled_offload_en[0x1];
2594         u8         reserved_at_103[0x5];
2595         u8         indirect_table[0x18];
2596
2597         u8         rx_hash_fn[0x4];
2598         u8         reserved_at_124[0x2];
2599         u8         self_lb_block[0x2];
2600         u8         transport_domain[0x18];
2601
2602         u8         rx_hash_toeplitz_key[10][0x20];
2603
2604         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2605
2606         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2607
2608         u8         reserved_at_2c0[0x4c0];
2609 };
2610
2611 enum {
2612         MLX5_SRQC_STATE_GOOD   = 0x0,
2613         MLX5_SRQC_STATE_ERROR  = 0x1,
2614 };
2615
2616 struct mlx5_ifc_srqc_bits {
2617         u8         state[0x4];
2618         u8         log_srq_size[0x4];
2619         u8         reserved_at_8[0x18];
2620
2621         u8         wq_signature[0x1];
2622         u8         cont_srq[0x1];
2623         u8         reserved_at_22[0x1];
2624         u8         rlky[0x1];
2625         u8         reserved_at_24[0x1];
2626         u8         log_rq_stride[0x3];
2627         u8         xrcd[0x18];
2628
2629         u8         page_offset[0x6];
2630         u8         reserved_at_46[0x2];
2631         u8         cqn[0x18];
2632
2633         u8         reserved_at_60[0x20];
2634
2635         u8         reserved_at_80[0x2];
2636         u8         log_page_size[0x6];
2637         u8         reserved_at_88[0x18];
2638
2639         u8         reserved_at_a0[0x20];
2640
2641         u8         reserved_at_c0[0x8];
2642         u8         pd[0x18];
2643
2644         u8         lwm[0x10];
2645         u8         wqe_cnt[0x10];
2646
2647         u8         reserved_at_100[0x40];
2648
2649         u8         dbr_addr[0x40];
2650
2651         u8         reserved_at_180[0x80];
2652 };
2653
2654 enum {
2655         MLX5_SQC_STATE_RST  = 0x0,
2656         MLX5_SQC_STATE_RDY  = 0x1,
2657         MLX5_SQC_STATE_ERR  = 0x3,
2658 };
2659
2660 struct mlx5_ifc_sqc_bits {
2661         u8         rlky[0x1];
2662         u8         cd_master[0x1];
2663         u8         fre[0x1];
2664         u8         flush_in_error_en[0x1];
2665         u8         allow_multi_pkt_send_wqe[0x1];
2666         u8         min_wqe_inline_mode[0x3];
2667         u8         state[0x4];
2668         u8         reg_umr[0x1];
2669         u8         allow_swp[0x1];
2670         u8         hairpin[0x1];
2671         u8         reserved_at_f[0x11];
2672
2673         u8         reserved_at_20[0x8];
2674         u8         user_index[0x18];
2675
2676         u8         reserved_at_40[0x8];
2677         u8         cqn[0x18];
2678
2679         u8         reserved_at_60[0x8];
2680         u8         hairpin_peer_rq[0x18];
2681
2682         u8         reserved_at_80[0x10];
2683         u8         hairpin_peer_vhca[0x10];
2684
2685         u8         reserved_at_a0[0x50];
2686
2687         u8         packet_pacing_rate_limit_index[0x10];
2688         u8         tis_lst_sz[0x10];
2689         u8         reserved_at_110[0x10];
2690
2691         u8         reserved_at_120[0x40];
2692
2693         u8         reserved_at_160[0x8];
2694         u8         tis_num_0[0x18];
2695
2696         struct mlx5_ifc_wq_bits wq;
2697 };
2698
2699 enum {
2700         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2701         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2702         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2703         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2704 };
2705
2706 struct mlx5_ifc_scheduling_context_bits {
2707         u8         element_type[0x8];
2708         u8         reserved_at_8[0x18];
2709
2710         u8         element_attributes[0x20];
2711
2712         u8         parent_element_id[0x20];
2713
2714         u8         reserved_at_60[0x40];
2715
2716         u8         bw_share[0x20];
2717
2718         u8         max_average_bw[0x20];
2719
2720         u8         reserved_at_e0[0x120];
2721 };
2722
2723 struct mlx5_ifc_rqtc_bits {
2724         u8         reserved_at_0[0xa0];
2725
2726         u8         reserved_at_a0[0x10];
2727         u8         rqt_max_size[0x10];
2728
2729         u8         reserved_at_c0[0x10];
2730         u8         rqt_actual_size[0x10];
2731
2732         u8         reserved_at_e0[0x6a0];
2733
2734         struct mlx5_ifc_rq_num_bits rq_num[0];
2735 };
2736
2737 enum {
2738         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2739         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2740 };
2741
2742 enum {
2743         MLX5_RQC_STATE_RST  = 0x0,
2744         MLX5_RQC_STATE_RDY  = 0x1,
2745         MLX5_RQC_STATE_ERR  = 0x3,
2746 };
2747
2748 struct mlx5_ifc_rqc_bits {
2749         u8         rlky[0x1];
2750         u8         delay_drop_en[0x1];
2751         u8         scatter_fcs[0x1];
2752         u8         vsd[0x1];
2753         u8         mem_rq_type[0x4];
2754         u8         state[0x4];
2755         u8         reserved_at_c[0x1];
2756         u8         flush_in_error_en[0x1];
2757         u8         hairpin[0x1];
2758         u8         reserved_at_f[0x11];
2759
2760         u8         reserved_at_20[0x8];
2761         u8         user_index[0x18];
2762
2763         u8         reserved_at_40[0x8];
2764         u8         cqn[0x18];
2765
2766         u8         counter_set_id[0x8];
2767         u8         reserved_at_68[0x18];
2768
2769         u8         reserved_at_80[0x8];
2770         u8         rmpn[0x18];
2771
2772         u8         reserved_at_a0[0x8];
2773         u8         hairpin_peer_sq[0x18];
2774
2775         u8         reserved_at_c0[0x10];
2776         u8         hairpin_peer_vhca[0x10];
2777
2778         u8         reserved_at_e0[0xa0];
2779
2780         struct mlx5_ifc_wq_bits wq;
2781 };
2782
2783 enum {
2784         MLX5_RMPC_STATE_RDY  = 0x1,
2785         MLX5_RMPC_STATE_ERR  = 0x3,
2786 };
2787
2788 struct mlx5_ifc_rmpc_bits {
2789         u8         reserved_at_0[0x8];
2790         u8         state[0x4];
2791         u8         reserved_at_c[0x14];
2792
2793         u8         basic_cyclic_rcv_wqe[0x1];
2794         u8         reserved_at_21[0x1f];
2795
2796         u8         reserved_at_40[0x140];
2797
2798         struct mlx5_ifc_wq_bits wq;
2799 };
2800
2801 struct mlx5_ifc_nic_vport_context_bits {
2802         u8         reserved_at_0[0x5];
2803         u8         min_wqe_inline_mode[0x3];
2804         u8         reserved_at_8[0x15];
2805         u8         disable_mc_local_lb[0x1];
2806         u8         disable_uc_local_lb[0x1];
2807         u8         roce_en[0x1];
2808
2809         u8         arm_change_event[0x1];
2810         u8         reserved_at_21[0x1a];
2811         u8         event_on_mtu[0x1];
2812         u8         event_on_promisc_change[0x1];
2813         u8         event_on_vlan_change[0x1];
2814         u8         event_on_mc_address_change[0x1];
2815         u8         event_on_uc_address_change[0x1];
2816
2817         u8         reserved_at_40[0xc];
2818
2819         u8         affiliation_criteria[0x4];
2820         u8         affiliated_vhca_id[0x10];
2821
2822         u8         reserved_at_60[0xd0];
2823
2824         u8         mtu[0x10];
2825
2826         u8         system_image_guid[0x40];
2827         u8         port_guid[0x40];
2828         u8         node_guid[0x40];
2829
2830         u8         reserved_at_200[0x140];
2831         u8         qkey_violation_counter[0x10];
2832         u8         reserved_at_350[0x430];
2833
2834         u8         promisc_uc[0x1];
2835         u8         promisc_mc[0x1];
2836         u8         promisc_all[0x1];
2837         u8         reserved_at_783[0x2];
2838         u8         allowed_list_type[0x3];
2839         u8         reserved_at_788[0xc];
2840         u8         allowed_list_size[0xc];
2841
2842         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2843
2844         u8         reserved_at_7e0[0x20];
2845
2846         u8         current_uc_mac_address[0][0x40];
2847 };
2848
2849 enum {
2850         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2851         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2852         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2853         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2854         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2855 };
2856
2857 struct mlx5_ifc_mkc_bits {
2858         u8         reserved_at_0[0x1];
2859         u8         free[0x1];
2860         u8         reserved_at_2[0x1];
2861         u8         access_mode_4_2[0x3];
2862         u8         reserved_at_6[0x7];
2863         u8         relaxed_ordering_write[0x1];
2864         u8         reserved_at_e[0x1];
2865         u8         small_fence_on_rdma_read_response[0x1];
2866         u8         umr_en[0x1];
2867         u8         a[0x1];
2868         u8         rw[0x1];
2869         u8         rr[0x1];
2870         u8         lw[0x1];
2871         u8         lr[0x1];
2872         u8         access_mode_1_0[0x2];
2873         u8         reserved_at_18[0x8];
2874
2875         u8         qpn[0x18];
2876         u8         mkey_7_0[0x8];
2877
2878         u8         reserved_at_40[0x20];
2879
2880         u8         length64[0x1];
2881         u8         bsf_en[0x1];
2882         u8         sync_umr[0x1];
2883         u8         reserved_at_63[0x2];
2884         u8         expected_sigerr_count[0x1];
2885         u8         reserved_at_66[0x1];
2886         u8         en_rinval[0x1];
2887         u8         pd[0x18];
2888
2889         u8         start_addr[0x40];
2890
2891         u8         len[0x40];
2892
2893         u8         bsf_octword_size[0x20];
2894
2895         u8         reserved_at_120[0x80];
2896
2897         u8         translations_octword_size[0x20];
2898
2899         u8         reserved_at_1c0[0x1b];
2900         u8         log_page_size[0x5];
2901
2902         u8         reserved_at_1e0[0x20];
2903 };
2904
2905 struct mlx5_ifc_pkey_bits {
2906         u8         reserved_at_0[0x10];
2907         u8         pkey[0x10];
2908 };
2909
2910 struct mlx5_ifc_array128_auto_bits {
2911         u8         array128_auto[16][0x8];
2912 };
2913
2914 struct mlx5_ifc_hca_vport_context_bits {
2915         u8         field_select[0x20];
2916
2917         u8         reserved_at_20[0xe0];
2918
2919         u8         sm_virt_aware[0x1];
2920         u8         has_smi[0x1];
2921         u8         has_raw[0x1];
2922         u8         grh_required[0x1];
2923         u8         reserved_at_104[0xc];
2924         u8         port_physical_state[0x4];
2925         u8         vport_state_policy[0x4];
2926         u8         port_state[0x4];
2927         u8         vport_state[0x4];
2928
2929         u8         reserved_at_120[0x20];
2930
2931         u8         system_image_guid[0x40];
2932
2933         u8         port_guid[0x40];
2934
2935         u8         node_guid[0x40];
2936
2937         u8         cap_mask1[0x20];
2938
2939         u8         cap_mask1_field_select[0x20];
2940
2941         u8         cap_mask2[0x20];
2942
2943         u8         cap_mask2_field_select[0x20];
2944
2945         u8         reserved_at_280[0x80];
2946
2947         u8         lid[0x10];
2948         u8         reserved_at_310[0x4];
2949         u8         init_type_reply[0x4];
2950         u8         lmc[0x3];
2951         u8         subnet_timeout[0x5];
2952
2953         u8         sm_lid[0x10];
2954         u8         sm_sl[0x4];
2955         u8         reserved_at_334[0xc];
2956
2957         u8         qkey_violation_counter[0x10];
2958         u8         pkey_violation_counter[0x10];
2959
2960         u8         reserved_at_360[0xca0];
2961 };
2962
2963 struct mlx5_ifc_esw_vport_context_bits {
2964         u8         reserved_at_0[0x3];
2965         u8         vport_svlan_strip[0x1];
2966         u8         vport_cvlan_strip[0x1];
2967         u8         vport_svlan_insert[0x1];
2968         u8         vport_cvlan_insert[0x2];
2969         u8         reserved_at_8[0x18];
2970
2971         u8         reserved_at_20[0x20];
2972
2973         u8         svlan_cfi[0x1];
2974         u8         svlan_pcp[0x3];
2975         u8         svlan_id[0xc];
2976         u8         cvlan_cfi[0x1];
2977         u8         cvlan_pcp[0x3];
2978         u8         cvlan_id[0xc];
2979
2980         u8         reserved_at_60[0x7a0];
2981 };
2982
2983 enum {
2984         MLX5_EQC_STATUS_OK                = 0x0,
2985         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2986 };
2987
2988 enum {
2989         MLX5_EQC_ST_ARMED  = 0x9,
2990         MLX5_EQC_ST_FIRED  = 0xa,
2991 };
2992
2993 struct mlx5_ifc_eqc_bits {
2994         u8         status[0x4];
2995         u8         reserved_at_4[0x9];
2996         u8         ec[0x1];
2997         u8         oi[0x1];
2998         u8         reserved_at_f[0x5];
2999         u8         st[0x4];
3000         u8         reserved_at_18[0x8];
3001
3002         u8         reserved_at_20[0x20];
3003
3004         u8         reserved_at_40[0x14];
3005         u8         page_offset[0x6];
3006         u8         reserved_at_5a[0x6];
3007
3008         u8         reserved_at_60[0x3];
3009         u8         log_eq_size[0x5];
3010         u8         uar_page[0x18];
3011
3012         u8         reserved_at_80[0x20];
3013
3014         u8         reserved_at_a0[0x18];
3015         u8         intr[0x8];
3016
3017         u8         reserved_at_c0[0x3];
3018         u8         log_page_size[0x5];
3019         u8         reserved_at_c8[0x18];
3020
3021         u8         reserved_at_e0[0x60];
3022
3023         u8         reserved_at_140[0x8];
3024         u8         consumer_counter[0x18];
3025
3026         u8         reserved_at_160[0x8];
3027         u8         producer_counter[0x18];
3028
3029         u8         reserved_at_180[0x80];
3030 };
3031
3032 enum {
3033         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3034         MLX5_DCTC_STATE_DRAINING  = 0x1,
3035         MLX5_DCTC_STATE_DRAINED   = 0x2,
3036 };
3037
3038 enum {
3039         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3040         MLX5_DCTC_CS_RES_NA         = 0x1,
3041         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3042 };
3043
3044 enum {
3045         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3046         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3047         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3048         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3049         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3050 };
3051
3052 struct mlx5_ifc_dctc_bits {
3053         u8         reserved_at_0[0x4];
3054         u8         state[0x4];
3055         u8         reserved_at_8[0x18];
3056
3057         u8         reserved_at_20[0x8];
3058         u8         user_index[0x18];
3059
3060         u8         reserved_at_40[0x8];
3061         u8         cqn[0x18];
3062
3063         u8         counter_set_id[0x8];
3064         u8         atomic_mode[0x4];
3065         u8         rre[0x1];
3066         u8         rwe[0x1];
3067         u8         rae[0x1];
3068         u8         atomic_like_write_en[0x1];
3069         u8         latency_sensitive[0x1];
3070         u8         rlky[0x1];
3071         u8         free_ar[0x1];
3072         u8         reserved_at_73[0xd];
3073
3074         u8         reserved_at_80[0x8];
3075         u8         cs_res[0x8];
3076         u8         reserved_at_90[0x3];
3077         u8         min_rnr_nak[0x5];
3078         u8         reserved_at_98[0x8];
3079
3080         u8         reserved_at_a0[0x8];
3081         u8         srqn_xrqn[0x18];
3082
3083         u8         reserved_at_c0[0x8];
3084         u8         pd[0x18];
3085
3086         u8         tclass[0x8];
3087         u8         reserved_at_e8[0x4];
3088         u8         flow_label[0x14];
3089
3090         u8         dc_access_key[0x40];
3091
3092         u8         reserved_at_140[0x5];
3093         u8         mtu[0x3];
3094         u8         port[0x8];
3095         u8         pkey_index[0x10];
3096
3097         u8         reserved_at_160[0x8];
3098         u8         my_addr_index[0x8];
3099         u8         reserved_at_170[0x8];
3100         u8         hop_limit[0x8];
3101
3102         u8         dc_access_key_violation_count[0x20];
3103
3104         u8         reserved_at_1a0[0x14];
3105         u8         dei_cfi[0x1];
3106         u8         eth_prio[0x3];
3107         u8         ecn[0x2];
3108         u8         dscp[0x6];
3109
3110         u8         reserved_at_1c0[0x40];
3111 };
3112
3113 enum {
3114         MLX5_CQC_STATUS_OK             = 0x0,
3115         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3116         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3117 };
3118
3119 enum {
3120         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3121         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3122 };
3123
3124 enum {
3125         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3126         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3127         MLX5_CQC_ST_FIRED                                 = 0xa,
3128 };
3129
3130 enum {
3131         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3132         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3133         MLX5_CQ_PERIOD_NUM_MODES
3134 };
3135
3136 struct mlx5_ifc_cqc_bits {
3137         u8         status[0x4];
3138         u8         reserved_at_4[0x2];
3139         u8         dbr_umem_valid[0x1];
3140         u8         reserved_at_7[0x1];
3141         u8         cqe_sz[0x3];
3142         u8         cc[0x1];
3143         u8         reserved_at_c[0x1];
3144         u8         scqe_break_moderation_en[0x1];
3145         u8         oi[0x1];
3146         u8         cq_period_mode[0x2];
3147         u8         cqe_comp_en[0x1];
3148         u8         mini_cqe_res_format[0x2];
3149         u8         st[0x4];
3150         u8         reserved_at_18[0x8];
3151
3152         u8         reserved_at_20[0x20];
3153
3154         u8         reserved_at_40[0x14];
3155         u8         page_offset[0x6];
3156         u8         reserved_at_5a[0x6];
3157
3158         u8         reserved_at_60[0x3];
3159         u8         log_cq_size[0x5];
3160         u8         uar_page[0x18];
3161
3162         u8         reserved_at_80[0x4];
3163         u8         cq_period[0xc];
3164         u8         cq_max_count[0x10];
3165
3166         u8         reserved_at_a0[0x18];
3167         u8         c_eqn[0x8];
3168
3169         u8         reserved_at_c0[0x3];
3170         u8         log_page_size[0x5];
3171         u8         reserved_at_c8[0x18];
3172
3173         u8         reserved_at_e0[0x20];
3174
3175         u8         reserved_at_100[0x8];
3176         u8         last_notified_index[0x18];
3177
3178         u8         reserved_at_120[0x8];
3179         u8         last_solicit_index[0x18];
3180
3181         u8         reserved_at_140[0x8];
3182         u8         consumer_counter[0x18];
3183
3184         u8         reserved_at_160[0x8];
3185         u8         producer_counter[0x18];
3186
3187         u8         reserved_at_180[0x40];
3188
3189         u8         dbr_addr[0x40];
3190 };
3191
3192 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3193         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3194         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3195         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3196         u8         reserved_at_0[0x800];
3197 };
3198
3199 struct mlx5_ifc_query_adapter_param_block_bits {
3200         u8         reserved_at_0[0xc0];
3201
3202         u8         reserved_at_c0[0x8];
3203         u8         ieee_vendor_id[0x18];
3204
3205         u8         reserved_at_e0[0x10];
3206         u8         vsd_vendor_id[0x10];
3207
3208         u8         vsd[208][0x8];
3209
3210         u8         vsd_contd_psid[16][0x8];
3211 };
3212
3213 enum {
3214         MLX5_XRQC_STATE_GOOD   = 0x0,
3215         MLX5_XRQC_STATE_ERROR  = 0x1,
3216 };
3217
3218 enum {
3219         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3220         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3221 };
3222
3223 enum {
3224         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3225 };
3226
3227 struct mlx5_ifc_tag_matching_topology_context_bits {
3228         u8         log_matching_list_sz[0x4];
3229         u8         reserved_at_4[0xc];
3230         u8         append_next_index[0x10];
3231
3232         u8         sw_phase_cnt[0x10];
3233         u8         hw_phase_cnt[0x10];
3234
3235         u8         reserved_at_40[0x40];
3236 };
3237
3238 struct mlx5_ifc_xrqc_bits {
3239         u8         state[0x4];
3240         u8         rlkey[0x1];
3241         u8         reserved_at_5[0xf];
3242         u8         topology[0x4];
3243         u8         reserved_at_18[0x4];
3244         u8         offload[0x4];
3245
3246         u8         reserved_at_20[0x8];
3247         u8         user_index[0x18];
3248
3249         u8         reserved_at_40[0x8];
3250<