include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
  96         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
  97         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  98         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  99         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 100         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 101         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 102         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 103         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 104         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 105         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 106         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 107         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 108         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 109         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 110         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 111         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 112         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 113         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 114         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 115         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 116         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 117         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 118         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 119         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 120         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 121         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 122         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 123         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 124         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 125         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 126         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 127         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 128         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 129         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 130         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 131         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 132         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 133         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 134         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 135         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 136         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 137         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 138         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 139         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 140         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 141         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 142         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 143         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 145         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 146         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 147         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 148         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 149         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 150         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 151         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 152         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 153         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 154         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 155         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 156         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 157         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 158         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 159         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 160         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 161         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 162         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 163         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 164         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 165         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 166         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 167         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 168         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 169         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 170         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 171         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 172         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 173         MLX5_CMD_OP_NOP                           = 0x80d,
 174         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 175         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 178         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 179         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 180         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 181         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 182         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 183         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 184         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 185         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 186         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 187         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 188         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 189         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 190         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 191         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 192         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 193         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 194         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 195         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 196         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 197         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 198         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 199         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 200         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 201         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 202         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 203         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 204         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 205         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 206         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 207         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 208         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 209         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 210         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 211         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 212         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 213         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 214         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 215         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 216         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 217         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 218         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 219         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 220         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 222         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 223         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 224         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 225         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 226         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 227         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 228         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 229         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 230         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 231         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 232         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 233         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 234         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 235         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 236         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 237         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 238         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 239         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 240         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 241         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 242         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 243         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 244         MLX5_CMD_OP_MAX
 245 };
 246
 247 struct mlx5_ifc_flow_table_fields_supported_bits {
 248         u8         outer_dmac[0x1];
 249         u8         outer_smac[0x1];
 250         u8         outer_ether_type[0x1];
 251         u8         outer_ip_version[0x1];
 252         u8         outer_first_prio[0x1];
 253         u8         outer_first_cfi[0x1];
 254         u8         outer_first_vid[0x1];
 255         u8         outer_ipv4_ttl[0x1];
 256         u8         outer_second_prio[0x1];
 257         u8         outer_second_cfi[0x1];
 258         u8         outer_second_vid[0x1];
 259         u8         reserved_at_b[0x1];
 260         u8         outer_sip[0x1];
 261         u8         outer_dip[0x1];
 262         u8         outer_frag[0x1];
 263         u8         outer_ip_protocol[0x1];
 264         u8         outer_ip_ecn[0x1];
 265         u8         outer_ip_dscp[0x1];
 266         u8         outer_udp_sport[0x1];
 267         u8         outer_udp_dport[0x1];
 268         u8         outer_tcp_sport[0x1];
 269         u8         outer_tcp_dport[0x1];
 270         u8         outer_tcp_flags[0x1];
 271         u8         outer_gre_protocol[0x1];
 272         u8         outer_gre_key[0x1];
 273         u8         outer_vxlan_vni[0x1];
 274         u8         reserved_at_1a[0x5];
 275         u8         source_eswitch_port[0x1];
 276
 277         u8         inner_dmac[0x1];
 278         u8         inner_smac[0x1];
 279         u8         inner_ether_type[0x1];
 280         u8         inner_ip_version[0x1];
 281         u8         inner_first_prio[0x1];
 282         u8         inner_first_cfi[0x1];
 283         u8         inner_first_vid[0x1];
 284         u8         reserved_at_27[0x1];
 285         u8         inner_second_prio[0x1];
 286         u8         inner_second_cfi[0x1];
 287         u8         inner_second_vid[0x1];
 288         u8         reserved_at_2b[0x1];
 289         u8         inner_sip[0x1];
 290         u8         inner_dip[0x1];
 291         u8         inner_frag[0x1];
 292         u8         inner_ip_protocol[0x1];
 293         u8         inner_ip_ecn[0x1];
 294         u8         inner_ip_dscp[0x1];
 295         u8         inner_udp_sport[0x1];
 296         u8         inner_udp_dport[0x1];
 297         u8         inner_tcp_sport[0x1];
 298         u8         inner_tcp_dport[0x1];
 299         u8         inner_tcp_flags[0x1];
 300         u8         reserved_at_37[0x9];
 301         u8         reserved_at_40[0x17];
 302         u8         outer_esp_spi[0x1];
 303         u8         reserved_at_58[0x2];
 304         u8         bth_dst_qp[0x1];
 305
 306         u8         reserved_at_5b[0x25];
 307 };
 308
 309 struct mlx5_ifc_flow_table_prop_layout_bits {
 310         u8         ft_support[0x1];
 311         u8         reserved_at_1[0x1];
 312         u8         flow_counter[0x1];
 313         u8         flow_modify_en[0x1];
 314         u8         modify_root[0x1];
 315         u8         identified_miss_table_mode[0x1];
 316         u8         flow_table_modify[0x1];
 317         u8         encap[0x1];
 318         u8         decap[0x1];
 319         u8         reserved_at_9[0x1];
 320         u8         pop_vlan[0x1];
 321         u8         push_vlan[0x1];
 322         u8         reserved_at_c[0x14];
 323
 324         u8         reserved_at_20[0x2];
 325         u8         log_max_ft_size[0x6];
 326         u8         log_max_modify_header_context[0x8];
 327         u8         max_modify_header_actions[0x8];
 328         u8         max_ft_level[0x8];
 329
 330         u8         reserved_at_40[0x20];
 331
 332         u8         reserved_at_60[0x18];
 333         u8         log_max_ft_num[0x8];
 334
 335         u8         reserved_at_80[0x18];
 336         u8         log_max_destination[0x8];
 337
 338         u8         log_max_flow_counter[0x8];
 339         u8         reserved_at_a8[0x10];
 340         u8         log_max_flow[0x8];
 341
 342         u8         reserved_at_c0[0x40];
 343
 344         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 345
 346         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 347 };
 348
 349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 350         u8         send[0x1];
 351         u8         receive[0x1];
 352         u8         write[0x1];
 353         u8         read[0x1];
 354         u8         atomic[0x1];
 355         u8         srq_receive[0x1];
 356         u8         reserved_at_6[0x1a];
 357 };
 358
 359 struct mlx5_ifc_ipv4_layout_bits {
 360         u8         reserved_at_0[0x60];
 361
 362         u8         ipv4[0x20];
 363 };
 364
 365 struct mlx5_ifc_ipv6_layout_bits {
 366         u8         ipv6[16][0x8];
 367 };
 368
 369 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 370         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 371         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 372         u8         reserved_at_0[0x80];
 373 };
 374
 375 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 376         u8         smac_47_16[0x20];
 377
 378         u8         smac_15_0[0x10];
 379         u8         ethertype[0x10];
 380
 381         u8         dmac_47_16[0x20];
 382
 383         u8         dmac_15_0[0x10];
 384         u8         first_prio[0x3];
 385         u8         first_cfi[0x1];
 386         u8         first_vid[0xc];
 387
 388         u8         ip_protocol[0x8];
 389         u8         ip_dscp[0x6];
 390         u8         ip_ecn[0x2];
 391         u8         cvlan_tag[0x1];
 392         u8         svlan_tag[0x1];
 393         u8         frag[0x1];
 394         u8         ip_version[0x4];
 395         u8         tcp_flags[0x9];
 396
 397         u8         tcp_sport[0x10];
 398         u8         tcp_dport[0x10];
 399
 400         u8         reserved_at_c0[0x18];
 401         u8         ttl_hoplimit[0x8];
 402
 403         u8         udp_sport[0x10];
 404         u8         udp_dport[0x10];
 405
 406         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 407
 408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 409 };
 410
 411 struct mlx5_ifc_fte_match_set_misc_bits {
 412         u8         reserved_at_0[0x8];
 413         u8         source_sqn[0x18];
 414
 415         u8         source_eswitch_owner_vhca_id[0x10];
 416         u8         source_port[0x10];
 417
 418         u8         outer_second_prio[0x3];
 419         u8         outer_second_cfi[0x1];
 420         u8         outer_second_vid[0xc];
 421         u8         inner_second_prio[0x3];
 422         u8         inner_second_cfi[0x1];
 423         u8         inner_second_vid[0xc];
 424
 425         u8         outer_second_cvlan_tag[0x1];
 426         u8         inner_second_cvlan_tag[0x1];
 427         u8         outer_second_svlan_tag[0x1];
 428         u8         inner_second_svlan_tag[0x1];
 429         u8         reserved_at_64[0xc];
 430         u8         gre_protocol[0x10];
 431
 432         u8         gre_key_h[0x18];
 433         u8         gre_key_l[0x8];
 434
 435         u8         vxlan_vni[0x18];
 436         u8         reserved_at_b8[0x8];
 437
 438         u8         reserved_at_c0[0x20];
 439
 440         u8         reserved_at_e0[0xc];
 441         u8         outer_ipv6_flow_label[0x14];
 442
 443         u8         reserved_at_100[0xc];
 444         u8         inner_ipv6_flow_label[0x14];
 445
 446         u8         reserved_at_120[0x28];
 447         u8         bth_dst_qp[0x18];
 448         u8         reserved_at_160[0x20];
 449         u8         outer_esp_spi[0x20];
 450         u8         reserved_at_1a0[0x60];
 451 };
 452
 453 struct mlx5_ifc_cmd_pas_bits {
 454         u8         pa_h[0x20];
 455
 456         u8         pa_l[0x14];
 457         u8         reserved_at_34[0xc];
 458 };
 459
 460 struct mlx5_ifc_uint64_bits {
 461         u8         hi[0x20];
 462
 463         u8         lo[0x20];
 464 };
 465
 466 enum {
 467         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 468         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 469         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 470         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 471         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 472         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 473         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 474         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 475         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 476         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 477 };
 478
 479 struct mlx5_ifc_ads_bits {
 480         u8         fl[0x1];
 481         u8         free_ar[0x1];
 482         u8         reserved_at_2[0xe];
 483         u8         pkey_index[0x10];
 484
 485         u8         reserved_at_20[0x8];
 486         u8         grh[0x1];
 487         u8         mlid[0x7];
 488         u8         rlid[0x10];
 489
 490         u8         ack_timeout[0x5];
 491         u8         reserved_at_45[0x3];
 492         u8         src_addr_index[0x8];
 493         u8         reserved_at_50[0x4];
 494         u8         stat_rate[0x4];
 495         u8         hop_limit[0x8];
 496
 497         u8         reserved_at_60[0x4];
 498         u8         tclass[0x8];
 499         u8         flow_label[0x14];
 500
 501         u8         rgid_rip[16][0x8];
 502
 503         u8         reserved_at_100[0x4];
 504         u8         f_dscp[0x1];
 505         u8         f_ecn[0x1];
 506         u8         reserved_at_106[0x1];
 507         u8         f_eth_prio[0x1];
 508         u8         ecn[0x2];
 509         u8         dscp[0x6];
 510         u8         udp_sport[0x10];
 511
 512         u8         dei_cfi[0x1];
 513         u8         eth_prio[0x3];
 514         u8         sl[0x4];
 515         u8         vhca_port_num[0x8];
 516         u8         rmac_47_32[0x10];
 517
 518         u8         rmac_31_0[0x20];
 519 };
 520
 521 struct mlx5_ifc_flow_table_nic_cap_bits {
 522         u8         nic_rx_multi_path_tirs[0x1];
 523         u8         nic_rx_multi_path_tirs_fts[0x1];
 524         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 525         u8         reserved_at_3[0x1fd];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 528
 529         u8         reserved_at_400[0x200];
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 532
 533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 534
 535         u8         reserved_at_a00[0x200];
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 538
 539         u8         reserved_at_e00[0x7200];
 540 };
 541
 542 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 543         u8     reserved_at_0[0x200];
 544
 545         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 546
 547         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 548
 549         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 550
 551         u8      reserved_at_800[0x7800];
 552 };
 553
 554 struct mlx5_ifc_e_switch_cap_bits {
 555         u8         vport_svlan_strip[0x1];
 556         u8         vport_cvlan_strip[0x1];
 557         u8         vport_svlan_insert[0x1];
 558         u8         vport_cvlan_insert_if_not_exist[0x1];
 559         u8         vport_cvlan_insert_overwrite[0x1];
 560         u8         reserved_at_5[0x18];
 561         u8         merged_eswitch[0x1];
 562         u8         nic_vport_node_guid_modify[0x1];
 563         u8         nic_vport_port_guid_modify[0x1];
 564
 565         u8         vxlan_encap_decap[0x1];
 566         u8         nvgre_encap_decap[0x1];
 567         u8         reserved_at_22[0x9];
 568         u8         log_max_encap_headers[0x5];
 569         u8         reserved_2b[0x6];
 570         u8         max_encap_header_size[0xa];
 571
 572         u8         reserved_40[0x7c0];
 573
 574 };
 575
 576 struct mlx5_ifc_qos_cap_bits {
 577         u8         packet_pacing[0x1];
 578         u8         esw_scheduling[0x1];
 579         u8         esw_bw_share[0x1];
 580         u8         esw_rate_limit[0x1];
 581         u8         reserved_at_4[0x1];
 582         u8         packet_pacing_burst_bound[0x1];
 583         u8         packet_pacing_typical_size[0x1];
 584         u8         reserved_at_7[0x19];
 585
 586         u8         reserved_at_20[0x20];
 587
 588         u8         packet_pacing_max_rate[0x20];
 589
 590         u8         packet_pacing_min_rate[0x20];
 591
 592         u8         reserved_at_80[0x10];
 593         u8         packet_pacing_rate_table_size[0x10];
 594
 595         u8         esw_element_type[0x10];
 596         u8         esw_tsar_type[0x10];
 597
 598         u8         reserved_at_c0[0x10];
 599         u8         max_qos_para_vport[0x10];
 600
 601         u8         max_tsar_bw_share[0x20];
 602
 603         u8         reserved_at_100[0x700];
 604 };
 605
 606 struct mlx5_ifc_debug_cap_bits {
 607         u8         reserved_at_0[0x20];
 608
 609         u8         reserved_at_20[0x2];
 610         u8         stall_detect[0x1];
 611         u8         reserved_at_23[0x1d];
 612
 613         u8         reserved_at_40[0x7c0];
 614 };
 615
 616 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 617         u8         csum_cap[0x1];
 618         u8         vlan_cap[0x1];
 619         u8         lro_cap[0x1];
 620         u8         lro_psh_flag[0x1];
 621         u8         lro_time_stamp[0x1];
 622         u8         reserved_at_5[0x2];
 623         u8         wqe_vlan_insert[0x1];
 624         u8         self_lb_en_modifiable[0x1];
 625         u8         reserved_at_9[0x2];
 626         u8         max_lso_cap[0x5];
 627         u8         multi_pkt_send_wqe[0x2];
 628         u8         wqe_inline_mode[0x2];
 629         u8         rss_ind_tbl_cap[0x4];
 630         u8         reg_umr_sq[0x1];
 631         u8         scatter_fcs[0x1];
 632         u8         enhanced_multi_pkt_send_wqe[0x1];
 633         u8         tunnel_lso_const_out_ip_id[0x1];
 634         u8         reserved_at_1c[0x2];
 635         u8         tunnel_stateless_gre[0x1];
 636         u8         tunnel_stateless_vxlan[0x1];
 637
 638         u8         swp[0x1];
 639         u8         swp_csum[0x1];
 640         u8         swp_lso[0x1];
 641         u8         reserved_at_23[0x1b];
 642         u8         max_geneve_opt_len[0x1];
 643         u8         tunnel_stateless_geneve_rx[0x1];
 644
 645         u8         reserved_at_40[0x10];
 646         u8         lro_min_mss_size[0x10];
 647
 648         u8         reserved_at_60[0x120];
 649
 650         u8         lro_timer_supported_periods[4][0x20];
 651
 652         u8         reserved_at_200[0x600];
 653 };
 654
 655 struct mlx5_ifc_roce_cap_bits {
 656         u8         roce_apm[0x1];
 657         u8         reserved_at_1[0x1f];
 658
 659         u8         reserved_at_20[0x60];
 660
 661         u8         reserved_at_80[0xc];
 662         u8         l3_type[0x4];
 663         u8         reserved_at_90[0x8];
 664         u8         roce_version[0x8];
 665
 666         u8         reserved_at_a0[0x10];
 667         u8         r_roce_dest_udp_port[0x10];
 668
 669         u8         r_roce_max_src_udp_port[0x10];
 670         u8         r_roce_min_src_udp_port[0x10];
 671
 672         u8         reserved_at_e0[0x10];
 673         u8         roce_address_table_size[0x10];
 674
 675         u8         reserved_at_100[0x700];
 676 };
 677
 678 struct mlx5_ifc_device_mem_cap_bits {
 679         u8         memic[0x1];
 680         u8         reserved_at_1[0x1f];
 681
 682         u8         reserved_at_20[0xb];
 683         u8         log_min_memic_alloc_size[0x5];
 684         u8         reserved_at_30[0x8];
 685         u8         log_max_memic_addr_alignment[0x8];
 686
 687         u8         memic_bar_start_addr[0x40];
 688
 689         u8         memic_bar_size[0x20];
 690
 691         u8         max_memic_size[0x20];
 692
 693         u8         reserved_at_c0[0x740];
 694 };
 695
 696 enum {
 697         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 698         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 699         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 700         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 701         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 702         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 703         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 704         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 705         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 706 };
 707
 708 enum {
 709         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 710         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 711         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 712         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 713         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 714         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 715         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 716         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 717         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 718 };
 719
 720 struct mlx5_ifc_atomic_caps_bits {
 721         u8         reserved_at_0[0x40];
 722
 723         u8         atomic_req_8B_endianness_mode[0x2];
 724         u8         reserved_at_42[0x4];
 725         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 726
 727         u8         reserved_at_47[0x19];
 728
 729         u8         reserved_at_60[0x20];
 730
 731         u8         reserved_at_80[0x10];
 732         u8         atomic_operations[0x10];
 733
 734         u8         reserved_at_a0[0x10];
 735         u8         atomic_size_qp[0x10];
 736
 737         u8         reserved_at_c0[0x10];
 738         u8         atomic_size_dc[0x10];
 739
 740         u8         reserved_at_e0[0x720];
 741 };
 742
 743 struct mlx5_ifc_odp_cap_bits {
 744         u8         reserved_at_0[0x40];
 745
 746         u8         sig[0x1];
 747         u8         reserved_at_41[0x1f];
 748
 749         u8         reserved_at_60[0x20];
 750
 751         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 752
 753         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 754
 755         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 756
 757         u8         reserved_at_e0[0x720];
 758 };
 759
 760 struct mlx5_ifc_calc_op {
 761         u8        reserved_at_0[0x10];
 762         u8        reserved_at_10[0x9];
 763         u8        op_swap_endianness[0x1];
 764         u8        op_min[0x1];
 765         u8        op_xor[0x1];
 766         u8        op_or[0x1];
 767         u8        op_and[0x1];
 768         u8        op_max[0x1];
 769         u8        op_add[0x1];
 770 };
 771
 772 struct mlx5_ifc_vector_calc_cap_bits {
 773         u8         calc_matrix[0x1];
 774         u8         reserved_at_1[0x1f];
 775         u8         reserved_at_20[0x8];
 776         u8         max_vec_count[0x8];
 777         u8         reserved_at_30[0xd];
 778         u8         max_chunk_size[0x3];
 779         struct mlx5_ifc_calc_op calc0;
 780         struct mlx5_ifc_calc_op calc1;
 781         struct mlx5_ifc_calc_op calc2;
 782         struct mlx5_ifc_calc_op calc3;
 783
 784         u8         reserved_at_e0[0x720];
 785 };
 786
 787 enum {
 788         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 789         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 790         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 791         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 792 };
 793
 794 enum {
 795         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 796         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 797 };
 798
 799 enum {
 800         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 801         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 802         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 803         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 804         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 805 };
 806
 807 enum {
 808         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 809         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 810         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 811         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 812         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 813         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 814 };
 815
 816 enum {
 817         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 818         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 819 };
 820
 821 enum {
 822         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 823         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 824         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 825 };
 826
 827 enum {
 828         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 829         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 830 };
 831
 832 enum {
 833         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 834         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 835         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 836 };
 837
 838 struct mlx5_ifc_cmd_hca_cap_bits {
 839         u8         reserved_at_0[0x30];
 840         u8         vhca_id[0x10];
 841
 842         u8         reserved_at_40[0x40];
 843
 844         u8         log_max_srq_sz[0x8];
 845         u8         log_max_qp_sz[0x8];
 846         u8         reserved_at_90[0xb];
 847         u8         log_max_qp[0x5];
 848
 849         u8         reserved_at_a0[0xb];
 850         u8         log_max_srq[0x5];
 851         u8         reserved_at_b0[0x10];
 852
 853         u8         reserved_at_c0[0x8];
 854         u8         log_max_cq_sz[0x8];
 855         u8         reserved_at_d0[0xb];
 856         u8         log_max_cq[0x5];
 857
 858         u8         log_max_eq_sz[0x8];
 859         u8         reserved_at_e8[0x2];
 860         u8         log_max_mkey[0x6];
 861         u8         reserved_at_f0[0xc];
 862         u8         log_max_eq[0x4];
 863
 864         u8         max_indirection[0x8];
 865         u8         fixed_buffer_size[0x1];
 866         u8         log_max_mrw_sz[0x7];
 867         u8         force_teardown[0x1];
 868         u8         reserved_at_111[0x1];
 869         u8         log_max_bsf_list_size[0x6];
 870         u8         umr_extended_translation_offset[0x1];
 871         u8         null_mkey[0x1];
 872         u8         log_max_klm_list_size[0x6];
 873
 874         u8         reserved_at_120[0xa];
 875         u8         log_max_ra_req_dc[0x6];
 876         u8         reserved_at_130[0xa];
 877         u8         log_max_ra_res_dc[0x6];
 878
 879         u8         reserved_at_140[0xa];
 880         u8         log_max_ra_req_qp[0x6];
 881         u8         reserved_at_150[0xa];
 882         u8         log_max_ra_res_qp[0x6];
 883
 884         u8         end_pad[0x1];
 885         u8         cc_query_allowed[0x1];
 886         u8         cc_modify_allowed[0x1];
 887         u8         start_pad[0x1];
 888         u8         cache_line_128byte[0x1];
 889         u8         reserved_at_165[0xa];
 890         u8         qcam_reg[0x1];
 891         u8         gid_table_size[0x10];
 892
 893         u8         out_of_seq_cnt[0x1];
 894         u8         vport_counters[0x1];
 895         u8         retransmission_q_counters[0x1];
 896         u8         debug[0x1];
 897         u8         modify_rq_counter_set_id[0x1];
 898         u8         rq_delay_drop[0x1];
 899         u8         max_qp_cnt[0xa];
 900         u8         pkey_table_size[0x10];
 901
 902         u8         vport_group_manager[0x1];
 903         u8         vhca_group_manager[0x1];
 904         u8         ib_virt[0x1];
 905         u8         eth_virt[0x1];
 906         u8         vnic_env_queue_counters[0x1];
 907         u8         ets[0x1];
 908         u8         nic_flow_table[0x1];
 909         u8         eswitch_flow_table[0x1];
 910         u8         device_memory[0x1];
 911         u8         mcam_reg[0x1];
 912         u8         pcam_reg[0x1];
 913         u8         local_ca_ack_delay[0x5];
 914         u8         port_module_event[0x1];
 915         u8         enhanced_error_q_counters[0x1];
 916         u8         ports_check[0x1];
 917         u8         reserved_at_1b3[0x1];
 918         u8         disable_link_up[0x1];
 919         u8         beacon_led[0x1];
 920         u8         port_type[0x2];
 921         u8         num_ports[0x8];
 922
 923         u8         reserved_at_1c0[0x1];
 924         u8         pps[0x1];
 925         u8         pps_modify[0x1];
 926         u8         log_max_msg[0x5];
 927         u8         reserved_at_1c8[0x4];
 928         u8         max_tc[0x4];
 929         u8         reserved_at_1d0[0x1];
 930         u8         dcbx[0x1];
 931         u8         general_notification_event[0x1];
 932         u8         reserved_at_1d3[0x2];
 933         u8         fpga[0x1];
 934         u8         rol_s[0x1];
 935         u8         rol_g[0x1];
 936         u8         reserved_at_1d8[0x1];
 937         u8         wol_s[0x1];
 938         u8         wol_g[0x1];
 939         u8         wol_a[0x1];
 940         u8         wol_b[0x1];
 941         u8         wol_m[0x1];
 942         u8         wol_u[0x1];
 943         u8         wol_p[0x1];
 944
 945         u8         stat_rate_support[0x10];
 946         u8         reserved_at_1f0[0xc];
 947         u8         cqe_version[0x4];
 948
 949         u8         compact_address_vector[0x1];
 950         u8         striding_rq[0x1];
 951         u8         reserved_at_202[0x1];
 952         u8         ipoib_enhanced_offloads[0x1];
 953         u8         ipoib_basic_offloads[0x1];
 954         u8         reserved_at_205[0x1];
 955         u8         repeated_block_disabled[0x1];
 956         u8         umr_modify_entity_size_disabled[0x1];
 957         u8         umr_modify_atomic_disabled[0x1];
 958         u8         umr_indirect_mkey_disabled[0x1];
 959         u8         umr_fence[0x2];
 960         u8         reserved_at_20c[0x3];
 961         u8         drain_sigerr[0x1];
 962         u8         cmdif_checksum[0x2];
 963         u8         sigerr_cqe[0x1];
 964         u8         reserved_at_213[0x1];
 965         u8         wq_signature[0x1];
 966         u8         sctr_data_cqe[0x1];
 967         u8         reserved_at_216[0x1];
 968         u8         sho[0x1];
 969         u8         tph[0x1];
 970         u8         rf[0x1];
 971         u8         dct[0x1];
 972         u8         qos[0x1];
 973         u8         eth_net_offloads[0x1];
 974         u8         roce[0x1];
 975         u8         atomic[0x1];
 976         u8         reserved_at_21f[0x1];
 977
 978         u8         cq_oi[0x1];
 979         u8         cq_resize[0x1];
 980         u8         cq_moderation[0x1];
 981         u8         reserved_at_223[0x3];
 982         u8         cq_eq_remap[0x1];
 983         u8         pg[0x1];
 984         u8         block_lb_mc[0x1];
 985         u8         reserved_at_229[0x1];
 986         u8         scqe_break_moderation[0x1];
 987         u8         cq_period_start_from_cqe[0x1];
 988         u8         cd[0x1];
 989         u8         reserved_at_22d[0x1];
 990         u8         apm[0x1];
 991         u8         vector_calc[0x1];
 992         u8         umr_ptr_rlky[0x1];
 993         u8         imaicl[0x1];
 994         u8         reserved_at_232[0x4];
 995         u8         qkv[0x1];
 996         u8         pkv[0x1];
 997         u8         set_deth_sqpn[0x1];
 998         u8         reserved_at_239[0x3];
 999         u8         xrc[0x1];
1000         u8         ud[0x1];
1001         u8         uc[0x1];
1002         u8         rc[0x1];
1003
1004         u8         uar_4k[0x1];
1005         u8         reserved_at_241[0x9];
1006         u8         uar_sz[0x6];
1007         u8         reserved_at_250[0x8];
1008         u8         log_pg_sz[0x8];
1009
1010         u8         bf[0x1];
1011         u8         driver_version[0x1];
1012         u8         pad_tx_eth_packet[0x1];
1013         u8         reserved_at_263[0x8];
1014         u8         log_bf_reg_size[0x5];
1015
1016         u8         reserved_at_270[0xb];
1017         u8         lag_master[0x1];
1018         u8         num_lag_ports[0x4];
1019
1020         u8         reserved_at_280[0x10];
1021         u8         max_wqe_sz_sq[0x10];
1022
1023         u8         reserved_at_2a0[0x10];
1024         u8         max_wqe_sz_rq[0x10];
1025
1026         u8         max_flow_counter_31_16[0x10];
1027         u8         max_wqe_sz_sq_dc[0x10];
1028
1029         u8         reserved_at_2e0[0x7];
1030         u8         max_qp_mcg[0x19];
1031
1032         u8         reserved_at_300[0x18];
1033         u8         log_max_mcg[0x8];
1034
1035         u8         reserved_at_320[0x3];
1036         u8         log_max_transport_domain[0x5];
1037         u8         reserved_at_328[0x3];
1038         u8         log_max_pd[0x5];
1039         u8         reserved_at_330[0xb];
1040         u8         log_max_xrcd[0x5];
1041
1042         u8         nic_receive_steering_discard[0x1];
1043         u8         receive_discard_vport_down[0x1];
1044         u8         transmit_discard_vport_down[0x1];
1045         u8         reserved_at_343[0x5];
1046         u8         log_max_flow_counter_bulk[0x8];
1047         u8         max_flow_counter_15_0[0x10];
1048
1049
1050         u8         reserved_at_360[0x3];
1051         u8         log_max_rq[0x5];
1052         u8         reserved_at_368[0x3];
1053         u8         log_max_sq[0x5];
1054         u8         reserved_at_370[0x3];
1055         u8         log_max_tir[0x5];
1056         u8         reserved_at_378[0x3];
1057         u8         log_max_tis[0x5];
1058
1059         u8         basic_cyclic_rcv_wqe[0x1];
1060         u8         reserved_at_381[0x2];
1061         u8         log_max_rmp[0x5];
1062         u8         reserved_at_388[0x3];
1063         u8         log_max_rqt[0x5];
1064         u8         reserved_at_390[0x3];
1065         u8         log_max_rqt_size[0x5];
1066         u8         reserved_at_398[0x3];
1067         u8         log_max_tis_per_sq[0x5];
1068
1069         u8         ext_stride_num_range[0x1];
1070         u8         reserved_at_3a1[0x2];
1071         u8         log_max_stride_sz_rq[0x5];
1072         u8         reserved_at_3a8[0x3];
1073         u8         log_min_stride_sz_rq[0x5];
1074         u8         reserved_at_3b0[0x3];
1075         u8         log_max_stride_sz_sq[0x5];
1076         u8         reserved_at_3b8[0x3];
1077         u8         log_min_stride_sz_sq[0x5];
1078
1079         u8         hairpin[0x1];
1080         u8         reserved_at_3c1[0x2];
1081         u8         log_max_hairpin_queues[0x5];
1082         u8         reserved_at_3c8[0x3];
1083         u8         log_max_hairpin_wq_data_sz[0x5];
1084         u8         reserved_at_3d0[0x3];
1085         u8         log_max_hairpin_num_packets[0x5];
1086         u8         reserved_at_3d8[0x3];
1087         u8         log_max_wq_sz[0x5];
1088
1089         u8         nic_vport_change_event[0x1];
1090         u8         disable_local_lb_uc[0x1];
1091         u8         disable_local_lb_mc[0x1];
1092         u8         log_min_hairpin_wq_data_sz[0x5];
1093         u8         reserved_at_3e8[0x3];
1094         u8         log_max_vlan_list[0x5];
1095         u8         reserved_at_3f0[0x3];
1096         u8         log_max_current_mc_list[0x5];
1097         u8         reserved_at_3f8[0x3];
1098         u8         log_max_current_uc_list[0x5];
1099
1100         u8         reserved_at_400[0x80];
1101
1102         u8         reserved_at_480[0x3];
1103         u8         log_max_l2_table[0x5];
1104         u8         reserved_at_488[0x8];
1105         u8         log_uar_page_sz[0x10];
1106
1107         u8         reserved_at_4a0[0x20];
1108         u8         device_frequency_mhz[0x20];
1109         u8         device_frequency_khz[0x20];
1110
1111         u8         reserved_at_500[0x20];
1112         u8         num_of_uars_per_page[0x20];
1113         u8         reserved_at_540[0x40];
1114
1115         u8         reserved_at_580[0x3c];
1116         u8         mini_cqe_resp_stride_index[0x1];
1117         u8         cqe_128_always[0x1];
1118         u8         cqe_compression_128[0x1];
1119         u8         cqe_compression[0x1];
1120
1121         u8         cqe_compression_timeout[0x10];
1122         u8         cqe_compression_max_num[0x10];
1123
1124         u8         reserved_at_5e0[0x10];
1125         u8         tag_matching[0x1];
1126         u8         rndv_offload_rc[0x1];
1127         u8         rndv_offload_dc[0x1];
1128         u8         log_tag_matching_list_sz[0x5];
1129         u8         reserved_at_5f8[0x3];
1130         u8         log_max_xrq[0x5];
1131
1132         u8         affiliate_nic_vport_criteria[0x8];
1133         u8         native_port_num[0x8];
1134         u8         num_vhca_ports[0x8];
1135         u8         reserved_at_618[0x6];
1136         u8         sw_owner_id[0x1];
1137         u8         reserved_at_61f[0x1e1];
1138 };
1139
1140 enum mlx5_flow_destination_type {
1141         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1142         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1143         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1144
1145         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1146         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1147 };
1148
1149 struct mlx5_ifc_dest_format_struct_bits {
1150         u8         destination_type[0x8];
1151         u8         destination_id[0x18];
1152         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1153         u8         reserved_at_21[0xf];
1154         u8         destination_eswitch_owner_vhca_id[0x10];
1155 };
1156
1157 struct mlx5_ifc_flow_counter_list_bits {
1158         u8         flow_counter_id[0x20];
1159
1160         u8         reserved_at_20[0x20];
1161 };
1162
1163 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1164         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1165         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1166         u8         reserved_at_0[0x40];
1167 };
1168
1169 struct mlx5_ifc_fte_match_param_bits {
1170         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1171
1172         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1173
1174         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1175
1176         u8         reserved_at_600[0xa00];
1177 };
1178
1179 enum {
1180         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1181         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1182         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1183         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1184         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1185 };
1186
1187 struct mlx5_ifc_rx_hash_field_select_bits {
1188         u8         l3_prot_type[0x1];
1189         u8         l4_prot_type[0x1];
1190         u8         selected_fields[0x1e];
1191 };
1192
1193 enum {
1194         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1195         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1196 };
1197
1198 enum {
1199         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1200         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1201 };
1202
1203 struct mlx5_ifc_wq_bits {
1204         u8         wq_type[0x4];
1205         u8         wq_signature[0x1];
1206         u8         end_padding_mode[0x2];
1207         u8         cd_slave[0x1];
1208         u8         reserved_at_8[0x18];
1209
1210         u8         hds_skip_first_sge[0x1];
1211         u8         log2_hds_buf_size[0x3];
1212         u8         reserved_at_24[0x7];
1213         u8         page_offset[0x5];
1214         u8         lwm[0x10];
1215
1216         u8         reserved_at_40[0x8];
1217         u8         pd[0x18];
1218
1219         u8         reserved_at_60[0x8];
1220         u8         uar_page[0x18];
1221
1222         u8         dbr_addr[0x40];
1223
1224         u8         hw_counter[0x20];
1225
1226         u8         sw_counter[0x20];
1227
1228         u8         reserved_at_100[0xc];
1229         u8         log_wq_stride[0x4];
1230         u8         reserved_at_110[0x3];
1231         u8         log_wq_pg_sz[0x5];
1232         u8         reserved_at_118[0x3];
1233         u8         log_wq_sz[0x5];
1234
1235         u8         reserved_at_120[0x3];
1236         u8         log_hairpin_num_packets[0x5];
1237         u8         reserved_at_128[0x3];
1238         u8         log_hairpin_data_sz[0x5];
1239
1240         u8         reserved_at_130[0x4];
1241         u8         log_wqe_num_of_strides[0x4];
1242         u8         two_byte_shift_en[0x1];
1243         u8         reserved_at_139[0x4];
1244         u8         log_wqe_stride_size[0x3];
1245
1246         u8         reserved_at_140[0x4c0];
1247
1248         struct mlx5_ifc_cmd_pas_bits pas[0];
1249 };
1250
1251 struct mlx5_ifc_rq_num_bits {
1252         u8         reserved_at_0[0x8];
1253         u8         rq_num[0x18];
1254 };
1255
1256 struct mlx5_ifc_mac_address_layout_bits {
1257         u8         reserved_at_0[0x10];
1258         u8         mac_addr_47_32[0x10];
1259
1260         u8         mac_addr_31_0[0x20];
1261 };
1262
1263 struct mlx5_ifc_vlan_layout_bits {
1264         u8         reserved_at_0[0x14];
1265         u8         vlan[0x0c];
1266
1267         u8         reserved_at_20[0x20];
1268 };
1269
1270 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1271         u8         reserved_at_0[0xa0];
1272
1273         u8         min_time_between_cnps[0x20];
1274
1275         u8         reserved_at_c0[0x12];
1276         u8         cnp_dscp[0x6];
1277         u8         reserved_at_d8[0x4];
1278         u8         cnp_prio_mode[0x1];
1279         u8         cnp_802p_prio[0x3];
1280
1281         u8         reserved_at_e0[0x720];
1282 };
1283
1284 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1285         u8         reserved_at_0[0x60];
1286
1287         u8         reserved_at_60[0x4];
1288         u8         clamp_tgt_rate[0x1];
1289         u8         reserved_at_65[0x3];
1290         u8         clamp_tgt_rate_after_time_inc[0x1];
1291         u8         reserved_at_69[0x17];
1292
1293         u8         reserved_at_80[0x20];
1294
1295         u8         rpg_time_reset[0x20];
1296
1297         u8         rpg_byte_reset[0x20];
1298
1299         u8         rpg_threshold[0x20];
1300
1301         u8         rpg_max_rate[0x20];
1302
1303         u8         rpg_ai_rate[0x20];
1304
1305         u8         rpg_hai_rate[0x20];
1306
1307         u8         rpg_gd[0x20];
1308
1309         u8         rpg_min_dec_fac[0x20];
1310
1311         u8         rpg_min_rate[0x20];
1312
1313         u8         reserved_at_1c0[0xe0];
1314
1315         u8         rate_to_set_on_first_cnp[0x20];
1316
1317         u8         dce_tcp_g[0x20];
1318
1319         u8         dce_tcp_rtt[0x20];
1320
1321         u8         rate_reduce_monitor_period[0x20];
1322
1323         u8         reserved_at_320[0x20];
1324
1325         u8         initial_alpha_value[0x20];
1326
1327         u8         reserved_at_360[0x4a0];
1328 };
1329
1330 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1331         u8         reserved_at_0[0x80];
1332
1333         u8         rppp_max_rps[0x20];
1334
1335         u8         rpg_time_reset[0x20];
1336
1337         u8         rpg_byte_reset[0x20];
1338
1339         u8         rpg_threshold[0x20];
1340
1341         u8         rpg_max_rate[0x20];
1342
1343         u8         rpg_ai_rate[0x20];
1344
1345         u8         rpg_hai_rate[0x20];
1346
1347         u8         rpg_gd[0x20];
1348
1349         u8         rpg_min_dec_fac[0x20];
1350
1351         u8         rpg_min_rate[0x20];
1352
1353         u8         reserved_at_1c0[0x640];
1354 };
1355
1356 enum {
1357         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1358         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1359         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1360 };
1361
1362 struct mlx5_ifc_resize_field_select_bits {
1363         u8         resize_field_select[0x20];
1364 };
1365
1366 enum {
1367         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1368         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1369         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1370         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1371 };
1372
1373 struct mlx5_ifc_modify_field_select_bits {
1374         u8         modify_field_select[0x20];
1375 };
1376
1377 struct mlx5_ifc_field_select_r_roce_np_bits {
1378         u8         field_select_r_roce_np[0x20];
1379 };
1380
1381 struct mlx5_ifc_field_select_r_roce_rp_bits {
1382         u8         field_select_r_roce_rp[0x20];
1383 };
1384
1385 enum {
1386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1392         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1393         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1394         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1395         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1396 };
1397
1398 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1399         u8         field_select_8021qaurp[0x20];
1400 };
1401
1402 struct mlx5_ifc_phys_layer_cntrs_bits {
1403         u8         time_since_last_clear_high[0x20];
1404
1405         u8         time_since_last_clear_low[0x20];
1406
1407         u8         symbol_errors_high[0x20];
1408
1409         u8         symbol_errors_low[0x20];
1410
1411         u8         sync_headers_errors_high[0x20];
1412
1413         u8         sync_headers_errors_low[0x20];
1414
1415         u8         edpl_bip_errors_lane0_high[0x20];
1416
1417         u8         edpl_bip_errors_lane0_low[0x20];
1418
1419         u8         edpl_bip_errors_lane1_high[0x20];
1420
1421         u8         edpl_bip_errors_lane1_low[0x20];
1422
1423         u8         edpl_bip_errors_lane2_high[0x20];
1424
1425         u8         edpl_bip_errors_lane2_low[0x20];
1426
1427         u8         edpl_bip_errors_lane3_high[0x20];
1428
1429         u8         edpl_bip_errors_lane3_low[0x20];
1430
1431         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1432
1433         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1434
1435         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1436
1437         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1438
1439         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1440
1441         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1442
1443         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1444
1445         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1446
1447         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1448
1449         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1450
1451         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1452
1453         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1454
1455         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1456
1457         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1458
1459         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1460
1461         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1462
1463         u8         rs_fec_corrected_blocks_high[0x20];
1464
1465         u8         rs_fec_corrected_blocks_low[0x20];
1466
1467         u8         rs_fec_uncorrectable_blocks_high[0x20];
1468
1469         u8         rs_fec_uncorrectable_blocks_low[0x20];
1470
1471         u8         rs_fec_no_errors_blocks_high[0x20];
1472
1473         u8         rs_fec_no_errors_blocks_low[0x20];
1474
1475         u8         rs_fec_single_error_blocks_high[0x20];
1476
1477         u8         rs_fec_single_error_blocks_low[0x20];
1478
1479         u8         rs_fec_corrected_symbols_total_high[0x20];
1480
1481         u8         rs_fec_corrected_symbols_total_low[0x20];
1482
1483         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1484
1485         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1486
1487         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1488
1489         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1490
1491         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1492
1493         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1494
1495         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1496
1497         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1498
1499         u8         link_down_events[0x20];
1500
1501         u8         successful_recovery_events[0x20];
1502
1503         u8         reserved_at_640[0x180];
1504 };
1505
1506 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1507         u8         time_since_last_clear_high[0x20];
1508
1509         u8         time_since_last_clear_low[0x20];
1510
1511         u8         phy_received_bits_high[0x20];
1512
1513         u8         phy_received_bits_low[0x20];
1514
1515         u8         phy_symbol_errors_high[0x20];
1516
1517         u8         phy_symbol_errors_low[0x20];
1518
1519         u8         phy_corrected_bits_high[0x20];
1520
1521         u8         phy_corrected_bits_low[0x20];
1522
1523         u8         phy_corrected_bits_lane0_high[0x20];
1524
1525         u8         phy_corrected_bits_lane0_low[0x20];
1526
1527         u8         phy_corrected_bits_lane1_high[0x20];
1528
1529         u8         phy_corrected_bits_lane1_low[0x20];
1530
1531         u8         phy_corrected_bits_lane2_high[0x20];
1532
1533         u8         phy_corrected_bits_lane2_low[0x20];
1534
1535         u8         phy_corrected_bits_lane3_high[0x20];
1536
1537         u8         phy_corrected_bits_lane3_low[0x20];
1538
1539         u8         reserved_at_200[0x5c0];
1540 };
1541
1542 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1543         u8         symbol_error_counter[0x10];
1544
1545         u8         link_error_recovery_counter[0x8];
1546
1547         u8         link_downed_counter[0x8];
1548
1549         u8         port_rcv_errors[0x10];
1550
1551         u8         port_rcv_remote_physical_errors[0x10];
1552
1553         u8         port_rcv_switch_relay_errors[0x10];
1554
1555         u8         port_xmit_discards[0x10];
1556
1557         u8         port_xmit_constraint_errors[0x8];
1558
1559         u8         port_rcv_constraint_errors[0x8];
1560
1561         u8         reserved_at_70[0x8];
1562
1563         u8         link_overrun_errors[0x8];
1564
1565         u8         reserved_at_80[0x10];
1566
1567         u8         vl_15_dropped[0x10];
1568
1569         u8         reserved_at_a0[0x80];
1570
1571         u8         port_xmit_wait[0x20];
1572 };
1573
1574 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1575         u8         transmit_queue_high[0x20];
1576
1577         u8         transmit_queue_low[0x20];
1578
1579         u8         reserved_at_40[0x780];
1580 };
1581
1582 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1583         u8         rx_octets_high[0x20];
1584
1585         u8         rx_octets_low[0x20];
1586
1587         u8         reserved_at_40[0xc0];
1588
1589         u8         rx_frames_high[0x20];
1590
1591         u8         rx_frames_low[0x20];
1592
1593         u8         tx_octets_high[0x20];
1594
1595         u8         tx_octets_low[0x20];
1596
1597         u8         reserved_at_180[0xc0];
1598
1599         u8         tx_frames_high[0x20];
1600
1601         u8         tx_frames_low[0x20];
1602
1603         u8         rx_pause_high[0x20];
1604
1605         u8         rx_pause_low[0x20];
1606
1607         u8         rx_pause_duration_high[0x20];
1608
1609         u8         rx_pause_duration_low[0x20];
1610
1611         u8         tx_pause_high[0x20];
1612
1613         u8         tx_pause_low[0x20];
1614
1615         u8         tx_pause_duration_high[0x20];
1616
1617         u8         tx_pause_duration_low[0x20];
1618
1619         u8         rx_pause_transition_high[0x20];
1620
1621         u8         rx_pause_transition_low[0x20];
1622
1623         u8         reserved_at_3c0[0x40];
1624
1625         u8         device_stall_minor_watermark_cnt_high[0x20];
1626
1627         u8         device_stall_minor_watermark_cnt_low[0x20];
1628
1629         u8         device_stall_critical_watermark_cnt_high[0x20];
1630
1631         u8         device_stall_critical_watermark_cnt_low[0x20];
1632
1633         u8         reserved_at_480[0x340];
1634 };
1635
1636 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1637         u8         port_transmit_wait_high[0x20];
1638
1639         u8         port_transmit_wait_low[0x20];
1640
1641         u8         reserved_at_40[0x100];
1642
1643         u8         rx_buffer_almost_full_high[0x20];
1644
1645         u8         rx_buffer_almost_full_low[0x20];
1646
1647         u8         rx_buffer_full_high[0x20];
1648
1649         u8         rx_buffer_full_low[0x20];
1650
1651         u8         reserved_at_1c0[0x600];
1652 };
1653
1654 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1655         u8         dot3stats_alignment_errors_high[0x20];
1656
1657         u8         dot3stats_alignment_errors_low[0x20];
1658
1659         u8         dot3stats_fcs_errors_high[0x20];
1660
1661         u8         dot3stats_fcs_errors_low[0x20];
1662
1663         u8         dot3stats_single_collision_frames_high[0x20];
1664
1665         u8         dot3stats_single_collision_frames_low[0x20];
1666
1667         u8         dot3stats_multiple_collision_frames_high[0x20];
1668
1669         u8         dot3stats_multiple_collision_frames_low[0x20];
1670
1671         u8         dot3stats_sqe_test_errors_high[0x20];
1672
1673         u8         dot3stats_sqe_test_errors_low[0x20];
1674
1675         u8         dot3stats_deferred_transmissions_high[0x20];
1676
1677         u8         dot3stats_deferred_transmissions_low[0x20];
1678
1679         u8         dot3stats_late_collisions_high[0x20];
1680
1681         u8         dot3stats_late_collisions_low[0x20];
1682
1683         u8         dot3stats_excessive_collisions_high[0x20];
1684
1685         u8         dot3stats_excessive_collisions_low[0x20];
1686
1687         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1688
1689         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1690
1691         u8         dot3stats_carrier_sense_errors_high[0x20];
1692
1693         u8         dot3stats_carrier_sense_errors_low[0x20];
1694
1695         u8         dot3stats_frame_too_longs_high[0x20];
1696
1697         u8         dot3stats_frame_too_longs_low[0x20];
1698
1699         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1700
1701         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1702
1703         u8         dot3stats_symbol_errors_high[0x20];
1704
1705         u8         dot3stats_symbol_errors_low[0x20];
1706
1707         u8         dot3control_in_unknown_opcodes_high[0x20];
1708
1709         u8         dot3control_in_unknown_opcodes_low[0x20];
1710
1711         u8         dot3in_pause_frames_high[0x20];
1712
1713         u8         dot3in_pause_frames_low[0x20];
1714
1715         u8         dot3out_pause_frames_high[0x20];
1716
1717         u8         dot3out_pause_frames_low[0x20];
1718
1719         u8         reserved_at_400[0x3c0];
1720 };
1721
1722 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1723         u8         ether_stats_drop_events_high[0x20];
1724
1725         u8         ether_stats_drop_events_low[0x20];
1726
1727         u8         ether_stats_octets_high[0x20];
1728
1729         u8         ether_stats_octets_low[0x20];
1730
1731         u8         ether_stats_pkts_high[0x20];
1732
1733         u8         ether_stats_pkts_low[0x20];
1734
1735         u8         ether_stats_broadcast_pkts_high[0x20];
1736
1737         u8         ether_stats_broadcast_pkts_low[0x20];
1738
1739         u8         ether_stats_multicast_pkts_high[0x20];
1740
1741         u8         ether_stats_multicast_pkts_low[0x20];
1742
1743         u8         ether_stats_crc_align_errors_high[0x20];
1744
1745         u8         ether_stats_crc_align_errors_low[0x20];
1746
1747         u8         ether_stats_undersize_pkts_high[0x20];
1748
1749         u8         ether_stats_undersize_pkts_low[0x20];
1750
1751         u8         ether_stats_oversize_pkts_high[0x20];
1752
1753         u8         ether_stats_oversize_pkts_low[0x20];
1754
1755         u8         ether_stats_fragments_high[0x20];
1756
1757         u8         ether_stats_fragments_low[0x20];
1758
1759         u8         ether_stats_jabbers_high[0x20];
1760
1761         u8         ether_stats_jabbers_low[0x20];
1762
1763         u8         ether_stats_collisions_high[0x20];
1764
1765         u8         ether_stats_collisions_low[0x20];
1766
1767         u8         ether_stats_pkts64octets_high[0x20];
1768
1769         u8         ether_stats_pkts64octets_low[0x20];
1770
1771         u8         ether_stats_pkts65to127octets_high[0x20];
1772
1773         u8         ether_stats_pkts65to127octets_low[0x20];
1774
1775         u8         ether_stats_pkts128to255octets_high[0x20];
1776
1777         u8         ether_stats_pkts128to255octets_low[0x20];
1778
1779         u8         ether_stats_pkts256to511octets_high[0x20];
1780
1781         u8         ether_stats_pkts256to511octets_low[0x20];
1782
1783         u8         ether_stats_pkts512to1023octets_high[0x20];
1784
1785         u8         ether_stats_pkts512to1023octets_low[0x20];
1786
1787         u8         ether_stats_pkts1024to1518octets_high[0x20];
1788
1789         u8         ether_stats_pkts1024to1518octets_low[0x20];
1790
1791         u8         ether_stats_pkts1519to2047octets_high[0x20];
1792
1793         u8         ether_stats_pkts1519to2047octets_low[0x20];
1794
1795         u8         ether_stats_pkts2048to4095octets_high[0x20];
1796
1797         u8         ether_stats_pkts2048to4095octets_low[0x20];
1798
1799         u8         ether_stats_pkts4096to8191octets_high[0x20];
1800
1801         u8         ether_stats_pkts4096to8191octets_low[0x20];
1802
1803         u8         ether_stats_pkts8192to10239octets_high[0x20];
1804
1805         u8         ether_stats_pkts8192to10239octets_low[0x20];
1806
1807         u8         reserved_at_540[0x280];
1808 };
1809
1810 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1811         u8         if_in_octets_high[0x20];
1812
1813         u8         if_in_octets_low[0x20];
1814
1815         u8         if_in_ucast_pkts_high[0x20];
1816
1817         u8         if_in_ucast_pkts_low[0x20];
1818
1819         u8         if_in_discards_high[0x20];
1820
1821         u8         if_in_discards_low[0x20];
1822
1823         u8         if_in_errors_high[0x20];
1824
1825         u8         if_in_errors_low[0x20];
1826
1827         u8         if_in_unknown_protos_high[0x20];
1828
1829         u8         if_in_unknown_protos_low[0x20];
1830
1831         u8         if_out_octets_high[0x20];
1832
1833         u8         if_out_octets_low[0x20];
1834
1835         u8         if_out_ucast_pkts_high[0x20];
1836
1837         u8         if_out_ucast_pkts_low[0x20];
1838
1839         u8         if_out_discards_high[0x20];
1840
1841         u8         if_out_discards_low[0x20];
1842
1843         u8         if_out_errors_high[0x20];
1844
1845         u8         if_out_errors_low[0x20];
1846
1847         u8         if_in_multicast_pkts_high[0x20];
1848
1849         u8         if_in_multicast_pkts_low[0x20];
1850
1851         u8         if_in_broadcast_pkts_high[0x20];
1852
1853         u8         if_in_broadcast_pkts_low[0x20];
1854
1855         u8         if_out_multicast_pkts_high[0x20];
1856
1857         u8         if_out_multicast_pkts_low[0x20];
1858
1859         u8         if_out_broadcast_pkts_high[0x20];
1860
1861         u8         if_out_broadcast_pkts_low[0x20];
1862
1863         u8         reserved_at_340[0x480];
1864 };
1865
1866 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1867         u8         a_frames_transmitted_ok_high[0x20];
1868
1869         u8         a_frames_transmitted_ok_low[0x20];
1870
1871         u8         a_frames_received_ok_high[0x20];
1872
1873         u8         a_frames_received_ok_low[0x20];
1874
1875         u8         a_frame_check_sequence_errors_high[0x20];
1876
1877         u8         a_frame_check_sequence_errors_low[0x20];
1878
1879         u8         a_alignment_errors_high[0x20];
1880
1881         u8         a_alignment_errors_low[0x20];
1882
1883         u8         a_octets_transmitted_ok_high[0x20];
1884
1885         u8         a_octets_transmitted_ok_low[0x20];
1886
1887         u8         a_octets_received_ok_high[0x20];
1888
1889         u8         a_octets_received_ok_low[0x20];
1890
1891         u8         a_multicast_frames_xmitted_ok_high[0x20];
1892
1893         u8         a_multicast_frames_xmitted_ok_low[0x20];
1894
1895         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1896
1897         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1898
1899         u8         a_multicast_frames_received_ok_high[0x20];
1900
1901         u8         a_multicast_frames_received_ok_low[0x20];
1902
1903         u8         a_broadcast_frames_received_ok_high[0x20];
1904
1905         u8         a_broadcast_frames_received_ok_low[0x20];
1906
1907         u8         a_in_range_length_errors_high[0x20];
1908
1909         u8         a_in_range_length_errors_low[0x20];
1910
1911         u8         a_out_of_range_length_field_high[0x20];
1912
1913         u8         a_out_of_range_length_field_low[0x20];
1914
1915         u8         a_frame_too_long_errors_high[0x20];
1916
1917         u8         a_frame_too_long_errors_low[0x20];
1918
1919         u8         a_symbol_error_during_carrier_high[0x20];
1920
1921         u8         a_symbol_error_during_carrier_low[0x20];
1922
1923         u8         a_mac_control_frames_transmitted_high[0x20];
1924
1925         u8         a_mac_control_frames_transmitted_low[0x20];
1926
1927         u8         a_mac_control_frames_received_high[0x20];
1928
1929         u8         a_mac_control_frames_received_low[0x20];
1930
1931         u8         a_unsupported_opcodes_received_high[0x20];
1932
1933         u8         a_unsupported_opcodes_received_low[0x20];
1934
1935         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1936
1937         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1938
1939         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1940
1941         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1942
1943         u8         reserved_at_4c0[0x300];
1944 };
1945
1946 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1947         u8         life_time_counter_high[0x20];
1948
1949         u8         life_time_counter_low[0x20];
1950
1951         u8         rx_errors[0x20];
1952
1953         u8         tx_errors[0x20];
1954
1955         u8         l0_to_recovery_eieos[0x20];
1956
1957         u8         l0_to_recovery_ts[0x20];
1958
1959         u8         l0_to_recovery_framing[0x20];
1960
1961         u8         l0_to_recovery_retrain[0x20];
1962
1963         u8         crc_error_dllp[0x20];
1964
1965         u8         crc_error_tlp[0x20];
1966
1967         u8         tx_overflow_buffer_pkt_high[0x20];
1968
1969         u8         tx_overflow_buffer_pkt_low[0x20];
1970
1971         u8         outbound_stalled_reads[0x20];
1972
1973         u8         outbound_stalled_writes[0x20];
1974
1975         u8         outbound_stalled_reads_events[0x20];
1976
1977         u8         outbound_stalled_writes_events[0x20];
1978
1979         u8         reserved_at_200[0x5c0];
1980 };
1981
1982 struct mlx5_ifc_cmd_inter_comp_event_bits {
1983         u8         command_completion_vector[0x20];
1984
1985         u8         reserved_at_20[0xc0];
1986 };
1987
1988 struct mlx5_ifc_stall_vl_event_bits {
1989         u8         reserved_at_0[0x18];
1990         u8         port_num[0x1];
1991         u8         reserved_at_19[0x3];
1992         u8         vl[0x4];
1993
1994         u8         reserved_at_20[0xa0];
1995 };
1996
1997 struct mlx5_ifc_db_bf_congestion_event_bits {
1998         u8         event_subtype[0x8];
1999         u8         reserved_at_8[0x8];
2000         u8         congestion_level[0x8];
2001         u8         reserved_at_18[0x8];
2002
2003         u8         reserved_at_20[0xa0];
2004 };
2005
2006 struct mlx5_ifc_gpio_event_bits {
2007         u8         reserved_at_0[0x60];
2008
2009         u8         gpio_event_hi[0x20];
2010
2011         u8         gpio_event_lo[0x20];
2012
2013         u8         reserved_at_a0[0x40];
2014 };
2015
2016 struct mlx5_ifc_port_state_change_event_bits {
2017         u8         reserved_at_0[0x40];
2018
2019         u8         port_num[0x4];
2020         u8         reserved_at_44[0x1c];
2021
2022         u8         reserved_at_60[0x80];
2023 };
2024
2025 struct mlx5_ifc_dropped_packet_logged_bits {
2026         u8         reserved_at_0[0xe0];
2027 };
2028
2029 enum {
2030         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2031         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2032 };
2033
2034 struct mlx5_ifc_cq_error_bits {
2035         u8         reserved_at_0[0x8];
2036         u8         cqn[0x18];
2037
2038         u8         reserved_at_20[0x20];
2039
2040         u8         reserved_at_40[0x18];
2041         u8         syndrome[0x8];
2042
2043         u8         reserved_at_60[0x80];
2044 };
2045
2046 struct mlx5_ifc_rdma_page_fault_event_bits {
2047         u8         bytes_committed[0x20];
2048
2049         u8         r_key[0x20];
2050
2051         u8         reserved_at_40[0x10];
2052         u8         packet_len[0x10];
2053
2054         u8         rdma_op_len[0x20];
2055
2056         u8         rdma_va[0x40];
2057
2058         u8         reserved_at_c0[0x5];
2059         u8         rdma[0x1];
2060         u8         write[0x1];
2061         u8         requestor[0x1];
2062         u8         qp_number[0x18];
2063 };
2064
2065 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2066         u8         bytes_committed[0x20];
2067
2068         u8         reserved_at_20[0x10];
2069         u8         wqe_index[0x10];
2070
2071         u8         reserved_at_40[0x10];
2072         u8         len[0x10];
2073
2074         u8         reserved_at_60[0x60];
2075
2076         u8         reserved_at_c0[0x5];
2077         u8         rdma[0x1];
2078         u8         write_read[0x1];
2079         u8         requestor[0x1];
2080         u8         qpn[0x18];
2081 };
2082
2083 struct mlx5_ifc_qp_events_bits {
2084         u8         reserved_at_0[0xa0];
2085
2086         u8         type[0x8];
2087         u8         reserved_at_a8[0x18];
2088
2089         u8         reserved_at_c0[0x8];
2090         u8         qpn_rqn_sqn[0x18];
2091 };
2092
2093 struct mlx5_ifc_dct_events_bits {
2094         u8         reserved_at_0[0xc0];
2095
2096         u8         reserved_at_c0[0x8];
2097         u8         dct_number[0x18];
2098 };
2099
2100 struct mlx5_ifc_comp_event_bits {
2101         u8         reserved_at_0[0xc0];
2102
2103         u8         reserved_at_c0[0x8];
2104         u8         cq_number[0x18];
2105 };
2106
2107 enum {
2108         MLX5_QPC_STATE_RST        = 0x0,
2109         MLX5_QPC_STATE_INIT       = 0x1,
2110         MLX5_QPC_STATE_RTR        = 0x2,
2111         MLX5_QPC_STATE_RTS        = 0x3,
2112         MLX5_QPC_STATE_SQER       = 0x4,
2113         MLX5_QPC_STATE_ERR        = 0x6,
2114         MLX5_QPC_STATE_SQD        = 0x7,
2115         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2116 };
2117
2118 enum {
2119         MLX5_QPC_ST_RC            = 0x0,
2120         MLX5_QPC_ST_UC            = 0x1,
2121         MLX5_QPC_ST_UD            = 0x2,
2122         MLX5_QPC_ST_XRC           = 0x3,
2123         MLX5_QPC_ST_DCI           = 0x5,
2124         MLX5_QPC_ST_QP0           = 0x7,
2125         MLX5_QPC_ST_QP1           = 0x8,
2126         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2127         MLX5_QPC_ST_REG_UMR       = 0xc,
2128 };
2129
2130 enum {
2131         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2132         MLX5_QPC_PM_STATE_REARM     = 0x1,
2133         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2134         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2135 };
2136
2137 enum {
2138         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2139 };
2140
2141 enum {
2142         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2143         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2144 };
2145
2146 enum {
2147         MLX5_QPC_MTU_256_BYTES        = 0x1,
2148         MLX5_QPC_MTU_512_BYTES        = 0x2,
2149         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2150         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2151         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2152         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2153 };
2154
2155 enum {
2156         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2157         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2158         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2159         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2160         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2161         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2162         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2163         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2164 };
2165
2166 enum {
2167         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2168         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2169         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2170 };
2171
2172 enum {
2173         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2174         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2175         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2176 };
2177
2178 struct mlx5_ifc_qpc_bits {
2179         u8         state[0x4];
2180         u8         lag_tx_port_affinity[0x4];
2181         u8         st[0x8];
2182         u8         reserved_at_10[0x3];
2183         u8         pm_state[0x2];
2184         u8         reserved_at_15[0x3];
2185         u8         offload_type[0x4];
2186         u8         end_padding_mode[0x2];
2187         u8         reserved_at_1e[0x2];
2188
2189         u8         wq_signature[0x1];
2190         u8         block_lb_mc[0x1];
2191         u8         atomic_like_write_en[0x1];
2192         u8         latency_sensitive[0x1];
2193         u8         reserved_at_24[0x1];
2194         u8         drain_sigerr[0x1];
2195         u8         reserved_at_26[0x2];
2196         u8         pd[0x18];
2197
2198         u8         mtu[0x3];
2199         u8         log_msg_max[0x5];
2200         u8         reserved_at_48[0x1];
2201         u8         log_rq_size[0x4];
2202         u8         log_rq_stride[0x3];
2203         u8         no_sq[0x1];
2204         u8         log_sq_size[0x4];
2205         u8         reserved_at_55[0x6];
2206         u8         rlky[0x1];
2207         u8         ulp_stateless_offload_mode[0x4];
2208
2209         u8         counter_set_id[0x8];
2210         u8         uar_page[0x18];
2211
2212         u8         reserved_at_80[0x8];
2213         u8         user_index[0x18];
2214
2215         u8         reserved_at_a0[0x3];
2216         u8         log_page_size[0x5];
2217         u8         remote_qpn[0x18];
2218
2219         struct mlx5_ifc_ads_bits primary_address_path;
2220
2221         struct mlx5_ifc_ads_bits secondary_address_path;
2222
2223         u8         log_ack_req_freq[0x4];
2224         u8         reserved_at_384[0x4];
2225         u8         log_sra_max[0x3];
2226         u8         reserved_at_38b[0x2];
2227         u8         retry_count[0x3];
2228         u8         rnr_retry[0x3];
2229         u8         reserved_at_393[0x1];
2230         u8         fre[0x1];
2231         u8         cur_rnr_retry[0x3];
2232         u8         cur_retry_count[0x3];
2233         u8         reserved_at_39b[0x5];
2234
2235         u8         reserved_at_3a0[0x20];
2236
2237         u8         reserved_at_3c0[0x8];
2238         u8         next_send_psn[0x18];
2239
2240         u8         reserved_at_3e0[0x8];
2241         u8         cqn_snd[0x18];
2242
2243         u8         reserved_at_400[0x8];
2244         u8         deth_sqpn[0x18];
2245
2246         u8         reserved_at_420[0x20];
2247
2248         u8         reserved_at_440[0x8];
2249         u8         last_acked_psn[0x18];
2250
2251         u8         reserved_at_460[0x8];
2252         u8         ssn[0x18];
2253
2254         u8         reserved_at_480[0x8];
2255         u8         log_rra_max[0x3];
2256         u8         reserved_at_48b[0x1];
2257         u8         atomic_mode[0x4];
2258         u8         rre[0x1];
2259         u8         rwe[0x1];
2260         u8         rae[0x1];
2261         u8         reserved_at_493[0x1];
2262         u8         page_offset[0x6];
2263         u8         reserved_at_49a[0x3];
2264         u8         cd_slave_receive[0x1];
2265         u8         cd_slave_send[0x1];
2266         u8         cd_master[0x1];
2267
2268         u8         reserved_at_4a0[0x3];
2269         u8         min_rnr_nak[0x5];
2270         u8         next_rcv_psn[0x18];
2271
2272         u8         reserved_at_4c0[0x8];
2273         u8         xrcd[0x18];
2274
2275         u8         reserved_at_4e0[0x8];
2276         u8         cqn_rcv[0x18];
2277
2278         u8         dbr_addr[0x40];
2279
2280         u8         q_key[0x20];
2281
2282         u8         reserved_at_560[0x5];
2283         u8         rq_type[0x3];
2284         u8         srqn_rmpn_xrqn[0x18];
2285
2286         u8         reserved_at_580[0x8];
2287         u8         rmsn[0x18];
2288
2289         u8         hw_sq_wqebb_counter[0x10];
2290         u8         sw_sq_wqebb_counter[0x10];
2291
2292         u8         hw_rq_counter[0x20];
2293
2294         u8         sw_rq_counter[0x20];
2295
2296         u8         reserved_at_600[0x20];
2297
2298         u8         reserved_at_620[0xf];
2299         u8         cgs[0x1];
2300         u8         cs_req[0x8];
2301         u8         cs_res[0x8];
2302
2303         u8         dc_access_key[0x40];
2304
2305         u8         reserved_at_680[0xc0];
2306 };
2307
2308 struct mlx5_ifc_roce_addr_layout_bits {
2309         u8         source_l3_address[16][0x8];
2310
2311         u8         reserved_at_80[0x3];
2312         u8         vlan_valid[0x1];
2313         u8         vlan_id[0xc];
2314         u8         source_mac_47_32[0x10];
2315
2316         u8         source_mac_31_0[0x20];
2317
2318         u8         reserved_at_c0[0x14];
2319         u8         roce_l3_type[0x4];
2320         u8         roce_version[0x8];
2321
2322         u8         reserved_at_e0[0x20];
2323 };
2324
2325 union mlx5_ifc_hca_cap_union_bits {
2326         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2327         struct mlx5_ifc_odp_cap_bits odp_cap;
2328         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2329         struct mlx5_ifc_roce_cap_bits roce_cap;
2330         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2331         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2332         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2333         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2334         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2335         struct mlx5_ifc_qos_cap_bits qos_cap;
2336         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2337         u8         reserved_at_0[0x8000];
2338 };
2339
2340 enum {
2341         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2342         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2343         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2344         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2345         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2346         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2347         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2348         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2349         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2350 };
2351
2352 struct mlx5_ifc_vlan_bits {
2353         u8         ethtype[0x10];
2354         u8         prio[0x3];
2355         u8         cfi[0x1];
2356         u8         vid[0xc];
2357 };
2358
2359 struct mlx5_ifc_flow_context_bits {
2360         struct mlx5_ifc_vlan_bits push_vlan;
2361
2362         u8         group_id[0x20];
2363
2364         u8         reserved_at_40[0x8];
2365         u8         flow_tag[0x18];
2366
2367         u8         reserved_at_60[0x10];
2368         u8         action[0x10];
2369
2370         u8         reserved_at_80[0x8];
2371         u8         destination_list_size[0x18];
2372
2373         u8         reserved_at_a0[0x8];
2374         u8         flow_counter_list_size[0x18];
2375
2376         u8         encap_id[0x20];
2377
2378         u8         modify_header_id[0x20];
2379
2380         u8         reserved_at_100[0x100];
2381
2382         struct mlx5_ifc_fte_match_param_bits match_value;
2383
2384         u8         reserved_at_1200[0x600];
2385
2386         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2387 };
2388
2389 enum {
2390         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2391         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2392 };
2393
2394 struct mlx5_ifc_xrc_srqc_bits {
2395         u8         state[0x4];
2396         u8         log_xrc_srq_size[0x4];
2397         u8         reserved_at_8[0x18];
2398
2399         u8         wq_signature[0x1];
2400         u8         cont_srq[0x1];
2401         u8         reserved_at_22[0x1];
2402         u8         rlky[0x1];
2403         u8         basic_cyclic_rcv_wqe[0x1];
2404         u8         log_rq_stride[0x3];
2405         u8         xrcd[0x18];
2406
2407         u8         page_offset[0x6];
2408         u8         reserved_at_46[0x2];
2409         u8         cqn[0x18];
2410
2411         u8         reserved_at_60[0x20];
2412
2413         u8         user_index_equal_xrc_srqn[0x1];
2414         u8         reserved_at_81[0x1];
2415         u8         log_page_size[0x6];
2416         u8         user_index[0x18];
2417
2418         u8         reserved_at_a0[0x20];
2419
2420         u8         reserved_at_c0[0x8];
2421         u8         pd[0x18];
2422
2423         u8         lwm[0x10];
2424         u8         wqe_cnt[0x10];
2425
2426         u8         reserved_at_100[0x40];
2427
2428         u8         db_record_addr_h[0x20];
2429
2430         u8         db_record_addr_l[0x1e];
2431         u8         reserved_at_17e[0x2];
2432
2433         u8         reserved_at_180[0x80];
2434 };
2435
2436 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2437         u8         counter_error_queues[0x20];
2438
2439         u8         total_error_queues[0x20];
2440
2441         u8         send_queue_priority_update_flow[0x20];
2442
2443         u8         reserved_at_60[0x20];
2444
2445         u8         nic_receive_steering_discard[0x40];
2446
2447         u8         receive_discard_vport_down[0x40];
2448
2449         u8         transmit_discard_vport_down[0x40];
2450
2451         u8         reserved_at_140[0xec0];
2452 };
2453
2454 struct mlx5_ifc_traffic_counter_bits {
2455         u8         packets[0x40];
2456
2457         u8         octets[0x40];
2458 };
2459
2460 struct mlx5_ifc_tisc_bits {
2461         u8         strict_lag_tx_port_affinity[0x1];
2462         u8         reserved_at_1[0x3];
2463         u8         lag_tx_port_affinity[0x04];
2464
2465         u8         reserved_at_8[0x4];
2466         u8         prio[0x4];
2467         u8         reserved_at_10[0x10];
2468
2469         u8         reserved_at_20[0x100];
2470
2471         u8         reserved_at_120[0x8];
2472         u8         transport_domain[0x18];
2473
2474         u8         reserved_at_140[0x8];
2475         u8         underlay_qpn[0x18];
2476         u8         reserved_at_160[0x3a0];
2477 };
2478
2479 enum {
2480         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2481         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2482 };
2483
2484 enum {
2485         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2486         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2487 };
2488
2489 enum {
2490         MLX5_RX_HASH_FN_NONE           = 0x0,
2491         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2492         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2493 };
2494
2495 enum {
2496         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2497         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2498 };
2499
2500 struct mlx5_ifc_tirc_bits {
2501         u8         reserved_at_0[0x20];
2502
2503         u8         disp_type[0x4];
2504         u8         reserved_at_24[0x1c];
2505
2506         u8         reserved_at_40[0x40];
2507
2508         u8         reserved_at_80[0x4];
2509         u8         lro_timeout_period_usecs[0x10];
2510         u8         lro_enable_mask[0x4];
2511         u8         lro_max_ip_payload_size[0x8];
2512
2513         u8         reserved_at_a0[0x40];
2514
2515         u8         reserved_at_e0[0x8];
2516         u8         inline_rqn[0x18];
2517
2518         u8         rx_hash_symmetric[0x1];
2519         u8         reserved_at_101[0x1];
2520         u8         tunneled_offload_en[0x1];
2521         u8         reserved_at_103[0x5];
2522         u8         indirect_table[0x18];
2523
2524         u8         rx_hash_fn[0x4];
2525         u8         reserved_at_124[0x2];
2526         u8         self_lb_block[0x2];
2527         u8         transport_domain[0x18];
2528
2529         u8         rx_hash_toeplitz_key[10][0x20];
2530
2531         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2532
2533         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2534
2535         u8         reserved_at_2c0[0x4c0];
2536 };
2537
2538 enum {
2539         MLX5_SRQC_STATE_GOOD   = 0x0,
2540         MLX5_SRQC_STATE_ERROR  = 0x1,
2541 };
2542
2543 struct mlx5_ifc_srqc_bits {
2544         u8         state[0x4];
2545         u8         log_srq_size[0x4];
2546         u8         reserved_at_8[0x18];
2547
2548         u8         wq_signature[0x1];
2549         u8         cont_srq[0x1];
2550         u8         reserved_at_22[0x1];
2551         u8         rlky[0x1];
2552         u8         reserved_at_24[0x1];
2553         u8         log_rq_stride[0x3];
2554         u8         xrcd[0x18];
2555
2556         u8         page_offset[0x6];
2557         u8         reserved_at_46[0x2];
2558         u8         cqn[0x18];
2559
2560         u8         reserved_at_60[0x20];
2561
2562         u8         reserved_at_80[0x2];
2563         u8         log_page_size[0x6];
2564         u8         reserved_at_88[0x18];
2565
2566         u8         reserved_at_a0[0x20];
2567
2568         u8         reserved_at_c0[0x8];
2569         u8         pd[0x18];
2570
2571         u8         lwm[0x10];
2572         u8         wqe_cnt[0x10];
2573
2574         u8         reserved_at_100[0x40];
2575
2576         u8         dbr_addr[0x40];
2577
2578         u8         reserved_at_180[0x80];
2579 };
2580
2581 enum {
2582         MLX5_SQC_STATE_RST  = 0x0,
2583         MLX5_SQC_STATE_RDY  = 0x1,
2584         MLX5_SQC_STATE_ERR  = 0x3,
2585 };
2586
2587 struct mlx5_ifc_sqc_bits {
2588         u8         rlky[0x1];
2589         u8         cd_master[0x1];
2590         u8         fre[0x1];
2591         u8         flush_in_error_en[0x1];
2592         u8         allow_multi_pkt_send_wqe[0x1];
2593         u8         min_wqe_inline_mode[0x3];
2594         u8         state[0x4];
2595         u8         reg_umr[0x1];
2596         u8         allow_swp[0x1];
2597         u8         hairpin[0x1];
2598         u8         reserved_at_f[0x11];
2599
2600         u8         reserved_at_20[0x8];
2601         u8         user_index[0x18];
2602
2603         u8         reserved_at_40[0x8];
2604         u8         cqn[0x18];
2605
2606         u8         reserved_at_60[0x8];
2607         u8         hairpin_peer_rq[0x18];
2608
2609         u8         reserved_at_80[0x10];
2610         u8         hairpin_peer_vhca[0x10];
2611
2612         u8         reserved_at_a0[0x50];
2613
2614         u8         packet_pacing_rate_limit_index[0x10];
2615         u8         tis_lst_sz[0x10];
2616         u8         reserved_at_110[0x10];
2617
2618         u8         reserved_at_120[0x40];
2619
2620         u8         reserved_at_160[0x8];
2621         u8         tis_num_0[0x18];
2622
2623         struct mlx5_ifc_wq_bits wq;
2624 };
2625
2626 enum {
2627         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2628         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2629         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2630         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2631 };
2632
2633 struct mlx5_ifc_scheduling_context_bits {
2634         u8         element_type[0x8];
2635         u8         reserved_at_8[0x18];
2636
2637         u8         element_attributes[0x20];
2638
2639         u8         parent_element_id[0x20];
2640
2641         u8         reserved_at_60[0x40];
2642
2643         u8         bw_share[0x20];
2644
2645         u8         max_average_bw[0x20];
2646
2647         u8         reserved_at_e0[0x120];
2648 };
2649
2650 struct mlx5_ifc_rqtc_bits {
2651         u8         reserved_at_0[0xa0];
2652
2653         u8         reserved_at_a0[0x10];
2654         u8         rqt_max_size[0x10];
2655
2656         u8         reserved_at_c0[0x10];
2657         u8         rqt_actual_size[0x10];
2658
2659         u8         reserved_at_e0[0x6a0];
2660
2661         struct mlx5_ifc_rq_num_bits rq_num[0];
2662 };
2663
2664 enum {
2665         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2666         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2667 };
2668
2669 enum {
2670         MLX5_RQC_STATE_RST  = 0x0,
2671         MLX5_RQC_STATE_RDY  = 0x1,
2672         MLX5_RQC_STATE_ERR  = 0x3,
2673 };
2674
2675 struct mlx5_ifc_rqc_bits {
2676         u8         rlky[0x1];
2677         u8         delay_drop_en[0x1];
2678         u8         scatter_fcs[0x1];
2679         u8         vsd[0x1];
2680         u8         mem_rq_type[0x4];
2681         u8         state[0x4];
2682         u8         reserved_at_c[0x1];
2683         u8         flush_in_error_en[0x1];
2684         u8         hairpin[0x1];
2685         u8         reserved_at_f[0x11];
2686
2687         u8         reserved_at_20[0x8];
2688         u8         user_index[0x18];
2689
2690         u8         reserved_at_40[0x8];
2691         u8         cqn[0x18];
2692
2693         u8         counter_set_id[0x8];
2694         u8         reserved_at_68[0x18];
2695
2696         u8         reserved_at_80[0x8];
2697         u8         rmpn[0x18];
2698
2699         u8         reserved_at_a0[0x8];
2700         u8         hairpin_peer_sq[0x18];
2701
2702         u8         reserved_at_c0[0x10];
2703         u8         hairpin_peer_vhca[0x10];
2704
2705         u8         reserved_at_e0[0xa0];
2706
2707         struct mlx5_ifc_wq_bits wq;
2708 };
2709
2710 enum {
2711         MLX5_RMPC_STATE_RDY  = 0x1,
2712         MLX5_RMPC_STATE_ERR  = 0x3,
2713 };
2714
2715 struct mlx5_ifc_rmpc_bits {
2716         u8         reserved_at_0[0x8];
2717         u8         state[0x4];
2718         u8         reserved_at_c[0x14];
2719
2720         u8         basic_cyclic_rcv_wqe[0x1];
2721         u8         reserved_at_21[0x1f];
2722
2723         u8         reserved_at_40[0x140];
2724
2725         struct mlx5_ifc_wq_bits wq;
2726 };
2727
2728 struct mlx5_ifc_nic_vport_context_bits {
2729         u8         reserved_at_0[0x5];
2730         u8         min_wqe_inline_mode[0x3];
2731         u8         reserved_at_8[0x15];
2732         u8         disable_mc_local_lb[0x1];
2733         u8         disable_uc_local_lb[0x1];
2734         u8         roce_en[0x1];
2735
2736         u8         arm_change_event[0x1];
2737         u8         reserved_at_21[0x1a];
2738         u8         event_on_mtu[0x1];
2739         u8         event_on_promisc_change[0x1];
2740         u8         event_on_vlan_change[0x1];
2741         u8         event_on_mc_address_change[0x1];
2742         u8         event_on_uc_address_change[0x1];
2743
2744         u8         reserved_at_40[0xc];
2745
2746         u8         affiliation_criteria[0x4];
2747         u8         affiliated_vhca_id[0x10];
2748
2749         u8         reserved_at_60[0xd0];
2750
2751         u8         mtu[0x10];
2752
2753         u8         system_image_guid[0x40];
2754         u8         port_guid[0x40];
2755         u8         node_guid[0x40];
2756
2757         u8         reserved_at_200[0x140];
2758         u8         qkey_violation_counter[0x10];
2759         u8         reserved_at_350[0x430];
2760
2761         u8         promisc_uc[0x1];
2762         u8         promisc_mc[0x1];
2763         u8         promisc_all[0x1];
2764         u8         reserved_at_783[0x2];
2765         u8         allowed_list_type[0x3];
2766         u8         reserved_at_788[0xc];
2767         u8         allowed_list_size[0xc];
2768
2769         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2770
2771         u8         reserved_at_7e0[0x20];
2772
2773         u8         current_uc_mac_address[0][0x40];
2774 };
2775
2776 enum {
2777         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2778         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2779         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2780         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2781         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2782 };
2783
2784 struct mlx5_ifc_mkc_bits {
2785         u8         reserved_at_0[0x1];
2786         u8         free[0x1];
2787         u8         reserved_at_2[0x1];
2788         u8         access_mode_4_2[0x3];
2789         u8         reserved_at_6[0x7];
2790         u8         relaxed_ordering_write[0x1];
2791         u8         reserved_at_e[0x1];
2792         u8         small_fence_on_rdma_read_response[0x1];
2793         u8         umr_en[0x1];
2794         u8         a[0x1];
2795         u8         rw[0x1];
2796         u8         rr[0x1];
2797         u8         lw[0x1];
2798         u8         lr[0x1];
2799         u8         access_mode_1_0[0x2];
2800         u8         reserved_at_18[0x8];
2801
2802         u8         qpn[0x18];
2803         u8         mkey_7_0[0x8];
2804
2805         u8         reserved_at_40[0x20];
2806
2807         u8         length64[0x1];
2808         u8         bsf_en[0x1];
2809         u8         sync_umr[0x1];
2810         u8         reserved_at_63[0x2];
2811         u8         expected_sigerr_count[0x1];
2812         u8         reserved_at_66[0x1];
2813         u8         en_rinval[0x1];
2814         u8         pd[0x18];
2815
2816         u8         start_addr[0x40];
2817
2818         u8         len[0x40];
2819
2820         u8         bsf_octword_size[0x20];
2821
2822         u8         reserved_at_120[0x80];
2823
2824         u8         translations_octword_size[0x20];
2825
2826         u8         reserved_at_1c0[0x1b];
2827         u8         log_page_size[0x5];
2828
2829         u8         reserved_at_1e0[0x20];
2830 };
2831
2832 struct mlx5_ifc_pkey_bits {
2833         u8         reserved_at_0[0x10];
2834         u8         pkey[0x10];
2835 };
2836
2837 struct mlx5_ifc_array128_auto_bits {
2838         u8         array128_auto[16][0x8];
2839 };
2840
2841 struct mlx5_ifc_hca_vport_context_bits {
2842         u8         field_select[0x20];
2843
2844         u8         reserved_at_20[0xe0];
2845
2846         u8         sm_virt_aware[0x1];
2847         u8         has_smi[0x1];
2848         u8         has_raw[0x1];
2849         u8         grh_required[0x1];
2850         u8         reserved_at_104[0xc];
2851         u8         port_physical_state[0x4];
2852         u8         vport_state_policy[0x4];
2853         u8         port_state[0x4];
2854         u8         vport_state[0x4];
2855
2856         u8         reserved_at_120[0x20];
2857
2858         u8         system_image_guid[0x40];
2859
2860         u8         port_guid[0x40];
2861
2862         u8         node_guid[0x40];
2863
2864         u8         cap_mask1[0x20];
2865
2866         u8         cap_mask1_field_select[0x20];
2867
2868         u8         cap_mask2[0x20];
2869
2870         u8         cap_mask2_field_select[0x20];
2871
2872         u8         reserved_at_280[0x80];
2873
2874         u8         lid[0x10];
2875         u8         reserved_at_310[0x4];
2876         u8         init_type_reply[0x4];
2877         u8         lmc[0x3];
2878         u8         subnet_timeout[0x5];
2879
2880         u8         sm_lid[0x10];
2881         u8         sm_sl[0x4];
2882         u8         reserved_at_334[0xc];
2883
2884         u8         qkey_violation_counter[0x10];
2885         u8         pkey_violation_counter[0x10];
2886
2887         u8         reserved_at_360[0xca0];
2888 };
2889
2890 struct mlx5_ifc_esw_vport_context_bits {
2891         u8         reserved_at_0[0x3];
2892         u8         vport_svlan_strip[0x1];
2893         u8         vport_cvlan_strip[0x1];
2894         u8         vport_svlan_insert[0x1];
2895         u8         vport_cvlan_insert[0x2];
2896         u8         reserved_at_8[0x18];
2897
2898         u8         reserved_at_20[0x20];
2899
2900         u8         svlan_cfi[0x1];
2901         u8         svlan_pcp[0x3];
2902         u8         svlan_id[0xc];
2903         u8         cvlan_cfi[0x1];
2904         u8         cvlan_pcp[0x3];
2905         u8         cvlan_id[0xc];
2906
2907         u8         reserved_at_60[0x7a0];
2908 };
2909
2910 enum {
2911         MLX5_EQC_STATUS_OK                = 0x0,
2912         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2913 };
2914
2915 enum {
2916         MLX5_EQC_ST_ARMED  = 0x9,
2917         MLX5_EQC_ST_FIRED  = 0xa,
2918 };
2919
2920 struct mlx5_ifc_eqc_bits {
2921         u8         status[0x4];
2922         u8         reserved_at_4[0x9];
2923         u8         ec[0x1];
2924         u8         oi[0x1];
2925         u8         reserved_at_f[0x5];
2926         u8         st[0x4];
2927         u8         reserved_at_18[0x8];
2928
2929         u8         reserved_at_20[0x20];
2930
2931         u8         reserved_at_40[0x14];
2932         u8         page_offset[0x6];
2933         u8         reserved_at_5a[0x6];
2934
2935         u8         reserved_at_60[0x3];
2936         u8         log_eq_size[0x5];
2937         u8         uar_page[0x18];
2938
2939         u8         reserved_at_80[0x20];
2940
2941         u8         reserved_at_a0[0x18];
2942         u8         intr[0x8];
2943
2944         u8         reserved_at_c0[0x3];
2945         u8         log_page_size[0x5];
2946         u8         reserved_at_c8[0x18];
2947
2948         u8         reserved_at_e0[0x60];
2949
2950         u8         reserved_at_140[0x8];
2951         u8         consumer_counter[0x18];
2952
2953         u8         reserved_at_160[0x8];
2954         u8         producer_counter[0x18];
2955
2956         u8         reserved_at_180[0x80];
2957 };
2958
2959 enum {
2960         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2961         MLX5_DCTC_STATE_DRAINING  = 0x1,
2962         MLX5_DCTC_STATE_DRAINED   = 0x2,
2963 };
2964
2965 enum {
2966         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2967         MLX5_DCTC_CS_RES_NA         = 0x1,
2968         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2969 };
2970
2971 enum {
2972         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2973         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2974         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2975         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2976         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2977 };
2978
2979 struct mlx5_ifc_dctc_bits {
2980         u8         reserved_at_0[0x4];
2981         u8         state[0x4];
2982         u8         reserved_at_8[0x18];
2983
2984         u8         reserved_at_20[0x8];
2985         u8         user_index[0x18];
2986
2987         u8         reserved_at_40[0x8];
2988         u8         cqn[0x18];
2989
2990         u8         counter_set_id[0x8];
2991         u8         atomic_mode[0x4];
2992         u8         rre[0x1];
2993         u8         rwe[0x1];
2994         u8         rae[0x1];
2995         u8         atomic_like_write_en[0x1];
2996         u8         latency_sensitive[0x1];
2997         u8         rlky[0x1];
2998         u8         free_ar[0x1];
2999         u8         reserved_at_73[0xd];
3000
3001         u8         reserved_at_80[0x8];
3002         u8         cs_res[0x8];
3003         u8         reserved_at_90[0x3];
3004         u8         min_rnr_nak[0x5];
3005         u8         reserved_at_98[0x8];
3006
3007         u8         reserved_at_a0[0x8];
3008         u8         srqn_xrqn[0x18];
3009
3010         u8         reserved_at_c0[0x8];
3011         u8         pd[0x18];
3012
3013         u8         tclass[0x8];
3014         u8         reserved_at_e8[0x4];
3015         u8         flow_label[0x14];
3016
3017         u8         dc_access_key[0x40];
3018
3019         u8         reserved_at_140[0x5];
3020         u8         mtu[0x3];
3021         u8         port[0x8];
3022         u8         pkey_index[0x10];
3023
3024         u8         reserved_at_160[0x8];
3025         u8         my_addr_index[0x8];
3026         u8         reserved_at_170[0x8];
3027         u8         hop_limit[0x8];
3028
3029         u8         dc_access_key_violation_count[0x20];
3030
3031         u8         reserved_at_1a0[0x14];
3032         u8         dei_cfi[0x1];
3033         u8         eth_prio[0x3];
3034         u8         ecn[0x2];
3035         u8         dscp[0x6];
3036
3037         u8         reserved_at_1c0[0x40];
3038 };
3039
3040 enum {
3041         MLX5_CQC_STATUS_OK             = 0x0,
3042         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3043         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3044 };
3045
3046 enum {
3047         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3048         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3049 };
3050
3051 enum {
3052         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3053         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3054         MLX5_CQC_ST_FIRED                                 = 0xa,
3055 };
3056
3057 enum {
3058         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3059         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3060         MLX5_CQ_PERIOD_NUM_MODES
3061 };
3062
3063 struct mlx5_ifc_cqc_bits {
3064         u8         status[0x4];
3065         u8         reserved_at_4[0x4];
3066         u8         cqe_sz[0x3];
3067         u8         cc[0x1];
3068         u8         reserved_at_c[0x1];
3069         u8         scqe_break_moderation_en[0x1];
3070         u8         oi[0x1];
3071         u8         cq_period_mode[0x2];
3072         u8         cqe_comp_en[0x1];
3073         u8         mini_cqe_res_format[0x2];
3074         u8         st[0x4];
3075         u8         reserved_at_18[0x8];
3076
3077         u8         reserved_at_20[0x20];
3078
3079         u8         reserved_at_40[0x14];
3080         u8         page_offset[0x6];
3081         u8         reserved_at_5a[0x6];
3082
3083         u8         reserved_at_60[0x3];
3084         u8         log_cq_size[0x5];
3085         u8         uar_page[0x18];
3086
3087         u8         reserved_at_80[0x4];
3088         u8         cq_period[0xc];
3089         u8         cq_max_count[0x10];
3090
3091         u8         reserved_at_a0[0x18];
3092         u8         c_eqn[0x8];
3093
3094         u8         reserved_at_c0[0x3];
3095         u8         log_page_size[0x5];
3096         u8         reserved_at_c8[0x18];
3097
3098         u8         reserved_at_e0[0x20];
3099
3100         u8         reserved_at_100[0x8];
3101         u8         last_notified_index[0x18];
3102
3103         u8         reserved_at_120[0x8];
3104         u8         last_solicit_index[0x18];
3105
3106         u8         reserved_at_140[0x8];
3107         u8         consumer_counter[0x18];
3108
3109         u8         reserved_at_160[0x8];
3110         u8         producer_counter[0x18];
3111
3112         u8         reserved_at_180[0x40];
3113
3114         u8         dbr_addr[0x40];
3115 };
3116
3117 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3118         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3119         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3120         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3121         u8         reserved_at_0[0x800];
3122 };
3123
3124 struct mlx5_ifc_query_adapter_param_block_bits {
3125         u8         reserved_at_0[0xc0];
3126
3127         u8         reserved_at_c0[0x8];
3128         u8         ieee_vendor_id[0x18];
3129
3130         u8         reserved_at_e0[0x10];
3131         u8         vsd_vendor_id[0x10];
3132
3133         u8         vsd[208][0x8];
3134
3135         u8         vsd_contd_psid[16][0x8];
3136 };
3137
3138 enum {
3139         MLX5_XRQC_STATE_GOOD   = 0x0,
3140         MLX5_XRQC_STATE_ERROR  = 0x1,
3141 };
3142
3143 enum {
3144         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3145         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3146 };
3147
3148 enum {
3149         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3150 };
3151
3152 struct mlx5_ifc_tag_matching_topology_context_bits {
3153         u8         log_matching_list_sz[0x4];
3154         u8         reserved_at_4[0xc];
3155         u8         append_next_index[0x10];
3156
3157         u8         sw_phase_cnt[0x10];
3158         u8         hw_phase_cnt[0x10];
3159
3160         u8         reserved_at_40[0x40];
3161 };
3162
3163 struct mlx5_ifc_xrqc_bits {
3164         u8         state[0x4];
3165         u8         rlkey[0x1];
3166         u8         reserved_at_5[0xf];
3167         u8         topology[0x4];
3168         u8         reserved_at_18[0x4];
3169         u8         offload[0x4];
3170
3171         u8         reserved_at_20[0x8];
3172         u8         user_index[0x18];
3173
3174         u8         reserved_at_40[0x8];
3175         u8         cqn[0x18];
3176
3177         u8         reserved_at_60[0xa0];
3178
3179         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3180
3181         u8         reserved_at_180[0x280];
3182
3183         struct mlx5_ifc_wq_bits wq;
3184 };
3185
3186 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3187         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3188         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3189         u8         reserved_at_0[0x20];
3190 };
3191
3192 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3193         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3194         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3195         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3196         u8         reserved_at_0[0x20];
3197 };
3198
3199 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3200         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3201         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3202         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3203         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3204         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3205         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3206         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3207         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3208         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3209         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3210         u8         reserved_at_0[0x7c0];
3211 };
3212
3213 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3214         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3215         u8         reserved_at_0[0x7c0];
3216 };
3217
3218 union mlx5_ifc_event_auto_bits {
3219         struct mlx5_ifc_comp_event_bits comp_event;
3220         struct mlx5_ifc_dct_events_bits dct_events;
3221         struct mlx5_ifc_qp_events_bits qp_events;
3222         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3223         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3224         struct mlx5_ifc_cq_error_bits cq_error;
3225         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3226         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3227         struct mlx5_ifc_gpio_event_bits gpio_event;
3228         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3229         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3230         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3231         u8         reserved_at_0[0xe0];
3232 };
3233
3234 struct mlx5_ifc_health_buffer_bits {
3235         u8         reserved_at_0[0x100];
3236
3237         u8         assert_existptr[0x20];
3238
3239         u8         assert_callra[0x20];
3240
3241         u8         reserved_at_140[0x40];
3242
3243         u8         fw_version[0x20];
3244
3245         u8         hw_id[0x20];
3246
3247         u8         reserved_at_1c0[0x20];
3248
3249         u8         irisc_index[0x8];
3250         u8         synd[0x8];
3251         u8         ext_synd[0x10];
3252 };
3253
3254 struct mlx5_ifc_register_loopback_control_bits {