include/linux/mfd/tps65910.h

   1 /*
   2  * tps65910.h  --  TI TPS6591x
   3  *
   4  * Copyright 2010-2011 Texas Instruments Inc.
   5  *
   6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
   7  * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
   8  * Author: Arnaud Deconinck <a-deconinck@ti.com>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under  the terms of the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the License, or (at your
  13  *  option) any later version.
  14  *
  15  */
  16
  17 #ifndef __LINUX_MFD_TPS65910_H
  18 #define __LINUX_MFD_TPS65910_H
  19
  20 #include <linux/gpio.h>
  21 #include <linux/regmap.h>
  22
  23 /* TPS chip id list */
  24 #define TPS65910                        0
  25 #define TPS65911                        1
  26
  27 /* TPS regulator type list */
  28 #define REGULATOR_LDO                   0
  29 #define REGULATOR_DCDC                  1
  30
  31 /*
  32  * List of registers for component TPS65910
  33  *
  34  */
  35
  36 #define TPS65910_SECONDS                                0x0
  37 #define TPS65910_MINUTES                                0x1
  38 #define TPS65910_HOURS                                  0x2
  39 #define TPS65910_DAYS                                   0x3
  40 #define TPS65910_MONTHS                                 0x4
  41 #define TPS65910_YEARS                                  0x5
  42 #define TPS65910_WEEKS                                  0x6
  43 #define TPS65910_ALARM_SECONDS                          0x8
  44 #define TPS65910_ALARM_MINUTES                          0x9
  45 #define TPS65910_ALARM_HOURS                            0xA
  46 #define TPS65910_ALARM_DAYS                             0xB
  47 #define TPS65910_ALARM_MONTHS                           0xC
  48 #define TPS65910_ALARM_YEARS                            0xD
  49 #define TPS65910_RTC_CTRL                               0x10
  50 #define TPS65910_RTC_STATUS                             0x11
  51 #define TPS65910_RTC_INTERRUPTS                         0x12
  52 #define TPS65910_RTC_COMP_LSB                           0x13
  53 #define TPS65910_RTC_COMP_MSB                           0x14
  54 #define TPS65910_RTC_RES_PROG                           0x15
  55 #define TPS65910_RTC_RESET_STATUS                       0x16
  56 #define TPS65910_BCK1                                   0x17
  57 #define TPS65910_BCK2                                   0x18
  58 #define TPS65910_BCK3                                   0x19
  59 #define TPS65910_BCK4                                   0x1A
  60 #define TPS65910_BCK5                                   0x1B
  61 #define TPS65910_PUADEN                                 0x1C
  62 #define TPS65910_REF                                    0x1D
  63 #define TPS65910_VRTC                                   0x1E
  64 #define TPS65910_VIO                                    0x20
  65 #define TPS65910_VDD1                                   0x21
  66 #define TPS65910_VDD1_OP                                0x22
  67 #define TPS65910_VDD1_SR                                0x23
  68 #define TPS65910_VDD2                                   0x24
  69 #define TPS65910_VDD2_OP                                0x25
  70 #define TPS65910_VDD2_SR                                0x26
  71 #define TPS65910_VDD3                                   0x27
  72 #define TPS65910_VDIG1                                  0x30
  73 #define TPS65910_VDIG2                                  0x31
  74 #define TPS65910_VAUX1                                  0x32
  75 #define TPS65910_VAUX2                                  0x33
  76 #define TPS65910_VAUX33                                 0x34
  77 #define TPS65910_VMMC                                   0x35
  78 #define TPS65910_VPLL                                   0x36
  79 #define TPS65910_VDAC                                   0x37
  80 #define TPS65910_THERM                                  0x38
  81 #define TPS65910_BBCH                                   0x39
  82 #define TPS65910_DCDCCTRL                               0x3E
  83 #define TPS65910_DEVCTRL                                0x3F
  84 #define TPS65910_DEVCTRL2                               0x40
  85 #define TPS65910_SLEEP_KEEP_LDO_ON                      0x41
  86 #define TPS65910_SLEEP_KEEP_RES_ON                      0x42
  87 #define TPS65910_SLEEP_SET_LDO_OFF                      0x43
  88 #define TPS65910_SLEEP_SET_RES_OFF                      0x44
  89 #define TPS65910_EN1_LDO_ASS                            0x45
  90 #define TPS65910_EN1_SMPS_ASS                           0x46
  91 #define TPS65910_EN2_LDO_ASS                            0x47
  92 #define TPS65910_EN2_SMPS_ASS                           0x48
  93 #define TPS65910_EN3_LDO_ASS                            0x49
  94 #define TPS65910_SPARE                                  0x4A
  95 #define TPS65910_INT_STS                                0x50
  96 #define TPS65910_INT_MSK                                0x51
  97 #define TPS65910_INT_STS2                               0x52
  98 #define TPS65910_INT_MSK2                               0x53
  99 #define TPS65910_INT_STS3                               0x54
 100 #define TPS65910_INT_MSK3                               0x55
 101 #define TPS65910_GPIO0                                  0x60
 102 #define TPS65910_GPIO1                                  0x61
 103 #define TPS65910_GPIO2                                  0x62
 104 #define TPS65910_GPIO3                                  0x63
 105 #define TPS65910_GPIO4                                  0x64
 106 #define TPS65910_GPIO5                                  0x65
 107 #define TPS65910_GPIO6                                  0x66
 108 #define TPS65910_GPIO7                                  0x67
 109 #define TPS65910_GPIO8                                  0x68
 110 #define TPS65910_JTAGVERNUM                             0x80
 111 #define TPS65910_MAX_REGISTER                           0x80
 112
 113 /*
 114  * List of registers specific to TPS65911
 115  */
 116 #define TPS65911_VDDCTRL                                0x27
 117 #define TPS65911_VDDCTRL_OP                             0x28
 118 #define TPS65911_VDDCTRL_SR                             0x29
 119 #define TPS65911_LDO1                                   0x30
 120 #define TPS65911_LDO2                                   0x31
 121 #define TPS65911_LDO5                                   0x32
 122 #define TPS65911_LDO8                                   0x33
 123 #define TPS65911_LDO7                                   0x34
 124 #define TPS65911_LDO6                                   0x35
 125 #define TPS65911_LDO4                                   0x36
 126 #define TPS65911_LDO3                                   0x37
 127 #define TPS65911_VMBCH                                  0x6A
 128 #define TPS65911_VMBCH2                                 0x6B
 129
 130 /*
 131  * List of register bitfields for component TPS65910
 132  *
 133  */
 134
 135 /* RTC_CTRL_REG bitfields */
 136 #define TPS65910_RTC_CTRL_STOP_RTC                      0x01 /*0=stop, 1=run */
 137 #define TPS65910_RTC_CTRL_AUTO_COMP                     0x04
 138 #define TPS65910_RTC_CTRL_GET_TIME                      0x40
 139
 140 /* RTC_STATUS_REG bitfields */
 141 #define TPS65910_RTC_STATUS_ALARM               0x40
 142
 143 /* RTC_INTERRUPTS_REG bitfields */
 144 #define TPS65910_RTC_INTERRUPTS_EVERY           0x03
 145 #define TPS65910_RTC_INTERRUPTS_IT_ALARM        0x08
 146
 147 /*Register BCK1  (0x80) register.RegisterDescription */
 148 #define BCK1_BCKUP_MASK                                 0xFF
 149 #define BCK1_BCKUP_SHIFT                                0
 150
 151
 152 /*Register BCK2  (0x80) register.RegisterDescription */
 153 #define BCK2_BCKUP_MASK                                 0xFF
 154 #define BCK2_BCKUP_SHIFT                                0
 155
 156
 157 /*Register BCK3  (0x80) register.RegisterDescription */
 158 #define BCK3_BCKUP_MASK                                 0xFF
 159 #define BCK3_BCKUP_SHIFT                                0
 160
 161
 162 /*Register BCK4  (0x80) register.RegisterDescription */
 163 #define BCK4_BCKUP_MASK                                 0xFF
 164 #define BCK4_BCKUP_SHIFT                                0
 165
 166
 167 /*Register BCK5  (0x80) register.RegisterDescription */
 168 #define BCK5_BCKUP_MASK                                 0xFF
 169 #define BCK5_BCKUP_SHIFT                                0
 170
 171
 172 /*Register PUADEN  (0x80) register.RegisterDescription */
 173 #define PUADEN_EN3P_MASK                                0x80
 174 #define PUADEN_EN3P_SHIFT                               7
 175 #define PUADEN_I2CCTLP_MASK                             0x40
 176 #define PUADEN_I2CCTLP_SHIFT                            6
 177 #define PUADEN_I2CSRP_MASK                              0x20
 178 #define PUADEN_I2CSRP_SHIFT                             5
 179 #define PUADEN_PWRONP_MASK                              0x10
 180 #define PUADEN_PWRONP_SHIFT                             4
 181 #define PUADEN_SLEEPP_MASK                              0x08
 182 #define PUADEN_SLEEPP_SHIFT                             3
 183 #define PUADEN_PWRHOLDP_MASK                            0x04
 184 #define PUADEN_PWRHOLDP_SHIFT                           2
 185 #define PUADEN_BOOT1P_MASK                              0x02
 186 #define PUADEN_BOOT1P_SHIFT                             1
 187 #define PUADEN_BOOT0P_MASK                              0x01
 188 #define PUADEN_BOOT0P_SHIFT                             0
 189
 190
 191 /*Register REF  (0x80) register.RegisterDescription */
 192 #define REF_VMBCH_SEL_MASK                              0x0C
 193 #define REF_VMBCH_SEL_SHIFT                             2
 194 #define REF_ST_MASK                                     0x03
 195 #define REF_ST_SHIFT                                    0
 196
 197
 198 /*Register VRTC  (0x80) register.RegisterDescription */
 199 #define VRTC_VRTC_OFFMASK_MASK                          0x08
 200 #define VRTC_VRTC_OFFMASK_SHIFT                         3
 201 #define VRTC_ST_MASK                                    0x03
 202 #define VRTC_ST_SHIFT                                   0
 203
 204
 205 /*Register VIO  (0x80) register.RegisterDescription */
 206 #define VIO_ILMAX_MASK                                  0xC0
 207 #define VIO_ILMAX_SHIFT                                 6
 208 #define VIO_SEL_MASK                                    0x0C
 209 #define VIO_SEL_SHIFT                                   2
 210 #define VIO_ST_MASK                                     0x03
 211 #define VIO_ST_SHIFT                                    0
 212
 213
 214 /*Register VDD1  (0x80) register.RegisterDescription */
 215 #define VDD1_VGAIN_SEL_MASK                             0xC0
 216 #define VDD1_VGAIN_SEL_SHIFT                            6
 217 #define VDD1_ILMAX_MASK                                 0x20
 218 #define VDD1_ILMAX_SHIFT                                5
 219 #define VDD1_TSTEP_MASK                                 0x1C
 220 #define VDD1_TSTEP_SHIFT                                2
 221 #define VDD1_ST_MASK                                    0x03
 222 #define VDD1_ST_SHIFT                                   0
 223
 224
 225 /*Register VDD1_OP  (0x80) register.RegisterDescription */
 226 #define VDD1_OP_CMD_MASK                                0x80
 227 #define VDD1_OP_CMD_SHIFT                               7
 228 #define VDD1_OP_SEL_MASK                                0x7F
 229 #define VDD1_OP_SEL_SHIFT                               0
 230
 231
 232 /*Register VDD1_SR  (0x80) register.RegisterDescription */
 233 #define VDD1_SR_SEL_MASK                                0x7F
 234 #define VDD1_SR_SEL_SHIFT                               0
 235
 236
 237 /*Register VDD2  (0x80) register.RegisterDescription */
 238 #define VDD2_VGAIN_SEL_MASK                             0xC0
 239 #define VDD2_VGAIN_SEL_SHIFT                            6
 240 #define VDD2_ILMAX_MASK                                 0x20
 241 #define VDD2_ILMAX_SHIFT                                5
 242 #define VDD2_TSTEP_MASK                                 0x1C
 243 #define VDD2_TSTEP_SHIFT                                2
 244 #define VDD2_ST_MASK                                    0x03
 245 #define VDD2_ST_SHIFT                                   0
 246
 247
 248 /*Register VDD2_OP  (0x80) register.RegisterDescription */
 249 #define VDD2_OP_CMD_MASK                                0x80
 250 #define VDD2_OP_CMD_SHIFT                               7
 251 #define VDD2_OP_SEL_MASK                                0x7F
 252 #define VDD2_OP_SEL_SHIFT                               0
 253
 254 /*Register VDD2_SR  (0x80) register.RegisterDescription */
 255 #define VDD2_SR_SEL_MASK                                0x7F
 256 #define VDD2_SR_SEL_SHIFT                               0
 257
 258
 259 /*Registers VDD1, VDD2 voltage values definitions */
 260 #define VDD1_2_NUM_VOLT_FINE                            73
 261 #define VDD1_2_NUM_VOLT_COARSE                          3
 262 #define VDD1_2_MIN_VOLT                                 6000
 263 #define VDD1_2_OFFSET                                   125
 264
 265
 266 /*Register VDD3  (0x80) register.RegisterDescription */
 267 #define VDD3_CKINEN_MASK                                0x04
 268 #define VDD3_CKINEN_SHIFT                               2
 269 #define VDD3_ST_MASK                                    0x03
 270 #define VDD3_ST_SHIFT                                   0
 271 #define VDDCTRL_MIN_VOLT                                6000
 272 #define VDDCTRL_OFFSET                                  125
 273
 274 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
 275 #define LDO_SEL_MASK                                    0x0C
 276 #define LDO_SEL_SHIFT                                   2
 277 #define LDO_ST_MASK                                     0x03
 278 #define LDO_ST_SHIFT                                    0
 279 #define LDO_ST_ON_BIT                                   0x01
 280 #define LDO_ST_MODE_BIT                                 0x02
 281
 282
 283 /* Registers LDO1 to LDO8 in tps65910 */
 284 #define LDO1_SEL_MASK                                   0xFC
 285 #define LDO3_SEL_MASK                                   0x7C
 286 #define LDO_MIN_VOLT                                    1000
 287 #define LDO_MAX_VOLT                                    3300
 288
 289
 290 /*Register VDIG1  (0x80) register.RegisterDescription */
 291 #define VDIG1_SEL_MASK                                  0x0C
 292 #define VDIG1_SEL_SHIFT                                 2
 293 #define VDIG1_ST_MASK                                   0x03
 294 #define VDIG1_ST_SHIFT                                  0
 295
 296
 297 /*Register VDIG2  (0x80) register.RegisterDescription */
 298 #define VDIG2_SEL_MASK                                  0x0C
 299 #define VDIG2_SEL_SHIFT                                 2
 300 #define VDIG2_ST_MASK                                   0x03
 301 #define VDIG2_ST_SHIFT                                  0
 302
 303
 304 /*Register VAUX1  (0x80) register.RegisterDescription */
 305 #define VAUX1_SEL_MASK                                  0x0C
 306 #define VAUX1_SEL_SHIFT                                 2
 307 #define VAUX1_ST_MASK                                   0x03
 308 #define VAUX1_ST_SHIFT                                  0
 309
 310
 311 /*Register VAUX2  (0x80) register.RegisterDescription */
 312 #define VAUX2_SEL_MASK                                  0x0C
 313 #define VAUX2_SEL_SHIFT                                 2
 314 #define VAUX2_ST_MASK                                   0x03
 315 #define VAUX2_ST_SHIFT                                  0
 316
 317
 318 /*Register VAUX33  (0x80) register.RegisterDescription */
 319 #define VAUX33_SEL_MASK                                 0x0C
 320 #define VAUX33_SEL_SHIFT                                2
 321 #define VAUX33_ST_MASK                                  0x03
 322 #define VAUX33_ST_SHIFT                                 0
 323
 324
 325 /*Register VMMC  (0x80) register.RegisterDescription */
 326 #define VMMC_SEL_MASK                                   0x0C
 327 #define VMMC_SEL_SHIFT                                  2
 328 #define VMMC_ST_MASK                                    0x03
 329 #define VMMC_ST_SHIFT                                   0
 330
 331
 332 /*Register VPLL  (0x80) register.RegisterDescription */
 333 #define VPLL_SEL_MASK                                   0x0C
 334 #define VPLL_SEL_SHIFT                                  2
 335 #define VPLL_ST_MASK                                    0x03
 336 #define VPLL_ST_SHIFT                                   0
 337
 338
 339 /*Register VDAC  (0x80) register.RegisterDescription */
 340 #define VDAC_SEL_MASK                                   0x0C
 341 #define VDAC_SEL_SHIFT                                  2
 342 #define VDAC_ST_MASK                                    0x03
 343 #define VDAC_ST_SHIFT                                   0
 344
 345
 346 /*Register THERM  (0x80) register.RegisterDescription */
 347 #define THERM_THERM_HD_MASK                             0x20
 348 #define THERM_THERM_HD_SHIFT                            5
 349 #define THERM_THERM_TS_MASK                             0x10
 350 #define THERM_THERM_TS_SHIFT                            4
 351 #define THERM_THERM_HDSEL_MASK                          0x0C
 352 #define THERM_THERM_HDSEL_SHIFT                         2
 353 #define THERM_RSVD1_MASK                                0x02
 354 #define THERM_RSVD1_SHIFT                               1
 355 #define THERM_THERM_STATE_MASK                          0x01
 356 #define THERM_THERM_STATE_SHIFT                         0
 357
 358
 359 /*Register BBCH  (0x80) register.RegisterDescription */
 360 #define BBCH_BBSEL_MASK                                 0x06
 361 #define BBCH_BBSEL_SHIFT                                1
 362
 363
 364 /*Register DCDCCTRL  (0x80) register.RegisterDescription */
 365 #define DCDCCTRL_VDD2_PSKIP_MASK                        0x20
 366 #define DCDCCTRL_VDD2_PSKIP_SHIFT                       5
 367 #define DCDCCTRL_VDD1_PSKIP_MASK                        0x10
 368 #define DCDCCTRL_VDD1_PSKIP_SHIFT                       4
 369 #define DCDCCTRL_VIO_PSKIP_MASK                         0x08
 370 #define DCDCCTRL_VIO_PSKIP_SHIFT                        3
 371 #define DCDCCTRL_DCDCCKEXT_MASK                         0x04
 372 #define DCDCCTRL_DCDCCKEXT_SHIFT                        2
 373 #define DCDCCTRL_DCDCCKSYNC_MASK                        0x03
 374 #define DCDCCTRL_DCDCCKSYNC_SHIFT                       0
 375
 376
 377 /*Register DEVCTRL  (0x80) register.RegisterDescription */
 378 #define DEVCTRL_PWR_OFF_MASK                            0x80
 379 #define DEVCTRL_PWR_OFF_SHIFT                           7
 380 #define DEVCTRL_RTC_PWDN_MASK                           0x40
 381 #define DEVCTRL_RTC_PWDN_SHIFT                          6
 382 #define DEVCTRL_CK32K_CTRL_MASK                         0x20
 383 #define DEVCTRL_CK32K_CTRL_SHIFT                        5
 384 #define DEVCTRL_SR_CTL_I2C_SEL_MASK                     0x10
 385 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT                    4
 386 #define DEVCTRL_DEV_OFF_RST_MASK                        0x08
 387 #define DEVCTRL_DEV_OFF_RST_SHIFT                       3
 388 #define DEVCTRL_DEV_ON_MASK                             0x04
 389 #define DEVCTRL_DEV_ON_SHIFT                            2
 390 #define DEVCTRL_DEV_SLP_MASK                            0x02
 391 #define DEVCTRL_DEV_SLP_SHIFT                           1
 392 #define DEVCTRL_DEV_OFF_MASK                            0x01
 393 #define DEVCTRL_DEV_OFF_SHIFT                           0
 394
 395
 396 /*Register DEVCTRL2  (0x80) register.RegisterDescription */
 397 #define DEVCTRL2_TSLOT_LENGTH_MASK                      0x30
 398 #define DEVCTRL2_TSLOT_LENGTH_SHIFT                     4
 399 #define DEVCTRL2_SLEEPSIG_POL_MASK                      0x08
 400 #define DEVCTRL2_SLEEPSIG_POL_SHIFT                     3
 401 #define DEVCTRL2_PWON_LP_OFF_MASK                       0x04
 402 #define DEVCTRL2_PWON_LP_OFF_SHIFT                      2
 403 #define DEVCTRL2_PWON_LP_RST_MASK                       0x02
 404 #define DEVCTRL2_PWON_LP_RST_SHIFT                      1
 405 #define DEVCTRL2_IT_POL_MASK                            0x01
 406 #define DEVCTRL2_IT_POL_SHIFT                           0
 407
 408
 409 /*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
 410 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK              0x80
 411 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT             7
 412 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK              0x40
 413 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT             6
 414 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK            0x20
 415 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT           5
 416 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK             0x10
 417 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT            4
 418 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK             0x08
 419 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT            3
 420 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK             0x04
 421 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT            2
 422 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK             0x02
 423 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT            1
 424 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK              0x01
 425 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT             0
 426
 427
 428 /*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
 429 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK             0x80
 430 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT            7
 431 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK         0x40
 432 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT        6
 433 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK              0x20
 434 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT             5
 435 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK             0x10
 436 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT            4
 437 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK              0x08
 438 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT             3
 439 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK              0x04
 440 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT             2
 441 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK              0x02
 442 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT             1
 443 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK               0x01
 444 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT              0
 445
 446
 447 /*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
 448 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK              0x80
 449 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT             7
 450 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK              0x40
 451 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT             6
 452 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK            0x20
 453 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT           5
 454 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK             0x10
 455 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT            4
 456 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK             0x08
 457 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT            3
 458 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK             0x04
 459 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT            2
 460 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK             0x02
 461 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT            1
 462 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK              0x01
 463 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT             0
 464
 465
 466 /*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
 467 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK             0x80
 468 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT            7
 469 #define SLEEP_SET_RES_OFF_RSVD_MASK                     0x60
 470 #define SLEEP_SET_RES_OFF_RSVD_SHIFT                    5
 471 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK             0x10
 472 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT            4
 473 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK              0x08
 474 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT             3
 475 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK              0x04
 476 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT             2
 477 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK              0x02
 478 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT             1
 479 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK               0x01
 480 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT              0
 481
 482
 483 /*Register EN1_LDO_ASS  (0x80) register.RegisterDescription */
 484 #define EN1_LDO_ASS_VDAC_EN1_MASK                       0x80
 485 #define EN1_LDO_ASS_VDAC_EN1_SHIFT                      7
 486 #define EN1_LDO_ASS_VPLL_EN1_MASK                       0x40
 487 #define EN1_LDO_ASS_VPLL_EN1_SHIFT                      6
 488 #define EN1_LDO_ASS_VAUX33_EN1_MASK                     0x20
 489 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT                    5
 490 #define EN1_LDO_ASS_VAUX2_EN1_MASK                      0x10
 491 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT                     4
 492 #define EN1_LDO_ASS_VAUX1_EN1_MASK                      0x08
 493 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT                     3
 494 #define EN1_LDO_ASS_VDIG2_EN1_MASK                      0x04
 495 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT                     2
 496 #define EN1_LDO_ASS_VDIG1_EN1_MASK                      0x02
 497 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT                     1
 498 #define EN1_LDO_ASS_VMMC_EN1_MASK                       0x01
 499 #define EN1_LDO_ASS_VMMC_EN1_SHIFT                      0
 500
 501
 502 /*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
 503 #define EN1_SMPS_ASS_RSVD_MASK                          0xE0
 504 #define EN1_SMPS_ASS_RSVD_SHIFT                         5
 505 #define EN1_SMPS_ASS_SPARE_EN1_MASK                     0x10
 506 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT                    4
 507 #define EN1_SMPS_ASS_VDD3_EN1_MASK                      0x08
 508 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT                     3
 509 #define EN1_SMPS_ASS_VDD2_EN1_MASK                      0x04
 510 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT                     2
 511 #define EN1_SMPS_ASS_VDD1_EN1_MASK                      0x02
 512 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT                     1
 513 #define EN1_SMPS_ASS_VIO_EN1_MASK                       0x01
 514 #define EN1_SMPS_ASS_VIO_EN1_SHIFT                      0
 515
 516
 517 /*Register EN2_LDO_ASS  (0x80) register.RegisterDescription */
 518 #define EN2_LDO_ASS_VDAC_EN2_MASK                       0x80
 519 #define EN2_LDO_ASS_VDAC_EN2_SHIFT                      7
 520 #define EN2_LDO_ASS_VPLL_EN2_MASK                       0x40
 521 #define EN2_LDO_ASS_VPLL_EN2_SHIFT                      6
 522 #define EN2_LDO_ASS_VAUX33_EN2_MASK                     0x20
 523 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT                    5
 524 #define EN2_LDO_ASS_VAUX2_EN2_MASK                      0x10
 525 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT                     4
 526 #define EN2_LDO_ASS_VAUX1_EN2_MASK                      0x08
 527 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT                     3
 528 #define EN2_LDO_ASS_VDIG2_EN2_MASK                      0x04
 529 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT                     2
 530 #define EN2_LDO_ASS_VDIG1_EN2_MASK                      0x02
 531 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT                     1
 532 #define EN2_LDO_ASS_VMMC_EN2_MASK                       0x01
 533 #define EN2_LDO_ASS_VMMC_EN2_SHIFT                      0
 534
 535
 536 /*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
 537 #define EN2_SMPS_ASS_RSVD_MASK                          0xE0
 538 #define EN2_SMPS_ASS_RSVD_SHIFT                         5
 539 #define EN2_SMPS_ASS_SPARE_EN2_MASK                     0x10
 540 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT                    4
 541 #define EN2_SMPS_ASS_VDD3_EN2_MASK                      0x08
 542 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT                     3
 543 #define EN2_SMPS_ASS_VDD2_EN2_MASK                      0x04
 544 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT                     2
 545 #define EN2_SMPS_ASS_VDD1_EN2_MASK                      0x02
 546 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT                     1
 547 #define EN2_SMPS_ASS_VIO_EN2_MASK                       0x01
 548 #define EN2_SMPS_ASS_VIO_EN2_SHIFT                      0
 549
 550
 551 /*Register EN3_LDO_ASS  (0x80) register.RegisterDescription */
 552 #define EN3_LDO_ASS_VDAC_EN3_MASK                       0x80
 553 #define EN3_LDO_ASS_VDAC_EN3_SHIFT                      7
 554 #define EN3_LDO_ASS_VPLL_EN3_MASK                       0x40
 555 #define EN3_LDO_ASS_VPLL_EN3_SHIFT                      6
 556 #define EN3_LDO_ASS_VAUX33_EN3_MASK                     0x20
 557 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT                    5
 558 #define EN3_LDO_ASS_VAUX2_EN3_MASK                      0x10
 559 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT                     4
 560 #define EN3_LDO_ASS_VAUX1_EN3_MASK                      0x08
 561 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT                     3
 562 #define EN3_LDO_ASS_VDIG2_EN3_MASK                      0x04
 563 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT                     2
 564 #define EN3_LDO_ASS_VDIG1_EN3_MASK                      0x02
 565 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT                     1
 566 #define EN3_LDO_ASS_VMMC_EN3_MASK                       0x01
 567 #define EN3_LDO_ASS_VMMC_EN3_SHIFT                      0
 568
 569
 570 /*Register SPARE  (0x80) register.RegisterDescription */
 571 #define SPARE_SPARE_MASK                                0xFF
 572 #define SPARE_SPARE_SHIFT                               0
 573
 574 #define TPS65910_INT_STS_RTC_PERIOD_IT_MASK                     0x80
 575 #define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT                    7
 576 #define TPS65910_INT_STS_RTC_ALARM_IT_MASK                      0x40
 577 #define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT                     6
 578 #define TPS65910_INT_STS_HOTDIE_IT_MASK                         0x20
 579 #define TPS65910_INT_STS_HOTDIE_IT_SHIFT                        5
 580 #define TPS65910_INT_STS_PWRHOLD_F_IT_MASK                      0x10
 581 #define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT                     4
 582 #define TPS65910_INT_STS_PWRON_LP_IT_MASK                       0x08
 583 #define TPS65910_INT_STS_PWRON_LP_IT_SHIFT                      3
 584 #define TPS65910_INT_STS_PWRON_IT_MASK                          0x04
 585 #define TPS65910_INT_STS_PWRON_IT_SHIFT                         2
 586 #define TPS65910_INT_STS_VMBHI_IT_MASK                          0x02
 587 #define TPS65910_INT_STS_VMBHI_IT_SHIFT                         1
 588 #define TPS65910_INT_STS_VMBDCH_IT_MASK                         0x01
 589 #define TPS65910_INT_STS_VMBDCH_IT_SHIFT                        0
 590
 591 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK                 0x80
 592 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                7
 593 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK                  0x40
 594 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT                 6
 595 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK                     0x20
 596 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT                    5
 597 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK                    0x10
 598 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT                   4
 599 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK                   0x08
 600 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT                  3
 601 #define TPS65910_INT_MSK_PWRON_IT_MSK_MASK                      0x04
 602 #define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT                     2
 603 #define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK                      0x02
 604 #define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT                     1
 605 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK                     0x01
 606 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT                    0
 607
 608 #define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT                      2
 609 #define TPS65910_INT_STS2_GPIO0_F_IT_MASK                       0x02
 610 #define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT                      1
 611 #define TPS65910_INT_STS2_GPIO0_R_IT_MASK                       0x01
 612
 613 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT                  2
 614 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK                   0x02
 615 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT                  1
 616 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK                   0x01
 617
 618 /*Register INT_STS  (0x80) register.RegisterDescription */
 619 #define INT_STS_RTC_PERIOD_IT_MASK                      0x80
 620 #define INT_STS_RTC_PERIOD_IT_SHIFT                     7
 621 #define INT_STS_RTC_ALARM_IT_MASK                       0x40
 622 #define INT_STS_RTC_ALARM_IT_SHIFT                      6
 623 #define INT_STS_HOTDIE_IT_MASK                          0x20
 624 #define INT_STS_HOTDIE_IT_SHIFT                         5
 625 #define INT_STS_PWRHOLD_R_IT_MASK                       0x10
 626 #define INT_STS_PWRHOLD_R_IT_SHIFT                      4
 627 #define INT_STS_PWRON_LP_IT_MASK                        0x08
 628 #define INT_STS_PWRON_LP_IT_SHIFT                       3
 629 #define INT_STS_PWRON_IT_MASK                           0x04
 630 #define INT_STS_PWRON_IT_SHIFT                          2
 631 #define INT_STS_VMBHI_IT_MASK                           0x02
 632 #define INT_STS_VMBHI_IT_SHIFT                          1
 633 #define INT_STS_PWRHOLD_F_IT_MASK                       0x01
 634 #define INT_STS_PWRHOLD_F_IT_SHIFT                      0
 635
 636
 637 /*Register INT_MSK  (0x80) register.RegisterDescription */
 638 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK                  0x80
 639 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                 7
 640 #define INT_MSK_RTC_ALARM_IT_MSK_MASK                   0x40
 641 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
 642 #define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
 643 #define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
 644 #define INT_MSK_PWRHOLD_R_IT_MSK_MASK                   0x10
 645 #define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT                  4
 646 #define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
 647 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
 648 #define INT_MSK_PWRON_IT_MSK_MASK                       0x04
 649 #define INT_MSK_PWRON_IT_MSK_SHIFT                      2
 650 #define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
 651 #define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
 652 #define INT_MSK_PWRHOLD_F_IT_MSK_MASK                   0x01
 653 #define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT                  0
 654
 655
 656 /*Register INT_STS2  (0x80) register.RegisterDescription */
 657 #define INT_STS2_GPIO3_F_IT_MASK                        0x80
 658 #define INT_STS2_GPIO3_F_IT_SHIFT                       7
 659 #define INT_STS2_GPIO3_R_IT_MASK                        0x40
 660 #define INT_STS2_GPIO3_R_IT_SHIFT                       6
 661 #define INT_STS2_GPIO2_F_IT_MASK                        0x20
 662 #define INT_STS2_GPIO2_F_IT_SHIFT                       5
 663 #define INT_STS2_GPIO2_R_IT_MASK                        0x10
 664 #define INT_STS2_GPIO2_R_IT_SHIFT                       4
 665 #define INT_STS2_GPIO1_F_IT_MASK                        0x08
 666 #define INT_STS2_GPIO1_F_IT_SHIFT                       3
 667 #define INT_STS2_GPIO1_R_IT_MASK                        0x04
 668 #define INT_STS2_GPIO1_R_IT_SHIFT                       2
 669 #define INT_STS2_GPIO0_F_IT_MASK                        0x02
 670 #define INT_STS2_GPIO0_F_IT_SHIFT                       1
 671 #define INT_STS2_GPIO0_R_IT_MASK                        0x01
 672 #define INT_STS2_GPIO0_R_IT_SHIFT                       0
 673
 674
 675 /*Register INT_MSK2  (0x80) register.RegisterDescription */
 676 #define INT_MSK2_GPIO3_F_IT_MSK_MASK                    0x80
 677 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT                   7
 678 #define INT_MSK2_GPIO3_R_IT_MSK_MASK                    0x40
 679 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT                   6
 680 #define INT_MSK2_GPIO2_F_IT_MSK_MASK                    0x20
 681 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT                   5
 682 #define INT_MSK2_GPIO2_R_IT_MSK_MASK                    0x10
 683 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT                   4
 684 #define INT_MSK2_GPIO1_F_IT_MSK_MASK                    0x08
 685 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT                   3
 686 #define INT_MSK2_GPIO1_R_IT_MSK_MASK                    0x04
 687 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT                   2
 688 #define INT_MSK2_GPIO0_F_IT_MSK_MASK                    0x02
 689 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT                   1
 690 #define INT_MSK2_GPIO0_R_IT_MSK_MASK                    0x01
 691 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT                   0
 692
 693
 694 /*Register INT_STS3  (0x80) register.RegisterDescription */
 695 #define INT_STS3_PWRDN_IT_MASK                          0x80
 696 #define INT_STS3_PWRDN_IT_SHIFT                         7
 697 #define INT_STS3_VMBCH2_L_IT_MASK                       0x40
 698 #define INT_STS3_VMBCH2_L_IT_SHIFT                      6
 699 #define INT_STS3_VMBCH2_H_IT_MASK                       0x20
 700 #define INT_STS3_VMBCH2_H_IT_SHIFT                      5
 701 #define INT_STS3_WTCHDG_IT_MASK                         0x10
 702 #define INT_STS3_WTCHDG_IT_SHIFT                        4
 703 #define INT_STS3_GPIO5_F_IT_MASK                        0x08
 704 #define INT_STS3_GPIO5_F_IT_SHIFT                       3
 705 #define INT_STS3_GPIO5_R_IT_MASK                        0x04
 706 #define INT_STS3_GPIO5_R_IT_SHIFT                       2
 707 #define INT_STS3_GPIO4_F_IT_MASK                        0x02
 708 #define INT_STS3_GPIO4_F_IT_SHIFT                       1
 709 #define INT_STS3_GPIO4_R_IT_MASK                        0x01
 710 #define INT_STS3_GPIO4_R_IT_SHIFT                       0
 711
 712
 713 /*Register INT_MSK3  (0x80) register.RegisterDescription */
 714 #define INT_MSK3_PWRDN_IT_MSK_MASK                      0x80
 715 #define INT_MSK3_PWRDN_IT_MSK_SHIFT                     7
 716 #define INT_MSK3_VMBCH2_L_IT_MSK_MASK                   0x40
 717 #define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT                  6
 718 #define INT_MSK3_VMBCH2_H_IT_MSK_MASK                   0x20
 719 #define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT                  5
 720 #define INT_MSK3_WTCHDG_IT_MSK_MASK                     0x10
 721 #define INT_MSK3_WTCHDG_IT_MSK_SHIFT                    4
 722 #define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
 723 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
 724 #define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
 725 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT                   2
 726 #define INT_MSK3_GPIO4_F_IT_MSK_MASK                    0x02
 727 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT                   1
 728 #define INT_MSK3_GPIO4_R_IT_MSK_MASK                    0x01
 729 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT                   0
 730
 731
 732 /*Register GPIO  (0x80) register.RegisterDescription */
 733 #define GPIO_SLEEP_MASK                         0x80
 734 #define GPIO_SLEEP_SHIFT                        7
 735 #define GPIO_DEB_MASK                           0x10
 736 #define GPIO_DEB_SHIFT                          4
 737 #define GPIO_PUEN_MASK                          0x08
 738 #define GPIO_PUEN_SHIFT                         3
 739 #define GPIO_CFG_MASK                           0x04
 740 #define GPIO_CFG_SHIFT                          2
 741 #define GPIO_STS_MASK                           0x02
 742 #define GPIO_STS_SHIFT                          1
 743 #define GPIO_SET_MASK                           0x01
 744 #define GPIO_SET_SHIFT                          0
 745
 746
 747 /*Register JTAGVERNUM  (0x80) register.RegisterDescription */
 748 #define JTAGVERNUM_VERNUM_MASK                          0x0F
 749 #define JTAGVERNUM_VERNUM_SHIFT                         0
 750
 751
 752 /* Register VDDCTRL (0x27) bit definitions */
 753 #define VDDCTRL_ST_MASK                                  0x03
 754 #define VDDCTRL_ST_SHIFT                                 0
 755
 756
 757 /*Register VDDCTRL_OP  (0x28) bit definitios */
 758 #define VDDCTRL_OP_CMD_MASK                              0x80
 759 #define VDDCTRL_OP_CMD_SHIFT                             7
 760 #define VDDCTRL_OP_SEL_MASK                              0x7F
 761 #define VDDCTRL_OP_SEL_SHIFT                             0
 762
 763
 764 /*Register VDDCTRL_SR  (0x29) bit definitions */
 765 #define VDDCTRL_SR_SEL_MASK                              0x7F
 766 #define VDDCTRL_SR_SEL_SHIFT                             0
 767
 768
 769 /* IRQ Definitions */
 770 #define TPS65910_IRQ_VBAT_VMBDCH                        0
 771 #define TPS65910_IRQ_VBAT_VMHI                          1
 772 #define TPS65910_IRQ_PWRON                              2
 773 #define TPS65910_IRQ_PWRON_LP                           3
 774 #define TPS65910_IRQ_PWRHOLD                            4
 775 #define TPS65910_IRQ_HOTDIE                             5
 776 #define TPS65910_IRQ_RTC_ALARM                          6
 777 #define TPS65910_IRQ_RTC_PERIOD                         7
 778 #define TPS65910_IRQ_GPIO_R                             8
 779 #define TPS65910_IRQ_GPIO_F                             9
 780 #define TPS65910_NUM_IRQ                                10
 781
 782 #define TPS65911_IRQ_PWRHOLD_F                          0
 783 #define TPS65911_IRQ_VBAT_VMHI                          1
 784 #define TPS65911_IRQ_PWRON                              2
 785 #define TPS65911_IRQ_PWRON_LP                           3
 786 #define TPS65911_IRQ_PWRHOLD_R                          4
 787 #define TPS65911_IRQ_HOTDIE                             5
 788 #define TPS65911_IRQ_RTC_ALARM                          6
 789 #define TPS65911_IRQ_RTC_PERIOD                         7
 790 #define TPS65911_IRQ_GPIO0_R                            8
 791 #define TPS65911_IRQ_GPIO0_F                            9
 792 #define TPS65911_IRQ_GPIO1_R                            10
 793 #define TPS65911_IRQ_GPIO1_F                            11
 794 #define TPS65911_IRQ_GPIO2_R                            12
 795 #define TPS65911_IRQ_GPIO2_F                            13
 796 #define TPS65911_IRQ_GPIO3_R                            14
 797 #define TPS65911_IRQ_GPIO3_F                            15
 798 #define TPS65911_IRQ_GPIO4_R                            16
 799 #define TPS65911_IRQ_GPIO4_F                            17
 800 #define TPS65911_IRQ_GPIO5_R                            18
 801 #define TPS65911_IRQ_GPIO5_F                            19
 802 #define TPS65911_IRQ_WTCHDG                             20
 803 #define TPS65911_IRQ_VMBCH2_H                           21
 804 #define TPS65911_IRQ_VMBCH2_L                           22
 805 #define TPS65911_IRQ_PWRDN                              23
 806
 807 #define TPS65911_NUM_IRQ                                24
 808
 809 /* GPIO Register Definitions */
 810 #define TPS65910_GPIO_DEB                               BIT(2)
 811 #define TPS65910_GPIO_PUEN                              BIT(3)
 812 #define TPS65910_GPIO_CFG                               BIT(2)
 813 #define TPS65910_GPIO_STS                               BIT(1)
 814 #define TPS65910_GPIO_SET                               BIT(0)
 815
 816 /* Max number of TPS65910/11 GPIOs */
 817 #define TPS65910_NUM_GPIO                               6
 818 #define TPS65911_NUM_GPIO                               9
 819 #define TPS6591X_MAX_NUM_GPIO                           9
 820
 821 /* Regulator Index Definitions */
 822 #define TPS65910_REG_VRTC                               0
 823 #define TPS65910_REG_VIO                                1
 824 #define TPS65910_REG_VDD1                               2
 825 #define TPS65910_REG_VDD2                               3
 826 #define TPS65910_REG_VDD3                               4
 827 #define TPS65910_REG_VDIG1                              5
 828 #define TPS65910_REG_VDIG2                              6
 829 #define TPS65910_REG_VPLL                               7
 830 #define TPS65910_REG_VDAC                               8
 831 #define TPS65910_REG_VAUX1                              9
 832 #define TPS65910_REG_VAUX2                              10
 833 #define TPS65910_REG_VAUX33                             11
 834 #define TPS65910_REG_VMMC                               12
 835 #define TPS65910_REG_VBB                                13
 836
 837 #define TPS65911_REG_VDDCTRL                            4
 838 #define TPS65911_REG_LDO1                               5
 839 #define TPS65911_REG_LDO2                               6
 840 #define TPS65911_REG_LDO3                               7
 841 #define TPS65911_REG_LDO4                               8
 842 #define TPS65911_REG_LDO5                               9
 843 #define TPS65911_REG_LDO6                               10
 844 #define TPS65911_REG_LDO7                               11
 845 #define TPS65911_REG_LDO8                               12
 846
 847 /* Max number of TPS65910/11 regulators */
 848 #define TPS65910_NUM_REGS                               14
 849
 850 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
 851 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1            0x1
 852 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2            0x2
 853 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3            0x4
 854 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP          0x8
 855
 856 /*
 857  * Sleep keepon data: Maintains the state in sleep mode
 858  * @therm_keepon: Keep on the thermal monitoring in sleep state.
 859  * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state.
 860  * @i2chs_keepon: Keep on high speed internal clock in sleep state.
 861  */
 862 struct tps65910_sleep_keepon_data {
 863         unsigned therm_keepon:1;
 864         unsigned clkout32k_keepon:1;
 865         unsigned i2chs_keepon:1;
 866 };
 867
 868 /**
 869  * struct tps65910_board
 870  * Board platform data may be used to initialize regulators.
 871  */
 872
 873 struct tps65910_board {
 874         int gpio_base;
 875         int irq;
 876         int irq_base;
 877         int vmbch_threshold;
 878         int vmbch2_threshold;
 879         bool en_ck32k_xtal;
 880         bool en_dev_slp;
 881         bool pm_off;
 882         struct tps65910_sleep_keepon_data *slp_keepon;
 883         bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
 884         unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
 885         struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
 886 };
 887
 888 /**
 889  * struct tps65910 - tps65910 sub-driver chip access routines
 890  */
 891
 892 struct tps65910 {
 893         struct device *dev;
 894         struct i2c_client *i2c_client;
 895         struct regmap *regmap;
 896         unsigned long id;
 897
 898         /* Client devices */
 899         struct tps65910_pmic *pmic;
 900         struct tps65910_rtc *rtc;
 901         struct tps65910_power *power;
 902
 903         /* Device node parsed board data */
 904         struct tps65910_board *of_plat_data;
 905
 906         /* IRQ Handling */
 907         int chip_irq;
 908         struct regmap_irq_chip_data *irq_data;
 909 };
 910
 911 struct tps65910_platform_data {
 912         int irq;
 913         int irq_base;
 914 };
 915
 916 static inline int tps65910_chip_id(struct tps65910 *tps65910)
 917 {
 918         return tps65910->id;
 919 }
 920
 921 static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg,
 922                 unsigned int *val)
 923 {
 924         return regmap_read(tps65910->regmap, reg, val);
 925 }
 926
 927 static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg,
 928                 unsigned int val)
 929 {
 930         return regmap_write(tps65910->regmap, reg, val);
 931 }
 932
 933 static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg,
 934                 u8 mask)
 935 {
 936         return regmap_update_bits(tps65910->regmap, reg, mask, mask);
 937 }
 938
 939 static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg,
 940                 u8 mask)
 941 {
 942         return regmap_update_bits(tps65910->regmap, reg, mask, 0);
 943 }
 944
 945 static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg,
 946                                            u8 mask, u8 val)
 947 {
 948         return regmap_update_bits(tps65910->regmap, reg, mask, val);
 949 }
 950
 951 static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq)
 952 {
 953         return regmap_irq_get_virq(tps65910->irq_data, irq);
 954 }
 955
 956 #endif /*  __LINUX_MFD_TPS65910_H */