Merge tag 'mfd-next-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
[sfrench/cifs-2.6.git] / include / linux / mfd / rtsx_pci.h
1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  *   Wei WANG <wei_wang@realsil.com.cn>
20  */
21
22 #ifndef __RTSX_PCI_H
23 #define __RTSX_PCI_H
24
25 #include <linux/sched.h>
26 #include <linux/pci.h>
27 #include <linux/mfd/rtsx_common.h>
28
29 #define MAX_RW_REG_CNT                  1024
30
31 #define RTSX_HCBAR                      0x00
32 #define RTSX_HCBCTLR                    0x04
33 #define   STOP_CMD                      (0x01 << 28)
34 #define   READ_REG_CMD                  0
35 #define   WRITE_REG_CMD                 1
36 #define   CHECK_REG_CMD                 2
37
38 #define RTSX_HDBAR                      0x08
39 #define   SG_INT                        0x04
40 #define   SG_END                        0x02
41 #define   SG_VALID                      0x01
42 #define   SG_NO_OP                      0x00
43 #define   SG_TRANS_DATA                 (0x02 << 4)
44 #define   SG_LINK_DESC                  (0x03 << 4)
45 #define RTSX_HDBCTLR                    0x0C
46 #define   SDMA_MODE                     0x00
47 #define   ADMA_MODE                     (0x02 << 26)
48 #define   STOP_DMA                      (0x01 << 28)
49 #define   TRIG_DMA                      (0x01 << 31)
50
51 #define RTSX_HAIMR                      0x10
52 #define   HAIMR_TRANS_START             (0x01 << 31)
53 #define   HAIMR_READ                    0x00
54 #define   HAIMR_WRITE                   (0x01 << 30)
55 #define   HAIMR_READ_START              (HAIMR_TRANS_START | HAIMR_READ)
56 #define   HAIMR_WRITE_START             (HAIMR_TRANS_START | HAIMR_WRITE)
57 #define   HAIMR_TRANS_END                       (HAIMR_TRANS_START)
58
59 #define RTSX_BIPR                       0x14
60 #define   CMD_DONE_INT                  (1 << 31)
61 #define   DATA_DONE_INT                 (1 << 30)
62 #define   TRANS_OK_INT                  (1 << 29)
63 #define   TRANS_FAIL_INT                (1 << 28)
64 #define   XD_INT                        (1 << 27)
65 #define   MS_INT                        (1 << 26)
66 #define   SD_INT                        (1 << 25)
67 #define   GPIO0_INT                     (1 << 24)
68 #define   OC_INT                        (1 << 23)
69 #define   SD_WRITE_PROTECT              (1 << 19)
70 #define   XD_EXIST                      (1 << 18)
71 #define   MS_EXIST                      (1 << 17)
72 #define   SD_EXIST                      (1 << 16)
73 #define   DELINK_INT                    GPIO0_INT
74 #define   MS_OC_INT                     (1 << 23)
75 #define   SD_OC_INT                     (1 << 22)
76
77 #define CARD_INT                (XD_INT | MS_INT | SD_INT)
78 #define NEED_COMPLETE_INT       (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
79 #define RTSX_INT                (CMD_DONE_INT | NEED_COMPLETE_INT | \
80                                         CARD_INT | GPIO0_INT | OC_INT)
81 #define CARD_EXIST              (XD_EXIST | MS_EXIST | SD_EXIST)
82
83 #define RTSX_BIER                       0x18
84 #define   CMD_DONE_INT_EN               (1 << 31)
85 #define   DATA_DONE_INT_EN              (1 << 30)
86 #define   TRANS_OK_INT_EN               (1 << 29)
87 #define   TRANS_FAIL_INT_EN             (1 << 28)
88 #define   XD_INT_EN                     (1 << 27)
89 #define   MS_INT_EN                     (1 << 26)
90 #define   SD_INT_EN                     (1 << 25)
91 #define   GPIO0_INT_EN                  (1 << 24)
92 #define   OC_INT_EN                     (1 << 23)
93 #define   DELINK_INT_EN                 GPIO0_INT_EN
94 #define   MS_OC_INT_EN                  (1 << 23)
95 #define   SD_OC_INT_EN                  (1 << 22)
96
97
98 /*
99  * macros for easy use
100  */
101 #define rtsx_pci_writel(pcr, reg, value) \
102         iowrite32(value, (pcr)->remap_addr + reg)
103 #define rtsx_pci_readl(pcr, reg) \
104         ioread32((pcr)->remap_addr + reg)
105 #define rtsx_pci_writew(pcr, reg, value) \
106         iowrite16(value, (pcr)->remap_addr + reg)
107 #define rtsx_pci_readw(pcr, reg) \
108         ioread16((pcr)->remap_addr + reg)
109 #define rtsx_pci_writeb(pcr, reg, value) \
110         iowrite8(value, (pcr)->remap_addr + reg)
111 #define rtsx_pci_readb(pcr, reg) \
112         ioread8((pcr)->remap_addr + reg)
113
114 #define rtsx_pci_read_config_byte(pcr, where, val) \
115         pci_read_config_byte((pcr)->pci, where, val)
116
117 #define rtsx_pci_write_config_byte(pcr, where, val) \
118         pci_write_config_byte((pcr)->pci, where, val)
119
120 #define rtsx_pci_read_config_dword(pcr, where, val) \
121         pci_read_config_dword((pcr)->pci, where, val)
122
123 #define rtsx_pci_write_config_dword(pcr, where, val) \
124         pci_write_config_dword((pcr)->pci, where, val)
125
126 #define STATE_TRANS_NONE                0
127 #define STATE_TRANS_CMD                 1
128 #define STATE_TRANS_BUF                 2
129 #define STATE_TRANS_SG                  3
130
131 #define TRANS_NOT_READY                 0
132 #define TRANS_RESULT_OK                 1
133 #define TRANS_RESULT_FAIL               2
134 #define TRANS_NO_DEVICE                 3
135
136 #define RTSX_RESV_BUF_LEN               4096
137 #define HOST_CMDS_BUF_LEN               1024
138 #define HOST_SG_TBL_BUF_LEN             (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
139 #define HOST_SG_TBL_ITEMS               (HOST_SG_TBL_BUF_LEN / 8)
140 #define MAX_SG_ITEM_LEN                 0x80000
141 #define HOST_TO_DEVICE                  0
142 #define DEVICE_TO_HOST                  1
143
144 #define OUTPUT_3V3                      0
145 #define OUTPUT_1V8                      1
146
147 #define RTSX_PHASE_MAX                  32
148 #define RX_TUNING_CNT                   3
149
150 #define MS_CFG                          0xFD40
151 #define   SAMPLE_TIME_RISING            0x00
152 #define   SAMPLE_TIME_FALLING           0x80
153 #define   PUSH_TIME_DEFAULT             0x00
154 #define   PUSH_TIME_ODD                 0x40
155 #define   NO_EXTEND_TOGGLE              0x00
156 #define   EXTEND_TOGGLE_CHK             0x20
157 #define   MS_BUS_WIDTH_1                0x00
158 #define   MS_BUS_WIDTH_4                0x10
159 #define   MS_BUS_WIDTH_8                0x18
160 #define   MS_2K_SECTOR_MODE             0x04
161 #define   MS_512_SECTOR_MODE            0x00
162 #define   MS_TOGGLE_TIMEOUT_EN          0x00
163 #define   MS_TOGGLE_TIMEOUT_DISEN       0x01
164 #define MS_NO_CHECK_INT                 0x02
165 #define MS_TPC                          0xFD41
166 #define MS_TRANS_CFG                    0xFD42
167 #define   WAIT_INT                      0x80
168 #define   NO_WAIT_INT                   0x00
169 #define   NO_AUTO_READ_INT_REG          0x00
170 #define   AUTO_READ_INT_REG             0x40
171 #define   MS_CRC16_ERR                  0x20
172 #define   MS_RDY_TIMEOUT                0x10
173 #define   MS_INT_CMDNK                  0x08
174 #define   MS_INT_BREQ                   0x04
175 #define   MS_INT_ERR                    0x02
176 #define   MS_INT_CED                    0x01
177 #define MS_TRANSFER                     0xFD43
178 #define   MS_TRANSFER_START             0x80
179 #define   MS_TRANSFER_END               0x40
180 #define   MS_TRANSFER_ERR               0x20
181 #define   MS_BS_STATE                   0x10
182 #define   MS_TM_READ_BYTES              0x00
183 #define   MS_TM_NORMAL_READ             0x01
184 #define   MS_TM_WRITE_BYTES             0x04
185 #define   MS_TM_NORMAL_WRITE            0x05
186 #define   MS_TM_AUTO_READ               0x08
187 #define   MS_TM_AUTO_WRITE              0x0C
188 #define MS_INT_REG                      0xFD44
189 #define MS_BYTE_CNT                     0xFD45
190 #define MS_SECTOR_CNT_L                 0xFD46
191 #define MS_SECTOR_CNT_H                 0xFD47
192 #define MS_DBUS_H                       0xFD48
193
194 #define SD_CFG1                         0xFDA0
195 #define   SD_CLK_DIVIDE_0               0x00
196 #define   SD_CLK_DIVIDE_256             0xC0
197 #define   SD_CLK_DIVIDE_128             0x80
198 #define   SD_BUS_WIDTH_1BIT             0x00
199 #define   SD_BUS_WIDTH_4BIT             0x01
200 #define   SD_BUS_WIDTH_8BIT             0x02
201 #define   SD_ASYNC_FIFO_NOT_RST         0x10
202 #define   SD_20_MODE                    0x00
203 #define   SD_DDR_MODE                   0x04
204 #define   SD_30_MODE                    0x08
205 #define   SD_CLK_DIVIDE_MASK            0xC0
206 #define SD_CFG2                         0xFDA1
207 #define   SD_CALCULATE_CRC7             0x00
208 #define   SD_NO_CALCULATE_CRC7          0x80
209 #define   SD_CHECK_CRC16                0x00
210 #define   SD_NO_CHECK_CRC16             0x40
211 #define   SD_NO_CHECK_WAIT_CRC_TO       0x20
212 #define   SD_WAIT_BUSY_END              0x08
213 #define   SD_NO_WAIT_BUSY_END           0x00
214 #define   SD_CHECK_CRC7                 0x00
215 #define   SD_NO_CHECK_CRC7              0x04
216 #define   SD_RSP_LEN_0                  0x00
217 #define   SD_RSP_LEN_6                  0x01
218 #define   SD_RSP_LEN_17                 0x02
219 #define   SD_RSP_TYPE_R0                0x04
220 #define   SD_RSP_TYPE_R1                0x01
221 #define   SD_RSP_TYPE_R1b               0x09
222 #define   SD_RSP_TYPE_R2                0x02
223 #define   SD_RSP_TYPE_R3                0x05
224 #define   SD_RSP_TYPE_R4                0x05
225 #define   SD_RSP_TYPE_R5                0x01
226 #define   SD_RSP_TYPE_R6                0x01
227 #define   SD_RSP_TYPE_R7                0x01
228 #define SD_CFG3                         0xFDA2
229 #define   SD_RSP_80CLK_TIMEOUT_EN       0x01
230
231 #define SD_STAT1                        0xFDA3
232 #define   SD_CRC7_ERR                   0x80
233 #define   SD_CRC16_ERR                  0x40
234 #define   SD_CRC_WRITE_ERR              0x20
235 #define   SD_CRC_WRITE_ERR_MASK         0x1C
236 #define   GET_CRC_TIME_OUT              0x02
237 #define   SD_TUNING_COMPARE_ERR         0x01
238 #define SD_STAT2                        0xFDA4
239 #define   SD_RSP_80CLK_TIMEOUT          0x01
240
241 #define SD_BUS_STAT                     0xFDA5
242 #define   SD_CLK_TOGGLE_EN              0x80
243 #define   SD_CLK_FORCE_STOP             0x40
244 #define   SD_DAT3_STATUS                0x10
245 #define   SD_DAT2_STATUS                0x08
246 #define   SD_DAT1_STATUS                0x04
247 #define   SD_DAT0_STATUS                0x02
248 #define   SD_CMD_STATUS                 0x01
249 #define SD_PAD_CTL                      0xFDA6
250 #define   SD_IO_USING_1V8               0x80
251 #define   SD_IO_USING_3V3               0x7F
252 #define   TYPE_A_DRIVING                0x00
253 #define   TYPE_B_DRIVING                0x01
254 #define   TYPE_C_DRIVING                0x02
255 #define   TYPE_D_DRIVING                0x03
256 #define SD_SAMPLE_POINT_CTL             0xFDA7
257 #define   DDR_FIX_RX_DAT                0x00
258 #define   DDR_VAR_RX_DAT                0x80
259 #define   DDR_FIX_RX_DAT_EDGE           0x00
260 #define   DDR_FIX_RX_DAT_14_DELAY       0x40
261 #define   DDR_FIX_RX_CMD                0x00
262 #define   DDR_VAR_RX_CMD                0x20
263 #define   DDR_FIX_RX_CMD_POS_EDGE       0x00
264 #define   DDR_FIX_RX_CMD_14_DELAY       0x10
265 #define   SD20_RX_POS_EDGE              0x00
266 #define   SD20_RX_14_DELAY              0x08
267 #define SD20_RX_SEL_MASK                0x08
268 #define SD_PUSH_POINT_CTL               0xFDA8
269 #define   DDR_FIX_TX_CMD_DAT            0x00
270 #define   DDR_VAR_TX_CMD_DAT            0x80
271 #define   DDR_FIX_TX_DAT_14_TSU         0x00
272 #define   DDR_FIX_TX_DAT_12_TSU         0x40
273 #define   DDR_FIX_TX_CMD_NEG_EDGE       0x00
274 #define   DDR_FIX_TX_CMD_14_AHEAD       0x20
275 #define   SD20_TX_NEG_EDGE              0x00
276 #define   SD20_TX_14_AHEAD              0x10
277 #define   SD20_TX_SEL_MASK              0x10
278 #define   DDR_VAR_SDCLK_POL_SWAP        0x01
279 #define SD_CMD0                         0xFDA9
280 #define   SD_CMD_START                  0x40
281 #define SD_CMD1                         0xFDAA
282 #define SD_CMD2                         0xFDAB
283 #define SD_CMD3                         0xFDAC
284 #define SD_CMD4                         0xFDAD
285 #define SD_CMD5                         0xFDAE
286 #define SD_BYTE_CNT_L                   0xFDAF
287 #define SD_BYTE_CNT_H                   0xFDB0
288 #define SD_BLOCK_CNT_L                  0xFDB1
289 #define SD_BLOCK_CNT_H                  0xFDB2
290 #define SD_TRANSFER                     0xFDB3
291 #define   SD_TRANSFER_START             0x80
292 #define   SD_TRANSFER_END               0x40
293 #define   SD_STAT_IDLE                  0x20
294 #define   SD_TRANSFER_ERR               0x10
295 #define   SD_TM_NORMAL_WRITE            0x00
296 #define   SD_TM_AUTO_WRITE_3            0x01
297 #define   SD_TM_AUTO_WRITE_4            0x02
298 #define   SD_TM_AUTO_READ_3             0x05
299 #define   SD_TM_AUTO_READ_4             0x06
300 #define   SD_TM_CMD_RSP                 0x08
301 #define   SD_TM_AUTO_WRITE_1            0x09
302 #define   SD_TM_AUTO_WRITE_2            0x0A
303 #define   SD_TM_NORMAL_READ             0x0C
304 #define   SD_TM_AUTO_READ_1             0x0D
305 #define   SD_TM_AUTO_READ_2             0x0E
306 #define   SD_TM_AUTO_TUNING             0x0F
307 #define SD_CMD_STATE                    0xFDB5
308 #define   SD_CMD_IDLE                   0x80
309
310 #define SD_DATA_STATE                   0xFDB6
311 #define   SD_DATA_IDLE                  0x80
312
313 #define SRCTL                           0xFC13
314
315 #define DCM_DRP_CTL                     0xFC23
316 #define   DCM_RESET                     0x08
317 #define   DCM_LOCKED                    0x04
318 #define   DCM_208M                      0x00
319 #define   DCM_TX                        0x01
320 #define   DCM_RX                        0x02
321 #define DCM_DRP_TRIG                    0xFC24
322 #define   DRP_START                     0x80
323 #define   DRP_DONE                      0x40
324 #define DCM_DRP_CFG                     0xFC25
325 #define   DRP_WRITE                     0x80
326 #define   DRP_READ                      0x00
327 #define   DCM_WRITE_ADDRESS_50          0x50
328 #define   DCM_WRITE_ADDRESS_51          0x51
329 #define   DCM_READ_ADDRESS_00           0x00
330 #define   DCM_READ_ADDRESS_51           0x51
331 #define DCM_DRP_WR_DATA_L               0xFC26
332 #define DCM_DRP_WR_DATA_H               0xFC27
333 #define DCM_DRP_RD_DATA_L               0xFC28
334 #define DCM_DRP_RD_DATA_H               0xFC29
335 #define SD_VPCLK0_CTL                   0xFC2A
336 #define SD_VPCLK1_CTL                   0xFC2B
337 #define   PHASE_SELECT_MASK             0x1F
338 #define SD_DCMPS0_CTL                   0xFC2C
339 #define SD_DCMPS1_CTL                   0xFC2D
340 #define SD_VPTX_CTL                     SD_VPCLK0_CTL
341 #define SD_VPRX_CTL                     SD_VPCLK1_CTL
342 #define   PHASE_CHANGE                  0x80
343 #define   PHASE_NOT_RESET               0x40
344 #define SD_DCMPS_TX_CTL                 SD_DCMPS0_CTL
345 #define SD_DCMPS_RX_CTL                 SD_DCMPS1_CTL
346 #define   DCMPS_CHANGE                  0x80
347 #define   DCMPS_CHANGE_DONE             0x40
348 #define   DCMPS_ERROR                   0x20
349 #define   DCMPS_CURRENT_PHASE           0x1F
350 #define CARD_CLK_SOURCE                 0xFC2E
351 #define   CRC_FIX_CLK                   (0x00 << 0)
352 #define   CRC_VAR_CLK0                  (0x01 << 0)
353 #define   CRC_VAR_CLK1                  (0x02 << 0)
354 #define   SD30_FIX_CLK                  (0x00 << 2)
355 #define   SD30_VAR_CLK0                 (0x01 << 2)
356 #define   SD30_VAR_CLK1                 (0x02 << 2)
357 #define   SAMPLE_FIX_CLK                (0x00 << 4)
358 #define   SAMPLE_VAR_CLK0               (0x01 << 4)
359 #define   SAMPLE_VAR_CLK1               (0x02 << 4)
360 #define CARD_PWR_CTL                    0xFD50
361 #define   PMOS_STRG_MASK                0x10
362 #define   PMOS_STRG_800mA               0x10
363 #define   PMOS_STRG_400mA               0x00
364 #define   SD_POWER_OFF                  0x03
365 #define   SD_PARTIAL_POWER_ON           0x01
366 #define   SD_POWER_ON                   0x00
367 #define   SD_POWER_MASK                 0x03
368 #define   MS_POWER_OFF                  0x0C
369 #define   MS_PARTIAL_POWER_ON           0x04
370 #define   MS_POWER_ON                   0x00
371 #define   MS_POWER_MASK                 0x0C
372 #define   BPP_POWER_OFF                 0x0F
373 #define   BPP_POWER_5_PERCENT_ON        0x0E
374 #define   BPP_POWER_10_PERCENT_ON       0x0C
375 #define   BPP_POWER_15_PERCENT_ON       0x08
376 #define   BPP_POWER_ON                  0x00
377 #define   BPP_POWER_MASK                0x0F
378 #define   SD_VCC_PARTIAL_POWER_ON       0x02
379 #define   SD_VCC_POWER_ON               0x00
380 #define CARD_CLK_SWITCH                 0xFD51
381 #define RTL8411B_PACKAGE_MODE           0xFD51
382 #define CARD_SHARE_MODE                 0xFD52
383 #define   CARD_SHARE_MASK               0x0F
384 #define   CARD_SHARE_MULTI_LUN          0x00
385 #define   CARD_SHARE_NORMAL             0x00
386 #define   CARD_SHARE_48_SD              0x04
387 #define   CARD_SHARE_48_MS              0x08
388 #define   CARD_SHARE_BAROSSA_SD         0x01
389 #define   CARD_SHARE_BAROSSA_MS         0x02
390 #define CARD_DRIVE_SEL                  0xFD53
391 #define   MS_DRIVE_8mA                  (0x01 << 6)
392 #define   MMC_DRIVE_8mA                 (0x01 << 4)
393 #define   XD_DRIVE_8mA                  (0x01 << 2)
394 #define   GPIO_DRIVE_8mA                0x01
395 #define RTS5209_CARD_DRIVE_DEFAULT      (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
396                                         XD_DRIVE_8mA | GPIO_DRIVE_8mA)
397 #define RTL8411_CARD_DRIVE_DEFAULT      (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
398                                         XD_DRIVE_8mA)
399 #define RTSX_CARD_DRIVE_DEFAULT         (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
400
401 #define CARD_STOP                       0xFD54
402 #define   SPI_STOP                      0x01
403 #define   XD_STOP                       0x02
404 #define   SD_STOP                       0x04
405 #define   MS_STOP                       0x08
406 #define   SPI_CLR_ERR                   0x10
407 #define   XD_CLR_ERR                    0x20
408 #define   SD_CLR_ERR                    0x40
409 #define   MS_CLR_ERR                    0x80
410 #define CARD_OE                         0xFD55
411 #define   SD_OUTPUT_EN                  0x04
412 #define   MS_OUTPUT_EN                  0x08
413 #define CARD_AUTO_BLINK                 0xFD56
414 #define CARD_GPIO_DIR                   0xFD57
415 #define CARD_GPIO                       0xFD58
416 #define CARD_DATA_SOURCE                0xFD5B
417 #define   PINGPONG_BUFFER               0x01
418 #define   RING_BUFFER                   0x00
419 #define SD30_CLK_DRIVE_SEL              0xFD5A
420 #define   DRIVER_TYPE_A                 0x05
421 #define   DRIVER_TYPE_B                 0x03
422 #define   DRIVER_TYPE_C                 0x02
423 #define   DRIVER_TYPE_D                 0x01
424 #define CARD_SELECT                     0xFD5C
425 #define   SD_MOD_SEL                    2
426 #define   MS_MOD_SEL                    3
427 #define SD30_DRIVE_SEL                  0xFD5E
428 #define   CFG_DRIVER_TYPE_A             0x02
429 #define   CFG_DRIVER_TYPE_B             0x03
430 #define   CFG_DRIVER_TYPE_C             0x01
431 #define   CFG_DRIVER_TYPE_D             0x00
432 #define SD30_CMD_DRIVE_SEL              0xFD5E
433 #define SD30_DAT_DRIVE_SEL              0xFD5F
434 #define CARD_CLK_EN                     0xFD69
435 #define   SD_CLK_EN                     0x04
436 #define   MS_CLK_EN                     0x08
437 #define SDIO_CTRL                       0xFD6B
438 #define CD_PAD_CTL                      0xFD73
439 #define   CD_DISABLE_MASK               0x07
440 #define   MS_CD_DISABLE                 0x04
441 #define   SD_CD_DISABLE                 0x02
442 #define   XD_CD_DISABLE                 0x01
443 #define   CD_DISABLE                    0x07
444 #define   CD_ENABLE                     0x00
445 #define   MS_CD_EN_ONLY                 0x03
446 #define   SD_CD_EN_ONLY                 0x05
447 #define   XD_CD_EN_ONLY                 0x06
448 #define   FORCE_CD_LOW_MASK             0x38
449 #define   FORCE_CD_XD_LOW               0x08
450 #define   FORCE_CD_SD_LOW               0x10
451 #define   FORCE_CD_MS_LOW               0x20
452 #define   CD_AUTO_DISABLE               0x40
453 #define FPDCTL                          0xFC00
454 #define   SSC_POWER_DOWN                0x01
455 #define   SD_OC_POWER_DOWN              0x02
456 #define   ALL_POWER_DOWN                0x07
457 #define   OC_POWER_DOWN                 0x06
458 #define PDINFO                          0xFC01
459
460 #define CLK_CTL                         0xFC02
461 #define   CHANGE_CLK                    0x01
462 #define   CLK_LOW_FREQ                  0x01
463
464 #define CLK_DIV                         0xFC03
465 #define   CLK_DIV_1                     0x01
466 #define   CLK_DIV_2                     0x02
467 #define   CLK_DIV_4                     0x03
468 #define   CLK_DIV_8                     0x04
469 #define CLK_SEL                         0xFC04
470
471 #define SSC_DIV_N_0                     0xFC0F
472 #define SSC_DIV_N_1                     0xFC10
473 #define SSC_CTL1                        0xFC11
474 #define    SSC_RSTB                     0x80
475 #define    SSC_8X_EN                    0x40
476 #define    SSC_FIX_FRAC                 0x20
477 #define    SSC_SEL_1M                   0x00
478 #define    SSC_SEL_2M                   0x08
479 #define    SSC_SEL_4M                   0x10
480 #define    SSC_SEL_8M                   0x18
481 #define SSC_CTL2                        0xFC12
482 #define    SSC_DEPTH_MASK               0x07
483 #define    SSC_DEPTH_DISALBE            0x00
484 #define    SSC_DEPTH_4M                 0x01
485 #define    SSC_DEPTH_2M                 0x02
486 #define    SSC_DEPTH_1M                 0x03
487 #define    SSC_DEPTH_500K               0x04
488 #define    SSC_DEPTH_250K               0x05
489 #define RCCTL                           0xFC14
490
491 #define FPGA_PULL_CTL                   0xFC1D
492 #define OLT_LED_CTL                     0xFC1E
493 #define GPIO_CTL                        0xFC1F
494
495 #define LDO_CTL                         0xFC1E
496 #define   BPP_ASIC_1V7                  0x00
497 #define   BPP_ASIC_1V8                  0x01
498 #define   BPP_ASIC_1V9                  0x02
499 #define   BPP_ASIC_2V0                  0x03
500 #define   BPP_ASIC_2V7                  0x04
501 #define   BPP_ASIC_2V8                  0x05
502 #define   BPP_ASIC_3V2                  0x06
503 #define   BPP_ASIC_3V3                  0x07
504 #define   BPP_REG_TUNED18               0x07
505 #define   BPP_TUNED18_SHIFT_8402        5
506 #define   BPP_TUNED18_SHIFT_8411        4
507 #define   BPP_PAD_MASK                  0x04
508 #define   BPP_PAD_3V3                   0x04
509 #define   BPP_PAD_1V8                   0x00
510 #define   BPP_LDO_POWB                  0x03
511 #define   BPP_LDO_ON                    0x00
512 #define   BPP_LDO_SUSPEND               0x02
513 #define   BPP_LDO_OFF                   0x03
514 #define SYS_VER                         0xFC32
515
516 #define CARD_PULL_CTL1                  0xFD60
517 #define CARD_PULL_CTL2                  0xFD61
518 #define CARD_PULL_CTL3                  0xFD62
519 #define CARD_PULL_CTL4                  0xFD63
520 #define CARD_PULL_CTL5                  0xFD64
521 #define CARD_PULL_CTL6                  0xFD65
522
523 /* PCI Express Related Registers */
524 #define IRQEN0                          0xFE20
525 #define IRQSTAT0                        0xFE21
526 #define    DMA_DONE_INT                 0x80
527 #define    SUSPEND_INT                  0x40
528 #define    LINK_RDY_INT                 0x20
529 #define    LINK_DOWN_INT                0x10
530 #define IRQEN1                          0xFE22
531 #define IRQSTAT1                        0xFE23
532 #define TLPRIEN                         0xFE24
533 #define TLPRISTAT                       0xFE25
534 #define TLPTIEN                         0xFE26
535 #define TLPTISTAT                       0xFE27
536 #define DMATC0                          0xFE28
537 #define DMATC1                          0xFE29
538 #define DMATC2                          0xFE2A
539 #define DMATC3                          0xFE2B
540 #define DMACTL                          0xFE2C
541 #define   DMA_RST                       0x80
542 #define   DMA_BUSY                      0x04
543 #define   DMA_DIR_TO_CARD               0x00
544 #define   DMA_DIR_FROM_CARD             0x02
545 #define   DMA_EN                        0x01
546 #define   DMA_128                       (0 << 4)
547 #define   DMA_256                       (1 << 4)
548 #define   DMA_512                       (2 << 4)
549 #define   DMA_1024                      (3 << 4)
550 #define   DMA_PACK_SIZE_MASK            0x30
551 #define BCTL                            0xFE2D
552 #define RBBC0                           0xFE2E
553 #define RBBC1                           0xFE2F
554 #define RBDAT                           0xFE30
555 #define RBCTL                           0xFE34
556 #define CFGADDR0                        0xFE35
557 #define CFGADDR1                        0xFE36
558 #define CFGDATA0                        0xFE37
559 #define CFGDATA1                        0xFE38
560 #define CFGDATA2                        0xFE39
561 #define CFGDATA3                        0xFE3A
562 #define CFGRWCTL                        0xFE3B
563 #define PHYRWCTL                        0xFE3C
564 #define PHYDATA0                        0xFE3D
565 #define PHYDATA1                        0xFE3E
566 #define PHYADDR                         0xFE3F
567 #define MSGRXDATA0                      0xFE40
568 #define MSGRXDATA1                      0xFE41
569 #define MSGRXDATA2                      0xFE42
570 #define MSGRXDATA3                      0xFE43
571 #define MSGTXDATA0                      0xFE44
572 #define MSGTXDATA1                      0xFE45
573 #define MSGTXDATA2                      0xFE46
574 #define MSGTXDATA3                      0xFE47
575 #define MSGTXCTL                        0xFE48
576 #define LTR_CTL                         0xFE4A
577 #define LTR_TX_EN_MASK          BIT(7)
578 #define LTR_TX_EN_1                     BIT(7)
579 #define LTR_TX_EN_0                     0
580 #define LTR_LATENCY_MODE_MASK           BIT(6)
581 #define LTR_LATENCY_MODE_HW             0
582 #define LTR_LATENCY_MODE_SW             BIT(6)
583 #define OBFF_CFG                        0xFE4C
584
585 #define CDRESUMECTL                     0xFE52
586 #define WAKE_SEL_CTL                    0xFE54
587 #define PCLK_CTL                        0xFE55
588 #define   PCLK_MODE_SEL                 0x20
589 #define PME_FORCE_CTL                   0xFE56
590
591 #define ASPM_FORCE_CTL                  0xFE57
592 #define   FORCE_ASPM_CTL0               0x10
593 #define   FORCE_ASPM_VAL_MASK           0x03
594 #define   FORCE_ASPM_L1_EN              0x02
595 #define   FORCE_ASPM_L0_EN              0x01
596 #define   FORCE_ASPM_NO_ASPM            0x00
597 #define PM_CLK_FORCE_CTL                0xFE58
598 #define FUNC_FORCE_CTL                  0xFE59
599 #define   FUNC_FORCE_UPME_XMT_DBG       0x02
600 #define PERST_GLITCH_WIDTH              0xFE5C
601 #define CHANGE_LINK_STATE               0xFE5B
602 #define RESET_LOAD_REG                  0xFE5E
603 #define EFUSE_CONTENT                   0xFE5F
604 #define HOST_SLEEP_STATE                0xFE60
605 #define   HOST_ENTER_S1                 1
606 #define   HOST_ENTER_S3                 2
607
608 #define SDIO_CFG                        0xFE70
609 #define PM_EVENT_DEBUG                  0xFE71
610 #define   PME_DEBUG_0                   0x08
611 #define NFTS_TX_CTRL                    0xFE72
612
613 #define PWR_GATE_CTRL                   0xFE75
614 #define   PWR_GATE_EN                   0x01
615 #define   LDO3318_PWR_MASK              0x06
616 #define   LDO_ON                        0x00
617 #define   LDO_SUSPEND                   0x04
618 #define   LDO_OFF                       0x06
619 #define PWD_SUSPEND_EN                  0xFE76
620 #define LDO_PWR_SEL                     0xFE78
621
622 #define L1SUB_CONFIG1                   0xFE8D
623 #define L1SUB_CONFIG2                   0xFE8E
624 #define   L1SUB_AUTO_CFG                0x02
625 #define L1SUB_CONFIG3                   0xFE8F
626 #define   L1OFF_MBIAS2_EN_5250          BIT(7)
627
628 #define DUMMY_REG_RESET_0               0xFE90
629
630 #define AUTOLOAD_CFG_BASE               0xFF00
631 #define PETXCFG                         0xFF03
632 #define FORCE_CLKREQ_DELINK_MASK        BIT(7)
633 #define FORCE_CLKREQ_LOW        0x80
634 #define FORCE_CLKREQ_HIGH       0x00
635
636 #define PM_CTRL1                        0xFF44
637 #define   CD_RESUME_EN_MASK             0xF0
638
639 #define PM_CTRL2                        0xFF45
640 #define PM_CTRL3                        0xFF46
641 #define   SDIO_SEND_PME_EN              0x80
642 #define   FORCE_RC_MODE_ON              0x40
643 #define   FORCE_RX50_LINK_ON            0x20
644 #define   D3_DELINK_MODE_EN             0x10
645 #define   USE_PESRTB_CTL_DELINK         0x08
646 #define   DELAY_PIN_WAKE                0x04
647 #define   RESET_PIN_WAKE                0x02
648 #define   PM_WAKE_EN                    0x01
649 #define PM_CTRL4                        0xFF47
650
651 /* Memory mapping */
652 #define SRAM_BASE                       0xE600
653 #define RBUF_BASE                       0xF400
654 #define PPBUF_BASE1                     0xF800
655 #define PPBUF_BASE2                     0xFA00
656 #define IMAGE_FLAG_ADDR0                0xCE80
657 #define IMAGE_FLAG_ADDR1                0xCE81
658
659 #define RREF_CFG                        0xFF6C
660 #define   RREF_VBGSEL_MASK              0x38
661 #define   RREF_VBGSEL_1V25              0x28
662
663 #define OOBS_CONFIG                     0xFF6E
664 #define   OOBS_AUTOK_DIS                0x80
665 #define   OOBS_VAL_MASK                 0x1F
666
667 #define LDO_DV18_CFG                    0xFF70
668 #define   LDO_DV18_SR_MASK              0xC0
669 #define   LDO_DV18_SR_DF                0x40
670
671 #define LDO_CONFIG2                     0xFF71
672 #define   LDO_D3318_MASK                0x07
673 #define   LDO_D3318_33V                 0x07
674 #define   LDO_D3318_18V                 0x02
675
676 #define LDO_VCC_CFG0                    0xFF72
677 #define   LDO_VCC_LMTVTH_MASK           0x30
678 #define   LDO_VCC_LMTVTH_2A             0x10
679
680 #define LDO_VCC_CFG1                    0xFF73
681 #define   LDO_VCC_REF_TUNE_MASK         0x30
682 #define   LDO_VCC_REF_1V2               0x20
683 #define   LDO_VCC_TUNE_MASK             0x07
684 #define   LDO_VCC_1V8                   0x04
685 #define   LDO_VCC_3V3                   0x07
686 #define   LDO_VCC_LMT_EN                0x08
687
688 #define LDO_VIO_CFG                     0xFF75
689 #define   LDO_VIO_SR_MASK               0xC0
690 #define   LDO_VIO_SR_DF                 0x40
691 #define   LDO_VIO_REF_TUNE_MASK         0x30
692 #define   LDO_VIO_REF_1V2               0x20
693 #define   LDO_VIO_TUNE_MASK             0x07
694 #define   LDO_VIO_1V7                   0x03
695 #define   LDO_VIO_1V8                   0x04
696 #define   LDO_VIO_3V3                   0x07
697
698 #define LDO_DV12S_CFG                   0xFF76
699 #define   LDO_REF12_TUNE_MASK           0x18
700 #define   LDO_REF12_TUNE_DF             0x10
701 #define   LDO_D12_TUNE_MASK             0x07
702 #define   LDO_D12_TUNE_DF               0x04
703
704 #define LDO_AV12S_CFG                   0xFF77
705 #define   LDO_AV12S_TUNE_MASK           0x07
706 #define   LDO_AV12S_TUNE_DF             0x04
707
708 #define SD40_LDO_CTL1                   0xFE7D
709 #define   SD40_VIO_TUNE_MASK            0x70
710 #define   SD40_VIO_TUNE_1V7             0x30
711 #define   SD_VIO_LDO_1V8                0x40
712 #define   SD_VIO_LDO_3V3                0x70
713
714 /* Phy register */
715 #define PHY_PCR                         0x00
716 #define   PHY_PCR_FORCE_CODE            0xB000
717 #define   PHY_PCR_OOBS_CALI_50          0x0800
718 #define   PHY_PCR_OOBS_VCM_08           0x0200
719 #define   PHY_PCR_OOBS_SEN_90           0x0040
720 #define   PHY_PCR_RSSI_EN               0x0002
721 #define   PHY_PCR_RX10K                 0x0001
722
723 #define PHY_RCR0                        0x01
724 #define PHY_RCR1                        0x02
725 #define   PHY_RCR1_ADP_TIME_4           0x0400
726 #define   PHY_RCR1_VCO_COARSE           0x001F
727 #define   PHY_RCR1_INIT_27S             0x0A1F
728 #define PHY_SSCCR2                      0x02
729 #define   PHY_SSCCR2_PLL_NCODE          0x0A00
730 #define   PHY_SSCCR2_TIME0              0x001C
731 #define   PHY_SSCCR2_TIME2_WIDTH        0x0003
732
733 #define PHY_RCR2                        0x03
734 #define   PHY_RCR2_EMPHASE_EN           0x8000
735 #define   PHY_RCR2_NADJR                0x4000
736 #define   PHY_RCR2_CDR_SR_2             0x0100
737 #define   PHY_RCR2_FREQSEL_12           0x0040
738 #define   PHY_RCR2_CDR_SC_12P           0x0010
739 #define   PHY_RCR2_CALIB_LATE           0x0002
740 #define   PHY_RCR2_INIT_27S             0xC152
741 #define PHY_SSCCR3                      0x03
742 #define   PHY_SSCCR3_STEP_IN            0x2740
743 #define   PHY_SSCCR3_CHECK_DELAY        0x0008
744 #define _PHY_ANA03                      0x03
745 #define   _PHY_ANA03_TIMER_MAX          0x2700
746 #define   _PHY_ANA03_OOBS_DEB_EN        0x0040
747 #define   _PHY_CMU_DEBUG_EN             0x0008
748
749 #define PHY_RTCR                        0x04
750 #define PHY_RDR                         0x05
751 #define   PHY_RDR_RXDSEL_1_9            0x4000
752 #define   PHY_SSC_AUTO_PWD              0x0600
753 #define PHY_TCR0                        0x06
754 #define PHY_TCR1                        0x07
755 #define PHY_TUNE                        0x08
756 #define   PHY_TUNE_TUNEREF_1_0          0x4000
757 #define   PHY_TUNE_VBGSEL_1252          0x0C00
758 #define   PHY_TUNE_SDBUS_33             0x0200
759 #define   PHY_TUNE_TUNED18              0x01C0
760 #define   PHY_TUNE_TUNED12              0X0020
761 #define   PHY_TUNE_TUNEA12              0x0004
762 #define   PHY_TUNE_VOLTAGE_MASK         0xFC3F
763 #define   PHY_TUNE_VOLTAGE_3V3          0x03C0
764 #define   PHY_TUNE_D18_1V8              0x0100
765 #define   PHY_TUNE_D18_1V7              0x0080
766 #define PHY_ANA08                       0x08
767 #define   PHY_ANA08_RX_EQ_DCGAIN        0x5000
768 #define   PHY_ANA08_SEL_RX_EN           0x0400
769 #define   PHY_ANA08_RX_EQ_VAL           0x03C0
770 #define   PHY_ANA08_SCP                 0x0020
771 #define   PHY_ANA08_SEL_IPI             0x0004
772
773 #define PHY_IMR                         0x09
774 #define PHY_BPCR                        0x0A
775 #define   PHY_BPCR_IBRXSEL              0x0400
776 #define   PHY_BPCR_IBTXSEL              0x0100
777 #define   PHY_BPCR_IB_FILTER            0x0080
778 #define   PHY_BPCR_CMIRROR_EN           0x0040
779
780 #define PHY_BIST                        0x0B
781 #define PHY_RAW_L                       0x0C
782 #define PHY_RAW_H                       0x0D
783 #define PHY_RAW_DATA                    0x0E
784 #define PHY_HOST_CLK_CTRL               0x0F
785 #define PHY_DMR                         0x10
786 #define PHY_BACR                        0x11
787 #define   PHY_BACR_BASIC_MASK           0xFFF3
788 #define PHY_IER                         0x12
789 #define PHY_BCSR                        0x13
790 #define PHY_BPR                         0x14
791 #define PHY_BPNR2                       0x15
792 #define PHY_BPNR                        0x16
793 #define PHY_BRNR2                       0x17
794 #define PHY_BENR                        0x18
795 #define PHY_REV                         0x19
796 #define   PHY_REV_RESV                  0xE000
797 #define   PHY_REV_RXIDLE_LATCHED        0x1000
798 #define   PHY_REV_P1_EN                 0x0800
799 #define   PHY_REV_RXIDLE_EN             0x0400
800 #define   PHY_REV_CLKREQ_TX_EN          0x0200
801 #define   PHY_REV_CLKREQ_RX_EN          0x0100
802 #define   PHY_REV_CLKREQ_DT_1_0         0x0040
803 #define   PHY_REV_STOP_CLKRD            0x0020
804 #define   PHY_REV_RX_PWST               0x0008
805 #define   PHY_REV_STOP_CLKWR            0x0004
806 #define _PHY_REV0                       0x19
807 #define   _PHY_REV0_FILTER_OUT          0x3800
808 #define   _PHY_REV0_CDR_BYPASS_PFD      0x0100
809 #define   _PHY_REV0_CDR_RX_IDLE_BYPASS  0x0002
810
811 #define PHY_FLD0                        0x1A
812 #define PHY_ANA1A                       0x1A
813 #define   PHY_ANA1A_TXR_LOOPBACK        0x2000
814 #define   PHY_ANA1A_RXT_BIST            0x0500
815 #define   PHY_ANA1A_TXR_BIST            0x0040
816 #define   PHY_ANA1A_REV                 0x0006
817 #define   PHY_FLD0_INIT_27S             0x2546
818 #define PHY_FLD1                        0x1B
819 #define PHY_FLD2                        0x1C
820 #define PHY_FLD3                        0x1D
821 #define   PHY_FLD3_TIMER_4              0x0800
822 #define   PHY_FLD3_TIMER_6              0x0020
823 #define   PHY_FLD3_RXDELINK             0x0004
824 #define   PHY_FLD3_INIT_27S             0x0004
825 #define PHY_ANA1D                       0x1D
826 #define   PHY_ANA1D_DEBUG_ADDR          0x0004
827 #define _PHY_FLD0                       0x1D
828 #define   _PHY_FLD0_CLK_REQ_20C         0x8000
829 #define   _PHY_FLD0_RX_IDLE_EN          0x1000
830 #define   _PHY_FLD0_BIT_ERR_RSTN        0x0800
831 #define   _PHY_FLD0_BER_COUNT           0x01E0
832 #define   _PHY_FLD0_BER_TIMER           0x001E
833 #define   _PHY_FLD0_CHECK_EN            0x0001
834
835 #define PHY_FLD4                        0x1E
836 #define   PHY_FLD4_FLDEN_SEL            0x4000
837 #define   PHY_FLD4_REQ_REF              0x2000
838 #define   PHY_FLD4_RXAMP_OFF            0x1000
839 #define   PHY_FLD4_REQ_ADDA             0x0800
840 #define   PHY_FLD4_BER_COUNT            0x00E0
841 #define   PHY_FLD4_BER_TIMER            0x000A
842 #define   PHY_FLD4_BER_CHK_EN           0x0001
843 #define   PHY_FLD4_INIT_27S             0x5C7F
844 #define PHY_DIG1E                       0x1E
845 #define   PHY_DIG1E_REV                 0x4000
846 #define   PHY_DIG1E_D0_X_D1             0x1000
847 #define   PHY_DIG1E_RX_ON_HOST          0x0800
848 #define   PHY_DIG1E_RCLK_REF_HOST       0x0400
849 #define   PHY_DIG1E_RCLK_TX_EN_KEEP     0x0040
850 #define   PHY_DIG1E_RCLK_TX_TERM_KEEP   0x0020
851 #define   PHY_DIG1E_RCLK_RX_EIDLE_ON    0x0010
852 #define   PHY_DIG1E_TX_TERM_KEEP        0x0008
853 #define   PHY_DIG1E_RX_TERM_KEEP        0x0004
854 #define   PHY_DIG1E_TX_EN_KEEP          0x0002
855 #define   PHY_DIG1E_RX_EN_KEEP          0x0001
856 #define PHY_DUM_REG                     0x1F
857
858 #define PCR_ASPM_SETTING_REG1           0x160
859 #define PCR_ASPM_SETTING_REG2           0x168
860
861 #define PCR_SETTING_REG1                0x724
862 #define PCR_SETTING_REG2                0x814
863 #define PCR_SETTING_REG3                0x747
864
865 #define rtsx_pci_init_cmd(pcr)          ((pcr)->ci = 0)
866
867 #define RTS5227_DEVICE_ID               0x5227
868 #define RTS_MAX_TIMES_FREQ_REDUCTION    8
869
870 struct rtsx_pcr;
871
872 struct pcr_handle {
873         struct rtsx_pcr                 *pcr;
874 };
875
876 struct pcr_ops {
877         int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
878         int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
879         int             (*extra_init_hw)(struct rtsx_pcr *pcr);
880         int             (*optimize_phy)(struct rtsx_pcr *pcr);
881         int             (*turn_on_led)(struct rtsx_pcr *pcr);
882         int             (*turn_off_led)(struct rtsx_pcr *pcr);
883         int             (*enable_auto_blink)(struct rtsx_pcr *pcr);
884         int             (*disable_auto_blink)(struct rtsx_pcr *pcr);
885         int             (*card_power_on)(struct rtsx_pcr *pcr, int card);
886         int             (*card_power_off)(struct rtsx_pcr *pcr, int card);
887         int             (*switch_output_voltage)(struct rtsx_pcr *pcr,
888                                                 u8 voltage);
889         unsigned int    (*cd_deglitch)(struct rtsx_pcr *pcr);
890         int             (*conv_clk_and_div_n)(int clk, int dir);
891         void            (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
892         void            (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
893
894         void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
895         int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
896         int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
897         void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
898         void (*full_on)(struct rtsx_pcr *pcr);
899         void (*power_saving)(struct rtsx_pcr *pcr);
900 };
901
902 enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
903
904 #define ASPM_L1_1_EN_MASK               BIT(3)
905 #define ASPM_L1_2_EN_MASK               BIT(2)
906 #define PM_L1_1_EN_MASK         BIT(1)
907 #define PM_L1_2_EN_MASK         BIT(0)
908
909 #define ASPM_L1_1_EN                    BIT(0)
910 #define ASPM_L1_2_EN                    BIT(1)
911 #define PM_L1_1_EN                              BIT(2)
912 #define PM_L1_2_EN                              BIT(3)
913 #define LTR_L1SS_PWR_GATE_EN    BIT(4)
914 #define L1_SNOOZE_TEST_EN               BIT(5)
915 #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
916
917 enum dev_aspm_mode {
918         DEV_ASPM_DISABLE = 0,
919         DEV_ASPM_DYNAMIC,
920         DEV_ASPM_BACKDOOR,
921         DEV_ASPM_STATIC,
922 };
923
924 /*
925  * struct rtsx_cr_option  - card reader option
926  * @dev_flags: device flags
927  * @force_clkreq_0: force clock request
928  * @ltr_en: enable ltr mode flag
929  * @ltr_enabled: ltr mode in configure space flag
930  * @ltr_active: ltr mode status
931  * @ltr_active_latency: ltr mode active latency
932  * @ltr_idle_latency: ltr mode idle latency
933  * @ltr_l1off_latency: ltr mode l1off latency
934  * @dev_aspm_mode: device aspm mode
935  * @l1_snooze_delay: l1 snooze delay
936  * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
937  * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
938  */
939 struct rtsx_cr_option {
940         u32 dev_flags;
941         bool force_clkreq_0;
942         bool ltr_en;
943         bool ltr_enabled;
944         bool ltr_active;
945         u32 ltr_active_latency;
946         u32 ltr_idle_latency;
947         u32 ltr_l1off_latency;
948         enum dev_aspm_mode dev_aspm_mode;
949         u32 l1_snooze_delay;
950         u8 ltr_l1off_sspwrgate;
951         u8 ltr_l1off_snooze_sspwrgate;
952 };
953
954 #define rtsx_set_dev_flag(cr, flag) \
955         ((cr)->option.dev_flags |= (flag))
956 #define rtsx_clear_dev_flag(cr, flag) \
957         ((cr)->option.dev_flags &= ~(flag))
958 #define rtsx_check_dev_flag(cr, flag) \
959         ((cr)->option.dev_flags & (flag))
960
961 struct rtsx_pcr {
962         struct pci_dev                  *pci;
963         unsigned int                    id;
964         int                             pcie_cap;
965         struct rtsx_cr_option   option;
966
967         /* pci resources */
968         unsigned long                   addr;
969         void __iomem                    *remap_addr;
970         int                             irq;
971
972         /* host reserved buffer */
973         void                            *rtsx_resv_buf;
974         dma_addr_t                      rtsx_resv_buf_addr;
975
976         void                            *host_cmds_ptr;
977         dma_addr_t                      host_cmds_addr;
978         int                             ci;
979
980         void                            *host_sg_tbl_ptr;
981         dma_addr_t                      host_sg_tbl_addr;
982         int                             sgi;
983
984         u32                             bier;
985         char                            trans_result;
986
987         unsigned int                    card_inserted;
988         unsigned int                    card_removed;
989         unsigned int                    card_exist;
990
991         struct delayed_work             carddet_work;
992         struct delayed_work             idle_work;
993
994         spinlock_t                      lock;
995         struct mutex                    pcr_mutex;
996         struct completion               *done;
997         struct completion               *finish_me;
998
999         unsigned int                    cur_clock;
1000         bool                            remove_pci;
1001         bool                            msi_en;
1002
1003 #define EXTRA_CAPS_SD_SDR50             (1 << 0)
1004 #define EXTRA_CAPS_SD_SDR104            (1 << 1)
1005 #define EXTRA_CAPS_SD_DDR50             (1 << 2)
1006 #define EXTRA_CAPS_MMC_HSDDR            (1 << 3)
1007 #define EXTRA_CAPS_MMC_HS200            (1 << 4)
1008 #define EXTRA_CAPS_MMC_8BIT             (1 << 5)
1009         u32                             extra_caps;
1010
1011 #define IC_VER_A                        0
1012 #define IC_VER_B                        1
1013 #define IC_VER_C                        2
1014 #define IC_VER_D                        3
1015         u8                              ic_version;
1016
1017         u8                              sd30_drive_sel_1v8;
1018         u8                              sd30_drive_sel_3v3;
1019         u8                              card_drive_sel;
1020 #define ASPM_L1_EN                      0x02
1021         u8                              aspm_en;
1022         bool                            aspm_enabled;
1023
1024 #define PCR_MS_PMOS                     (1 << 0)
1025 #define PCR_REVERSE_SOCKET              (1 << 1)
1026         u32                             flags;
1027
1028         u32                             tx_initial_phase;
1029         u32                             rx_initial_phase;
1030
1031         const u32                       *sd_pull_ctl_enable_tbl;
1032         const u32                       *sd_pull_ctl_disable_tbl;
1033         const u32                       *ms_pull_ctl_enable_tbl;
1034         const u32                       *ms_pull_ctl_disable_tbl;
1035
1036         const struct pcr_ops            *ops;
1037         enum PDEV_STAT                  state;
1038
1039         u16                             reg_pm_ctrl3;
1040
1041         int                             num_slots;
1042         struct rtsx_slot                *slots;
1043
1044         u8                              dma_error_count;
1045 };
1046
1047 #define PID_524A        0x524A
1048 #define PID_5249                0x5249
1049 #define PID_5250                0x5250
1050 #define PID_525A        0x525A
1051
1052 #define CHK_PCI_PID(pcr, pid)           ((pcr)->pci->device == (pid))
1053 #define PCI_VID(pcr)                    ((pcr)->pci->vendor)
1054 #define PCI_PID(pcr)                    ((pcr)->pci->device)
1055 #define is_version(pcr, pid, ver)                               \
1056         (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1057 #define pcr_dbg(pcr, fmt, arg...)                               \
1058         dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1059
1060 #define SDR104_PHASE(val)               ((val) & 0xFF)
1061 #define SDR50_PHASE(val)                (((val) >> 8) & 0xFF)
1062 #define DDR50_PHASE(val)                (((val) >> 16) & 0xFF)
1063 #define SDR104_TX_PHASE(pcr)            SDR104_PHASE((pcr)->tx_initial_phase)
1064 #define SDR50_TX_PHASE(pcr)             SDR50_PHASE((pcr)->tx_initial_phase)
1065 #define DDR50_TX_PHASE(pcr)             DDR50_PHASE((pcr)->tx_initial_phase)
1066 #define SDR104_RX_PHASE(pcr)            SDR104_PHASE((pcr)->rx_initial_phase)
1067 #define SDR50_RX_PHASE(pcr)             SDR50_PHASE((pcr)->rx_initial_phase)
1068 #define DDR50_RX_PHASE(pcr)             DDR50_PHASE((pcr)->rx_initial_phase)
1069 #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50)   \
1070                                 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
1071
1072 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1073 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1074 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1075 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1076 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1077 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1078 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1079                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
1080 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1081 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1082 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1083                 int num_sg, bool read, int timeout);
1084 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1085                 int num_sg, bool read);
1086 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1087                 int num_sg, bool read);
1088 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1089                 int count, bool read, int timeout);
1090 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1091 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1092 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1093 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1094 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1095                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
1096 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1097 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1098 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1099 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1100 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1101 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1102
1103 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
1104 {
1105         return (u8 *)(pcr->host_cmds_ptr);
1106 }
1107
1108 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
1109                 u8 mask, u8 append)
1110 {
1111         int err;
1112         u8 val;
1113
1114         err = pci_read_config_byte(pcr->pci, addr, &val);
1115         if (err < 0)
1116                 return err;
1117         return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
1118 }
1119
1120 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1121 {
1122         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg,     0xFF, val >> 24);
1123         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
1124         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
1125         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1126 }
1127
1128 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1129         u16 mask, u16 append)
1130 {
1131         int err;
1132         u16 val;
1133
1134         err = rtsx_pci_read_phy_register(pcr, addr, &val);
1135         if (err < 0)
1136                 return err;
1137
1138         return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1139 }
1140
1141 #endif