2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 /* sclk gates (special clocks) */
34 #define SCLK_SARADC 73
36 #define SCLK_NANDC0 75
37 #define SCLK_NANDC1 76
45 #define SCLK_SPDIF8CH 84
46 #define SCLK_TIMER0 85
47 #define SCLK_TIMER1 86
48 #define SCLK_TIMER2 87
49 #define SCLK_TIMER3 88
50 #define SCLK_TIMER4 89
51 #define SCLK_TIMER5 90
52 #define SCLK_TIMER6 91
54 #define SCLK_OTGPHY0 93
55 #define SCLK_OTGPHY1 94
56 #define SCLK_OTGPHY2 95
57 #define SCLK_OTG_ADP 96
58 #define SCLK_HSICPHY480M 97
59 #define SCLK_HSICPHY12M 98
60 #define SCLK_MACREF 99
61 #define SCLK_LCDC_PWM0 100
62 #define SCLK_LCDC_PWM1 101
63 #define SCLK_MAC_RX 102
64 #define SCLK_MAC_TX 103
65 #define SCLK_EDP_24M 104
69 #define SCLK_ISP_JPE 108
70 #define SCLK_HDMI_HDCP 109
71 #define SCLK_HDMI_CEC 110
72 #define SCLK_HEVC_CABAC 111
73 #define SCLK_HEVC_CORE 112
80 #define ACLK_DMAC1 193
81 #define ACLK_DMAC2 194
86 #define ACLK_CRYPTO 199
88 #define ACLK_RGA_NIU 201
90 #define ACLK_VIO0_NIU 203
93 #define ACLK_VIO1_NIU 206
95 #define ACLK_VCODEC 208
100 #define PCLK_GPIO0 320
101 #define PCLK_GPIO1 321
102 #define PCLK_GPIO2 322
103 #define PCLK_GPIO3 323
104 #define PCLK_GPIO4 324
105 #define PCLK_GPIO5 325
106 #define PCLK_GPIO6 326
107 #define PCLK_GPIO7 327
108 #define PCLK_GPIO8 328
110 #define PCLK_SGRF 330
112 #define PCLK_I2C0 332
113 #define PCLK_I2C1 333
114 #define PCLK_I2C2 334
115 #define PCLK_I2C3 335
116 #define PCLK_I2C4 336
117 #define PCLK_I2C5 337
118 #define PCLK_SPI0 338
119 #define PCLK_SPI1 339
120 #define PCLK_SPI2 340
121 #define PCLK_UART0 341
122 #define PCLK_UART1 342
123 #define PCLK_UART2 343
124 #define PCLK_UART3 344
125 #define PCLK_UART4 345
126 #define PCLK_TSADC 346
127 #define PCLK_SARADC 347
129 #define PCLK_GMAC 349
131 #define PCLK_RKPWM 351
132 #define PCLK_PS2C 352
133 #define PCLK_TIMER 353
134 #define PCLK_TZPC 354
135 #define PCLK_EDP_CTRL 355
136 #define PCLK_MIPI_DSI0 356
137 #define PCLK_MIPI_DSI1 357
138 #define PCLK_MIPI_CSI 358
139 #define PCLK_LVDS_PHY 359
140 #define PCLK_HDMI_CTRL 360
141 #define PCLK_VIO2_H2P 361
143 #define PCLK_PERI 363
147 #define HCLK_OTG0 449
148 #define HCLK_USBHOST0 450
149 #define HCLK_USBHOST1 451
150 #define HCLK_HSIC 452
151 #define HCLK_NANDC0 453
152 #define HCLK_NANDC1 454
154 #define HCLK_SDMMC 456
155 #define HCLK_SDIO0 457
156 #define HCLK_SDIO1 458
157 #define HCLK_EMMC 459
158 #define HCLK_HSADC 460
159 #define HCLK_CRYPTO 461
160 #define HCLK_I2S0 462
161 #define HCLK_SPDIF 463
162 #define HCLK_SPDIF8CH 464
163 #define HCLK_VOP0 465
164 #define HCLK_VOP1 466
169 #define HCLK_VIO_AHB_ARBI 471
170 #define HCLK_VIO_NIU 472
172 #define HCLK_VIO2_H2P 474
173 #define HCLK_HEVC 475
174 #define HCLK_VCODEC 476
176 #define HCLK_PERI 478
178 #define CLK_NR_CLKS (HCLK_PERI + 1)
180 /* soft-reset indices */
185 #define SRST_CORE0_PO 4
186 #define SRST_CORE1_PO 5
187 #define SRST_CORE2_PO 6
188 #define SRST_CORE3_PO 7
189 #define SRST_PDCORE_STRSYS 8
190 #define SRST_PDBUS_STRSYS 9
192 #define SRST_TOPDBG 11
193 #define SRST_CORE0_DBG 12
194 #define SRST_CORE1_DBG 13
195 #define SRST_CORE2_DBG 14
196 #define SRST_CORE3_DBG 15
198 #define SRST_PDBUG_AHB_ARBITOR 16
199 #define SRST_EFUSE256 17
200 #define SRST_DMAC1 18
201 #define SRST_INTMEM 19
203 #define SRST_SPDIF8CH 21
204 #define SRST_TIMER 22
206 #define SRST_SPDIF 24
207 #define SRST_TIMER0 25
208 #define SRST_TIMER1 26
209 #define SRST_TIMER2 27
210 #define SRST_TIMER3 28
211 #define SRST_TIMER4 29
212 #define SRST_TIMER5 30
213 #define SRST_EFUSE 31
215 #define SRST_GPIO0 32
216 #define SRST_GPIO1 33
217 #define SRST_GPIO2 34
218 #define SRST_GPIO3 35
219 #define SRST_GPIO4 36
220 #define SRST_GPIO5 37
221 #define SRST_GPIO6 38
222 #define SRST_GPIO7 39
223 #define SRST_GPIO8 40
231 #define SRST_DWPWM 48
232 #define SRST_MMC_PERI 49
233 #define SRST_PERIPH_MMU 50
235 #define SRST_DAP_SYS 52
237 #define SRST_PMU_APB 54
240 #define SRST_PERIPH_AXI 57
241 #define SRST_PERIPH_AHB 58
242 #define SRST_PERIPH_APB 59
243 #define SRST_PERIPH_NIU 60
244 #define SRST_PDPERI_AHB_ARBI 61
246 #define SRST_USB_PERI 63
248 #define SRST_DMAC2 64
251 #define SRST_RKPWM 69
253 #define SRST_USBHOST0 72
255 #define SRST_HSIC_AUX 74
256 #define SRST_HSIC_PHY 75
257 #define SRST_HSADC 76
258 #define SRST_NANDC0 77
259 #define SRST_NANDC1 78
265 #define SRST_SARADC 87
266 #define SRST_PDALIVE_NIU 88
267 #define SRST_PDPMU_INTMEM 89
268 #define SRST_PDPMU_NIU 90
271 #define SRST_VIO_ARBI 96
272 #define SRST_RGA_NIU 97
273 #define SRST_VIO0_NIU_AXI 98
274 #define SRST_VIO_NIU_AHB 99
275 #define SRST_LCDC0_AXI 100
276 #define SRST_LCDC0_AHB 101
277 #define SRST_LCDC0_DCLK 102
278 #define SRST_VIO1_NIU_AXI 103
280 #define SRST_RGA_CORE 105
281 #define SRST_IEP_AXI 106
282 #define SRST_IEP_AHB 107
283 #define SRST_RGA_AXI 108
284 #define SRST_RGA_AHB 109
288 #define SRST_VCODEC_AXI 112
289 #define SRST_VCODEC_AHB 113
290 #define SRST_VIO_H2P 114
291 #define SRST_MIPIDSI0 115
292 #define SRST_MIPIDSI1 116
293 #define SRST_MIPICSI 117
294 #define SRST_LVDS_PHY 118
295 #define SRST_LVDS_CON 119
297 #define SRST_HDMI 121
298 #define SRST_CORE_PVTM 124
299 #define SRST_GPU_PVTM 125
301 #define SRST_MMC0 128
302 #define SRST_SDIO0 129
303 #define SRST_SDIO1 130
304 #define SRST_EMMC 131
305 #define SRST_USBOTG_AHB 132
306 #define SRST_USBOTG_PHY 133
307 #define SRST_USBOTG_CON 134
308 #define SRST_USBHOST0_AHB 135
309 #define SRST_USBHOST0_PHY 136
310 #define SRST_USBHOST0_CON 137
311 #define SRST_USBHOST1_AHB 138
312 #define SRST_USBHOST1_PHY 139
313 #define SRST_USBHOST1_CON 140
314 #define SRST_USB_ADP 141
315 #define SRST_ACC_EFUSE 142
317 #define SRST_CORESIGHT 144
318 #define SRST_PD_CORE_AHB_NOC 145
319 #define SRST_PD_CORE_APB_NOC 146
320 #define SRST_PD_CORE_MP_AXI 147
322 #define SRST_LCDC_PWM0 149
323 #define SRST_LCDC_PWM1 150
324 #define SRST_VIO0_H2P_BRG 151
325 #define SRST_VIO1_H2P_BRG 152
326 #define SRST_RGA_H2P_BRG 153
327 #define SRST_HEVC 154
328 #define SRST_TSADC 159
330 #define SRST_DDRPHY0 160
331 #define SRST_DDRPHY0_APB 161
332 #define SRST_DDRCTRL0 162
333 #define SRST_DDRCTRL0_APB 163
334 #define SRST_DDRPHY0_CTRL 164
335 #define SRST_DDRPHY1 165
336 #define SRST_DDRPHY1_APB 166
337 #define SRST_DDRCTRL1 167
338 #define SRST_DDRCTRL1_APB 168
339 #define SRST_DDRPHY1_CTRL 169
340 #define SRST_DDRMSCH0 170
341 #define SRST_DDRMSCH1 171
342 #define SRST_CRYPTO 174
343 #define SRST_C2C_HOST 175
345 #define SRST_LCDC1_AXI 176
346 #define SRST_LCDC1_AHB 177
347 #define SRST_LCDC1_DCLK 178
348 #define SRST_UART0 179
349 #define SRST_UART1 180
350 #define SRST_UART2 181
351 #define SRST_UART3 182
352 #define SRST_UART4 183
353 #define SRST_SIMC 186
354 #define SRST_PS2C 187
356 #define SRST_TSP_CLKIN0 189
357 #define SRST_TSP_CLKIN1 190
358 #define SRST_TSP_27M 191