include/dt-bindings/clock/qcom,gcc-msm8996.h

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
  15 #define _DT_BINDINGS_CLK_MSM_GCC_8996_H
  16
  17 #define GPLL0_EARLY                                             0
  18 #define GPLL0                                                   1
  19 #define GPLL1_EARLY                                             2
  20 #define GPLL1                                                   3
  21 #define GPLL2_EARLY                                             4
  22 #define GPLL2                                                   5
  23 #define GPLL3_EARLY                                             6
  24 #define GPLL3                                                   7
  25 #define GPLL4_EARLY                                             8
  26 #define GPLL4                                                   9
  27 #define SYSTEM_NOC_CLK_SRC                                      10
  28 #define CONFIG_NOC_CLK_SRC                                      11
  29 #define PERIPH_NOC_CLK_SRC                                      12
  30 #define MMSS_BIMC_GFX_CLK_SRC                                   13
  31 #define USB30_MASTER_CLK_SRC                                    14
  32 #define USB30_MOCK_UTMI_CLK_SRC                                 15
  33 #define USB3_PHY_AUX_CLK_SRC                                    16
  34 #define USB20_MASTER_CLK_SRC                                    17
  35 #define USB20_MOCK_UTMI_CLK_SRC                                 18
  36 #define SDCC1_APPS_CLK_SRC                                      19
  37 #define SDCC1_ICE_CORE_CLK_SRC                                  20
  38 #define SDCC2_APPS_CLK_SRC                                      21
  39 #define SDCC3_APPS_CLK_SRC                                      22
  40 #define SDCC4_APPS_CLK_SRC                                      23
  41 #define BLSP1_QUP1_SPI_APPS_CLK_SRC                             24
  42 #define BLSP1_QUP1_I2C_APPS_CLK_SRC                             25
  43 #define BLSP1_UART1_APPS_CLK_SRC                                26
  44 #define BLSP1_QUP2_SPI_APPS_CLK_SRC                             27
  45 #define BLSP1_QUP2_I2C_APPS_CLK_SRC                             28
  46 #define BLSP1_UART2_APPS_CLK_SRC                                29
  47 #define BLSP1_QUP3_SPI_APPS_CLK_SRC                             30
  48 #define BLSP1_QUP3_I2C_APPS_CLK_SRC                             31
  49 #define BLSP1_UART3_APPS_CLK_SRC                                32
  50 #define BLSP1_QUP4_SPI_APPS_CLK_SRC                             33
  51 #define BLSP1_QUP4_I2C_APPS_CLK_SRC                             34
  52 #define BLSP1_UART4_APPS_CLK_SRC                                35
  53 #define BLSP1_QUP5_SPI_APPS_CLK_SRC                             36
  54 #define BLSP1_QUP5_I2C_APPS_CLK_SRC                             37
  55 #define BLSP1_UART5_APPS_CLK_SRC                                38
  56 #define BLSP1_QUP6_SPI_APPS_CLK_SRC                             39
  57 #define BLSP1_QUP6_I2C_APPS_CLK_SRC                             40
  58 #define BLSP1_UART6_APPS_CLK_SRC                                41
  59 #define BLSP2_QUP1_SPI_APPS_CLK_SRC                             42
  60 #define BLSP2_QUP1_I2C_APPS_CLK_SRC                             43
  61 #define BLSP2_UART1_APPS_CLK_SRC                                44
  62 #define BLSP2_QUP2_SPI_APPS_CLK_SRC                             45
  63 #define BLSP2_QUP2_I2C_APPS_CLK_SRC                             46
  64 #define BLSP2_UART2_APPS_CLK_SRC                                47
  65 #define BLSP2_QUP3_SPI_APPS_CLK_SRC                             48
  66 #define BLSP2_QUP3_I2C_APPS_CLK_SRC                             49
  67 #define BLSP2_UART3_APPS_CLK_SRC                                50
  68 #define BLSP2_QUP4_SPI_APPS_CLK_SRC                             51
  69 #define BLSP2_QUP4_I2C_APPS_CLK_SRC                             52
  70 #define BLSP2_UART4_APPS_CLK_SRC                                53
  71 #define BLSP2_QUP5_SPI_APPS_CLK_SRC                             54
  72 #define BLSP2_QUP5_I2C_APPS_CLK_SRC                             55
  73 #define BLSP2_UART5_APPS_CLK_SRC                                56
  74 #define BLSP2_QUP6_SPI_APPS_CLK_SRC                             57
  75 #define BLSP2_QUP6_I2C_APPS_CLK_SRC                             58
  76 #define BLSP2_UART6_APPS_CLK_SRC                                59
  77 #define PDM2_CLK_SRC                                            60
  78 #define TSIF_REF_CLK_SRC                                        61
  79 #define CE1_CLK_SRC                                             62
  80 #define GCC_SLEEP_CLK_SRC                                       63
  81 #define BIMC_CLK_SRC                                            64
  82 #define HMSS_AHB_CLK_SRC                                        65
  83 #define BIMC_HMSS_AXI_CLK_SRC                                   66
  84 #define HMSS_RBCPR_CLK_SRC                                      67
  85 #define HMSS_GPLL0_CLK_SRC                                      68
  86 #define GP1_CLK_SRC                                             69
  87 #define GP2_CLK_SRC                                             70
  88 #define GP3_CLK_SRC                                             71
  89 #define PCIE_AUX_CLK_SRC                                        72
  90 #define UFS_AXI_CLK_SRC                                         73
  91 #define UFS_ICE_CORE_CLK_SRC                                    74
  92 #define QSPI_SER_CLK_SRC                                        75
  93 #define GCC_SYS_NOC_AXI_CLK                                     76
  94 #define GCC_SYS_NOC_HMSS_AHB_CLK                                77
  95 #define GCC_SNOC_CNOC_AHB_CLK                                   78
  96 #define GCC_SNOC_PNOC_AHB_CLK                                   79
  97 #define GCC_SYS_NOC_AT_CLK                                      80
  98 #define GCC_SYS_NOC_USB3_AXI_CLK                                81
  99 #define GCC_SYS_NOC_UFS_AXI_CLK                                 82
 100 #define GCC_CFG_NOC_AHB_CLK                                     83
 101 #define GCC_PERIPH_NOC_AHB_CLK                                  84
 102 #define GCC_PERIPH_NOC_USB20_AHB_CLK                            85
 103 #define GCC_TIC_CLK                                             86
 104 #define GCC_IMEM_AXI_CLK                                        87
 105 #define GCC_MMSS_SYS_NOC_AXI_CLK                                88
 106 #define GCC_MMSS_NOC_CFG_AHB_CLK                                89
 107 #define GCC_MMSS_BIMC_GFX_CLK                                   90
 108 #define GCC_USB30_MASTER_CLK                                    91
 109 #define GCC_USB30_SLEEP_CLK                                     92
 110 #define GCC_USB30_MOCK_UTMI_CLK                                 93
 111 #define GCC_USB3_PHY_AUX_CLK                                    94
 112 #define GCC_USB3_PHY_PIPE_CLK                                   95
 113 #define GCC_USB20_MASTER_CLK                                    96
 114 #define GCC_USB20_SLEEP_CLK                                     97
 115 #define GCC_USB20_MOCK_UTMI_CLK                                 98
 116 #define GCC_USB_PHY_CFG_AHB2PHY_CLK                             99
 117 #define GCC_SDCC1_APPS_CLK                                      100
 118 #define GCC_SDCC1_AHB_CLK                                       101
 119 #define GCC_SDCC1_ICE_CORE_CLK                                  102
 120 #define GCC_SDCC2_APPS_CLK                                      103
 121 #define GCC_SDCC2_AHB_CLK                                       104
 122 #define GCC_SDCC3_APPS_CLK                                      105
 123 #define GCC_SDCC3_AHB_CLK                                       106
 124 #define GCC_SDCC4_APPS_CLK                                      107
 125 #define GCC_SDCC4_AHB_CLK                                       108
 126 #define GCC_BLSP1_AHB_CLK                                       109
 127 #define GCC_BLSP1_SLEEP_CLK                                     110
 128 #define GCC_BLSP1_QUP1_SPI_APPS_CLK                             111
 129 #define GCC_BLSP1_QUP1_I2C_APPS_CLK                             112
 130 #define GCC_BLSP1_UART1_APPS_CLK                                113
 131 #define GCC_BLSP1_QUP2_SPI_APPS_CLK                             114
 132 #define GCC_BLSP1_QUP2_I2C_APPS_CLK                             115
 133 #define GCC_BLSP1_UART2_APPS_CLK                                116
 134 #define GCC_BLSP1_QUP3_SPI_APPS_CLK                             117
 135 #define GCC_BLSP1_QUP3_I2C_APPS_CLK                             118
 136 #define GCC_BLSP1_UART3_APPS_CLK                                119
 137 #define GCC_BLSP1_QUP4_SPI_APPS_CLK                             120
 138 #define GCC_BLSP1_QUP4_I2C_APPS_CLK                             121
 139 #define GCC_BLSP1_UART4_APPS_CLK                                122
 140 #define GCC_BLSP1_QUP5_SPI_APPS_CLK                             123
 141 #define GCC_BLSP1_QUP5_I2C_APPS_CLK                             124
 142 #define GCC_BLSP1_UART5_APPS_CLK                                125
 143 #define GCC_BLSP1_QUP6_SPI_APPS_CLK                             126
 144 #define GCC_BLSP1_QUP6_I2C_APPS_CLK                             127
 145 #define GCC_BLSP1_UART6_APPS_CLK                                128
 146 #define GCC_BLSP2_AHB_CLK                                       129
 147 #define GCC_BLSP2_SLEEP_CLK                                     130
 148 #define GCC_BLSP2_QUP1_SPI_APPS_CLK                             131
 149 #define GCC_BLSP2_QUP1_I2C_APPS_CLK                             132
 150 #define GCC_BLSP2_UART1_APPS_CLK                                133
 151 #define GCC_BLSP2_QUP2_SPI_APPS_CLK                             134
 152 #define GCC_BLSP2_QUP2_I2C_APPS_CLK                             135
 153 #define GCC_BLSP2_UART2_APPS_CLK                                136
 154 #define GCC_BLSP2_QUP3_SPI_APPS_CLK                             137
 155 #define GCC_BLSP2_QUP3_I2C_APPS_CLK                             138
 156 #define GCC_BLSP2_UART3_APPS_CLK                                139
 157 #define GCC_BLSP2_QUP4_SPI_APPS_CLK                             140
 158 #define GCC_BLSP2_QUP4_I2C_APPS_CLK                             141
 159 #define GCC_BLSP2_UART4_APPS_CLK                                142
 160 #define GCC_BLSP2_QUP5_SPI_APPS_CLK                             143
 161 #define GCC_BLSP2_QUP5_I2C_APPS_CLK                             144
 162 #define GCC_BLSP2_UART5_APPS_CLK                                145
 163 #define GCC_BLSP2_QUP6_SPI_APPS_CLK                             146
 164 #define GCC_BLSP2_QUP6_I2C_APPS_CLK                             147
 165 #define GCC_BLSP2_UART6_APPS_CLK                                148
 166 #define GCC_PDM_AHB_CLK                                         149
 167 #define GCC_PDM_XO4_CLK                                         150
 168 #define GCC_PDM2_CLK                                            151
 169 #define GCC_PRNG_AHB_CLK                                        152
 170 #define GCC_TSIF_AHB_CLK                                        153
 171 #define GCC_TSIF_REF_CLK                                        154
 172 #define GCC_TSIF_INACTIVITY_TIMERS_CLK                          155
 173 #define GCC_TCSR_AHB_CLK                                        156
 174 #define GCC_BOOT_ROM_AHB_CLK                                    157
 175 #define GCC_MSG_RAM_AHB_CLK                                     158
 176 #define GCC_TLMM_AHB_CLK                                        159
 177 #define GCC_TLMM_CLK                                            160
 178 #define GCC_MPM_AHB_CLK                                         161
 179 #define GCC_SPMI_SER_CLK                                        162
 180 #define GCC_SPMI_CNOC_AHB_CLK                                   163
 181 #define GCC_CE1_CLK                                             164
 182 #define GCC_CE1_AXI_CLK                                         165
 183 #define GCC_CE1_AHB_CLK                                         166
 184 #define GCC_BIMC_HMSS_AXI_CLK                                   167
 185 #define GCC_BIMC_GFX_CLK                                        168
 186 #define GCC_HMSS_AHB_CLK                                        169
 187 #define GCC_HMSS_SLV_AXI_CLK                                    170
 188 #define GCC_HMSS_MSTR_AXI_CLK                                   171
 189 #define GCC_HMSS_RBCPR_CLK                                      172
 190 #define GCC_GP1_CLK                                             173
 191 #define GCC_GP2_CLK                                             174
 192 #define GCC_GP3_CLK                                             175
 193 #define GCC_PCIE_0_SLV_AXI_CLK                                  176
 194 #define GCC_PCIE_0_MSTR_AXI_CLK                                 177
 195 #define GCC_PCIE_0_CFG_AHB_CLK                                  178
 196 #define GCC_PCIE_0_AUX_CLK                                      179
 197 #define GCC_PCIE_0_PIPE_CLK                                     180
 198 #define GCC_PCIE_1_SLV_AXI_CLK                                  181
 199 #define GCC_PCIE_1_MSTR_AXI_CLK                                 182
 200 #define GCC_PCIE_1_CFG_AHB_CLK                                  183
 201 #define GCC_PCIE_1_AUX_CLK                                      184
 202 #define GCC_PCIE_1_PIPE_CLK                                     185
 203 #define GCC_PCIE_2_SLV_AXI_CLK                                  186
 204 #define GCC_PCIE_2_MSTR_AXI_CLK                                 187
 205 #define GCC_PCIE_2_CFG_AHB_CLK                                  188
 206 #define GCC_PCIE_2_AUX_CLK                                      189
 207 #define GCC_PCIE_2_PIPE_CLK                                     190
 208 #define GCC_PCIE_PHY_CFG_AHB_CLK                                191
 209 #define GCC_PCIE_PHY_AUX_CLK                                    192
 210 #define GCC_UFS_AXI_CLK                                         193
 211 #define GCC_UFS_AHB_CLK                                         194
 212 #define GCC_UFS_TX_CFG_CLK                                      195
 213 #define GCC_UFS_RX_CFG_CLK                                      196
 214 #define GCC_UFS_TX_SYMBOL_0_CLK                                 197
 215 #define GCC_UFS_RX_SYMBOL_0_CLK                                 198
 216 #define GCC_UFS_RX_SYMBOL_1_CLK                                 199
 217 #define GCC_UFS_UNIPRO_CORE_CLK                                 200
 218 #define GCC_UFS_ICE_CORE_CLK                                    201
 219 #define GCC_UFS_SYS_CLK_CORE_CLK                                202
 220 #define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK                          203
 221 #define GCC_AGGRE0_SNOC_AXI_CLK                                 204
 222 #define GCC_AGGRE0_CNOC_AHB_CLK                                 205
 223 #define GCC_SMMU_AGGRE0_AXI_CLK                                 206
 224 #define GCC_SMMU_AGGRE0_AHB_CLK                                 207
 225 #define GCC_AGGRE1_PNOC_AHB_CLK                                 208
 226 #define GCC_AGGRE2_UFS_AXI_CLK                                  209
 227 #define GCC_AGGRE2_USB3_AXI_CLK                                 210
 228 #define GCC_QSPI_AHB_CLK                                        211
 229 #define GCC_QSPI_SER_CLK                                        212
 230 #define GCC_USB3_CLKREF_CLK                                     213
 231 #define GCC_HDMI_CLKREF_CLK                                     214
 232 #define GCC_UFS_CLKREF_CLK                                      215
 233 #define GCC_PCIE_CLKREF_CLK                                     216
 234 #define GCC_RX2_USB2_CLKREF_CLK                                 217
 235 #define GCC_RX1_USB2_CLKREF_CLK                                 218
 236 #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK                      219
 237 #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK                      220
 238
 239 #define GCC_SYSTEM_NOC_BCR                                      0
 240 #define GCC_CONFIG_NOC_BCR                                      1
 241 #define GCC_PERIPH_NOC_BCR                                      2
 242 #define GCC_IMEM_BCR                                            3
 243 #define GCC_MMSS_BCR                                            4
 244 #define GCC_PIMEM_BCR                                           5
 245 #define GCC_QDSS_BCR                                            6
 246 #define GCC_USB_30_BCR                                          7
 247 #define GCC_USB_20_BCR                                          8
 248 #define GCC_QUSB2PHY_PRIM_BCR                                   9
 249 #define GCC_QUSB2PHY_SEC_BCR                                    10
 250 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             11
 251 #define GCC_SDCC1_BCR                                           12
 252 #define GCC_SDCC2_BCR                                           13
 253 #define GCC_SDCC3_BCR                                           14
 254 #define GCC_SDCC4_BCR                                           15
 255 #define GCC_BLSP1_BCR                                           16
 256 #define GCC_BLSP1_QUP1_BCR                                      17
 257 #define GCC_BLSP1_UART1_BCR                                     18
 258 #define GCC_BLSP1_QUP2_BCR                                      19
 259 #define GCC_BLSP1_UART2_BCR                                     20
 260 #define GCC_BLSP1_QUP3_BCR                                      21
 261 #define GCC_BLSP1_UART3_BCR                                     22
 262 #define GCC_BLSP1_QUP4_BCR                                      23
 263 #define GCC_BLSP1_UART4_BCR                                     24
 264 #define GCC_BLSP1_QUP5_BCR                                      25
 265 #define GCC_BLSP1_UART5_BCR                                     26
 266 #define GCC_BLSP1_QUP6_BCR                                      27
 267 #define GCC_BLSP1_UART6_BCR                                     28
 268 #define GCC_BLSP2_BCR                                           29
 269 #define GCC_BLSP2_QUP1_BCR                                      30
 270 #define GCC_BLSP2_UART1_BCR                                     31
 271 #define GCC_BLSP2_QUP2_BCR                                      32
 272 #define GCC_BLSP2_UART2_BCR                                     33
 273 #define GCC_BLSP2_QUP3_BCR                                      34
 274 #define GCC_BLSP2_UART3_BCR                                     35
 275 #define GCC_BLSP2_QUP4_BCR                                      36
 276 #define GCC_BLSP2_UART4_BCR                                     37
 277 #define GCC_BLSP2_QUP5_BCR                                      38
 278 #define GCC_BLSP2_UART5_BCR                                     39
 279 #define GCC_BLSP2_QUP6_BCR                                      40
 280 #define GCC_BLSP2_UART6_BCR                                     41
 281 #define GCC_PDM_BCR                                             42
 282 #define GCC_PRNG_BCR                                            43
 283 #define GCC_TSIF_BCR                                            44
 284 #define GCC_TCSR_BCR                                            45
 285 #define GCC_BOOT_ROM_BCR                                        46
 286 #define GCC_MSG_RAM_BCR                                         47
 287 #define GCC_TLMM_BCR                                            48
 288 #define GCC_MPM_BCR                                             49
 289 #define GCC_SEC_CTRL_BCR                                        50
 290 #define GCC_SPMI_BCR                                            51
 291 #define GCC_SPDM_BCR                                            52
 292 #define GCC_CE1_BCR                                             53
 293 #define GCC_BIMC_BCR                                            54
 294 #define GCC_SNOC_BUS_TIMEOUT0_BCR                               55
 295 #define GCC_SNOC_BUS_TIMEOUT2_BCR                               56
 296 #define GCC_SNOC_BUS_TIMEOUT1_BCR                               57
 297 #define GCC_SNOC_BUS_TIMEOUT3_BCR                               58
 298 #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR                         59
 299 #define GCC_PNOC_BUS_TIMEOUT0_BCR                               60
 300 #define GCC_PNOC_BUS_TIMEOUT1_BCR                               61
 301 #define GCC_PNOC_BUS_TIMEOUT2_BCR                               62
 302 #define GCC_PNOC_BUS_TIMEOUT3_BCR                               63
 303 #define GCC_PNOC_BUS_TIMEOUT4_BCR                               64
 304 #define GCC_CNOC_BUS_TIMEOUT0_BCR                               65
 305 #define GCC_CNOC_BUS_TIMEOUT1_BCR                               66
 306 #define GCC_CNOC_BUS_TIMEOUT2_BCR                               67
 307 #define GCC_CNOC_BUS_TIMEOUT3_BCR                               68
 308 #define GCC_CNOC_BUS_TIMEOUT4_BCR                               69
 309 #define GCC_CNOC_BUS_TIMEOUT5_BCR                               70
 310 #define GCC_CNOC_BUS_TIMEOUT6_BCR                               71
 311 #define GCC_CNOC_BUS_TIMEOUT7_BCR                               72
 312 #define GCC_CNOC_BUS_TIMEOUT8_BCR                               73
 313 #define GCC_CNOC_BUS_TIMEOUT9_BCR                               74
 314 #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR                         75
 315 #define GCC_APB2JTAG_BCR                                        76
 316 #define GCC_RBCPR_CX_BCR                                        77
 317 #define GCC_RBCPR_MX_BCR                                        78
 318 #define GCC_PCIE_0_BCR                                          79
 319 #define GCC_PCIE_0_PHY_BCR                                      80
 320 #define GCC_PCIE_1_BCR                                          81
 321 #define GCC_PCIE_1_PHY_BCR                                      82
 322 #define GCC_PCIE_2_BCR                                          83
 323 #define GCC_PCIE_2_PHY_BCR                                      84
 324 #define GCC_PCIE_PHY_BCR                                        85
 325 #define GCC_DCD_BCR                                             86
 326 #define GCC_OBT_ODT_BCR                                         87
 327 #define GCC_UFS_BCR                                             88
 328 #define GCC_SSC_BCR                                             89
 329 #define GCC_VS_BCR                                              90
 330 #define GCC_AGGRE0_NOC_BCR                                      91
 331 #define GCC_AGGRE1_NOC_BCR                                      92
 332 #define GCC_AGGRE2_NOC_BCR                                      93
 333 #define GCC_DCC_BCR                                             94
 334 #define GCC_IPA_BCR                                             95
 335 #define GCC_QSPI_BCR                                            96
 336 #define GCC_SKL_BCR                                             97
 337 #define GCC_MSMPU_BCR                                           98
 338 #define GCC_MSS_Q6_BCR                                          99
 339 #define GCC_QREFS_VBG_CAL_BCR                                   100
 340 #define GCC_PCIE_PHY_COM_BCR                                    101
 341 #define GCC_PCIE_PHY_COM_NOCSR_BCR                              102
 342 #define GCC_USB3_PHY_BCR                                        103
 343 #define GCC_USB3PHY_PHY_BCR                                     104
 344 #define GCC_MSS_RESTART                                         105
 345
 346
 347 /* Indexes for GDSCs */
 348 #define AGGRE0_NOC_GDSC                 0
 349 #define HLOS1_VOTE_AGGRE0_NOC_GDSC      1
 350 #define HLOS1_VOTE_LPASS_ADSP_GDSC      2
 351 #define HLOS1_VOTE_LPASS_CORE_GDSC      3
 352 #define USB30_GDSC                      4
 353 #define PCIE0_GDSC                      5
 354 #define PCIE1_GDSC                      6
 355 #define PCIE2_GDSC                      7
 356 #define UFS_GDSC                        8
 357
 358 #endif