include/dt-bindings/clock/lpc18xx-ccu.h

   1 /*
   2  * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
   3  *
   4  * This code is released using a dual license strategy: BSD/GPL
   5  * You can choose the licence that better fits your requirements.
   6  *
   7  * Released under the terms of 3-clause BSD License
   8  * Released under the terms of GNU General Public License Version 2.0
   9  *
  10  */
  11
  12 /* Clock Control Unit 1 (CCU1) clock offsets */
  13 #define CLK_APB3_BUS            0x100
  14 #define CLK_APB3_I2C1           0x108
  15 #define CLK_APB3_DAC            0x110
  16 #define CLK_APB3_ADC0           0x118
  17 #define CLK_APB3_ADC1           0x120
  18 #define CLK_APB3_CAN0           0x128
  19 #define CLK_APB1_BUS            0x200
  20 #define CLK_APB1_MOTOCON_PWM    0x208
  21 #define CLK_APB1_I2C0           0x210
  22 #define CLK_APB1_I2S            0x218
  23 #define CLK_APB1_CAN1           0x220
  24 #define CLK_SPIFI               0x300
  25 #define CLK_CPU_BUS             0x400
  26 #define CLK_CPU_SPIFI           0x408
  27 #define CLK_CPU_GPIO            0x410
  28 #define CLK_CPU_LCD             0x418
  29 #define CLK_CPU_ETHERNET        0x420
  30 #define CLK_CPU_USB0            0x428
  31 #define CLK_CPU_EMC             0x430
  32 #define CLK_CPU_SDIO            0x438
  33 #define CLK_CPU_DMA             0x440
  34 #define CLK_CPU_CORE            0x448
  35 #define CLK_CPU_SCT             0x468
  36 #define CLK_CPU_USB1            0x470
  37 #define CLK_CPU_EMCDIV          0x478
  38 #define CLK_CPU_FLASHA          0x480
  39 #define CLK_CPU_FLASHB          0x488
  40 #define CLK_CPU_M0APP           0x490
  41 #define CLK_CPU_ADCHS           0x498
  42 #define CLK_CPU_EEPROM          0x4a0
  43 #define CLK_CPU_WWDT            0x500
  44 #define CLK_CPU_UART0           0x508
  45 #define CLK_CPU_UART1           0x510
  46 #define CLK_CPU_SSP0            0x518
  47 #define CLK_CPU_TIMER0          0x520
  48 #define CLK_CPU_TIMER1          0x528
  49 #define CLK_CPU_SCU             0x530
  50 #define CLK_CPU_CREG            0x538
  51 #define CLK_CPU_RITIMER         0x600
  52 #define CLK_CPU_UART2           0x608
  53 #define CLK_CPU_UART3           0x610
  54 #define CLK_CPU_TIMER2          0x618
  55 #define CLK_CPU_TIMER3          0x620
  56 #define CLK_CPU_SSP1            0x628
  57 #define CLK_CPU_QEI             0x630
  58 #define CLK_PERIPH_BUS          0x700
  59 #define CLK_PERIPH_CORE         0x710
  60 #define CLK_PERIPH_SGPIO        0x718
  61 #define CLK_USB0                0x800
  62 #define CLK_USB1                0x900
  63 #define CLK_SPI                 0xA00
  64 #define CLK_ADCHS               0xB00
  65
  66 /* Clock Control Unit 2 (CCU2) clock offsets */
  67 #define CLK_AUDIO               0x100
  68 #define CLK_APB2_UART3          0x200
  69 #define CLK_APB2_UART2          0x300
  70 #define CLK_APB0_UART1          0x400
  71 #define CLK_APB0_UART0          0x500
  72 #define CLK_APB2_SSP1           0x600
  73 #define CLK_APB0_SSP0           0x700
  74 #define CLK_SDIO                0x800