Merge tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm
[sfrench/cifs-2.6.git] / include / drm / bridge / dw_hdmi.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
4  */
5
6 #ifndef __DW_HDMI__
7 #define __DW_HDMI__
8
9 #include <sound/hdmi-codec.h>
10
11 struct drm_connector;
12 struct drm_display_mode;
13 struct drm_encoder;
14 struct dw_hdmi;
15 struct platform_device;
16
17 /**
18  * DOC: Supported input formats and encodings
19  *
20  * Depending on the Hardware configuration of the Controller IP, it supports
21  * a subset of the following input formats and encodings on its internal
22  * 48bit bus.
23  *
24  * +----------------------+----------------------------------+------------------------------+
25  * | Format Name          | Format Code                      | Encodings                    |
26  * +----------------------+----------------------------------+------------------------------+
27  * | RGB 4:4:4 8bit       | ``MEDIA_BUS_FMT_RGB888_1X24``    | ``V4L2_YCBCR_ENC_DEFAULT``   |
28  * +----------------------+----------------------------------+------------------------------+
29  * | RGB 4:4:4 10bits     | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
30  * +----------------------+----------------------------------+------------------------------+
31  * | RGB 4:4:4 12bits     | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
32  * +----------------------+----------------------------------+------------------------------+
33  * | RGB 4:4:4 16bits     | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
34  * +----------------------+----------------------------------+------------------------------+
35  * | YCbCr 4:4:4 8bit     | ``MEDIA_BUS_FMT_YUV8_1X24``      | ``V4L2_YCBCR_ENC_601``       |
36  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
37  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
38  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
39  * +----------------------+----------------------------------+------------------------------+
40  * | YCbCr 4:4:4 10bits   | ``MEDIA_BUS_FMT_YUV10_1X30``     | ``V4L2_YCBCR_ENC_601``       |
41  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
42  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
43  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
44  * +----------------------+----------------------------------+------------------------------+
45  * | YCbCr 4:4:4 12bits   | ``MEDIA_BUS_FMT_YUV12_1X36``     | ``V4L2_YCBCR_ENC_601``       |
46  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
47  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
48  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
49  * +----------------------+----------------------------------+------------------------------+
50  * | YCbCr 4:4:4 16bits   | ``MEDIA_BUS_FMT_YUV16_1X48``     | ``V4L2_YCBCR_ENC_601``       |
51  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
52  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
53  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
54  * +----------------------+----------------------------------+------------------------------+
55  * | YCbCr 4:2:2 8bit     | ``MEDIA_BUS_FMT_UYVY8_1X16``     | ``V4L2_YCBCR_ENC_601``       |
56  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
57  * +----------------------+----------------------------------+------------------------------+
58  * | YCbCr 4:2:2 10bits   | ``MEDIA_BUS_FMT_UYVY10_1X20``    | ``V4L2_YCBCR_ENC_601``       |
59  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
60  * +----------------------+----------------------------------+------------------------------+
61  * | YCbCr 4:2:2 12bits   | ``MEDIA_BUS_FMT_UYVY12_1X24``    | ``V4L2_YCBCR_ENC_601``       |
62  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
63  * +----------------------+----------------------------------+------------------------------+
64  * | YCbCr 4:2:0 8bit     | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601``       |
65  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
66  * +----------------------+----------------------------------+------------------------------+
67  * | YCbCr 4:2:0 10bits   | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601``       |
68  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
69  * +----------------------+----------------------------------+------------------------------+
70  * | YCbCr 4:2:0 12bits   | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601``       |
71  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
72  * +----------------------+----------------------------------+------------------------------+
73  * | YCbCr 4:2:0 16bits   | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601``       |
74  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
75  * +----------------------+----------------------------------+------------------------------+
76  */
77
78 enum {
79         DW_HDMI_RES_8,
80         DW_HDMI_RES_10,
81         DW_HDMI_RES_12,
82         DW_HDMI_RES_MAX,
83 };
84
85 enum dw_hdmi_phy_type {
86         DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
87         DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
88         DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
89         DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
90         DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
91         DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
92         DW_HDMI_PHY_VENDOR_PHY = 0xfe,
93 };
94
95 struct dw_hdmi_mpll_config {
96         unsigned long mpixelclock;
97         struct {
98                 u16 cpce;
99                 u16 gmp;
100         } res[DW_HDMI_RES_MAX];
101 };
102
103 struct dw_hdmi_curr_ctrl {
104         unsigned long mpixelclock;
105         u16 curr[DW_HDMI_RES_MAX];
106 };
107
108 struct dw_hdmi_phy_config {
109         unsigned long mpixelclock;
110         u16 sym_ctr;    /*clock symbol and transmitter control*/
111         u16 term;       /*transmission termination value*/
112         u16 vlev_ctr;   /* voltage level control */
113 };
114
115 struct dw_hdmi_phy_ops {
116         int (*init)(struct dw_hdmi *hdmi, void *data,
117                     struct drm_display_mode *mode);
118         void (*disable)(struct dw_hdmi *hdmi, void *data);
119         enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
120         void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
121                            bool force, bool disabled, bool rxsense);
122         void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
123 };
124
125 struct dw_hdmi_plat_data {
126         struct regmap *regm;
127         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
128                                            const struct drm_display_mode *mode);
129         unsigned long input_bus_format;
130         unsigned long input_bus_encoding;
131         bool use_drm_infoframe;
132
133         /* Vendor PHY support */
134         const struct dw_hdmi_phy_ops *phy_ops;
135         const char *phy_name;
136         void *phy_data;
137         unsigned int phy_force_vendor;
138
139         /* Synopsys PHY support */
140         const struct dw_hdmi_mpll_config *mpll_cfg;
141         const struct dw_hdmi_curr_ctrl *cur_ctr;
142         const struct dw_hdmi_phy_config *phy_config;
143         int (*configure_phy)(struct dw_hdmi *hdmi,
144                              const struct dw_hdmi_plat_data *pdata,
145                              unsigned long mpixelclock);
146 };
147
148 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
149                               const struct dw_hdmi_plat_data *plat_data);
150 void dw_hdmi_remove(struct dw_hdmi *hdmi);
151 void dw_hdmi_unbind(struct dw_hdmi *hdmi);
152 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
153                              struct drm_encoder *encoder,
154                              const struct dw_hdmi_plat_data *plat_data);
155
156 void dw_hdmi_resume(struct dw_hdmi *hdmi);
157
158 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
159
160 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
161                            struct device *codec_dev);
162 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
163 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
164 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
165 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
166 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
167 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
168 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
169
170 /* PHY configuration */
171 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
172 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
173                            unsigned char addr);
174
175 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
176 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
177 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
178
179 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
180                                                void *data);
181 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
182                             bool force, bool disabled, bool rxsense);
183 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
184
185 #endif /* __IMX_HDMI_H__ */