include/asm-x86/system_64.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cmpxchg.h>
   7
   8 #ifdef __KERNEL__
   9
  10 /* entries in ARCH_DLINFO: */
  11 #ifdef CONFIG_IA32_EMULATION
  12 # define AT_VECTOR_SIZE_ARCH 2
  13 #else
  14 # define AT_VECTOR_SIZE_ARCH 1
  15 #endif
  16
  17 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  18 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  19
  20 /* frame pointer must be last for get_wchan */
  21 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  22 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  23
  24 #define __EXTRA_CLOBBER  \
  25         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  26
  27 /* Save restore flags to clear handle leaking NT */
  28 #define switch_to(prev,next,last) \
  29         asm volatile(SAVE_CONTEXT                                                   \
  30                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  31                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  32                      "call __switch_to\n\t"                                       \
  33                      ".globl thread_return\n"                                   \
  34                      "thread_return:\n\t"                                           \
  35                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  36                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  37                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  38                      "movq %%rax,%%rdi\n\t"                                       \
  39                      "jc   ret_from_fork\n\t"                                     \
  40                      RESTORE_CONTEXT                                                \
  41                      : "=a" (last)                                                \
  42                      : [next] "S" (next), [prev] "D" (prev),                      \
  43                        [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
  44                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  45                        [tif_fork] "i" (TIF_FORK),                         \
  46                        [thread_info] "i" (offsetof(struct task_struct, stack)), \
  47                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  48                      : "memory", "cc" __EXTRA_CLOBBER)
  49
  50 extern void load_gs_index(unsigned);
  51
  52 /*
  53  * Load a segment. Fall back on loading the zero
  54  * segment if something goes wrong..
  55  */
  56 #define loadsegment(seg,value)  \
  57         asm volatile("\n"                       \
  58                 "1:\t"                          \
  59                 "movl %k0,%%" #seg "\n"         \
  60                 "2:\n"                          \
  61                 ".section .fixup,\"ax\"\n"      \
  62                 "3:\t"                          \
  63                 "movl %1,%%" #seg "\n\t"        \
  64                 "jmp 2b\n"                      \
  65                 ".previous\n"                   \
  66                 ".section __ex_table,\"a\"\n\t" \
  67                 ".align 8\n\t"                  \
  68                 ".quad 1b,3b\n"                 \
  69                 ".previous"                     \
  70                 : :"r" (value), "r" (0))
  71
  72 /*
  73  * Clear and set 'TS' bit respectively
  74  */
  75 #define clts() __asm__ __volatile__ ("clts")
  76
  77 static inline unsigned long read_cr0(void)
  78 {
  79         unsigned long cr0;
  80         asm volatile("movq %%cr0,%0" : "=r" (cr0));
  81         return cr0;
  82 }
  83
  84 static inline void write_cr0(unsigned long val)
  85 {
  86         asm volatile("movq %0,%%cr0" :: "r" (val));
  87 }
  88
  89 static inline unsigned long read_cr2(void)
  90 {
  91         unsigned long cr2;
  92         asm volatile("movq %%cr2,%0" : "=r" (cr2));
  93         return cr2;
  94 }
  95
  96 static inline void write_cr2(unsigned long val)
  97 {
  98         asm volatile("movq %0,%%cr2" :: "r" (val));
  99 }
 100
 101 static inline unsigned long read_cr3(void)
 102 {
 103         unsigned long cr3;
 104         asm volatile("movq %%cr3,%0" : "=r" (cr3));
 105         return cr3;
 106 }
 107
 108 static inline void write_cr3(unsigned long val)
 109 {
 110         asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
 111 }
 112
 113 static inline unsigned long read_cr4(void)
 114 {
 115         unsigned long cr4;
 116         asm volatile("movq %%cr4,%0" : "=r" (cr4));
 117         return cr4;
 118 }
 119
 120 static inline void write_cr4(unsigned long val)
 121 {
 122         asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
 123 }
 124
 125 static inline unsigned long read_cr8(void)
 126 {
 127         unsigned long cr8;
 128         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 129         return cr8;
 130 }
 131
 132 static inline void write_cr8(unsigned long val)
 133 {
 134         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 135 }
 136
 137 #define stts() write_cr0(8 | read_cr0())
 138
 139 #define wbinvd() \
 140         __asm__ __volatile__ ("wbinvd": : :"memory")
 141
 142 #endif  /* __KERNEL__ */
 143
 144 static inline void clflush(volatile void *__p)
 145 {
 146         asm volatile("clflush %0" : "+m" (*(char __force *)__p));
 147 }
 148
 149 #define nop() __asm__ __volatile__ ("nop")
 150
 151 #ifdef CONFIG_SMP
 152 #define smp_mb()        mb()
 153 #define smp_rmb()       barrier()
 154 #define smp_wmb()       barrier()
 155 #define smp_read_barrier_depends()      do {} while(0)
 156 #else
 157 #define smp_mb()        barrier()
 158 #define smp_rmb()       barrier()
 159 #define smp_wmb()       barrier()
 160 #define smp_read_barrier_depends()      do {} while(0)
 161 #endif
 162
 163
 164 /*
 165  * Force strict CPU ordering.
 166  * And yes, this is required on UP too when we're talking
 167  * to devices.
 168  */
 169 #define mb()    asm volatile("mfence":::"memory")
 170 #define rmb()   asm volatile("lfence":::"memory")
 171 #define wmb()   asm volatile("sfence" ::: "memory")
 172
 173 #define read_barrier_depends()  do {} while(0)
 174 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 175
 176 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 177
 178 #include <linux/irqflags.h>
 179
 180 void cpu_idle_wait(void);
 181
 182 extern unsigned long arch_align_stack(unsigned long sp);
 183 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 184
 185 #endif