x86: provide read and write cr8 paravirt hooks
[sfrench/cifs-2.6.git] / include / asm-x86 / system.h
1 #ifndef _ASM_X86_SYSTEM_H_
2 #define _ASM_X86_SYSTEM_H_
3
4 #include <asm/asm.h>
5 #include <asm/segment.h>
6 #include <asm/cpufeature.h>
7 #include <asm/cmpxchg.h>
8 #include <asm/nops.h>
9
10 #include <linux/kernel.h>
11 #include <linux/irqflags.h>
12
13 /* entries in ARCH_DLINFO: */
14 #ifdef CONFIG_IA32_EMULATION
15 # define AT_VECTOR_SIZE_ARCH 2
16 #else
17 # define AT_VECTOR_SIZE_ARCH 1
18 #endif
19
20 #ifdef CONFIG_X86_32
21
22 struct task_struct; /* one of the stranger aspects of C forward declarations */
23 extern struct task_struct *FASTCALL(__switch_to(struct task_struct *prev,
24                                                 struct task_struct *next));
25
26 /*
27  * Saving eflags is important. It switches not only IOPL between tasks,
28  * it also protects other tasks from NT leaking through sysenter etc.
29  */
30 #define switch_to(prev, next, last) do {                                \
31         unsigned long esi, edi;                                         \
32         asm volatile("pushfl\n\t"               /* Save flags */        \
33                      "pushl %%ebp\n\t"                                  \
34                      "movl %%esp,%0\n\t"        /* save ESP */          \
35                      "movl %5,%%esp\n\t"        /* restore ESP */       \
36                      "movl $1f,%1\n\t"          /* save EIP */          \
37                      "pushl %6\n\t"             /* restore EIP */       \
38                      "jmp __switch_to\n"                                \
39                      "1:\t"                                             \
40                      "popl %%ebp\n\t"                                   \
41                      "popfl"                                            \
42                      :"=m" (prev->thread.sp), "=m" (prev->thread.ip),   \
43                       "=a" (last), "=S" (esi), "=D" (edi)               \
44                      :"m" (next->thread.sp), "m" (next->thread.ip),     \
45                       "2" (prev), "d" (next));                          \
46 } while (0)
47
48 /*
49  * disable hlt during certain critical i/o operations
50  */
51 #define HAVE_DISABLE_HLT
52 #else
53 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
54 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
55
56 /* frame pointer must be last for get_wchan */
57 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
58 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
59
60 #define __EXTRA_CLOBBER  \
61         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
62           "r12", "r13", "r14", "r15"
63
64 /* Save restore flags to clear handle leaking NT */
65 #define switch_to(prev, next, last) \
66         asm volatile(SAVE_CONTEXT                                                   \
67              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
68              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
69              "call __switch_to\n\t"                                       \
70              ".globl thread_return\n"                                     \
71              "thread_return:\n\t"                                         \
72              "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
73              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
74              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
75              "movq %%rax,%%rdi\n\t"                                       \
76              "jc   ret_from_fork\n\t"                                     \
77              RESTORE_CONTEXT                                              \
78              : "=a" (last)                                                \
79              : [next] "S" (next), [prev] "D" (prev),                      \
80                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
81                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
82                [tif_fork] "i" (TIF_FORK),                                 \
83                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
84                [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))  \
85              : "memory", "cc" __EXTRA_CLOBBER)
86 #endif
87
88 #ifdef __KERNEL__
89 #define _set_base(addr, base) do { unsigned long __pr; \
90 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
91         "rorl $16,%%edx\n\t" \
92         "movb %%dl,%2\n\t" \
93         "movb %%dh,%3" \
94         :"=&d" (__pr) \
95         :"m" (*((addr)+2)), \
96          "m" (*((addr)+4)), \
97          "m" (*((addr)+7)), \
98          "0" (base) \
99         ); } while (0)
100
101 #define _set_limit(addr, limit) do { unsigned long __lr; \
102 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
103         "rorl $16,%%edx\n\t" \
104         "movb %2,%%dh\n\t" \
105         "andb $0xf0,%%dh\n\t" \
106         "orb %%dh,%%dl\n\t" \
107         "movb %%dl,%2" \
108         :"=&d" (__lr) \
109         :"m" (*(addr)), \
110          "m" (*((addr)+6)), \
111          "0" (limit) \
112         ); } while (0)
113
114 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
115 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
116
117 extern void load_gs_index(unsigned);
118
119 /*
120  * Load a segment. Fall back on loading the zero
121  * segment if something goes wrong..
122  */
123 #define loadsegment(seg, value)                 \
124         asm volatile("\n"                       \
125                 "1:\t"                          \
126                 "movl %k0,%%" #seg "\n"         \
127                 "2:\n"                          \
128                 ".section .fixup,\"ax\"\n"      \
129                 "3:\t"                          \
130                 "movl %k1, %%" #seg "\n\t"      \
131                 "jmp 2b\n"                      \
132                 ".previous\n"                   \
133                 ".section __ex_table,\"a\"\n\t" \
134                 _ASM_ALIGN "\n\t"               \
135                 _ASM_PTR " 1b,3b\n"             \
136                 ".previous"                     \
137                 : :"r" (value), "r" (0))
138
139
140 /*
141  * Save a segment register away
142  */
143 #define savesegment(seg, value) \
144         asm volatile("mov %%" #seg ",%0":"=rm" (value))
145
146 static inline unsigned long get_limit(unsigned long segment)
147 {
148         unsigned long __limit;
149         __asm__("lsll %1,%0"
150                 :"=r" (__limit):"r" (segment));
151         return __limit+1;
152 }
153
154 static inline void native_clts(void)
155 {
156         asm volatile ("clts");
157 }
158
159 /*
160  * Volatile isn't enough to prevent the compiler from reordering the
161  * read/write functions for the control registers and messing everything up.
162  * A memory clobber would solve the problem, but would prevent reordering of
163  * all loads stores around it, which can hurt performance. Solution is to
164  * use a variable and mimic reads and writes to it to enforce serialization
165  */
166 static unsigned long __force_order;
167
168 static inline unsigned long native_read_cr0(void)
169 {
170         unsigned long val;
171         asm volatile("mov %%cr0,%0\n\t" :"=r" (val), "=m" (__force_order));
172         return val;
173 }
174
175 static inline void native_write_cr0(unsigned long val)
176 {
177         asm volatile("mov %0,%%cr0": :"r" (val), "m" (__force_order));
178 }
179
180 static inline unsigned long native_read_cr2(void)
181 {
182         unsigned long val;
183         asm volatile("mov %%cr2,%0\n\t" :"=r" (val), "=m" (__force_order));
184         return val;
185 }
186
187 static inline void native_write_cr2(unsigned long val)
188 {
189         asm volatile("mov %0,%%cr2": :"r" (val), "m" (__force_order));
190 }
191
192 static inline unsigned long native_read_cr3(void)
193 {
194         unsigned long val;
195         asm volatile("mov %%cr3,%0\n\t" :"=r" (val), "=m" (__force_order));
196         return val;
197 }
198
199 static inline void native_write_cr3(unsigned long val)
200 {
201         asm volatile("mov %0,%%cr3": :"r" (val), "m" (__force_order));
202 }
203
204 static inline unsigned long native_read_cr4(void)
205 {
206         unsigned long val;
207         asm volatile("mov %%cr4,%0\n\t" :"=r" (val), "=m" (__force_order));
208         return val;
209 }
210
211 static inline unsigned long native_read_cr4_safe(void)
212 {
213         unsigned long val;
214         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
215          * exists, so it will never fail. */
216 #ifdef CONFIG_X86_32
217         asm volatile("1: mov %%cr4, %0          \n"
218                 "2:                             \n"
219                 ".section __ex_table,\"a\"      \n"
220                 ".long 1b,2b                    \n"
221                 ".previous                      \n"
222                 : "=r" (val), "=m" (__force_order) : "0" (0));
223 #else
224         val = native_read_cr4();
225 #endif
226         return val;
227 }
228
229 static inline void native_write_cr4(unsigned long val)
230 {
231         asm volatile("mov %0,%%cr4": :"r" (val), "m" (__force_order));
232 }
233
234 #ifdef CONFIG_X86_64
235 static inline unsigned long native_read_cr8(void)
236 {
237         unsigned long cr8;
238         asm volatile("movq %%cr8,%0" : "=r" (cr8));
239         return cr8;
240 }
241
242 static inline void native_write_cr8(unsigned long val)
243 {
244         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
245 }
246 #endif
247
248 static inline void native_wbinvd(void)
249 {
250         asm volatile("wbinvd": : :"memory");
251 }
252 #ifdef CONFIG_PARAVIRT
253 #include <asm/paravirt.h>
254 #else
255 #define read_cr0()      (native_read_cr0())
256 #define write_cr0(x)    (native_write_cr0(x))
257 #define read_cr2()      (native_read_cr2())
258 #define write_cr2(x)    (native_write_cr2(x))
259 #define read_cr3()      (native_read_cr3())
260 #define write_cr3(x)    (native_write_cr3(x))
261 #define read_cr4()      (native_read_cr4())
262 #define read_cr4_safe() (native_read_cr4_safe())
263 #define write_cr4(x)    (native_write_cr4(x))
264 #define wbinvd()        (native_wbinvd())
265 #ifdef CONFIG_X86_64
266 #define read_cr8()      (native_read_cr8())
267 #define write_cr8(x)    (native_write_cr8(x))
268 #endif
269
270 /* Clear the 'TS' bit */
271 #define clts()          (native_clts())
272
273 #endif/* CONFIG_PARAVIRT */
274
275 #define stts() write_cr0(8 | read_cr0())
276
277 #endif /* __KERNEL__ */
278
279 static inline void clflush(void *__p)
280 {
281         asm volatile("clflush %0" : "+m" (*(char __force *)__p));
282 }
283
284 #define nop() __asm__ __volatile__ ("nop")
285
286 void disable_hlt(void);
287 void enable_hlt(void);
288
289 extern int es7000_plat;
290 void cpu_idle_wait(void);
291
292 extern unsigned long arch_align_stack(unsigned long sp);
293 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
294
295 void default_idle(void);
296
297 /*
298  * Force strict CPU ordering.
299  * And yes, this is required on UP too when we're talking
300  * to devices.
301  */
302 #ifdef CONFIG_X86_32
303 /*
304  * For now, "wmb()" doesn't actually do anything, as all
305  * Intel CPU's follow what Intel calls a *Processor Order*,
306  * in which all writes are seen in the program order even
307  * outside the CPU.
308  *
309  * I expect future Intel CPU's to have a weaker ordering,
310  * but I'd also expect them to finally get their act together
311  * and add some real memory barriers if so.
312  *
313  * Some non intel clones support out of order store. wmb() ceases to be a
314  * nop for these.
315  */
316 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
317 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
318 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
319 #else
320 #define mb()    asm volatile("mfence":::"memory")
321 #define rmb()   asm volatile("lfence":::"memory")
322 #define wmb()   asm volatile("sfence" ::: "memory")
323 #endif
324
325 /**
326  * read_barrier_depends - Flush all pending reads that subsequents reads
327  * depend on.
328  *
329  * No data-dependent reads from memory-like regions are ever reordered
330  * over this barrier.  All reads preceding this primitive are guaranteed
331  * to access memory (but not necessarily other CPUs' caches) before any
332  * reads following this primitive that depend on the data return by
333  * any of the preceding reads.  This primitive is much lighter weight than
334  * rmb() on most CPUs, and is never heavier weight than is
335  * rmb().
336  *
337  * These ordering constraints are respected by both the local CPU
338  * and the compiler.
339  *
340  * Ordering is not guaranteed by anything other than these primitives,
341  * not even by data dependencies.  See the documentation for
342  * memory_barrier() for examples and URLs to more information.
343  *
344  * For example, the following code would force ordering (the initial
345  * value of "a" is zero, "b" is one, and "p" is "&a"):
346  *
347  * <programlisting>
348  *      CPU 0                           CPU 1
349  *
350  *      b = 2;
351  *      memory_barrier();
352  *      p = &b;                         q = p;
353  *                                      read_barrier_depends();
354  *                                      d = *q;
355  * </programlisting>
356  *
357  * because the read of "*q" depends on the read of "p" and these
358  * two reads are separated by a read_barrier_depends().  However,
359  * the following code, with the same initial values for "a" and "b":
360  *
361  * <programlisting>
362  *      CPU 0                           CPU 1
363  *
364  *      a = 2;
365  *      memory_barrier();
366  *      b = 3;                          y = b;
367  *                                      read_barrier_depends();
368  *                                      x = a;
369  * </programlisting>
370  *
371  * does not enforce ordering, since there is no data dependency between
372  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
373  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
374  * in cases like this where there are no data dependencies.
375  **/
376
377 #define read_barrier_depends()  do { } while (0)
378
379 #ifdef CONFIG_SMP
380 #define smp_mb()        mb()
381 #ifdef CONFIG_X86_PPRO_FENCE
382 # define smp_rmb()      rmb()
383 #else
384 # define smp_rmb()      barrier()
385 #endif
386 #ifdef CONFIG_X86_OOSTORE
387 # define smp_wmb()      wmb()
388 #else
389 # define smp_wmb()      barrier()
390 #endif
391 #define smp_read_barrier_depends()      read_barrier_depends()
392 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
393 #else
394 #define smp_mb()        barrier()
395 #define smp_rmb()       barrier()
396 #define smp_wmb()       barrier()
397 #define smp_read_barrier_depends()      do { } while (0)
398 #define set_mb(var, value) do { var = value; barrier(); } while (0)
399 #endif
400
401 /*
402  * Stop RDTSC speculation. This is needed when you need to use RDTSC
403  * (or get_cycles or vread that possibly accesses the TSC) in a defined
404  * code region.
405  *
406  * (Could use an alternative three way for this if there was one.)
407  */
408 static inline void rdtsc_barrier(void)
409 {
410         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
411         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
412 }
413
414 #endif