2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/processor-flags.h>
23 #include <asm/desc_defs.h>
25 /* flag for disabling the tsc */
26 extern int tsc_disable;
28 static inline int desc_empty(const void *ptr)
30 const u32 *desc = ptr;
31 return !(desc[0] | desc[1]);
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41 * CPU type and hardware bug flags. Kept separately for each CPU.
42 * Members of this structure are referenced in head.S, so think twice
43 * before touching them. [mj]
47 __u8 x86; /* CPU family */
48 __u8 x86_vendor; /* CPU vendor */
51 char wp_works_ok; /* It doesn't on 386's */
52 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
56 unsigned long x86_capability[NCAPINTS];
57 char x86_vendor_id[16];
58 char x86_model_id[64];
59 int x86_cache_size; /* in KB - valid for CPUS which support this
61 int x86_cache_alignment; /* In bytes */
67 unsigned long loops_per_jiffy;
69 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
71 unsigned char x86_max_cores; /* cpuid returned max cores value */
73 unsigned short x86_clflush_size;
75 unsigned char booted_cores; /* number of cores as seen by OS */
76 __u8 phys_proc_id; /* Physical processor id. */
77 __u8 cpu_core_id; /* Core id */
78 __u8 cpu_index; /* index into per_cpu list */
80 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
82 #define X86_VENDOR_INTEL 0
83 #define X86_VENDOR_CYRIX 1
84 #define X86_VENDOR_AMD 2
85 #define X86_VENDOR_UMC 3
86 #define X86_VENDOR_NEXGEN 4
87 #define X86_VENDOR_CENTAUR 5
88 #define X86_VENDOR_TRANSMETA 7
89 #define X86_VENDOR_NSC 8
90 #define X86_VENDOR_NUM 9
91 #define X86_VENDOR_UNKNOWN 0xff
94 * capabilities of CPUs
97 extern struct cpuinfo_x86 boot_cpu_data;
98 extern struct cpuinfo_x86 new_cpu_data;
99 extern struct tss_struct doublefault_tss;
100 DECLARE_PER_CPU(struct tss_struct, init_tss);
103 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
104 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
105 #define current_cpu_data cpu_data(smp_processor_id())
107 #define cpu_data(cpu) boot_cpu_data
108 #define current_cpu_data boot_cpu_data
112 * the following now lives in the per cpu area:
113 * extern int cpu_llc_id[NR_CPUS];
115 DECLARE_PER_CPU(u8, cpu_llc_id);
116 extern char ignore_fpu_irq;
118 void __init cpu_detect(struct cpuinfo_x86 *c);
120 extern void identify_boot_cpu(void);
121 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
122 extern void print_cpu_info(struct cpuinfo_x86 *);
123 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
124 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
125 extern unsigned short num_cache_leaves;
128 extern void detect_ht(struct cpuinfo_x86 *c);
130 static inline void detect_ht(struct cpuinfo_x86 *c) {}
133 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
136 * Save the cr4 feature set we're using (ie
137 * Pentium 4MB enable and PPro Global page
138 * enable), so that any CPU's that boot up
139 * after us can get the correct flags.
141 extern unsigned long mmu_cr4_features;
143 static inline void set_in_cr4 (unsigned long mask)
146 mmu_cr4_features |= mask;
152 static inline void clear_in_cr4 (unsigned long mask)
155 mmu_cr4_features &= ~mask;
161 /* Stop speculative execution */
162 static inline void sync_core(void)
165 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
168 static inline void __monitor(const void *eax, unsigned long ecx,
171 /* "monitor %eax,%ecx,%edx;" */
173 ".byte 0x0f,0x01,0xc8;"
174 : :"a" (eax), "c" (ecx), "d"(edx));
177 static inline void __mwait(unsigned long eax, unsigned long ecx)
179 /* "mwait %eax,%ecx;" */
181 ".byte 0x0f,0x01,0xc9;"
182 : :"a" (eax), "c" (ecx));
185 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
187 /* from system description table in BIOS. Mostly for MCA use, but
188 others may find it useful. */
189 extern unsigned int machine_id;
190 extern unsigned int machine_submodel_id;
191 extern unsigned int BIOS_revision;
192 extern unsigned int mca_pentium_flag;
194 /* Boot loader type from the setup header */
195 extern int bootloader_type;
198 * User space process size: 3GB (default).
200 #define TASK_SIZE (PAGE_OFFSET)
202 /* This decides where the kernel will search for a free chunk of vm
203 * space during mmap's.
205 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
207 #define HAVE_ARCH_PICK_MMAP_LAYOUT
209 extern void hard_disable_TSC(void);
210 extern void disable_TSC(void);
211 extern void hard_enable_TSC(void);
216 #define IO_BITMAP_BITS 65536
217 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
218 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
219 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
220 #define INVALID_IO_BITMAP_OFFSET 0x8000
221 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
223 struct i387_fsave_struct {
231 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
232 long status; /* software status information */
235 struct i387_fxsave_struct {
246 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
247 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
249 } __attribute__ ((aligned (16)));
251 struct i387_soft_struct {
259 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
260 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
262 unsigned long entry_eip;
266 struct i387_fsave_struct fsave;
267 struct i387_fxsave_struct fxsave;
268 struct i387_soft_struct soft;
275 struct thread_struct;
277 /* This is the TSS defined by the hardware. */
279 unsigned short back_link,__blh;
281 unsigned short ss0,__ss0h;
283 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
285 unsigned short ss2,__ss2h;
289 unsigned long ax, cx, dx, bx;
290 unsigned long sp, bp, si, di;
291 unsigned short es, __esh;
292 unsigned short cs, __csh;
293 unsigned short ss, __ssh;
294 unsigned short ds, __dsh;
295 unsigned short fs, __fsh;
296 unsigned short gs, __gsh;
297 unsigned short ldt, __ldth;
298 unsigned short trace, io_bitmap_base;
299 } __attribute__((packed));
302 struct i386_hw_tss x86_tss;
305 * The extra 1 is there because the CPU will access an
306 * additional byte beyond the end of the IO permission
307 * bitmap. The extra byte must be all 1 bits, and must
308 * be within the limit.
310 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
312 * Cache the current maximum and the last task that used the bitmap:
314 unsigned long io_bitmap_max;
315 struct thread_struct *io_bitmap_owner;
317 * pads the TSS to be cacheline-aligned (size is 0x100)
319 unsigned long __cacheline_filler[35];
321 * .. and then another 0x100 bytes for emergency kernel stack
323 unsigned long stack[64];
324 } __attribute__((packed));
326 #define ARCH_MIN_TASKALIGN 16
328 struct thread_struct {
329 /* cached TLS descriptors. */
330 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
332 unsigned long sysenter_cs;
337 /* Hardware debugging registers */
338 unsigned long debugreg0;
339 unsigned long debugreg1;
340 unsigned long debugreg2;
341 unsigned long debugreg3;
342 unsigned long debugreg6;
343 unsigned long debugreg7;
345 unsigned long cr2, trap_no, error_code;
346 /* floating point info */
347 union i387_union i387;
348 /* virtual 86 mode info */
349 struct vm86_struct __user * vm86_info;
350 unsigned long screen_bitmap;
351 unsigned long v86flags, v86mask, saved_sp0;
352 unsigned int saved_fs, saved_gs;
354 unsigned long *io_bitmap_ptr;
356 /* max allowed port in the bitmap, in bytes: */
357 unsigned long io_bitmap_max;
358 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
359 unsigned long debugctlmsr;
360 /* Debug Store - if not 0 points to a DS Save Area configuration;
361 * goes into MSR_IA32_DS_AREA */
362 unsigned long ds_area_msr;
365 #define INIT_THREAD { \
366 .sp0 = sizeof(init_stack) + (long)&init_stack, \
368 .sysenter_cs = __KERNEL_CS, \
369 .io_bitmap_ptr = NULL, \
370 .fs = __KERNEL_PERCPU, \
374 * Note that the .io_bitmap member must be extra-big. This is because
375 * the CPU will access an additional byte beyond the end of the IO
376 * permission bitmap. The extra byte must be all 1 bits, and must
377 * be within the limit.
381 .sp0 = sizeof(init_stack) + (long)&init_stack, \
382 .ss0 = __KERNEL_DS, \
383 .ss1 = __KERNEL_CS, \
384 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
386 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
389 #define start_thread(regs, new_eip, new_esp) do { \
390 __asm__("movl %0,%%gs": :"r" (0)); \
393 regs->ds = __USER_DS; \
394 regs->es = __USER_DS; \
395 regs->ss = __USER_DS; \
396 regs->cs = __USER_CS; \
397 regs->ip = new_eip; \
398 regs->sp = new_esp; \
401 /* Forward declaration, a strange C thing */
405 /* Free all resources held by a thread. */
406 extern void release_thread(struct task_struct *);
408 /* Prepare to copy thread state - unlazy all lazy status */
409 extern void prepare_to_copy(struct task_struct *tsk);
412 * create a kernel thread without removing it from tasklists
414 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
416 extern unsigned long thread_saved_pc(struct task_struct *tsk);
418 unsigned long get_wchan(struct task_struct *p);
420 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
421 #define KSTK_TOP(info) \
423 unsigned long *__ptr = (unsigned long *)(info); \
424 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
428 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
429 * This is necessary to guarantee that the entire "struct pt_regs"
430 * is accessable even if the CPU haven't stored the SS/ESP registers
431 * on the stack (interrupt gate does not save these registers
432 * when switching to the same priv ring).
433 * Therefore beware: accessing the ss/esp fields of the
434 * "struct pt_regs" is possible, but they may contain the
435 * completely wrong values.
437 #define task_pt_regs(task) \
439 struct pt_regs *__regs__; \
440 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
444 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
445 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
448 struct microcode_header {
456 unsigned int datasize;
457 unsigned int totalsize;
458 unsigned int reserved[3];
462 struct microcode_header hdr;
463 unsigned int bits[0];
466 typedef struct microcode microcode_t;
467 typedef struct microcode_header microcode_header_t;
469 /* microcode format is extended from prescott processors */
470 struct extended_signature {
476 struct extended_sigtable {
479 unsigned int reserved[3];
480 struct extended_signature sigs[0];
483 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
484 static inline void rep_nop(void)
486 __asm__ __volatile__("rep;nop": : :"memory");
489 #define cpu_relax() rep_nop()
491 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
493 tss->x86_tss.sp0 = thread->sp0;
494 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
495 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
496 tss->x86_tss.ss1 = thread->sysenter_cs;
497 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
502 static inline unsigned long native_get_debugreg(int regno)
504 unsigned long val = 0; /* Damn you, gcc! */
508 asm("movl %%db0, %0" :"=r" (val)); break;
510 asm("movl %%db1, %0" :"=r" (val)); break;
512 asm("movl %%db2, %0" :"=r" (val)); break;
514 asm("movl %%db3, %0" :"=r" (val)); break;
516 asm("movl %%db6, %0" :"=r" (val)); break;
518 asm("movl %%db7, %0" :"=r" (val)); break;
525 static inline void native_set_debugreg(int regno, unsigned long value)
529 asm("movl %0,%%db0" : /* no output */ :"r" (value));
532 asm("movl %0,%%db1" : /* no output */ :"r" (value));
535 asm("movl %0,%%db2" : /* no output */ :"r" (value));
538 asm("movl %0,%%db3" : /* no output */ :"r" (value));
541 asm("movl %0,%%db6" : /* no output */ :"r" (value));
544 asm("movl %0,%%db7" : /* no output */ :"r" (value));
552 * Set IOPL bits in EFLAGS from given mask
554 static inline void native_set_iopl_mask(unsigned mask)
557 __asm__ __volatile__ ("pushfl;"
564 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
567 #ifdef CONFIG_PARAVIRT
568 #include <asm/paravirt.h>
570 #define paravirt_enabled() 0
572 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
574 native_load_sp0(tss, thread);
578 * These special macros can be used to get or set a debugging register
580 #define get_debugreg(var, register) \
581 (var) = native_get_debugreg(register)
582 #define set_debugreg(value, register) \
583 native_set_debugreg(register, value)
585 #define set_iopl_mask native_set_iopl_mask
586 #endif /* CONFIG_PARAVIRT */
588 /* generic versions from gas */
589 #define GENERIC_NOP1 ".byte 0x90\n"
590 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
591 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
592 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
593 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
594 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
595 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
596 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
599 #define K8_NOP1 GENERIC_NOP1
600 #define K8_NOP2 ".byte 0x66,0x90\n"
601 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
602 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
603 #define K8_NOP5 K8_NOP3 K8_NOP2
604 #define K8_NOP6 K8_NOP3 K8_NOP3
605 #define K8_NOP7 K8_NOP4 K8_NOP3
606 #define K8_NOP8 K8_NOP4 K8_NOP4
609 /* uses eax dependencies (arbitary choice) */
610 #define K7_NOP1 GENERIC_NOP1
611 #define K7_NOP2 ".byte 0x8b,0xc0\n"
612 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
613 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
614 #define K7_NOP5 K7_NOP4 ASM_NOP1
615 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
616 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
617 #define K7_NOP8 K7_NOP7 ASM_NOP1
620 /* uses eax dependencies (Intel-recommended choice) */
621 #define P6_NOP1 GENERIC_NOP1
622 #define P6_NOP2 ".byte 0x66,0x90\n"
623 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
624 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
625 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
626 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
627 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
628 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
631 #define ASM_NOP1 K8_NOP1
632 #define ASM_NOP2 K8_NOP2
633 #define ASM_NOP3 K8_NOP3
634 #define ASM_NOP4 K8_NOP4
635 #define ASM_NOP5 K8_NOP5
636 #define ASM_NOP6 K8_NOP6
637 #define ASM_NOP7 K8_NOP7
638 #define ASM_NOP8 K8_NOP8
639 #elif defined(CONFIG_MK7)
640 #define ASM_NOP1 K7_NOP1
641 #define ASM_NOP2 K7_NOP2
642 #define ASM_NOP3 K7_NOP3
643 #define ASM_NOP4 K7_NOP4
644 #define ASM_NOP5 K7_NOP5
645 #define ASM_NOP6 K7_NOP6
646 #define ASM_NOP7 K7_NOP7
647 #define ASM_NOP8 K7_NOP8
648 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
649 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
650 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
651 #define ASM_NOP1 P6_NOP1
652 #define ASM_NOP2 P6_NOP2
653 #define ASM_NOP3 P6_NOP3
654 #define ASM_NOP4 P6_NOP4
655 #define ASM_NOP5 P6_NOP5
656 #define ASM_NOP6 P6_NOP6
657 #define ASM_NOP7 P6_NOP7
658 #define ASM_NOP8 P6_NOP8
660 #define ASM_NOP1 GENERIC_NOP1
661 #define ASM_NOP2 GENERIC_NOP2
662 #define ASM_NOP3 GENERIC_NOP3
663 #define ASM_NOP4 GENERIC_NOP4
664 #define ASM_NOP5 GENERIC_NOP5
665 #define ASM_NOP6 GENERIC_NOP6
666 #define ASM_NOP7 GENERIC_NOP7
667 #define ASM_NOP8 GENERIC_NOP8
670 #define ASM_NOP_MAX 8
672 /* Prefetch instructions for Pentium III and AMD Athlon */
673 /* It's not worth to care about 3dnow! prefetches for the K6
674 because they are microcoded there and very slow.
675 However we don't do prefetches for pre XP Athlons currently
676 That should be fixed. */
677 #define ARCH_HAS_PREFETCH
678 static inline void prefetch(const void *x)
680 alternative_input(ASM_NOP4,
686 #define ARCH_HAS_PREFETCH
687 #define ARCH_HAS_PREFETCHW
688 #define ARCH_HAS_SPINLOCK_PREFETCH
690 /* 3dnow! prefetch to get an exclusive cache line. Useful for
691 spinlocks to avoid one state transition in the cache coherency protocol. */
692 static inline void prefetchw(const void *x)
694 alternative_input(ASM_NOP4,
699 #define spin_lock_prefetch(x) prefetchw(x)
701 extern void select_idle_routine(const struct cpuinfo_x86 *c);
703 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
705 extern unsigned long boot_option_idle_override;
706 extern void enable_sep_cpu(void);
707 extern int sysenter_setup(void);
709 /* Defined in head.S */
710 extern struct desc_ptr early_gdt_descr;
712 extern void cpu_set_gdt(int);
713 extern void switch_to_new_gdt(void);
714 extern void cpu_init(void);
715 extern void init_gdt(int cpu);
717 extern int force_mwait;
719 #endif /* __ASM_I386_PROCESSOR_H */