1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeature.h>
18 #include <asm/system.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
23 #include <linux/personality.h>
24 #include <linux/cpumask.h>
25 #include <linux/cache.h>
26 #include <linux/threads.h>
27 #include <linux/init.h>
30 * Default implementation of macro that returns current
31 * instruction pointer ("program counter").
33 static inline void *current_text_addr(void)
36 asm volatile("mov $1f,%0\n1:":"=r" (pc));
40 #ifdef CONFIG_X86_VSMP
41 #define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
42 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
44 #define ARCH_MIN_TASKALIGN 16
45 #define ARCH_MIN_MMSTRUCT_ALIGN 0
49 * CPU type and hardware bug flags. Kept separately for each CPU.
50 * Members of this structure are referenced in head.S, so think twice
51 * before touching them. [mj]
55 __u8 x86; /* CPU family */
56 __u8 x86_vendor; /* CPU vendor */
60 char wp_works_ok; /* It doesn't on 386's */
61 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
69 /* number of 4K pages in DTLB/ITLB combined(in pages)*/
71 __u8 x86_virt_bits, x86_phys_bits;
72 /* cpuid returned core id bits */
74 /* Max extended CPUID function supported */
75 __u32 extended_cpuid_level;
77 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
78 __u32 x86_capability[NCAPINTS];
79 char x86_vendor_id[16];
80 char x86_model_id[64];
81 int x86_cache_size; /* in KB - valid for CPUS which support this
83 int x86_cache_alignment; /* In bytes */
85 unsigned long loops_per_jiffy;
87 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
89 unsigned char x86_max_cores; /* cpuid returned max cores value */
91 unsigned short x86_clflush_size;
93 unsigned char booted_cores; /* number of cores as seen by OS */
94 __u8 phys_proc_id; /* Physical processor id. */
95 __u8 cpu_core_id; /* Core id */
96 __u8 cpu_index; /* index into per_cpu list */
98 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
100 #define X86_VENDOR_INTEL 0
101 #define X86_VENDOR_CYRIX 1
102 #define X86_VENDOR_AMD 2
103 #define X86_VENDOR_UMC 3
104 #define X86_VENDOR_NEXGEN 4
105 #define X86_VENDOR_CENTAUR 5
106 #define X86_VENDOR_TRANSMETA 7
107 #define X86_VENDOR_NSC 8
108 #define X86_VENDOR_NUM 9
109 #define X86_VENDOR_UNKNOWN 0xff
112 * capabilities of CPUs
114 extern struct cpuinfo_x86 boot_cpu_data;
115 extern struct cpuinfo_x86 new_cpu_data;
116 extern struct tss_struct doublefault_tss;
119 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
120 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
121 #define current_cpu_data cpu_data(smp_processor_id())
123 #define cpu_data(cpu) boot_cpu_data
124 #define current_cpu_data boot_cpu_data
127 void cpu_detect(struct cpuinfo_x86 *c);
129 extern void identify_cpu(struct cpuinfo_x86 *);
130 extern void identify_boot_cpu(void);
131 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
132 extern void print_cpu_info(struct cpuinfo_x86 *);
133 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
134 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
135 extern unsigned short num_cache_leaves;
137 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
138 extern void detect_ht(struct cpuinfo_x86 *c);
140 static inline void detect_ht(struct cpuinfo_x86 *c) {}
143 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
144 unsigned int *ecx, unsigned int *edx)
146 /* ecx is often an input as well as an output. */
152 : "0" (*eax), "2" (*ecx));
155 static inline void load_cr3(pgd_t *pgdir)
157 write_cr3(__pa(pgdir));
161 /* This is the TSS defined by the hardware. */
163 unsigned short back_link, __blh;
165 unsigned short ss0, __ss0h;
167 unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
169 unsigned short ss2, __ss2h;
173 unsigned long ax, cx, dx, bx;
174 unsigned long sp, bp, si, di;
175 unsigned short es, __esh;
176 unsigned short cs, __csh;
177 unsigned short ss, __ssh;
178 unsigned short ds, __dsh;
179 unsigned short fs, __fsh;
180 unsigned short gs, __gsh;
181 unsigned short ldt, __ldth;
182 unsigned short trace, io_bitmap_base;
183 } __attribute__((packed));
196 } __attribute__((packed)) ____cacheline_aligned;
202 #define IO_BITMAP_BITS 65536
203 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
204 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
205 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
206 #define INVALID_IO_BITMAP_OFFSET 0x8000
207 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
210 struct x86_hw_tss x86_tss;
213 * The extra 1 is there because the CPU will access an
214 * additional byte beyond the end of the IO permission
215 * bitmap. The extra byte must be all 1 bits, and must
216 * be within the limit.
218 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
220 * Cache the current maximum and the last task that used the bitmap:
222 unsigned long io_bitmap_max;
223 struct thread_struct *io_bitmap_owner;
225 * pads the TSS to be cacheline-aligned (size is 0x100)
227 unsigned long __cacheline_filler[35];
229 * .. and then another 0x100 bytes for emergency kernel stack
231 unsigned long stack[64];
232 } __attribute__((packed));
234 DECLARE_PER_CPU(struct tss_struct, init_tss);
236 /* Save the original ist values for checking stack pointers during debugging */
238 unsigned long ist[7];
241 #define MXCSR_DEFAULT 0x1f80
243 struct i387_fsave_struct {
251 u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
252 u32 status; /* software status information */
255 struct i387_fxsave_struct {
274 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
275 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
277 } __attribute__((aligned(16)));
279 struct i387_soft_struct {
287 u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
288 u8 ftop, changed, lookahead, no_update, rm, alimit;
294 struct i387_fsave_struct fsave;
295 struct i387_fxsave_struct fxsave;
296 struct i387_soft_struct soft;
301 * the following now lives in the per cpu area:
302 * extern int cpu_llc_id[NR_CPUS];
304 DECLARE_PER_CPU(u8, cpu_llc_id);
306 DECLARE_PER_CPU(struct orig_ist, orig_ist);
309 extern void print_cpu_info(struct cpuinfo_x86 *);
310 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
311 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
312 extern unsigned short num_cache_leaves;
314 struct thread_struct {
315 /* cached TLS descriptors. */
316 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
320 unsigned long sysenter_cs;
322 unsigned long usersp; /* Copy from PDA */
323 unsigned short es, ds, fsindex, gsindex;
328 /* Hardware debugging registers */
329 unsigned long debugreg0;
330 unsigned long debugreg1;
331 unsigned long debugreg2;
332 unsigned long debugreg3;
333 unsigned long debugreg6;
334 unsigned long debugreg7;
336 unsigned long cr2, trap_no, error_code;
337 /* floating point info */
338 union i387_union i387 __attribute__((aligned(16)));;
340 /* virtual 86 mode info */
341 struct vm86_struct __user *vm86_info;
342 unsigned long screen_bitmap;
343 unsigned long v86flags, v86mask, saved_sp0;
344 unsigned int saved_fs, saved_gs;
347 unsigned long *io_bitmap_ptr;
349 /* max allowed port in the bitmap, in bytes: */
350 unsigned io_bitmap_max;
351 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
352 unsigned long debugctlmsr;
353 /* Debug Store - if not 0 points to a DS Save Area configuration;
354 * goes into MSR_IA32_DS_AREA */
355 unsigned long ds_area_msr;
358 static inline unsigned long native_get_debugreg(int regno)
360 unsigned long val = 0; /* Damn you, gcc! */
364 asm("mov %%db0, %0" :"=r" (val)); break;
366 asm("mov %%db1, %0" :"=r" (val)); break;
368 asm("mov %%db2, %0" :"=r" (val)); break;
370 asm("mov %%db3, %0" :"=r" (val)); break;
372 asm("mov %%db6, %0" :"=r" (val)); break;
374 asm("mov %%db7, %0" :"=r" (val)); break;
381 static inline void native_set_debugreg(int regno, unsigned long value)
385 asm("mov %0,%%db0" : /* no output */ :"r" (value));
388 asm("mov %0,%%db1" : /* no output */ :"r" (value));
391 asm("mov %0,%%db2" : /* no output */ :"r" (value));
394 asm("mov %0,%%db3" : /* no output */ :"r" (value));
397 asm("mov %0,%%db6" : /* no output */ :"r" (value));
400 asm("mov %0,%%db7" : /* no output */ :"r" (value));
408 * Set IOPL bits in EFLAGS from given mask
410 static inline void native_set_iopl_mask(unsigned mask)
414 __asm__ __volatile__ ("pushfl;"
421 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
425 static inline void native_load_sp0(struct tss_struct *tss,
426 struct thread_struct *thread)
428 tss->x86_tss.sp0 = thread->sp0;
430 /* Only happens when SEP is enabled, no need to test "SEP"arately */
431 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
432 tss->x86_tss.ss1 = thread->sysenter_cs;
433 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
438 #ifdef CONFIG_PARAVIRT
439 #include <asm/paravirt.h>
441 #define __cpuid native_cpuid
442 #define paravirt_enabled() 0
445 * These special macros can be used to get or set a debugging register
447 #define get_debugreg(var, register) \
448 (var) = native_get_debugreg(register)
449 #define set_debugreg(value, register) \
450 native_set_debugreg(register, value)
452 static inline void load_sp0(struct tss_struct *tss,
453 struct thread_struct *thread)
455 native_load_sp0(tss, thread);
458 #define set_iopl_mask native_set_iopl_mask
459 #endif /* CONFIG_PARAVIRT */
462 * Save the cr4 feature set we're using (ie
463 * Pentium 4MB enable and PPro Global page
464 * enable), so that any CPU's that boot up
465 * after us can get the correct flags.
467 extern unsigned long mmu_cr4_features;
469 static inline void set_in_cr4(unsigned long mask)
472 mmu_cr4_features |= mask;
478 static inline void clear_in_cr4(unsigned long mask)
481 mmu_cr4_features &= ~mask;
487 struct microcode_header {
495 unsigned int datasize;
496 unsigned int totalsize;
497 unsigned int reserved[3];
501 struct microcode_header hdr;
502 unsigned int bits[0];
505 typedef struct microcode microcode_t;
506 typedef struct microcode_header microcode_header_t;
508 /* microcode format is extended from prescott processors */
509 struct extended_signature {
515 struct extended_sigtable {
518 unsigned int reserved[3];
519 struct extended_signature sigs[0];
528 * create a kernel thread without removing it from tasklists
530 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
532 /* Free all resources held by a thread. */
533 extern void release_thread(struct task_struct *);
535 /* Prepare to copy thread state - unlazy all lazy status */
536 extern void prepare_to_copy(struct task_struct *tsk);
538 unsigned long get_wchan(struct task_struct *p);
541 * Generic CPUID function
542 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
543 * resulting in stale register contents being returned.
545 static inline void cpuid(unsigned int op,
546 unsigned int *eax, unsigned int *ebx,
547 unsigned int *ecx, unsigned int *edx)
551 __cpuid(eax, ebx, ecx, edx);
554 /* Some CPUID calls want 'count' to be placed in ecx */
555 static inline void cpuid_count(unsigned int op, int count,
556 unsigned int *eax, unsigned int *ebx,
557 unsigned int *ecx, unsigned int *edx)
561 __cpuid(eax, ebx, ecx, edx);
565 * CPUID functions returning a single datum
567 static inline unsigned int cpuid_eax(unsigned int op)
569 unsigned int eax, ebx, ecx, edx;
571 cpuid(op, &eax, &ebx, &ecx, &edx);
574 static inline unsigned int cpuid_ebx(unsigned int op)
576 unsigned int eax, ebx, ecx, edx;
578 cpuid(op, &eax, &ebx, &ecx, &edx);
581 static inline unsigned int cpuid_ecx(unsigned int op)
583 unsigned int eax, ebx, ecx, edx;
585 cpuid(op, &eax, &ebx, &ecx, &edx);
588 static inline unsigned int cpuid_edx(unsigned int op)
590 unsigned int eax, ebx, ecx, edx;
592 cpuid(op, &eax, &ebx, &ecx, &edx);
596 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
597 static inline void rep_nop(void)
599 __asm__ __volatile__("rep;nop": : :"memory");
602 /* Stop speculative execution */
603 static inline void sync_core(void)
606 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
607 : "ebx", "ecx", "edx", "memory");
610 #define cpu_relax() rep_nop()
612 static inline void __monitor(const void *eax, unsigned long ecx,
615 /* "monitor %eax,%ecx,%edx;" */
617 ".byte 0x0f,0x01,0xc8;"
618 : :"a" (eax), "c" (ecx), "d"(edx));
621 static inline void __mwait(unsigned long eax, unsigned long ecx)
623 /* "mwait %eax,%ecx;" */
625 ".byte 0x0f,0x01,0xc9;"
626 : :"a" (eax), "c" (ecx));
629 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
631 /* "mwait %eax,%ecx;" */
633 "sti; .byte 0x0f,0x01,0xc9;"
634 : :"a" (eax), "c" (ecx));
637 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
639 extern int force_mwait;
641 extern void select_idle_routine(const struct cpuinfo_x86 *c);
643 extern unsigned long boot_option_idle_override;
645 extern void enable_sep_cpu(void);
646 extern int sysenter_setup(void);
648 /* Defined in head.S */
649 extern struct desc_ptr early_gdt_descr;
651 extern void cpu_set_gdt(int);
652 extern void switch_to_new_gdt(void);
653 extern void cpu_init(void);
654 extern void init_gdt(int cpu);
656 /* from system description table in BIOS. Mostly for MCA use, but
657 * others may find it useful. */
658 extern unsigned int machine_id;
659 extern unsigned int machine_submodel_id;
660 extern unsigned int BIOS_revision;
661 extern unsigned int mca_pentium_flag;
663 /* Boot loader type from the setup header */
664 extern int bootloader_type;
666 extern char ignore_fpu_irq;
667 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
669 /* generic versions from gas */
670 #define GENERIC_NOP1 ".byte 0x90\n"
671 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
672 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
673 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
674 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
675 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
676 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
677 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
680 #define K8_NOP1 GENERIC_NOP1
681 #define K8_NOP2 ".byte 0x66,0x90\n"
682 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
683 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
684 #define K8_NOP5 K8_NOP3 K8_NOP2
685 #define K8_NOP6 K8_NOP3 K8_NOP3
686 #define K8_NOP7 K8_NOP4 K8_NOP3
687 #define K8_NOP8 K8_NOP4 K8_NOP4
690 /* uses eax dependencies (arbitary choice) */
691 #define K7_NOP1 GENERIC_NOP1
692 #define K7_NOP2 ".byte 0x8b,0xc0\n"
693 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
694 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
695 #define K7_NOP5 K7_NOP4 ASM_NOP1
696 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
697 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
698 #define K7_NOP8 K7_NOP7 ASM_NOP1
701 /* uses eax dependencies (Intel-recommended choice) */
702 #define P6_NOP1 GENERIC_NOP1
703 #define P6_NOP2 ".byte 0x66,0x90\n"
704 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
705 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
706 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
707 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
708 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
709 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
712 #define ASM_NOP1 K7_NOP1
713 #define ASM_NOP2 K7_NOP2
714 #define ASM_NOP3 K7_NOP3
715 #define ASM_NOP4 K7_NOP4
716 #define ASM_NOP5 K7_NOP5
717 #define ASM_NOP6 K7_NOP6
718 #define ASM_NOP7 K7_NOP7
719 #define ASM_NOP8 K7_NOP8
720 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
721 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
722 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4) || \
724 #define ASM_NOP1 P6_NOP1
725 #define ASM_NOP2 P6_NOP2
726 #define ASM_NOP3 P6_NOP3
727 #define ASM_NOP4 P6_NOP4
728 #define ASM_NOP5 P6_NOP5
729 #define ASM_NOP6 P6_NOP6
730 #define ASM_NOP7 P6_NOP7
731 #define ASM_NOP8 P6_NOP8
732 #elif defined(CONFIG_MK8) || defined(CONFIG_X86_64)
733 #define ASM_NOP1 K8_NOP1
734 #define ASM_NOP2 K8_NOP2
735 #define ASM_NOP3 K8_NOP3
736 #define ASM_NOP4 K8_NOP4
737 #define ASM_NOP5 K8_NOP5
738 #define ASM_NOP6 K8_NOP6
739 #define ASM_NOP7 K8_NOP7
740 #define ASM_NOP8 K8_NOP8
742 #define ASM_NOP1 GENERIC_NOP1
743 #define ASM_NOP2 GENERIC_NOP2
744 #define ASM_NOP3 GENERIC_NOP3
745 #define ASM_NOP4 GENERIC_NOP4
746 #define ASM_NOP5 GENERIC_NOP5
747 #define ASM_NOP6 GENERIC_NOP6
748 #define ASM_NOP7 GENERIC_NOP7
749 #define ASM_NOP8 GENERIC_NOP8
752 #define ASM_NOP_MAX 8
754 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
755 #define ARCH_HAS_PREFETCHW
756 #define ARCH_HAS_SPINLOCK_PREFETCH
759 #define BASE_PREFETCH ASM_NOP4
760 #define ARCH_HAS_PREFETCH
762 #define BASE_PREFETCH "prefetcht0 (%1)"
765 /* Prefetch instructions for Pentium III and AMD Athlon */
766 /* It's not worth to care about 3dnow! prefetches for the K6
767 because they are microcoded there and very slow.
768 However we don't do prefetches for pre XP Athlons currently
769 That should be fixed. */
770 static inline void prefetch(const void *x)
772 alternative_input(BASE_PREFETCH,
778 /* 3dnow! prefetch to get an exclusive cache line. Useful for
779 spinlocks to avoid one state transition in the cache coherency protocol. */
780 static inline void prefetchw(const void *x)
782 alternative_input(BASE_PREFETCH,
788 #define spin_lock_prefetch(x) prefetchw(x)
791 * User space process size: 3GB (default).
793 #define TASK_SIZE (PAGE_OFFSET)
795 #define INIT_THREAD { \
796 .sp0 = sizeof(init_stack) + (long)&init_stack, \
798 .sysenter_cs = __KERNEL_CS, \
799 .io_bitmap_ptr = NULL, \
800 .fs = __KERNEL_PERCPU, \
804 * Note that the .io_bitmap member must be extra-big. This is because
805 * the CPU will access an additional byte beyond the end of the IO
806 * permission bitmap. The extra byte must be all 1 bits, and must
807 * be within the limit.
811 .sp0 = sizeof(init_stack) + (long)&init_stack, \
812 .ss0 = __KERNEL_DS, \
813 .ss1 = __KERNEL_CS, \
814 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
816 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
819 #define start_thread(regs, new_eip, new_esp) do { \
820 __asm__("movl %0,%%gs": :"r" (0)); \
823 regs->ds = __USER_DS; \
824 regs->es = __USER_DS; \
825 regs->ss = __USER_DS; \
826 regs->cs = __USER_CS; \
827 regs->ip = new_eip; \
828 regs->sp = new_esp; \
832 extern unsigned long thread_saved_pc(struct task_struct *tsk);
834 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
835 #define KSTK_TOP(info) \
837 unsigned long *__ptr = (unsigned long *)(info); \
838 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
842 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
843 * This is necessary to guarantee that the entire "struct pt_regs"
844 * is accessable even if the CPU haven't stored the SS/ESP registers
845 * on the stack (interrupt gate does not save these registers
846 * when switching to the same priv ring).
847 * Therefore beware: accessing the ss/esp fields of the
848 * "struct pt_regs" is possible, but they may contain the
849 * completely wrong values.
851 #define task_pt_regs(task) \
853 struct pt_regs *__regs__; \
854 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
858 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
862 * User space process size. 47bits minus one guard page.
864 #define TASK_SIZE64 (0x800000000000UL - 4096)
866 /* This decides where the kernel will search for a free chunk of vm
867 * space during mmap's.
869 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
870 0xc0000000 : 0xFFFFe000)
872 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
873 IA32_PAGE_OFFSET : TASK_SIZE64)
874 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
875 IA32_PAGE_OFFSET : TASK_SIZE64)
877 #define INIT_THREAD { \
878 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
882 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
885 #define start_thread(regs, new_rip, new_rsp) do { \
886 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
888 (regs)->ip = (new_rip); \
889 (regs)->sp = (new_rsp); \
890 write_pda(oldrsp, (new_rsp)); \
891 (regs)->cs = __USER_CS; \
892 (regs)->ss = __USER_DS; \
893 (regs)->flags = 0x200; \
898 * Return saved PC of a blocked thread.
899 * What is this good for? it will be always the scheduler or ret_from_fork.
901 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
903 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
904 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
905 #endif /* CONFIG_X86_64 */
907 /* This decides where the kernel will search for a free chunk of vm
908 * space during mmap's.
910 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
912 #define KSTK_EIP(task) (task_pt_regs(task)->ip)