x86: unify msr smp funcs
[sfrench/cifs-2.6.git] / include / asm-x86 / msr.h
1 #ifndef __ASM_X86_MSR_H_
2 #define __ASM_X86_MSR_H_
3
4 #include <asm/msr-index.h>
5
6 #ifndef __ASSEMBLY__
7 # include <linux/types.h>
8 #endif
9
10 #ifdef __i386__
11
12 #ifdef __KERNEL__
13 #ifndef __ASSEMBLY__
14
15 #include <asm/errno.h>
16
17 static inline unsigned long long native_read_msr(unsigned int msr)
18 {
19         unsigned long long val;
20
21         asm volatile("rdmsr" : "=A" (val) : "c" (msr));
22         return val;
23 }
24
25 static inline unsigned long long native_read_msr_safe(unsigned int msr,
26                                                       int *err)
27 {
28         unsigned long long val;
29
30         asm volatile("2: rdmsr ; xorl %0,%0\n"
31                      "1:\n\t"
32                      ".section .fixup,\"ax\"\n\t"
33                      "3:  movl %3,%0 ; jmp 1b\n\t"
34                      ".previous\n\t"
35                      ".section __ex_table,\"a\"\n"
36                      "   .align 4\n\t"
37                      "   .long  2b,3b\n\t"
38                      ".previous"
39                      : "=r" (*err), "=A" (val)
40                      : "c" (msr), "i" (-EFAULT));
41
42         return val;
43 }
44
45 static inline void native_write_msr(unsigned int msr, unsigned long long val)
46 {
47         asm volatile("wrmsr" : : "c" (msr), "A"(val));
48 }
49
50 static inline int native_write_msr_safe(unsigned int msr,
51                                         unsigned long long val)
52 {
53         int err;
54         asm volatile("2: wrmsr ; xorl %0,%0\n"
55                      "1:\n\t"
56                      ".section .fixup,\"ax\"\n\t"
57                      "3:  movl %4,%0 ; jmp 1b\n\t"
58                      ".previous\n\t"
59                      ".section __ex_table,\"a\"\n"
60                      "   .align 4\n\t"
61                      "   .long  2b,3b\n\t"
62                      ".previous"
63                      : "=a" (err)
64                      : "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
65                        "i" (-EFAULT));
66         return err;
67 }
68
69 static inline unsigned long long native_read_tsc(void)
70 {
71         unsigned long long val;
72         asm volatile("rdtsc" : "=A" (val));
73         return val;
74 }
75
76 static inline unsigned long long native_read_pmc(void)
77 {
78         unsigned long long val;
79         asm volatile("rdpmc" : "=A" (val));
80         return val;
81 }
82
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
85 #else
86 #include <linux/errno.h>
87 /*
88  * Access to machine-specific registers (available on 586 and better only)
89  * Note: the rd* operations modify the parameters directly (without using
90  * pointer indirection), this allows gcc to optimize better
91  */
92
93 #define rdmsr(msr,val1,val2)                                            \
94         do {                                                            \
95                 u64 __val = native_read_msr(msr);                       \
96                 (val1) = (u32)__val;                                    \
97                 (val2) = (u32)(__val >> 32);                            \
98         } while(0)
99
100 static inline void wrmsr(u32 __msr, u32 __low, u32 __high)
101 {
102         native_write_msr(__msr, ((u64)__high << 32) | __low);
103 }
104
105 #define rdmsrl(msr,val)                                                 \
106         ((val) = native_read_msr(msr))
107
108 #define wrmsrl(msr,val) native_write_msr(msr, val)
109
110 /* wrmsr with exception handling */
111 static inline int wrmsr_safe(u32 __msr, u32 __low, u32 __high)
112 {
113         return native_write_msr_safe(__msr, ((u64)__high << 32) | __low);
114 }
115
116 /* rdmsr with exception handling */
117 #define rdmsr_safe(msr,p1,p2)                                           \
118         ({                                                              \
119                 int __err;                                              \
120                 u64 __val = native_read_msr_safe(msr, &__err);          \
121                 (*p1) = (u32)__val;                                     \
122                 (*p2) = (u32)(__val >> 32);                             \
123                 __err;                                                  \
124         })
125
126 #define rdtscl(low)                                             \
127         ((low) = (u32)native_read_tsc())
128
129 #define rdtscll(val)                                            \
130         ((val) = native_read_tsc())
131
132 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
133
134 #define rdpmc(counter,low,high)                                 \
135         do {                                                    \
136                 u64 _l = native_read_pmc();                     \
137                 (low)  = (u32)_l;                               \
138                 (high) = (u32)(_l >> 32);                       \
139         } while(0)
140 #endif  /* !CONFIG_PARAVIRT */
141
142 #endif  /* ! __ASSEMBLY__ */
143 #endif  /* __KERNEL__ */
144
145 #else   /* __i386__ */
146
147 #ifndef __ASSEMBLY__
148 #include <linux/errno.h>
149 /*
150  * Access to machine-specific registers (available on 586 and better only)
151  * Note: the rd* operations modify the parameters directly (without using
152  * pointer indirection), this allows gcc to optimize better
153  */
154
155 #define rdmsr(msr,val1,val2) \
156        __asm__ __volatile__("rdmsr" \
157                             : "=a" (val1), "=d" (val2) \
158                             : "c" (msr))
159
160
161 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
162        __asm__ __volatile__("rdmsr" \
163                             : "=a" (a__), "=d" (b__) \
164                             : "c" (msr)); \
165        val = a__ | (b__<<32); \
166 } while(0)
167
168 #define wrmsr(msr,val1,val2) \
169      __asm__ __volatile__("wrmsr" \
170                           : /* no outputs */ \
171                           : "c" (msr), "a" (val1), "d" (val2))
172
173 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
174
175 #define rdtsc(low,high) \
176      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
177
178 #define rdtscl(low) \
179      __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
180
181 #define rdtscp(low,high,aux) \
182      __asm__ __volatile__ (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
183
184 #define rdtscll(val) do { \
185      unsigned int __a,__d; \
186      __asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
187      (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
188 } while(0)
189
190 #define rdtscpll(val, aux) do { \
191      unsigned long __a, __d; \
192      __asm__ __volatile__ (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
193      (val) = (__d << 32) | __a; \
194 } while (0)
195
196 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
197
198 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
199
200 #define rdpmc(counter,low,high) \
201      __asm__ __volatile__("rdpmc" \
202                           : "=a" (low), "=d" (high) \
203                           : "c" (counter))
204
205
206 static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
207                          unsigned int *ecx, unsigned int *edx)
208 {
209         __asm__("cpuid"
210                 : "=a" (*eax),
211                   "=b" (*ebx),
212                   "=c" (*ecx),
213                   "=d" (*edx)
214                 : "0" (op));
215 }
216
217 /* Some CPUID calls want 'count' to be placed in ecx */
218 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
219                                int *edx)
220 {
221         __asm__("cpuid"
222                 : "=a" (*eax),
223                   "=b" (*ebx),
224                   "=c" (*ecx),
225                   "=d" (*edx)
226                 : "0" (op), "c" (count));
227 }
228
229 /*
230  * CPUID functions returning a single datum
231  */
232 static inline unsigned int cpuid_eax(unsigned int op)
233 {
234         unsigned int eax;
235
236         __asm__("cpuid"
237                 : "=a" (eax)
238                 : "0" (op)
239                 : "bx", "cx", "dx");
240         return eax;
241 }
242 static inline unsigned int cpuid_ebx(unsigned int op)
243 {
244         unsigned int eax, ebx;
245
246         __asm__("cpuid"
247                 : "=a" (eax), "=b" (ebx)
248                 : "0" (op)
249                 : "cx", "dx" );
250         return ebx;
251 }
252 static inline unsigned int cpuid_ecx(unsigned int op)
253 {
254         unsigned int eax, ecx;
255
256         __asm__("cpuid"
257                 : "=a" (eax), "=c" (ecx)
258                 : "0" (op)
259                 : "bx", "dx" );
260         return ecx;
261 }
262 static inline unsigned int cpuid_edx(unsigned int op)
263 {
264         unsigned int eax, edx;
265
266         __asm__("cpuid"
267                 : "=a" (eax), "=d" (edx)
268                 : "0" (op)
269                 : "bx", "cx");
270         return edx;
271 }
272
273 #ifdef __KERNEL__
274
275 /* wrmsr with exception handling */
276 #define wrmsr_safe(msr,a,b) ({ int ret__;                       \
277         asm volatile("2: wrmsr ; xorl %0,%0\n"                  \
278                      "1:\n\t"                                   \
279                      ".section .fixup,\"ax\"\n\t"               \
280                      "3:  movl %4,%0 ; jmp 1b\n\t"              \
281                      ".previous\n\t"                            \
282                      ".section __ex_table,\"a\"\n"              \
283                      "   .align 8\n\t"                          \
284                      "   .quad  2b,3b\n\t"                      \
285                      ".previous"                                \
286                      : "=a" (ret__)                             \
287                      : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
288         ret__; })
289
290 #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
291
292 #define rdmsr_safe(msr,a,b) \
293         ({ int ret__;                                           \
294           asm volatile ("1:       rdmsr\n"                      \
295                         "2:\n"                                  \
296                         ".section .fixup,\"ax\"\n"              \
297                         "3:       movl %4,%0\n"                 \
298                         " jmp 2b\n"                             \
299                         ".previous\n"                           \
300                         ".section __ex_table,\"a\"\n"           \
301                         " .align 8\n"                           \
302                         " .quad 1b,3b\n"                                \
303                         ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
304                         :"c"(msr), "i"(-EIO), "0"(0));                  \
305           ret__; })
306
307 #endif  /* __ASSEMBLY__ */
308
309 #endif  /* !__i386__ */
310
311 #ifndef __ASSEMBLY__
312
313 #ifdef CONFIG_SMP
314 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
315 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
316 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
317 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
318 #else  /*  CONFIG_SMP  */
319 static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
320 {
321         rdmsr(msr_no, *l, *h);
322 }
323 static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
324 {
325         wrmsr(msr_no, l, h);
326 }
327 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
328 {
329         return rdmsr_safe(msr_no, l, h);
330 }
331 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
332 {
333         return wrmsr_safe(msr_no, l, h);
334 }
335 #endif  /* CONFIG_SMP */
336 #endif  /* __KERNEL__ */
337 #endif /* __ASSEMBLY__ */
338
339 #endif