1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
76 #define HV_ECHANNEL 16 /* Invalid LDC channel */
77 #define HV_EBUSY 17 /* Resource busy */
81 * FUNCTION: HV_FAST_MACH_EXIT
83 * ERRORS: This service does not return.
85 * Stop all CPUs in the virtual domain and place them into the stopped
86 * state. The 64-bit exit code may be passed to a service entity as
87 * the domain's exit status. On systems without a service entity, the
88 * domain will undergo a reset, and the boot firmware will be
91 * This function will never return to the guest that invokes it.
93 * Note: By convention an exit code of zero denotes a successful exit by
94 * the guest code. A non-zero exit code denotes a guest specific
98 #define HV_FAST_MACH_EXIT 0x00
101 extern void sun4v_mach_exit(unsigned long exit_core);
104 /* Domain services. */
108 * FUNCTION: HV_FAST_MACH_DESC
113 * ERRORS: HV_EBADALIGN Buffer is badly aligned
114 * HV_ENORADDR Buffer is to an illegal real address.
115 * HV_EINVAL Buffer length is too small for complete
116 * machine description.
118 * Copy the most current machine description into the buffer indicated
119 * by the real address in ARG0. The buffer provided must be 16 byte
120 * aligned. Upon success or HV_EINVAL, this service returns the
121 * actual size of the machine description in the RET1 return value.
123 * Note: A method of determining the appropriate buffer size for the
124 * machine description is to first call this service with a buffer
127 #define HV_FAST_MACH_DESC 0x01
130 extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131 unsigned long buf_len,
132 unsigned long *real_buf_len);
137 * FUNCTION: HV_FAST_MACH_SIR
138 * ERRORS: This service does not return.
140 * Perform a software initiated reset of the virtual machine domain.
141 * All CPUs are captured as soon as possible, all hardware devices are
142 * returned to the entry default state, and the domain is restarted at
143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
144 * of the CPUs. The single CPU restarted is selected as determined by
145 * platform specific policy. Memory is preserved across this
148 #define HV_FAST_MACH_SIR 0x02
151 extern void sun4v_mach_sir(void);
154 /* mach_set_watchdog()
156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
157 * ARG0: timeout in milliseconds
159 * RET1: time remaining in milliseconds
161 * A guest uses this API to set a watchdog timer. Once the gues has set
162 * the timer, it must call the timer service again either to disable or
163 * postpone the expiration. If the timer expires before being reset or
164 * disabled, then the hypervisor take a platform specific action leading
165 * to guest termination within a bounded time period. The platform action
166 * may include recovery actions such as reporting the expiration to a
167 * Service Processor, and/or automatically restarting the gues.
169 * The 'timeout' parameter is specified in milliseconds, however the
170 * implementated granularity is given by the 'watchdog-resolution'
171 * property in the 'platform' node of the guest's machine description.
172 * The largest allowed timeout value is specified by the
173 * 'watchdog-max-timeout' property of the 'platform' node.
175 * If the 'timeout' argument is not zero, the watchdog timer is set to
176 * expire after a minimum of 'timeout' milliseconds.
178 * If the 'timeout' argument is zero, the watchdog timer is disabled.
180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181 * property, the hypervisor leaves the watchdog timer state unchanged,
182 * and returns a status of EINVAL.
184 * The 'time remaining' return value is valid regardless of whether the
185 * return status is EOK or EINVAL. A non-zero return value indicates the
186 * number of milliseconds that were remaining until the timer was to expire.
187 * If less than one millisecond remains, the return value is '1'. If the
188 * watchdog timer was disabled at the time of the call, the return value is
191 * If the hypervisor cannot support the exact timeout value requested, but
192 * can support a larger timeout value, the hypervisor may round the actual
193 * timeout to a value larger than the requested timeout, consequently the
194 * 'time remaining' return value may be larger than the previously requested
197 * Any guest OS debugger should be aware that the watchdog service may be in
198 * use. Consequently, it is recommended that the watchdog service is
199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200 * re-enabled upon returning to normal execution. The API has been designed
201 * with this in mind, and the 'time remaining' result of the disable call may
202 * be used directly as the timeout argument of the re-enable call.
204 #define HV_FAST_MACH_SET_WATCHDOG 0x05
207 extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
208 unsigned long *orig_timeout);
213 * CPUs represent devices that can execute software threads. A single
214 * chip that contains multiple cores or strands is represented as
215 * multiple CPUs with unique CPU identifiers. CPUs are exported to
216 * OBP via the machine description (and to the OS via the OBP device
217 * tree). CPUs are always in one of three states: stopped, running,
220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
221 * CPU within a logical domain. Operations that are to be performed
222 * on multiple CPUs specify them via a CPU list. A CPU list is an
223 * array in real memory, of which each 16-bit word is a CPU ID. CPU
224 * lists are passed through the API as two arguments. The first is
225 * the number of entries (16-bit words) in the CPU list, and the
226 * second is the (real address) pointer to the CPU ID list.
231 * FUNCTION: HV_FAST_CPU_START
237 * ERRORS: ENOCPU Invalid CPU ID
238 * EINVAL Target CPU ID is not in the stopped state
239 * ENORADDR Invalid PC or RTBA real address
240 * EBADALIGN Unaligned PC or unaligned RTBA
241 * EWOULDBLOCK Starting resources are not available
243 * Start CPU with given CPU ID with PC in %pc and with a real trap
244 * base address value of RTBA. The indicated CPU must be in the
245 * stopped state. The supplied RTBA must be aligned on a 256 byte
246 * boundary. On successful completion, the specified CPU will be in
247 * the running state and will be supplied with "target ARG0" in %o0
250 #define HV_FAST_CPU_START 0x10
253 extern unsigned long sun4v_cpu_start(unsigned long cpuid,
261 * FUNCTION: HV_FAST_CPU_STOP
264 * ERRORS: ENOCPU Invalid CPU ID
265 * EINVAL Target CPU ID is the current cpu
266 * EINVAL Target CPU ID is not in the running state
267 * EWOULDBLOCK Stopping resources are not available
268 * ENOTSUPPORTED Not supported on this platform
270 * The specified CPU is stopped. The indicated CPU must be in the
271 * running state. On completion, it will be in the stopped state. It
272 * is not legal to stop the current CPU.
274 * Note: As this service cannot be used to stop the current cpu, this service
275 * may not be used to stop the last running CPU in a domain. To stop
276 * and exit a running domain, a guest must use the mach_exit() service.
278 #define HV_FAST_CPU_STOP 0x11
281 extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
286 * FUNCTION: HV_FAST_CPU_YIELD
288 * ERRORS: No possible error.
290 * Suspend execution on the current CPU. Execution will resume when
291 * an interrupt (device, %stick_compare, or cross-call) is targeted to
292 * the CPU. On some CPUs, this API may be used by the hypervisor to
293 * save power by disabling hardware strands.
295 #define HV_FAST_CPU_YIELD 0x12
298 extern unsigned long sun4v_cpu_yield(void);
303 * FUNCTION: HV_FAST_CPU_QCONF
305 * ARG1: base real address
306 * ARG2: number of entries
308 * ERRORS: ENORADDR Invalid base real address
309 * EINVAL Invalid queue or number of entries is less
310 * than 2 or too large.
311 * EBADALIGN Base real address is not correctly aligned
314 * Configure the given queue to be placed at the given base real
315 * address, with the given number of entries. The number of entries
316 * must be a power of 2. The base real address must be aligned
317 * exactly to match the queue size. Each queue entry is 64 bytes
318 * long, so for example a 32 entry queue must be aligned on a 2048
319 * byte real address boundary.
321 * The specified queue is unconfigured if the number of entries is given
324 * For the current version of this API service, the argument queue is defined
328 * ----- -------------------------
329 * 0x3c cpu mondo queue
330 * 0x3d device mondo queue
331 * 0x3e resumable error queue
332 * 0x3f non-resumable error queue
334 * Note: The maximum number of entries for each queue for a specific cpu may
335 * be determined from the machine description.
337 #define HV_FAST_CPU_QCONF 0x14
338 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
339 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
340 #define HV_CPU_QUEUE_RES_ERROR 0x3e
341 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
344 extern unsigned long sun4v_cpu_qconf(unsigned long type,
345 unsigned long queue_paddr,
346 unsigned long num_queue_entries);
351 * FUNCTION: HV_FAST_CPU_QINFO
354 * RET1: base real address
355 * RET1: number of entries
356 * ERRORS: EINVAL Invalid queue
358 * Return the configuration info for the given queue. The base real
359 * address and number of entries of the defined queue are returned.
360 * The queue argument values are the same as for cpu_qconf() above.
362 * If the specified queue is a valid queue number, but no queue has
363 * been defined, the number of entries will be set to zero and the
364 * base real address returned is undefined.
366 #define HV_FAST_CPU_QINFO 0x15
370 * FUNCTION: HV_FAST_CPU_MONDO_SEND
372 * ARG2: data real address
374 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
375 * is not 2-byte aligned.
376 * ENORADDR Invalid data mondo address, or invalid cpu list
378 * ENOCPU Invalid cpu in CPU list
379 * EWOULDBLOCK Some or all of the listed CPUs did not receive
381 * ECPUERROR One or more of the listed CPUs are in error
382 * state, use HV_FAST_CPU_STATE to see which ones
383 * EINVAL CPU list includes caller's CPU ID
385 * Send a mondo interrupt to the CPUs in the given CPU list with the
386 * 64-bytes at the given data real address. The data must be 64-byte
387 * aligned. The mondo data will be delivered to the cpu_mondo queues
388 * of the recipient CPUs.
390 * In all cases, error or not, the CPUs in the CPU list to which the
391 * mondo has been successfully delivered will be indicated by having
392 * their entry in CPU list updated with the value 0xffff.
394 #define HV_FAST_CPU_MONDO_SEND 0x42
397 extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
402 * FUNCTION: HV_FAST_CPU_MYID
405 * ERRORS: No errors defined.
407 * Return the hypervisor ID handle for the current CPU. Use by a
408 * virtual CPU to discover it's own identity.
410 #define HV_FAST_CPU_MYID 0x16
414 * FUNCTION: HV_FAST_CPU_STATE
418 * ERRORS: ENOCPU Invalid CPU ID
420 * Retrieve the current state of the CPU with the given CPU ID.
422 #define HV_FAST_CPU_STATE 0x17
423 #define HV_CPU_STATE_STOPPED 0x01
424 #define HV_CPU_STATE_RUNNING 0x02
425 #define HV_CPU_STATE_ERROR 0x03
428 extern long sun4v_cpu_state(unsigned long cpuid);
433 * FUNCTION: HV_FAST_CPU_SET_RTBA
436 * RET1: previous RTBA
437 * ERRORS: ENORADDR Invalid RTBA real address
438 * EBADALIGN RTBA is incorrectly aligned for a trap table
440 * Set the real trap base address of the local cpu to the given RTBA.
441 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
442 * success the previous value of the RTBA is returned in RET1.
444 * Note: This service does not affect %tba
446 #define HV_FAST_CPU_SET_RTBA 0x18
450 * FUNCTION: HV_FAST_CPU_GET_RTBA
452 * RET1: previous RTBA
453 * ERRORS: No possible error.
455 * Returns the current value of RTBA in RET1.
457 #define HV_FAST_CPU_GET_RTBA 0x19
461 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
464 struct hv_tsb_descr {
465 unsigned short pgsz_idx;
466 unsigned short assoc;
467 unsigned int num_ttes; /* in TTEs */
468 unsigned int ctx_idx;
469 unsigned int pgsz_mask;
470 unsigned long tsb_base;
474 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
475 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
476 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
477 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
478 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
479 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
480 #define HV_TSB_DESCR_RESV_OFFSET 0x18
482 /* Page size bitmask. */
483 #define HV_PGSZ_MASK_8K (1 << 0)
484 #define HV_PGSZ_MASK_64K (1 << 1)
485 #define HV_PGSZ_MASK_512K (1 << 2)
486 #define HV_PGSZ_MASK_4MB (1 << 3)
487 #define HV_PGSZ_MASK_32MB (1 << 4)
488 #define HV_PGSZ_MASK_256MB (1 << 5)
489 #define HV_PGSZ_MASK_2GB (1 << 6)
490 #define HV_PGSZ_MASK_16GB (1 << 7)
492 /* Page size index. The value given in the TSB descriptor must correspond
493 * to the smallest page size specified in the pgsz_mask page size bitmask.
495 #define HV_PGSZ_IDX_8K 0
496 #define HV_PGSZ_IDX_64K 1
497 #define HV_PGSZ_IDX_512K 2
498 #define HV_PGSZ_IDX_4MB 3
499 #define HV_PGSZ_IDX_32MB 4
500 #define HV_PGSZ_IDX_256MB 5
501 #define HV_PGSZ_IDX_2GB 6
502 #define HV_PGSZ_IDX_16GB 7
504 /* MMU fault status area.
506 * MMU related faults have their status and fault address information
507 * placed into a memory region made available by privileged code. Each
508 * virtual processor must make a mmu_fault_area_conf() call to tell the
509 * hypervisor where that processor's fault status should be stored.
511 * The fault status block is a multiple of 64-bytes and must be aligned
512 * on a 64-byte boundary.
515 struct hv_fault_status {
516 unsigned long i_fault_type;
517 unsigned long i_fault_addr;
518 unsigned long i_fault_ctx;
519 unsigned long i_reserved[5];
520 unsigned long d_fault_type;
521 unsigned long d_fault_addr;
522 unsigned long d_fault_ctx;
523 unsigned long d_reserved[5];
526 #define HV_FAULT_I_TYPE_OFFSET 0x00
527 #define HV_FAULT_I_ADDR_OFFSET 0x08
528 #define HV_FAULT_I_CTX_OFFSET 0x10
529 #define HV_FAULT_D_TYPE_OFFSET 0x40
530 #define HV_FAULT_D_ADDR_OFFSET 0x48
531 #define HV_FAULT_D_CTX_OFFSET 0x50
533 #define HV_FAULT_TYPE_FAST_MISS 1
534 #define HV_FAULT_TYPE_FAST_PROT 2
535 #define HV_FAULT_TYPE_MMU_MISS 3
536 #define HV_FAULT_TYPE_INV_RA 4
537 #define HV_FAULT_TYPE_PRIV_VIOL 5
538 #define HV_FAULT_TYPE_PROT_VIOL 6
539 #define HV_FAULT_TYPE_NFO 7
540 #define HV_FAULT_TYPE_NFO_SEFF 8
541 #define HV_FAULT_TYPE_INV_VA 9
542 #define HV_FAULT_TYPE_INV_ASI 10
543 #define HV_FAULT_TYPE_NC_ATOMIC 11
544 #define HV_FAULT_TYPE_PRIV_ACT 12
545 #define HV_FAULT_TYPE_RESV1 13
546 #define HV_FAULT_TYPE_UNALIGNED 14
547 #define HV_FAULT_TYPE_INV_PGSZ 15
548 /* Values 16 --> -2 are reserved. */
549 #define HV_FAULT_TYPE_MULTIPLE -1
551 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
552 * and mmu_{map,unmap}_perm_addr().
554 #define HV_MMU_DMMU 0x01
555 #define HV_MMU_IMMU 0x02
556 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
559 * TRAP: HV_MMU_MAP_ADDR_TRAP
560 * ARG0: virtual address
563 * ARG3: flags (HV_MMU_{IMMU,DMMU})
564 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
565 * EBADPGSZ Invalid page size value
566 * ENORADDR Invalid real address in TTE
568 * Create a non-permanent mapping using the given TTE, virtual
569 * address, and mmu context. The flags argument determines which
570 * (data, or instruction, or both) TLB the mapping gets loaded into.
572 * The behavior is undefined if the valid bit is clear in the TTE.
574 * Note: This API call is for privileged code to specify temporary translation
575 * mappings without the need to create and manage a TSB.
579 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
580 * ARG0: virtual address
582 * ARG2: flags (HV_MMU_{IMMU,DMMU})
583 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
585 * Demaps the given virtual address in the given mmu context on this
586 * CPU. This function is intended to be used to demap pages mapped
587 * with mmu_map_addr. This service is equivalent to invoking
588 * mmu_demap_page() with only the current CPU in the CPU list. The
589 * flags argument determines which (data, or instruction, or both) TLB
590 * the mapping gets unmapped from.
592 * Attempting to perform an unmap operation for a previously defined
593 * permanent mapping will have undefined results.
598 * FUNCTION: HV_FAST_MMU_TSB_CTX0
599 * ARG0: number of TSB descriptions
600 * ARG1: TSB descriptions pointer
602 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
603 * TSB base within a descriptor
604 * EBADALIGN TSB descriptions pointer is not aligned
605 * to an 8-byte boundary, or TSB base
606 * within a descriptor is not aligned for
608 * EBADPGSZ Invalid page size in a TSB descriptor
609 * EBADTSB Invalid associativity or size in a TSB
611 * EINVAL Invalid number of TSB descriptions, or
612 * invalid context index in a TSB
613 * descriptor, or index page size not
614 * equal to smallest page size in page
615 * size bitmask field.
617 * Configures the TSBs for the current CPU for virtual addresses with
618 * context zero. The TSB descriptions pointer is a pointer to an
619 * array of the given number of TSB descriptions.
621 * Note: The maximum number of TSBs available to a virtual CPU is given by the
622 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
623 * machine description.
625 #define HV_FAST_MMU_TSB_CTX0 0x20
628 extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
629 unsigned long tsb_desc_ra);
634 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
635 * ARG0: number of TSB descriptions
636 * ARG1: TSB descriptions pointer
638 * ERRORS: Same as for mmu_tsb_ctx0() above.
640 * Configures the TSBs for the current CPU for virtual addresses with
641 * non-zero contexts. The TSB descriptions pointer is a pointer to an
642 * array of the given number of TSB descriptions.
644 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
646 #define HV_FAST_MMU_TSB_CTXNON0 0x21
650 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
651 * ARG0: reserved, must be zero
652 * ARG1: reserved, must be zero
653 * ARG2: virtual address
655 * ARG4: flags (HV_MMU_{IMMU,DMMU})
657 * ERRORS: EINVAL Invalid virutal address, context, or
659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
661 * Demaps any page mapping of the given virtual address in the given
662 * mmu context for the current virtual CPU. Any virtually tagged
663 * caches are guaranteed to be kept consistent. The flags argument
664 * determines which TLB (instruction, or data, or both) participate in
667 * ARG0 and ARG1 are both reserved and must be set to zero.
669 #define HV_FAST_MMU_DEMAP_PAGE 0x22
673 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
674 * ARG0: reserved, must be zero
675 * ARG1: reserved, must be zero
677 * ARG3: flags (HV_MMU_{IMMU,DMMU})
679 * ERRORS: EINVAL Invalid context or flags value
680 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
682 * Demaps all non-permanent virtual page mappings previously specified
683 * for the given context for the current virtual CPU. Any virtual
684 * tagged caches are guaranteed to be kept consistent. The flags
685 * argument determines which TLB (instruction, or data, or both)
686 * participate in the operation.
688 * ARG0 and ARG1 are both reserved and must be set to zero.
690 #define HV_FAST_MMU_DEMAP_CTX 0x23
694 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
695 * ARG0: reserved, must be zero
696 * ARG1: reserved, must be zero
697 * ARG2: flags (HV_MMU_{IMMU,DMMU})
699 * ERRORS: EINVAL Invalid flags value
700 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
702 * Demaps all non-permanent virtual page mappings previously specified
703 * for the current virtual CPU. Any virtual tagged caches are
704 * guaranteed to be kept consistent. The flags argument determines
705 * which TLB (instruction, or data, or both) participate in the
708 * ARG0 and ARG1 are both reserved and must be set to zero.
710 #define HV_FAST_MMU_DEMAP_ALL 0x24
712 /* mmu_map_perm_addr()
714 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
715 * ARG0: virtual address
716 * ARG1: reserved, must be zero
718 * ARG3: flags (HV_MMU_{IMMU,DMMU})
720 * ERRORS: EINVAL Invalid virutal address or flags value
721 * EBADPGSZ Invalid page size value
722 * ENORADDR Invalid real address in TTE
723 * ETOOMANY Too many mappings (max of 8 reached)
725 * Create a permanent mapping using the given TTE and virtual address
726 * for context 0 on the calling virtual CPU. A maximum of 8 such
727 * permanent mappings may be specified by privileged code. Mappings
728 * may be removed with mmu_unmap_perm_addr().
730 * The behavior is undefined if a TTE with the valid bit clear is given.
732 * Note: This call is used to specify address space mappings for which
733 * privileged code does not expect to receive misses. For example,
734 * this mechanism can be used to map kernel nucleus code and data.
736 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
739 extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
740 unsigned long set_to_zero,
742 unsigned long flags);
745 /* mmu_fault_area_conf()
747 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
750 * RET1: previous mmu fault area real address
751 * ERRORS: ENORADDR Invalid real address
752 * EBADALIGN Invalid alignment for fault area
754 * Configure the MMU fault status area for the calling CPU. A 64-byte
755 * aligned real address specifies where MMU fault status information
756 * is placed. The return value is the previously specified area, or 0
757 * for the first invocation. Specifying a fault area at real address
760 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
764 * FUNCTION: HV_FAST_MMU_ENABLE
766 * ARG1: return target address
768 * ERRORS: ENORADDR Invalid real address when disabling
770 * EBADALIGN The return target address is not
771 * aligned to an instruction.
772 * EINVAL The enable flag request the current
773 * operating mode (e.g. disable if already
776 * Enable or disable virtual address translation for the calling CPU
777 * within the virtual machine domain. If the enable flag is zero,
778 * translation is disabled, any non-zero value will enable
781 * When this function returns, the newly selected translation mode
782 * will be active. If the mmu is being enabled, then the return
783 * target address is a virtual address else it is a real address.
785 * Upon successful completion, control will be returned to the given
786 * return target address (ie. the cpu will jump to that address). On
787 * failure, the previous mmu mode remains and the trap simply returns
788 * as normal with the appropriate error code in RET0.
790 #define HV_FAST_MMU_ENABLE 0x27
792 /* mmu_unmap_perm_addr()
794 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
795 * ARG0: virtual address
796 * ARG1: reserved, must be zero
797 * ARG2: flags (HV_MMU_{IMMU,DMMU})
799 * ERRORS: EINVAL Invalid virutal address or flags value
800 * ENOMAP Specified mapping was not found
802 * Demaps any permanent page mapping (established via
803 * mmu_map_perm_addr()) at the given virtual address for context 0 on
804 * the current virtual CPU. Any virtual tagged caches are guaranteed
805 * to be kept consistent.
807 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
809 /* mmu_tsb_ctx0_info()
811 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
813 * ARG1: buffer pointer
815 * RET1: number of TSBs
816 * ERRORS: EINVAL Supplied buffer is too small
817 * EBADALIGN The buffer pointer is badly aligned
818 * ENORADDR Invalid real address for buffer pointer
820 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
821 * into the provided buffer. The size of the buffer is given in ARG1
822 * in terms of the number of TSB description entries.
824 * Upon return, RET1 always contains the number of TSB descriptions
825 * previously configured. If zero TSBs were configured, EOK is
826 * returned with RET1 containing 0.
828 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
830 /* mmu_tsb_ctxnon0_info()
832 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
834 * ARG1: buffer pointer
836 * RET1: number of TSBs
837 * ERRORS: EINVAL Supplied buffer is too small
838 * EBADALIGN The buffer pointer is badly aligned
839 * ENORADDR Invalid real address for buffer pointer
841 * Return the TSB configuration as previous defined by
842 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
843 * is given in ARG1 in terms of the number of TSB description entries.
845 * Upon return, RET1 always contains the number of TSB descriptions
846 * previously configured. If zero TSBs were configured, EOK is
847 * returned with RET1 containing 0.
849 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
851 /* mmu_fault_area_info()
853 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
855 * RET1: fault area real address
856 * ERRORS: No errors defined.
858 * Return the currently defined MMU fault status area for the current
859 * CPU. The real address of the fault status area is returned in
860 * RET1, or 0 is returned in RET1 if no fault status area is defined.
862 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
863 * from this service if there is a need to save and restore the fault
866 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
868 /* Cache and Memory services. */
872 * FUNCTION: HV_FAST_MEM_SCRUB
876 * RET1: length scrubbed
877 * ERRORS: ENORADDR Invalid real address
878 * EBADALIGN Start address or length are not correctly
880 * EINVAL Length is zero
882 * Zero the memory contents in the range real address to real address
883 * plus length minus 1. Also, valid ECC will be generated for that
884 * memory address range. Scrubbing is started at the given real
885 * address, but may not scrub the entire given length. The actual
886 * length scrubbed will be returned in RET1.
888 * The real address and length must be aligned on an 8K boundary, or
889 * contain the start address and length from a sun4v error report.
891 * Note: There are two uses for this function. The first use is to block clear
892 * and initialize memory and the second is to scrub an u ncorrectable
893 * error reported via a resumable or non-resumable trap. The second
894 * use requires the arguments to be equal to the real address and length
895 * provided in a sun4v memory error report.
897 #define HV_FAST_MEM_SCRUB 0x31
901 * FUNCTION: HV_FAST_MEM_SYNC
905 * RET1: length synced
906 * ERRORS: ENORADDR Invalid real address
907 * EBADALIGN Start address or length are not correctly
909 * EINVAL Length is zero
911 * Force the next access within the real address to real address plus
912 * length minus 1 to be fetches from main system memory. Less than
913 * the given length may be synced, the actual amount synced is
914 * returned in RET1. The real address and length must be aligned on
917 #define HV_FAST_MEM_SYNC 0x32
919 /* Time of day services.
921 * The hypervisor maintains the time of day on a per-domain basis.
922 * Changing the time of day in one domain does not affect the time of
923 * day on any other domain.
925 * Time is described by a single unsigned 64-bit word which is the
926 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
932 * FUNCTION: HV_FAST_TOD_GET
935 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
936 * ENOTSUPPORTED If TOD not supported on this platform
938 * Return the current time of day. May block if TOD access is
939 * temporarily not possible.
941 #define HV_FAST_TOD_GET 0x50
944 extern unsigned long sun4v_tod_get(unsigned long *time);
949 * FUNCTION: HV_FAST_TOD_SET
952 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
953 * ENOTSUPPORTED If TOD not supported on this platform
955 * The current time of day is set to the value specified in ARG0. May
956 * block if TOD access is temporarily not possible.
958 #define HV_FAST_TOD_SET 0x51
961 extern unsigned long sun4v_tod_set(unsigned long time);
964 /* Console services */
968 * FUNCTION: HV_FAST_CONS_GETCHAR
971 * ERRORS: EWOULDBLOCK No character available.
973 * Returns a character from the console device. If no character is
974 * available then an EWOULDBLOCK error is returned. If a character is
975 * available, then the returned status is EOK and the character value
978 * A virtual BREAK is represented by the 64-bit value -1.
980 * A virtual HUP signal is represented by the 64-bit value -2.
982 #define HV_FAST_CONS_GETCHAR 0x60
986 * FUNCTION: HV_FAST_CONS_PUTCHAR
989 * ERRORS: EINVAL Illegal character
990 * EWOULDBLOCK Output buffer currently full, would block
992 * Send a character to the console device. Only character values
993 * between 0 and 255 may be used. Values outside this range are
994 * invalid except for the 64-bit value -1 which is used to send a
997 #define HV_FAST_CONS_PUTCHAR 0x61
1000 * TRAP: HV_FAST_TRAP
1001 * FUNCTION: HV_FAST_CONS_READ
1002 * ARG0: buffer real address
1003 * ARG1: buffer size in bytes
1005 * RET1: bytes read or BREAK or HUP
1006 * ERRORS: EWOULDBLOCK No character available.
1008 * Reads characters into a buffer from the console device. If no
1009 * character is available then an EWOULDBLOCK error is returned.
1010 * If a character is available, then the returned status is EOK
1011 * and the number of bytes read into the given buffer is provided
1014 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1016 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1018 * If BREAK or HUP are indicated, no bytes were read into buffer.
1020 #define HV_FAST_CONS_READ 0x62
1023 * TRAP: HV_FAST_TRAP
1024 * FUNCTION: HV_FAST_CONS_WRITE
1025 * ARG0: buffer real address
1026 * ARG1: buffer size in bytes
1028 * RET1: bytes written
1029 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
1031 * Send a characters in buffer to the console device. Breaks must be
1032 * sent using con_putchar().
1034 #define HV_FAST_CONS_WRITE 0x63
1036 #ifndef __ASSEMBLY__
1037 extern long sun4v_con_getchar(long *status);
1038 extern long sun4v_con_putchar(long c);
1039 extern long sun4v_con_read(unsigned long buffer,
1041 unsigned long *bytes_read);
1042 extern unsigned long sun4v_con_write(unsigned long buffer,
1044 unsigned long *bytes_written);
1047 /* mach_set_soft_state()
1048 * TRAP: HV_FAST_TRAP
1049 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1050 * ARG0: software state
1051 * ARG1: software state description pointer
1053 * ERRORS: EINVAL software state not valid or software state
1054 * description is not NULL terminated
1055 * ENORADDR software state description pointer is not a
1056 * valid real address
1057 * EBADALIGNED software state description is not correctly
1060 * This allows the guest to report it's soft state to the hypervisor. There
1061 * are two primary components to this state. The first part states whether
1062 * the guest software is running or not. The second containts optional
1063 * details specific to the software.
1065 * The software state argument is defined below in HV_SOFT_STATE_*, and
1066 * indicates whether the guest is operating normally or in a transitional
1069 * The software state description argument is a real address of a data buffer
1070 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1071 * terminated 7-bit ASCII string of up to 31 characters not including the
1074 #define HV_FAST_MACH_SET_SOFT_STATE 0x70
1075 #define HV_SOFT_STATE_NORMAL 0x01
1076 #define HV_SOFT_STATE_TRANSITION 0x02
1078 #ifndef __ASSEMBLY__
1079 extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1080 unsigned long msg_string_ra);
1083 /* mach_get_soft_state()
1084 * TRAP: HV_FAST_TRAP
1085 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1086 * ARG0: software state description pointer
1088 * RET1: software state
1089 * ERRORS: ENORADDR software state description pointer is not a
1090 * valid real address
1091 * EBADALIGNED software state description is not correctly
1094 * Retrieve the current value of the guest's software state. The rules
1095 * for the software state pointer are the same as for mach_set_soft_state()
1098 #define HV_FAST_MACH_GET_SOFT_STATE 0x71
1101 * TRAP: HV_FAST_TRAP
1102 * FUNCTION: HV_FAST_SVC_SEND
1104 * ARG1: buffer real address
1109 * Be careful, all output registers are clobbered by this operation,
1110 * so for example it is not possible to save away a value in %o4
1113 #define HV_FAST_SVC_SEND 0x80
1116 * TRAP: HV_FAST_TRAP
1117 * FUNCTION: HV_FAST_SVC_RECV
1119 * ARG1: buffer real address
1124 * Be careful, all output registers are clobbered by this operation,
1125 * so for example it is not possible to save away a value in %o4
1128 #define HV_FAST_SVC_RECV 0x81
1131 * TRAP: HV_FAST_TRAP
1132 * FUNCTION: HV_FAST_SVC_GETSTATUS
1137 #define HV_FAST_SVC_GETSTATUS 0x82
1140 * TRAP: HV_FAST_TRAP
1141 * FUNCTION: HV_FAST_SVC_SETSTATUS
1146 #define HV_FAST_SVC_SETSTATUS 0x83
1149 * TRAP: HV_FAST_TRAP
1150 * FUNCTION: HV_FAST_SVC_CLRSTATUS
1152 * ARG1: bits to clear
1155 #define HV_FAST_SVC_CLRSTATUS 0x84
1157 #ifndef __ASSEMBLY__
1158 extern unsigned long sun4v_svc_send(unsigned long svc_id,
1159 unsigned long buffer,
1160 unsigned long buffer_size,
1161 unsigned long *sent_bytes);
1162 extern unsigned long sun4v_svc_recv(unsigned long svc_id,
1163 unsigned long buffer,
1164 unsigned long buffer_size,
1165 unsigned long *recv_bytes);
1166 extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1167 unsigned long *status_bits);
1168 extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1169 unsigned long status_bits);
1170 extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1171 unsigned long status_bits);
1174 /* Trap trace services.
1176 * The hypervisor provides a trap tracing capability for privileged
1177 * code running on each virtual CPU. Privileged code provides a
1178 * round-robin trap trace queue within which the hypervisor writes
1179 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1180 * privileged code. This is provided as a debugging capability for
1183 * The trap trace control structure is 64-bytes long and placed at the
1184 * start (offset 0) of the trap trace buffer, and is described as
1187 #ifndef __ASSEMBLY__
1188 struct hv_trap_trace_control {
1189 unsigned long head_offset;
1190 unsigned long tail_offset;
1191 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1194 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1195 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1197 /* The head offset is the offset of the most recently completed entry
1198 * in the trap-trace buffer. The tail offset is the offset of the
1199 * next entry to be written. The control structure is owned and
1200 * modified by the hypervisor. A guest may not modify the control
1201 * structure contents. Attempts to do so will result in undefined
1202 * behavior for the guest.
1204 * Each trap trace buffer entry is layed out as follows:
1206 #ifndef __ASSEMBLY__
1207 struct hv_trap_trace_entry {
1208 unsigned char type; /* Hypervisor or guest entry? */
1209 unsigned char hpstate; /* Hyper-privileged state */
1210 unsigned char tl; /* Trap level */
1211 unsigned char gl; /* Global register level */
1212 unsigned short tt; /* Trap type */
1213 unsigned short tag; /* Extended trap identifier */
1214 unsigned long tstate; /* Trap state */
1215 unsigned long tick; /* Tick */
1216 unsigned long tpc; /* Trap PC */
1217 unsigned long f1; /* Entry specific */
1218 unsigned long f2; /* Entry specific */
1219 unsigned long f3; /* Entry specific */
1220 unsigned long f4; /* Entry specific */
1223 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1224 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1225 #define HV_TRAP_TRACE_ENTRY_TL 0x02
1226 #define HV_TRAP_TRACE_ENTRY_GL 0x03
1227 #define HV_TRAP_TRACE_ENTRY_TT 0x04
1228 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
1229 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1230 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
1231 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
1232 #define HV_TRAP_TRACE_ENTRY_F1 0x20
1233 #define HV_TRAP_TRACE_ENTRY_F2 0x28
1234 #define HV_TRAP_TRACE_ENTRY_F3 0x30
1235 #define HV_TRAP_TRACE_ENTRY_F4 0x38
1237 /* The type field is encoded as follows. */
1238 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1239 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1240 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1242 /* ttrace_buf_conf()
1243 * TRAP: HV_FAST_TRAP
1244 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1245 * ARG0: real address
1246 * ARG1: number of entries
1248 * RET1: number of entries
1249 * ERRORS: ENORADDR Invalid real address
1250 * EINVAL Size is too small
1251 * EBADALIGN Real address not aligned on 64-byte boundary
1253 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1254 * trace buffer to the hypervisor. The real address supplies the real
1255 * base address of the trap trace queue and must be 64-byte aligned.
1256 * Specifying a value of 0 for the number of entries disables trap
1257 * tracing for the calling virtual CPU. The buffer allocated must be
1258 * sized for a power of two number of 64-byte trap trace entries plus
1259 * an initial 64-byte control structure.
1261 * This may be invoked any number of times so that a virtual CPU may
1262 * relocate a trap trace buffer or create "snapshots" of information.
1264 * If the real address is illegal or badly aligned, then trap tracing
1265 * is disabled and an error is returned.
1267 * Upon failure with EINVAL, this service call returns in RET1 the
1268 * minimum number of buffer entries required. Upon other failures
1269 * RET1 is undefined.
1271 #define HV_FAST_TTRACE_BUF_CONF 0x90
1273 /* ttrace_buf_info()
1274 * TRAP: HV_FAST_TRAP
1275 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1277 * RET1: real address
1279 * ERRORS: None defined.
1281 * Returns the size and location of the previously declared trap-trace
1282 * buffer. In the event that no buffer was previously defined, or the
1283 * buffer is disabled, this call will return a size of zero bytes.
1285 #define HV_FAST_TTRACE_BUF_INFO 0x91
1288 * TRAP: HV_FAST_TRAP
1289 * FUNCTION: HV_FAST_TTRACE_ENABLE
1292 * RET1: previous enable state
1293 * ERRORS: EINVAL No trap trace buffer currently defined
1295 * Enable or disable trap tracing, and return the previous enabled
1296 * state in RET1. Future systems may define various flags for the
1297 * enable argument (ARG0), for the moment a guest should pass
1298 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1299 * tracing - which will ensure future compatability.
1301 #define HV_FAST_TTRACE_ENABLE 0x92
1304 * TRAP: HV_FAST_TRAP
1305 * FUNCTION: HV_FAST_TTRACE_FREEZE
1308 * RET1: previous freeze state
1309 * ERRORS: EINVAL No trap trace buffer currently defined
1311 * Freeze or unfreeze trap tracing, returning the previous freeze
1312 * state in RET1. A guest should pass a non-zero value to freeze and
1313 * a zero value to unfreeze all tracing. The returned previous state
1314 * is 0 for not frozen and 1 for frozen.
1316 #define HV_FAST_TTRACE_FREEZE 0x93
1318 /* ttrace_addentry()
1319 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1320 * ARG0: tag (16-bits)
1326 * ERRORS: EINVAL No trap trace buffer currently defined
1328 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1329 * is modified - none of the other registers holding arguments are
1330 * volatile across this hypervisor service.
1333 /* Core dump services.
1335 * Since the hypervisor viraulizes and thus obscures a lot of the
1336 * physical machine layout and state, traditional OS crash dumps can
1337 * be difficult to diagnose especially when the problem is a
1338 * configuration error of some sort.
1340 * The dump services provide an opaque buffer into which the
1341 * hypervisor can place it's internal state in order to assist in
1342 * debugging such situations. The contents are opaque and extremely
1343 * platform and hypervisor implementation specific. The guest, during
1344 * a core dump, requests that the hypervisor update any information in
1345 * the dump buffer in preparation to being dumped as part of the
1346 * domain's memory image.
1349 /* dump_buf_update()
1350 * TRAP: HV_FAST_TRAP
1351 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1352 * ARG0: real address
1355 * RET1: required size of dump buffer
1356 * ERRORS: ENORADDR Invalid real address
1357 * EBADALIGN Real address is not aligned on a 64-byte
1359 * EINVAL Size is non-zero but less than minimum size
1361 * ENOTSUPPORTED Operation not supported on current logical
1364 * Declare a domain dump buffer to the hypervisor. The real address
1365 * provided for the domain dump buffer must be 64-byte aligned. The
1366 * size specifies the size of the dump buffer and may be larger than
1367 * the minimum size specified in the machine description. The
1368 * hypervisor will fill the dump buffer with opaque data.
1370 * Note: A guest may elect to include dump buffer contents as part of a crash
1371 * dump to assist with debugging. This function may be called any number
1372 * of times so that a guest may relocate a dump buffer, or create
1373 * "snapshots" of any dump-buffer information. Each call to
1374 * dump_buf_update() atomically declares the new dump buffer to the
1377 * A specified size of 0 unconfigures the dump buffer. If the real
1378 * address is illegal or badly aligned, then any currently active dump
1379 * buffer is disabled and an error is returned.
1381 * In the event that the call fails with EINVAL, RET1 contains the
1382 * minimum size requires by the hypervisor for a valid dump buffer.
1384 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1387 * TRAP: HV_FAST_TRAP
1388 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1390 * RET1: real address of current dump buffer
1391 * RET2: size of current dump buffer
1392 * ERRORS: No errors defined.
1394 * Return the currently configures dump buffer description. A
1395 * returned size of 0 bytes indicates an undefined dump buffer. In
1396 * this case the return address in RET1 is undefined.
1398 #define HV_FAST_DUMP_BUF_INFO 0x95
1400 /* Device interrupt services.
1402 * Device interrupts are allocated to system bus bridges by the hypervisor,
1403 * and described to OBP in the machine description. OBP then describes
1404 * these interrupts to the OS via properties in the device tree.
1408 * cpuid Unique opaque value which represents a target cpu.
1410 * devhandle Device handle. It uniquely identifies a device, and
1411 * consistes of the lower 28-bits of the hi-cell of the
1412 * first entry of the device's "reg" property in the
1415 * devino Device interrupt number. Specifies the relative
1416 * interrupt number within the device. The unique
1417 * combination of devhandle and devino are used to
1418 * identify a specific device interrupt.
1420 * Note: The devino value is the same as the values in the
1421 * "interrupts" property or "interrupt-map" property
1422 * in the OBP device tree for that device.
1424 * sysino System interrupt number. A 64-bit unsigned interger
1425 * representing a unique interrupt within a virtual
1428 * intr_state A flag representing the interrupt state for a given
1429 * sysino. The state values are defined below.
1431 * intr_enabled A flag representing the 'enabled' state for a given
1432 * sysino. The enable values are defined below.
1435 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1436 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1437 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1439 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1440 #define HV_INTR_ENABLED 1 /* sysino enabled */
1442 /* intr_devino_to_sysino()
1443 * TRAP: HV_FAST_TRAP
1444 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1449 * ERRORS: EINVAL Invalid devhandle/devino
1451 * Converts a device specific interrupt number of the given
1452 * devhandle/devino into a system specific ino (sysino).
1454 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1456 #ifndef __ASSEMBLY__
1457 extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1458 unsigned long devino);
1461 /* intr_getenabled()
1462 * TRAP: HV_FAST_TRAP
1463 * FUNCTION: HV_FAST_INTR_GETENABLED
1466 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1467 * ERRORS: EINVAL Invalid sysino
1469 * Returns interrupt enabled state in RET1 for the interrupt defined
1470 * by the given sysino.
1472 #define HV_FAST_INTR_GETENABLED 0xa1
1474 #ifndef __ASSEMBLY__
1475 extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1478 /* intr_setenabled()
1479 * TRAP: HV_FAST_TRAP
1480 * FUNCTION: HV_FAST_INTR_SETENABLED
1482 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1484 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1486 * Set the 'enabled' state of the interrupt sysino.
1488 #define HV_FAST_INTR_SETENABLED 0xa2
1490 #ifndef __ASSEMBLY__
1491 extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1495 * TRAP: HV_FAST_TRAP
1496 * FUNCTION: HV_FAST_INTR_GETSTATE
1499 * RET1: intr_state (HV_INTR_STATE_*)
1500 * ERRORS: EINVAL Invalid sysino
1502 * Returns current state of the interrupt defined by the given sysino.
1504 #define HV_FAST_INTR_GETSTATE 0xa3
1506 #ifndef __ASSEMBLY__
1507 extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1511 * TRAP: HV_FAST_TRAP
1512 * FUNCTION: HV_FAST_INTR_SETSTATE
1514 * ARG1: intr_state (HV_INTR_STATE_*)
1516 * ERRORS: EINVAL Invalid sysino or intr_state value
1518 * Sets the current state of the interrupt described by the given sysino
1521 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1522 * interrupt for sysino.
1524 #define HV_FAST_INTR_SETSTATE 0xa4
1526 #ifndef __ASSEMBLY__
1527 extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1531 * TRAP: HV_FAST_TRAP
1532 * FUNCTION: HV_FAST_INTR_GETTARGET
1536 * ERRORS: EINVAL Invalid sysino
1538 * Returns CPU that is the current target of the interrupt defined by
1539 * the given sysino. The CPU value returned is undefined if the target
1540 * has not been set via intr_settarget().
1542 #define HV_FAST_INTR_GETTARGET 0xa5
1544 #ifndef __ASSEMBLY__
1545 extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1549 * TRAP: HV_FAST_TRAP
1550 * FUNCTION: HV_FAST_INTR_SETTARGET
1554 * ERRORS: EINVAL Invalid sysino
1555 * ENOCPU Invalid cpuid
1557 * Set the target CPU for the interrupt defined by the given sysino.
1559 #define HV_FAST_INTR_SETTARGET 0xa6
1561 #ifndef __ASSEMBLY__
1562 extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1565 /* vintr_get_cookie()
1566 * TRAP: HV_FAST_TRAP
1567 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1568 * ARG0: device handle
1573 #define HV_FAST_VINTR_GET_COOKIE 0xa7
1575 /* vintr_set_cookie()
1576 * TRAP: HV_FAST_TRAP
1577 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1578 * ARG0: device handle
1583 #define HV_FAST_VINTR_SET_COOKIE 0xa8
1585 /* vintr_get_valid()
1586 * TRAP: HV_FAST_TRAP
1587 * FUNCTION: HV_FAST_VINTR_GET_VALID
1588 * ARG0: device handle
1593 #define HV_FAST_VINTR_GET_VALID 0xa9
1595 /* vintr_set_valid()
1596 * TRAP: HV_FAST_TRAP
1597 * FUNCTION: HV_FAST_VINTR_SET_VALID
1598 * ARG0: device handle
1603 #define HV_FAST_VINTR_SET_VALID 0xaa
1605 /* vintr_get_state()
1606 * TRAP: HV_FAST_TRAP
1607 * FUNCTION: HV_FAST_VINTR_GET_STATE
1608 * ARG0: device handle
1613 #define HV_FAST_VINTR_GET_STATE 0xab
1615 /* vintr_set_state()
1616 * TRAP: HV_FAST_TRAP
1617 * FUNCTION: HV_FAST_VINTR_SET_STATE
1618 * ARG0: device handle
1623 #define HV_FAST_VINTR_SET_STATE 0xac
1625 /* vintr_get_target()
1626 * TRAP: HV_FAST_TRAP
1627 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1628 * ARG0: device handle
1633 #define HV_FAST_VINTR_GET_TARGET 0xad
1635 /* vintr_set_target()
1636 * TRAP: HV_FAST_TRAP
1637 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1638 * ARG0: device handle
1643 #define HV_FAST_VINTR_SET_TARGET 0xae
1645 #ifndef __ASSEMBLY__
1646 extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1647 unsigned long dev_ino,
1648 unsigned long *cookie);
1649 extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1650 unsigned long dev_ino,
1651 unsigned long cookie);
1652 extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1653 unsigned long dev_ino,
1654 unsigned long *valid);
1655 extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1656 unsigned long dev_ino,
1657 unsigned long valid);
1658 extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1659 unsigned long dev_ino,
1660 unsigned long *state);
1661 extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1662 unsigned long dev_ino,
1663 unsigned long state);
1664 extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1665 unsigned long dev_ino,
1666 unsigned long *cpuid);
1667 extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1668 unsigned long dev_ino,
1669 unsigned long cpuid);
1674 * See the terminology descriptions in the device interrupt services
1675 * section above as those apply here too. Here are terminology
1676 * definitions specific to these PCI IO services:
1678 * tsbnum TSB number. Indentifies which io-tsb is used.
1679 * For this version of the specification, tsbnum
1682 * tsbindex TSB index. Identifies which entry in the TSB
1683 * is used. The first entry is zero.
1685 * tsbid A 64-bit aligned data structure which contains
1686 * a tsbnum and a tsbindex. Bits 63:32 contain the
1687 * tsbnum and bits 31:00 contain the tsbindex.
1689 * Use the HV_PCI_TSBID() macro to construct such
1692 * io_attributes IO attributes for IOMMU mappings. One of more
1693 * of the attritbute bits are stores in a 64-bit
1694 * value. The values are defined below.
1696 * r_addr 64-bit real address
1698 * pci_device PCI device address. A PCI device address identifies
1699 * a specific device on a specific PCI bus segment.
1700 * A PCI device address ia a 32-bit unsigned integer
1701 * with the following format:
1703 * 00000000.bbbbbbbb.dddddfff.00000000
1705 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1709 * PCI configureation space offset. For conventional
1710 * PCI a value between 0 and 255. For extended
1711 * configuration space, a value between 0 and 4095.
1713 * Note: For PCI configuration space accesses, the offset
1714 * must be aligned to the access size.
1716 * error_flag A return value which specifies if the action succeeded
1717 * or failed. 0 means no error, non-0 means some error
1718 * occurred while performing the service.
1721 * Direction definition for pci_dma_sync(), defined
1722 * below in HV_PCI_SYNC_*.
1724 * io_page_list A list of io_page_addresses, an io_page_address is
1727 * io_page_list_p A pointer to an io_page_list.
1729 * "size based byte swap" - Some functions do size based byte swapping
1730 * which allows sw to access pointers and
1731 * counters in native form when the processor
1732 * operates in a different endianness than the
1733 * IO bus. Size-based byte swapping converts a
1734 * multi-byte field between big-endian and
1735 * little-endian format.
1738 #define HV_PCI_MAP_ATTR_READ 0x01
1739 #define HV_PCI_MAP_ATTR_WRITE 0x02
1741 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1742 ((((b) & 0xff) << 16) | \
1743 (((d) & 0x1f) << 11) | \
1744 (((f) & 0x07) << 8))
1746 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1747 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1749 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1750 #define HV_PCI_SYNC_FOR_CPU 0x02
1753 * TRAP: HV_FAST_TRAP
1754 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1758 * ARG3: io_attributes
1759 * ARG4: io_page_list_p
1761 * RET1: #ttes mapped
1762 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1763 * EBADALIGN Improperly aligned real address
1764 * ENORADDR Invalid real address
1766 * Create IOMMU mappings in the sun4v device defined by the given
1767 * devhandle. The mappings are created in the TSB defined by the
1768 * tsbnum component of the given tsbid. The first mapping is created
1769 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1770 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1771 * the second at tsbnum, tsbindex + 1, etc.
1773 * All mappings are created with the attributes defined by the io_attributes
1774 * argument. The page mapping addresses are described in the io_page_list
1775 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1776 * The first entry in the io_page_list is the address for the first iotte, the
1777 * 2nd for the 2nd iotte, and so on.
1779 * Each io_page_address in the io_page_list must be appropriately aligned.
1780 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1781 * component of the given tsbid must be zero.
1783 * Returns the actual number of mappings creates, which may be less than
1784 * or equal to the argument #ttes. If the function returns a value which
1785 * is less than the #ttes, the caller may continus to call the function with
1786 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1789 * Note: This function does not imply an iotte cache flush. The guest must
1790 * demap an entry before re-mapping it.
1792 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1794 /* pci_iommu_demap()
1795 * TRAP: HV_FAST_TRAP
1796 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1801 * RET1: #ttes demapped
1802 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1804 * Demap and flush IOMMU mappings in the device defined by the given
1805 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1806 * component of the given tsbid, starting at the TSB index defined by the
1807 * tsbindex component of the given tsbid.
1809 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1810 * #ttes must be greater than zero.
1812 * Returns the actual number of ttes demapped, which may be less than or equal
1813 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1814 * may continue to call this function with updated tsbid and #ttes arguments
1815 * until all pages are demapped.
1817 * Note: Entries do not have to be mapped to be demapped. A demap of an
1818 * unmapped page will flush the entry from the tte cache.
1820 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1822 /* pci_iommu_getmap()
1823 * TRAP: HV_FAST_TRAP
1824 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1828 * RET1: io_attributes
1829 * RET2: real address
1830 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1831 * ENOMAP Mapping is not valid, no translation exists
1833 * Read and return the mapping in the device described by the given devhandle
1834 * and tsbid. If successful, the io_attributes shall be returned in RET1
1835 * and the page address of the mapping shall be returned in RET2.
1837 * For this version of the spec, the tsbnum component of the given tsbid
1840 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1842 /* pci_iommu_getbypass()
1843 * TRAP: HV_FAST_TRAP
1844 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1846 * ARG1: real address
1847 * ARG2: io_attributes
1850 * ERRORS: EINVAL Invalid devhandle/io_attributes
1851 * ENORADDR Invalid real address
1852 * ENOTSUPPORTED Function not supported in this implementation.
1854 * Create a "special" mapping in the device described by the given devhandle,
1855 * for the given real address and attributes. Return the IO address in RET1
1858 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1861 * TRAP: HV_FAST_TRAP
1862 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1865 * ARG2: pci_config_offset
1870 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1871 * EBADALIGN pci_config_offset not size aligned
1872 * ENOACCESS Access to this offset is not permitted
1874 * Read PCI configuration space for the adapter described by the given
1875 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1876 * pci_device, at pci_config_offset from the beginning of the device's
1877 * configuration space. If there was no error, RET1 is set to zero and
1878 * RET2 is set to the data read. Insignificant bits in RET2 are not
1879 * guarenteed to have any specific value and therefore must be ignored.
1881 * The data returned in RET2 is size based byte swapped.
1883 * If an error occurs during the read, set RET1 to a non-zero value. The
1884 * given pci_config_offset must be 'size' aligned.
1886 #define HV_FAST_PCI_CONFIG_GET 0xb4
1889 * TRAP: HV_FAST_TRAP
1890 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1893 * ARG2: pci_config_offset
1898 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1899 * EBADALIGN pci_config_offset not size aligned
1900 * ENOACCESS Access to this offset is not permitted
1902 * Write PCI configuration space for the adapter described by the given
1903 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1904 * at pci_config_offset from the beginning of the device's configuration
1905 * space. The data argument contains the data to be written to configuration
1906 * space. Prior to writing, the data is size based byte swapped.
1908 * If an error occurs during the write access, do not generate an error
1909 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1910 * The given pci_config_offset must be 'size' aligned.
1912 * This function is permitted to read from offset zero in the configuration
1913 * space described by the given pci_device if necessary to ensure that the
1914 * write access to config space completes.
1916 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1919 * TRAP: HV_FAST_TRAP
1920 * FUNCTION: HV_FAST_PCI_PEEK
1922 * ARG1: real address
1927 * ERRORS: EINVAL Invalid devhandle or size
1928 * EBADALIGN Improperly aligned real address
1929 * ENORADDR Bad real address
1930 * ENOACCESS Guest access prohibited
1932 * Attempt to read the IO address given by the given devhandle, real address,
1933 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1934 * access operation using the given size. If an error occurs when reading
1935 * from the given location, do not generate an error report, but return a
1936 * non-zero value in RET1. If the read was successful, return zero in RET1
1937 * and return the actual data read in RET2. The data returned is size based
1940 * Non-significant bits in RET2 are not guarenteed to have any specific value
1941 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1942 * value is not guarenteed to have any specific value and should be ignored.
1944 * The caller must have permission to read from the given devhandle, real
1945 * address, which must be an IO address. The argument real address must be a
1946 * size aligned address.
1948 * The hypervisor implementation of this function must block access to any
1949 * IO address that the guest does not have explicit permission to access.
1951 #define HV_FAST_PCI_PEEK 0xb6
1954 * TRAP: HV_FAST_TRAP
1955 * FUNCTION: HV_FAST_PCI_POKE
1957 * ARG1: real address
1963 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1964 * EBADALIGN Improperly aligned real address
1965 * ENORADDR Bad real address
1966 * ENOACCESS Guest access prohibited
1967 * ENOTSUPPORTED Function is not supported by implementation
1969 * Attempt to write data to the IO address given by the given devhandle,
1970 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1971 * performed as a single access operation using the given size. Prior to
1972 * writing the data is size based swapped.
1974 * If an error occurs when writing to the given location, do not generate an
1975 * error report, but return a non-zero value in RET1. If the write was
1976 * successful, return zero in RET1.
1978 * pci_device describes the configuration address of the device being
1979 * written to. The implementation may safely read from offset 0 with
1980 * the configuration space of the device described by devhandle and
1981 * pci_device in order to guarantee that the write portion of the operation
1984 * Any error that occurs due to the read shall be reported using the normal
1985 * error reporting mechanisms .. the read error is not suppressed.
1987 * The caller must have permission to write to the given devhandle, real
1988 * address, which must be an IO address. The argument real address must be a
1989 * size aligned address. The caller must have permission to read from
1990 * the given devhandle, pci_device cofiguration space offset 0.
1992 * The hypervisor implementation of this function must block access to any
1993 * IO address that the guest does not have explicit permission to access.
1995 #define HV_FAST_PCI_POKE 0xb7
1998 * TRAP: HV_FAST_TRAP
1999 * FUNCTION: HV_FAST_PCI_DMA_SYNC
2001 * ARG1: real address
2003 * ARG3: io_sync_direction
2006 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
2007 * ENORADDR Bad real address
2009 * Synchronize a memory region described by the given real address and size,
2010 * for the device defined by the given devhandle using the direction(s)
2011 * defined by the given io_sync_direction. The argument size is the size of
2012 * the memory region in bytes.
2014 * Return the actual number of bytes synchronized in the return value #synced,
2015 * which may be less than or equal to the argument size. If the return
2016 * value #synced is less than size, the caller must continue to call this
2017 * function with updated real address and size arguments until the entire
2018 * memory region is synchronized.
2020 #define HV_FAST_PCI_DMA_SYNC 0xb8
2022 /* PCI MSI services. */
2024 #define HV_MSITYPE_MSI32 0x00
2025 #define HV_MSITYPE_MSI64 0x01
2027 #define HV_MSIQSTATE_IDLE 0x00
2028 #define HV_MSIQSTATE_ERROR 0x01
2030 #define HV_MSIQ_INVALID 0x00
2031 #define HV_MSIQ_VALID 0x01
2033 #define HV_MSISTATE_IDLE 0x00
2034 #define HV_MSISTATE_DELIVERED 0x01
2036 #define HV_MSIVALID_INVALID 0x00
2037 #define HV_MSIVALID_VALID 0x01
2039 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
2040 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
2041 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
2042 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
2043 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
2045 #define HV_MSG_INVALID 0x00
2046 #define HV_MSG_VALID 0x01
2049 * TRAP: HV_FAST_TRAP
2050 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
2053 * ARG2: real address
2054 * ARG3: number of entries
2056 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
2057 * EBADALIGN Improperly aligned real address
2058 * ENORADDR Bad real address
2060 * Configure the MSI queue given by the devhandle and msiqid arguments,
2061 * and to be placed at the given real address and be of the given
2062 * number of entries. The real address must be aligned exactly to match
2063 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2064 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2065 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2067 * Implementation Note: Certain implementations have fixed sized queues. In
2068 * that case, number of entries must contain the correct
2071 #define HV_FAST_PCI_MSIQ_CONF 0xc0
2074 * TRAP: HV_FAST_TRAP
2075 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
2079 * RET1: real address
2080 * RET2: number of entries
2081 * ERRORS: EINVAL Invalid devhandle or msiqid
2083 * Return the configuration information for the MSI queue described
2084 * by the given devhandle and msiqid. The base address of the queue
2085 * is returned in ARG1 and the number of entries is returned in ARG2.
2086 * If the queue is unconfigured, the real address is undefined and the
2087 * number of entries will be returned as zero.
2089 #define HV_FAST_PCI_MSIQ_INFO 0xc1
2091 /* pci_msiq_getvalid()
2092 * TRAP: HV_FAST_TRAP
2093 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2097 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2098 * ERRORS: EINVAL Invalid devhandle or msiqid
2100 * Get the valid state of the MSI-EQ described by the given devhandle and
2103 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
2105 /* pci_msiq_setvalid()
2106 * TRAP: HV_FAST_TRAP
2107 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
2110 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2112 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
2113 * value or MSI EQ is uninitialized
2115 * Set the valid state of the MSI-EQ described by the given devhandle and
2116 * msiqid to the given msiqvalid.
2118 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
2120 /* pci_msiq_getstate()
2121 * TRAP: HV_FAST_TRAP
2122 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
2126 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2127 * ERRORS: EINVAL Invalid devhandle or msiqid
2129 * Get the state of the MSI-EQ described by the given devhandle and
2132 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
2134 /* pci_msiq_getvalid()
2135 * TRAP: HV_FAST_TRAP
2136 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2139 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2141 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
2142 * value or MSI EQ is uninitialized
2144 * Set the state of the MSI-EQ described by the given devhandle and
2145 * msiqid to the given msiqvalid.
2147 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
2149 /* pci_msiq_gethead()
2150 * TRAP: HV_FAST_TRAP
2151 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
2156 * ERRORS: EINVAL Invalid devhandle or msiqid
2158 * Get the current MSI EQ queue head for the MSI-EQ described by the
2159 * given devhandle and msiqid.
2161 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
2163 /* pci_msiq_sethead()
2164 * TRAP: HV_FAST_TRAP
2165 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
2170 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
2171 * or MSI EQ is uninitialized
2173 * Set the current MSI EQ queue head for the MSI-EQ described by the
2174 * given devhandle and msiqid.
2176 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
2178 /* pci_msiq_gettail()
2179 * TRAP: HV_FAST_TRAP
2180 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
2185 * ERRORS: EINVAL Invalid devhandle or msiqid
2187 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2188 * given devhandle and msiqid.
2190 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
2192 /* pci_msi_getvalid()
2193 * TRAP: HV_FAST_TRAP
2194 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
2198 * RET1: msivalidstate
2199 * ERRORS: EINVAL Invalid devhandle or msinum
2201 * Get the current valid/enabled state for the MSI defined by the
2202 * given devhandle and msinum.
2204 #define HV_FAST_PCI_MSI_GETVALID 0xc9
2206 /* pci_msi_setvalid()
2207 * TRAP: HV_FAST_TRAP
2208 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
2211 * ARG2: msivalidstate
2213 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
2215 * Set the current valid/enabled state for the MSI defined by the
2216 * given devhandle and msinum.
2218 #define HV_FAST_PCI_MSI_SETVALID 0xca
2220 /* pci_msi_getmsiq()
2221 * TRAP: HV_FAST_TRAP
2222 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
2227 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
2229 * Get the MSI EQ that the MSI defined by the given devhandle and
2230 * msinum is bound to.
2232 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
2234 /* pci_msi_setmsiq()
2235 * TRAP: HV_FAST_TRAP
2236 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
2242 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
2244 * Set the MSI EQ that the MSI defined by the given devhandle and
2245 * msinum is bound to.
2247 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
2249 /* pci_msi_getstate()
2250 * TRAP: HV_FAST_TRAP
2251 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
2256 * ERRORS: EINVAL Invalid devhandle or msinum
2258 * Get the state of the MSI defined by the given devhandle and msinum.
2259 * If not initialized, return HV_MSISTATE_IDLE.
2261 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
2263 /* pci_msi_setstate()
2264 * TRAP: HV_FAST_TRAP
2265 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
2270 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
2272 * Set the state of the MSI defined by the given devhandle and msinum.
2274 #define HV_FAST_PCI_MSI_SETSTATE 0xce
2276 /* pci_msg_getmsiq()
2277 * TRAP: HV_FAST_TRAP
2278 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2283 * ERRORS: EINVAL Invalid devhandle or msgtype
2285 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2287 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2289 /* pci_msg_setmsiq()
2290 * TRAP: HV_FAST_TRAP
2291 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2296 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2298 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2300 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2302 /* pci_msg_getvalid()
2303 * TRAP: HV_FAST_TRAP
2304 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2308 * RET1: msgvalidstate
2309 * ERRORS: EINVAL Invalid devhandle or msgtype
2311 * Get the valid/enabled state of the MSG defined by the given
2312 * devhandle and msgtype.
2314 #define HV_FAST_PCI_MSG_GETVALID 0xd2
2316 /* pci_msg_setvalid()
2317 * TRAP: HV_FAST_TRAP
2318 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2321 * ARG2: msgvalidstate
2323 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2325 * Set the valid/enabled state of the MSG defined by the given
2326 * devhandle and msgtype.
2328 #define HV_FAST_PCI_MSG_SETVALID 0xd3
2330 /* Logical Domain Channel services. */
2332 #define LDC_CHANNEL_DOWN 0
2333 #define LDC_CHANNEL_UP 1
2334 #define LDC_CHANNEL_RESETTING 2
2337 * TRAP: HV_FAST_TRAP
2338 * FUNCTION: HV_FAST_LDC_TX_QCONF
2340 * ARG1: real address base of queue
2341 * ARG2: num entries in queue
2344 * Configure transmit queue for the LDC endpoint specified by the
2345 * given channel ID, to be placed at the given real address, and
2346 * be of the given num entries. Num entries must be a power of two.
2347 * The real address base of the queue must be aligned on the queue
2348 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2349 * queue must be aligned on a 2048 byte real address boundary.
2351 * Upon configuration of a valid transmit queue the head and tail
2352 * pointers are set to a hypervisor specific identical value indicating
2353 * that the queue initially is empty.
2355 * The endpoint's transmit queue is un-configured if num entries is zero.
2357 * The maximum number of entries for each queue for a specific cpu may be
2358 * determined from the machine description. A transmit queue may be
2359 * specified even in the event that the LDC is down (peer endpoint has no
2360 * receive queue specified). Transmission will begin as soon as the peer
2361 * endpoint defines a receive queue.
2363 * It is recommended that a guest wait for a transmit queue to empty prior
2364 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2365 * non-empty transmit queue behaves exactly as defined above, however it
2366 * is undefined as to how many of the pending entries in the original queue
2367 * will be delivered prior to the re-configuration taking effect.
2368 * Furthermore, as the queue configuration causes a reset of the head and
2369 * tail pointers there is no way for a guest to determine how many entries
2370 * have been sent after the configuration operation.
2372 #define HV_FAST_LDC_TX_QCONF 0xe0
2375 * TRAP: HV_FAST_TRAP
2376 * FUNCTION: HV_FAST_LDC_TX_QINFO
2379 * RET1: real address base of queue
2380 * RET2: num entries in queue
2382 * Return the configuration info for the transmit queue of LDC endpoint
2383 * defined by the given channel ID. The real address is the currently
2384 * defined real address base of the defined queue, and num entries is the
2385 * size of the queue in terms of number of entries.
2387 * If the specified channel ID is a valid endpoint number, but no transmit
2388 * queue has been defined this service will return success, but with num
2389 * entries set to zero and the real address will have an undefined value.
2391 #define HV_FAST_LDC_TX_QINFO 0xe1
2393 /* ldc_tx_get_state()
2394 * TRAP: HV_FAST_TRAP
2395 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2400 * RET3: channel state
2402 * Return the transmit state, and the head and tail queue pointers, for
2403 * the transmit queue of the LDC endpoint defined by the given channel ID.
2404 * The head and tail values are the byte offset of the head and tail
2405 * positions of the transmit queue for the specified endpoint.
2407 #define HV_FAST_LDC_TX_GET_STATE 0xe2
2409 /* ldc_tx_set_qtail()
2410 * TRAP: HV_FAST_TRAP
2411 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2416 * Update the tail pointer for the transmit queue associated with the LDC
2417 * endpoint defined by the given channel ID. The tail offset specified
2418 * must be aligned on a 64 byte boundary, and calculated so as to increase
2419 * the number of pending entries on the transmit queue. Any attempt to
2420 * decrease the number of pending transmit queue entires is considered
2421 * an invalid tail offset and will result in an EINVAL error.
2423 * Since the tail of the transmit queue may not be moved backwards, the
2424 * transmit queue may be flushed by configuring a new transmit queue,
2425 * whereupon the hypervisor will configure the initial transmit head and
2426 * tail pointers to be equal.
2428 #define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2431 * TRAP: HV_FAST_TRAP
2432 * FUNCTION: HV_FAST_LDC_RX_QCONF
2434 * ARG1: real address base of queue
2435 * ARG2: num entries in queue
2438 * Configure receive queue for the LDC endpoint specified by the
2439 * given channel ID, to be placed at the given real address, and
2440 * be of the given num entries. Num entries must be a power of two.
2441 * The real address base of the queue must be aligned on the queue
2442 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2443 * queue must be aligned on a 2048 byte real address boundary.
2445 * The endpoint's transmit queue is un-configured if num entries is zero.
2447 * If a valid receive queue is specified for a local endpoint the LDC is
2448 * in the up state for the purpose of transmission to this endpoint.
2450 * The maximum number of entries for each queue for a specific cpu may be
2451 * determined from the machine description.
2453 * As receive queue configuration causes a reset of the queue's head and
2454 * tail pointers there is no way for a gues to determine how many entries
2455 * have been received between a preceeding ldc_get_rx_state() API call
2456 * and the completion of the configuration operation. It should be noted
2457 * that datagram delivery is not guarenteed via domain channels anyway,
2458 * and therefore any higher protocol should be resilient to datagram
2459 * loss if necessary. However, to overcome this specific race potential
2460 * it is recommended, for example, that a higher level protocol be employed
2461 * to ensure either retransmission, or ensure that no datagrams are pending
2462 * on the peer endpoint's transmit queue prior to the configuration process.
2464 #define HV_FAST_LDC_RX_QCONF 0xe4
2467 * TRAP: HV_FAST_TRAP
2468 * FUNCTION: HV_FAST_LDC_RX_QINFO
2471 * RET1: real address base of queue
2472 * RET2: num entries in queue
2474 * Return the configuration info for the receive queue of LDC endpoint
2475 * defined by the given channel ID. The real address is the currently
2476 * defined real address base of the defined queue, and num entries is the
2477 * size of the queue in terms of number of entries.
2479 * If the specified channel ID is a valid endpoint number, but no receive
2480 * queue has been defined this service will return success, but with num
2481 * entries set to zero and the real address will have an undefined value.
2483 #define HV_FAST_LDC_RX_QINFO 0xe5
2485 /* ldc_rx_get_state()
2486 * TRAP: HV_FAST_TRAP
2487 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2492 * RET3: channel state
2494 * Return the receive state, and the head and tail queue pointers, for
2495 * the receive queue of the LDC endpoint defined by the given channel ID.
2496 * The head and tail values are the byte offset of the head and tail
2497 * positions of the receive queue for the specified endpoint.
2499 #define HV_FAST_LDC_RX_GET_STATE 0xe6
2501 /* ldc_rx_set_qhead()
2502 * TRAP: HV_FAST_TRAP
2503 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2508 * Update the head pointer for the receive queue associated with the LDC
2509 * endpoint defined by the given channel ID. The head offset specified
2510 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2511 * the number of pending entries on the receive queue. Any attempt to
2512 * increase the number of pending receive queue entires is considered
2513 * an invalid head offset and will result in an EINVAL error.
2515 * The receive queue may be flushed by setting the head offset equal
2516 * to the current tail offset.
2518 #define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2520 /* LDC Map Table Entry. Each slot is defined by a translation table
2521 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2522 * hypervisor invalidation cookie.
2524 #define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2525 #define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2526 #define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2527 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2528 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2529 #define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2530 #define LDC_MTE_WRITE 0x0000000000000020 /* read */
2531 #define LDC_MTE_READ 0x0000000000000010 /* write */
2532 #define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2533 #define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2534 #define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2535 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2536 #define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2537 #define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2538 #define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2539 #define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2540 #define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2542 #ifndef __ASSEMBLY__
2543 struct ldc_mtable_entry {
2545 unsigned long cookie;
2549 /* ldc_set_map_table()
2550 * TRAP: HV_FAST_TRAP
2551 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2553 * ARG1: table real address
2557 * Register the MTE table at the given table real address, with the
2558 * specified num entries, for the LDC indicated by the given channel
2561 #define HV_FAST_LDC_SET_MAP_TABLE 0xea
2563 /* ldc_get_map_table()
2564 * TRAP: HV_FAST_TRAP
2565 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2568 * RET1: table real address
2571 * Return the configuration of the current mapping table registered
2572 * for the given channel ID.
2574 #define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2576 #define LDC_COPY_IN 0
2577 #define LDC_COPY_OUT 1
2580 * TRAP: HV_FAST_TRAP
2581 * FUNCTION: HV_FAST_LDC_COPY
2583 * ARG1: LDC_COPY_* direction code
2584 * ARG2: target real address
2585 * ARG3: local real address
2586 * ARG4: length in bytes
2588 * RET1: actual length in bytes
2590 #define HV_FAST_LDC_COPY 0xec
2592 #define LDC_MEM_READ 1
2593 #define LDC_MEM_WRITE 2
2594 #define LDC_MEM_EXEC 4
2597 * TRAP: HV_FAST_TRAP
2598 * FUNCTION: HV_FAST_LDC_MAPIN
2602 * RET1: real address
2603 * RET2: LDC_MEM_* permissions
2605 #define HV_FAST_LDC_MAPIN 0xed
2608 * TRAP: HV_FAST_TRAP
2609 * FUNCTION: HV_FAST_LDC_UNMAP
2610 * ARG0: real address
2613 #define HV_FAST_LDC_UNMAP 0xee
2616 * TRAP: HV_FAST_TRAP
2617 * FUNCTION: HV_FAST_LDC_REVOKE
2619 * ARG1: ldc_mtable_entry cookie
2622 #define HV_FAST_LDC_REVOKE 0xef
2624 #ifndef __ASSEMBLY__
2625 extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2627 unsigned long num_entries);
2628 extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2630 unsigned long *num_entries);
2631 extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2632 unsigned long *head_off,
2633 unsigned long *tail_off,
2634 unsigned long *chan_state);
2635 extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2636 unsigned long tail_off);
2637 extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2639 unsigned long num_entries);
2640 extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2642 unsigned long *num_entries);
2643 extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2644 unsigned long *head_off,
2645 unsigned long *tail_off,
2646 unsigned long *chan_state);
2647 extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2648 unsigned long head_off);
2649 extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
2651 unsigned long num_entries);
2652 extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
2654 unsigned long *num_entries);
2655 extern unsigned long sun4v_ldc_copy(unsigned long channel,
2656 unsigned long dir_code,
2657 unsigned long tgt_raddr,
2658 unsigned long lcl_raddr,
2660 unsigned long *actual_len);
2661 extern unsigned long sun4v_ldc_mapin(unsigned long channel,
2662 unsigned long cookie,
2664 unsigned long *perm);
2665 extern unsigned long sun4v_ldc_unmap(unsigned long ra);
2666 extern unsigned long sun4v_ldc_revoke(unsigned long cookie,
2667 unsigned long mte_cookie);
2670 /* Performance counter services. */
2672 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
2673 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
2674 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
2675 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
2676 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
2677 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
2678 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
2679 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
2680 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
2681 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
2684 * TRAP: HV_FAST_TRAP
2685 * FUNCTION: HV_FAST_GET_PERFREG
2686 * ARG0: performance reg number
2688 * RET1: performance reg value
2689 * ERRORS: EINVAL Invalid performance register number
2690 * ENOACCESS No access allowed to performance counters
2692 * Read the value of the given DRAM/JBUS performance counter/control register.
2694 #define HV_FAST_GET_PERFREG 0x100
2697 * TRAP: HV_FAST_TRAP
2698 * FUNCTION: HV_FAST_SET_PERFREG
2699 * ARG0: performance reg number
2700 * ARG1: performance reg value
2702 * ERRORS: EINVAL Invalid performance register number
2703 * ENOACCESS No access allowed to performance counters
2705 * Write the given performance reg value to the given DRAM/JBUS
2706 * performance counter/control register.
2708 #define HV_FAST_SET_PERFREG 0x101
2710 /* MMU statistics services.
2712 * The hypervisor maintains MMU statistics and privileged code provides
2713 * a buffer where these statistics can be collected. It is continually
2714 * updated once configured. The layout is as follows:
2716 #ifndef __ASSEMBLY__
2717 struct hv_mmu_statistics {
2718 unsigned long immu_tsb_hits_ctx0_8k_tte;
2719 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2720 unsigned long immu_tsb_hits_ctx0_64k_tte;
2721 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2722 unsigned long __reserved1[2];
2723 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2724 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2725 unsigned long __reserved2[2];
2726 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2727 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2728 unsigned long __reserved3[4];
2729 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2730 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2731 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2732 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2733 unsigned long __reserved4[2];
2734 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2735 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2736 unsigned long __reserved5[2];
2737 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2738 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2739 unsigned long __reserved6[4];
2740 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2741 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2742 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2743 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2744 unsigned long __reserved7[2];
2745 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2746 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2747 unsigned long __reserved8[2];
2748 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2749 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2750 unsigned long __reserved9[4];
2751 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2752 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2753 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2754 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2755 unsigned long __reserved10[2];
2756 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2757 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2758 unsigned long __reserved11[2];
2759 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2760 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2761 unsigned long __reserved12[4];
2766 * TRAP: HV_FAST_TRAP
2767 * FUNCTION: HV_FAST_MMUSTAT_CONF
2768 * ARG0: real address
2770 * RET1: real address
2771 * ERRORS: ENORADDR Invalid real address
2772 * EBADALIGN Real address not aligned on 64-byte boundary
2773 * EBADTRAP API not supported on this processor
2775 * Enable MMU statistic gathering using the buffer at the given real
2776 * address on the current virtual CPU. The new buffer real address
2777 * is given in ARG1, and the previously specified buffer real address
2778 * is returned in RET1, or is returned as zero for the first invocation.
2780 * If the passed in real address argument is zero, this will disable
2781 * MMU statistic collection on the current virtual CPU. If an error is
2782 * returned then no statistics are collected.
2784 * The buffer contents should be initialized to all zeros before being
2785 * given to the hypervisor or else the statistics will be meaningless.
2787 #define HV_FAST_MMUSTAT_CONF 0x102
2790 * TRAP: HV_FAST_TRAP
2791 * FUNCTION: HV_FAST_MMUSTAT_INFO
2793 * RET1: real address
2794 * ERRORS: EBADTRAP API not supported on this processor
2796 * Return the current state and real address of the currently configured
2797 * MMU statistics buffer on the current virtual CPU.
2799 #define HV_FAST_MMUSTAT_INFO 0x103
2801 /* NCS crypto services */
2803 /* ncs_request() sub-function numbers */
2804 #define HV_NCS_QCONF 0x01
2805 #define HV_NCS_QTAIL_UPDATE 0x02
2807 #ifndef __ASSEMBLY__
2808 struct hv_ncs_queue_entry {
2809 /* MAU Control Register */
2810 unsigned long mau_control;
2811 #define MAU_CONTROL_INV_PARITY 0x0000000000002000
2812 #define MAU_CONTROL_STRAND 0x0000000000001800
2813 #define MAU_CONTROL_BUSY 0x0000000000000400
2814 #define MAU_CONTROL_INT 0x0000000000000200
2815 #define MAU_CONTROL_OP 0x00000000000001c0
2816 #define MAU_CONTROL_OP_SHIFT 6
2817 #define MAU_OP_LOAD_MA_MEMORY 0x0
2818 #define MAU_OP_STORE_MA_MEMORY 0x1
2819 #define MAU_OP_MODULAR_MULT 0x2
2820 #define MAU_OP_MODULAR_REDUCE 0x3
2821 #define MAU_OP_MODULAR_EXP_LOOP 0x4
2822 #define MAU_CONTROL_LEN 0x000000000000003f
2823 #define MAU_CONTROL_LEN_SHIFT 0
2825 /* Real address of bytes to load or store bytes
2826 * into/out-of the MAU.
2828 unsigned long mau_mpa;
2830 /* Modular Arithmetic MA Offset Register. */
2831 unsigned long mau_ma;
2833 /* Modular Arithmetic N Prime Register. */
2834 unsigned long mau_np;
2837 struct hv_ncs_qconf_arg {
2838 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2839 unsigned long base; /* Real address base of queue */
2840 unsigned long end; /* Real address end of queue */
2841 unsigned long num_ents; /* Number of entries in queue */
2844 struct hv_ncs_qtail_update_arg {
2845 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2846 unsigned long tail; /* New tail index to use */
2847 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
2848 #define HV_NCS_SYNCFLAG_SYNC 0x00
2849 #define HV_NCS_SYNCFLAG_ASYNC 0x01
2854 * TRAP: HV_FAST_TRAP
2855 * FUNCTION: HV_FAST_NCS_REQUEST
2856 * ARG0: NCS sub-function
2857 * ARG1: sub-function argument real address
2858 * ARG2: size in bytes of sub-function argument
2861 * The MAU chip of the Niagara processor is not directly accessible
2862 * to privileged code, instead it is programmed indirectly via this
2865 * The interfaces defines a queue of MAU operations to perform.
2866 * Privileged code registers a queue with the hypervisor by invoking
2867 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
2868 * base, end, and number of entries of the queue. Each queue entry
2869 * contains a MAU register struct block.
2871 * The privileged code then proceeds to add entries to the queue and
2872 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
2873 * synchronous operations are supported by the current hypervisor,
2874 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
2875 * completion and return HV_EOK, or return an error code.
2877 * The real address of the sub-function argument must be aligned on at
2878 * least an 8-byte boundary.
2880 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
2881 * offset, into the queue and must be less than or equal the 'num_ents'
2882 * argument given in the HV_NCS_QCONF call.
2884 #define HV_FAST_NCS_REQUEST 0x110
2886 #ifndef __ASSEMBLY__
2887 extern unsigned long sun4v_ncs_request(unsigned long request,
2888 unsigned long arg_ra,
2889 unsigned long arg_size);
2892 #define HV_FAST_FIRE_GET_PERFREG 0x120
2893 #define HV_FAST_FIRE_SET_PERFREG 0x121
2895 /* Function numbers for HV_CORE_TRAP. */
2896 #define HV_CORE_SET_VER 0x00
2897 #define HV_CORE_PUTCHAR 0x01
2898 #define HV_CORE_EXIT 0x02
2899 #define HV_CORE_GET_VER 0x03
2901 /* Hypervisor API groups for use with HV_CORE_SET_VER and
2904 #define HV_GRP_SUN4V 0x0000
2905 #define HV_GRP_CORE 0x0001
2906 #define HV_GRP_INTR 0x0002
2907 #define HV_GRP_SOFT_STATE 0x0003
2908 #define HV_GRP_PCI 0x0100
2909 #define HV_GRP_LDOM 0x0101
2910 #define HV_GRP_SVC_CHAN 0x0102
2911 #define HV_GRP_NCS 0x0103
2912 #define HV_GRP_NIAG_PERF 0x0200
2913 #define HV_GRP_FIRE_PERF 0x0201
2914 #define HV_GRP_DIAG 0x0300
2916 #ifndef __ASSEMBLY__
2917 extern unsigned long sun4v_get_version(unsigned long group,
2918 unsigned long *major,
2919 unsigned long *minor);
2920 extern unsigned long sun4v_set_version(unsigned long group,
2921 unsigned long major,
2922 unsigned long minor,
2923 unsigned long *actual_minor);
2925 extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
2926 unsigned long *minor);
2927 extern void sun4v_hvapi_unregister(unsigned long group);
2928 extern int sun4v_hvapi_get(unsigned long group,
2929 unsigned long *major,
2930 unsigned long *minor);
2931 extern void sun4v_hvapi_init(void);
2934 #endif /* !(_SPARC64_HYPERVISOR_H) */
git.samba.org / sfrench / cifs-2.6.git / blob