56e9210733d61aa720ea525b52c07cf3b72656fb
[sfrench/cifs-2.6.git] / include / asm-ia64 / pal.h
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
3
4 /*
5  * Processor Abstraction Layer definitions.
6  *
7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8  * chapter 11 IA-64 Processor Abstraction Layer
9  *
10  * Copyright (C) 1998-2001 Hewlett-Packard Co
11  *      David Mosberger-Tang <davidm@hpl.hp.com>
12  *      Stephane Eranian <eranian@hpl.hp.com>
13  * Copyright (C) 1999 VA Linux Systems
14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16  *
17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
21  * 00/05/25     eranian Support for stack calls, and static physical calls
22  * 00/06/18     eranian Support for stacked physical calls
23  * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
24  *                      Manual Rev 2.2 (Jan 2006)
25  */
26
27 /*
28  * Note that some of these calls use a static-register only calling
29  * convention which has nothing to do with the regular calling
30  * convention.
31  */
32 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
33 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
34 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
35 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
36 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
37 #define PAL_PTCE_INFO           6       /* purge TLB info */
38 #define PAL_VM_INFO             7       /* return supported virtual memory features */
39 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
40 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
41 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
42 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
43 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
44 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
45 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
46 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
47 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
48 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
49 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
50 #define PAL_RSE_INFO            19      /* return rse information */
51 #define PAL_VERSION             20      /* return version of PAL code */
52 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
53 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
54 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
55 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
56 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
57 #define PAL_MC_RESUME           26      /* Return to interrupted process */
58 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
59 #define PAL_HALT                28      /* enter the low power HALT state */
60 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
61 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
62 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
63 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
64 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
65 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
66
67 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
68 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
69 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
70 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
71 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
72 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
73 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
74 #define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
75 #define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
76
77 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
78 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
79 #define PAL_TEST_PROC           258     /* perform late processor self-test */
80 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
81 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
82 #define PAL_VM_TR_READ          261     /* read contents of translation register */
83 #define PAL_GET_PSTATE          262     /* get the current P-state */
84 #define PAL_SET_PSTATE          263     /* set the P-state */
85 #define PAL_BRAND_INFO          274     /* Processor branding information */
86
87 #define PAL_GET_PSTATE_TYPE_LASTSET     0
88 #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
89 #define PAL_GET_PSTATE_TYPE_AVGNORESET  2
90 #define PAL_GET_PSTATE_TYPE_INSTANT     3
91
92 #define PAL_MC_ERROR_INJECT     276     /* Injects processor error or returns injection capabilities */
93
94 #ifndef __ASSEMBLY__
95
96 #include <linux/types.h>
97 #include <asm/fpu.h>
98
99 /*
100  * Data types needed to pass information into PAL procedures and
101  * interpret information returned by them.
102  */
103
104 /* Return status from the PAL procedure */
105 typedef s64                             pal_status_t;
106
107 #define PAL_STATUS_SUCCESS              0       /* No error */
108 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
109 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
110 #define PAL_STATUS_ERROR                (-3)    /* Error */
111 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
112                                                  * specified level and type of
113                                                  * cache without sideeffects
114                                                  * and "restrict" was 1
115                                                  */
116 #define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
117
118 /* Processor cache level in the heirarchy */
119 typedef u64                             pal_cache_level_t;
120 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
121 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
122 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
123
124
125 /* Processor cache type at a particular level in the heirarchy */
126
127 typedef u64                             pal_cache_type_t;
128 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
129 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
130 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
131
132
133 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
134 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
135
136 /* Processor cache line size in bytes  */
137 typedef int                             pal_cache_line_size_t;
138
139 /* Processor cache line state */
140 typedef u64                             pal_cache_line_state_t;
141 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
142 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
143 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
144 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
145
146 typedef struct pal_freq_ratio {
147         u32 den, num;           /* numerator & denominator */
148 } itc_ratio, proc_ratio;
149
150 typedef union  pal_cache_config_info_1_s {
151         struct {
152                 u64             u               : 1,    /* 0 Unified cache ? */
153                                 at              : 2,    /* 2-1 Cache mem attr*/
154                                 reserved        : 5,    /* 7-3 Reserved */
155                                 associativity   : 8,    /* 16-8 Associativity*/
156                                 line_size       : 8,    /* 23-17 Line size */
157                                 stride          : 8,    /* 31-24 Stride */
158                                 store_latency   : 8,    /*39-32 Store latency*/
159                                 load_latency    : 8,    /* 47-40 Load latency*/
160                                 store_hints     : 8,    /* 55-48 Store hints*/
161                                 load_hints      : 8;    /* 63-56 Load hints */
162         } pcci1_bits;
163         u64                     pcci1_data;
164 } pal_cache_config_info_1_t;
165
166 typedef union  pal_cache_config_info_2_s {
167         struct {
168                 u32             cache_size;             /*cache size in bytes*/
169
170
171                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
172                                                          * separation for max
173                                                          * performance.
174                                                          */
175                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
176                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
177                                 reserved        : 8;    /* 63-56 Reserved */
178         } pcci2_bits;
179         u64                     pcci2_data;
180 } pal_cache_config_info_2_t;
181
182
183 typedef struct pal_cache_config_info_s {
184         pal_status_t                    pcci_status;
185         pal_cache_config_info_1_t       pcci_info_1;
186         pal_cache_config_info_2_t       pcci_info_2;
187         u64                             pcci_reserved;
188 } pal_cache_config_info_t;
189
190 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
191 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
192 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
193 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
194 #define pcci_stride             pcci_info_1.pcci1_bits.stride
195 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
196 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
197 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
198 #define pcci_unified            pcci_info_1.pcci1_bits.u
199 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
200 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
201 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
202 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
203
204
205
206 /* Possible values for cache attributes */
207
208 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
209 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
210 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
211                                                  * back depending on TLB
212                                                  * memory attributes
213                                                  */
214
215
216 /* Possible values for cache hints */
217
218 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
219 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
220 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
221
222 /* Processor cache protection  information */
223 typedef union pal_cache_protection_element_u {
224         u32                     pcpi_data;
225         struct {
226                 u32             data_bits       : 8, /* # data bits covered by
227                                                       * each unit of protection
228                                                       */
229
230                                 tagprot_lsb     : 6, /* Least -do- */
231                                 tagprot_msb     : 6, /* Most Sig. tag address
232                                                       * bit that this
233                                                       * protection covers.
234                                                       */
235                                 prot_bits       : 6, /* # of protection bits */
236                                 method          : 4, /* Protection method */
237                                 t_d             : 2; /* Indicates which part
238                                                       * of the cache this
239                                                       * protection encoding
240                                                       * applies.
241                                                       */
242         } pcp_info;
243 } pal_cache_protection_element_t;
244
245 #define pcpi_cache_prot_part    pcp_info.t_d
246 #define pcpi_prot_method        pcp_info.method
247 #define pcpi_prot_bits          pcp_info.prot_bits
248 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
249 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
250 #define pcpi_data_bits          pcp_info.data_bits
251
252 /* Processor cache part encodings */
253 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
254 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
255 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
256                                                  * more significant )
257                                                  */
258 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
259                                                  * more significant )
260                                                  */
261 #define PAL_CACHE_PROT_PART_MAX         6
262
263
264 typedef struct pal_cache_protection_info_s {
265         pal_status_t                    pcpi_status;
266         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
267 } pal_cache_protection_info_t;
268
269
270 /* Processor cache protection method encodings */
271 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
272 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
273 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
274 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
275
276
277 /* Processor cache line identification in the heirarchy */
278 typedef union pal_cache_line_id_u {
279         u64                     pclid_data;
280         struct {
281                 u64             cache_type      : 8,    /* 7-0 cache type */
282                                 level           : 8,    /* 15-8 level of the
283                                                          * cache in the
284                                                          * heirarchy.
285                                                          */
286                                 way             : 8,    /* 23-16 way in the set
287                                                          */
288                                 part            : 8,    /* 31-24 part of the
289                                                          * cache
290                                                          */
291                                 reserved        : 32;   /* 63-32 is reserved*/
292         } pclid_info_read;
293         struct {
294                 u64             cache_type      : 8,    /* 7-0 cache type */
295                                 level           : 8,    /* 15-8 level of the
296                                                          * cache in the
297                                                          * heirarchy.
298                                                          */
299                                 way             : 8,    /* 23-16 way in the set
300                                                          */
301                                 part            : 8,    /* 31-24 part of the
302                                                          * cache
303                                                          */
304                                 mesi            : 8,    /* 39-32 cache line
305                                                          * state
306                                                          */
307                                 start           : 8,    /* 47-40 lsb of data to
308                                                          * invert
309                                                          */
310                                 length          : 8,    /* 55-48 #bits to
311                                                          * invert
312                                                          */
313                                 trigger         : 8;    /* 63-56 Trigger error
314                                                          * by doing a load
315                                                          * after the write
316                                                          */
317
318         } pclid_info_write;
319 } pal_cache_line_id_u_t;
320
321 #define pclid_read_part         pclid_info_read.part
322 #define pclid_read_way          pclid_info_read.way
323 #define pclid_read_level        pclid_info_read.level
324 #define pclid_read_cache_type   pclid_info_read.cache_type
325
326 #define pclid_write_trigger     pclid_info_write.trigger
327 #define pclid_write_length      pclid_info_write.length
328 #define pclid_write_start       pclid_info_write.start
329 #define pclid_write_mesi        pclid_info_write.mesi
330 #define pclid_write_part        pclid_info_write.part
331 #define pclid_write_way         pclid_info_write.way
332 #define pclid_write_level       pclid_info_write.level
333 #define pclid_write_cache_type  pclid_info_write.cache_type
334
335 /* Processor cache line part encodings */
336 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
337 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
338 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
339 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
340 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
341                                                          * protection
342                                                          */
343 typedef struct pal_cache_line_info_s {
344         pal_status_t            pcli_status;            /* Return status of the read cache line
345                                                          * info call.
346                                                          */
347         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
348         u64                     pcli_data_len;          /* data length in bits */
349         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
350
351 } pal_cache_line_info_t;
352
353
354 /* Machine Check related crap */
355
356 /* Pending event status bits  */
357 typedef u64                                     pal_mc_pending_events_t;
358
359 #define PAL_MC_PENDING_MCA                      (1 << 0)
360 #define PAL_MC_PENDING_INIT                     (1 << 1)
361
362 /* Error information type */
363 typedef u64                                     pal_mc_info_index_t;
364
365 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
366 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
367 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
368 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
369 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
370 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
371 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
372 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
373                                                          * dependent
374                                                          */
375
376
377 typedef struct pal_process_state_info_s {
378         u64             reserved1       : 2,
379                         rz              : 1,    /* PAL_CHECK processor
380                                                  * rendezvous
381                                                  * successful.
382                                                  */
383
384                         ra              : 1,    /* PAL_CHECK attempted
385                                                  * a rendezvous.
386                                                  */
387                         me              : 1,    /* Distinct multiple
388                                                  * errors occurred
389                                                  */
390
391                         mn              : 1,    /* Min. state save
392                                                  * area has been
393                                                  * registered with PAL
394                                                  */
395
396                         sy              : 1,    /* Storage integrity
397                                                  * synched
398                                                  */
399
400
401                         co              : 1,    /* Continuable */
402                         ci              : 1,    /* MC isolated */
403                         us              : 1,    /* Uncontained storage
404                                                  * damage.
405                                                  */
406
407
408                         hd              : 1,    /* Non-essential hw
409                                                  * lost (no loss of
410                                                  * functionality)
411                                                  * causing the
412                                                  * processor to run in
413                                                  * degraded mode.
414                                                  */
415
416                         tl              : 1,    /* 1 => MC occurred
417                                                  * after an instr was
418                                                  * executed but before
419                                                  * the trap that
420                                                  * resulted from instr
421                                                  * execution was
422                                                  * generated.
423                                                  * (Trap Lost )
424                                                  */
425                         mi              : 1,    /* More information available
426                                                  * call PAL_MC_ERROR_INFO
427                                                  */
428                         pi              : 1,    /* Precise instruction pointer */
429                         pm              : 1,    /* Precise min-state save area */
430
431                         dy              : 1,    /* Processor dynamic
432                                                  * state valid
433                                                  */
434
435
436                         in              : 1,    /* 0 = MC, 1 = INIT */
437                         rs              : 1,    /* RSE valid */
438                         cm              : 1,    /* MC corrected */
439                         ex              : 1,    /* MC is expected */
440                         cr              : 1,    /* Control regs valid*/
441                         pc              : 1,    /* Perf cntrs valid */
442                         dr              : 1,    /* Debug regs valid */
443                         tr              : 1,    /* Translation regs
444                                                  * valid
445                                                  */
446                         rr              : 1,    /* Region regs valid */
447                         ar              : 1,    /* App regs valid */
448                         br              : 1,    /* Branch regs valid */
449                         pr              : 1,    /* Predicate registers
450                                                  * valid
451                                                  */
452
453                         fp              : 1,    /* fp registers valid*/
454                         b1              : 1,    /* Preserved bank one
455                                                  * general registers
456                                                  * are valid
457                                                  */
458                         b0              : 1,    /* Preserved bank zero
459                                                  * general registers
460                                                  * are valid
461                                                  */
462                         gr              : 1,    /* General registers
463                                                  * are valid
464                                                  * (excl. banked regs)
465                                                  */
466                         dsize           : 16,   /* size of dynamic
467                                                  * state returned
468                                                  * by the processor
469                                                  */
470
471                         se              : 1,    /* Shared error.  MCA in a
472                                                    shared structure */
473                         reserved2       : 10,
474                         cc              : 1,    /* Cache check */
475                         tc              : 1,    /* TLB check */
476                         bc              : 1,    /* Bus check */
477                         rc              : 1,    /* Register file check */
478                         uc              : 1;    /* Uarch check */
479
480 } pal_processor_state_info_t;
481
482 typedef struct pal_cache_check_info_s {
483         u64             op              : 4,    /* Type of cache
484                                                  * operation that
485                                                  * caused the machine
486                                                  * check.
487                                                  */
488                         level           : 2,    /* Cache level */
489                         reserved1       : 2,
490                         dl              : 1,    /* Failure in data part
491                                                  * of cache line
492                                                  */
493                         tl              : 1,    /* Failure in tag part
494                                                  * of cache line
495                                                  */
496                         dc              : 1,    /* Failure in dcache */
497                         ic              : 1,    /* Failure in icache */
498                         mesi            : 3,    /* Cache line state */
499                         mv              : 1,    /* mesi valid */
500                         way             : 5,    /* Way in which the
501                                                  * error occurred
502                                                  */
503                         wiv             : 1,    /* Way field valid */
504                         reserved2       : 1,
505                         dp              : 1,    /* Data poisoned on MBE */
506                         reserved3       : 8,
507
508                         index           : 20,   /* Cache line index */
509                         reserved4       : 2,
510
511                         is              : 1,    /* instruction set (1 == ia32) */
512                         iv              : 1,    /* instruction set field valid */
513                         pl              : 2,    /* privilege level */
514                         pv              : 1,    /* privilege level field valid */
515                         mcc             : 1,    /* Machine check corrected */
516                         tv              : 1,    /* Target address
517                                                  * structure is valid
518                                                  */
519                         rq              : 1,    /* Requester identifier
520                                                  * structure is valid
521                                                  */
522                         rp              : 1,    /* Responder identifier
523                                                  * structure is valid
524                                                  */
525                         pi              : 1;    /* Precise instruction pointer
526                                                  * structure is valid
527                                                  */
528 } pal_cache_check_info_t;
529
530 typedef struct pal_tlb_check_info_s {
531
532         u64             tr_slot         : 8,    /* Slot# of TR where
533                                                  * error occurred
534                                                  */
535                         trv             : 1,    /* tr_slot field is valid */
536                         reserved1       : 1,
537                         level           : 2,    /* TLB level where failure occurred */
538                         reserved2       : 4,
539                         dtr             : 1,    /* Fail in data TR */
540                         itr             : 1,    /* Fail in inst TR */
541                         dtc             : 1,    /* Fail in data TC */
542                         itc             : 1,    /* Fail in inst. TC */
543                         op              : 4,    /* Cache operation */
544                         reserved3       : 30,
545
546                         is              : 1,    /* instruction set (1 == ia32) */
547                         iv              : 1,    /* instruction set field valid */
548                         pl              : 2,    /* privilege level */
549                         pv              : 1,    /* privilege level field valid */
550                         mcc             : 1,    /* Machine check corrected */
551                         tv              : 1,    /* Target address
552                                                  * structure is valid
553                                                  */
554                         rq              : 1,    /* Requester identifier
555                                                  * structure is valid
556                                                  */
557                         rp              : 1,    /* Responder identifier
558                                                  * structure is valid
559                                                  */
560                         pi              : 1;    /* Precise instruction pointer
561                                                  * structure is valid
562                                                  */
563 } pal_tlb_check_info_t;
564
565 typedef struct pal_bus_check_info_s {
566         u64             size            : 5,    /* Xaction size */
567                         ib              : 1,    /* Internal bus error */
568                         eb              : 1,    /* External bus error */
569                         cc              : 1,    /* Error occurred
570                                                  * during cache-cache
571                                                  * transfer.
572                                                  */
573                         type            : 8,    /* Bus xaction type*/
574                         sev             : 5,    /* Bus error severity*/
575                         hier            : 2,    /* Bus hierarchy level */
576                         dp              : 1,    /* Data poisoned on MBE */
577                         bsi             : 8,    /* Bus error status
578                                                  * info
579                                                  */
580                         reserved2       : 22,
581
582                         is              : 1,    /* instruction set (1 == ia32) */
583                         iv              : 1,    /* instruction set field valid */
584                         pl              : 2,    /* privilege level */
585                         pv              : 1,    /* privilege level field valid */
586                         mcc             : 1,    /* Machine check corrected */
587                         tv              : 1,    /* Target address
588                                                  * structure is valid
589                                                  */
590                         rq              : 1,    /* Requester identifier
591                                                  * structure is valid
592                                                  */
593                         rp              : 1,    /* Responder identifier
594                                                  * structure is valid
595                                                  */
596                         pi              : 1;    /* Precise instruction pointer
597                                                  * structure is valid
598                                                  */
599 } pal_bus_check_info_t;
600
601 typedef struct pal_reg_file_check_info_s {
602         u64             id              : 4,    /* Register file identifier */
603                         op              : 4,    /* Type of register
604                                                  * operation that
605                                                  * caused the machine
606                                                  * check.
607                                                  */
608                         reg_num         : 7,    /* Register number */
609                         rnv             : 1,    /* reg_num valid */
610                         reserved2       : 38,
611
612                         is              : 1,    /* instruction set (1 == ia32) */
613                         iv              : 1,    /* instruction set field valid */
614                         pl              : 2,    /* privilege level */
615                         pv              : 1,    /* privilege level field valid */
616                         mcc             : 1,    /* Machine check corrected */
617                         reserved3       : 3,
618                         pi              : 1;    /* Precise instruction pointer
619                                                  * structure is valid
620                                                  */
621 } pal_reg_file_check_info_t;
622
623 typedef struct pal_uarch_check_info_s {
624         u64             sid             : 5,    /* Structure identification */
625                         level           : 3,    /* Level of failure */
626                         array_id        : 4,    /* Array identification */
627                         op              : 4,    /* Type of
628                                                  * operation that
629                                                  * caused the machine
630                                                  * check.
631                                                  */
632                         way             : 6,    /* Way of structure */
633                         wv              : 1,    /* way valid */
634                         xv              : 1,    /* index valid */
635                         reserved1       : 8,
636                         index           : 8,    /* Index or set of the uarch
637                                                  * structure that failed.
638                                                  */
639                         reserved2       : 24,
640
641                         is              : 1,    /* instruction set (1 == ia32) */
642                         iv              : 1,    /* instruction set field valid */
643                         pl              : 2,    /* privilege level */
644                         pv              : 1,    /* privilege level field valid */
645                         mcc             : 1,    /* Machine check corrected */
646                         tv              : 1,    /* Target address
647                                                  * structure is valid
648                                                  */
649                         rq              : 1,    /* Requester identifier
650                                                  * structure is valid
651                                                  */
652                         rp              : 1,    /* Responder identifier
653                                                  * structure is valid
654                                                  */
655                         pi              : 1;    /* Precise instruction pointer
656                                                  * structure is valid
657                                                  */
658 } pal_uarch_check_info_t;
659
660 typedef union pal_mc_error_info_u {
661         u64                             pmei_data;
662         pal_processor_state_info_t      pme_processor;
663         pal_cache_check_info_t          pme_cache;
664         pal_tlb_check_info_t            pme_tlb;
665         pal_bus_check_info_t            pme_bus;
666         pal_reg_file_check_info_t       pme_reg_file;
667         pal_uarch_check_info_t          pme_uarch;
668 } pal_mc_error_info_t;
669
670 #define pmci_proc_unknown_check                 pme_processor.uc
671 #define pmci_proc_bus_check                     pme_processor.bc
672 #define pmci_proc_tlb_check                     pme_processor.tc
673 #define pmci_proc_cache_check                   pme_processor.cc
674 #define pmci_proc_dynamic_state_size            pme_processor.dsize
675 #define pmci_proc_gpr_valid                     pme_processor.gr
676 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
677 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
678 #define pmci_proc_fp_valid                      pme_processor.fp
679 #define pmci_proc_predicate_regs_valid          pme_processor.pr
680 #define pmci_proc_branch_regs_valid             pme_processor.br
681 #define pmci_proc_app_regs_valid                pme_processor.ar
682 #define pmci_proc_region_regs_valid             pme_processor.rr
683 #define pmci_proc_translation_regs_valid        pme_processor.tr
684 #define pmci_proc_debug_regs_valid              pme_processor.dr
685 #define pmci_proc_perf_counters_valid           pme_processor.pc
686 #define pmci_proc_control_regs_valid            pme_processor.cr
687 #define pmci_proc_machine_check_expected        pme_processor.ex
688 #define pmci_proc_machine_check_corrected       pme_processor.cm
689 #define pmci_proc_rse_valid                     pme_processor.rs
690 #define pmci_proc_machine_check_or_init         pme_processor.in
691 #define pmci_proc_dynamic_state_valid           pme_processor.dy
692 #define pmci_proc_operation                     pme_processor.op
693 #define pmci_proc_trap_lost                     pme_processor.tl
694 #define pmci_proc_hardware_damage               pme_processor.hd
695 #define pmci_proc_uncontained_storage_damage    pme_processor.us
696 #define pmci_proc_machine_check_isolated        pme_processor.ci
697 #define pmci_proc_continuable                   pme_processor.co
698 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
699 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
700 #define pmci_proc_distinct_multiple_errors      pme_processor.me
701 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
702 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
703
704
705 #define pmci_cache_level                        pme_cache.level
706 #define pmci_cache_line_state                   pme_cache.mesi
707 #define pmci_cache_line_state_valid             pme_cache.mv
708 #define pmci_cache_line_index                   pme_cache.index
709 #define pmci_cache_instr_cache_fail             pme_cache.ic
710 #define pmci_cache_data_cache_fail              pme_cache.dc
711 #define pmci_cache_line_tag_fail                pme_cache.tl
712 #define pmci_cache_line_data_fail               pme_cache.dl
713 #define pmci_cache_operation                    pme_cache.op
714 #define pmci_cache_way_valid                    pme_cache.wv
715 #define pmci_cache_target_address_valid         pme_cache.tv
716 #define pmci_cache_way                          pme_cache.way
717 #define pmci_cache_mc                           pme_cache.mc
718
719 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
720 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
721 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
722 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
723 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
724 #define pmci_tlb_mc                             pme_tlb.mc
725
726 #define pmci_bus_status_info                    pme_bus.bsi
727 #define pmci_bus_req_address_valid              pme_bus.rq
728 #define pmci_bus_resp_address_valid             pme_bus.rp
729 #define pmci_bus_target_address_valid           pme_bus.tv
730 #define pmci_bus_error_severity                 pme_bus.sev
731 #define pmci_bus_transaction_type               pme_bus.type
732 #define pmci_bus_cache_cache_transfer           pme_bus.cc
733 #define pmci_bus_transaction_size               pme_bus.size
734 #define pmci_bus_internal_error                 pme_bus.ib
735 #define pmci_bus_external_error                 pme_bus.eb
736 #define pmci_bus_mc                             pme_bus.mc
737
738 /*
739  * NOTE: this min_state_save area struct only includes the 1KB
740  * architectural state save area.  The other 3 KB is scratch space
741  * for PAL.
742  */
743
744 typedef struct pal_min_state_area_s {
745         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
746         u64     pmsa_gr[15];            /* GR1  - GR15             */
747         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
748         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
749         u64     pmsa_pr;                /* predicate registers     */
750         u64     pmsa_br0;               /* branch register 0       */
751         u64     pmsa_rsc;               /* ar.rsc                  */
752         u64     pmsa_iip;               /* cr.iip                  */
753         u64     pmsa_ipsr;              /* cr.ipsr                 */
754         u64     pmsa_ifs;               /* cr.ifs                  */
755         u64     pmsa_xip;               /* previous iip            */
756         u64     pmsa_xpsr;              /* previous psr            */
757         u64     pmsa_xfs;               /* previous ifs            */
758         u64     pmsa_br1;               /* branch register 1       */
759         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
760 } pal_min_state_area_t;
761
762
763 struct ia64_pal_retval {
764         /*
765          * A zero status value indicates call completed without error.
766          * A negative status value indicates reason of call failure.
767          * A positive status value indicates success but an
768          * informational value should be printed (e.g., "reboot for
769          * change to take effect").
770          */
771         s64 status;
772         u64 v0;
773         u64 v1;
774         u64 v2;
775 };
776
777 /*
778  * Note: Currently unused PAL arguments are generally labeled
779  * "reserved" so the value specified in the PAL documentation
780  * (generally 0) MUST be passed.  Reserved parameters are not optional
781  * parameters.
782  */
783 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
784 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
785 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
786 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
787 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
788 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
789
790 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
791         struct ia64_fpreg fr[6];                        \
792         ia64_save_scratch_fpregs(fr);                   \
793         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
794         ia64_load_scratch_fpregs(fr);                   \
795 } while (0)
796
797 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
798         struct ia64_fpreg fr[6];                        \
799         ia64_save_scratch_fpregs(fr);                   \
800         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
801         ia64_load_scratch_fpregs(fr);                   \
802 } while (0)
803
804 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
805         struct ia64_fpreg fr[6];                                \
806         ia64_save_scratch_fpregs(fr);                           \
807         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
808         ia64_load_scratch_fpregs(fr);                           \
809 } while (0)
810
811 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
812         struct ia64_fpreg fr[6];                                \
813         ia64_save_scratch_fpregs(fr);                           \
814         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
815         ia64_load_scratch_fpregs(fr);                           \
816 } while (0)
817
818 typedef int (*ia64_pal_handler) (u64, ...);
819 extern ia64_pal_handler ia64_pal;
820 extern void ia64_pal_handler_init (void *);
821
822 extern ia64_pal_handler ia64_pal;
823
824 extern pal_cache_config_info_t          l0d_cache_config_info;
825 extern pal_cache_config_info_t          l0i_cache_config_info;
826 extern pal_cache_config_info_t          l1_cache_config_info;
827 extern pal_cache_config_info_t          l2_cache_config_info;
828
829 extern pal_cache_protection_info_t      l0d_cache_protection_info;
830 extern pal_cache_protection_info_t      l0i_cache_protection_info;
831 extern pal_cache_protection_info_t      l1_cache_protection_info;
832 extern pal_cache_protection_info_t      l2_cache_protection_info;
833
834 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
835                                                                   pal_cache_type_t);
836
837 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
838                                                                       pal_cache_type_t);
839
840
841 extern void                             pal_error(int);
842
843
844 /* Useful wrappers for the current list of pal procedures */
845
846 typedef union pal_bus_features_u {
847         u64     pal_bus_features_val;
848         struct {
849                 u64     pbf_reserved1                           :       29;
850                 u64     pbf_req_bus_parking                     :       1;
851                 u64     pbf_bus_lock_mask                       :       1;
852                 u64     pbf_enable_half_xfer_rate               :       1;
853                 u64     pbf_reserved2                           :       20;
854                 u64     pbf_enable_shared_line_replace          :       1;
855                 u64     pbf_enable_exclusive_line_replace       :       1;
856                 u64     pbf_disable_xaction_queueing            :       1;
857                 u64     pbf_disable_resp_err_check              :       1;
858                 u64     pbf_disable_berr_check                  :       1;
859                 u64     pbf_disable_bus_req_internal_err_signal :       1;
860                 u64     pbf_disable_bus_req_berr_signal         :       1;
861                 u64     pbf_disable_bus_init_event_check        :       1;
862                 u64     pbf_disable_bus_init_event_signal       :       1;
863                 u64     pbf_disable_bus_addr_err_check          :       1;
864                 u64     pbf_disable_bus_addr_err_signal         :       1;
865                 u64     pbf_disable_bus_data_err_check          :       1;
866         } pal_bus_features_s;
867 } pal_bus_features_u_t;
868
869 extern void pal_bus_features_print (u64);
870
871 /* Provide information about configurable processor bus features */
872 static inline s64
873 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
874                            pal_bus_features_u_t *features_status,
875                            pal_bus_features_u_t *features_control)
876 {
877         struct ia64_pal_retval iprv;
878         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
879         if (features_avail)
880                 features_avail->pal_bus_features_val = iprv.v0;
881         if (features_status)
882                 features_status->pal_bus_features_val = iprv.v1;
883         if (features_control)
884                 features_control->pal_bus_features_val = iprv.v2;
885         return iprv.status;
886 }
887
888 /* Enables/disables specific processor bus features */
889 static inline s64
890 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
891 {
892         struct ia64_pal_retval iprv;
893         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
894         return iprv.status;
895 }
896
897 /* Get detailed cache information */
898 static inline s64
899 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
900 {
901         struct ia64_pal_retval iprv;
902
903         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
904
905         if (iprv.status == 0) {
906                 conf->pcci_status                 = iprv.status;
907                 conf->pcci_info_1.pcci1_data      = iprv.v0;
908                 conf->pcci_info_2.pcci2_data      = iprv.v1;
909                 conf->pcci_reserved               = iprv.v2;
910         }
911         return iprv.status;
912
913 }
914
915 /* Get detailed cche protection information */
916 static inline s64
917 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
918 {
919         struct ia64_pal_retval iprv;
920
921         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
922
923         if (iprv.status == 0) {
924                 prot->pcpi_status           = iprv.status;
925                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
926                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
927                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
928                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
929                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
930                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
931         }
932         return iprv.status;
933 }
934
935 /*
936  * Flush the processor instruction or data caches.  *PROGRESS must be
937  * initialized to zero before calling this for the first time..
938  */
939 static inline s64
940 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
941 {
942         struct ia64_pal_retval iprv;
943         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
944         if (vector)
945                 *vector = iprv.v0;
946         *progress = iprv.v1;
947         return iprv.status;
948 }
949
950
951 /* Initialize the processor controlled caches */
952 static inline s64
953 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
954 {
955         struct ia64_pal_retval iprv;
956         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
957         return iprv.status;
958 }
959
960 /* Initialize the tags and data of a data or unified cache line of
961  * processor controlled cache to known values without the availability
962  * of backing memory.
963  */
964 static inline s64
965 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
966 {
967         struct ia64_pal_retval iprv;
968         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
969         return iprv.status;
970 }
971
972
973 /* Read the data and tag of a processor controlled cache line for diags */
974 static inline s64
975 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
976 {
977         struct ia64_pal_retval iprv;
978         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
979                                 physical_addr, 0);
980         return iprv.status;
981 }
982
983 /* Return summary information about the heirarchy of caches controlled by the processor */
984 static inline s64
985 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
986 {
987         struct ia64_pal_retval iprv;
988         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
989         if (cache_levels)
990                 *cache_levels = iprv.v0;
991         if (unique_caches)
992                 *unique_caches = iprv.v1;
993         return iprv.status;
994 }
995
996 /* Write the data and tag of a processor-controlled cache line for diags */
997 static inline s64
998 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
999 {
1000         struct ia64_pal_retval iprv;
1001         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1002                                 physical_addr, data);
1003         return iprv.status;
1004 }
1005
1006
1007 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1008 static inline s64
1009 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1010                     u64 *buffer_size, u64 *buffer_align)
1011 {
1012         struct ia64_pal_retval iprv;
1013         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1014         if (buffer_size)
1015                 *buffer_size = iprv.v0;
1016         if (buffer_align)
1017                 *buffer_align = iprv.v1;
1018         return iprv.status;
1019 }
1020
1021 /* Copy relocatable PAL procedures from ROM to memory */
1022 static inline s64
1023 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1024 {
1025         struct ia64_pal_retval iprv;
1026         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1027         if (pal_proc_offset)
1028                 *pal_proc_offset = iprv.v0;
1029         return iprv.status;
1030 }
1031
1032 /* Return the number of instruction and data debug register pairs */
1033 static inline s64
1034 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1035 {
1036         struct ia64_pal_retval iprv;
1037         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1038         if (inst_regs)
1039                 *inst_regs = iprv.v0;
1040         if (data_regs)
1041                 *data_regs = iprv.v1;
1042
1043         return iprv.status;
1044 }
1045
1046 #ifdef TBD
1047 /* Switch from IA64-system environment to IA-32 system environment */
1048 static inline s64
1049 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1050 {
1051         struct ia64_pal_retval iprv;
1052         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1053         return iprv.status;
1054 }
1055 #endif
1056
1057 /* Get unique geographical address of this processor on its bus */
1058 static inline s64
1059 ia64_pal_fixed_addr (u64 *global_unique_addr)
1060 {
1061         struct ia64_pal_retval iprv;
1062         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1063         if (global_unique_addr)
1064                 *global_unique_addr = iprv.v0;
1065         return iprv.status;
1066 }
1067
1068 /* Get base frequency of the platform if generated by the processor */
1069 static inline s64
1070 ia64_pal_freq_base (u64 *platform_base_freq)
1071 {
1072         struct ia64_pal_retval iprv;
1073         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1074         if (platform_base_freq)
1075                 *platform_base_freq = iprv.v0;
1076         return iprv.status;
1077 }
1078
1079 /*
1080  * Get the ratios for processor frequency, bus frequency and interval timer to
1081  * to base frequency of the platform
1082  */
1083 static inline s64
1084 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1085                       struct pal_freq_ratio *itc_ratio)
1086 {
1087         struct ia64_pal_retval iprv;
1088         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1089         if (proc_ratio)
1090                 *(u64 *)proc_ratio = iprv.v0;
1091         if (bus_ratio)
1092                 *(u64 *)bus_ratio = iprv.v1;
1093         if (itc_ratio)
1094                 *(u64 *)itc_ratio = iprv.v2;
1095         return iprv.status;
1096 }
1097
1098 /*
1099  * Get the current hardware resource sharing policy of the processor
1100  */
1101 static inline s64
1102 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1103                         u64 *la)
1104 {
1105         struct ia64_pal_retval iprv;
1106         PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1107         if (cur_policy)
1108                 *cur_policy = iprv.v0;
1109         if (num_impacted)
1110                 *num_impacted = iprv.v1;
1111         if (la)
1112                 *la = iprv.v2;
1113         return iprv.status;
1114 }
1115
1116 /* Make the processor enter HALT or one of the implementation dependent low
1117  * power states where prefetching and execution are suspended and cache and
1118  * TLB coherency is not maintained.
1119  */
1120 static inline s64
1121 ia64_pal_halt (u64 halt_state)
1122 {
1123         struct ia64_pal_retval iprv;
1124         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1125         return iprv.status;
1126 }
1127
1128 typedef union pal_power_mgmt_info_u {
1129         u64                     ppmi_data;
1130         struct {
1131                u64              exit_latency            : 16,
1132                                 entry_latency           : 16,
1133                                 power_consumption       : 28,
1134                                 im                      : 1,
1135                                 co                      : 1,
1136                                 reserved                : 2;
1137         } pal_power_mgmt_info_s;
1138 } pal_power_mgmt_info_u_t;
1139
1140 /* Return information about processor's optional power management capabilities. */
1141 static inline s64
1142 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1143 {
1144         struct ia64_pal_retval iprv;
1145         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1146         return iprv.status;
1147 }
1148
1149 /* Get the current P-state information */
1150 static inline s64
1151 ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1152 {
1153         struct ia64_pal_retval iprv;
1154         PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1155         *pstate_index = iprv.v0;
1156         return iprv.status;
1157 }
1158
1159 /* Set the P-state */
1160 static inline s64
1161 ia64_pal_set_pstate (u64 pstate_index)
1162 {
1163         struct ia64_pal_retval iprv;
1164         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1165         return iprv.status;
1166 }
1167
1168 /* Processor branding information*/
1169 static inline s64
1170 ia64_pal_get_brand_info (char *brand_info)
1171 {
1172         struct ia64_pal_retval iprv;
1173         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1174         return iprv.status;
1175 }
1176
1177 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1178  * suspended, but cache and TLB coherency is maintained.
1179  */
1180 static inline s64
1181 ia64_pal_halt_light (void)
1182 {
1183         struct ia64_pal_retval iprv;
1184         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1185         return iprv.status;
1186 }
1187
1188 /* Clear all the processor error logging   registers and reset the indicator that allows
1189  * the error logging registers to be written. This procedure also checks the pending
1190  * machine check bit and pending INIT bit and reports their states.
1191  */
1192 static inline s64
1193 ia64_pal_mc_clear_log (u64 *pending_vector)
1194 {
1195         struct ia64_pal_retval iprv;
1196         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1197         if (pending_vector)
1198                 *pending_vector = iprv.v0;
1199         return iprv.status;
1200 }
1201
1202 /* Ensure that all outstanding transactions in a processor are completed or that any
1203  * MCA due to thes outstanding transaction is taken.
1204  */
1205 static inline s64
1206 ia64_pal_mc_drain (void)
1207 {
1208         struct ia64_pal_retval iprv;
1209         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1210         return iprv.status;
1211 }
1212
1213 /* Return the machine check dynamic processor state */
1214 static inline s64
1215 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1216 {
1217         struct ia64_pal_retval iprv;
1218         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1219         if (size)
1220                 *size = iprv.v0;
1221         if (pds)
1222                 *pds = iprv.v1;
1223         return iprv.status;
1224 }
1225
1226 /* Return processor machine check information */
1227 static inline s64
1228 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1229 {
1230         struct ia64_pal_retval iprv;
1231         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1232         if (size)
1233                 *size = iprv.v0;
1234         if (error_info)
1235                 *error_info = iprv.v1;
1236         return iprv.status;
1237 }
1238
1239 /* Injects the requested processor error or returns info on
1240  * supported injection capabilities for current processor implementation
1241  */
1242 static inline s64
1243 ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1244                         u64 err_data_buffer, u64 *capabilities, u64 *resources)
1245 {
1246         struct ia64_pal_retval iprv;
1247         PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1248                           err_struct_info, err_data_buffer);
1249         if (capabilities)
1250                 *capabilities= iprv.v0;
1251         if (resources)
1252                 *resources= iprv.v1;
1253         return iprv.status;
1254 }
1255
1256 static inline s64
1257 ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1258                         u64 err_data_buffer, u64 *capabilities, u64 *resources)
1259 {
1260         struct ia64_pal_retval iprv;
1261         PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1262                           err_struct_info, err_data_buffer);
1263         if (capabilities)
1264                 *capabilities= iprv.v0;
1265         if (resources)
1266                 *resources= iprv.v1;
1267         return iprv.status;
1268 }
1269
1270 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1271  * attempt to correct any expected machine checks.
1272  */
1273 static inline s64
1274 ia64_pal_mc_expected (u64 expected, u64 *previous)
1275 {
1276         struct ia64_pal_retval iprv;
1277         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1278         if (previous)
1279                 *previous = iprv.v0;
1280         return iprv.status;
1281 }
1282
1283 /* Register a platform dependent location with PAL to which it can save
1284  * minimal processor state in the event of a machine check or initialization
1285  * event.
1286  */
1287 static inline s64
1288 ia64_pal_mc_register_mem (u64 physical_addr)
1289 {
1290         struct ia64_pal_retval iprv;
1291         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1292         return iprv.status;
1293 }
1294
1295 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1296  * and resume execution
1297  */
1298 static inline s64
1299 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1300 {
1301         struct ia64_pal_retval iprv;
1302         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1303         return iprv.status;
1304 }
1305
1306 /* Return the memory attributes implemented by the processor */
1307 static inline s64
1308 ia64_pal_mem_attrib (u64 *mem_attrib)
1309 {
1310         struct ia64_pal_retval iprv;
1311         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1312         if (mem_attrib)
1313                 *mem_attrib = iprv.v0 & 0xff;
1314         return iprv.status;
1315 }
1316
1317 /* Return the amount of memory needed for second phase of processor
1318  * self-test and the required alignment of memory.
1319  */
1320 static inline s64
1321 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1322 {
1323         struct ia64_pal_retval iprv;
1324         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1325         if (bytes_needed)
1326                 *bytes_needed = iprv.v0;
1327         if (alignment)
1328                 *alignment = iprv.v1;
1329         return iprv.status;
1330 }
1331
1332 typedef union pal_perf_mon_info_u {
1333         u64                       ppmi_data;
1334         struct {
1335                u64              generic         : 8,
1336                                 width           : 8,
1337                                 cycles          : 8,
1338                                 retired         : 8,
1339                                 reserved        : 32;
1340         } pal_perf_mon_info_s;
1341 } pal_perf_mon_info_u_t;
1342
1343 /* Return the performance monitor information about what can be counted
1344  * and how to configure the monitors to count the desired events.
1345  */
1346 static inline s64
1347 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1348 {
1349         struct ia64_pal_retval iprv;
1350         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1351         if (pm_info)
1352                 pm_info->ppmi_data = iprv.v0;
1353         return iprv.status;
1354 }
1355
1356 /* Specifies the physical address of the processor interrupt block
1357  * and I/O port space.
1358  */
1359 static inline s64
1360 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1361 {
1362         struct ia64_pal_retval iprv;
1363         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1364         return iprv.status;
1365 }
1366
1367 /* Set the SAL PMI entrypoint in memory */
1368 static inline s64
1369 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1370 {
1371         struct ia64_pal_retval iprv;
1372         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1373         return iprv.status;
1374 }
1375
1376 struct pal_features_s;
1377 /* Provide information about configurable processor features */
1378 static inline s64
1379 ia64_pal_proc_get_features (u64 *features_avail,
1380                             u64 *features_status,
1381                             u64 *features_control)
1382 {
1383         struct ia64_pal_retval iprv;
1384         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1385         if (iprv.status == 0) {
1386                 *features_avail   = iprv.v0;
1387                 *features_status  = iprv.v1;
1388                 *features_control = iprv.v2;
1389         }
1390         return iprv.status;
1391 }
1392
1393 /* Enable/disable processor dependent features */
1394 static inline s64
1395 ia64_pal_proc_set_features (u64 feature_select)
1396 {
1397         struct ia64_pal_retval iprv;
1398         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1399         return iprv.status;
1400 }
1401
1402 /*
1403  * Put everything in a struct so we avoid the global offset table whenever
1404  * possible.
1405  */
1406 typedef struct ia64_ptce_info_s {
1407         u64             base;
1408         u32             count[2];
1409         u32             stride[2];
1410 } ia64_ptce_info_t;
1411
1412 /* Return the information required for the architected loop used to purge
1413  * (initialize) the entire TC
1414  */
1415 static inline s64
1416 ia64_get_ptce (ia64_ptce_info_t *ptce)
1417 {
1418         struct ia64_pal_retval iprv;
1419
1420         if (!ptce)
1421                 return -1;
1422
1423         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1424         if (iprv.status == 0) {
1425                 ptce->base = iprv.v0;
1426                 ptce->count[0] = iprv.v1 >> 32;
1427                 ptce->count[1] = iprv.v1 & 0xffffffff;
1428                 ptce->stride[0] = iprv.v2 >> 32;
1429                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1430         }
1431         return iprv.status;
1432 }
1433
1434 /* Return info about implemented application and control registers. */
1435 static inline s64
1436 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1437 {
1438         struct ia64_pal_retval iprv;
1439         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1440         if (reg_info_1)
1441                 *reg_info_1 = iprv.v0;
1442         if (reg_info_2)
1443                 *reg_info_2 = iprv.v1;
1444         return iprv.status;
1445 }
1446
1447 typedef union pal_hints_u {
1448         u64                     ph_data;
1449         struct {
1450                u64              si              : 1,
1451                                 li              : 1,
1452                                 reserved        : 62;
1453         } pal_hints_s;
1454 } pal_hints_u_t;
1455
1456 /* Return information about the register stack and RSE for this processor
1457  * implementation.
1458  */
1459 static inline s64
1460 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1461 {
1462         struct ia64_pal_retval iprv;
1463         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1464         if (num_phys_stacked)
1465                 *num_phys_stacked = iprv.v0;
1466         if (hints)
1467                 hints->ph_data = iprv.v1;
1468         return iprv.status;
1469 }
1470
1471 /*
1472  * Set the current hardware resource sharing policy of the processor
1473  */
1474 static inline s64
1475 ia64_pal_set_hw_policy (u64 policy)
1476 {
1477         struct ia64_pal_retval iprv;
1478         PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1479         return iprv.status;
1480 }
1481
1482 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1483  * suspended, but cause cache and TLB coherency to be maintained.
1484  * This is usually called in IA-32 mode.
1485  */
1486 static inline s64
1487 ia64_pal_shutdown (void)
1488 {
1489         struct ia64_pal_retval iprv;
1490         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1491         return iprv.status;
1492 }
1493
1494 /* Perform the second phase of processor self-test. */
1495 static inline s64
1496 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1497 {
1498         struct ia64_pal_retval iprv;
1499         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1500         if (self_test_state)
1501                 *self_test_state = iprv.v0;
1502         return iprv.status;
1503 }
1504
1505 typedef union  pal_version_u {
1506         u64     pal_version_val;
1507         struct {
1508                 u64     pv_pal_b_rev            :       8;
1509                 u64     pv_pal_b_model          :       8;
1510                 u64     pv_reserved1            :       8;
1511                 u64     pv_pal_vendor           :       8;
1512                 u64     pv_pal_a_rev            :       8;
1513                 u64     pv_pal_a_model          :       8;
1514                 u64     pv_reserved2            :       16;
1515         } pal_version_s;
1516 } pal_version_u_t;
1517
1518
1519 /*
1520  * Return PAL version information.  While the documentation states that
1521  * PAL_VERSION can be called in either physical or virtual mode, some
1522  * implementations only allow physical calls.  We don't call it very often,
1523  * so the overhead isn't worth eliminating.
1524  */
1525 static inline s64
1526 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1527 {
1528         struct ia64_pal_retval iprv;
1529         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1530         if (pal_min_version)
1531                 pal_min_version->pal_version_val = iprv.v0;
1532
1533         if (pal_cur_version)
1534                 pal_cur_version->pal_version_val = iprv.v1;
1535
1536         return iprv.status;
1537 }
1538
1539 typedef union pal_tc_info_u {
1540         u64                     pti_val;
1541         struct {
1542                u64              num_sets        :       8,
1543                                 associativity   :       8,
1544                                 num_entries     :       16,
1545                                 pf              :       1,
1546                                 unified         :       1,
1547                                 reduce_tr       :       1,
1548                                 reserved        :       29;
1549         } pal_tc_info_s;
1550 } pal_tc_info_u_t;
1551
1552 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1553 #define tc_unified              pal_tc_info_s.unified
1554 #define tc_pf                   pal_tc_info_s.pf
1555 #define tc_num_entries          pal_tc_info_s.num_entries
1556 #define tc_associativity        pal_tc_info_s.associativity
1557 #define tc_num_sets             pal_tc_info_s.num_sets
1558
1559
1560 /* Return information about the virtual memory characteristics of the processor
1561  * implementation.
1562  */
1563 static inline s64
1564 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1565 {
1566         struct ia64_pal_retval iprv;
1567         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1568         if (tc_info)
1569                 tc_info->pti_val = iprv.v0;
1570         if (tc_pages)
1571                 *tc_pages = iprv.v1;
1572         return iprv.status;
1573 }
1574
1575 /* Get page size information about the virtual memory characteristics of the processor
1576  * implementation.
1577  */
1578 static inline s64
1579 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1580 {
1581         struct ia64_pal_retval iprv;
1582         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1583         if (tr_pages)
1584                 *tr_pages = iprv.v0;
1585         if (vw_pages)
1586                 *vw_pages = iprv.v1;
1587         return iprv.status;
1588 }
1589
1590 typedef union pal_vm_info_1_u {
1591         u64                     pvi1_val;
1592         struct {
1593                 u64             vw              : 1,
1594                                 phys_add_size   : 7,
1595                                 key_size        : 8,
1596                                 max_pkr         : 8,
1597                                 hash_tag_id     : 8,
1598                                 max_dtr_entry   : 8,
1599                                 max_itr_entry   : 8,
1600                                 max_unique_tcs  : 8,
1601                                 num_tc_levels   : 8;
1602         } pal_vm_info_1_s;
1603 } pal_vm_info_1_u_t;
1604
1605 #define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
1606
1607 typedef union pal_vm_info_2_u {
1608         u64                     pvi2_val;
1609         struct {
1610                 u64             impl_va_msb     : 8,
1611                                 rid_size        : 8,
1612                                 max_purges      : 16,
1613                                 reserved        : 32;
1614         } pal_vm_info_2_s;
1615 } pal_vm_info_2_u_t;
1616
1617 /* Get summary information about the virtual memory characteristics of the processor
1618  * implementation.
1619  */
1620 static inline s64
1621 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1622 {
1623         struct ia64_pal_retval iprv;
1624         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1625         if (vm_info_1)
1626                 vm_info_1->pvi1_val = iprv.v0;
1627         if (vm_info_2)
1628                 vm_info_2->pvi2_val = iprv.v1;
1629         return iprv.status;
1630 }
1631
1632 typedef union pal_itr_valid_u {
1633         u64                     piv_val;
1634         struct {
1635                u64              access_rights_valid     : 1,
1636                                 priv_level_valid        : 1,
1637                                 dirty_bit_valid         : 1,
1638                                 mem_attr_valid          : 1,
1639                                 reserved                : 60;
1640         } pal_tr_valid_s;
1641 } pal_tr_valid_u_t;
1642
1643 /* Read a translation register */
1644 static inline s64
1645 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1646 {
1647         struct ia64_pal_retval iprv;
1648         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1649         if (tr_valid)
1650                 tr_valid->piv_val = iprv.v0;
1651         return iprv.status;
1652 }
1653
1654 /*
1655  * PAL_PREFETCH_VISIBILITY transaction types
1656  */
1657 #define PAL_VISIBILITY_VIRTUAL          0
1658 #define PAL_VISIBILITY_PHYSICAL         1
1659
1660 /*
1661  * PAL_PREFETCH_VISIBILITY return codes
1662  */
1663 #define PAL_VISIBILITY_OK               1
1664 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1665 #define PAL_VISIBILITY_INVAL_ARG        -2
1666 #define PAL_VISIBILITY_ERROR            -3
1667
1668 static inline s64
1669 ia64_pal_prefetch_visibility (s64 trans_type)
1670 {
1671         struct ia64_pal_retval iprv;
1672         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1673         return iprv.status;
1674 }
1675
1676 /* data structure for getting information on logical to physical mappings */
1677 typedef union pal_log_overview_u {
1678         struct {
1679                 u64     num_log         :16,    /* Total number of logical
1680                                                  * processors on this die
1681                                                  */
1682                         tpc             :8,     /* Threads per core */
1683                         reserved3       :8,     /* Reserved */
1684                         cpp             :8,     /* Cores per processor */
1685                         reserved2       :8,     /* Reserved */
1686                         ppid            :8,     /* Physical processor ID */
1687                         reserved1       :8;     /* Reserved */
1688         } overview_bits;
1689         u64 overview_data;
1690 } pal_log_overview_t;
1691
1692 typedef union pal_proc_n_log_info1_u{
1693         struct {
1694                 u64     tid             :16,    /* Thread id */
1695                         reserved2       :16,    /* Reserved */
1696                         cid             :16,    /* Core id */
1697                         reserved1       :16;    /* Reserved */
1698         } ppli1_bits;
1699         u64     ppli1_data;
1700 } pal_proc_n_log_info1_t;
1701
1702 typedef union pal_proc_n_log_info2_u {
1703         struct {
1704                 u64     la              :16,    /* Logical address */
1705                         reserved        :48;    /* Reserved */
1706         } ppli2_bits;
1707         u64     ppli2_data;
1708 } pal_proc_n_log_info2_t;
1709
1710 typedef struct pal_logical_to_physical_s
1711 {
1712         pal_log_overview_t overview;
1713         pal_proc_n_log_info1_t ppli1;
1714         pal_proc_n_log_info2_t ppli2;
1715 } pal_logical_to_physical_t;
1716
1717 #define overview_num_log        overview.overview_bits.num_log
1718 #define overview_tpc            overview.overview_bits.tpc
1719 #define overview_cpp            overview.overview_bits.cpp
1720 #define overview_ppid           overview.overview_bits.ppid
1721 #define log1_tid                ppli1.ppli1_bits.tid
1722 #define log1_cid                ppli1.ppli1_bits.cid
1723 #define log2_la                 ppli2.ppli2_bits.la
1724
1725 /* Get information on logical to physical processor mappings. */
1726 static inline s64
1727 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1728 {
1729         struct ia64_pal_retval iprv;
1730
1731         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1732
1733         if (iprv.status == PAL_STATUS_SUCCESS)
1734         {
1735                 mapping->overview.overview_data = iprv.v0;
1736                 mapping->ppli1.ppli1_data = iprv.v1;
1737                 mapping->ppli2.ppli2_data = iprv.v2;
1738         }
1739
1740         return iprv.status;
1741 }
1742
1743 typedef struct pal_cache_shared_info_s
1744 {
1745         u64 num_shared;
1746         pal_proc_n_log_info1_t ppli1;
1747         pal_proc_n_log_info2_t ppli2;
1748 } pal_cache_shared_info_t;
1749
1750 /* Get information on logical to physical processor mappings. */
1751 static inline s64
1752 ia64_pal_cache_shared_info(u64 level,
1753                 u64 type,
1754                 u64 proc_number,
1755                 pal_cache_shared_info_t *info)
1756 {
1757         struct ia64_pal_retval iprv;
1758
1759         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1760
1761         if (iprv.status == PAL_STATUS_SUCCESS) {
1762                 info->num_shared = iprv.v0;
1763                 info->ppli1.ppli1_data = iprv.v1;
1764                 info->ppli2.ppli2_data = iprv.v2;
1765         }
1766
1767         return iprv.status;
1768 }
1769 #endif /* __ASSEMBLY__ */
1770
1771 #endif /* _ASM_IA64_PAL_H */