1d1de919d6157860e165c0178721d247b7a5a64c
[sfrench/cifs-2.6.git] / drivers / watchdog / pnx4008_wdt.c
1 /*
2  * drivers/char/watchdog/pnx4008_wdt.c
3  *
4  * Watchdog driver for PNX4008 board
5  *
6  * Authors: Dmitry Chigirev <source@mvista.com>,
7  *          Vitaly Wool <vitalywool@gmail.com>
8  * Based on sa1100 driver,
9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
10  *
11  * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
12  * the terms of the GNU General Public License version 2. This program
13  * is licensed "as is" without any warranty of any kind, whether express
14  * or implied.
15  */
16
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/fs.h>
22 #include <linux/miscdevice.h>
23 #include <linux/watchdog.h>
24 #include <linux/init.h>
25 #include <linux/bitops.h>
26 #include <linux/ioport.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/spinlock.h>
31 #include <linux/uaccess.h>
32 #include <linux/io.h>
33 #include <linux/slab.h>
34 #include <mach/hardware.h>
35
36 #define MODULE_NAME "PNX4008-WDT: "
37
38 /* WatchDog Timer - Chapter 23 Page 207 */
39
40 #define DEFAULT_HEARTBEAT 19
41 #define MAX_HEARTBEAT     60
42
43 /* Watchdog timer register set definition */
44 #define WDTIM_INT(p)     ((p) + 0x0)
45 #define WDTIM_CTRL(p)    ((p) + 0x4)
46 #define WDTIM_COUNTER(p) ((p) + 0x8)
47 #define WDTIM_MCTRL(p)   ((p) + 0xC)
48 #define WDTIM_MATCH0(p)  ((p) + 0x10)
49 #define WDTIM_EMR(p)     ((p) + 0x14)
50 #define WDTIM_PULSE(p)   ((p) + 0x18)
51 #define WDTIM_RES(p)     ((p) + 0x1C)
52
53 /* WDTIM_INT bit definitions */
54 #define MATCH_INT      1
55
56 /* WDTIM_CTRL bit definitions */
57 #define COUNT_ENAB     1
58 #define RESET_COUNT    (1 << 1)
59 #define DEBUG_EN       (1 << 2)
60
61 /* WDTIM_MCTRL bit definitions */
62 #define MR0_INT        1
63 #undef  RESET_COUNT0
64 #define RESET_COUNT0   (1 << 2)
65 #define STOP_COUNT0    (1 << 2)
66 #define M_RES1         (1 << 3)
67 #define M_RES2         (1 << 4)
68 #define RESFRC1        (1 << 5)
69 #define RESFRC2        (1 << 6)
70
71 /* WDTIM_EMR bit definitions */
72 #define EXT_MATCH0      1
73 #define MATCH_OUTPUT_HIGH (2 << 4)      /*a MATCH_CTRL setting */
74
75 /* WDTIM_RES bit definitions */
76 #define WDOG_RESET      1       /* read only */
77
78 #define WDOG_COUNTER_RATE 13000000      /*the counter clock is 13 MHz fixed */
79
80 static int nowayout = WATCHDOG_NOWAYOUT;
81 static int heartbeat = DEFAULT_HEARTBEAT;
82
83 static DEFINE_SPINLOCK(io_lock);
84 static unsigned long wdt_status;
85 #define WDT_IN_USE        0
86 #define WDT_OK_TO_CLOSE   1
87
88 static unsigned long boot_status;
89
90 static void __iomem     *wdt_base;
91 struct clk              *wdt_clk;
92
93 static void wdt_enable(void)
94 {
95         spin_lock(&io_lock);
96
97         /* stop counter, initiate counter reset */
98         writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
99         /*wait for reset to complete. 100% guarantee event */
100         while (readl(WDTIM_COUNTER(wdt_base)))
101                 cpu_relax();
102         /* internal and external reset, stop after that */
103         writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
104         /* configure match output */
105         writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
106         /* clear interrupt, just in case */
107         writel(MATCH_INT, WDTIM_INT(wdt_base));
108         /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
109         writel(0xFFFF, WDTIM_PULSE(wdt_base));
110         writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
111         /*enable counter, stop when debugger active */
112         writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
113
114         spin_unlock(&io_lock);
115 }
116
117 static void wdt_disable(void)
118 {
119         spin_lock(&io_lock);
120
121         writel(0, WDTIM_CTRL(wdt_base));        /*stop counter */
122
123         spin_unlock(&io_lock);
124 }
125
126 static int pnx4008_wdt_open(struct inode *inode, struct file *file)
127 {
128         int ret;
129
130         if (test_and_set_bit(WDT_IN_USE, &wdt_status))
131                 return -EBUSY;
132
133         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
134
135         ret = clk_enable(wdt_clk);
136         if (ret) {
137                 clear_bit(WDT_IN_USE, &wdt_status);
138                 return ret;
139         }
140
141         wdt_enable();
142
143         return nonseekable_open(inode, file);
144 }
145
146 static ssize_t pnx4008_wdt_write(struct file *file, const char *data,
147                                         size_t len, loff_t *ppos)
148 {
149         if (len) {
150                 if (!nowayout) {
151                         size_t i;
152
153                         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
154
155                         for (i = 0; i != len; i++) {
156                                 char c;
157
158                                 if (get_user(c, data + i))
159                                         return -EFAULT;
160                                 if (c == 'V')
161                                         set_bit(WDT_OK_TO_CLOSE, &wdt_status);
162                         }
163                 }
164                 wdt_enable();
165         }
166
167         return len;
168 }
169
170 static const struct watchdog_info ident = {
171         .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
172             WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
173         .identity = "PNX4008 Watchdog",
174 };
175
176 static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
177                                 unsigned long arg)
178 {
179         int ret = -ENOTTY;
180         int time;
181
182         switch (cmd) {
183         case WDIOC_GETSUPPORT:
184                 ret = copy_to_user((struct watchdog_info *)arg, &ident,
185                                    sizeof(ident)) ? -EFAULT : 0;
186                 break;
187
188         case WDIOC_GETSTATUS:
189                 ret = put_user(0, (int *)arg);
190                 break;
191
192         case WDIOC_GETBOOTSTATUS:
193                 ret = put_user(boot_status, (int *)arg);
194                 break;
195
196         case WDIOC_KEEPALIVE:
197                 wdt_enable();
198                 ret = 0;
199                 break;
200
201         case WDIOC_SETTIMEOUT:
202                 ret = get_user(time, (int *)arg);
203                 if (ret)
204                         break;
205
206                 if (time <= 0 || time > MAX_HEARTBEAT) {
207                         ret = -EINVAL;
208                         break;
209                 }
210
211                 heartbeat = time;
212                 wdt_enable();
213                 /* Fall through */
214
215         case WDIOC_GETTIMEOUT:
216                 ret = put_user(heartbeat, (int *)arg);
217                 break;
218         }
219         return ret;
220 }
221
222 static int pnx4008_wdt_release(struct inode *inode, struct file *file)
223 {
224         if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
225                 printk(KERN_WARNING "WATCHDOG: Device closed unexpectedly\n");
226
227         wdt_disable();
228         clk_disable(wdt_clk);
229         clear_bit(WDT_IN_USE, &wdt_status);
230         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
231
232         return 0;
233 }
234
235 static const struct file_operations pnx4008_wdt_fops = {
236         .owner = THIS_MODULE,
237         .llseek = no_llseek,
238         .write = pnx4008_wdt_write,
239         .unlocked_ioctl = pnx4008_wdt_ioctl,
240         .open = pnx4008_wdt_open,
241         .release = pnx4008_wdt_release,
242 };
243
244 static struct miscdevice pnx4008_wdt_miscdev = {
245         .minor = WATCHDOG_MINOR,
246         .name = "watchdog",
247         .fops = &pnx4008_wdt_fops,
248 };
249
250 static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
251 {
252         struct resource *r;
253         int ret = 0;
254
255         if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
256                 heartbeat = DEFAULT_HEARTBEAT;
257
258         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259         wdt_base = devm_request_and_ioremap(&pdev->dev, r);
260         if (!wdt_base)
261                 return -EADDRINUSE;
262
263         wdt_clk = clk_get(&pdev->dev, NULL);
264         if (IS_ERR(wdt_clk))
265                 return PTR_ERR(wdt_clk);
266
267         ret = clk_enable(wdt_clk);
268         if (ret)
269                 goto out;
270
271         boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
272                         WDIOF_CARDRESET : 0;
273         wdt_disable();          /*disable for now */
274         clk_disable(wdt_clk);
275
276         ret = misc_register(&pnx4008_wdt_miscdev);
277         if (ret < 0) {
278                 dev_err(&pdev->dev, "cannot register misc device\n");
279                 goto out;
280         }
281
282         dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
283                         heartbeat);
284
285         return 0;
286
287 out:
288         clk_put(wdt_clk);
289         return ret;
290 }
291
292 static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
293 {
294         misc_deregister(&pnx4008_wdt_miscdev);
295
296         clk_disable(wdt_clk);
297         clk_put(wdt_clk);
298
299         return 0;
300 }
301
302 static struct platform_driver platform_wdt_driver = {
303         .driver = {
304                 .name = "pnx4008-watchdog",
305                 .owner  = THIS_MODULE,
306         },
307         .probe = pnx4008_wdt_probe,
308         .remove = __devexit_p(pnx4008_wdt_remove),
309 };
310
311 module_platform_driver(platform_wdt_driver);
312
313 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
314 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
315
316 module_param(heartbeat, int, 0);
317 MODULE_PARM_DESC(heartbeat,
318                  "Watchdog heartbeat period in seconds from 1 to "
319                  __MODULE_STRING(MAX_HEARTBEAT) ", default "
320                  __MODULE_STRING(DEFAULT_HEARTBEAT));
321
322 module_param(nowayout, int, 0);
323 MODULE_PARM_DESC(nowayout,
324                  "Set to 1 to keep watchdog running after device release");
325
326 MODULE_LICENSE("GPL");
327 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
328 MODULE_ALIAS("platform:pnx4008-watchdog");