Merge master.kernel.org:/home/rmk/linux-2.6-arm
[sfrench/cifs-2.6.git] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  */
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
33 #include <linux/fb.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40
41 #include <asm/hardware.h>
42 #include <asm/io.h>
43 #include <asm/irq.h>
44 #include <asm/uaccess.h>
45 #include <asm/div64.h>
46 #include <asm/arch/pxa-regs.h>
47 #include <asm/arch/bitfield.h>
48 #include <asm/arch/pxafb.h>
49
50 /*
51  * Complain if VAR is out of range.
52  */
53 #define DEBUG_VAR 1
54
55 #include "pxafb.h"
56
57 /* Bits which should not be set in machine configuration structures */
58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
60
61 static void (*pxafb_backlight_power)(int);
62 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
63
64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
66
67 #ifdef CONFIG_FB_PXA_PARAMETERS
68 #define PXAFB_OPTIONS_SIZE 256
69 static char g_options[PXAFB_OPTIONS_SIZE] __devinitdata = "";
70 #endif
71
72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
73 {
74         unsigned long flags;
75
76         local_irq_save(flags);
77         /*
78          * We need to handle two requests being made at the same time.
79          * There are two important cases:
80          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
81          *     We must perform the unblanking, which will do our REENABLE for us.
82          *  2. When we are blanking, but immediately unblank before we have
83          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
84          */
85         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
86                 state = (u_int) -1;
87         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
88                 state = C_REENABLE;
89
90         if (state != (u_int)-1) {
91                 fbi->task_state = state;
92                 schedule_work(&fbi->task);
93         }
94         local_irq_restore(flags);
95 }
96
97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
98 {
99         chan &= 0xffff;
100         chan >>= 16 - bf->length;
101         return chan << bf->offset;
102 }
103
104 static int
105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
106                        u_int trans, struct fb_info *info)
107 {
108         struct pxafb_info *fbi = (struct pxafb_info *)info;
109         u_int val, ret = 1;
110
111         if (regno < fbi->palette_size) {
112                 if (fbi->fb.var.grayscale) {
113                         val = ((blue >> 8) & 0x00ff);
114                 } else {
115                         val  = ((red   >>  0) & 0xf800);
116                         val |= ((green >>  5) & 0x07e0);
117                         val |= ((blue  >> 11) & 0x001f);
118                 }
119                 fbi->palette_cpu[regno] = val;
120                 ret = 0;
121         }
122         return ret;
123 }
124
125 static int
126 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
127                    u_int trans, struct fb_info *info)
128 {
129         struct pxafb_info *fbi = (struct pxafb_info *)info;
130         unsigned int val;
131         int ret = 1;
132
133         /*
134          * If inverse mode was selected, invert all the colours
135          * rather than the register number.  The register number
136          * is what you poke into the framebuffer to produce the
137          * colour you requested.
138          */
139         if (fbi->cmap_inverse) {
140                 red   = 0xffff - red;
141                 green = 0xffff - green;
142                 blue  = 0xffff - blue;
143         }
144
145         /*
146          * If greyscale is true, then we convert the RGB value
147          * to greyscale no matter what visual we are using.
148          */
149         if (fbi->fb.var.grayscale)
150                 red = green = blue = (19595 * red + 38470 * green +
151                                         7471 * blue) >> 16;
152
153         switch (fbi->fb.fix.visual) {
154         case FB_VISUAL_TRUECOLOR:
155                 /*
156                  * 16-bit True Colour.  We encode the RGB value
157                  * according to the RGB bitfield information.
158                  */
159                 if (regno < 16) {
160                         u32 *pal = fbi->fb.pseudo_palette;
161
162                         val  = chan_to_field(red, &fbi->fb.var.red);
163                         val |= chan_to_field(green, &fbi->fb.var.green);
164                         val |= chan_to_field(blue, &fbi->fb.var.blue);
165
166                         pal[regno] = val;
167                         ret = 0;
168                 }
169                 break;
170
171         case FB_VISUAL_STATIC_PSEUDOCOLOR:
172         case FB_VISUAL_PSEUDOCOLOR:
173                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
174                 break;
175         }
176
177         return ret;
178 }
179
180 /*
181  *  pxafb_bpp_to_lccr3():
182  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
183  */
184 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
185 {
186         int ret = 0;
187         switch (var->bits_per_pixel) {
188         case 1:  ret = LCCR3_1BPP; break;
189         case 2:  ret = LCCR3_2BPP; break;
190         case 4:  ret = LCCR3_4BPP; break;
191         case 8:  ret = LCCR3_8BPP; break;
192         case 16: ret = LCCR3_16BPP; break;
193         }
194         return ret;
195 }
196
197 #ifdef CONFIG_CPU_FREQ
198 /*
199  *  pxafb_display_dma_period()
200  *    Calculate the minimum period (in picoseconds) between two DMA
201  *    requests for the LCD controller.  If we hit this, it means we're
202  *    doing nothing but LCD DMA.
203  */
204 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
205 {
206        /*
207         * Period = pixclock * bits_per_byte * bytes_per_transfer
208         *              / memory_bits_per_pixel;
209         */
210        return var->pixclock * 8 * 16 / var->bits_per_pixel;
211 }
212
213 extern unsigned int get_clk_frequency_khz(int info);
214 #endif
215
216 /*
217  * Select the smallest mode that allows the desired resolution to be
218  * displayed. If desired parameters can be rounded up.
219  */
220 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, struct fb_var_screeninfo *var)
221 {
222         struct pxafb_mode_info *mode = NULL;
223         struct pxafb_mode_info *modelist = mach->modes;
224         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
225         unsigned int i;
226
227         for (i = 0 ; i < mach->num_modes ; i++) {
228                 if (modelist[i].xres >= var->xres && modelist[i].yres >= var->yres &&
229                                 modelist[i].xres < best_x && modelist[i].yres < best_y &&
230                                 modelist[i].bpp >= var->bits_per_pixel ) {
231                         best_x = modelist[i].xres;
232                         best_y = modelist[i].yres;
233                         mode = &modelist[i];
234                 }
235         }
236
237         return mode;
238 }
239
240 static void pxafb_setmode(struct fb_var_screeninfo *var, struct pxafb_mode_info *mode)
241 {
242         var->xres               = mode->xres;
243         var->yres               = mode->yres;
244         var->bits_per_pixel     = mode->bpp;
245         var->pixclock           = mode->pixclock;
246         var->hsync_len          = mode->hsync_len;
247         var->left_margin        = mode->left_margin;
248         var->right_margin       = mode->right_margin;
249         var->vsync_len          = mode->vsync_len;
250         var->upper_margin       = mode->upper_margin;
251         var->lower_margin       = mode->lower_margin;
252         var->sync               = mode->sync;
253         var->grayscale          = mode->cmap_greyscale;
254         var->xres_virtual       = var->xres;
255         var->yres_virtual       = var->yres;
256 }
257
258 /*
259  *  pxafb_check_var():
260  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
261  *    if it's too big, return -EINVAL.
262  *
263  *    Round up in the following order: bits_per_pixel, xres,
264  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
265  *    bitfields, horizontal timing, vertical timing.
266  */
267 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
268 {
269         struct pxafb_info *fbi = (struct pxafb_info *)info;
270         struct pxafb_mach_info *inf = fbi->dev->platform_data;
271
272         if (var->xres < MIN_XRES)
273                 var->xres = MIN_XRES;
274         if (var->yres < MIN_YRES)
275                 var->yres = MIN_YRES;
276
277         if (inf->fixed_modes) {
278                 struct pxafb_mode_info *mode;
279
280                 mode = pxafb_getmode(inf, var);
281                 if (!mode)
282                         return -EINVAL;
283                 pxafb_setmode(var, mode);
284         } else {
285                 if (var->xres > inf->modes->xres)
286                         return -EINVAL;
287                 if (var->yres > inf->modes->yres)
288                         return -EINVAL;
289                 if (var->bits_per_pixel > inf->modes->bpp)
290                         return -EINVAL;
291         }
292
293         var->xres_virtual =
294                 max(var->xres_virtual, var->xres);
295         var->yres_virtual =
296                 max(var->yres_virtual, var->yres);
297
298         /*
299          * Setup the RGB parameters for this display.
300          *
301          * The pixel packing format is described on page 7-11 of the
302          * PXA2XX Developer's Manual.
303          */
304         if (var->bits_per_pixel == 16) {
305                 var->red.offset   = 11; var->red.length   = 5;
306                 var->green.offset = 5;  var->green.length = 6;
307                 var->blue.offset  = 0;  var->blue.length  = 5;
308                 var->transp.offset = var->transp.length = 0;
309         } else {
310                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
311                 var->red.length   = 8;
312                 var->green.length = 8;
313                 var->blue.length  = 8;
314                 var->transp.length = 0;
315         }
316
317 #ifdef CONFIG_CPU_FREQ
318         pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
319                  pxafb_display_dma_period(var),
320                  get_clk_frequency_khz(0));
321 #endif
322
323         return 0;
324 }
325
326 static inline void pxafb_set_truecolor(u_int is_true_color)
327 {
328         pr_debug("pxafb: true_color = %d\n", is_true_color);
329         // do your machine-specific setup if needed
330 }
331
332 /*
333  * pxafb_set_par():
334  *      Set the user defined part of the display for the specified console
335  */
336 static int pxafb_set_par(struct fb_info *info)
337 {
338         struct pxafb_info *fbi = (struct pxafb_info *)info;
339         struct fb_var_screeninfo *var = &info->var;
340         unsigned long palette_mem_size;
341
342         pr_debug("pxafb: set_par\n");
343
344         if (var->bits_per_pixel == 16)
345                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
346         else if (!fbi->cmap_static)
347                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
348         else {
349                 /*
350                  * Some people have weird ideas about wanting static
351                  * pseudocolor maps.  I suspect their user space
352                  * applications are broken.
353                  */
354                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
355         }
356
357         fbi->fb.fix.line_length = var->xres_virtual *
358                                   var->bits_per_pixel / 8;
359         if (var->bits_per_pixel == 16)
360                 fbi->palette_size = 0;
361         else
362                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
363
364         palette_mem_size = fbi->palette_size * sizeof(u16);
365
366         pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
367
368         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
369         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
370
371         /*
372          * Set (any) board control register to handle new color depth
373          */
374         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
375
376         if (fbi->fb.var.bits_per_pixel == 16)
377                 fb_dealloc_cmap(&fbi->fb.cmap);
378         else
379                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
380
381         pxafb_activate_var(var, fbi);
382
383         return 0;
384 }
385
386 /*
387  * Formal definition of the VESA spec:
388  *  On
389  *      This refers to the state of the display when it is in full operation
390  *  Stand-By
391  *      This defines an optional operating state of minimal power reduction with
392  *      the shortest recovery time
393  *  Suspend
394  *      This refers to a level of power management in which substantial power
395  *      reduction is achieved by the display.  The display can have a longer
396  *      recovery time from this state than from the Stand-by state
397  *  Off
398  *      This indicates that the display is consuming the lowest level of power
399  *      and is non-operational. Recovery from this state may optionally require
400  *      the user to manually power on the monitor
401  *
402  *  Now, the fbdev driver adds an additional state, (blank), where they
403  *  turn off the video (maybe by colormap tricks), but don't mess with the
404  *  video itself: think of it semantically between on and Stand-By.
405  *
406  *  So here's what we should do in our fbdev blank routine:
407  *
408  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
409  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
410  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
411  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
412  *
413  *  This will match the matrox implementation.
414  */
415
416 /*
417  * pxafb_blank():
418  *      Blank the display by setting all palette values to zero.  Note, the
419  *      16 bpp mode does not really use the palette, so this will not
420  *      blank the display in all modes.
421  */
422 static int pxafb_blank(int blank, struct fb_info *info)
423 {
424         struct pxafb_info *fbi = (struct pxafb_info *)info;
425         int i;
426
427         pr_debug("pxafb: blank=%d\n", blank);
428
429         switch (blank) {
430         case FB_BLANK_POWERDOWN:
431         case FB_BLANK_VSYNC_SUSPEND:
432         case FB_BLANK_HSYNC_SUSPEND:
433         case FB_BLANK_NORMAL:
434                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
435                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
436                         for (i = 0; i < fbi->palette_size; i++)
437                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
438
439                 pxafb_schedule_work(fbi, C_DISABLE);
440                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
441                 break;
442
443         case FB_BLANK_UNBLANK:
444                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
445                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
446                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
447                         fb_set_cmap(&fbi->fb.cmap, info);
448                 pxafb_schedule_work(fbi, C_ENABLE);
449         }
450         return 0;
451 }
452
453 static int pxafb_mmap(struct fb_info *info,
454                       struct vm_area_struct *vma)
455 {
456         struct pxafb_info *fbi = (struct pxafb_info *)info;
457         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
458
459         if (off < info->fix.smem_len) {
460                 vma->vm_pgoff += 1;
461                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
462                                              fbi->map_dma, fbi->map_size);
463         }
464         return -EINVAL;
465 }
466
467 static struct fb_ops pxafb_ops = {
468         .owner          = THIS_MODULE,
469         .fb_check_var   = pxafb_check_var,
470         .fb_set_par     = pxafb_set_par,
471         .fb_setcolreg   = pxafb_setcolreg,
472         .fb_fillrect    = cfb_fillrect,
473         .fb_copyarea    = cfb_copyarea,
474         .fb_imageblit   = cfb_imageblit,
475         .fb_blank       = pxafb_blank,
476         .fb_mmap        = pxafb_mmap,
477 };
478
479 /*
480  * Calculate the PCD value from the clock rate (in picoseconds).
481  * We take account of the PPCR clock setting.
482  * From PXA Developer's Manual:
483  *
484  *   PixelClock =      LCLK
485  *                -------------
486  *                2 ( PCD + 1 )
487  *
488  *   PCD =      LCLK
489  *         ------------- - 1
490  *         2(PixelClock)
491  *
492  * Where:
493  *   LCLK = LCD/Memory Clock
494  *   PCD = LCCR3[7:0]
495  *
496  * PixelClock here is in Hz while the pixclock argument given is the
497  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
498  *
499  * The function get_lclk_frequency_10khz returns LCLK in units of
500  * 10khz. Calling the result of this function lclk gives us the
501  * following
502  *
503  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
504  *          -------------------------------------- - 1
505  *                          2
506  *
507  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
508  */
509 static inline unsigned int get_pcd(unsigned int pixclock)
510 {
511         unsigned long long pcd;
512
513         /* FIXME: Need to take into account Double Pixel Clock mode
514          * (DPC) bit? or perhaps set it based on the various clock
515          * speeds */
516
517         pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
518         do_div(pcd, 100000000 * 2);
519         /* no need for this, since we should subtract 1 anyway. they cancel */
520         /* pcd += 1; */ /* make up for integer math truncations */
521         return (unsigned int)pcd;
522 }
523
524 /*
525  * Some touchscreens need hsync information from the video driver to
526  * function correctly. We export it here.
527  */
528 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
529 {
530         unsigned long long htime;
531
532         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
533                 fbi->hsync_time=0;
534                 return;
535         }
536
537         htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
538         do_div(htime, pcd * fbi->fb.var.hsync_len);
539         fbi->hsync_time = htime;
540 }
541
542 unsigned long pxafb_get_hsync_time(struct device *dev)
543 {
544         struct pxafb_info *fbi = dev_get_drvdata(dev);
545
546         /* If display is blanked/suspended, hsync isn't active */
547         if (!fbi || (fbi->state != C_ENABLE))
548                 return 0;
549
550         return fbi->hsync_time;
551 }
552 EXPORT_SYMBOL(pxafb_get_hsync_time);
553
554 /*
555  * pxafb_activate_var():
556  *      Configures LCD Controller based on entries in var parameter.  Settings are
557  *      only written to the controller if changes were made.
558  */
559 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
560 {
561         struct pxafb_lcd_reg new_regs;
562         u_long flags;
563         u_int lines_per_panel, pcd = get_pcd(var->pixclock);
564
565         pr_debug("pxafb: Configuring PXA LCD\n");
566
567         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
568                  var->xres, var->hsync_len,
569                  var->left_margin, var->right_margin);
570         pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
571                  var->yres, var->vsync_len,
572                  var->upper_margin, var->lower_margin);
573         pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
574
575 #if DEBUG_VAR
576         if (var->xres < 16        || var->xres > 1024)
577                 printk(KERN_ERR "%s: invalid xres %d\n",
578                         fbi->fb.fix.id, var->xres);
579         switch(var->bits_per_pixel) {
580         case 1:
581         case 2:
582         case 4:
583         case 8:
584         case 16:
585                 break;
586         default:
587                 printk(KERN_ERR "%s: invalid bit depth %d\n",
588                        fbi->fb.fix.id, var->bits_per_pixel);
589                 break;
590         }
591         if (var->hsync_len < 1    || var->hsync_len > 64)
592                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
593                         fbi->fb.fix.id, var->hsync_len);
594         if (var->left_margin < 1  || var->left_margin > 255)
595                 printk(KERN_ERR "%s: invalid left_margin %d\n",
596                         fbi->fb.fix.id, var->left_margin);
597         if (var->right_margin < 1 || var->right_margin > 255)
598                 printk(KERN_ERR "%s: invalid right_margin %d\n",
599                         fbi->fb.fix.id, var->right_margin);
600         if (var->yres < 1         || var->yres > 1024)
601                 printk(KERN_ERR "%s: invalid yres %d\n",
602                         fbi->fb.fix.id, var->yres);
603         if (var->vsync_len < 1    || var->vsync_len > 64)
604                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
605                         fbi->fb.fix.id, var->vsync_len);
606         if (var->upper_margin < 0 || var->upper_margin > 255)
607                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
608                         fbi->fb.fix.id, var->upper_margin);
609         if (var->lower_margin < 0 || var->lower_margin > 255)
610                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
611                         fbi->fb.fix.id, var->lower_margin);
612 #endif
613
614         new_regs.lccr0 = fbi->lccr0 |
615                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
616                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
617
618         new_regs.lccr1 =
619                 LCCR1_DisWdth(var->xres) +
620                 LCCR1_HorSnchWdth(var->hsync_len) +
621                 LCCR1_BegLnDel(var->left_margin) +
622                 LCCR1_EndLnDel(var->right_margin);
623
624         /*
625          * If we have a dual scan LCD, we need to halve
626          * the YRES parameter.
627          */
628         lines_per_panel = var->yres;
629         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
630                 lines_per_panel /= 2;
631
632         new_regs.lccr2 =
633                 LCCR2_DisHght(lines_per_panel) +
634                 LCCR2_VrtSnchWdth(var->vsync_len) +
635                 LCCR2_BegFrmDel(var->upper_margin) +
636                 LCCR2_EndFrmDel(var->lower_margin);
637
638         new_regs.lccr3 = fbi->lccr3 |
639                 pxafb_bpp_to_lccr3(var) |
640                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
641                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
642
643         if (pcd)
644                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
645
646         pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
647         pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
648         pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
649         pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
650
651         /* Update shadow copy atomically */
652         local_irq_save(flags);
653
654         /* setup dma descriptors */
655         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
656         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
657         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
658
659         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
660         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
661         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
662
663 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
664
665         /* populate descriptors */
666         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
667         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
668         fbi->dmadesc_fblow_cpu->fidr  = 0;
669         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
670
671         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
672
673         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
674         fbi->dmadesc_fbhigh_cpu->fidr = 0;
675         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
676
677         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
678         fbi->dmadesc_palette_cpu->fidr  = 0;
679         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
680
681         if (var->bits_per_pixel == 16) {
682                 /* palette shouldn't be loaded in true-color mode */
683                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
684                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
685                 /* init it to something, even though we won't be using it */
686                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
687         } else {
688                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
689                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
690                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
691         }
692
693 #if 0
694         pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
695         pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
696         pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
697         pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
698         pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
699         pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
700
701         pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
702         pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
703         pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
704
705         pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
706         pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
707         pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
708
709         pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
710         pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
711         pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
712 #endif
713
714         fbi->reg_lccr0 = new_regs.lccr0;
715         fbi->reg_lccr1 = new_regs.lccr1;
716         fbi->reg_lccr2 = new_regs.lccr2;
717         fbi->reg_lccr3 = new_regs.lccr3;
718         set_hsync_time(fbi, pcd);
719         local_irq_restore(flags);
720
721         /*
722          * Only update the registers if the controller is enabled
723          * and something has changed.
724          */
725         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
726             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
727             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
728                 pxafb_schedule_work(fbi, C_REENABLE);
729
730         return 0;
731 }
732
733 /*
734  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
735  * Do not call them directly; set_ctrlr_state does the correct serialisation
736  * to ensure that things happen in the right way 100% of time time.
737  *      -- rmk
738  */
739 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
740 {
741         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
742
743         if (pxafb_backlight_power)
744                 pxafb_backlight_power(on);
745 }
746
747 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
748 {
749         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
750
751         if (pxafb_lcd_power)
752                 pxafb_lcd_power(on, &fbi->fb.var);
753 }
754
755 static void pxafb_setup_gpio(struct pxafb_info *fbi)
756 {
757         int gpio, ldd_bits;
758         unsigned int lccr0 = fbi->lccr0;
759
760         /*
761          * setup is based on type of panel supported
762         */
763
764         /* 4 bit interface */
765         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
766             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
767             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
768                 ldd_bits = 4;
769
770         /* 8 bit interface */
771         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
772                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
773                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
774                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
775                 ldd_bits = 8;
776
777         /* 16 bit interface */
778         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
779                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
780                 ldd_bits = 16;
781
782         else {
783                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
784                 return;
785         }
786
787         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
788                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
789         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
790         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
791         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
792         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
793 }
794
795 static void pxafb_enable_controller(struct pxafb_info *fbi)
796 {
797         pr_debug("pxafb: Enabling LCD controller\n");
798         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
799         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
800         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
801         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
802         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
803         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
804
805         /* enable LCD controller clock */
806         pxa_set_cken(CKEN_LCD, 1);
807
808         /* Sequence from 11.7.10 */
809         LCCR3 = fbi->reg_lccr3;
810         LCCR2 = fbi->reg_lccr2;
811         LCCR1 = fbi->reg_lccr1;
812         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
813
814         FDADR0 = fbi->fdadr0;
815         FDADR1 = fbi->fdadr1;
816         LCCR0 |= LCCR0_ENB;
817
818         pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
819         pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
820         pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
821         pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
822         pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
823         pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
824 }
825
826 static void pxafb_disable_controller(struct pxafb_info *fbi)
827 {
828         DECLARE_WAITQUEUE(wait, current);
829
830         pr_debug("pxafb: disabling LCD controller\n");
831
832         set_current_state(TASK_UNINTERRUPTIBLE);
833         add_wait_queue(&fbi->ctrlr_wait, &wait);
834
835         LCSR = 0xffffffff;      /* Clear LCD Status Register */
836         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
837         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
838
839         schedule_timeout(200 * HZ / 1000);
840         remove_wait_queue(&fbi->ctrlr_wait, &wait);
841
842         /* disable LCD controller clock */
843         pxa_set_cken(CKEN_LCD, 0);
844 }
845
846 /*
847  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
848  */
849 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
850 {
851         struct pxafb_info *fbi = dev_id;
852         unsigned int lcsr = LCSR;
853
854         if (lcsr & LCSR_LDD) {
855                 LCCR0 |= LCCR0_LDM;
856                 wake_up(&fbi->ctrlr_wait);
857         }
858
859         LCSR = lcsr;
860         return IRQ_HANDLED;
861 }
862
863 /*
864  * This function must be called from task context only, since it will
865  * sleep when disabling the LCD controller, or if we get two contending
866  * processes trying to alter state.
867  */
868 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
869 {
870         u_int old_state;
871
872         down(&fbi->ctrlr_sem);
873
874         old_state = fbi->state;
875
876         /*
877          * Hack around fbcon initialisation.
878          */
879         if (old_state == C_STARTUP && state == C_REENABLE)
880                 state = C_ENABLE;
881
882         switch (state) {
883         case C_DISABLE_CLKCHANGE:
884                 /*
885                  * Disable controller for clock change.  If the
886                  * controller is already disabled, then do nothing.
887                  */
888                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
889                         fbi->state = state;
890                         //TODO __pxafb_lcd_power(fbi, 0);
891                         pxafb_disable_controller(fbi);
892                 }
893                 break;
894
895         case C_DISABLE_PM:
896         case C_DISABLE:
897                 /*
898                  * Disable controller
899                  */
900                 if (old_state != C_DISABLE) {
901                         fbi->state = state;
902                         __pxafb_backlight_power(fbi, 0);
903                         __pxafb_lcd_power(fbi, 0);
904                         if (old_state != C_DISABLE_CLKCHANGE)
905                                 pxafb_disable_controller(fbi);
906                 }
907                 break;
908
909         case C_ENABLE_CLKCHANGE:
910                 /*
911                  * Enable the controller after clock change.  Only
912                  * do this if we were disabled for the clock change.
913                  */
914                 if (old_state == C_DISABLE_CLKCHANGE) {
915                         fbi->state = C_ENABLE;
916                         pxafb_enable_controller(fbi);
917                         //TODO __pxafb_lcd_power(fbi, 1);
918                 }
919                 break;
920
921         case C_REENABLE:
922                 /*
923                  * Re-enable the controller only if it was already
924                  * enabled.  This is so we reprogram the control
925                  * registers.
926                  */
927                 if (old_state == C_ENABLE) {
928                         __pxafb_lcd_power(fbi, 0);
929                         pxafb_disable_controller(fbi);
930                         pxafb_setup_gpio(fbi);
931                         pxafb_enable_controller(fbi);
932                         __pxafb_lcd_power(fbi, 1);
933                 }
934                 break;
935
936         case C_ENABLE_PM:
937                 /*
938                  * Re-enable the controller after PM.  This is not
939                  * perfect - think about the case where we were doing
940                  * a clock change, and we suspended half-way through.
941                  */
942                 if (old_state != C_DISABLE_PM)
943                         break;
944                 /* fall through */
945
946         case C_ENABLE:
947                 /*
948                  * Power up the LCD screen, enable controller, and
949                  * turn on the backlight.
950                  */
951                 if (old_state != C_ENABLE) {
952                         fbi->state = C_ENABLE;
953                         pxafb_setup_gpio(fbi);
954                         pxafb_enable_controller(fbi);
955                         __pxafb_lcd_power(fbi, 1);
956                         __pxafb_backlight_power(fbi, 1);
957                 }
958                 break;
959         }
960         up(&fbi->ctrlr_sem);
961 }
962
963 /*
964  * Our LCD controller task (which is called when we blank or unblank)
965  * via keventd.
966  */
967 static void pxafb_task(struct work_struct *work)
968 {
969         struct pxafb_info *fbi =
970                 container_of(work, struct pxafb_info, task);
971         u_int state = xchg(&fbi->task_state, -1);
972
973         set_ctrlr_state(fbi, state);
974 }
975
976 #ifdef CONFIG_CPU_FREQ
977 /*
978  * CPU clock speed change handler.  We need to adjust the LCD timing
979  * parameters when the CPU clock is adjusted by the power management
980  * subsystem.
981  *
982  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
983  */
984 static int
985 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
986 {
987         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
988         //TODO struct cpufreq_freqs *f = data;
989         u_int pcd;
990
991         switch (val) {
992         case CPUFREQ_PRECHANGE:
993                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
994                 break;
995
996         case CPUFREQ_POSTCHANGE:
997                 pcd = get_pcd(fbi->fb.var.pixclock);
998                 set_hsync_time(fbi, pcd);
999                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1000                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1001                 break;
1002         }
1003         return 0;
1004 }
1005
1006 static int
1007 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1008 {
1009         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1010         struct fb_var_screeninfo *var = &fbi->fb.var;
1011         struct cpufreq_policy *policy = data;
1012
1013         switch (val) {
1014         case CPUFREQ_ADJUST:
1015         case CPUFREQ_INCOMPATIBLE:
1016                 printk(KERN_DEBUG "min dma period: %d ps, "
1017                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1018                         policy->max);
1019                 // TODO: fill in min/max values
1020                 break;
1021 #if 0
1022         case CPUFREQ_NOTIFY:
1023                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
1024                 do {} while(0);
1025                 /* todo: panic if min/max values aren't fulfilled
1026                  * [can't really happen unless there's a bug in the
1027                  * CPU policy verification process *
1028                  */
1029                 break;
1030 #endif
1031         }
1032         return 0;
1033 }
1034 #endif
1035
1036 #ifdef CONFIG_PM
1037 /*
1038  * Power management hooks.  Note that we won't be called from IRQ context,
1039  * unlike the blank functions above, so we may sleep.
1040  */
1041 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1042 {
1043         struct pxafb_info *fbi = platform_get_drvdata(dev);
1044
1045         set_ctrlr_state(fbi, C_DISABLE_PM);
1046         return 0;
1047 }
1048
1049 static int pxafb_resume(struct platform_device *dev)
1050 {
1051         struct pxafb_info *fbi = platform_get_drvdata(dev);
1052
1053         set_ctrlr_state(fbi, C_ENABLE_PM);
1054         return 0;
1055 }
1056 #else
1057 #define pxafb_suspend   NULL
1058 #define pxafb_resume    NULL
1059 #endif
1060
1061 /*
1062  * pxafb_map_video_memory():
1063  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1064  *      remapped into a non-cached, non-buffered, memory region to
1065  *      allow palette and pixel writes to occur without flushing the
1066  *      cache.  Once this area is remapped, all virtual memory
1067  *      access to the video memory should occur at the new region.
1068  */
1069 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1070 {
1071         u_long palette_mem_size;
1072
1073         /*
1074          * We reserve one page for the palette, plus the size
1075          * of the framebuffer.
1076          */
1077         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1078         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1079                                               &fbi->map_dma, GFP_KERNEL);
1080
1081         if (fbi->map_cpu) {
1082                 /* prevent initial garbage on screen */
1083                 memset(fbi->map_cpu, 0, fbi->map_size);
1084                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1085                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1086                 /*
1087                  * FIXME: this is actually the wrong thing to place in
1088                  * smem_start.  But fbdev suffers from the problem that
1089                  * it needs an API which doesn't exist (in this case,
1090                  * dma_writecombine_mmap)
1091                  */
1092                 fbi->fb.fix.smem_start = fbi->screen_dma;
1093
1094                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1095
1096                 palette_mem_size = fbi->palette_size * sizeof(u16);
1097                 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1098
1099                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1100                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1101         }
1102
1103         return fbi->map_cpu ? 0 : -ENOMEM;
1104 }
1105
1106 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1107 {
1108         struct pxafb_info *fbi;
1109         void *addr;
1110         struct pxafb_mach_info *inf = dev->platform_data;
1111         struct pxafb_mode_info *mode = inf->modes;
1112         int i, smemlen;
1113
1114         /* Alloc the pxafb_info and pseudo_palette in one step */
1115         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1116         if (!fbi)
1117                 return NULL;
1118
1119         memset(fbi, 0, sizeof(struct pxafb_info));
1120         fbi->dev = dev;
1121
1122         strcpy(fbi->fb.fix.id, PXA_NAME);
1123
1124         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1125         fbi->fb.fix.type_aux    = 0;
1126         fbi->fb.fix.xpanstep    = 0;
1127         fbi->fb.fix.ypanstep    = 0;
1128         fbi->fb.fix.ywrapstep   = 0;
1129         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1130
1131         fbi->fb.var.nonstd      = 0;
1132         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1133         fbi->fb.var.height      = -1;
1134         fbi->fb.var.width       = -1;
1135         fbi->fb.var.accel_flags = 0;
1136         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1137
1138         fbi->fb.fbops           = &pxafb_ops;
1139         fbi->fb.flags           = FBINFO_DEFAULT;
1140         fbi->fb.node            = -1;
1141
1142         addr = fbi;
1143         addr = addr + sizeof(struct pxafb_info);
1144         fbi->fb.pseudo_palette  = addr;
1145
1146         pxafb_setmode(&fbi->fb.var, mode);
1147
1148         fbi->cmap_inverse               = inf->cmap_inverse;
1149         fbi->cmap_static                = inf->cmap_static;
1150
1151         fbi->lccr0                      = inf->lccr0;
1152         fbi->lccr3                      = inf->lccr3;
1153         fbi->state                      = C_STARTUP;
1154         fbi->task_state                 = (u_char)-1;
1155
1156         for (i = 0; i < inf->num_modes; i++) {
1157                 smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8;
1158                 if (smemlen > fbi->fb.fix.smem_len)
1159                         fbi->fb.fix.smem_len = smemlen;
1160         }
1161
1162         init_waitqueue_head(&fbi->ctrlr_wait);
1163         INIT_WORK(&fbi->task, pxafb_task);
1164         init_MUTEX(&fbi->ctrlr_sem);
1165
1166         return fbi;
1167 }
1168
1169 #ifdef CONFIG_FB_PXA_PARAMETERS
1170 static int __init pxafb_parse_options(struct device *dev, char *options)
1171 {
1172         struct pxafb_mach_info *inf = dev->platform_data;
1173         char *this_opt;
1174
1175         if (!options || !*options)
1176                 return 0;
1177
1178         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1179
1180         /* could be made table driven or similar?... */
1181         while ((this_opt = strsep(&options, ",")) != NULL) {
1182                 if (!strncmp(this_opt, "mode:", 5)) {
1183                         const char *name = this_opt+5;
1184                         unsigned int namelen = strlen(name);
1185                         int res_specified = 0, bpp_specified = 0;
1186                         unsigned int xres = 0, yres = 0, bpp = 0;
1187                         int yres_specified = 0;
1188                         int i;
1189                         for (i = namelen-1; i >= 0; i--) {
1190                                 switch (name[i]) {
1191                                 case '-':
1192                                         namelen = i;
1193                                         if (!bpp_specified && !yres_specified) {
1194                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1195                                                 bpp_specified = 1;
1196                                         } else
1197                                                 goto done;
1198                                         break;
1199                                 case 'x':
1200                                         if (!yres_specified) {
1201                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1202                                                 yres_specified = 1;
1203                                         } else
1204                                                 goto done;
1205                                         break;
1206                                 case '0' ... '9':
1207                                         break;
1208                                 default:
1209                                         goto done;
1210                                 }
1211                         }
1212                         if (i < 0 && yres_specified) {
1213                                 xres = simple_strtoul(name, NULL, 0);
1214                                 res_specified = 1;
1215                         }
1216                 done:
1217                         if (res_specified) {
1218                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1219                                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1220                         }
1221                         if (bpp_specified)
1222                                 switch (bpp) {
1223                                 case 1:
1224                                 case 2:
1225                                 case 4:
1226                                 case 8:
1227                                 case 16:
1228                                         inf->modes[0].bpp = bpp;
1229                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1230                                         break;
1231                                 default:
1232                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1233                                 }
1234                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1235                         inf->modes[0].pixclock = simple_strtoul(this_opt+9, NULL, 0);
1236                         dev_info(dev, "override pixclock: %ld\n", inf->modes[0].pixclock);
1237                 } else if (!strncmp(this_opt, "left:", 5)) {
1238                         inf->modes[0].left_margin = simple_strtoul(this_opt+5, NULL, 0);
1239                         dev_info(dev, "override left: %u\n", inf->modes[0].left_margin);
1240                 } else if (!strncmp(this_opt, "right:", 6)) {
1241                         inf->modes[0].right_margin = simple_strtoul(this_opt+6, NULL, 0);
1242                         dev_info(dev, "override right: %u\n", inf->modes[0].right_margin);
1243                 } else if (!strncmp(this_opt, "upper:", 6)) {
1244                         inf->modes[0].upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1245                         dev_info(dev, "override upper: %u\n", inf->modes[0].upper_margin);
1246                 } else if (!strncmp(this_opt, "lower:", 6)) {
1247                         inf->modes[0].lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1248                         dev_info(dev, "override lower: %u\n", inf->modes[0].lower_margin);
1249                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1250                         inf->modes[0].hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1251                         dev_info(dev, "override hsynclen: %u\n", inf->modes[0].hsync_len);
1252                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1253                         inf->modes[0].vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1254                         dev_info(dev, "override vsynclen: %u\n", inf->modes[0].vsync_len);
1255                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1256                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1257                                 dev_info(dev, "override hsync: Active Low\n");
1258                                 inf->modes[0].sync &= ~FB_SYNC_HOR_HIGH_ACT;
1259                         } else {
1260                                 dev_info(dev, "override hsync: Active High\n");
1261                                 inf->modes[0].sync |= FB_SYNC_HOR_HIGH_ACT;
1262                         }
1263                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1264                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1265                                 dev_info(dev, "override vsync: Active Low\n");
1266                                 inf->modes[0].sync &= ~FB_SYNC_VERT_HIGH_ACT;
1267                         } else {
1268                                 dev_info(dev, "override vsync: Active High\n");
1269                                 inf->modes[0].sync |= FB_SYNC_VERT_HIGH_ACT;
1270                         }
1271                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1272                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1273                                 dev_info(dev, "override double pixel clock: false\n");
1274                                 inf->lccr3 &= ~LCCR3_DPC;
1275                         } else {
1276                                 dev_info(dev, "override double pixel clock: true\n");
1277                                 inf->lccr3 |= LCCR3_DPC;
1278                         }
1279                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1280                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1281                                 dev_info(dev, "override output enable: active low\n");
1282                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1283                         } else {
1284                                 dev_info(dev, "override output enable: active high\n");
1285                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1286                         }
1287                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1288                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1289                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1290                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1291                         } else {
1292                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1293                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1294                         }
1295                 } else if (!strncmp(this_opt, "color", 5)) {
1296                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1297                 } else if (!strncmp(this_opt, "mono", 4)) {
1298                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1299                 } else if (!strncmp(this_opt, "active", 6)) {
1300                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1301                 } else if (!strncmp(this_opt, "passive", 7)) {
1302                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1303                 } else if (!strncmp(this_opt, "single", 6)) {
1304                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1305                 } else if (!strncmp(this_opt, "dual", 4)) {
1306                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1307                 } else if (!strncmp(this_opt, "4pix", 4)) {
1308                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1309                 } else if (!strncmp(this_opt, "8pix", 4)) {
1310                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1311                 } else {
1312                         dev_err(dev, "unknown option: %s\n", this_opt);
1313                         return -EINVAL;
1314                 }
1315         }
1316         return 0;
1317
1318 }
1319 #endif
1320
1321 int __init pxafb_probe(struct platform_device *dev)
1322 {
1323         struct pxafb_info *fbi;
1324         struct pxafb_mach_info *inf;
1325         int ret;
1326
1327         dev_dbg(&dev->dev, "pxafb_probe\n");
1328
1329         inf = dev->dev.platform_data;
1330         ret = -ENOMEM;
1331         fbi = NULL;
1332         if (!inf)
1333                 goto failed;
1334
1335 #ifdef CONFIG_FB_PXA_PARAMETERS
1336         ret = pxafb_parse_options(&dev->dev, g_options);
1337         if (ret < 0)
1338                 goto failed;
1339 #endif
1340
1341 #ifdef DEBUG_VAR
1342         /* Check for various illegal bit-combinations. Currently only
1343          * a warning is given. */
1344
1345         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1346                 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1347                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1348         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1349                 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1350                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1351         if (inf->lccr0 & LCCR0_DPD &&
1352             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1353              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1354              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1355                 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1356                          " single panel mode\n");
1357         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1358             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1359                 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1360         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1361              (inf->modes->upper_margin || inf->modes->lower_margin))
1362                 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
1363 #endif
1364
1365         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp);
1366         if (inf->modes->xres == 0 || inf->modes->yres == 0 || inf->modes->bpp == 0) {
1367                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1368                 ret = -EINVAL;
1369                 goto failed;
1370         }
1371         pxafb_backlight_power = inf->pxafb_backlight_power;
1372         pxafb_lcd_power = inf->pxafb_lcd_power;
1373         fbi = pxafb_init_fbinfo(&dev->dev);
1374         if (!fbi) {
1375                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1376                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1377                 goto failed;
1378         }
1379
1380         /* Initialize video memory */
1381         ret = pxafb_map_video_memory(fbi);
1382         if (ret) {
1383                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1384                 ret = -ENOMEM;
1385                 goto failed;
1386         }
1387
1388         ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1389         if (ret) {
1390                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1391                 ret = -EBUSY;
1392                 goto failed;
1393         }
1394
1395         /*
1396          * This makes sure that our colour bitfield
1397          * descriptors are correctly initialised.
1398          */
1399         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1400         pxafb_set_par(&fbi->fb);
1401
1402         platform_set_drvdata(dev, fbi);
1403
1404         ret = register_framebuffer(&fbi->fb);
1405         if (ret < 0) {
1406                 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
1407                 goto failed;
1408         }
1409
1410 #ifdef CONFIG_PM
1411         // TODO
1412 #endif
1413
1414 #ifdef CONFIG_CPU_FREQ
1415         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1416         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1417         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1418         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1419 #endif
1420
1421         /*
1422          * Ok, now enable the LCD controller
1423          */
1424         set_ctrlr_state(fbi, C_ENABLE);
1425
1426         return 0;
1427
1428 failed:
1429         platform_set_drvdata(dev, NULL);
1430         kfree(fbi);
1431         return ret;
1432 }
1433
1434 static struct platform_driver pxafb_driver = {
1435         .probe          = pxafb_probe,
1436 #ifdef CONFIG_PM
1437         .suspend        = pxafb_suspend,
1438         .resume         = pxafb_resume,
1439 #endif
1440         .driver         = {
1441                 .name   = "pxa2xx-fb",
1442         },
1443 };
1444
1445 #ifndef MODULE
1446 int __devinit pxafb_setup(char *options)
1447 {
1448 # ifdef CONFIG_FB_PXA_PARAMETERS
1449         if (options)
1450                 strlcpy(g_options, options, sizeof(g_options));
1451 # endif
1452         return 0;
1453 }
1454 #else
1455 # ifdef CONFIG_FB_PXA_PARAMETERS
1456 module_param_string(options, g_options, sizeof(g_options), 0);
1457 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1458 # endif
1459 #endif
1460
1461 int __devinit pxafb_init(void)
1462 {
1463 #ifndef MODULE
1464         char *option = NULL;
1465
1466         if (fb_get_options("pxafb", &option))
1467                 return -ENODEV;
1468         pxafb_setup(option);
1469 #endif
1470         return platform_driver_register(&pxafb_driver);
1471 }
1472
1473 module_init(pxafb_init);
1474
1475 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1476 MODULE_LICENSE("GPL");