drivers/video/pm3fb.c

   1 /*
   2  *  linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
   3  *
   4  *  Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
   5  *
   6  *  Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
   7  *      based on pm2fb.c
   8  *
   9  *  Based on code written by:
  10  *         Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11  *         Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12  *         Russell King, <rmk@arm.linux.org.uk>
  13  *  Based on linux/drivers/video/skeletonfb.c:
  14  *      Copyright (C) 1997 Geert Uytterhoeven
  15  *  Based on linux/driver/video/pm2fb.c:
  16  *      Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17  *      Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License. See the file COPYING in the main directory of this archive for
  21  *  more details.
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/fb.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35
  36 #include <video/pm3fb.h>
  37
  38 #if !defined(CONFIG_PCI)
  39 #error "Only generic PCI cards supported."
  40 #endif
  41
  42 #undef PM3FB_MASTER_DEBUG
  43 #ifdef PM3FB_MASTER_DEBUG
  44 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
  45 #else
  46 #define DPRINTK(a,b...)
  47 #endif
  48
  49 /*
  50  * Driver data
  51  */
  52 static char *mode_option __devinitdata;
  53
  54 /*
  55  *  If your driver supports multiple boards, you should make the
  56  *  below data types arrays, or allocate them dynamically (using kmalloc()).
  57  */
  58
  59 /*
  60  * This structure defines the hardware state of the graphics card. Normally
  61  * you place this in a header file in linux/include/video. This file usually
  62  * also includes register information. That allows other driver subsystems
  63  * and userland applications the ability to use the same header file to
  64  * avoid duplicate work and easy porting of software.
  65  */
  66 struct pm3_par {
  67         unsigned char   __iomem *v_regs;/* virtual address of p_regs */
  68         u32             video;          /* video flags before blanking */
  69         u32             base;           /* screen base (xoffset+yoffset) in 128 bits unit */
  70         u32             palette[16];
  71 };
  72
  73 /*
  74  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  75  * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  76  * to get a fb_var_screeninfo. Otherwise define a default var as well.
  77  */
  78 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
  79         .id =           "Permedia3",
  80         .type =         FB_TYPE_PACKED_PIXELS,
  81         .visual =       FB_VISUAL_PSEUDOCOLOR,
  82         .xpanstep =     1,
  83         .ypanstep =     1,
  84         .ywrapstep =    0,
  85         .accel =        FB_ACCEL_NONE,
  86 };
  87
  88 /*
  89  * Utility functions
  90  */
  91
  92 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
  93 {
  94         return fb_readl(par->v_regs + off);
  95 }
  96
  97 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
  98 {
  99         fb_writel(v, par->v_regs + off);
 100 }
 101
 102 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
 103 {
 104         while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
 105 }
 106
 107 static inline void PM3_SLOW_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
 108 {
 109         if (par->v_regs) {
 110                 mb();
 111                 PM3_WAIT(par, 1);
 112                 wmb();
 113                 PM3_WRITE_REG(par, off, v);
 114         }
 115 }
 116
 117 static inline void PM3_SET_INDEX(struct pm3_par *par, unsigned index)
 118 {
 119         PM3_SLOW_WRITE_REG(par, PM3RD_IndexHigh, (index >> 8) & 0xff);
 120         PM3_SLOW_WRITE_REG(par, PM3RD_IndexLow, index & 0xff);
 121 }
 122
 123 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
 124 {
 125         PM3_SET_INDEX(par, r);
 126         wmb();
 127         PM3_WRITE_REG(par, PM3RD_IndexedData, v);
 128 }
 129
 130 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
 131                         unsigned char r, unsigned char g, unsigned char b)
 132 {
 133         PM3_SLOW_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
 134         PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, r);
 135         PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, g);
 136         PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, b);
 137 }
 138
 139 static void pm3fb_clear_colormap(struct pm3_par *par,
 140                         unsigned char r, unsigned char g, unsigned char b)
 141 {
 142         int i;
 143
 144         for (i = 0; i < 256 ; i++) /* fill color map with white */
 145                 pm3fb_set_color(par, i, r, g, b);
 146
 147 }
 148
 149 /* Calculating various clock parameter */
 150 static void pm3fb_calculate_clock(unsigned long reqclock,
 151                                 unsigned char *prescale,
 152                                 unsigned char *feedback,
 153                                 unsigned char *postscale)
 154 {
 155         int f, pre, post;
 156         unsigned long freq;
 157         long freqerr = 1000;
 158         long currerr;
 159
 160         for (f = 1; f < 256; f++) {
 161                 for (pre = 1; pre < 256; pre++) {
 162                         for (post = 0; post < 5; post++) {
 163                                 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
 164                                 currerr = (reqclock > freq)
 165                                         ? reqclock - freq
 166                                         : freq - reqclock;
 167                                 if (currerr < freqerr) {
 168                                         freqerr = currerr;
 169                                         *feedback = f;
 170                                         *prescale = pre;
 171                                         *postscale = post;
 172                                 }
 173                         }
 174                 }
 175         }
 176 }
 177
 178 static inline int pm3fb_shift_bpp(unsigned long depth, int v)
 179 {
 180         switch (depth) {
 181         case 8:
 182                 return (v >> 4);
 183         case 12:
 184         case 15:
 185         case 16:
 186                 return (v >> 3);
 187         case 32:
 188                 return (v >> 2);
 189         }
 190         DPRINTK("Unsupported depth %ld\n", depth);
 191         return 0;
 192 }
 193
 194 /* write the mode to registers */
 195 static void pm3fb_write_mode(struct fb_info *info)
 196 {
 197         struct pm3_par *par = info->par;
 198         char tempsync = 0x00, tempmisc = 0x00;
 199         const u32 hsstart = info->var.right_margin;
 200         const u32 hsend = hsstart + info->var.hsync_len;
 201         const u32 hbend = hsend + info->var.left_margin;
 202         const u32 xres = (info->var.xres + 31) & ~31;
 203         const u32 htotal = xres + hbend;
 204         const u32 vsstart = info->var.lower_margin;
 205         const u32 vsend = vsstart + info->var.vsync_len;
 206         const u32 vbend = vsend + info->var.upper_margin;
 207         const u32 vtotal = info->var.yres + vbend;
 208         const u32 width = (info->var.xres_virtual + 7) & ~7;
 209
 210         PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
 211         PM3_SLOW_WRITE_REG(par, PM3Aperture0, 0x00000000);
 212         PM3_SLOW_WRITE_REG(par, PM3Aperture1, 0x00000000);
 213         PM3_SLOW_WRITE_REG(par, PM3FIFODis, 0x00000007);
 214
 215         PM3_SLOW_WRITE_REG(par, PM3HTotal,
 216                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 217                                           htotal - 1));
 218         PM3_SLOW_WRITE_REG(par, PM3HsEnd,
 219                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 220                                           hsend));
 221         PM3_SLOW_WRITE_REG(par, PM3HsStart,
 222                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 223                                           hsstart));
 224         PM3_SLOW_WRITE_REG(par, PM3HbEnd,
 225                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 226                                           hbend));
 227         PM3_SLOW_WRITE_REG(par, PM3HgEnd,
 228                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 229                                           hbend));
 230         PM3_SLOW_WRITE_REG(par, PM3ScreenStride,
 231                            pm3fb_shift_bpp(info->var.bits_per_pixel,
 232                                           width));
 233         PM3_SLOW_WRITE_REG(par, PM3VTotal, vtotal - 1);
 234         PM3_SLOW_WRITE_REG(par, PM3VsEnd, vsend - 1);
 235         PM3_SLOW_WRITE_REG(par, PM3VsStart, vsstart - 1);
 236         PM3_SLOW_WRITE_REG(par, PM3VbEnd, vbend);
 237
 238         switch (info->var.bits_per_pixel) {
 239         case 8:
 240                 PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode,
 241                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 242                 PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode,
 243                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 244                 break;
 245
 246         case 12:
 247         case 15:
 248         case 16:
 249 #ifndef __BIG_ENDIAN
 250                 PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode,
 251                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 252                 PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode,
 253                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 254 #else
 255                 PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode,
 256                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 257                                    PM3ByApertureMode_BYTESWAP_BADC);
 258                 PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode,
 259                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 260                                    PM3ByApertureMode_BYTESWAP_BADC);
 261 #endif /* ! __BIG_ENDIAN */
 262                 break;
 263
 264         case 32:
 265 #ifndef __BIG_ENDIAN
 266                 PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode,
 267                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 268                 PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode,
 269                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 270 #else
 271                 PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode,
 272                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 273                                    PM3ByApertureMode_BYTESWAP_DCBA);
 274                 PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode,
 275                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 276                                    PM3ByApertureMode_BYTESWAP_DCBA);
 277 #endif /* ! __BIG_ENDIAN */
 278                 break;
 279
 280         default:
 281                 DPRINTK("Unsupported depth %d\n",
 282                         info->var.bits_per_pixel);
 283                 break;
 284         }
 285
 286         /*
 287          * Oxygen VX1 - it appears that setting PM3VideoControl and
 288          * then PM3RD_SyncControl to the same SYNC settings undoes
 289          * any net change - they seem to xor together.  Only set the
 290          * sync options in PM3RD_SyncControl.  --rmk
 291          */
 292         {
 293                 unsigned int video = par->video;
 294
 295                 video &= ~(PM3VideoControl_HSYNC_MASK |
 296                            PM3VideoControl_VSYNC_MASK);
 297                 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 298                          PM3VideoControl_VSYNC_ACTIVE_HIGH;
 299                 PM3_SLOW_WRITE_REG(par, PM3VideoControl, video);
 300         }
 301         PM3_SLOW_WRITE_REG(par, PM3VClkCtl,
 302                            (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
 303         PM3_SLOW_WRITE_REG(par, PM3ScreenBase, par->base);
 304         PM3_SLOW_WRITE_REG(par, PM3ChipConfig,
 305                            (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
 306
 307         {
 308                 unsigned char uninitialized_var(m);     /* ClkPreScale */
 309                 unsigned char uninitialized_var(n);     /* ClkFeedBackScale */
 310                 unsigned char uninitialized_var(p);     /* ClkPostScale */
 311                 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
 312
 313                 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
 314
 315                 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
 316                         pixclock, (int) m, (int) n, (int) p);
 317
 318                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
 319                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
 320                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
 321         }
 322         /*
 323            PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
 324          */
 325         /*
 326            PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
 327          */
 328         if ((par->video & PM3VideoControl_HSYNC_MASK) ==
 329             PM3VideoControl_HSYNC_ACTIVE_HIGH)
 330                 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
 331         if ((par->video & PM3VideoControl_VSYNC_MASK) ==
 332             PM3VideoControl_VSYNC_ACTIVE_HIGH)
 333                 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
 334
 335         PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
 336         DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
 337
 338         PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
 339
 340         switch (info->var.bits_per_pixel) {
 341         case 8:
 342                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 343                                   PM3RD_PixelSize_8_BIT_PIXELS);
 344                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 345                                   PM3RD_ColorFormat_CI8_COLOR |
 346                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 347                 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 348                 break;
 349         case 12:
 350                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 351                                   PM3RD_PixelSize_16_BIT_PIXELS);
 352                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 353                                   PM3RD_ColorFormat_4444_COLOR |
 354                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 355                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 356                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 357                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 358                 break;
 359         case 15:
 360                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 361                                   PM3RD_PixelSize_16_BIT_PIXELS);
 362                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 363                                   PM3RD_ColorFormat_5551_FRONT_COLOR |
 364                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 365                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 366                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 367                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 368                 break;
 369         case 16:
 370                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 371                                   PM3RD_PixelSize_16_BIT_PIXELS);
 372                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 373                                   PM3RD_ColorFormat_565_FRONT_COLOR |
 374                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 375                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 376                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 377                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 378                 break;
 379         case 32:
 380                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 381                                   PM3RD_PixelSize_32_BIT_PIXELS);
 382                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 383                                   PM3RD_ColorFormat_8888_COLOR |
 384                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 385                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 386                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 387                 break;
 388         }
 389         PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
 390 }
 391
 392 /*
 393  * hardware independent functions
 394  */
 395 int pm3fb_init(void);
 396 int pm3fb_setup(char*);
 397
 398 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 399 {
 400         u32 lpitch;
 401
 402         var->transp.offset = 0;
 403         var->transp.length = 0;
 404         switch(var->bits_per_pixel) {
 405         case 8:
 406                 var->red.length = var->green.length = var->blue.length = 8;
 407                 var->red.offset = var->green.offset = var->blue.offset = 0;
 408                 break;
 409         case 12:
 410                 var->red.offset   = 8;
 411                 var->red.length   = 4;
 412                 var->green.offset = 4;
 413                 var->green.length = 4;
 414                 var->blue.offset  = 0;
 415                 var->blue.length  = 4;
 416                 var->transp.offset = 12;
 417                 var->transp.length = 4;
 418         case 15:
 419                 var->red.offset   = 10;
 420                 var->red.length   = 5;
 421                 var->green.offset = 5;
 422                 var->green.length = 5;
 423                 var->blue.offset  = 0;
 424                 var->blue.length  = 5;
 425                 var->transp.offset = 15;
 426                 var->transp.length = 1;
 427                 break;
 428         case 16:
 429                 var->red.offset   = 11;
 430                 var->red.length   = 5;
 431                 var->green.offset = 5;
 432                 var->green.length = 6;
 433                 var->blue.offset  = 0;
 434                 var->blue.length  = 5;
 435                 break;
 436         case 32:
 437                 var->transp.offset = 24;
 438                 var->transp.length = 8;
 439                 var->red.offset   = 16;
 440                 var->green.offset = 8;
 441                 var->blue.offset  = 0;
 442                 var->red.length = var->green.length = var->blue.length = 8;
 443                 break;
 444         default:
 445                 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 446                 return -EINVAL;
 447         }
 448         var->height = var->width = -1;
 449
 450         if (var->xres != var->xres_virtual) {
 451                 DPRINTK("virtual x resolution != physical x resolution not supported\n");
 452                 return -EINVAL;
 453         }
 454
 455         if (var->yres > var->yres_virtual) {
 456                 DPRINTK("virtual y resolution < physical y resolution not possible\n");
 457                 return -EINVAL;
 458         }
 459
 460         if (var->xoffset) {
 461                 DPRINTK("xoffset not supported\n");
 462                 return -EINVAL;
 463         }
 464
 465         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 466                 DPRINTK("interlace not supported\n");
 467                 return -EINVAL;
 468         }
 469
 470         var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
 471         lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
 472
 473         if (var->xres < 200 || var->xres > 2048) {
 474                 DPRINTK("width not supported: %u\n", var->xres);
 475                 return -EINVAL;
 476         }
 477
 478         if (var->yres < 200 || var->yres > 4095) {
 479                 DPRINTK("height not supported: %u\n", var->yres);
 480                 return -EINVAL;
 481         }
 482
 483         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 484                 DPRINTK("no memory for screen (%ux%ux%u)\n",
 485                         var->xres, var->yres_virtual, var->bits_per_pixel);
 486                 return -EINVAL;
 487         }
 488
 489         if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
 490                 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
 491                 return -EINVAL;
 492         }
 493
 494         var->accel_flags = 0;   /* Can't mmap if this is on */
 495
 496         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 497                 var->xres, var->yres, var->bits_per_pixel);
 498         return 0;
 499 }
 500
 501 static int pm3fb_set_par(struct fb_info *info)
 502 {
 503         struct pm3_par *par = info->par;
 504         const u32 xres = (info->var.xres + 31) & ~31;
 505         const int depth = (info->var.bits_per_pixel + 7) & ~7;
 506
 507         par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
 508                                         (info->var.yoffset * xres)
 509                                         + info->var.xoffset);
 510         par->video = 0;
 511
 512         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 513                 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
 514         else
 515                 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
 516
 517         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 518                 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
 519         else
 520                 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
 521
 522         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
 523                 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
 524         else
 525                 par->video |= PM3VideoControl_LINE_DOUBLE_OFF;
 526
 527         if (info->var.activate == FB_ACTIVATE_NOW)
 528                 par->video |= PM3VideoControl_ENABLE;
 529         else {
 530                 par->video |= PM3VideoControl_DISABLE;
 531                 DPRINTK("PM3Video disabled\n");
 532         }
 533         switch (depth) {
 534         case 8:
 535                 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
 536                 break;
 537         case 12:
 538         case 15:
 539         case 16:
 540                 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
 541                 break;
 542         case 32:
 543                 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
 544                 break;
 545         default:
 546                 DPRINTK("Unsupported depth\n");
 547                 break;
 548         }
 549
 550         info->fix.visual =
 551                 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 552         info->fix.line_length = ((info->var.xres_virtual + 7)  & ~7)
 553                                         * depth / 8;
 554
 555 /*      pm3fb_clear_memory(info, 0);*/
 556         pm3fb_clear_colormap(par, 0, 0, 0);
 557         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode,
 558                           PM3RD_CursorMode_CURSOR_DISABLE);
 559         pm3fb_write_mode(info);
 560         return 0;
 561 }
 562
 563 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 564                            unsigned blue, unsigned transp,
 565                            struct fb_info *info)
 566 {
 567         struct pm3_par *par = info->par;
 568
 569         if (regno >= 256)  /* no. of hw registers */
 570            return -EINVAL;
 571
 572         /* grayscale works only partially under directcolor */
 573         if (info->var.grayscale) {
 574            /* grayscale = 0.30*R + 0.59*G + 0.11*B */
 575            red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 576         }
 577
 578         /* Directcolor:
 579          *   var->{color}.offset contains start of bitfield
 580          *   var->{color}.length contains length of bitfield
 581          *   {hardwarespecific} contains width of DAC
 582          *   pseudo_palette[X] is programmed to (X << red.offset) |
 583          *                                    (X << green.offset) |
 584          *                                    (X << blue.offset)
 585          *   RAMDAC[X] is programmed to (red, green, blue)
 586          *   color depth = SUM(var->{color}.length)
 587          *
 588          * Pseudocolor:
 589          *      var->{color}.offset is 0
 590          *      var->{color}.length contains width of DAC or the number of unique
 591          *                      colors available (color depth)
 592          *      pseudo_palette is not used
 593          *      RAMDAC[X] is programmed to (red, green, blue)
 594          *      color depth = var->{color}.length
 595          */
 596
 597         /*
 598          * This is the point where the color is converted to something that
 599          * is acceptable by the hardware.
 600          */
 601 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 602         red = CNVT_TOHW(red, info->var.red.length);
 603         green = CNVT_TOHW(green, info->var.green.length);
 604         blue = CNVT_TOHW(blue, info->var.blue.length);
 605         transp = CNVT_TOHW(transp, info->var.transp.length);
 606 #undef CNVT_TOHW
 607
 608         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 609         info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 610                 u32 v;
 611
 612                 if (regno >= 16)
 613                         return -EINVAL;
 614
 615                 v = (red << info->var.red.offset) |
 616                         (green << info->var.green.offset) |
 617                         (blue << info->var.blue.offset) |
 618                         (transp << info->var.transp.offset);
 619
 620                 switch (info->var.bits_per_pixel) {
 621                 case 8:
 622                         break;
 623                 case 16:
 624                 case 24:
 625                 case 32:
 626                         ((u32*)(info->pseudo_palette))[regno] = v;
 627                         break;
 628                 }
 629                 return 0;
 630         }
 631         else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
 632                 pm3fb_set_color(par, regno, red, green, blue);
 633
 634         return 0;
 635 }
 636
 637 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
 638                                  struct fb_info *info)
 639 {
 640         struct pm3_par *par = info->par;
 641         const u32 xres = (var->xres + 31) & ~31;
 642
 643         par->base = pm3fb_shift_bpp(var->bits_per_pixel,
 644                                         (var->yoffset * xres)
 645                                         + var->xoffset);
 646         PM3_SLOW_WRITE_REG(par, PM3ScreenBase, par->base);
 647         return 0;
 648 }
 649
 650 static int pm3fb_blank(int blank_mode, struct fb_info *info)
 651 {
 652         struct pm3_par *par = info->par;
 653         u32 video = par->video;
 654
 655         /*
 656          * Oxygen VX1 - it appears that setting PM3VideoControl and
 657          * then PM3RD_SyncControl to the same SYNC settings undoes
 658          * any net change - they seem to xor together.  Only set the
 659          * sync options in PM3RD_SyncControl.  --rmk
 660          */
 661         video &= ~(PM3VideoControl_HSYNC_MASK |
 662                    PM3VideoControl_VSYNC_MASK);
 663         video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 664                  PM3VideoControl_VSYNC_ACTIVE_HIGH;
 665
 666         switch (blank_mode) {
 667         case FB_BLANK_UNBLANK:
 668                 video = video | PM3VideoControl_ENABLE;
 669                 break;
 670         case FB_BLANK_NORMAL:   /* FIXME */
 671                 video = video & ~(PM3VideoControl_ENABLE);
 672                 break;
 673         case FB_BLANK_HSYNC_SUSPEND:
 674                 video = video & ~(PM3VideoControl_HSYNC_MASK |
 675                                   PM3VideoControl_BLANK_ACTIVE_LOW);
 676                 break;
 677         case FB_BLANK_VSYNC_SUSPEND:
 678                 video = video & ~(PM3VideoControl_VSYNC_MASK |
 679                                   PM3VideoControl_BLANK_ACTIVE_LOW);
 680                 break;
 681         case FB_BLANK_POWERDOWN:
 682                 video = video & ~(PM3VideoControl_HSYNC_MASK |
 683                                   PM3VideoControl_VSYNC_MASK |
 684                                   PM3VideoControl_BLANK_ACTIVE_LOW);
 685                 break;
 686         default:
 687                 DPRINTK("Unsupported blanking %d\n", blank_mode);
 688                 return 1;
 689         }
 690
 691         PM3_SLOW_WRITE_REG(par,PM3VideoControl, video);
 692
 693         return 0;
 694 }
 695
 696         /*
 697          *  Frame buffer operations
 698          */
 699
 700 static struct fb_ops pm3fb_ops = {
 701         .owner          = THIS_MODULE,
 702         .fb_check_var   = pm3fb_check_var,
 703         .fb_set_par     = pm3fb_set_par,
 704         .fb_setcolreg   = pm3fb_setcolreg,
 705         .fb_pan_display = pm3fb_pan_display,
 706         .fb_fillrect    = cfb_fillrect,         /* Needed !!! */
 707         .fb_copyarea    = cfb_copyarea,         /* Needed !!! */
 708         .fb_imageblit   = cfb_imageblit,        /* Needed !!! */
 709         .fb_blank       = pm3fb_blank,
 710 };
 711
 712 /* ------------------------------------------------------------------------- */
 713
 714         /*
 715          *  Initialization
 716          */
 717
 718 /* mmio register are already mapped when this function is called */
 719 /* the pm3fb_fix.smem_start is also set */
 720 static unsigned long pm3fb_size_memory(struct pm3_par *par)
 721 {
 722         unsigned long   memsize = 0, tempBypass, i, temp1, temp2;
 723         unsigned char   __iomem *screen_mem;
 724
 725         pm3fb_fix.smem_len = 64 * 1024 * 1024; /* request full aperture size */
 726         /* Linear frame buffer - request region and map it. */
 727         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
 728                                  "pm3fb smem")) {
 729                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
 730                 return 0;
 731         }
 732         screen_mem =
 733                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 734         if (!screen_mem) {
 735                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
 736                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 737                 return 0;
 738         }
 739
 740         /* TODO: card-specific stuff, *before* accessing *any* FB memory */
 741         /* For Appian Jeronimo 2000 board second head */
 742
 743         tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
 744
 745         DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
 746
 747         PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
 748
 749         /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */
 750         for (i = 0; i < 32; i++) {
 751                 fb_writel(i * 0x00345678,
 752                           (screen_mem + (i * 1048576)));
 753                 mb();
 754                 temp1 = fb_readl((screen_mem + (i * 1048576)));
 755
 756                 /* Let's check for wrapover, write will fail at 16MB boundary */
 757                 if (temp1 == (i * 0x00345678))
 758                         memsize = i;
 759                 else
 760                         break;
 761         }
 762
 763         DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
 764
 765         if (memsize + 1 == i) {
 766                 for (i = 0; i < 32; i++) {
 767                         /* Clear first 32MB ; 0 is 0, no need to byteswap */
 768                         writel(0x0000000,
 769                                (screen_mem + (i * 1048576)));
 770                         mb();
 771                 }
 772
 773                 for (i = 32; i < 64; i++) {
 774                         fb_writel(i * 0x00345678,
 775                                   (screen_mem + (i * 1048576)));
 776                         mb();
 777                         temp1 =
 778                             fb_readl((screen_mem + (i * 1048576)));
 779                         temp2 =
 780                             fb_readl((screen_mem + ((i - 32) * 1048576)));
 781                         /* different value, different RAM... */
 782                         if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
 783                                 memsize = i;
 784                         else
 785                                 break;
 786                 }
 787         }
 788         DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
 789
 790         PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
 791
 792         iounmap(screen_mem);
 793         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 794         memsize = 1048576 * (memsize + 1);
 795
 796         DPRINTK("Returning 0x%08lx bytes\n", memsize);
 797
 798         return memsize;
 799 }
 800
 801 static int __devinit pm3fb_probe(struct pci_dev *dev,
 802                                   const struct pci_device_id *ent)
 803 {
 804         struct fb_info *info;
 805         struct pm3_par *par;
 806         struct device* device = &dev->dev; /* for pci drivers */
 807         int err, retval = -ENXIO;
 808
 809         err = pci_enable_device(dev);
 810         if (err) {
 811                 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
 812                 return err;
 813         }
 814         /*
 815          * Dynamically allocate info and par
 816          */
 817         info = framebuffer_alloc(sizeof(struct pm3_par), device);
 818
 819         if (!info)
 820                 return -ENOMEM;
 821         par = info->par;
 822
 823         /*
 824          * Here we set the screen_base to the virtual memory address
 825          * for the framebuffer.
 826          */
 827         pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
 828         pm3fb_fix.mmio_len = PM3_REGS_SIZE;
 829
 830         /* Registers - request region and map it. */
 831         if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
 832                                  "pm3fb regbase")) {
 833                 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
 834                 goto err_exit_neither;
 835         }
 836         par->v_regs =
 837                 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
 838         if (!par->v_regs) {
 839                 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
 840                         pm3fb_fix.id);
 841                 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
 842                 goto err_exit_neither;
 843         }
 844
 845 #if defined(__BIG_ENDIAN)
 846         pm3fb_fix.mmio_start += PM3_REGS_SIZE;
 847         DPRINTK("Adjusting register base for big-endian.\n");
 848 #endif
 849         /* Linear frame buffer - request region and map it. */
 850         pm3fb_fix.smem_start = pci_resource_start(dev, 1);
 851         pm3fb_fix.smem_len = pm3fb_size_memory(par);
 852         if (!pm3fb_fix.smem_len)
 853         {
 854                 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
 855                 goto err_exit_mmio;
 856         }
 857         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
 858                                  "pm3fb smem")) {
 859                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
 860                 goto err_exit_mmio;
 861         }
 862         info->screen_base =
 863                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 864         if (!info->screen_base) {
 865                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
 866                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 867                 goto err_exit_mmio;
 868         }
 869         info->screen_size = pm3fb_fix.smem_len;
 870
 871         info->fbops = &pm3fb_ops;
 872
 873         par->video = PM3_READ_REG(par, PM3VideoControl);
 874
 875         info->fix = pm3fb_fix;
 876         info->pseudo_palette = par->palette;
 877         info->flags = FBINFO_DEFAULT;/* | FBINFO_HWACCEL_YPAN;*/
 878
 879         /*
 880          * This should give a reasonable default video mode. The following is
 881          * done when we can set a video mode.
 882          */
 883         if (!mode_option)
 884                 mode_option = "640x480@60";
 885
 886         retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
 887
 888         if (!retval || retval == 4) {
 889                 retval = -EINVAL;
 890                 goto err_exit_both;
 891         }
 892
 893         /* This has to been done !!! */
 894         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
 895                 retval = -ENOMEM;
 896                 goto err_exit_both;
 897         }
 898
 899         /*
 900          * For drivers that can...
 901          */
 902         pm3fb_check_var(&info->var, info);
 903
 904         if (register_framebuffer(info) < 0) {
 905                 retval = -EINVAL;
 906                 goto err_exit_all;
 907         }
 908         printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
 909            info->fix.id);
 910         pci_set_drvdata(dev, info); /* or dev_set_drvdata(device, info) */
 911         return 0;
 912
 913  err_exit_all:
 914         fb_dealloc_cmap(&info->cmap);
 915  err_exit_both:
 916         iounmap(info->screen_base);
 917         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 918  err_exit_mmio:
 919         iounmap(par->v_regs);
 920         release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
 921  err_exit_neither:
 922         framebuffer_release(info);
 923         return retval;
 924 }
 925
 926         /*
 927          *  Cleanup
 928          */
 929 static void __devexit pm3fb_remove(struct pci_dev *dev)
 930 {
 931         struct fb_info *info = pci_get_drvdata(dev);
 932
 933         if (info) {
 934                 struct fb_fix_screeninfo *fix = &info->fix;
 935                 struct pm3_par *par = info->par;
 936
 937                 unregister_framebuffer(info);
 938                 fb_dealloc_cmap(&info->cmap);
 939
 940                 iounmap(info->screen_base);
 941                 release_mem_region(fix->smem_start, fix->smem_len);
 942                 iounmap(par->v_regs);
 943                 release_mem_region(fix->mmio_start, fix->mmio_len);
 944
 945                 pci_set_drvdata(dev, NULL);
 946                 framebuffer_release(info);
 947         }
 948 }
 949
 950 static struct pci_device_id pm3fb_id_table[] = {
 951         { PCI_VENDOR_ID_3DLABS, 0x0a,
 952           PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 953           0xff0000, 0 },
 954         { 0, }
 955 };
 956
 957 /* For PCI drivers */
 958 static struct pci_driver pm3fb_driver = {
 959         .name =         "pm3fb",
 960         .id_table =     pm3fb_id_table,
 961         .probe =        pm3fb_probe,
 962         .remove =       __devexit_p(pm3fb_remove),
 963 };
 964
 965 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
 966
 967 int __init pm3fb_init(void)
 968 {
 969         /*
 970          *  For kernel boot options (in 'video=pm3fb:<options>' format)
 971          */
 972 #ifndef MODULE
 973         char *option = NULL;
 974
 975         if (fb_get_options("pm3fb", &option))
 976                 return -ENODEV;
 977         pm3fb_setup(option);
 978 #endif
 979
 980         return pci_register_driver(&pm3fb_driver);
 981 }
 982
 983 static void __exit pm3fb_exit(void)
 984 {
 985         pci_unregister_driver(&pm3fb_driver);
 986 }
 987
 988 #ifdef MODULE
 989         /*
 990          *  Setup
 991          */
 992
 993 /*
 994  * Only necessary if your driver takes special options,
 995  * otherwise we fall back on the generic fb_setup().
 996  */
 997 int __init pm3fb_setup(char *options)
 998 {
 999         /* Parse user speficied options (`video=pm3fb:') */
1000         return 0;
1001 }
1002 #endif /* MODULE */
1003
1004 module_init(pm3fb_init);
1005 module_exit(pm3fb_exit);
1006
1007 MODULE_LICENSE("GPL");