drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39
  40 #include <video/omapdss.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44 #include "dispc.h"
  45
  46 /* DISPC */
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 enum omap_burst_size {
  50         BURST_SIZE_X2 = 0,
  51         BURST_SIZE_X4 = 1,
  52         BURST_SIZE_X8 = 2,
  53 };
  54
  55 #define REG_GET(idx, start, end) \
  56         FLD_GET(dispc_read_reg(idx), start, end)
  57
  58 #define REG_FLD_MOD(idx, val, start, end)                               \
  59         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  60
  61 struct dispc_features {
  62         u8 sw_start;
  63         u8 fp_start;
  64         u8 bp_start;
  65         u16 sw_max;
  66         u16 vp_max;
  67         u16 hp_max;
  68         u8 mgr_width_start;
  69         u8 mgr_height_start;
  70         u16 mgr_width_max;
  71         u16 mgr_height_max;
  72         unsigned long max_lcd_pclk;
  73         unsigned long max_tv_pclk;
  74         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  75                 const struct omap_video_timings *mgr_timings,
  76                 u16 width, u16 height, u16 out_width, u16 out_height,
  77                 enum omap_color_mode color_mode, bool *five_taps,
  78                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  79                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  80         unsigned long (*calc_core_clk) (unsigned long pclk,
  81                 u16 width, u16 height, u16 out_width, u16 out_height,
  82                 bool mem_to_mem);
  83         u8 num_fifos;
  84
  85         /* swap GFX & WB fifos */
  86         bool gfx_fifo_workaround:1;
  87
  88         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  89         bool no_framedone_tv:1;
  90
  91         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  92         bool mstandby_workaround:1;
  93
  94         bool set_max_preload:1;
  95 };
  96
  97 #define DISPC_MAX_NR_FIFOS 5
  98
  99 static struct {
 100         struct platform_device *pdev;
 101         void __iomem    *base;
 102
 103         int             ctx_loss_cnt;
 104
 105         int irq;
 106
 107         unsigned long core_clk_rate;
 108         unsigned long tv_pclk_rate;
 109
 110         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 111         /* maps which plane is using a fifo. fifo-id -> plane-id */
 112         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 113
 114         bool            ctx_valid;
 115         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 116
 117         const struct dispc_features *feat;
 118 } dispc;
 119
 120 enum omap_color_component {
 121         /* used for all color formats for OMAP3 and earlier
 122          * and for RGB and Y color component on OMAP4
 123          */
 124         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 125         /* used for UV component for
 126          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 127          * color formats on OMAP4
 128          */
 129         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 130 };
 131
 132 enum mgr_reg_fields {
 133         DISPC_MGR_FLD_ENABLE,
 134         DISPC_MGR_FLD_STNTFT,
 135         DISPC_MGR_FLD_GO,
 136         DISPC_MGR_FLD_TFTDATALINES,
 137         DISPC_MGR_FLD_STALLMODE,
 138         DISPC_MGR_FLD_TCKENABLE,
 139         DISPC_MGR_FLD_TCKSELECTION,
 140         DISPC_MGR_FLD_CPR,
 141         DISPC_MGR_FLD_FIFOHANDCHECK,
 142         /* used to maintain a count of the above fields */
 143         DISPC_MGR_FLD_NUM,
 144 };
 145
 146 static const struct {
 147         const char *name;
 148         u32 vsync_irq;
 149         u32 framedone_irq;
 150         u32 sync_lost_irq;
 151         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
 152 } mgr_desc[] = {
 153         [OMAP_DSS_CHANNEL_LCD] = {
 154                 .name           = "LCD",
 155                 .vsync_irq      = DISPC_IRQ_VSYNC,
 156                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 157                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 158                 .reg_desc       = {
 159                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 160                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 161                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 162                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 163                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 164                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 165                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 166                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 167                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 168                 },
 169         },
 170         [OMAP_DSS_CHANNEL_DIGIT] = {
 171                 .name           = "DIGIT",
 172                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 173                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 174                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 175                 .reg_desc       = {
 176                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 177                         [DISPC_MGR_FLD_STNTFT]          = { },
 178                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 179                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 180                         [DISPC_MGR_FLD_STALLMODE]       = { },
 181                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 182                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 183                         [DISPC_MGR_FLD_CPR]             = { },
 184                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 185                 },
 186         },
 187         [OMAP_DSS_CHANNEL_LCD2] = {
 188                 .name           = "LCD2",
 189                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 190                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 191                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 192                 .reg_desc       = {
 193                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 194                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 195                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 196                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 197                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 198                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 199                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 200                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 201                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 202                 },
 203         },
 204         [OMAP_DSS_CHANNEL_LCD3] = {
 205                 .name           = "LCD3",
 206                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 207                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 208                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 209                 .reg_desc       = {
 210                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 211                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 212                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 213                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 214                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 215                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 216                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 217                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 218                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 219                 },
 220         },
 221 };
 222
 223 struct color_conv_coef {
 224         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 225         int full_range;
 226 };
 227
 228 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 229 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 230
 231 static inline void dispc_write_reg(const u16 idx, u32 val)
 232 {
 233         __raw_writel(val, dispc.base + idx);
 234 }
 235
 236 static inline u32 dispc_read_reg(const u16 idx)
 237 {
 238         return __raw_readl(dispc.base + idx);
 239 }
 240
 241 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 242 {
 243         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 244         return REG_GET(rfld.reg, rfld.high, rfld.low);
 245 }
 246
 247 static void mgr_fld_write(enum omap_channel channel,
 248                                         enum mgr_reg_fields regfld, int val) {
 249         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 250         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 251 }
 252
 253 #define SR(reg) \
 254         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 255 #define RR(reg) \
 256         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 257
 258 static void dispc_save_context(void)
 259 {
 260         int i, j;
 261
 262         DSSDBG("dispc_save_context\n");
 263
 264         SR(IRQENABLE);
 265         SR(CONTROL);
 266         SR(CONFIG);
 267         SR(LINE_NUMBER);
 268         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 269                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 270                 SR(GLOBAL_ALPHA);
 271         if (dss_has_feature(FEAT_MGR_LCD2)) {
 272                 SR(CONTROL2);
 273                 SR(CONFIG2);
 274         }
 275         if (dss_has_feature(FEAT_MGR_LCD3)) {
 276                 SR(CONTROL3);
 277                 SR(CONFIG3);
 278         }
 279
 280         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 281                 SR(DEFAULT_COLOR(i));
 282                 SR(TRANS_COLOR(i));
 283                 SR(SIZE_MGR(i));
 284                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 285                         continue;
 286                 SR(TIMING_H(i));
 287                 SR(TIMING_V(i));
 288                 SR(POL_FREQ(i));
 289                 SR(DIVISORo(i));
 290
 291                 SR(DATA_CYCLE1(i));
 292                 SR(DATA_CYCLE2(i));
 293                 SR(DATA_CYCLE3(i));
 294
 295                 if (dss_has_feature(FEAT_CPR)) {
 296                         SR(CPR_COEF_R(i));
 297                         SR(CPR_COEF_G(i));
 298                         SR(CPR_COEF_B(i));
 299                 }
 300         }
 301
 302         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 303                 SR(OVL_BA0(i));
 304                 SR(OVL_BA1(i));
 305                 SR(OVL_POSITION(i));
 306                 SR(OVL_SIZE(i));
 307                 SR(OVL_ATTRIBUTES(i));
 308                 SR(OVL_FIFO_THRESHOLD(i));
 309                 SR(OVL_ROW_INC(i));
 310                 SR(OVL_PIXEL_INC(i));
 311                 if (dss_has_feature(FEAT_PRELOAD))
 312                         SR(OVL_PRELOAD(i));
 313                 if (i == OMAP_DSS_GFX) {
 314                         SR(OVL_WINDOW_SKIP(i));
 315                         SR(OVL_TABLE_BA(i));
 316                         continue;
 317                 }
 318                 SR(OVL_FIR(i));
 319                 SR(OVL_PICTURE_SIZE(i));
 320                 SR(OVL_ACCU0(i));
 321                 SR(OVL_ACCU1(i));
 322
 323                 for (j = 0; j < 8; j++)
 324                         SR(OVL_FIR_COEF_H(i, j));
 325
 326                 for (j = 0; j < 8; j++)
 327                         SR(OVL_FIR_COEF_HV(i, j));
 328
 329                 for (j = 0; j < 5; j++)
 330                         SR(OVL_CONV_COEF(i, j));
 331
 332                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 333                         for (j = 0; j < 8; j++)
 334                                 SR(OVL_FIR_COEF_V(i, j));
 335                 }
 336
 337                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 338                         SR(OVL_BA0_UV(i));
 339                         SR(OVL_BA1_UV(i));
 340                         SR(OVL_FIR2(i));
 341                         SR(OVL_ACCU2_0(i));
 342                         SR(OVL_ACCU2_1(i));
 343
 344                         for (j = 0; j < 8; j++)
 345                                 SR(OVL_FIR_COEF_H2(i, j));
 346
 347                         for (j = 0; j < 8; j++)
 348                                 SR(OVL_FIR_COEF_HV2(i, j));
 349
 350                         for (j = 0; j < 8; j++)
 351                                 SR(OVL_FIR_COEF_V2(i, j));
 352                 }
 353                 if (dss_has_feature(FEAT_ATTR2))
 354                         SR(OVL_ATTRIBUTES2(i));
 355         }
 356
 357         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 358                 SR(DIVISOR);
 359
 360         dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
 361         dispc.ctx_valid = true;
 362
 363         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 364 }
 365
 366 static void dispc_restore_context(void)
 367 {
 368         int i, j, ctx;
 369
 370         DSSDBG("dispc_restore_context\n");
 371
 372         if (!dispc.ctx_valid)
 373                 return;
 374
 375         ctx = dss_get_ctx_loss_count();
 376
 377         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 378                 return;
 379
 380         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 381                         dispc.ctx_loss_cnt, ctx);
 382
 383         /*RR(IRQENABLE);*/
 384         /*RR(CONTROL);*/
 385         RR(CONFIG);
 386         RR(LINE_NUMBER);
 387         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 388                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 389                 RR(GLOBAL_ALPHA);
 390         if (dss_has_feature(FEAT_MGR_LCD2))
 391                 RR(CONFIG2);
 392         if (dss_has_feature(FEAT_MGR_LCD3))
 393                 RR(CONFIG3);
 394
 395         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 396                 RR(DEFAULT_COLOR(i));
 397                 RR(TRANS_COLOR(i));
 398                 RR(SIZE_MGR(i));
 399                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 400                         continue;
 401                 RR(TIMING_H(i));
 402                 RR(TIMING_V(i));
 403                 RR(POL_FREQ(i));
 404                 RR(DIVISORo(i));
 405
 406                 RR(DATA_CYCLE1(i));
 407                 RR(DATA_CYCLE2(i));
 408                 RR(DATA_CYCLE3(i));
 409
 410                 if (dss_has_feature(FEAT_CPR)) {
 411                         RR(CPR_COEF_R(i));
 412                         RR(CPR_COEF_G(i));
 413                         RR(CPR_COEF_B(i));
 414                 }
 415         }
 416
 417         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 418                 RR(OVL_BA0(i));
 419                 RR(OVL_BA1(i));
 420                 RR(OVL_POSITION(i));
 421                 RR(OVL_SIZE(i));
 422                 RR(OVL_ATTRIBUTES(i));
 423                 RR(OVL_FIFO_THRESHOLD(i));
 424                 RR(OVL_ROW_INC(i));
 425                 RR(OVL_PIXEL_INC(i));
 426                 if (dss_has_feature(FEAT_PRELOAD))
 427                         RR(OVL_PRELOAD(i));
 428                 if (i == OMAP_DSS_GFX) {
 429                         RR(OVL_WINDOW_SKIP(i));
 430                         RR(OVL_TABLE_BA(i));
 431                         continue;
 432                 }
 433                 RR(OVL_FIR(i));
 434                 RR(OVL_PICTURE_SIZE(i));
 435                 RR(OVL_ACCU0(i));
 436                 RR(OVL_ACCU1(i));
 437
 438                 for (j = 0; j < 8; j++)
 439                         RR(OVL_FIR_COEF_H(i, j));
 440
 441                 for (j = 0; j < 8; j++)
 442                         RR(OVL_FIR_COEF_HV(i, j));
 443
 444                 for (j = 0; j < 5; j++)
 445                         RR(OVL_CONV_COEF(i, j));
 446
 447                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 448                         for (j = 0; j < 8; j++)
 449                                 RR(OVL_FIR_COEF_V(i, j));
 450                 }
 451
 452                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 453                         RR(OVL_BA0_UV(i));
 454                         RR(OVL_BA1_UV(i));
 455                         RR(OVL_FIR2(i));
 456                         RR(OVL_ACCU2_0(i));
 457                         RR(OVL_ACCU2_1(i));
 458
 459                         for (j = 0; j < 8; j++)
 460                                 RR(OVL_FIR_COEF_H2(i, j));
 461
 462                         for (j = 0; j < 8; j++)
 463                                 RR(OVL_FIR_COEF_HV2(i, j));
 464
 465                         for (j = 0; j < 8; j++)
 466                                 RR(OVL_FIR_COEF_V2(i, j));
 467                 }
 468                 if (dss_has_feature(FEAT_ATTR2))
 469                         RR(OVL_ATTRIBUTES2(i));
 470         }
 471
 472         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 473                 RR(DIVISOR);
 474
 475         /* enable last, because LCD & DIGIT enable are here */
 476         RR(CONTROL);
 477         if (dss_has_feature(FEAT_MGR_LCD2))
 478                 RR(CONTROL2);
 479         if (dss_has_feature(FEAT_MGR_LCD3))
 480                 RR(CONTROL3);
 481         /* clear spurious SYNC_LOST_DIGIT interrupts */
 482         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 483
 484         /*
 485          * enable last so IRQs won't trigger before
 486          * the context is fully restored
 487          */
 488         RR(IRQENABLE);
 489
 490         DSSDBG("context restored\n");
 491 }
 492
 493 #undef SR
 494 #undef RR
 495
 496 int dispc_runtime_get(void)
 497 {
 498         int r;
 499
 500         DSSDBG("dispc_runtime_get\n");
 501
 502         r = pm_runtime_get_sync(&dispc.pdev->dev);
 503         WARN_ON(r < 0);
 504         return r < 0 ? r : 0;
 505 }
 506 EXPORT_SYMBOL(dispc_runtime_get);
 507
 508 void dispc_runtime_put(void)
 509 {
 510         int r;
 511
 512         DSSDBG("dispc_runtime_put\n");
 513
 514         r = pm_runtime_put_sync(&dispc.pdev->dev);
 515         WARN_ON(r < 0 && r != -ENOSYS);
 516 }
 517 EXPORT_SYMBOL(dispc_runtime_put);
 518
 519 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 520 {
 521         return mgr_desc[channel].vsync_irq;
 522 }
 523 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 524
 525 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 526 {
 527         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 528                 return 0;
 529
 530         return mgr_desc[channel].framedone_irq;
 531 }
 532 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 533
 534 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 535 {
 536         return mgr_desc[channel].sync_lost_irq;
 537 }
 538 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 539
 540 u32 dispc_wb_get_framedone_irq(void)
 541 {
 542         return DISPC_IRQ_FRAMEDONEWB;
 543 }
 544
 545 bool dispc_mgr_go_busy(enum omap_channel channel)
 546 {
 547         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 548 }
 549 EXPORT_SYMBOL(dispc_mgr_go_busy);
 550
 551 void dispc_mgr_go(enum omap_channel channel)
 552 {
 553         WARN_ON(dispc_mgr_is_enabled(channel) == false);
 554         WARN_ON(dispc_mgr_go_busy(channel));
 555
 556         DSSDBG("GO %s\n", mgr_desc[channel].name);
 557
 558         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 559 }
 560 EXPORT_SYMBOL(dispc_mgr_go);
 561
 562 bool dispc_wb_go_busy(void)
 563 {
 564         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 565 }
 566
 567 void dispc_wb_go(void)
 568 {
 569         enum omap_plane plane = OMAP_DSS_WB;
 570         bool enable, go;
 571
 572         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 573
 574         if (!enable)
 575                 return;
 576
 577         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 578         if (go) {
 579                 DSSERR("GO bit not down for WB\n");
 580                 return;
 581         }
 582
 583         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 584 }
 585
 586 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 587 {
 588         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 589 }
 590
 591 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 592 {
 593         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 594 }
 595
 596 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 597 {
 598         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 599 }
 600
 601 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 602 {
 603         BUG_ON(plane == OMAP_DSS_GFX);
 604
 605         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 606 }
 607
 608 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 609                 u32 value)
 610 {
 611         BUG_ON(plane == OMAP_DSS_GFX);
 612
 613         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 614 }
 615
 616 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 617 {
 618         BUG_ON(plane == OMAP_DSS_GFX);
 619
 620         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 621 }
 622
 623 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 624                                 int fir_vinc, int five_taps,
 625                                 enum omap_color_component color_comp)
 626 {
 627         const struct dispc_coef *h_coef, *v_coef;
 628         int i;
 629
 630         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 631         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 632
 633         for (i = 0; i < 8; i++) {
 634                 u32 h, hv;
 635
 636                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 637                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 638                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 639                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 640                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 641                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 642                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 643                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 644
 645                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 646                         dispc_ovl_write_firh_reg(plane, i, h);
 647                         dispc_ovl_write_firhv_reg(plane, i, hv);
 648                 } else {
 649                         dispc_ovl_write_firh2_reg(plane, i, h);
 650                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 651                 }
 652
 653         }
 654
 655         if (five_taps) {
 656                 for (i = 0; i < 8; i++) {
 657                         u32 v;
 658                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 659                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 660                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 661                                 dispc_ovl_write_firv_reg(plane, i, v);
 662                         else
 663                                 dispc_ovl_write_firv2_reg(plane, i, v);
 664                 }
 665         }
 666 }
 667
 668
 669 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 670                 const struct color_conv_coef *ct)
 671 {
 672 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 673
 674         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 675         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 676         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 677         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 678         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 679
 680         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 681
 682 #undef CVAL
 683 }
 684
 685 static void dispc_setup_color_conv_coef(void)
 686 {
 687         int i;
 688         int num_ovl = dss_feat_get_num_ovls();
 689         int num_wb = dss_feat_get_num_wbs();
 690         const struct color_conv_coef ctbl_bt601_5_ovl = {
 691                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 692         };
 693         const struct color_conv_coef ctbl_bt601_5_wb = {
 694                 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
 695         };
 696
 697         for (i = 1; i < num_ovl; i++)
 698                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 699
 700         for (; i < num_wb; i++)
 701                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
 702 }
 703
 704 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 705 {
 706         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 707 }
 708
 709 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 710 {
 711         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 712 }
 713
 714 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 715 {
 716         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 717 }
 718
 719 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 720 {
 721         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 722 }
 723
 724 static void dispc_ovl_set_pos(enum omap_plane plane,
 725                 enum omap_overlay_caps caps, int x, int y)
 726 {
 727         u32 val;
 728
 729         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 730                 return;
 731
 732         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 733
 734         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 735 }
 736
 737 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 738                 int height)
 739 {
 740         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 741
 742         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 743                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 744         else
 745                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 746 }
 747
 748 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 749                 int height)
 750 {
 751         u32 val;
 752
 753         BUG_ON(plane == OMAP_DSS_GFX);
 754
 755         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 756
 757         if (plane == OMAP_DSS_WB)
 758                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 759         else
 760                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 761 }
 762
 763 static void dispc_ovl_set_zorder(enum omap_plane plane,
 764                 enum omap_overlay_caps caps, u8 zorder)
 765 {
 766         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 767                 return;
 768
 769         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 770 }
 771
 772 static void dispc_ovl_enable_zorder_planes(void)
 773 {
 774         int i;
 775
 776         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 777                 return;
 778
 779         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 780                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 781 }
 782
 783 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 784                 enum omap_overlay_caps caps, bool enable)
 785 {
 786         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 787                 return;
 788
 789         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 790 }
 791
 792 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 793                 enum omap_overlay_caps caps, u8 global_alpha)
 794 {
 795         static const unsigned shifts[] = { 0, 8, 16, 24, };
 796         int shift;
 797
 798         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 799                 return;
 800
 801         shift = shifts[plane];
 802         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 803 }
 804
 805 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 806 {
 807         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 808 }
 809
 810 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 811 {
 812         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 813 }
 814
 815 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 816                 enum omap_color_mode color_mode)
 817 {
 818         u32 m = 0;
 819         if (plane != OMAP_DSS_GFX) {
 820                 switch (color_mode) {
 821                 case OMAP_DSS_COLOR_NV12:
 822                         m = 0x0; break;
 823                 case OMAP_DSS_COLOR_RGBX16:
 824                         m = 0x1; break;
 825                 case OMAP_DSS_COLOR_RGBA16:
 826                         m = 0x2; break;
 827                 case OMAP_DSS_COLOR_RGB12U:
 828                         m = 0x4; break;
 829                 case OMAP_DSS_COLOR_ARGB16:
 830                         m = 0x5; break;
 831                 case OMAP_DSS_COLOR_RGB16:
 832                         m = 0x6; break;
 833                 case OMAP_DSS_COLOR_ARGB16_1555:
 834                         m = 0x7; break;
 835                 case OMAP_DSS_COLOR_RGB24U:
 836                         m = 0x8; break;
 837                 case OMAP_DSS_COLOR_RGB24P:
 838                         m = 0x9; break;
 839                 case OMAP_DSS_COLOR_YUV2:
 840                         m = 0xa; break;
 841                 case OMAP_DSS_COLOR_UYVY:
 842                         m = 0xb; break;
 843                 case OMAP_DSS_COLOR_ARGB32:
 844                         m = 0xc; break;
 845                 case OMAP_DSS_COLOR_RGBA32:
 846                         m = 0xd; break;
 847                 case OMAP_DSS_COLOR_RGBX32:
 848                         m = 0xe; break;
 849                 case OMAP_DSS_COLOR_XRGB16_1555:
 850                         m = 0xf; break;
 851                 default:
 852                         BUG(); return;
 853                 }
 854         } else {
 855                 switch (color_mode) {
 856                 case OMAP_DSS_COLOR_CLUT1:
 857                         m = 0x0; break;
 858                 case OMAP_DSS_COLOR_CLUT2:
 859                         m = 0x1; break;
 860                 case OMAP_DSS_COLOR_CLUT4:
 861                         m = 0x2; break;
 862                 case OMAP_DSS_COLOR_CLUT8:
 863                         m = 0x3; break;
 864                 case OMAP_DSS_COLOR_RGB12U:
 865                         m = 0x4; break;
 866                 case OMAP_DSS_COLOR_ARGB16:
 867                         m = 0x5; break;
 868                 case OMAP_DSS_COLOR_RGB16:
 869                         m = 0x6; break;
 870                 case OMAP_DSS_COLOR_ARGB16_1555:
 871                         m = 0x7; break;
 872                 case OMAP_DSS_COLOR_RGB24U:
 873                         m = 0x8; break;
 874                 case OMAP_DSS_COLOR_RGB24P:
 875                         m = 0x9; break;
 876                 case OMAP_DSS_COLOR_RGBX16:
 877                         m = 0xa; break;
 878                 case OMAP_DSS_COLOR_RGBA16:
 879                         m = 0xb; break;
 880                 case OMAP_DSS_COLOR_ARGB32:
 881                         m = 0xc; break;
 882                 case OMAP_DSS_COLOR_RGBA32:
 883                         m = 0xd; break;
 884                 case OMAP_DSS_COLOR_RGBX32:
 885                         m = 0xe; break;
 886                 case OMAP_DSS_COLOR_XRGB16_1555:
 887                         m = 0xf; break;
 888                 default:
 889                         BUG(); return;
 890                 }
 891         }
 892
 893         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 894 }
 895
 896 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 897                 enum omap_dss_rotation_type rotation_type)
 898 {
 899         if (dss_has_feature(FEAT_BURST_2D) == 0)
 900                 return;
 901
 902         if (rotation_type == OMAP_DSS_ROT_TILER)
 903                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 904         else
 905                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 906 }
 907
 908 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 909 {
 910         int shift;
 911         u32 val;
 912         int chan = 0, chan2 = 0;
 913
 914         switch (plane) {
 915         case OMAP_DSS_GFX:
 916                 shift = 8;
 917                 break;
 918         case OMAP_DSS_VIDEO1:
 919         case OMAP_DSS_VIDEO2:
 920         case OMAP_DSS_VIDEO3:
 921                 shift = 16;
 922                 break;
 923         default:
 924                 BUG();
 925                 return;
 926         }
 927
 928         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 929         if (dss_has_feature(FEAT_MGR_LCD2)) {
 930                 switch (channel) {
 931                 case OMAP_DSS_CHANNEL_LCD:
 932                         chan = 0;
 933                         chan2 = 0;
 934                         break;
 935                 case OMAP_DSS_CHANNEL_DIGIT:
 936                         chan = 1;
 937                         chan2 = 0;
 938                         break;
 939                 case OMAP_DSS_CHANNEL_LCD2:
 940                         chan = 0;
 941                         chan2 = 1;
 942                         break;
 943                 case OMAP_DSS_CHANNEL_LCD3:
 944                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 945                                 chan = 0;
 946                                 chan2 = 2;
 947                         } else {
 948                                 BUG();
 949                                 return;
 950                         }
 951                         break;
 952                 default:
 953                         BUG();
 954                         return;
 955                 }
 956
 957                 val = FLD_MOD(val, chan, shift, shift);
 958                 val = FLD_MOD(val, chan2, 31, 30);
 959         } else {
 960                 val = FLD_MOD(val, channel, shift, shift);
 961         }
 962         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 963 }
 964 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
 965
 966 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 967 {
 968         int shift;
 969         u32 val;
 970         enum omap_channel channel;
 971
 972         switch (plane) {
 973         case OMAP_DSS_GFX:
 974                 shift = 8;
 975                 break;
 976         case OMAP_DSS_VIDEO1:
 977         case OMAP_DSS_VIDEO2:
 978         case OMAP_DSS_VIDEO3:
 979                 shift = 16;
 980                 break;
 981         default:
 982                 BUG();
 983                 return 0;
 984         }
 985
 986         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 987
 988         if (dss_has_feature(FEAT_MGR_LCD3)) {
 989                 if (FLD_GET(val, 31, 30) == 0)
 990                         channel = FLD_GET(val, shift, shift);
 991                 else if (FLD_GET(val, 31, 30) == 1)
 992                         channel = OMAP_DSS_CHANNEL_LCD2;
 993                 else
 994                         channel = OMAP_DSS_CHANNEL_LCD3;
 995         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
 996                 if (FLD_GET(val, 31, 30) == 0)
 997                         channel = FLD_GET(val, shift, shift);
 998                 else
 999                         channel = OMAP_DSS_CHANNEL_LCD2;
1000         } else {
1001                 channel = FLD_GET(val, shift, shift);
1002         }
1003
1004         return channel;
1005 }
1006
1007 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1008 {
1009         enum omap_plane plane = OMAP_DSS_WB;
1010
1011         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1012 }
1013
1014 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1015                 enum omap_burst_size burst_size)
1016 {
1017         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1018         int shift;
1019
1020         shift = shifts[plane];
1021         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1022 }
1023
1024 static void dispc_configure_burst_sizes(void)
1025 {
1026         int i;
1027         const int burst_size = BURST_SIZE_X8;
1028
1029         /* Configure burst size always to maximum size */
1030         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1031                 dispc_ovl_set_burst_size(i, burst_size);
1032 }
1033
1034 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1035 {
1036         unsigned unit = dss_feat_get_burst_size_unit();
1037         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1038         return unit * 8;
1039 }
1040
1041 void dispc_enable_gamma_table(bool enable)
1042 {
1043         /*
1044          * This is partially implemented to support only disabling of
1045          * the gamma table.
1046          */
1047         if (enable) {
1048                 DSSWARN("Gamma table enabling for TV not yet supported");
1049                 return;
1050         }
1051
1052         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1053 }
1054
1055 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1056 {
1057         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1058                 return;
1059
1060         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1061 }
1062
1063 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1064                 const struct omap_dss_cpr_coefs *coefs)
1065 {
1066         u32 coef_r, coef_g, coef_b;
1067
1068         if (!dss_mgr_is_lcd(channel))
1069                 return;
1070
1071         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1072                 FLD_VAL(coefs->rb, 9, 0);
1073         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1074                 FLD_VAL(coefs->gb, 9, 0);
1075         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1076                 FLD_VAL(coefs->bb, 9, 0);
1077
1078         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1079         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1080         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1081 }
1082
1083 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1084 {
1085         u32 val;
1086
1087         BUG_ON(plane == OMAP_DSS_GFX);
1088
1089         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1090         val = FLD_MOD(val, enable, 9, 9);
1091         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1092 }
1093
1094 static void dispc_ovl_enable_replication(enum omap_plane plane,
1095                 enum omap_overlay_caps caps, bool enable)
1096 {
1097         static const unsigned shifts[] = { 5, 10, 10, 10 };
1098         int shift;
1099
1100         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1101                 return;
1102
1103         shift = shifts[plane];
1104         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1105 }
1106
1107 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1108                 u16 height)
1109 {
1110         u32 val;
1111
1112         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1113                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1114
1115         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1116 }
1117
1118 static void dispc_init_fifos(void)
1119 {
1120         u32 size;
1121         int fifo;
1122         u8 start, end;
1123         u32 unit;
1124
1125         unit = dss_feat_get_buffer_size_unit();
1126
1127         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1128
1129         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1130                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1131                 size *= unit;
1132                 dispc.fifo_size[fifo] = size;
1133
1134                 /*
1135                  * By default fifos are mapped directly to overlays, fifo 0 to
1136                  * ovl 0, fifo 1 to ovl 1, etc.
1137                  */
1138                 dispc.fifo_assignment[fifo] = fifo;
1139         }
1140
1141         /*
1142          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1143          * causes problems with certain use cases, like using the tiler in 2D
1144          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1145          * giving GFX plane a larger fifo. WB but should work fine with a
1146          * smaller fifo.
1147          */
1148         if (dispc.feat->gfx_fifo_workaround) {
1149                 u32 v;
1150
1151                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1152
1153                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1154                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1155                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1156                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1157
1158                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1159
1160                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1161                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1162         }
1163 }
1164
1165 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1166 {
1167         int fifo;
1168         u32 size = 0;
1169
1170         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1171                 if (dispc.fifo_assignment[fifo] == plane)
1172                         size += dispc.fifo_size[fifo];
1173         }
1174
1175         return size;
1176 }
1177
1178 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1179 {
1180         u8 hi_start, hi_end, lo_start, lo_end;
1181         u32 unit;
1182
1183         unit = dss_feat_get_buffer_size_unit();
1184
1185         WARN_ON(low % unit != 0);
1186         WARN_ON(high % unit != 0);
1187
1188         low /= unit;
1189         high /= unit;
1190
1191         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1192         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1193
1194         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1195                         plane,
1196                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1197                                 lo_start, lo_end) * unit,
1198                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1199                                 hi_start, hi_end) * unit,
1200                         low * unit, high * unit);
1201
1202         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1203                         FLD_VAL(high, hi_start, hi_end) |
1204                         FLD_VAL(low, lo_start, lo_end));
1205
1206         /*
1207          * configure the preload to the pipeline's high threhold, if HT it's too
1208          * large for the preload field, set the threshold to the maximum value
1209          * that can be held by the preload register
1210          */
1211         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1212                         plane != OMAP_DSS_WB)
1213                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1214 }
1215 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1216
1217 void dispc_enable_fifomerge(bool enable)
1218 {
1219         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1220                 WARN_ON(enable);
1221                 return;
1222         }
1223
1224         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1225         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1226 }
1227
1228 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1229                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1230                 bool manual_update)
1231 {
1232         /*
1233          * All sizes are in bytes. Both the buffer and burst are made of
1234          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1235          */
1236
1237         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1238         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1239         int i;
1240
1241         burst_size = dispc_ovl_get_burst_size(plane);
1242         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1243
1244         if (use_fifomerge) {
1245                 total_fifo_size = 0;
1246                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1247                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1248         } else {
1249                 total_fifo_size = ovl_fifo_size;
1250         }
1251
1252         /*
1253          * We use the same low threshold for both fifomerge and non-fifomerge
1254          * cases, but for fifomerge we calculate the high threshold using the
1255          * combined fifo size
1256          */
1257
1258         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1259                 *fifo_low = ovl_fifo_size - burst_size * 2;
1260                 *fifo_high = total_fifo_size - burst_size;
1261         } else if (plane == OMAP_DSS_WB) {
1262                 /*
1263                  * Most optimal configuration for writeback is to push out data
1264                  * to the interconnect the moment writeback pushes enough pixels
1265                  * in the FIFO to form a burst
1266                  */
1267                 *fifo_low = 0;
1268                 *fifo_high = burst_size;
1269         } else {
1270                 *fifo_low = ovl_fifo_size - burst_size;
1271                 *fifo_high = total_fifo_size - buf_unit;
1272         }
1273 }
1274 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1275
1276 static void dispc_ovl_set_fir(enum omap_plane plane,
1277                                 int hinc, int vinc,
1278                                 enum omap_color_component color_comp)
1279 {
1280         u32 val;
1281
1282         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1283                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1284
1285                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1286                                         &hinc_start, &hinc_end);
1287                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1288                                         &vinc_start, &vinc_end);
1289                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1290                                 FLD_VAL(hinc, hinc_start, hinc_end);
1291
1292                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1293         } else {
1294                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1295                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1296         }
1297 }
1298
1299 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1300 {
1301         u32 val;
1302         u8 hor_start, hor_end, vert_start, vert_end;
1303
1304         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1305         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1306
1307         val = FLD_VAL(vaccu, vert_start, vert_end) |
1308                         FLD_VAL(haccu, hor_start, hor_end);
1309
1310         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1311 }
1312
1313 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1314 {
1315         u32 val;
1316         u8 hor_start, hor_end, vert_start, vert_end;
1317
1318         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1319         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1320
1321         val = FLD_VAL(vaccu, vert_start, vert_end) |
1322                         FLD_VAL(haccu, hor_start, hor_end);
1323
1324         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1325 }
1326
1327 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1328                 int vaccu)
1329 {
1330         u32 val;
1331
1332         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1333         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1334 }
1335
1336 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1337                 int vaccu)
1338 {
1339         u32 val;
1340
1341         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1342         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1343 }
1344
1345 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1346                 u16 orig_width, u16 orig_height,
1347                 u16 out_width, u16 out_height,
1348                 bool five_taps, u8 rotation,
1349                 enum omap_color_component color_comp)
1350 {
1351         int fir_hinc, fir_vinc;
1352
1353         fir_hinc = 1024 * orig_width / out_width;
1354         fir_vinc = 1024 * orig_height / out_height;
1355
1356         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1357                                 color_comp);
1358         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1359 }
1360
1361 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1362                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1363                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1364 {
1365         int h_accu2_0, h_accu2_1;
1366         int v_accu2_0, v_accu2_1;
1367         int chroma_hinc, chroma_vinc;
1368         int idx;
1369
1370         struct accu {
1371                 s8 h0_m, h0_n;
1372                 s8 h1_m, h1_n;
1373                 s8 v0_m, v0_n;
1374                 s8 v1_m, v1_n;
1375         };
1376
1377         const struct accu *accu_table;
1378         const struct accu *accu_val;
1379
1380         static const struct accu accu_nv12[4] = {
1381                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1382                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1383                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1384                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1385         };
1386
1387         static const struct accu accu_nv12_ilace[4] = {
1388                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1389                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1390                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1391                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1392         };
1393
1394         static const struct accu accu_yuv[4] = {
1395                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1396                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1397                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1398                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1399         };
1400
1401         switch (rotation) {
1402         case OMAP_DSS_ROT_0:
1403                 idx = 0;
1404                 break;
1405         case OMAP_DSS_ROT_90:
1406                 idx = 1;
1407                 break;
1408         case OMAP_DSS_ROT_180:
1409                 idx = 2;
1410                 break;
1411         case OMAP_DSS_ROT_270:
1412                 idx = 3;
1413                 break;
1414         default:
1415                 BUG();
1416                 return;
1417         }
1418
1419         switch (color_mode) {
1420         case OMAP_DSS_COLOR_NV12:
1421                 if (ilace)
1422                         accu_table = accu_nv12_ilace;
1423                 else
1424                         accu_table = accu_nv12;
1425                 break;
1426         case OMAP_DSS_COLOR_YUV2:
1427         case OMAP_DSS_COLOR_UYVY:
1428                 accu_table = accu_yuv;
1429                 break;
1430         default:
1431                 BUG();
1432                 return;
1433         }
1434
1435         accu_val = &accu_table[idx];
1436
1437         chroma_hinc = 1024 * orig_width / out_width;
1438         chroma_vinc = 1024 * orig_height / out_height;
1439
1440         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1441         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1442         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1443         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1444
1445         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1446         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1447 }
1448
1449 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1450                 u16 orig_width, u16 orig_height,
1451                 u16 out_width, u16 out_height,
1452                 bool ilace, bool five_taps,
1453                 bool fieldmode, enum omap_color_mode color_mode,
1454                 u8 rotation)
1455 {
1456         int accu0 = 0;
1457         int accu1 = 0;
1458         u32 l;
1459
1460         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1461                                 out_width, out_height, five_taps,
1462                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1463         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1464
1465         /* RESIZEENABLE and VERTICALTAPS */
1466         l &= ~((0x3 << 5) | (0x1 << 21));
1467         l |= (orig_width != out_width) ? (1 << 5) : 0;
1468         l |= (orig_height != out_height) ? (1 << 6) : 0;
1469         l |= five_taps ? (1 << 21) : 0;
1470
1471         /* VRESIZECONF and HRESIZECONF */
1472         if (dss_has_feature(FEAT_RESIZECONF)) {
1473                 l &= ~(0x3 << 7);
1474                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1475                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1476         }
1477
1478         /* LINEBUFFERSPLIT */
1479         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1480                 l &= ~(0x1 << 22);
1481                 l |= five_taps ? (1 << 22) : 0;
1482         }
1483
1484         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1485
1486         /*
1487          * field 0 = even field = bottom field
1488          * field 1 = odd field = top field
1489          */
1490         if (ilace && !fieldmode) {
1491                 accu1 = 0;
1492                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1493                 if (accu0 >= 1024/2) {
1494                         accu1 = 1024/2;
1495                         accu0 -= accu1;
1496                 }
1497         }
1498
1499         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1500         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1501 }
1502
1503 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1504                 u16 orig_width, u16 orig_height,
1505                 u16 out_width, u16 out_height,
1506                 bool ilace, bool five_taps,
1507                 bool fieldmode, enum omap_color_mode color_mode,
1508                 u8 rotation)
1509 {
1510         int scale_x = out_width != orig_width;
1511         int scale_y = out_height != orig_height;
1512         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1513
1514         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1515                 return;
1516         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1517                         color_mode != OMAP_DSS_COLOR_UYVY &&
1518                         color_mode != OMAP_DSS_COLOR_NV12)) {
1519                 /* reset chroma resampling for RGB formats  */
1520                 if (plane != OMAP_DSS_WB)
1521                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1522                 return;
1523         }
1524
1525         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1526                         out_height, ilace, color_mode, rotation);
1527
1528         switch (color_mode) {
1529         case OMAP_DSS_COLOR_NV12:
1530                 if (chroma_upscale) {
1531                         /* UV is subsampled by 2 horizontally and vertically */
1532                         orig_height >>= 1;
1533                         orig_width >>= 1;
1534                 } else {
1535                         /* UV is downsampled by 2 horizontally and vertically */
1536                         orig_height <<= 1;
1537                         orig_width <<= 1;
1538                 }
1539
1540                 break;
1541         case OMAP_DSS_COLOR_YUV2:
1542         case OMAP_DSS_COLOR_UYVY:
1543                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1544                 if (rotation == OMAP_DSS_ROT_0 ||
1545                                 rotation == OMAP_DSS_ROT_180) {
1546                         if (chroma_upscale)
1547                                 /* UV is subsampled by 2 horizontally */
1548                                 orig_width >>= 1;
1549                         else
1550                                 /* UV is downsampled by 2 horizontally */
1551                                 orig_width <<= 1;
1552                 }
1553
1554                 /* must use FIR for YUV422 if rotated */
1555                 if (rotation != OMAP_DSS_ROT_0)
1556                         scale_x = scale_y = true;
1557
1558                 break;
1559         default:
1560                 BUG();
1561                 return;
1562         }
1563
1564         if (out_width != orig_width)
1565                 scale_x = true;
1566         if (out_height != orig_height)
1567                 scale_y = true;
1568
1569         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1570                         out_width, out_height, five_taps,
1571                                 rotation, DISPC_COLOR_COMPONENT_UV);
1572
1573         if (plane != OMAP_DSS_WB)
1574                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1575                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1576
1577         /* set H scaling */
1578         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1579         /* set V scaling */
1580         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1581 }
1582
1583 static void dispc_ovl_set_scaling(enum omap_plane plane,
1584                 u16 orig_width, u16 orig_height,
1585                 u16 out_width, u16 out_height,
1586                 bool ilace, bool five_taps,
1587                 bool fieldmode, enum omap_color_mode color_mode,
1588                 u8 rotation)
1589 {
1590         BUG_ON(plane == OMAP_DSS_GFX);
1591
1592         dispc_ovl_set_scaling_common(plane,
1593                         orig_width, orig_height,
1594                         out_width, out_height,
1595                         ilace, five_taps,
1596                         fieldmode, color_mode,
1597                         rotation);
1598
1599         dispc_ovl_set_scaling_uv(plane,
1600                 orig_width, orig_height,
1601                 out_width, out_height,
1602                 ilace, five_taps,
1603                 fieldmode, color_mode,
1604                 rotation);
1605 }
1606
1607 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1608                 enum omap_dss_rotation_type rotation_type,
1609                 bool mirroring, enum omap_color_mode color_mode)
1610 {
1611         bool row_repeat = false;
1612         int vidrot = 0;
1613
1614         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1615                         color_mode == OMAP_DSS_COLOR_UYVY) {
1616
1617                 if (mirroring) {
1618                         switch (rotation) {
1619                         case OMAP_DSS_ROT_0:
1620                                 vidrot = 2;
1621                                 break;
1622                         case OMAP_DSS_ROT_90:
1623                                 vidrot = 1;
1624                                 break;
1625                         case OMAP_DSS_ROT_180:
1626                                 vidrot = 0;
1627                                 break;
1628                         case OMAP_DSS_ROT_270:
1629                                 vidrot = 3;
1630                                 break;
1631                         }
1632                 } else {
1633                         switch (rotation) {
1634                         case OMAP_DSS_ROT_0:
1635                                 vidrot = 0;
1636                                 break;
1637                         case OMAP_DSS_ROT_90:
1638                                 vidrot = 1;
1639                                 break;
1640                         case OMAP_DSS_ROT_180:
1641                                 vidrot = 2;
1642                                 break;
1643                         case OMAP_DSS_ROT_270:
1644                                 vidrot = 3;
1645                                 break;
1646                         }
1647                 }
1648
1649                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1650                         row_repeat = true;
1651                 else
1652                         row_repeat = false;
1653         }
1654
1655         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1656         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1657                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1658                         row_repeat ? 1 : 0, 18, 18);
1659
1660         if (color_mode == OMAP_DSS_COLOR_NV12) {
1661                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1662                                         (rotation == OMAP_DSS_ROT_0 ||
1663                                         rotation == OMAP_DSS_ROT_180);
1664                 /* DOUBLESTRIDE */
1665                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1666         }
1667
1668 }
1669
1670 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1671 {
1672         switch (color_mode) {
1673         case OMAP_DSS_COLOR_CLUT1:
1674                 return 1;
1675         case OMAP_DSS_COLOR_CLUT2:
1676                 return 2;
1677         case OMAP_DSS_COLOR_CLUT4:
1678                 return 4;
1679         case OMAP_DSS_COLOR_CLUT8:
1680         case OMAP_DSS_COLOR_NV12:
1681                 return 8;
1682         case OMAP_DSS_COLOR_RGB12U:
1683         case OMAP_DSS_COLOR_RGB16:
1684         case OMAP_DSS_COLOR_ARGB16:
1685         case OMAP_DSS_COLOR_YUV2:
1686         case OMAP_DSS_COLOR_UYVY:
1687         case OMAP_DSS_COLOR_RGBA16:
1688         case OMAP_DSS_COLOR_RGBX16:
1689         case OMAP_DSS_COLOR_ARGB16_1555:
1690         case OMAP_DSS_COLOR_XRGB16_1555:
1691                 return 16;
1692         case OMAP_DSS_COLOR_RGB24P:
1693                 return 24;
1694         case OMAP_DSS_COLOR_RGB24U:
1695         case OMAP_DSS_COLOR_ARGB32:
1696         case OMAP_DSS_COLOR_RGBA32:
1697         case OMAP_DSS_COLOR_RGBX32:
1698                 return 32;
1699         default:
1700                 BUG();
1701                 return 0;
1702         }
1703 }
1704
1705 static s32 pixinc(int pixels, u8 ps)
1706 {
1707         if (pixels == 1)
1708                 return 1;
1709         else if (pixels > 1)
1710                 return 1 + (pixels - 1) * ps;
1711         else if (pixels < 0)
1712                 return 1 - (-pixels + 1) * ps;
1713         else
1714                 BUG();
1715                 return 0;
1716 }
1717
1718 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1719                 u16 screen_width,
1720                 u16 width, u16 height,
1721                 enum omap_color_mode color_mode, bool fieldmode,
1722                 unsigned int field_offset,
1723                 unsigned *offset0, unsigned *offset1,
1724                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1725 {
1726         u8 ps;
1727
1728         /* FIXME CLUT formats */
1729         switch (color_mode) {
1730         case OMAP_DSS_COLOR_CLUT1:
1731         case OMAP_DSS_COLOR_CLUT2:
1732         case OMAP_DSS_COLOR_CLUT4:
1733         case OMAP_DSS_COLOR_CLUT8:
1734                 BUG();
1735                 return;
1736         case OMAP_DSS_COLOR_YUV2:
1737         case OMAP_DSS_COLOR_UYVY:
1738                 ps = 4;
1739                 break;
1740         default:
1741                 ps = color_mode_to_bpp(color_mode) / 8;
1742                 break;
1743         }
1744
1745         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1746                         width, height);
1747
1748         /*
1749          * field 0 = even field = bottom field
1750          * field 1 = odd field = top field
1751          */
1752         switch (rotation + mirror * 4) {
1753         case OMAP_DSS_ROT_0:
1754         case OMAP_DSS_ROT_180:
1755                 /*
1756                  * If the pixel format is YUV or UYVY divide the width
1757                  * of the image by 2 for 0 and 180 degree rotation.
1758                  */
1759                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1760                         color_mode == OMAP_DSS_COLOR_UYVY)
1761                         width = width >> 1;
1762         case OMAP_DSS_ROT_90:
1763         case OMAP_DSS_ROT_270:
1764                 *offset1 = 0;
1765                 if (field_offset)
1766                         *offset0 = field_offset * screen_width * ps;
1767                 else
1768                         *offset0 = 0;
1769
1770                 *row_inc = pixinc(1 +
1771                         (y_predecim * screen_width - x_predecim * width) +
1772                         (fieldmode ? screen_width : 0), ps);
1773                 *pix_inc = pixinc(x_predecim, ps);
1774                 break;
1775
1776         case OMAP_DSS_ROT_0 + 4:
1777         case OMAP_DSS_ROT_180 + 4:
1778                 /* If the pixel format is YUV or UYVY divide the width
1779                  * of the image by 2  for 0 degree and 180 degree
1780                  */
1781                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1782                         color_mode == OMAP_DSS_COLOR_UYVY)
1783                         width = width >> 1;
1784         case OMAP_DSS_ROT_90 + 4:
1785         case OMAP_DSS_ROT_270 + 4:
1786                 *offset1 = 0;
1787                 if (field_offset)
1788                         *offset0 = field_offset * screen_width * ps;
1789                 else
1790                         *offset0 = 0;
1791                 *row_inc = pixinc(1 -
1792                         (y_predecim * screen_width + x_predecim * width) -
1793                         (fieldmode ? screen_width : 0), ps);
1794                 *pix_inc = pixinc(x_predecim, ps);
1795                 break;
1796
1797         default:
1798                 BUG();
1799                 return;
1800         }
1801 }
1802
1803 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1804                 u16 screen_width,
1805                 u16 width, u16 height,
1806                 enum omap_color_mode color_mode, bool fieldmode,
1807                 unsigned int field_offset,
1808                 unsigned *offset0, unsigned *offset1,
1809                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1810 {
1811         u8 ps;
1812         u16 fbw, fbh;
1813
1814         /* FIXME CLUT formats */
1815         switch (color_mode) {
1816         case OMAP_DSS_COLOR_CLUT1:
1817         case OMAP_DSS_COLOR_CLUT2:
1818         case OMAP_DSS_COLOR_CLUT4:
1819         case OMAP_DSS_COLOR_CLUT8:
1820                 BUG();
1821                 return;
1822         default:
1823                 ps = color_mode_to_bpp(color_mode) / 8;
1824                 break;
1825         }
1826
1827         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1828                         width, height);
1829
1830         /* width & height are overlay sizes, convert to fb sizes */
1831
1832         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1833                 fbw = width;
1834                 fbh = height;
1835         } else {
1836                 fbw = height;
1837                 fbh = width;
1838         }
1839
1840         /*
1841          * field 0 = even field = bottom field
1842          * field 1 = odd field = top field
1843          */
1844         switch (rotation + mirror * 4) {
1845         case OMAP_DSS_ROT_0:
1846                 *offset1 = 0;
1847                 if (field_offset)
1848                         *offset0 = *offset1 + field_offset * screen_width * ps;
1849                 else
1850                         *offset0 = *offset1;
1851                 *row_inc = pixinc(1 +
1852                         (y_predecim * screen_width - fbw * x_predecim) +
1853                         (fieldmode ? screen_width : 0), ps);
1854                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1855                         color_mode == OMAP_DSS_COLOR_UYVY)
1856                         *pix_inc = pixinc(x_predecim, 2 * ps);
1857                 else
1858                         *pix_inc = pixinc(x_predecim, ps);
1859                 break;
1860         case OMAP_DSS_ROT_90:
1861                 *offset1 = screen_width * (fbh - 1) * ps;
1862                 if (field_offset)
1863                         *offset0 = *offset1 + field_offset * ps;
1864                 else
1865                         *offset0 = *offset1;
1866                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1867                                 y_predecim + (fieldmode ? 1 : 0), ps);
1868                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1869                 break;
1870         case OMAP_DSS_ROT_180:
1871                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1872                 if (field_offset)
1873                         *offset0 = *offset1 - field_offset * screen_width * ps;
1874                 else
1875                         *offset0 = *offset1;
1876                 *row_inc = pixinc(-1 -
1877                         (y_predecim * screen_width - fbw * x_predecim) -
1878                         (fieldmode ? screen_width : 0), ps);
1879                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1880                         color_mode == OMAP_DSS_COLOR_UYVY)
1881                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1882                 else
1883                         *pix_inc = pixinc(-x_predecim, ps);
1884                 break;
1885         case OMAP_DSS_ROT_270:
1886                 *offset1 = (fbw - 1) * ps;
1887                 if (field_offset)
1888                         *offset0 = *offset1 - field_offset * ps;
1889                 else
1890                         *offset0 = *offset1;
1891                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1892                                 y_predecim - (fieldmode ? 1 : 0), ps);
1893                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1894                 break;
1895
1896         /* mirroring */
1897         case OMAP_DSS_ROT_0 + 4:
1898                 *offset1 = (fbw - 1) * ps;
1899                 if (field_offset)
1900                         *offset0 = *offset1 + field_offset * screen_width * ps;
1901                 else
1902                         *offset0 = *offset1;
1903                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1904                                 (fieldmode ? screen_width : 0),
1905                                 ps);
1906                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1907                         color_mode == OMAP_DSS_COLOR_UYVY)
1908                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1909                 else
1910                         *pix_inc = pixinc(-x_predecim, ps);
1911                 break;
1912
1913         case OMAP_DSS_ROT_90 + 4:
1914                 *offset1 = 0;
1915                 if (field_offset)
1916                         *offset0 = *offset1 + field_offset * ps;
1917                 else
1918                         *offset0 = *offset1;
1919                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1920                                 y_predecim + (fieldmode ? 1 : 0),
1921                                 ps);
1922                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1923                 break;
1924
1925         case OMAP_DSS_ROT_180 + 4:
1926                 *offset1 = screen_width * (fbh - 1) * ps;
1927                 if (field_offset)
1928                         *offset0 = *offset1 - field_offset * screen_width * ps;
1929                 else
1930                         *offset0 = *offset1;
1931                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1932                                 (fieldmode ? screen_width : 0),
1933                                 ps);
1934                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1935                         color_mode == OMAP_DSS_COLOR_UYVY)
1936                         *pix_inc = pixinc(x_predecim, 2 * ps);
1937                 else
1938                         *pix_inc = pixinc(x_predecim, ps);
1939                 break;
1940
1941         case OMAP_DSS_ROT_270 + 4:
1942                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1943                 if (field_offset)
1944                         *offset0 = *offset1 - field_offset * ps;
1945                 else
1946                         *offset0 = *offset1;
1947                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1948                                 y_predecim - (fieldmode ? 1 : 0),
1949                                 ps);
1950                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1951                 break;
1952
1953         default:
1954                 BUG();
1955                 return;
1956         }
1957 }
1958
1959 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1960                 enum omap_color_mode color_mode, bool fieldmode,
1961                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1962                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1963 {
1964         u8 ps;
1965
1966         switch (color_mode) {
1967         case OMAP_DSS_COLOR_CLUT1:
1968         case OMAP_DSS_COLOR_CLUT2:
1969         case OMAP_DSS_COLOR_CLUT4:
1970         case OMAP_DSS_COLOR_CLUT8:
1971                 BUG();
1972                 return;
1973         default:
1974                 ps = color_mode_to_bpp(color_mode) / 8;
1975                 break;
1976         }
1977
1978         DSSDBG("scrw %d, width %d\n", screen_width, width);
1979
1980         /*
1981          * field 0 = even field = bottom field
1982          * field 1 = odd field = top field
1983          */
1984         *offset1 = 0;
1985         if (field_offset)
1986                 *offset0 = *offset1 + field_offset * screen_width * ps;
1987         else
1988                 *offset0 = *offset1;
1989         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1990                         (fieldmode ? screen_width : 0), ps);
1991         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1992                 color_mode == OMAP_DSS_COLOR_UYVY)
1993                 *pix_inc = pixinc(x_predecim, 2 * ps);
1994         else
1995                 *pix_inc = pixinc(x_predecim, ps);
1996 }
1997
1998 /*
1999  * This function is used to avoid synclosts in OMAP3, because of some
2000  * undocumented horizontal position and timing related limitations.
2001  */
2002 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2003                 const struct omap_video_timings *t, u16 pos_x,
2004                 u16 width, u16 height, u16 out_width, u16 out_height,
2005                 bool five_taps)
2006 {
2007         const int ds = DIV_ROUND_UP(height, out_height);
2008         unsigned long nonactive;
2009         static const u8 limits[3] = { 8, 10, 20 };
2010         u64 val, blank;
2011         int i;
2012
2013         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2014
2015         i = 0;
2016         if (out_height < height)
2017                 i++;
2018         if (out_width < width)
2019                 i++;
2020         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2021         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2022         if (blank <= limits[i])
2023                 return -EINVAL;
2024
2025         /* FIXME add checks for 3-tap filter once the limitations are known */
2026         if (!five_taps)
2027                 return 0;
2028
2029         /*
2030          * Pixel data should be prepared before visible display point starts.
2031          * So, atleast DS-2 lines must have already been fetched by DISPC
2032          * during nonactive - pos_x period.
2033          */
2034         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2035         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2036                 val, max(0, ds - 2) * width);
2037         if (val < max(0, ds - 2) * width)
2038                 return -EINVAL;
2039
2040         /*
2041          * All lines need to be refilled during the nonactive period of which
2042          * only one line can be loaded during the active period. So, atleast
2043          * DS - 1 lines should be loaded during nonactive period.
2044          */
2045         val =  div_u64((u64)nonactive * lclk, pclk);
2046         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2047                 val, max(0, ds - 1) * width);
2048         if (val < max(0, ds - 1) * width)
2049                 return -EINVAL;
2050
2051         return 0;
2052 }
2053
2054 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2055                 const struct omap_video_timings *mgr_timings, u16 width,
2056                 u16 height, u16 out_width, u16 out_height,
2057                 enum omap_color_mode color_mode)
2058 {
2059         u32 core_clk = 0;
2060         u64 tmp;
2061
2062         if (height <= out_height && width <= out_width)
2063                 return (unsigned long) pclk;
2064
2065         if (height > out_height) {
2066                 unsigned int ppl = mgr_timings->x_res;
2067
2068                 tmp = pclk * height * out_width;
2069                 do_div(tmp, 2 * out_height * ppl);
2070                 core_clk = tmp;
2071
2072                 if (height > 2 * out_height) {
2073                         if (ppl == out_width)
2074                                 return 0;
2075
2076                         tmp = pclk * (height - 2 * out_height) * out_width;
2077                         do_div(tmp, 2 * out_height * (ppl - out_width));
2078                         core_clk = max_t(u32, core_clk, tmp);
2079                 }
2080         }
2081
2082         if (width > out_width) {
2083                 tmp = pclk * width;
2084                 do_div(tmp, out_width);
2085                 core_clk = max_t(u32, core_clk, tmp);
2086
2087                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2088                         core_clk <<= 1;
2089         }
2090
2091         return core_clk;
2092 }
2093
2094 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2095                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2096 {
2097         if (height > out_height && width > out_width)
2098                 return pclk * 4;
2099         else
2100                 return pclk * 2;
2101 }
2102
2103 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2104                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2105 {
2106         unsigned int hf, vf;
2107
2108         /*
2109          * FIXME how to determine the 'A' factor
2110          * for the no downscaling case ?
2111          */
2112
2113         if (width > 3 * out_width)
2114                 hf = 4;
2115         else if (width > 2 * out_width)
2116                 hf = 3;
2117         else if (width > out_width)
2118                 hf = 2;
2119         else
2120                 hf = 1;
2121         if (height > out_height)
2122                 vf = 2;
2123         else
2124                 vf = 1;
2125
2126         return pclk * vf * hf;
2127 }
2128
2129 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2130                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2131 {
2132         /*
2133          * If the overlay/writeback is in mem to mem mode, there are no
2134          * downscaling limitations with respect to pixel clock, return 1 as
2135          * required core clock to represent that we have sufficient enough
2136          * core clock to do maximum downscaling
2137          */
2138         if (mem_to_mem)
2139                 return 1;
2140
2141         if (width > out_width)
2142                 return DIV_ROUND_UP(pclk, out_width) * width;
2143         else
2144                 return pclk;
2145 }
2146
2147 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2148                 const struct omap_video_timings *mgr_timings,
2149                 u16 width, u16 height, u16 out_width, u16 out_height,
2150                 enum omap_color_mode color_mode, bool *five_taps,
2151                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2152                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2153 {
2154         int error;
2155         u16 in_width, in_height;
2156         int min_factor = min(*decim_x, *decim_y);
2157         const int maxsinglelinewidth =
2158                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2159
2160         *five_taps = false;
2161
2162         do {
2163                 in_height = height / *decim_y;
2164                 in_width = width / *decim_x;
2165                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2166                                 in_height, out_width, out_height, mem_to_mem);
2167                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2168                         *core_clk > dispc_core_clk_rate());
2169                 if (error) {
2170                         if (*decim_x == *decim_y) {
2171                                 *decim_x = min_factor;
2172                                 ++*decim_y;
2173                         } else {
2174                                 swap(*decim_x, *decim_y);
2175                                 if (*decim_x < *decim_y)
2176                                         ++*decim_x;
2177                         }
2178                 }
2179         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2180
2181         if (in_width > maxsinglelinewidth) {
2182                 DSSERR("Cannot scale max input width exceeded");
2183                 return -EINVAL;
2184         }
2185         return 0;
2186 }
2187
2188 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2189                 const struct omap_video_timings *mgr_timings,
2190                 u16 width, u16 height, u16 out_width, u16 out_height,
2191                 enum omap_color_mode color_mode, bool *five_taps,
2192                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2193                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2194 {
2195         int error;
2196         u16 in_width, in_height;
2197         int min_factor = min(*decim_x, *decim_y);
2198         const int maxsinglelinewidth =
2199                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2200
2201         do {
2202                 in_height = height / *decim_y;
2203                 in_width = width / *decim_x;
2204                 *five_taps = in_height > out_height;
2205
2206                 if (in_width > maxsinglelinewidth)
2207                         if (in_height > out_height &&
2208                                                 in_height < out_height * 2)
2209                                 *five_taps = false;
2210 again:
2211                 if (*five_taps)
2212                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2213                                                 in_width, in_height, out_width,
2214                                                 out_height, color_mode);
2215                 else
2216                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2217                                         in_height, out_width, out_height,
2218                                         mem_to_mem);
2219
2220                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2221                                 pos_x, in_width, in_height, out_width,
2222                                 out_height, *five_taps);
2223                 if (error && *five_taps) {
2224                         *five_taps = false;
2225                         goto again;
2226                 }
2227
2228                 error = (error || in_width > maxsinglelinewidth * 2 ||
2229                         (in_width > maxsinglelinewidth && *five_taps) ||
2230                         !*core_clk || *core_clk > dispc_core_clk_rate());
2231                 if (error) {
2232                         if (*decim_x == *decim_y) {
2233                                 *decim_x = min_factor;
2234                                 ++*decim_y;
2235                         } else {
2236                                 swap(*decim_x, *decim_y);
2237                                 if (*decim_x < *decim_y)
2238                                         ++*decim_x;
2239                         }
2240                 }
2241         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2242
2243         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2244                                 height, out_width, out_height, *five_taps)) {
2245                         DSSERR("horizontal timing too tight\n");
2246                         return -EINVAL;
2247         }
2248
2249         if (in_width > (maxsinglelinewidth * 2)) {
2250                 DSSERR("Cannot setup scaling");
2251                 DSSERR("width exceeds maximum width possible");
2252                 return -EINVAL;
2253         }
2254
2255         if (in_width > maxsinglelinewidth && *five_taps) {
2256                 DSSERR("cannot setup scaling with five taps");
2257                 return -EINVAL;
2258         }
2259         return 0;
2260 }
2261
2262 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2263                 const struct omap_video_timings *mgr_timings,
2264                 u16 width, u16 height, u16 out_width, u16 out_height,
2265                 enum omap_color_mode color_mode, bool *five_taps,
2266                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2267                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2268 {
2269         u16 in_width, in_width_max;
2270         int decim_x_min = *decim_x;
2271         u16 in_height = height / *decim_y;
2272         const int maxsinglelinewidth =
2273                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2274         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2275
2276         if (mem_to_mem) {
2277                 in_width_max = out_width * maxdownscale;
2278         } else {
2279                 in_width_max = dispc_core_clk_rate() /
2280                                         DIV_ROUND_UP(pclk, out_width);
2281         }
2282
2283         *decim_x = DIV_ROUND_UP(width, in_width_max);
2284
2285         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2286         if (*decim_x > *x_predecim)
2287                 return -EINVAL;
2288
2289         do {
2290                 in_width = width / *decim_x;
2291         } while (*decim_x <= *x_predecim &&
2292                         in_width > maxsinglelinewidth && ++*decim_x);
2293
2294         if (in_width > maxsinglelinewidth) {
2295                 DSSERR("Cannot scale width exceeds max line width");
2296                 return -EINVAL;
2297         }
2298
2299         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2300                                 out_width, out_height, mem_to_mem);
2301         return 0;
2302 }
2303
2304 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2305                 enum omap_overlay_caps caps,
2306                 const struct omap_video_timings *mgr_timings,
2307                 u16 width, u16 height, u16 out_width, u16 out_height,
2308                 enum omap_color_mode color_mode, bool *five_taps,
2309                 int *x_predecim, int *y_predecim, u16 pos_x,
2310                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2311 {
2312         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2313         const int max_decim_limit = 16;
2314         unsigned long core_clk = 0;
2315         int decim_x, decim_y, ret;
2316
2317         if (width == out_width && height == out_height)
2318                 return 0;
2319
2320         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2321                 return -EINVAL;
2322
2323         if (mem_to_mem) {
2324                 *x_predecim = *y_predecim = 1;
2325         } else {
2326                 *x_predecim = max_decim_limit;
2327                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2328                                 dss_has_feature(FEAT_BURST_2D)) ?
2329                                 2 : max_decim_limit;
2330         }
2331
2332         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2333             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2334             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2335             color_mode == OMAP_DSS_COLOR_CLUT8) {
2336                 *x_predecim = 1;
2337                 *y_predecim = 1;
2338                 *five_taps = false;
2339                 return 0;
2340         }
2341
2342         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2343         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2344
2345         if (decim_x > *x_predecim || out_width > width * 8)
2346                 return -EINVAL;
2347
2348         if (decim_y > *y_predecim || out_height > height * 8)
2349                 return -EINVAL;
2350
2351         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2352                 out_width, out_height, color_mode, five_taps,
2353                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2354                 mem_to_mem);
2355         if (ret)
2356                 return ret;
2357
2358         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2359         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2360
2361         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2362                 DSSERR("failed to set up scaling, "
2363                         "required core clk rate = %lu Hz, "
2364                         "current core clk rate = %lu Hz\n",
2365                         core_clk, dispc_core_clk_rate());
2366                 return -EINVAL;
2367         }
2368
2369         *x_predecim = decim_x;
2370         *y_predecim = decim_y;
2371         return 0;
2372 }
2373
2374 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2375                 const struct omap_overlay_info *oi,
2376                 const struct omap_video_timings *timings,
2377                 int *x_predecim, int *y_predecim)
2378 {
2379         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2380         bool five_taps = true;
2381         bool fieldmode = false;
2382         u16 in_height = oi->height;
2383         u16 in_width = oi->width;
2384         bool ilace = timings->interlace;
2385         u16 out_width, out_height;
2386         int pos_x = oi->pos_x;
2387         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2388         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2389
2390         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2391         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2392
2393         if (ilace && oi->height == out_height)
2394                 fieldmode = true;
2395
2396         if (ilace) {
2397                 if (fieldmode)
2398                         in_height /= 2;
2399                 out_height /= 2;
2400
2401                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2402                                 in_height, out_height);
2403         }
2404
2405         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2406                 return -EINVAL;
2407
2408         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2409                         in_height, out_width, out_height, oi->color_mode,
2410                         &five_taps, x_predecim, y_predecim, pos_x,
2411                         oi->rotation_type, false);
2412 }
2413 EXPORT_SYMBOL(dispc_ovl_check);
2414
2415 static int dispc_ovl_setup_common(enum omap_plane plane,
2416                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2417                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2418                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2419                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2420                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2421                 bool replication, const struct omap_video_timings *mgr_timings,
2422                 bool mem_to_mem)
2423 {
2424         bool five_taps = true;
2425         bool fieldmode = false;
2426         int r, cconv = 0;
2427         unsigned offset0, offset1;
2428         s32 row_inc;
2429         s32 pix_inc;
2430         u16 frame_width, frame_height;
2431         unsigned int field_offset = 0;
2432         u16 in_height = height;
2433         u16 in_width = width;
2434         int x_predecim = 1, y_predecim = 1;
2435         bool ilace = mgr_timings->interlace;
2436         unsigned long pclk = dispc_plane_pclk_rate(plane);
2437         unsigned long lclk = dispc_plane_lclk_rate(plane);
2438
2439         if (paddr == 0)
2440                 return -EINVAL;
2441
2442         out_width = out_width == 0 ? width : out_width;
2443         out_height = out_height == 0 ? height : out_height;
2444
2445         if (ilace && height == out_height)
2446                 fieldmode = true;
2447
2448         if (ilace) {
2449                 if (fieldmode)
2450                         in_height /= 2;
2451                 pos_y /= 2;
2452                 out_height /= 2;
2453
2454                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2455                         "out_height %d\n", in_height, pos_y,
2456                         out_height);
2457         }
2458
2459         if (!dss_feat_color_mode_supported(plane, color_mode))
2460                 return -EINVAL;
2461
2462         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2463                         in_height, out_width, out_height, color_mode,
2464                         &five_taps, &x_predecim, &y_predecim, pos_x,
2465                         rotation_type, mem_to_mem);
2466         if (r)
2467                 return r;
2468
2469         in_width = in_width / x_predecim;
2470         in_height = in_height / y_predecim;
2471
2472         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2473                         color_mode == OMAP_DSS_COLOR_UYVY ||
2474                         color_mode == OMAP_DSS_COLOR_NV12)
2475                 cconv = 1;
2476
2477         if (ilace && !fieldmode) {
2478                 /*
2479                  * when downscaling the bottom field may have to start several
2480                  * source lines below the top field. Unfortunately ACCUI
2481                  * registers will only hold the fractional part of the offset
2482                  * so the integer part must be added to the base address of the
2483                  * bottom field.
2484                  */
2485                 if (!in_height || in_height == out_height)
2486                         field_offset = 0;
2487                 else
2488                         field_offset = in_height / out_height / 2;
2489         }
2490
2491         /* Fields are independent but interleaved in memory. */
2492         if (fieldmode)
2493                 field_offset = 1;
2494
2495         offset0 = 0;
2496         offset1 = 0;
2497         row_inc = 0;
2498         pix_inc = 0;
2499
2500         if (plane == OMAP_DSS_WB) {
2501                 frame_width = out_width;
2502                 frame_height = out_height;
2503         } else {
2504                 frame_width = in_width;
2505                 frame_height = height;
2506         }
2507
2508         if (rotation_type == OMAP_DSS_ROT_TILER)
2509                 calc_tiler_rotation_offset(screen_width, frame_width,
2510                                 color_mode, fieldmode, field_offset,
2511                                 &offset0, &offset1, &row_inc, &pix_inc,
2512                                 x_predecim, y_predecim);
2513         else if (rotation_type == OMAP_DSS_ROT_DMA)
2514                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2515                                 frame_width, frame_height,
2516                                 color_mode, fieldmode, field_offset,
2517                                 &offset0, &offset1, &row_inc, &pix_inc,
2518                                 x_predecim, y_predecim);
2519         else
2520                 calc_vrfb_rotation_offset(rotation, mirror,
2521                                 screen_width, frame_width, frame_height,
2522                                 color_mode, fieldmode, field_offset,
2523                                 &offset0, &offset1, &row_inc, &pix_inc,
2524                                 x_predecim, y_predecim);
2525
2526         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2527                         offset0, offset1, row_inc, pix_inc);
2528
2529         dispc_ovl_set_color_mode(plane, color_mode);
2530
2531         dispc_ovl_configure_burst_type(plane, rotation_type);
2532
2533         dispc_ovl_set_ba0(plane, paddr + offset0);
2534         dispc_ovl_set_ba1(plane, paddr + offset1);
2535
2536         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2537                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2538                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2539         }
2540
2541         dispc_ovl_set_row_inc(plane, row_inc);
2542         dispc_ovl_set_pix_inc(plane, pix_inc);
2543
2544         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2545                         in_height, out_width, out_height);
2546
2547         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2548
2549         dispc_ovl_set_input_size(plane, in_width, in_height);
2550
2551         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2552                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2553                                    out_height, ilace, five_taps, fieldmode,
2554                                    color_mode, rotation);
2555                 dispc_ovl_set_output_size(plane, out_width, out_height);
2556                 dispc_ovl_set_vid_color_conv(plane, cconv);
2557         }
2558
2559         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2560                         color_mode);
2561
2562         dispc_ovl_set_zorder(plane, caps, zorder);
2563         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2564         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2565
2566         dispc_ovl_enable_replication(plane, caps, replication);
2567
2568         return 0;
2569 }
2570
2571 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2572                 bool replication, const struct omap_video_timings *mgr_timings,
2573                 bool mem_to_mem)
2574 {
2575         int r;
2576         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2577         enum omap_channel channel;
2578
2579         channel = dispc_ovl_get_channel_out(plane);
2580
2581         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2582                 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2583                 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2584                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2585                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2586
2587         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2588                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2589                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2590                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2591                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2592
2593         return r;
2594 }
2595 EXPORT_SYMBOL(dispc_ovl_setup);
2596
2597 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2598                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2599 {
2600         int r;
2601         u32 l;
2602         enum omap_plane plane = OMAP_DSS_WB;
2603         const int pos_x = 0, pos_y = 0;
2604         const u8 zorder = 0, global_alpha = 0;
2605         const bool replication = false;
2606         bool truncation;
2607         int in_width = mgr_timings->x_res;
2608         int in_height = mgr_timings->y_res;
2609         enum omap_overlay_caps caps =
2610                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2611
2612         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2613                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2614                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2615                 wi->mirror);
2616
2617         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2618                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2619                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2620                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2621                 replication, mgr_timings, mem_to_mem);
2622
2623         switch (wi->color_mode) {
2624         case OMAP_DSS_COLOR_RGB16:
2625         case OMAP_DSS_COLOR_RGB24P:
2626         case OMAP_DSS_COLOR_ARGB16:
2627         case OMAP_DSS_COLOR_RGBA16:
2628         case OMAP_DSS_COLOR_RGB12U:
2629         case OMAP_DSS_COLOR_ARGB16_1555:
2630         case OMAP_DSS_COLOR_XRGB16_1555:
2631         case OMAP_DSS_COLOR_RGBX16:
2632                 truncation = true;
2633                 break;
2634         default:
2635                 truncation = false;
2636                 break;
2637         }
2638
2639         /* setup extra DISPC_WB_ATTRIBUTES */
2640         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2641         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2642         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2643         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2644
2645         return r;
2646 }
2647
2648 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2649 {
2650         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2651
2652         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2653
2654         return 0;
2655 }
2656 EXPORT_SYMBOL(dispc_ovl_enable);
2657
2658 bool dispc_ovl_enabled(enum omap_plane plane)
2659 {
2660         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2661 }
2662 EXPORT_SYMBOL(dispc_ovl_enabled);
2663
2664 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2665 {
2666         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2667         /* flush posted write */
2668         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2669 }
2670 EXPORT_SYMBOL(dispc_mgr_enable);
2671
2672 bool dispc_mgr_is_enabled(enum omap_channel channel)
2673 {
2674         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2675 }
2676 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2677
2678 void dispc_wb_enable(bool enable)
2679 {
2680         dispc_ovl_enable(OMAP_DSS_WB, enable);
2681 }
2682
2683 bool dispc_wb_is_enabled(void)
2684 {
2685         return dispc_ovl_enabled(OMAP_DSS_WB);
2686 }
2687
2688 static void dispc_lcd_enable_signal_polarity(bool act_high)
2689 {
2690         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2691                 return;
2692
2693         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2694 }
2695
2696 void dispc_lcd_enable_signal(bool enable)
2697 {
2698         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2699                 return;
2700
2701         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2702 }
2703
2704 void dispc_pck_free_enable(bool enable)
2705 {
2706         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2707                 return;
2708
2709         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2710 }
2711
2712 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2713 {
2714         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2715 }
2716
2717
2718 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2719 {
2720         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2721 }
2722
2723 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2724 {
2725         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2726 }
2727
2728
2729 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2730 {
2731         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2732 }
2733
2734 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2735                 enum omap_dss_trans_key_type type,
2736                 u32 trans_key)
2737 {
2738         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2739
2740         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2741 }
2742
2743 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2744 {
2745         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2746 }
2747
2748 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2749                 bool enable)
2750 {
2751         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2752                 return;
2753
2754         if (ch == OMAP_DSS_CHANNEL_LCD)
2755                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2756         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2757                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2758 }
2759
2760 void dispc_mgr_setup(enum omap_channel channel,
2761                 const struct omap_overlay_manager_info *info)
2762 {
2763         dispc_mgr_set_default_color(channel, info->default_color);
2764         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2765         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2766         dispc_mgr_enable_alpha_fixed_zorder(channel,
2767                         info->partial_alpha_enabled);
2768         if (dss_has_feature(FEAT_CPR)) {
2769                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2770                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2771         }
2772 }
2773 EXPORT_SYMBOL(dispc_mgr_setup);
2774
2775 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2776 {
2777         int code;
2778
2779         switch (data_lines) {
2780         case 12:
2781                 code = 0;
2782                 break;
2783         case 16:
2784                 code = 1;
2785                 break;
2786         case 18:
2787                 code = 2;
2788                 break;
2789         case 24:
2790                 code = 3;
2791                 break;
2792         default:
2793                 BUG();
2794                 return;
2795         }
2796
2797         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2798 }
2799
2800 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2801 {
2802         u32 l;
2803         int gpout0, gpout1;
2804
2805         switch (mode) {
2806         case DSS_IO_PAD_MODE_RESET:
2807                 gpout0 = 0;
2808                 gpout1 = 0;
2809                 break;
2810         case DSS_IO_PAD_MODE_RFBI:
2811                 gpout0 = 1;
2812                 gpout1 = 0;
2813                 break;
2814         case DSS_IO_PAD_MODE_BYPASS:
2815                 gpout0 = 1;
2816                 gpout1 = 1;
2817                 break;
2818         default:
2819                 BUG();
2820                 return;
2821         }
2822
2823         l = dispc_read_reg(DISPC_CONTROL);
2824         l = FLD_MOD(l, gpout0, 15, 15);
2825         l = FLD_MOD(l, gpout1, 16, 16);
2826         dispc_write_reg(DISPC_CONTROL, l);
2827 }
2828
2829 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2830 {
2831         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2832 }
2833
2834 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2835                 const struct dss_lcd_mgr_config *config)
2836 {
2837         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2838
2839         dispc_mgr_enable_stallmode(channel, config->stallmode);
2840         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2841
2842         dispc_mgr_set_clock_div(channel, &config->clock_info);
2843
2844         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2845
2846         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2847
2848         dispc_mgr_set_lcd_type_tft(channel);
2849 }
2850 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2851
2852 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2853 {
2854         return width <= dispc.feat->mgr_width_max &&
2855                 height <= dispc.feat->mgr_height_max;
2856 }
2857
2858 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2859                 int vsw, int vfp, int vbp)
2860 {
2861         if (hsw < 1 || hsw > dispc.feat->sw_max ||
2862                         hfp < 1 || hfp > dispc.feat->hp_max ||
2863                         hbp < 1 || hbp > dispc.feat->hp_max ||
2864                         vsw < 1 || vsw > dispc.feat->sw_max ||
2865                         vfp < 0 || vfp > dispc.feat->vp_max ||
2866                         vbp < 0 || vbp > dispc.feat->vp_max)
2867                 return false;
2868         return true;
2869 }
2870
2871 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2872                 unsigned long pclk)
2873 {
2874         if (dss_mgr_is_lcd(channel))
2875                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2876         else
2877                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2878 }
2879
2880 bool dispc_mgr_timings_ok(enum omap_channel channel,
2881                 const struct omap_video_timings *timings)
2882 {
2883         bool timings_ok;
2884
2885         timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2886
2887         timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000);
2888
2889         if (dss_mgr_is_lcd(channel)) {
2890                 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2891                                 timings->hbp, timings->vsw, timings->vfp,
2892                                 timings->vbp);
2893         }
2894
2895         return timings_ok;
2896 }
2897
2898 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2899                 int hfp, int hbp, int vsw, int vfp, int vbp,
2900                 enum omap_dss_signal_level vsync_level,
2901                 enum omap_dss_signal_level hsync_level,
2902                 enum omap_dss_signal_edge data_pclk_edge,
2903                 enum omap_dss_signal_level de_level,
2904                 enum omap_dss_signal_edge sync_pclk_edge)
2905
2906 {
2907         u32 timing_h, timing_v, l;
2908         bool onoff, rf, ipc;
2909
2910         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2911                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2912                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2913         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2914                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2915                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
2916
2917         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2918         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2919
2920         switch (data_pclk_edge) {
2921         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2922                 ipc = false;
2923                 break;
2924         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2925                 ipc = true;
2926                 break;
2927         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2928         default:
2929                 BUG();
2930         }
2931
2932         switch (sync_pclk_edge) {
2933         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2934                 onoff = false;
2935                 rf = false;
2936                 break;
2937         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2938                 onoff = true;
2939                 rf = false;
2940                 break;
2941         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2942                 onoff = true;
2943                 rf = true;
2944                 break;
2945         default:
2946                 BUG();
2947         }
2948
2949         l = dispc_read_reg(DISPC_POL_FREQ(channel));
2950         l |= FLD_VAL(onoff, 17, 17);
2951         l |= FLD_VAL(rf, 16, 16);
2952         l |= FLD_VAL(de_level, 15, 15);
2953         l |= FLD_VAL(ipc, 14, 14);
2954         l |= FLD_VAL(hsync_level, 13, 13);
2955         l |= FLD_VAL(vsync_level, 12, 12);
2956         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2957 }
2958
2959 /* change name to mode? */
2960 void dispc_mgr_set_timings(enum omap_channel channel,
2961                 const struct omap_video_timings *timings)
2962 {
2963         unsigned xtot, ytot;
2964         unsigned long ht, vt;
2965         struct omap_video_timings t = *timings;
2966
2967         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2968
2969         if (!dispc_mgr_timings_ok(channel, &t)) {
2970                 BUG();
2971                 return;
2972         }
2973
2974         if (dss_mgr_is_lcd(channel)) {
2975                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2976                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2977                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2978
2979                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2980                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2981
2982                 ht = (timings->pixel_clock * 1000) / xtot;
2983                 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2984
2985                 DSSDBG("pck %u\n", timings->pixel_clock);
2986                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2987                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2988                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2989                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
2990                         t.de_level, t.sync_pclk_edge);
2991
2992                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2993         } else {
2994                 if (t.interlace == true)
2995                         t.y_res /= 2;
2996         }
2997
2998         dispc_mgr_set_size(channel, t.x_res, t.y_res);
2999 }
3000 EXPORT_SYMBOL(dispc_mgr_set_timings);
3001
3002 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3003                 u16 pck_div)
3004 {
3005         BUG_ON(lck_div < 1);
3006         BUG_ON(pck_div < 1);
3007
3008         dispc_write_reg(DISPC_DIVISORo(channel),
3009                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3010
3011         if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3012                         channel == OMAP_DSS_CHANNEL_LCD)
3013                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3014 }
3015
3016 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3017                 int *pck_div)
3018 {
3019         u32 l;
3020         l = dispc_read_reg(DISPC_DIVISORo(channel));
3021         *lck_div = FLD_GET(l, 23, 16);
3022         *pck_div = FLD_GET(l, 7, 0);
3023 }
3024
3025 unsigned long dispc_fclk_rate(void)
3026 {
3027         struct platform_device *dsidev;
3028         unsigned long r = 0;
3029
3030         switch (dss_get_dispc_clk_source()) {
3031         case OMAP_DSS_CLK_SRC_FCK:
3032                 r = dss_get_dispc_clk_rate();
3033                 break;
3034         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3035                 dsidev = dsi_get_dsidev_from_id(0);
3036                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3037                 break;
3038         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3039                 dsidev = dsi_get_dsidev_from_id(1);
3040                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3041                 break;
3042         default:
3043                 BUG();
3044                 return 0;
3045         }
3046
3047         return r;
3048 }
3049
3050 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3051 {
3052         struct platform_device *dsidev;
3053         int lcd;
3054         unsigned long r;
3055         u32 l;
3056
3057         if (dss_mgr_is_lcd(channel)) {
3058                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3059
3060                 lcd = FLD_GET(l, 23, 16);
3061
3062                 switch (dss_get_lcd_clk_source(channel)) {
3063                 case OMAP_DSS_CLK_SRC_FCK:
3064                         r = dss_get_dispc_clk_rate();
3065                         break;
3066                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3067                         dsidev = dsi_get_dsidev_from_id(0);
3068                         r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3069                         break;
3070                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3071                         dsidev = dsi_get_dsidev_from_id(1);
3072                         r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3073                         break;
3074                 default:
3075                         BUG();
3076                         return 0;
3077                 }
3078
3079                 return r / lcd;
3080         } else {
3081                 return dispc_fclk_rate();
3082         }
3083 }
3084
3085 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3086 {
3087         unsigned long r;
3088
3089         if (dss_mgr_is_lcd(channel)) {
3090                 int pcd;
3091                 u32 l;
3092
3093                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3094
3095                 pcd = FLD_GET(l, 7, 0);
3096
3097                 r = dispc_mgr_lclk_rate(channel);
3098
3099                 return r / pcd;
3100         } else {
3101                 return dispc.tv_pclk_rate;
3102         }
3103 }
3104
3105 void dispc_set_tv_pclk(unsigned long pclk)
3106 {
3107         dispc.tv_pclk_rate = pclk;
3108 }
3109
3110 unsigned long dispc_core_clk_rate(void)
3111 {
3112         return dispc.core_clk_rate;
3113 }
3114
3115 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3116 {
3117         enum omap_channel channel;
3118
3119         if (plane == OMAP_DSS_WB)
3120                 return 0;
3121
3122         channel = dispc_ovl_get_channel_out(plane);
3123
3124         return dispc_mgr_pclk_rate(channel);
3125 }
3126
3127 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3128 {
3129         enum omap_channel channel;
3130
3131         if (plane == OMAP_DSS_WB)
3132                 return 0;
3133
3134         channel = dispc_ovl_get_channel_out(plane);
3135
3136         return dispc_mgr_lclk_rate(channel);
3137 }
3138
3139 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3140 {
3141         int lcd, pcd;
3142         enum omap_dss_clk_source lcd_clk_src;
3143
3144         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3145
3146         lcd_clk_src = dss_get_lcd_clk_source(channel);
3147
3148         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3149                 dss_get_generic_clk_source_name(lcd_clk_src),
3150                 dss_feat_get_clk_source_name(lcd_clk_src));
3151
3152         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3153
3154         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3155                 dispc_mgr_lclk_rate(channel), lcd);
3156         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3157                 dispc_mgr_pclk_rate(channel), pcd);
3158 }
3159
3160 void dispc_dump_clocks(struct seq_file *s)
3161 {
3162         int lcd;
3163         u32 l;
3164         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3165
3166         if (dispc_runtime_get())
3167                 return;
3168
3169         seq_printf(s, "- DISPC -\n");
3170
3171         seq_printf(s, "dispc fclk source = %s (%s)\n",
3172                         dss_get_generic_clk_source_name(dispc_clk_src),
3173                         dss_feat_get_clk_source_name(dispc_clk_src));
3174
3175         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3176
3177         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3178                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3179                 l = dispc_read_reg(DISPC_DIVISOR);
3180                 lcd = FLD_GET(l, 23, 16);
3181
3182                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3183                                 (dispc_fclk_rate()/lcd), lcd);
3184         }
3185
3186         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3187
3188         if (dss_has_feature(FEAT_MGR_LCD2))
3189                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3190         if (dss_has_feature(FEAT_MGR_LCD3))
3191                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3192
3193         dispc_runtime_put();
3194 }
3195
3196 static void dispc_dump_regs(struct seq_file *s)
3197 {
3198         int i, j;
3199         const char *mgr_names[] = {
3200                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3201                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3202                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3203                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3204         };
3205         const char *ovl_names[] = {
3206                 [OMAP_DSS_GFX]          = "GFX",
3207                 [OMAP_DSS_VIDEO1]       = "VID1",
3208                 [OMAP_DSS_VIDEO2]       = "VID2",
3209                 [OMAP_DSS_VIDEO3]       = "VID3",
3210         };
3211         const char **p_names;
3212
3213 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3214
3215         if (dispc_runtime_get())
3216                 return;
3217
3218         /* DISPC common registers */
3219         DUMPREG(DISPC_REVISION);
3220         DUMPREG(DISPC_SYSCONFIG);
3221         DUMPREG(DISPC_SYSSTATUS);
3222         DUMPREG(DISPC_IRQSTATUS);
3223         DUMPREG(DISPC_IRQENABLE);
3224         DUMPREG(DISPC_CONTROL);
3225         DUMPREG(DISPC_CONFIG);
3226         DUMPREG(DISPC_CAPABLE);
3227         DUMPREG(DISPC_LINE_STATUS);
3228         DUMPREG(DISPC_LINE_NUMBER);
3229         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3230                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3231                 DUMPREG(DISPC_GLOBAL_ALPHA);
3232         if (dss_has_feature(FEAT_MGR_LCD2)) {
3233                 DUMPREG(DISPC_CONTROL2);
3234                 DUMPREG(DISPC_CONFIG2);
3235         }
3236         if (dss_has_feature(FEAT_MGR_LCD3)) {
3237                 DUMPREG(DISPC_CONTROL3);
3238                 DUMPREG(DISPC_CONFIG3);
3239         }
3240         if (dss_has_feature(FEAT_MFLAG))
3241                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3242
3243 #undef DUMPREG
3244
3245 #define DISPC_REG(i, name) name(i)
3246 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3247         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3248         dispc_read_reg(DISPC_REG(i, r)))
3249
3250         p_names = mgr_names;
3251
3252         /* DISPC channel specific registers */
3253         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3254                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3255                 DUMPREG(i, DISPC_TRANS_COLOR);
3256                 DUMPREG(i, DISPC_SIZE_MGR);
3257
3258                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3259                         continue;
3260
3261                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3262                 DUMPREG(i, DISPC_TRANS_COLOR);
3263                 DUMPREG(i, DISPC_TIMING_H);
3264                 DUMPREG(i, DISPC_TIMING_V);
3265                 DUMPREG(i, DISPC_POL_FREQ);
3266                 DUMPREG(i, DISPC_DIVISORo);
3267                 DUMPREG(i, DISPC_SIZE_MGR);
3268
3269                 DUMPREG(i, DISPC_DATA_CYCLE1);
3270                 DUMPREG(i, DISPC_DATA_CYCLE2);
3271                 DUMPREG(i, DISPC_DATA_CYCLE3);
3272
3273                 if (dss_has_feature(FEAT_CPR)) {
3274                         DUMPREG(i, DISPC_CPR_COEF_R);
3275                         DUMPREG(i, DISPC_CPR_COEF_G);
3276                         DUMPREG(i, DISPC_CPR_COEF_B);
3277                 }
3278         }
3279
3280         p_names = ovl_names;
3281
3282         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3283                 DUMPREG(i, DISPC_OVL_BA0);
3284                 DUMPREG(i, DISPC_OVL_BA1);
3285                 DUMPREG(i, DISPC_OVL_POSITION);
3286                 DUMPREG(i, DISPC_OVL_SIZE);
3287                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3288                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3289                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3290                 DUMPREG(i, DISPC_OVL_ROW_INC);
3291                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3292                 if (dss_has_feature(FEAT_PRELOAD))
3293                         DUMPREG(i, DISPC_OVL_PRELOAD);
3294
3295                 if (i == OMAP_DSS_GFX) {
3296                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3297                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3298                         continue;
3299                 }
3300
3301                 DUMPREG(i, DISPC_OVL_FIR);
3302                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3303                 DUMPREG(i, DISPC_OVL_ACCU0);
3304                 DUMPREG(i, DISPC_OVL_ACCU1);
3305                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3306                         DUMPREG(i, DISPC_OVL_BA0_UV);
3307                         DUMPREG(i, DISPC_OVL_BA1_UV);
3308                         DUMPREG(i, DISPC_OVL_FIR2);
3309                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3310                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3311                 }
3312                 if (dss_has_feature(FEAT_ATTR2))
3313                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3314                 if (dss_has_feature(FEAT_PRELOAD))
3315                         DUMPREG(i, DISPC_OVL_PRELOAD);
3316                 if (dss_has_feature(FEAT_MFLAG))
3317                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3318         }
3319
3320 #undef DISPC_REG
3321 #undef DUMPREG
3322
3323 #define DISPC_REG(plane, name, i) name(plane, i)
3324 #define DUMPREG(plane, name, i) \
3325         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3326         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3327         dispc_read_reg(DISPC_REG(plane, name, i)))
3328
3329         /* Video pipeline coefficient registers */
3330
3331         /* start from OMAP_DSS_VIDEO1 */
3332         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3333                 for (j = 0; j < 8; j++)
3334                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3335
3336                 for (j = 0; j < 8; j++)
3337                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3338
3339                 for (j = 0; j < 5; j++)
3340                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3341
3342                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3343                         for (j = 0; j < 8; j++)
3344                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3345                 }
3346
3347                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3348                         for (j = 0; j < 8; j++)
3349                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3350
3351                         for (j = 0; j < 8; j++)
3352                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3353
3354                         for (j = 0; j < 8; j++)
3355                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3356                 }
3357         }
3358
3359         dispc_runtime_put();
3360
3361 #undef DISPC_REG
3362 #undef DUMPREG
3363 }
3364
3365 /* calculate clock rates using dividers in cinfo */
3366 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3367                 struct dispc_clock_info *cinfo)
3368 {
3369         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3370                 return -EINVAL;
3371         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3372                 return -EINVAL;
3373
3374         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3375         cinfo->pck = cinfo->lck / cinfo->pck_div;
3376
3377         return 0;
3378 }
3379
3380 bool dispc_div_calc(unsigned long dispc,
3381                 unsigned long pck_min, unsigned long pck_max,
3382                 dispc_div_calc_func func, void *data)
3383 {
3384         int lckd, lckd_start, lckd_stop;
3385         int pckd, pckd_start, pckd_stop;
3386         unsigned long pck, lck;
3387         unsigned long lck_max;
3388         unsigned long pckd_hw_min, pckd_hw_max;
3389         unsigned min_fck_per_pck;
3390         unsigned long fck;
3391
3392 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3393         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3394 #else
3395         min_fck_per_pck = 0;
3396 #endif
3397
3398         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3399         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3400
3401         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3402
3403         pck_min = pck_min ? pck_min : 1;
3404         pck_max = pck_max ? pck_max : ULONG_MAX;
3405
3406         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3407         lckd_stop = min(dispc / pck_min, 255ul);
3408
3409         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3410                 lck = dispc / lckd;
3411
3412                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3413                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3414
3415                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3416                         pck = lck / pckd;
3417
3418                         /*
3419                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3420                          * clock, which means we're configuring DISPC fclk here
3421                          * also. Thus we need to use the calculated lck. For
3422                          * OMAP4+ the DISPC fclk is a separate clock.
3423                          */
3424                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3425                                 fck = dispc_core_clk_rate();
3426                         else
3427                                 fck = lck;
3428
3429                         if (fck < pck * min_fck_per_pck)
3430                                 continue;
3431
3432                         if (func(lckd, pckd, lck, pck, data))
3433                                 return true;
3434                 }
3435         }
3436
3437         return false;
3438 }
3439
3440 void dispc_mgr_set_clock_div(enum omap_channel channel,
3441                 const struct dispc_clock_info *cinfo)
3442 {
3443         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3444         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3445
3446         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3447 }
3448
3449 int dispc_mgr_get_clock_div(enum omap_channel channel,
3450                 struct dispc_clock_info *cinfo)
3451 {
3452         unsigned long fck;
3453
3454         fck = dispc_fclk_rate();
3455
3456         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3457         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3458
3459         cinfo->lck = fck / cinfo->lck_div;
3460         cinfo->pck = cinfo->lck / cinfo->pck_div;
3461
3462         return 0;
3463 }
3464
3465 u32 dispc_read_irqstatus(void)
3466 {
3467         return dispc_read_reg(DISPC_IRQSTATUS);
3468 }
3469 EXPORT_SYMBOL(dispc_read_irqstatus);
3470
3471 void dispc_clear_irqstatus(u32 mask)
3472 {
3473         dispc_write_reg(DISPC_IRQSTATUS, mask);
3474 }
3475 EXPORT_SYMBOL(dispc_clear_irqstatus);
3476
3477 u32 dispc_read_irqenable(void)
3478 {
3479         return dispc_read_reg(DISPC_IRQENABLE);
3480 }
3481 EXPORT_SYMBOL(dispc_read_irqenable);
3482
3483 void dispc_write_irqenable(u32 mask)
3484 {
3485         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3486
3487         /* clear the irqstatus for newly enabled irqs */
3488         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3489
3490         dispc_write_reg(DISPC_IRQENABLE, mask);
3491 }
3492 EXPORT_SYMBOL(dispc_write_irqenable);
3493
3494 void dispc_enable_sidle(void)
3495 {
3496         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3497 }
3498
3499 void dispc_disable_sidle(void)
3500 {
3501         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3502 }
3503
3504 static void _omap_dispc_initial_config(void)
3505 {
3506         u32 l;
3507
3508         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3509         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3510                 l = dispc_read_reg(DISPC_DIVISOR);
3511                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3512                 l = FLD_MOD(l, 1, 0, 0);
3513                 l = FLD_MOD(l, 1, 23, 16);
3514                 dispc_write_reg(DISPC_DIVISOR, l);
3515
3516                 dispc.core_clk_rate = dispc_fclk_rate();
3517         }
3518
3519         /* FUNCGATED */
3520         if (dss_has_feature(FEAT_FUNCGATED))
3521                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3522
3523         dispc_setup_color_conv_coef();
3524
3525         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3526
3527         dispc_init_fifos();
3528
3529         dispc_configure_burst_sizes();
3530
3531         dispc_ovl_enable_zorder_planes();
3532
3533         if (dispc.feat->mstandby_workaround)
3534                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3535 }
3536
3537 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3538         .sw_start               =       5,
3539         .fp_start               =       15,
3540         .bp_start               =       27,
3541         .sw_max                 =       64,
3542         .vp_max                 =       255,
3543         .hp_max                 =       256,
3544         .mgr_width_start        =       10,
3545         .mgr_height_start       =       26,
3546         .mgr_width_max          =       2048,
3547         .mgr_height_max         =       2048,
3548         .max_lcd_pclk           =       66500000,
3549         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3550         .calc_core_clk          =       calc_core_clk_24xx,
3551         .num_fifos              =       3,
3552         .no_framedone_tv        =       true,
3553         .set_max_preload        =       false,
3554 };
3555
3556 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3557         .sw_start               =       5,
3558         .fp_start               =       15,
3559         .bp_start               =       27,
3560         .sw_max                 =       64,
3561         .vp_max                 =       255,
3562         .hp_max                 =       256,
3563         .mgr_width_start        =       10,
3564         .mgr_height_start       =       26,
3565         .mgr_width_max          =       2048,
3566         .mgr_height_max         =       2048,
3567         .max_lcd_pclk           =       173000000,
3568         .max_tv_pclk            =       59000000,
3569         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3570         .calc_core_clk          =       calc_core_clk_34xx,
3571         .num_fifos              =       3,
3572         .no_framedone_tv        =       true,
3573         .set_max_preload        =       false,
3574 };
3575
3576 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3577         .sw_start               =       7,
3578         .fp_start               =       19,
3579         .bp_start               =       31,
3580         .sw_max                 =       256,
3581         .vp_max                 =       4095,
3582         .hp_max                 =       4096,
3583         .mgr_width_start        =       10,
3584         .mgr_height_start       =       26,
3585         .mgr_width_max          =       2048,
3586         .mgr_height_max         =       2048,
3587         .max_lcd_pclk           =       173000000,
3588         .max_tv_pclk            =       59000000,
3589         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3590         .calc_core_clk          =       calc_core_clk_34xx,
3591         .num_fifos              =       3,
3592         .no_framedone_tv        =       true,
3593         .set_max_preload        =       false,
3594 };
3595
3596 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3597         .sw_start               =       7,
3598         .fp_start               =       19,
3599         .bp_start               =       31,
3600         .sw_max                 =       256,
3601         .vp_max                 =       4095,
3602         .hp_max                 =       4096,
3603         .mgr_width_start        =       10,
3604         .mgr_height_start       =       26,
3605         .mgr_width_max          =       2048,
3606         .mgr_height_max         =       2048,
3607         .max_lcd_pclk           =       170000000,
3608         .max_tv_pclk            =       185625000,
3609         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3610         .calc_core_clk          =       calc_core_clk_44xx,
3611         .num_fifos              =       5,
3612         .gfx_fifo_workaround    =       true,
3613         .set_max_preload        =       true,
3614 };
3615
3616 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3617         .sw_start               =       7,
3618         .fp_start               =       19,
3619         .bp_start               =       31,
3620         .sw_max                 =       256,
3621         .vp_max                 =       4095,
3622         .hp_max                 =       4096,
3623         .mgr_width_start        =       11,
3624         .mgr_height_start       =       27,
3625         .mgr_width_max          =       4096,
3626         .mgr_height_max         =       4096,
3627         .max_lcd_pclk           =       170000000,
3628         .max_tv_pclk            =       186000000,
3629         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3630         .calc_core_clk          =       calc_core_clk_44xx,
3631         .num_fifos              =       5,
3632         .gfx_fifo_workaround    =       true,
3633         .mstandby_workaround    =       true,
3634         .set_max_preload        =       true,
3635 };
3636
3637 static int __init dispc_init_features(struct platform_device *pdev)
3638 {
3639         const struct dispc_features *src;
3640         struct dispc_features *dst;
3641
3642         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3643         if (!dst) {
3644                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3645                 return -ENOMEM;
3646         }
3647
3648         switch (omapdss_get_version()) {
3649         case OMAPDSS_VER_OMAP24xx:
3650                 src = &omap24xx_dispc_feats;
3651                 break;
3652
3653         case OMAPDSS_VER_OMAP34xx_ES1:
3654                 src = &omap34xx_rev1_0_dispc_feats;
3655                 break;
3656
3657         case OMAPDSS_VER_OMAP34xx_ES3:
3658         case OMAPDSS_VER_OMAP3630:
3659         case OMAPDSS_VER_AM35xx:
3660                 src = &omap34xx_rev3_0_dispc_feats;
3661                 break;
3662
3663         case OMAPDSS_VER_OMAP4430_ES1:
3664         case OMAPDSS_VER_OMAP4430_ES2:
3665         case OMAPDSS_VER_OMAP4:
3666                 src = &omap44xx_dispc_feats;
3667                 break;
3668
3669         case OMAPDSS_VER_OMAP5:
3670                 src = &omap54xx_dispc_feats;
3671                 break;
3672
3673         default:
3674                 return -ENODEV;
3675         }
3676
3677         memcpy(dst, src, sizeof(*dst));
3678         dispc.feat = dst;
3679
3680         return 0;
3681 }
3682
3683 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3684 {
3685         return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3686                              IRQF_SHARED, "OMAP DISPC", dev_id);
3687 }
3688 EXPORT_SYMBOL(dispc_request_irq);
3689
3690 void dispc_free_irq(void *dev_id)
3691 {
3692         devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3693 }
3694 EXPORT_SYMBOL(dispc_free_irq);
3695
3696 /* DISPC HW IP initialisation */
3697 static int __init omap_dispchw_probe(struct platform_device *pdev)
3698 {
3699         u32 rev;
3700         int r = 0;
3701         struct resource *dispc_mem;
3702
3703         dispc.pdev = pdev;
3704
3705         r = dispc_init_features(dispc.pdev);
3706         if (r)
3707                 return r;
3708
3709         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3710         if (!dispc_mem) {
3711                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3712                 return -EINVAL;
3713         }
3714
3715         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3716                                   resource_size(dispc_mem));
3717         if (!dispc.base) {
3718                 DSSERR("can't ioremap DISPC\n");
3719                 return -ENOMEM;
3720         }
3721
3722         dispc.irq = platform_get_irq(dispc.pdev, 0);
3723         if (dispc.irq < 0) {
3724                 DSSERR("platform_get_irq failed\n");
3725                 return -ENODEV;
3726         }
3727
3728         pm_runtime_enable(&pdev->dev);
3729
3730         r = dispc_runtime_get();
3731         if (r)
3732                 goto err_runtime_get;
3733
3734         _omap_dispc_initial_config();
3735
3736         rev = dispc_read_reg(DISPC_REVISION);
3737         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3738                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3739
3740         dispc_runtime_put();
3741
3742         dss_init_overlay_managers();
3743
3744         dss_debugfs_create_file("dispc", dispc_dump_regs);
3745
3746         return 0;
3747
3748 err_runtime_get:
3749         pm_runtime_disable(&pdev->dev);
3750         return r;
3751 }
3752
3753 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3754 {
3755         pm_runtime_disable(&pdev->dev);
3756
3757         dss_uninit_overlay_managers();
3758
3759         return 0;
3760 }
3761
3762 static int dispc_runtime_suspend(struct device *dev)
3763 {
3764         dispc_save_context();
3765
3766         return 0;
3767 }
3768
3769 static int dispc_runtime_resume(struct device *dev)
3770 {
3771         _omap_dispc_initial_config();
3772
3773         dispc_restore_context();
3774
3775         return 0;
3776 }
3777
3778 static const struct dev_pm_ops dispc_pm_ops = {
3779         .runtime_suspend = dispc_runtime_suspend,
3780         .runtime_resume = dispc_runtime_resume,
3781 };
3782
3783 static struct platform_driver omap_dispchw_driver = {
3784         .remove         = __exit_p(omap_dispchw_remove),
3785         .driver         = {
3786                 .name   = "omapdss_dispc",
3787                 .owner  = THIS_MODULE,
3788                 .pm     = &dispc_pm_ops,
3789         },
3790 };
3791
3792 int __init dispc_init_platform_driver(void)
3793 {
3794         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3795 }
3796
3797 void __exit dispc_uninit_platform_driver(void)
3798 {
3799         platform_driver_unregister(&omap_dispchw_driver);
3800 }