drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 #define REG_GET(idx, start, end) \
 143         FLD_GET(dispc_read_reg(idx), start, end)
 144
 145 #define REG_FLD_MOD(idx, val, start, end)                               \
 146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 147
 148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 149         DISPC_VID_ATTRIBUTES(0),
 150         DISPC_VID_ATTRIBUTES(1) };
 151
 152 struct dispc_irq_stats {
 153         unsigned long last_reset;
 154         unsigned irq_count;
 155         unsigned irqs[32];
 156 };
 157
 158 static struct {
 159         void __iomem    *base;
 160
 161         u32     fifo_size[3];
 162
 163         spinlock_t irq_lock;
 164         u32 irq_error_mask;
 165         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 166         u32 error_irqs;
 167         struct work_struct error_work;
 168
 169         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 170
 171 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 172         spinlock_t irq_stats_lock;
 173         struct dispc_irq_stats irq_stats;
 174 #endif
 175 } dispc;
 176
 177 static void _omap_dispc_set_irqs(void);
 178
 179 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 180 {
 181         __raw_writel(val, dispc.base + idx.idx);
 182 }
 183
 184 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 185 {
 186         return __raw_readl(dispc.base + idx.idx);
 187 }
 188
 189 #define SR(reg) \
 190         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 191 #define RR(reg) \
 192         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 193
 194 void dispc_save_context(void)
 195 {
 196         if (cpu_is_omap24xx())
 197                 return;
 198
 199         SR(SYSCONFIG);
 200         SR(IRQENABLE);
 201         SR(CONTROL);
 202         SR(CONFIG);
 203         SR(DEFAULT_COLOR0);
 204         SR(DEFAULT_COLOR1);
 205         SR(TRANS_COLOR0);
 206         SR(TRANS_COLOR1);
 207         SR(LINE_NUMBER);
 208         SR(TIMING_H);
 209         SR(TIMING_V);
 210         SR(POL_FREQ);
 211         SR(DIVISOR);
 212         SR(GLOBAL_ALPHA);
 213         SR(SIZE_DIG);
 214         SR(SIZE_LCD);
 215
 216         SR(GFX_BA0);
 217         SR(GFX_BA1);
 218         SR(GFX_POSITION);
 219         SR(GFX_SIZE);
 220         SR(GFX_ATTRIBUTES);
 221         SR(GFX_FIFO_THRESHOLD);
 222         SR(GFX_ROW_INC);
 223         SR(GFX_PIXEL_INC);
 224         SR(GFX_WINDOW_SKIP);
 225         SR(GFX_TABLE_BA);
 226
 227         SR(DATA_CYCLE1);
 228         SR(DATA_CYCLE2);
 229         SR(DATA_CYCLE3);
 230
 231         SR(CPR_COEF_R);
 232         SR(CPR_COEF_G);
 233         SR(CPR_COEF_B);
 234
 235         SR(GFX_PRELOAD);
 236
 237         /* VID1 */
 238         SR(VID_BA0(0));
 239         SR(VID_BA1(0));
 240         SR(VID_POSITION(0));
 241         SR(VID_SIZE(0));
 242         SR(VID_ATTRIBUTES(0));
 243         SR(VID_FIFO_THRESHOLD(0));
 244         SR(VID_ROW_INC(0));
 245         SR(VID_PIXEL_INC(0));
 246         SR(VID_FIR(0));
 247         SR(VID_PICTURE_SIZE(0));
 248         SR(VID_ACCU0(0));
 249         SR(VID_ACCU1(0));
 250
 251         SR(VID_FIR_COEF_H(0, 0));
 252         SR(VID_FIR_COEF_H(0, 1));
 253         SR(VID_FIR_COEF_H(0, 2));
 254         SR(VID_FIR_COEF_H(0, 3));
 255         SR(VID_FIR_COEF_H(0, 4));
 256         SR(VID_FIR_COEF_H(0, 5));
 257         SR(VID_FIR_COEF_H(0, 6));
 258         SR(VID_FIR_COEF_H(0, 7));
 259
 260         SR(VID_FIR_COEF_HV(0, 0));
 261         SR(VID_FIR_COEF_HV(0, 1));
 262         SR(VID_FIR_COEF_HV(0, 2));
 263         SR(VID_FIR_COEF_HV(0, 3));
 264         SR(VID_FIR_COEF_HV(0, 4));
 265         SR(VID_FIR_COEF_HV(0, 5));
 266         SR(VID_FIR_COEF_HV(0, 6));
 267         SR(VID_FIR_COEF_HV(0, 7));
 268
 269         SR(VID_CONV_COEF(0, 0));
 270         SR(VID_CONV_COEF(0, 1));
 271         SR(VID_CONV_COEF(0, 2));
 272         SR(VID_CONV_COEF(0, 3));
 273         SR(VID_CONV_COEF(0, 4));
 274
 275         SR(VID_FIR_COEF_V(0, 0));
 276         SR(VID_FIR_COEF_V(0, 1));
 277         SR(VID_FIR_COEF_V(0, 2));
 278         SR(VID_FIR_COEF_V(0, 3));
 279         SR(VID_FIR_COEF_V(0, 4));
 280         SR(VID_FIR_COEF_V(0, 5));
 281         SR(VID_FIR_COEF_V(0, 6));
 282         SR(VID_FIR_COEF_V(0, 7));
 283
 284         SR(VID_PRELOAD(0));
 285
 286         /* VID2 */
 287         SR(VID_BA0(1));
 288         SR(VID_BA1(1));
 289         SR(VID_POSITION(1));
 290         SR(VID_SIZE(1));
 291         SR(VID_ATTRIBUTES(1));
 292         SR(VID_FIFO_THRESHOLD(1));
 293         SR(VID_ROW_INC(1));
 294         SR(VID_PIXEL_INC(1));
 295         SR(VID_FIR(1));
 296         SR(VID_PICTURE_SIZE(1));
 297         SR(VID_ACCU0(1));
 298         SR(VID_ACCU1(1));
 299
 300         SR(VID_FIR_COEF_H(1, 0));
 301         SR(VID_FIR_COEF_H(1, 1));
 302         SR(VID_FIR_COEF_H(1, 2));
 303         SR(VID_FIR_COEF_H(1, 3));
 304         SR(VID_FIR_COEF_H(1, 4));
 305         SR(VID_FIR_COEF_H(1, 5));
 306         SR(VID_FIR_COEF_H(1, 6));
 307         SR(VID_FIR_COEF_H(1, 7));
 308
 309         SR(VID_FIR_COEF_HV(1, 0));
 310         SR(VID_FIR_COEF_HV(1, 1));
 311         SR(VID_FIR_COEF_HV(1, 2));
 312         SR(VID_FIR_COEF_HV(1, 3));
 313         SR(VID_FIR_COEF_HV(1, 4));
 314         SR(VID_FIR_COEF_HV(1, 5));
 315         SR(VID_FIR_COEF_HV(1, 6));
 316         SR(VID_FIR_COEF_HV(1, 7));
 317
 318         SR(VID_CONV_COEF(1, 0));
 319         SR(VID_CONV_COEF(1, 1));
 320         SR(VID_CONV_COEF(1, 2));
 321         SR(VID_CONV_COEF(1, 3));
 322         SR(VID_CONV_COEF(1, 4));
 323
 324         SR(VID_FIR_COEF_V(1, 0));
 325         SR(VID_FIR_COEF_V(1, 1));
 326         SR(VID_FIR_COEF_V(1, 2));
 327         SR(VID_FIR_COEF_V(1, 3));
 328         SR(VID_FIR_COEF_V(1, 4));
 329         SR(VID_FIR_COEF_V(1, 5));
 330         SR(VID_FIR_COEF_V(1, 6));
 331         SR(VID_FIR_COEF_V(1, 7));
 332
 333         SR(VID_PRELOAD(1));
 334 }
 335
 336 void dispc_restore_context(void)
 337 {
 338         RR(SYSCONFIG);
 339         /*RR(IRQENABLE);*/
 340         /*RR(CONTROL);*/
 341         RR(CONFIG);
 342         RR(DEFAULT_COLOR0);
 343         RR(DEFAULT_COLOR1);
 344         RR(TRANS_COLOR0);
 345         RR(TRANS_COLOR1);
 346         RR(LINE_NUMBER);
 347         RR(TIMING_H);
 348         RR(TIMING_V);
 349         RR(POL_FREQ);
 350         RR(DIVISOR);
 351         RR(GLOBAL_ALPHA);
 352         RR(SIZE_DIG);
 353         RR(SIZE_LCD);
 354
 355         RR(GFX_BA0);
 356         RR(GFX_BA1);
 357         RR(GFX_POSITION);
 358         RR(GFX_SIZE);
 359         RR(GFX_ATTRIBUTES);
 360         RR(GFX_FIFO_THRESHOLD);
 361         RR(GFX_ROW_INC);
 362         RR(GFX_PIXEL_INC);
 363         RR(GFX_WINDOW_SKIP);
 364         RR(GFX_TABLE_BA);
 365
 366         RR(DATA_CYCLE1);
 367         RR(DATA_CYCLE2);
 368         RR(DATA_CYCLE3);
 369
 370         RR(CPR_COEF_R);
 371         RR(CPR_COEF_G);
 372         RR(CPR_COEF_B);
 373
 374         RR(GFX_PRELOAD);
 375
 376         /* VID1 */
 377         RR(VID_BA0(0));
 378         RR(VID_BA1(0));
 379         RR(VID_POSITION(0));
 380         RR(VID_SIZE(0));
 381         RR(VID_ATTRIBUTES(0));
 382         RR(VID_FIFO_THRESHOLD(0));
 383         RR(VID_ROW_INC(0));
 384         RR(VID_PIXEL_INC(0));
 385         RR(VID_FIR(0));
 386         RR(VID_PICTURE_SIZE(0));
 387         RR(VID_ACCU0(0));
 388         RR(VID_ACCU1(0));
 389
 390         RR(VID_FIR_COEF_H(0, 0));
 391         RR(VID_FIR_COEF_H(0, 1));
 392         RR(VID_FIR_COEF_H(0, 2));
 393         RR(VID_FIR_COEF_H(0, 3));
 394         RR(VID_FIR_COEF_H(0, 4));
 395         RR(VID_FIR_COEF_H(0, 5));
 396         RR(VID_FIR_COEF_H(0, 6));
 397         RR(VID_FIR_COEF_H(0, 7));
 398
 399         RR(VID_FIR_COEF_HV(0, 0));
 400         RR(VID_FIR_COEF_HV(0, 1));
 401         RR(VID_FIR_COEF_HV(0, 2));
 402         RR(VID_FIR_COEF_HV(0, 3));
 403         RR(VID_FIR_COEF_HV(0, 4));
 404         RR(VID_FIR_COEF_HV(0, 5));
 405         RR(VID_FIR_COEF_HV(0, 6));
 406         RR(VID_FIR_COEF_HV(0, 7));
 407
 408         RR(VID_CONV_COEF(0, 0));
 409         RR(VID_CONV_COEF(0, 1));
 410         RR(VID_CONV_COEF(0, 2));
 411         RR(VID_CONV_COEF(0, 3));
 412         RR(VID_CONV_COEF(0, 4));
 413
 414         RR(VID_FIR_COEF_V(0, 0));
 415         RR(VID_FIR_COEF_V(0, 1));
 416         RR(VID_FIR_COEF_V(0, 2));
 417         RR(VID_FIR_COEF_V(0, 3));
 418         RR(VID_FIR_COEF_V(0, 4));
 419         RR(VID_FIR_COEF_V(0, 5));
 420         RR(VID_FIR_COEF_V(0, 6));
 421         RR(VID_FIR_COEF_V(0, 7));
 422
 423         RR(VID_PRELOAD(0));
 424
 425         /* VID2 */
 426         RR(VID_BA0(1));
 427         RR(VID_BA1(1));
 428         RR(VID_POSITION(1));
 429         RR(VID_SIZE(1));
 430         RR(VID_ATTRIBUTES(1));
 431         RR(VID_FIFO_THRESHOLD(1));
 432         RR(VID_ROW_INC(1));
 433         RR(VID_PIXEL_INC(1));
 434         RR(VID_FIR(1));
 435         RR(VID_PICTURE_SIZE(1));
 436         RR(VID_ACCU0(1));
 437         RR(VID_ACCU1(1));
 438
 439         RR(VID_FIR_COEF_H(1, 0));
 440         RR(VID_FIR_COEF_H(1, 1));
 441         RR(VID_FIR_COEF_H(1, 2));
 442         RR(VID_FIR_COEF_H(1, 3));
 443         RR(VID_FIR_COEF_H(1, 4));
 444         RR(VID_FIR_COEF_H(1, 5));
 445         RR(VID_FIR_COEF_H(1, 6));
 446         RR(VID_FIR_COEF_H(1, 7));
 447
 448         RR(VID_FIR_COEF_HV(1, 0));
 449         RR(VID_FIR_COEF_HV(1, 1));
 450         RR(VID_FIR_COEF_HV(1, 2));
 451         RR(VID_FIR_COEF_HV(1, 3));
 452         RR(VID_FIR_COEF_HV(1, 4));
 453         RR(VID_FIR_COEF_HV(1, 5));
 454         RR(VID_FIR_COEF_HV(1, 6));
 455         RR(VID_FIR_COEF_HV(1, 7));
 456
 457         RR(VID_CONV_COEF(1, 0));
 458         RR(VID_CONV_COEF(1, 1));
 459         RR(VID_CONV_COEF(1, 2));
 460         RR(VID_CONV_COEF(1, 3));
 461         RR(VID_CONV_COEF(1, 4));
 462
 463         RR(VID_FIR_COEF_V(1, 0));
 464         RR(VID_FIR_COEF_V(1, 1));
 465         RR(VID_FIR_COEF_V(1, 2));
 466         RR(VID_FIR_COEF_V(1, 3));
 467         RR(VID_FIR_COEF_V(1, 4));
 468         RR(VID_FIR_COEF_V(1, 5));
 469         RR(VID_FIR_COEF_V(1, 6));
 470         RR(VID_FIR_COEF_V(1, 7));
 471
 472         RR(VID_PRELOAD(1));
 473
 474         /* enable last, because LCD & DIGIT enable are here */
 475         RR(CONTROL);
 476
 477         /* clear spurious SYNC_LOST_DIGIT interrupts */
 478         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 479
 480         /*
 481          * enable last so IRQs won't trigger before
 482          * the context is fully restored
 483          */
 484         RR(IRQENABLE);
 485 }
 486
 487 #undef SR
 488 #undef RR
 489
 490 static inline void enable_clocks(bool enable)
 491 {
 492         if (enable)
 493                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 494         else
 495                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 496 }
 497
 498 bool dispc_go_busy(enum omap_channel channel)
 499 {
 500         int bit;
 501
 502         if (channel == OMAP_DSS_CHANNEL_LCD)
 503                 bit = 5; /* GOLCD */
 504         else
 505                 bit = 6; /* GODIGIT */
 506
 507         return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 508 }
 509
 510 void dispc_go(enum omap_channel channel)
 511 {
 512         int bit;
 513
 514         enable_clocks(1);
 515
 516         if (channel == OMAP_DSS_CHANNEL_LCD)
 517                 bit = 0; /* LCDENABLE */
 518         else
 519                 bit = 1; /* DIGITALENABLE */
 520
 521         /* if the channel is not enabled, we don't need GO */
 522         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 523                 goto end;
 524
 525         if (channel == OMAP_DSS_CHANNEL_LCD)
 526                 bit = 5; /* GOLCD */
 527         else
 528                 bit = 6; /* GODIGIT */
 529
 530         if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 531                 DSSERR("GO bit not down for channel %d\n", channel);
 532                 goto end;
 533         }
 534
 535         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 536
 537         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 538 end:
 539         enable_clocks(0);
 540 }
 541
 542 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 543 {
 544         BUG_ON(plane == OMAP_DSS_GFX);
 545
 546         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 547 }
 548
 549 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 550 {
 551         BUG_ON(plane == OMAP_DSS_GFX);
 552
 553         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 554 }
 555
 556 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 557 {
 558         BUG_ON(plane == OMAP_DSS_GFX);
 559
 560         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 561 }
 562
 563 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 564                 int vscaleup, int five_taps)
 565 {
 566         /* Coefficients for horizontal up-sampling */
 567         static const u32 coef_hup[8] = {
 568                 0x00800000,
 569                 0x0D7CF800,
 570                 0x1E70F5FF,
 571                 0x335FF5FE,
 572                 0xF74949F7,
 573                 0xF55F33FB,
 574                 0xF5701EFE,
 575                 0xF87C0DFF,
 576         };
 577
 578         /* Coefficients for horizontal down-sampling */
 579         static const u32 coef_hdown[8] = {
 580                 0x24382400,
 581                 0x28371FFE,
 582                 0x2C361BFB,
 583                 0x303516F9,
 584                 0x11343311,
 585                 0x1635300C,
 586                 0x1B362C08,
 587                 0x1F372804,
 588         };
 589
 590         /* Coefficients for horizontal and vertical up-sampling */
 591         static const u32 coef_hvup[2][8] = {
 592                 {
 593                 0x00800000,
 594                 0x037B02FF,
 595                 0x0C6F05FE,
 596                 0x205907FB,
 597                 0x00404000,
 598                 0x075920FE,
 599                 0x056F0CFF,
 600                 0x027B0300,
 601                 },
 602                 {
 603                 0x00800000,
 604                 0x0D7CF8FF,
 605                 0x1E70F5FE,
 606                 0x335FF5FB,
 607                 0xF7404000,
 608                 0xF55F33FE,
 609                 0xF5701EFF,
 610                 0xF87C0D00,
 611                 },
 612         };
 613
 614         /* Coefficients for horizontal and vertical down-sampling */
 615         static const u32 coef_hvdown[2][8] = {
 616                 {
 617                 0x24382400,
 618                 0x28391F04,
 619                 0x2D381B08,
 620                 0x3237170C,
 621                 0x123737F7,
 622                 0x173732F9,
 623                 0x1B382DFB,
 624                 0x1F3928FE,
 625                 },
 626                 {
 627                 0x24382400,
 628                 0x28371F04,
 629                 0x2C361B08,
 630                 0x3035160C,
 631                 0x113433F7,
 632                 0x163530F9,
 633                 0x1B362CFB,
 634                 0x1F3728FE,
 635                 },
 636         };
 637
 638         /* Coefficients for vertical up-sampling */
 639         static const u32 coef_vup[8] = {
 640                 0x00000000,
 641                 0x0000FF00,
 642                 0x0000FEFF,
 643                 0x0000FBFE,
 644                 0x000000F7,
 645                 0x0000FEFB,
 646                 0x0000FFFE,
 647                 0x000000FF,
 648         };
 649
 650
 651         /* Coefficients for vertical down-sampling */
 652         static const u32 coef_vdown[8] = {
 653                 0x00000000,
 654                 0x000004FE,
 655                 0x000008FB,
 656                 0x00000CF9,
 657                 0x0000F711,
 658                 0x0000F90C,
 659                 0x0000FB08,
 660                 0x0000FE04,
 661         };
 662
 663         const u32 *h_coef;
 664         const u32 *hv_coef;
 665         const u32 *hv_coef_mod;
 666         const u32 *v_coef;
 667         int i;
 668
 669         if (hscaleup)
 670                 h_coef = coef_hup;
 671         else
 672                 h_coef = coef_hdown;
 673
 674         if (vscaleup) {
 675                 hv_coef = coef_hvup[five_taps];
 676                 v_coef = coef_vup;
 677
 678                 if (hscaleup)
 679                         hv_coef_mod = NULL;
 680                 else
 681                         hv_coef_mod = coef_hvdown[five_taps];
 682         } else {
 683                 hv_coef = coef_hvdown[five_taps];
 684                 v_coef = coef_vdown;
 685
 686                 if (hscaleup)
 687                         hv_coef_mod = coef_hvup[five_taps];
 688                 else
 689                         hv_coef_mod = NULL;
 690         }
 691
 692         for (i = 0; i < 8; i++) {
 693                 u32 h, hv;
 694
 695                 h = h_coef[i];
 696
 697                 hv = hv_coef[i];
 698
 699                 if (hv_coef_mod) {
 700                         hv &= 0xffffff00;
 701                         hv |= (hv_coef_mod[i] & 0xff);
 702                 }
 703
 704                 _dispc_write_firh_reg(plane, i, h);
 705                 _dispc_write_firhv_reg(plane, i, hv);
 706         }
 707
 708         if (!five_taps)
 709                 return;
 710
 711         for (i = 0; i < 8; i++) {
 712                 u32 v;
 713                 v = v_coef[i];
 714                 _dispc_write_firv_reg(plane, i, v);
 715         }
 716 }
 717
 718 static void _dispc_setup_color_conv_coef(void)
 719 {
 720         const struct color_conv_coef {
 721                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 722                 int  full_range;
 723         }  ctbl_bt601_5 = {
 724                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 725         };
 726
 727         const struct color_conv_coef *ct;
 728
 729 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 730
 731         ct = &ctbl_bt601_5;
 732
 733         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 734         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 735         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 736         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 737         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 738
 739         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 740         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 741         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 742         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 743         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 744
 745 #undef CVAL
 746
 747         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 748         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 749 }
 750
 751
 752 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 753 {
 754         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 755                 DISPC_VID_BA0(0),
 756                 DISPC_VID_BA0(1) };
 757
 758         dispc_write_reg(ba0_reg[plane], paddr);
 759 }
 760
 761 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 762 {
 763         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 764                                       DISPC_VID_BA1(0),
 765                                       DISPC_VID_BA1(1) };
 766
 767         dispc_write_reg(ba1_reg[plane], paddr);
 768 }
 769
 770 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 771 {
 772         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 773                                       DISPC_VID_POSITION(0),
 774                                       DISPC_VID_POSITION(1) };
 775
 776         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 777         dispc_write_reg(pos_reg[plane], val);
 778 }
 779
 780 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 781 {
 782         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 783                                       DISPC_VID_PICTURE_SIZE(0),
 784                                       DISPC_VID_PICTURE_SIZE(1) };
 785         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 786         dispc_write_reg(siz_reg[plane], val);
 787 }
 788
 789 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 790 {
 791         u32 val;
 792         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 793                                       DISPC_VID_SIZE(1) };
 794
 795         BUG_ON(plane == OMAP_DSS_GFX);
 796
 797         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 798         dispc_write_reg(vsi_reg[plane-1], val);
 799 }
 800
 801 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 802 {
 803
 804         BUG_ON(plane == OMAP_DSS_VIDEO1);
 805
 806         if (cpu_is_omap24xx())
 807                 return;
 808
 809         if (plane == OMAP_DSS_GFX)
 810                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 811         else if (plane == OMAP_DSS_VIDEO2)
 812                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 813 }
 814
 815 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 816 {
 817         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 818                                      DISPC_VID_PIXEL_INC(0),
 819                                      DISPC_VID_PIXEL_INC(1) };
 820
 821         dispc_write_reg(ri_reg[plane], inc);
 822 }
 823
 824 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 825 {
 826         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 827                                      DISPC_VID_ROW_INC(0),
 828                                      DISPC_VID_ROW_INC(1) };
 829
 830         dispc_write_reg(ri_reg[plane], inc);
 831 }
 832
 833 static void _dispc_set_color_mode(enum omap_plane plane,
 834                 enum omap_color_mode color_mode)
 835 {
 836         u32 m = 0;
 837
 838         switch (color_mode) {
 839         case OMAP_DSS_COLOR_CLUT1:
 840                 m = 0x0; break;
 841         case OMAP_DSS_COLOR_CLUT2:
 842                 m = 0x1; break;
 843         case OMAP_DSS_COLOR_CLUT4:
 844                 m = 0x2; break;
 845         case OMAP_DSS_COLOR_CLUT8:
 846                 m = 0x3; break;
 847         case OMAP_DSS_COLOR_RGB12U:
 848                 m = 0x4; break;
 849         case OMAP_DSS_COLOR_ARGB16:
 850                 m = 0x5; break;
 851         case OMAP_DSS_COLOR_RGB16:
 852                 m = 0x6; break;
 853         case OMAP_DSS_COLOR_RGB24U:
 854                 m = 0x8; break;
 855         case OMAP_DSS_COLOR_RGB24P:
 856                 m = 0x9; break;
 857         case OMAP_DSS_COLOR_YUV2:
 858                 m = 0xa; break;
 859         case OMAP_DSS_COLOR_UYVY:
 860                 m = 0xb; break;
 861         case OMAP_DSS_COLOR_ARGB32:
 862                 m = 0xc; break;
 863         case OMAP_DSS_COLOR_RGBA32:
 864                 m = 0xd; break;
 865         case OMAP_DSS_COLOR_RGBX32:
 866                 m = 0xe; break;
 867         default:
 868                 BUG(); break;
 869         }
 870
 871         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 872 }
 873
 874 static void _dispc_set_channel_out(enum omap_plane plane,
 875                 enum omap_channel channel)
 876 {
 877         int shift;
 878         u32 val;
 879
 880         switch (plane) {
 881         case OMAP_DSS_GFX:
 882                 shift = 8;
 883                 break;
 884         case OMAP_DSS_VIDEO1:
 885         case OMAP_DSS_VIDEO2:
 886                 shift = 16;
 887                 break;
 888         default:
 889                 BUG();
 890                 return;
 891         }
 892
 893         val = dispc_read_reg(dispc_reg_att[plane]);
 894         val = FLD_MOD(val, channel, shift, shift);
 895         dispc_write_reg(dispc_reg_att[plane], val);
 896 }
 897
 898 void dispc_set_burst_size(enum omap_plane plane,
 899                 enum omap_burst_size burst_size)
 900 {
 901         int shift;
 902         u32 val;
 903
 904         enable_clocks(1);
 905
 906         switch (plane) {
 907         case OMAP_DSS_GFX:
 908                 shift = 6;
 909                 break;
 910         case OMAP_DSS_VIDEO1:
 911         case OMAP_DSS_VIDEO2:
 912                 shift = 14;
 913                 break;
 914         default:
 915                 BUG();
 916                 return;
 917         }
 918
 919         val = dispc_read_reg(dispc_reg_att[plane]);
 920         val = FLD_MOD(val, burst_size, shift+1, shift);
 921         dispc_write_reg(dispc_reg_att[plane], val);
 922
 923         enable_clocks(0);
 924 }
 925
 926 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 927 {
 928         u32 val;
 929
 930         BUG_ON(plane == OMAP_DSS_GFX);
 931
 932         val = dispc_read_reg(dispc_reg_att[plane]);
 933         val = FLD_MOD(val, enable, 9, 9);
 934         dispc_write_reg(dispc_reg_att[plane], val);
 935 }
 936
 937 void dispc_enable_replication(enum omap_plane plane, bool enable)
 938 {
 939         int bit;
 940
 941         if (plane == OMAP_DSS_GFX)
 942                 bit = 5;
 943         else
 944                 bit = 10;
 945
 946         enable_clocks(1);
 947         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
 948         enable_clocks(0);
 949 }
 950
 951 void dispc_set_lcd_size(u16 width, u16 height)
 952 {
 953         u32 val;
 954         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 955         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 956         enable_clocks(1);
 957         dispc_write_reg(DISPC_SIZE_LCD, val);
 958         enable_clocks(0);
 959 }
 960
 961 void dispc_set_digit_size(u16 width, u16 height)
 962 {
 963         u32 val;
 964         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 965         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 966         enable_clocks(1);
 967         dispc_write_reg(DISPC_SIZE_DIG, val);
 968         enable_clocks(0);
 969 }
 970
 971 static void dispc_read_plane_fifo_sizes(void)
 972 {
 973         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 974                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 975                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 976         u32 size;
 977         int plane;
 978
 979         enable_clocks(1);
 980
 981         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
 982                 if (cpu_is_omap24xx())
 983                         size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 984                 else if (cpu_is_omap34xx())
 985                         size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 986                 else
 987                         BUG();
 988
 989                 dispc.fifo_size[plane] = size;
 990         }
 991
 992         enable_clocks(0);
 993 }
 994
 995 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 996 {
 997         return dispc.fifo_size[plane];
 998 }
 999
1000 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1001 {
1002         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1003                                        DISPC_VID_FIFO_THRESHOLD(0),
1004                                        DISPC_VID_FIFO_THRESHOLD(1) };
1005         enable_clocks(1);
1006
1007         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1008                         plane,
1009                         REG_GET(ftrs_reg[plane], 11, 0),
1010                         REG_GET(ftrs_reg[plane], 27, 16),
1011                         low, high);
1012
1013         if (cpu_is_omap24xx())
1014                 dispc_write_reg(ftrs_reg[plane],
1015                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
1016         else
1017                 dispc_write_reg(ftrs_reg[plane],
1018                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
1019
1020         enable_clocks(0);
1021 }
1022
1023 void dispc_enable_fifomerge(bool enable)
1024 {
1025         enable_clocks(1);
1026
1027         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1028         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1029
1030         enable_clocks(0);
1031 }
1032
1033 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1034 {
1035         u32 val;
1036         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1037                                       DISPC_VID_FIR(1) };
1038
1039         BUG_ON(plane == OMAP_DSS_GFX);
1040
1041         if (cpu_is_omap24xx())
1042                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1043         else
1044                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1045         dispc_write_reg(fir_reg[plane-1], val);
1046 }
1047
1048 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1049 {
1050         u32 val;
1051         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1052                                       DISPC_VID_ACCU0(1) };
1053
1054         BUG_ON(plane == OMAP_DSS_GFX);
1055
1056         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1057         dispc_write_reg(ac0_reg[plane-1], val);
1058 }
1059
1060 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1061 {
1062         u32 val;
1063         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1064                                       DISPC_VID_ACCU1(1) };
1065
1066         BUG_ON(plane == OMAP_DSS_GFX);
1067
1068         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1069         dispc_write_reg(ac1_reg[plane-1], val);
1070 }
1071
1072
1073 static void _dispc_set_scaling(enum omap_plane plane,
1074                 u16 orig_width, u16 orig_height,
1075                 u16 out_width, u16 out_height,
1076                 bool ilace, bool five_taps,
1077                 bool fieldmode)
1078 {
1079         int fir_hinc;
1080         int fir_vinc;
1081         int hscaleup, vscaleup;
1082         int accu0 = 0;
1083         int accu1 = 0;
1084         u32 l;
1085
1086         BUG_ON(plane == OMAP_DSS_GFX);
1087
1088         hscaleup = orig_width <= out_width;
1089         vscaleup = orig_height <= out_height;
1090
1091         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1092
1093         if (!orig_width || orig_width == out_width)
1094                 fir_hinc = 0;
1095         else
1096                 fir_hinc = 1024 * orig_width / out_width;
1097
1098         if (!orig_height || orig_height == out_height)
1099                 fir_vinc = 0;
1100         else
1101                 fir_vinc = 1024 * orig_height / out_height;
1102
1103         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1104
1105         l = dispc_read_reg(dispc_reg_att[plane]);
1106         l &= ~((0x0f << 5) | (0x3 << 21));
1107
1108         l |= fir_hinc ? (1 << 5) : 0;
1109         l |= fir_vinc ? (1 << 6) : 0;
1110
1111         l |= hscaleup ? 0 : (1 << 7);
1112         l |= vscaleup ? 0 : (1 << 8);
1113
1114         l |= five_taps ? (1 << 21) : 0;
1115         l |= five_taps ? (1 << 22) : 0;
1116
1117         dispc_write_reg(dispc_reg_att[plane], l);
1118
1119         /*
1120          * field 0 = even field = bottom field
1121          * field 1 = odd field = top field
1122          */
1123         if (ilace && !fieldmode) {
1124                 accu1 = 0;
1125                 accu0 = (fir_vinc / 2) & 0x3ff;
1126                 if (accu0 >= 1024/2) {
1127                         accu1 = 1024/2;
1128                         accu0 -= accu1;
1129                 }
1130         }
1131
1132         _dispc_set_vid_accu0(plane, 0, accu0);
1133         _dispc_set_vid_accu1(plane, 0, accu1);
1134 }
1135
1136 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1137                 bool mirroring, enum omap_color_mode color_mode)
1138 {
1139         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1140                         color_mode == OMAP_DSS_COLOR_UYVY) {
1141                 int vidrot = 0;
1142
1143                 if (mirroring) {
1144                         switch (rotation) {
1145                         case OMAP_DSS_ROT_0:
1146                                 vidrot = 2;
1147                                 break;
1148                         case OMAP_DSS_ROT_90:
1149                                 vidrot = 1;
1150                                 break;
1151                         case OMAP_DSS_ROT_180:
1152                                 vidrot = 0;
1153                                 break;
1154                         case OMAP_DSS_ROT_270:
1155                                 vidrot = 3;
1156                                 break;
1157                         }
1158                 } else {
1159                         switch (rotation) {
1160                         case OMAP_DSS_ROT_0:
1161                                 vidrot = 0;
1162                                 break;
1163                         case OMAP_DSS_ROT_90:
1164                                 vidrot = 1;
1165                                 break;
1166                         case OMAP_DSS_ROT_180:
1167                                 vidrot = 2;
1168                                 break;
1169                         case OMAP_DSS_ROT_270:
1170                                 vidrot = 3;
1171                                 break;
1172                         }
1173                 }
1174
1175                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1176
1177                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1178                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1179                 else
1180                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1181         } else {
1182                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1183                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1184         }
1185 }
1186
1187 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1188 {
1189         switch (color_mode) {
1190         case OMAP_DSS_COLOR_CLUT1:
1191                 return 1;
1192         case OMAP_DSS_COLOR_CLUT2:
1193                 return 2;
1194         case OMAP_DSS_COLOR_CLUT4:
1195                 return 4;
1196         case OMAP_DSS_COLOR_CLUT8:
1197                 return 8;
1198         case OMAP_DSS_COLOR_RGB12U:
1199         case OMAP_DSS_COLOR_RGB16:
1200         case OMAP_DSS_COLOR_ARGB16:
1201         case OMAP_DSS_COLOR_YUV2:
1202         case OMAP_DSS_COLOR_UYVY:
1203                 return 16;
1204         case OMAP_DSS_COLOR_RGB24P:
1205                 return 24;
1206         case OMAP_DSS_COLOR_RGB24U:
1207         case OMAP_DSS_COLOR_ARGB32:
1208         case OMAP_DSS_COLOR_RGBA32:
1209         case OMAP_DSS_COLOR_RGBX32:
1210                 return 32;
1211         default:
1212                 BUG();
1213         }
1214 }
1215
1216 static s32 pixinc(int pixels, u8 ps)
1217 {
1218         if (pixels == 1)
1219                 return 1;
1220         else if (pixels > 1)
1221                 return 1 + (pixels - 1) * ps;
1222         else if (pixels < 0)
1223                 return 1 - (-pixels + 1) * ps;
1224         else
1225                 BUG();
1226 }
1227
1228 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1229                 u16 screen_width,
1230                 u16 width, u16 height,
1231                 enum omap_color_mode color_mode, bool fieldmode,
1232                 unsigned int field_offset,
1233                 unsigned *offset0, unsigned *offset1,
1234                 s32 *row_inc, s32 *pix_inc)
1235 {
1236         u8 ps;
1237
1238         /* FIXME CLUT formats */
1239         switch (color_mode) {
1240         case OMAP_DSS_COLOR_CLUT1:
1241         case OMAP_DSS_COLOR_CLUT2:
1242         case OMAP_DSS_COLOR_CLUT4:
1243         case OMAP_DSS_COLOR_CLUT8:
1244                 BUG();
1245                 return;
1246         case OMAP_DSS_COLOR_YUV2:
1247         case OMAP_DSS_COLOR_UYVY:
1248                 ps = 4;
1249                 break;
1250         default:
1251                 ps = color_mode_to_bpp(color_mode) / 8;
1252                 break;
1253         }
1254
1255         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1256                         width, height);
1257
1258         /*
1259          * field 0 = even field = bottom field
1260          * field 1 = odd field = top field
1261          */
1262         switch (rotation + mirror * 4) {
1263         case OMAP_DSS_ROT_0:
1264         case OMAP_DSS_ROT_180:
1265                 /*
1266                  * If the pixel format is YUV or UYVY divide the width
1267                  * of the image by 2 for 0 and 180 degree rotation.
1268                  */
1269                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1270                         color_mode == OMAP_DSS_COLOR_UYVY)
1271                         width = width >> 1;
1272         case OMAP_DSS_ROT_90:
1273         case OMAP_DSS_ROT_270:
1274                 *offset1 = 0;
1275                 if (field_offset)
1276                         *offset0 = field_offset * screen_width * ps;
1277                 else
1278                         *offset0 = 0;
1279
1280                 *row_inc = pixinc(1 + (screen_width - width) +
1281                                 (fieldmode ? screen_width : 0),
1282                                 ps);
1283                 *pix_inc = pixinc(1, ps);
1284                 break;
1285
1286         case OMAP_DSS_ROT_0 + 4:
1287         case OMAP_DSS_ROT_180 + 4:
1288                 /* If the pixel format is YUV or UYVY divide the width
1289                  * of the image by 2  for 0 degree and 180 degree
1290                  */
1291                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1292                         color_mode == OMAP_DSS_COLOR_UYVY)
1293                         width = width >> 1;
1294         case OMAP_DSS_ROT_90 + 4:
1295         case OMAP_DSS_ROT_270 + 4:
1296                 *offset1 = 0;
1297                 if (field_offset)
1298                         *offset0 = field_offset * screen_width * ps;
1299                 else
1300                         *offset0 = 0;
1301                 *row_inc = pixinc(1 - (screen_width + width) -
1302                                 (fieldmode ? screen_width : 0),
1303                                 ps);
1304                 *pix_inc = pixinc(1, ps);
1305                 break;
1306
1307         default:
1308                 BUG();
1309         }
1310 }
1311
1312 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1313                 u16 screen_width,
1314                 u16 width, u16 height,
1315                 enum omap_color_mode color_mode, bool fieldmode,
1316                 unsigned int field_offset,
1317                 unsigned *offset0, unsigned *offset1,
1318                 s32 *row_inc, s32 *pix_inc)
1319 {
1320         u8 ps;
1321         u16 fbw, fbh;
1322
1323         /* FIXME CLUT formats */
1324         switch (color_mode) {
1325         case OMAP_DSS_COLOR_CLUT1:
1326         case OMAP_DSS_COLOR_CLUT2:
1327         case OMAP_DSS_COLOR_CLUT4:
1328         case OMAP_DSS_COLOR_CLUT8:
1329                 BUG();
1330                 return;
1331         default:
1332                 ps = color_mode_to_bpp(color_mode) / 8;
1333                 break;
1334         }
1335
1336         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1337                         width, height);
1338
1339         /* width & height are overlay sizes, convert to fb sizes */
1340
1341         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1342                 fbw = width;
1343                 fbh = height;
1344         } else {
1345                 fbw = height;
1346                 fbh = width;
1347         }
1348
1349         /*
1350          * field 0 = even field = bottom field
1351          * field 1 = odd field = top field
1352          */
1353         switch (rotation + mirror * 4) {
1354         case OMAP_DSS_ROT_0:
1355                 *offset1 = 0;
1356                 if (field_offset)
1357                         *offset0 = *offset1 + field_offset * screen_width * ps;
1358                 else
1359                         *offset0 = *offset1;
1360                 *row_inc = pixinc(1 + (screen_width - fbw) +
1361                                 (fieldmode ? screen_width : 0),
1362                                 ps);
1363                 *pix_inc = pixinc(1, ps);
1364                 break;
1365         case OMAP_DSS_ROT_90:
1366                 *offset1 = screen_width * (fbh - 1) * ps;
1367                 if (field_offset)
1368                         *offset0 = *offset1 + field_offset * ps;
1369                 else
1370                         *offset0 = *offset1;
1371                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1372                                 (fieldmode ? 1 : 0), ps);
1373                 *pix_inc = pixinc(-screen_width, ps);
1374                 break;
1375         case OMAP_DSS_ROT_180:
1376                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1377                 if (field_offset)
1378                         *offset0 = *offset1 - field_offset * screen_width * ps;
1379                 else
1380                         *offset0 = *offset1;
1381                 *row_inc = pixinc(-1 -
1382                                 (screen_width - fbw) -
1383                                 (fieldmode ? screen_width : 0),
1384                                 ps);
1385                 *pix_inc = pixinc(-1, ps);
1386                 break;
1387         case OMAP_DSS_ROT_270:
1388                 *offset1 = (fbw - 1) * ps;
1389                 if (field_offset)
1390                         *offset0 = *offset1 - field_offset * ps;
1391                 else
1392                         *offset0 = *offset1;
1393                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1394                                 (fieldmode ? 1 : 0), ps);
1395                 *pix_inc = pixinc(screen_width, ps);
1396                 break;
1397
1398         /* mirroring */
1399         case OMAP_DSS_ROT_0 + 4:
1400                 *offset1 = (fbw - 1) * ps;
1401                 if (field_offset)
1402                         *offset0 = *offset1 + field_offset * screen_width * ps;
1403                 else
1404                         *offset0 = *offset1;
1405                 *row_inc = pixinc(screen_width * 2 - 1 +
1406                                 (fieldmode ? screen_width : 0),
1407                                 ps);
1408                 *pix_inc = pixinc(-1, ps);
1409                 break;
1410
1411         case OMAP_DSS_ROT_90 + 4:
1412                 *offset1 = 0;
1413                 if (field_offset)
1414                         *offset0 = *offset1 + field_offset * ps;
1415                 else
1416                         *offset0 = *offset1;
1417                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1418                                 (fieldmode ? 1 : 0),
1419                                 ps);
1420                 *pix_inc = pixinc(screen_width, ps);
1421                 break;
1422
1423         case OMAP_DSS_ROT_180 + 4:
1424                 *offset1 = screen_width * (fbh - 1) * ps;
1425                 if (field_offset)
1426                         *offset0 = *offset1 - field_offset * screen_width * ps;
1427                 else
1428                         *offset0 = *offset1;
1429                 *row_inc = pixinc(1 - screen_width * 2 -
1430                                 (fieldmode ? screen_width : 0),
1431                                 ps);
1432                 *pix_inc = pixinc(1, ps);
1433                 break;
1434
1435         case OMAP_DSS_ROT_270 + 4:
1436                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1437                 if (field_offset)
1438                         *offset0 = *offset1 - field_offset * ps;
1439                 else
1440                         *offset0 = *offset1;
1441                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1442                                 (fieldmode ? 1 : 0),
1443                                 ps);
1444                 *pix_inc = pixinc(-screen_width, ps);
1445                 break;
1446
1447         default:
1448                 BUG();
1449         }
1450 }
1451
1452 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1453                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1454 {
1455         u32 fclk = 0;
1456         /* FIXME venc pclk? */
1457         u64 tmp, pclk = dispc_pclk_rate();
1458
1459         if (height > out_height) {
1460                 /* FIXME get real display PPL */
1461                 unsigned int ppl = 800;
1462
1463                 tmp = pclk * height * out_width;
1464                 do_div(tmp, 2 * out_height * ppl);
1465                 fclk = tmp;
1466
1467                 if (height > 2 * out_height) {
1468                         if (ppl == out_width)
1469                                 return 0;
1470
1471                         tmp = pclk * (height - 2 * out_height) * out_width;
1472                         do_div(tmp, 2 * out_height * (ppl - out_width));
1473                         fclk = max(fclk, (u32) tmp);
1474                 }
1475         }
1476
1477         if (width > out_width) {
1478                 tmp = pclk * width;
1479                 do_div(tmp, out_width);
1480                 fclk = max(fclk, (u32) tmp);
1481
1482                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1483                         fclk <<= 1;
1484         }
1485
1486         return fclk;
1487 }
1488
1489 static unsigned long calc_fclk(u16 width, u16 height,
1490                 u16 out_width, u16 out_height)
1491 {
1492         unsigned int hf, vf;
1493
1494         /*
1495          * FIXME how to determine the 'A' factor
1496          * for the no downscaling case ?
1497          */
1498
1499         if (width > 3 * out_width)
1500                 hf = 4;
1501         else if (width > 2 * out_width)
1502                 hf = 3;
1503         else if (width > out_width)
1504                 hf = 2;
1505         else
1506                 hf = 1;
1507
1508         if (height > out_height)
1509                 vf = 2;
1510         else
1511                 vf = 1;
1512
1513         /* FIXME venc pclk? */
1514         return dispc_pclk_rate() * vf * hf;
1515 }
1516
1517 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1518 {
1519         enable_clocks(1);
1520         _dispc_set_channel_out(plane, channel_out);
1521         enable_clocks(0);
1522 }
1523
1524 static int _dispc_setup_plane(enum omap_plane plane,
1525                 u32 paddr, u16 screen_width,
1526                 u16 pos_x, u16 pos_y,
1527                 u16 width, u16 height,
1528                 u16 out_width, u16 out_height,
1529                 enum omap_color_mode color_mode,
1530                 bool ilace,
1531                 enum omap_dss_rotation_type rotation_type,
1532                 u8 rotation, int mirror,
1533                 u8 global_alpha)
1534 {
1535         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1536         bool five_taps = 0;
1537         bool fieldmode = 0;
1538         int cconv = 0;
1539         unsigned offset0, offset1;
1540         s32 row_inc;
1541         s32 pix_inc;
1542         u16 frame_height = height;
1543         unsigned int field_offset = 0;
1544
1545         if (paddr == 0)
1546                 return -EINVAL;
1547
1548         if (ilace && height == out_height)
1549                 fieldmode = 1;
1550
1551         if (ilace) {
1552                 if (fieldmode)
1553                         height /= 2;
1554                 pos_y /= 2;
1555                 out_height /= 2;
1556
1557                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1558                                 "out_height %d\n",
1559                                 height, pos_y, out_height);
1560         }
1561
1562         if (plane == OMAP_DSS_GFX) {
1563                 if (width != out_width || height != out_height)
1564                         return -EINVAL;
1565
1566                 switch (color_mode) {
1567                 case OMAP_DSS_COLOR_ARGB16:
1568                 case OMAP_DSS_COLOR_ARGB32:
1569                 case OMAP_DSS_COLOR_RGBA32:
1570                 case OMAP_DSS_COLOR_RGBX32:
1571                         if (cpu_is_omap24xx())
1572                                 return -EINVAL;
1573                         /* fall through */
1574                 case OMAP_DSS_COLOR_RGB12U:
1575                 case OMAP_DSS_COLOR_RGB16:
1576                 case OMAP_DSS_COLOR_RGB24P:
1577                 case OMAP_DSS_COLOR_RGB24U:
1578                         break;
1579
1580                 default:
1581                         return -EINVAL;
1582                 }
1583         } else {
1584                 /* video plane */
1585
1586                 unsigned long fclk = 0;
1587
1588                 if (out_width < width / maxdownscale ||
1589                    out_width > width * 8)
1590                         return -EINVAL;
1591
1592                 if (out_height < height / maxdownscale ||
1593                    out_height > height * 8)
1594                         return -EINVAL;
1595
1596                 switch (color_mode) {
1597                 case OMAP_DSS_COLOR_RGBX32:
1598                 case OMAP_DSS_COLOR_RGB12U:
1599                         if (cpu_is_omap24xx())
1600                                 return -EINVAL;
1601                         /* fall through */
1602                 case OMAP_DSS_COLOR_RGB16:
1603                 case OMAP_DSS_COLOR_RGB24P:
1604                 case OMAP_DSS_COLOR_RGB24U:
1605                         break;
1606
1607                 case OMAP_DSS_COLOR_ARGB16:
1608                 case OMAP_DSS_COLOR_ARGB32:
1609                 case OMAP_DSS_COLOR_RGBA32:
1610                         if (cpu_is_omap24xx())
1611                                 return -EINVAL;
1612                         if (plane == OMAP_DSS_VIDEO1)
1613                                 return -EINVAL;
1614                         break;
1615
1616                 case OMAP_DSS_COLOR_YUV2:
1617                 case OMAP_DSS_COLOR_UYVY:
1618                         cconv = 1;
1619                         break;
1620
1621                 default:
1622                         return -EINVAL;
1623                 }
1624
1625                 /* Must use 5-tap filter? */
1626                 five_taps = height > out_height * 2;
1627
1628                 if (!five_taps) {
1629                         fclk = calc_fclk(width, height,
1630                                         out_width, out_height);
1631
1632                         /* Try 5-tap filter if 3-tap fclk is too high */
1633                         if (cpu_is_omap34xx() && height > out_height &&
1634                                         fclk > dispc_fclk_rate())
1635                                 five_taps = true;
1636                 }
1637
1638                 if (width > (2048 >> five_taps)) {
1639                         DSSERR("failed to set up scaling, fclk too low\n");
1640                         return -EINVAL;
1641                 }
1642
1643                 if (five_taps)
1644                         fclk = calc_fclk_five_taps(width, height,
1645                                         out_width, out_height, color_mode);
1646
1647                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1648                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1649
1650                 if (!fclk || fclk > dispc_fclk_rate()) {
1651                         DSSERR("failed to set up scaling, "
1652                                         "required fclk rate = %lu Hz, "
1653                                         "current fclk rate = %lu Hz\n",
1654                                         fclk, dispc_fclk_rate());
1655                         return -EINVAL;
1656                 }
1657         }
1658
1659         if (ilace && !fieldmode) {
1660                 /*
1661                  * when downscaling the bottom field may have to start several
1662                  * source lines below the top field. Unfortunately ACCUI
1663                  * registers will only hold the fractional part of the offset
1664                  * so the integer part must be added to the base address of the
1665                  * bottom field.
1666                  */
1667                 if (!height || height == out_height)
1668                         field_offset = 0;
1669                 else
1670                         field_offset = height / out_height / 2;
1671         }
1672
1673         /* Fields are independent but interleaved in memory. */
1674         if (fieldmode)
1675                 field_offset = 1;
1676
1677         if (rotation_type == OMAP_DSS_ROT_DMA)
1678                 calc_dma_rotation_offset(rotation, mirror,
1679                                 screen_width, width, frame_height, color_mode,
1680                                 fieldmode, field_offset,
1681                                 &offset0, &offset1, &row_inc, &pix_inc);
1682         else
1683                 calc_vrfb_rotation_offset(rotation, mirror,
1684                                 screen_width, width, frame_height, color_mode,
1685                                 fieldmode, field_offset,
1686                                 &offset0, &offset1, &row_inc, &pix_inc);
1687
1688         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1689                         offset0, offset1, row_inc, pix_inc);
1690
1691         _dispc_set_color_mode(plane, color_mode);
1692
1693         _dispc_set_plane_ba0(plane, paddr + offset0);
1694         _dispc_set_plane_ba1(plane, paddr + offset1);
1695
1696         _dispc_set_row_inc(plane, row_inc);
1697         _dispc_set_pix_inc(plane, pix_inc);
1698
1699         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1700                         out_width, out_height);
1701
1702         _dispc_set_plane_pos(plane, pos_x, pos_y);
1703
1704         _dispc_set_pic_size(plane, width, height);
1705
1706         if (plane != OMAP_DSS_GFX) {
1707                 _dispc_set_scaling(plane, width, height,
1708                                    out_width, out_height,
1709                                    ilace, five_taps, fieldmode);
1710                 _dispc_set_vid_size(plane, out_width, out_height);
1711                 _dispc_set_vid_color_conv(plane, cconv);
1712         }
1713
1714         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1715
1716         if (plane != OMAP_DSS_VIDEO1)
1717                 _dispc_setup_global_alpha(plane, global_alpha);
1718
1719         return 0;
1720 }
1721
1722 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1723 {
1724         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1725 }
1726
1727 static void dispc_disable_isr(void *data, u32 mask)
1728 {
1729         struct completion *compl = data;
1730         complete(compl);
1731 }
1732
1733 static void _enable_lcd_out(bool enable)
1734 {
1735         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1736 }
1737
1738 static void dispc_enable_lcd_out(bool enable)
1739 {
1740         struct completion frame_done_completion;
1741         bool is_on;
1742         int r;
1743
1744         enable_clocks(1);
1745
1746         /* When we disable LCD output, we need to wait until frame is done.
1747          * Otherwise the DSS is still working, and turning off the clocks
1748          * prevents DSS from going to OFF mode */
1749         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1750
1751         if (!enable && is_on) {
1752                 init_completion(&frame_done_completion);
1753
1754                 r = omap_dispc_register_isr(dispc_disable_isr,
1755                                 &frame_done_completion,
1756                                 DISPC_IRQ_FRAMEDONE);
1757
1758                 if (r)
1759                         DSSERR("failed to register FRAMEDONE isr\n");
1760         }
1761
1762         _enable_lcd_out(enable);
1763
1764         if (!enable && is_on) {
1765                 if (!wait_for_completion_timeout(&frame_done_completion,
1766                                         msecs_to_jiffies(100)))
1767                         DSSERR("timeout waiting for FRAME DONE\n");
1768
1769                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1770                                 &frame_done_completion,
1771                                 DISPC_IRQ_FRAMEDONE);
1772
1773                 if (r)
1774                         DSSERR("failed to unregister FRAMEDONE isr\n");
1775         }
1776
1777         enable_clocks(0);
1778 }
1779
1780 static void _enable_digit_out(bool enable)
1781 {
1782         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1783 }
1784
1785 static void dispc_enable_digit_out(bool enable)
1786 {
1787         struct completion frame_done_completion;
1788         int r;
1789
1790         enable_clocks(1);
1791
1792         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1793                 enable_clocks(0);
1794                 return;
1795         }
1796
1797         if (enable) {
1798                 unsigned long flags;
1799                 /* When we enable digit output, we'll get an extra digit
1800                  * sync lost interrupt, that we need to ignore */
1801                 spin_lock_irqsave(&dispc.irq_lock, flags);
1802                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1803                 _omap_dispc_set_irqs();
1804                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1805         }
1806
1807         /* When we disable digit output, we need to wait until fields are done.
1808          * Otherwise the DSS is still working, and turning off the clocks
1809          * prevents DSS from going to OFF mode. And when enabling, we need to
1810          * wait for the extra sync losts */
1811         init_completion(&frame_done_completion);
1812
1813         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1814                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1815         if (r)
1816                 DSSERR("failed to register EVSYNC isr\n");
1817
1818         _enable_digit_out(enable);
1819
1820         /* XXX I understand from TRM that we should only wait for the
1821          * current field to complete. But it seems we have to wait
1822          * for both fields */
1823         if (!wait_for_completion_timeout(&frame_done_completion,
1824                                 msecs_to_jiffies(100)))
1825                 DSSERR("timeout waiting for EVSYNC\n");
1826
1827         if (!wait_for_completion_timeout(&frame_done_completion,
1828                                 msecs_to_jiffies(100)))
1829                 DSSERR("timeout waiting for EVSYNC\n");
1830
1831         r = omap_dispc_unregister_isr(dispc_disable_isr,
1832                         &frame_done_completion,
1833                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1834         if (r)
1835                 DSSERR("failed to unregister EVSYNC isr\n");
1836
1837         if (enable) {
1838                 unsigned long flags;
1839                 spin_lock_irqsave(&dispc.irq_lock, flags);
1840                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1841                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1842                 _omap_dispc_set_irqs();
1843                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1844         }
1845
1846         enable_clocks(0);
1847 }
1848
1849 bool dispc_is_channel_enabled(enum omap_channel channel)
1850 {
1851         if (channel == OMAP_DSS_CHANNEL_LCD)
1852                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1853         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1854                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1855         else
1856                 BUG();
1857 }
1858
1859 void dispc_enable_channel(enum omap_channel channel, bool enable)
1860 {
1861         if (channel == OMAP_DSS_CHANNEL_LCD)
1862                 dispc_enable_lcd_out(enable);
1863         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1864                 dispc_enable_digit_out(enable);
1865         else
1866                 BUG();
1867 }
1868
1869 void dispc_lcd_enable_signal_polarity(bool act_high)
1870 {
1871         enable_clocks(1);
1872         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1873         enable_clocks(0);
1874 }
1875
1876 void dispc_lcd_enable_signal(bool enable)
1877 {
1878         enable_clocks(1);
1879         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1880         enable_clocks(0);
1881 }
1882
1883 void dispc_pck_free_enable(bool enable)
1884 {
1885         enable_clocks(1);
1886         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1887         enable_clocks(0);
1888 }
1889
1890 void dispc_enable_fifohandcheck(bool enable)
1891 {
1892         enable_clocks(1);
1893         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1894         enable_clocks(0);
1895 }
1896
1897
1898 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1899 {
1900         int mode;
1901
1902         switch (type) {
1903         case OMAP_DSS_LCD_DISPLAY_STN:
1904                 mode = 0;
1905                 break;
1906
1907         case OMAP_DSS_LCD_DISPLAY_TFT:
1908                 mode = 1;
1909                 break;
1910
1911         default:
1912                 BUG();
1913                 return;
1914         }
1915
1916         enable_clocks(1);
1917         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1918         enable_clocks(0);
1919 }
1920
1921 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1922 {
1923         enable_clocks(1);
1924         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1925         enable_clocks(0);
1926 }
1927
1928
1929 void dispc_set_default_color(enum omap_channel channel, u32 color)
1930 {
1931         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1932                                 DISPC_DEFAULT_COLOR1 };
1933
1934         enable_clocks(1);
1935         dispc_write_reg(def_reg[channel], color);
1936         enable_clocks(0);
1937 }
1938
1939 u32 dispc_get_default_color(enum omap_channel channel)
1940 {
1941         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1942                                 DISPC_DEFAULT_COLOR1 };
1943         u32 l;
1944
1945         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1946                channel != OMAP_DSS_CHANNEL_LCD);
1947
1948         enable_clocks(1);
1949         l = dispc_read_reg(def_reg[channel]);
1950         enable_clocks(0);
1951
1952         return l;
1953 }
1954
1955 void dispc_set_trans_key(enum omap_channel ch,
1956                 enum omap_dss_trans_key_type type,
1957                 u32 trans_key)
1958 {
1959         const struct dispc_reg tr_reg[] = {
1960                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1961
1962         enable_clocks(1);
1963         if (ch == OMAP_DSS_CHANNEL_LCD)
1964                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1965         else /* OMAP_DSS_CHANNEL_DIGIT */
1966                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1967
1968         dispc_write_reg(tr_reg[ch], trans_key);
1969         enable_clocks(0);
1970 }
1971
1972 void dispc_get_trans_key(enum omap_channel ch,
1973                 enum omap_dss_trans_key_type *type,
1974                 u32 *trans_key)
1975 {
1976         const struct dispc_reg tr_reg[] = {
1977                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1978
1979         enable_clocks(1);
1980         if (type) {
1981                 if (ch == OMAP_DSS_CHANNEL_LCD)
1982                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1983                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1984                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1985                 else
1986                         BUG();
1987         }
1988
1989         if (trans_key)
1990                 *trans_key = dispc_read_reg(tr_reg[ch]);
1991         enable_clocks(0);
1992 }
1993
1994 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1995 {
1996         enable_clocks(1);
1997         if (ch == OMAP_DSS_CHANNEL_LCD)
1998                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1999         else /* OMAP_DSS_CHANNEL_DIGIT */
2000                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2001         enable_clocks(0);
2002 }
2003 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2004 {
2005         if (cpu_is_omap24xx())
2006                 return;
2007
2008         enable_clocks(1);
2009         if (ch == OMAP_DSS_CHANNEL_LCD)
2010                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2011         else /* OMAP_DSS_CHANNEL_DIGIT */
2012                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2013         enable_clocks(0);
2014 }
2015 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2016 {
2017         bool enabled;
2018
2019         if (cpu_is_omap24xx())
2020                 return false;
2021
2022         enable_clocks(1);
2023         if (ch == OMAP_DSS_CHANNEL_LCD)
2024                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2025         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2026                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2027         else
2028                 BUG();
2029         enable_clocks(0);
2030
2031         return enabled;
2032
2033 }
2034
2035
2036 bool dispc_trans_key_enabled(enum omap_channel ch)
2037 {
2038         bool enabled;
2039
2040         enable_clocks(1);
2041         if (ch == OMAP_DSS_CHANNEL_LCD)
2042                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2043         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2044                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2045         else
2046                 BUG();
2047         enable_clocks(0);
2048
2049         return enabled;
2050 }
2051
2052
2053 void dispc_set_tft_data_lines(u8 data_lines)
2054 {
2055         int code;
2056
2057         switch (data_lines) {
2058         case 12:
2059                 code = 0;
2060                 break;
2061         case 16:
2062                 code = 1;
2063                 break;
2064         case 18:
2065                 code = 2;
2066                 break;
2067         case 24:
2068                 code = 3;
2069                 break;
2070         default:
2071                 BUG();
2072                 return;
2073         }
2074
2075         enable_clocks(1);
2076         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2077         enable_clocks(0);
2078 }
2079
2080 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2081 {
2082         u32 l;
2083         int stallmode;
2084         int gpout0 = 1;
2085         int gpout1;
2086
2087         switch (mode) {
2088         case OMAP_DSS_PARALLELMODE_BYPASS:
2089                 stallmode = 0;
2090                 gpout1 = 1;
2091                 break;
2092
2093         case OMAP_DSS_PARALLELMODE_RFBI:
2094                 stallmode = 1;
2095                 gpout1 = 0;
2096                 break;
2097
2098         case OMAP_DSS_PARALLELMODE_DSI:
2099                 stallmode = 1;
2100                 gpout1 = 1;
2101                 break;
2102
2103         default:
2104                 BUG();
2105                 return;
2106         }
2107
2108         enable_clocks(1);
2109
2110         l = dispc_read_reg(DISPC_CONTROL);
2111
2112         l = FLD_MOD(l, stallmode, 11, 11);
2113         l = FLD_MOD(l, gpout0, 15, 15);
2114         l = FLD_MOD(l, gpout1, 16, 16);
2115
2116         dispc_write_reg(DISPC_CONTROL, l);
2117
2118         enable_clocks(0);
2119 }
2120
2121 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2122                 int vsw, int vfp, int vbp)
2123 {
2124         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2125                 if (hsw < 1 || hsw > 64 ||
2126                                 hfp < 1 || hfp > 256 ||
2127                                 hbp < 1 || hbp > 256 ||
2128                                 vsw < 1 || vsw > 64 ||
2129                                 vfp < 0 || vfp > 255 ||
2130                                 vbp < 0 || vbp > 255)
2131                         return false;
2132         } else {
2133                 if (hsw < 1 || hsw > 256 ||
2134                                 hfp < 1 || hfp > 4096 ||
2135                                 hbp < 1 || hbp > 4096 ||
2136                                 vsw < 1 || vsw > 256 ||
2137                                 vfp < 0 || vfp > 4095 ||
2138                                 vbp < 0 || vbp > 4095)
2139                         return false;
2140         }
2141
2142         return true;
2143 }
2144
2145 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2146 {
2147         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2148                         timings->hbp, timings->vsw,
2149                         timings->vfp, timings->vbp);
2150 }
2151
2152 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2153                                    int vsw, int vfp, int vbp)
2154 {
2155         u32 timing_h, timing_v;
2156
2157         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2158                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2159                         FLD_VAL(hbp-1, 27, 20);
2160
2161                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2162                         FLD_VAL(vbp, 27, 20);
2163         } else {
2164                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2165                         FLD_VAL(hbp-1, 31, 20);
2166
2167                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2168                         FLD_VAL(vbp, 31, 20);
2169         }
2170
2171         enable_clocks(1);
2172         dispc_write_reg(DISPC_TIMING_H, timing_h);
2173         dispc_write_reg(DISPC_TIMING_V, timing_v);
2174         enable_clocks(0);
2175 }
2176
2177 /* change name to mode? */
2178 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2179 {
2180         unsigned xtot, ytot;
2181         unsigned long ht, vt;
2182
2183         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2184                                 timings->hbp, timings->vsw,
2185                                 timings->vfp, timings->vbp))
2186                 BUG();
2187
2188         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2189                         timings->vsw, timings->vfp, timings->vbp);
2190
2191         dispc_set_lcd_size(timings->x_res, timings->y_res);
2192
2193         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2194         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2195
2196         ht = (timings->pixel_clock * 1000) / xtot;
2197         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2198
2199         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2200         DSSDBG("pck %u\n", timings->pixel_clock);
2201         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2202                         timings->hsw, timings->hfp, timings->hbp,
2203                         timings->vsw, timings->vfp, timings->vbp);
2204
2205         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2206 }
2207
2208 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2209 {
2210         BUG_ON(lck_div < 1);
2211         BUG_ON(pck_div < 2);
2212
2213         enable_clocks(1);
2214         dispc_write_reg(DISPC_DIVISOR,
2215                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2216         enable_clocks(0);
2217 }
2218
2219 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2220 {
2221         u32 l;
2222         l = dispc_read_reg(DISPC_DIVISOR);
2223         *lck_div = FLD_GET(l, 23, 16);
2224         *pck_div = FLD_GET(l, 7, 0);
2225 }
2226
2227 unsigned long dispc_fclk_rate(void)
2228 {
2229         unsigned long r = 0;
2230
2231         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2232                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2233         else
2234 #ifdef CONFIG_OMAP2_DSS_DSI
2235                 r = dsi_get_dsi1_pll_rate();
2236 #else
2237         BUG();
2238 #endif
2239         return r;
2240 }
2241
2242 unsigned long dispc_lclk_rate(void)
2243 {
2244         int lcd;
2245         unsigned long r;
2246         u32 l;
2247
2248         l = dispc_read_reg(DISPC_DIVISOR);
2249
2250         lcd = FLD_GET(l, 23, 16);
2251
2252         r = dispc_fclk_rate();
2253
2254         return r / lcd;
2255 }
2256
2257 unsigned long dispc_pclk_rate(void)
2258 {
2259         int lcd, pcd;
2260         unsigned long r;
2261         u32 l;
2262
2263         l = dispc_read_reg(DISPC_DIVISOR);
2264
2265         lcd = FLD_GET(l, 23, 16);
2266         pcd = FLD_GET(l, 7, 0);
2267
2268         r = dispc_fclk_rate();
2269
2270         return r / lcd / pcd;
2271 }
2272
2273 void dispc_dump_clocks(struct seq_file *s)
2274 {
2275         int lcd, pcd;
2276
2277         enable_clocks(1);
2278
2279         dispc_get_lcd_divisor(&lcd, &pcd);
2280
2281         seq_printf(s, "- DISPC -\n");
2282
2283         seq_printf(s, "dispc fclk source = %s\n",
2284                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2285                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2286
2287         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2288         seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2289         seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2290
2291         enable_clocks(0);
2292 }
2293
2294 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2295 void dispc_dump_irqs(struct seq_file *s)
2296 {
2297         unsigned long flags;
2298         struct dispc_irq_stats stats;
2299
2300         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2301
2302         stats = dispc.irq_stats;
2303         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2304         dispc.irq_stats.last_reset = jiffies;
2305
2306         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2307
2308         seq_printf(s, "period %u ms\n",
2309                         jiffies_to_msecs(jiffies - stats.last_reset));
2310
2311         seq_printf(s, "irqs %d\n", stats.irq_count);
2312 #define PIS(x) \
2313         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2314
2315         PIS(FRAMEDONE);
2316         PIS(VSYNC);
2317         PIS(EVSYNC_EVEN);
2318         PIS(EVSYNC_ODD);
2319         PIS(ACBIAS_COUNT_STAT);
2320         PIS(PROG_LINE_NUM);
2321         PIS(GFX_FIFO_UNDERFLOW);
2322         PIS(GFX_END_WIN);
2323         PIS(PAL_GAMMA_MASK);
2324         PIS(OCP_ERR);
2325         PIS(VID1_FIFO_UNDERFLOW);
2326         PIS(VID1_END_WIN);
2327         PIS(VID2_FIFO_UNDERFLOW);
2328         PIS(VID2_END_WIN);
2329         PIS(SYNC_LOST);
2330         PIS(SYNC_LOST_DIGIT);
2331         PIS(WAKEUP);
2332 #undef PIS
2333 }
2334 #endif
2335
2336 void dispc_dump_regs(struct seq_file *s)
2337 {
2338 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2339
2340         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2341
2342         DUMPREG(DISPC_REVISION);
2343         DUMPREG(DISPC_SYSCONFIG);
2344         DUMPREG(DISPC_SYSSTATUS);
2345         DUMPREG(DISPC_IRQSTATUS);
2346         DUMPREG(DISPC_IRQENABLE);
2347         DUMPREG(DISPC_CONTROL);
2348         DUMPREG(DISPC_CONFIG);
2349         DUMPREG(DISPC_CAPABLE);
2350         DUMPREG(DISPC_DEFAULT_COLOR0);
2351         DUMPREG(DISPC_DEFAULT_COLOR1);
2352         DUMPREG(DISPC_TRANS_COLOR0);
2353         DUMPREG(DISPC_TRANS_COLOR1);
2354         DUMPREG(DISPC_LINE_STATUS);
2355         DUMPREG(DISPC_LINE_NUMBER);
2356         DUMPREG(DISPC_TIMING_H);
2357         DUMPREG(DISPC_TIMING_V);
2358         DUMPREG(DISPC_POL_FREQ);
2359         DUMPREG(DISPC_DIVISOR);
2360         DUMPREG(DISPC_GLOBAL_ALPHA);
2361         DUMPREG(DISPC_SIZE_DIG);
2362         DUMPREG(DISPC_SIZE_LCD);
2363
2364         DUMPREG(DISPC_GFX_BA0);
2365         DUMPREG(DISPC_GFX_BA1);
2366         DUMPREG(DISPC_GFX_POSITION);
2367         DUMPREG(DISPC_GFX_SIZE);
2368         DUMPREG(DISPC_GFX_ATTRIBUTES);
2369         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2370         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2371         DUMPREG(DISPC_GFX_ROW_INC);
2372         DUMPREG(DISPC_GFX_PIXEL_INC);
2373         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2374         DUMPREG(DISPC_GFX_TABLE_BA);
2375
2376         DUMPREG(DISPC_DATA_CYCLE1);
2377         DUMPREG(DISPC_DATA_CYCLE2);
2378         DUMPREG(DISPC_DATA_CYCLE3);
2379
2380         DUMPREG(DISPC_CPR_COEF_R);
2381         DUMPREG(DISPC_CPR_COEF_G);
2382         DUMPREG(DISPC_CPR_COEF_B);
2383
2384         DUMPREG(DISPC_GFX_PRELOAD);
2385
2386         DUMPREG(DISPC_VID_BA0(0));
2387         DUMPREG(DISPC_VID_BA1(0));
2388         DUMPREG(DISPC_VID_POSITION(0));
2389         DUMPREG(DISPC_VID_SIZE(0));
2390         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2391         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2392         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2393         DUMPREG(DISPC_VID_ROW_INC(0));
2394         DUMPREG(DISPC_VID_PIXEL_INC(0));
2395         DUMPREG(DISPC_VID_FIR(0));
2396         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2397         DUMPREG(DISPC_VID_ACCU0(0));
2398         DUMPREG(DISPC_VID_ACCU1(0));
2399
2400         DUMPREG(DISPC_VID_BA0(1));
2401         DUMPREG(DISPC_VID_BA1(1));
2402         DUMPREG(DISPC_VID_POSITION(1));
2403         DUMPREG(DISPC_VID_SIZE(1));
2404         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2405         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2406         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2407         DUMPREG(DISPC_VID_ROW_INC(1));
2408         DUMPREG(DISPC_VID_PIXEL_INC(1));
2409         DUMPREG(DISPC_VID_FIR(1));
2410         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2411         DUMPREG(DISPC_VID_ACCU0(1));
2412         DUMPREG(DISPC_VID_ACCU1(1));
2413
2414         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2415         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2416         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2417         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2418         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2419         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2420         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2421         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2422         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2423         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2424         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2425         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2426         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2427         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2428         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2429         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2430         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2431         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2432         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2433         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2434         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2435         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2436         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2437         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2438         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2439         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2440         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2441         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2442         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2443
2444         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2445         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2446         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2447         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2448         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2449         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2450         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2451         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2452         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2453         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2454         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2455         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2456         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2457         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2458         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2459         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2460         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2461         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2462         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2463         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2464         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2465         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2466         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2467         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2468         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2469         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2470         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2471         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2472         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2473
2474         DUMPREG(DISPC_VID_PRELOAD(0));
2475         DUMPREG(DISPC_VID_PRELOAD(1));
2476
2477         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2478 #undef DUMPREG
2479 }
2480
2481 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2482                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2483 {
2484         u32 l = 0;
2485
2486         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2487                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2488
2489         l |= FLD_VAL(onoff, 17, 17);
2490         l |= FLD_VAL(rf, 16, 16);
2491         l |= FLD_VAL(ieo, 15, 15);
2492         l |= FLD_VAL(ipc, 14, 14);
2493         l |= FLD_VAL(ihs, 13, 13);
2494         l |= FLD_VAL(ivs, 12, 12);
2495         l |= FLD_VAL(acbi, 11, 8);
2496         l |= FLD_VAL(acb, 7, 0);
2497
2498         enable_clocks(1);
2499         dispc_write_reg(DISPC_POL_FREQ, l);
2500         enable_clocks(0);
2501 }
2502
2503 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2504 {
2505         _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2506                         (config & OMAP_DSS_LCD_RF) != 0,
2507                         (config & OMAP_DSS_LCD_IEO) != 0,
2508                         (config & OMAP_DSS_LCD_IPC) != 0,
2509                         (config & OMAP_DSS_LCD_IHS) != 0,
2510                         (config & OMAP_DSS_LCD_IVS) != 0,
2511                         acbi, acb);
2512 }
2513
2514 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2515 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2516                 struct dispc_clock_info *cinfo)
2517 {
2518         u16 pcd_min = is_tft ? 2 : 3;
2519         unsigned long best_pck;
2520         u16 best_ld, cur_ld;
2521         u16 best_pd, cur_pd;
2522
2523         best_pck = 0;
2524         best_ld = 0;
2525         best_pd = 0;
2526
2527         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2528                 unsigned long lck = fck / cur_ld;
2529
2530                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2531                         unsigned long pck = lck / cur_pd;
2532                         long old_delta = abs(best_pck - req_pck);
2533                         long new_delta = abs(pck - req_pck);
2534
2535                         if (best_pck == 0 || new_delta < old_delta) {
2536                                 best_pck = pck;
2537                                 best_ld = cur_ld;
2538                                 best_pd = cur_pd;
2539
2540                                 if (pck == req_pck)
2541                                         goto found;
2542                         }
2543
2544                         if (pck < req_pck)
2545                                 break;
2546                 }
2547
2548                 if (lck / pcd_min < req_pck)
2549                         break;
2550         }
2551
2552 found:
2553         cinfo->lck_div = best_ld;
2554         cinfo->pck_div = best_pd;
2555         cinfo->lck = fck / cinfo->lck_div;
2556         cinfo->pck = cinfo->lck / cinfo->pck_div;
2557 }
2558
2559 /* calculate clock rates using dividers in cinfo */
2560 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2561                 struct dispc_clock_info *cinfo)
2562 {
2563         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2564                 return -EINVAL;
2565         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2566                 return -EINVAL;
2567
2568         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2569         cinfo->pck = cinfo->lck / cinfo->pck_div;
2570
2571         return 0;
2572 }
2573
2574 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2575 {
2576         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2577         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2578
2579         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2580
2581         return 0;
2582 }
2583
2584 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2585 {
2586         unsigned long fck;
2587
2588         fck = dispc_fclk_rate();
2589
2590         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2591         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2592
2593         cinfo->lck = fck / cinfo->lck_div;
2594         cinfo->pck = cinfo->lck / cinfo->pck_div;
2595
2596         return 0;
2597 }
2598
2599 /* dispc.irq_lock has to be locked by the caller */
2600 static void _omap_dispc_set_irqs(void)
2601 {
2602         u32 mask;
2603         u32 old_mask;
2604         int i;
2605         struct omap_dispc_isr_data *isr_data;
2606
2607         mask = dispc.irq_error_mask;
2608
2609         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2610                 isr_data = &dispc.registered_isr[i];
2611
2612                 if (isr_data->isr == NULL)
2613                         continue;
2614
2615                 mask |= isr_data->mask;
2616         }
2617
2618         enable_clocks(1);
2619
2620         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2621         /* clear the irqstatus for newly enabled irqs */
2622         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2623
2624         dispc_write_reg(DISPC_IRQENABLE, mask);
2625
2626         enable_clocks(0);
2627 }
2628
2629 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2630 {
2631         int i;
2632         int ret;
2633         unsigned long flags;
2634         struct omap_dispc_isr_data *isr_data;
2635
2636         if (isr == NULL)
2637                 return -EINVAL;
2638
2639         spin_lock_irqsave(&dispc.irq_lock, flags);
2640
2641         /* check for duplicate entry */
2642         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2643                 isr_data = &dispc.registered_isr[i];
2644                 if (isr_data->isr == isr && isr_data->arg == arg &&
2645                                 isr_data->mask == mask) {
2646                         ret = -EINVAL;
2647                         goto err;
2648                 }
2649         }
2650
2651         isr_data = NULL;
2652         ret = -EBUSY;
2653
2654         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2655                 isr_data = &dispc.registered_isr[i];
2656
2657                 if (isr_data->isr != NULL)
2658                         continue;
2659
2660                 isr_data->isr = isr;
2661                 isr_data->arg = arg;
2662                 isr_data->mask = mask;
2663                 ret = 0;
2664
2665                 break;
2666         }
2667
2668         _omap_dispc_set_irqs();
2669
2670         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2671
2672         return 0;
2673 err:
2674         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2675
2676         return ret;
2677 }
2678 EXPORT_SYMBOL(omap_dispc_register_isr);
2679
2680 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2681 {
2682         int i;
2683         unsigned long flags;
2684         int ret = -EINVAL;
2685         struct omap_dispc_isr_data *isr_data;
2686
2687         spin_lock_irqsave(&dispc.irq_lock, flags);
2688
2689         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2690                 isr_data = &dispc.registered_isr[i];
2691                 if (isr_data->isr != isr || isr_data->arg != arg ||
2692                                 isr_data->mask != mask)
2693                         continue;
2694
2695                 /* found the correct isr */
2696
2697                 isr_data->isr = NULL;
2698                 isr_data->arg = NULL;
2699                 isr_data->mask = 0;
2700
2701                 ret = 0;
2702                 break;
2703         }
2704
2705         if (ret == 0)
2706                 _omap_dispc_set_irqs();
2707
2708         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2709
2710         return ret;
2711 }
2712 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2713
2714 #ifdef DEBUG
2715 static void print_irq_status(u32 status)
2716 {
2717         if ((status & dispc.irq_error_mask) == 0)
2718                 return;
2719
2720         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2721
2722 #define PIS(x) \
2723         if (status & DISPC_IRQ_##x) \
2724                 printk(#x " ");
2725         PIS(GFX_FIFO_UNDERFLOW);
2726         PIS(OCP_ERR);
2727         PIS(VID1_FIFO_UNDERFLOW);
2728         PIS(VID2_FIFO_UNDERFLOW);
2729         PIS(SYNC_LOST);
2730         PIS(SYNC_LOST_DIGIT);
2731 #undef PIS
2732
2733         printk("\n");
2734 }
2735 #endif
2736
2737 /* Called from dss.c. Note that we don't touch clocks here,
2738  * but we presume they are on because we got an IRQ. However,
2739  * an irq handler may turn the clocks off, so we may not have
2740  * clock later in the function. */
2741 void dispc_irq_handler(void)
2742 {
2743         int i;
2744         u32 irqstatus;
2745         u32 handledirqs = 0;
2746         u32 unhandled_errors;
2747         struct omap_dispc_isr_data *isr_data;
2748         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2749
2750         spin_lock(&dispc.irq_lock);
2751
2752         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2753
2754 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2755         spin_lock(&dispc.irq_stats_lock);
2756         dispc.irq_stats.irq_count++;
2757         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2758         spin_unlock(&dispc.irq_stats_lock);
2759 #endif
2760
2761 #ifdef DEBUG
2762         if (dss_debug)
2763                 print_irq_status(irqstatus);
2764 #endif
2765         /* Ack the interrupt. Do it here before clocks are possibly turned
2766          * off */
2767         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2768         /* flush posted write */
2769         dispc_read_reg(DISPC_IRQSTATUS);
2770
2771         /* make a copy and unlock, so that isrs can unregister
2772          * themselves */
2773         memcpy(registered_isr, dispc.registered_isr,
2774                         sizeof(registered_isr));
2775
2776         spin_unlock(&dispc.irq_lock);
2777
2778         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2779                 isr_data = &registered_isr[i];
2780
2781                 if (!isr_data->isr)
2782                         continue;
2783
2784                 if (isr_data->mask & irqstatus) {
2785                         isr_data->isr(isr_data->arg, irqstatus);
2786                         handledirqs |= isr_data->mask;
2787                 }
2788         }
2789
2790         spin_lock(&dispc.irq_lock);
2791
2792         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2793
2794         if (unhandled_errors) {
2795                 dispc.error_irqs |= unhandled_errors;
2796
2797                 dispc.irq_error_mask &= ~unhandled_errors;
2798                 _omap_dispc_set_irqs();
2799
2800                 schedule_work(&dispc.error_work);
2801         }
2802
2803         spin_unlock(&dispc.irq_lock);
2804 }
2805
2806 static void dispc_error_worker(struct work_struct *work)
2807 {
2808         int i;
2809         u32 errors;
2810         unsigned long flags;
2811
2812         spin_lock_irqsave(&dispc.irq_lock, flags);
2813         errors = dispc.error_irqs;
2814         dispc.error_irqs = 0;
2815         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2816
2817         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2818                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2819                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2820                         struct omap_overlay *ovl;
2821                         ovl = omap_dss_get_overlay(i);
2822
2823                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2824                                 continue;
2825
2826                         if (ovl->id == 0) {
2827                                 dispc_enable_plane(ovl->id, 0);
2828                                 dispc_go(ovl->manager->id);
2829                                 mdelay(50);
2830                                 break;
2831                         }
2832                 }
2833         }
2834
2835         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2836                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2837                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2838                         struct omap_overlay *ovl;
2839                         ovl = omap_dss_get_overlay(i);
2840
2841                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2842                                 continue;
2843
2844                         if (ovl->id == 1) {
2845                                 dispc_enable_plane(ovl->id, 0);
2846                                 dispc_go(ovl->manager->id);
2847                                 mdelay(50);
2848                                 break;
2849                         }
2850                 }
2851         }
2852
2853         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2854                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2855                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2856                         struct omap_overlay *ovl;
2857                         ovl = omap_dss_get_overlay(i);
2858
2859                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2860                                 continue;
2861
2862                         if (ovl->id == 2) {
2863                                 dispc_enable_plane(ovl->id, 0);
2864                                 dispc_go(ovl->manager->id);
2865                                 mdelay(50);
2866                                 break;
2867                         }
2868                 }
2869         }
2870
2871         if (errors & DISPC_IRQ_SYNC_LOST) {
2872                 struct omap_overlay_manager *manager = NULL;
2873                 bool enable = false;
2874
2875                 DSSERR("SYNC_LOST, disabling LCD\n");
2876
2877                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2878                         struct omap_overlay_manager *mgr;
2879                         mgr = omap_dss_get_overlay_manager(i);
2880
2881                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2882                                 manager = mgr;
2883                                 enable = mgr->device->state ==
2884                                                 OMAP_DSS_DISPLAY_ACTIVE;
2885                                 mgr->device->driver->disable(mgr->device);
2886                                 break;
2887                         }
2888                 }
2889
2890                 if (manager) {
2891                         struct omap_dss_device *dssdev = manager->device;
2892                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2893                                 struct omap_overlay *ovl;
2894                                 ovl = omap_dss_get_overlay(i);
2895
2896                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2897                                         continue;
2898
2899                                 if (ovl->id != 0 && ovl->manager == manager)
2900                                         dispc_enable_plane(ovl->id, 0);
2901                         }
2902
2903                         dispc_go(manager->id);
2904                         mdelay(50);
2905                         if (enable)
2906                                 dssdev->driver->enable(dssdev);
2907                 }
2908         }
2909
2910         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2911                 struct omap_overlay_manager *manager = NULL;
2912                 bool enable = false;
2913
2914                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2915
2916                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2917                         struct omap_overlay_manager *mgr;
2918                         mgr = omap_dss_get_overlay_manager(i);
2919
2920                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2921                                 manager = mgr;
2922                                 enable = mgr->device->state ==
2923                                                 OMAP_DSS_DISPLAY_ACTIVE;
2924                                 mgr->device->driver->disable(mgr->device);
2925                                 break;
2926                         }
2927                 }
2928
2929                 if (manager) {
2930                         struct omap_dss_device *dssdev = manager->device;
2931                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2932                                 struct omap_overlay *ovl;
2933                                 ovl = omap_dss_get_overlay(i);
2934
2935                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2936                                         continue;
2937
2938                                 if (ovl->id != 0 && ovl->manager == manager)
2939                                         dispc_enable_plane(ovl->id, 0);
2940                         }
2941
2942                         dispc_go(manager->id);
2943                         mdelay(50);
2944                         if (enable)
2945                                 dssdev->driver->enable(dssdev);
2946                 }
2947         }
2948
2949         if (errors & DISPC_IRQ_OCP_ERR) {
2950                 DSSERR("OCP_ERR\n");
2951                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2952                         struct omap_overlay_manager *mgr;
2953                         mgr = omap_dss_get_overlay_manager(i);
2954
2955                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2956                                 mgr->device->driver->disable(mgr->device);
2957                 }
2958         }
2959
2960         spin_lock_irqsave(&dispc.irq_lock, flags);
2961         dispc.irq_error_mask |= errors;
2962         _omap_dispc_set_irqs();
2963         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2964 }
2965
2966 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2967 {
2968         void dispc_irq_wait_handler(void *data, u32 mask)
2969         {
2970                 complete((struct completion *)data);
2971         }
2972
2973         int r;
2974         DECLARE_COMPLETION_ONSTACK(completion);
2975
2976         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2977                         irqmask);
2978
2979         if (r)
2980                 return r;
2981
2982         timeout = wait_for_completion_timeout(&completion, timeout);
2983
2984         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2985
2986         if (timeout == 0)
2987                 return -ETIMEDOUT;
2988
2989         if (timeout == -ERESTARTSYS)
2990                 return -ERESTARTSYS;
2991
2992         return 0;
2993 }
2994
2995 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2996                 unsigned long timeout)
2997 {
2998         void dispc_irq_wait_handler(void *data, u32 mask)
2999         {
3000                 complete((struct completion *)data);
3001         }
3002
3003         int r;
3004         DECLARE_COMPLETION_ONSTACK(completion);
3005
3006         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3007                         irqmask);
3008
3009         if (r)
3010                 return r;
3011
3012         timeout = wait_for_completion_interruptible_timeout(&completion,
3013                         timeout);
3014
3015         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3016
3017         if (timeout == 0)
3018                 return -ETIMEDOUT;
3019
3020         if (timeout == -ERESTARTSYS)
3021                 return -ERESTARTSYS;
3022
3023         return 0;
3024 }
3025
3026 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3027 void dispc_fake_vsync_irq(void)
3028 {
3029         u32 irqstatus = DISPC_IRQ_VSYNC;
3030         int i;
3031
3032         WARN_ON(!in_interrupt());
3033
3034         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3035                 struct omap_dispc_isr_data *isr_data;
3036                 isr_data = &dispc.registered_isr[i];
3037
3038                 if (!isr_data->isr)
3039                         continue;
3040
3041                 if (isr_data->mask & irqstatus)
3042                         isr_data->isr(isr_data->arg, irqstatus);
3043         }
3044 }
3045 #endif
3046
3047 static void _omap_dispc_initialize_irq(void)
3048 {
3049         unsigned long flags;
3050
3051         spin_lock_irqsave(&dispc.irq_lock, flags);
3052
3053         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3054
3055         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3056
3057         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3058          * so clear it */
3059         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3060
3061         _omap_dispc_set_irqs();
3062
3063         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3064 }
3065
3066 void dispc_enable_sidle(void)
3067 {
3068         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3069 }
3070
3071 void dispc_disable_sidle(void)
3072 {
3073         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3074 }
3075
3076 static void _omap_dispc_initial_config(void)
3077 {
3078         u32 l;
3079
3080         l = dispc_read_reg(DISPC_SYSCONFIG);
3081         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3082         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3083         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3084         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3085         dispc_write_reg(DISPC_SYSCONFIG, l);
3086
3087         /* FUNCGATED */
3088         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3089
3090         /* L3 firewall setting: enable access to OCM RAM */
3091         /* XXX this should be somewhere in plat-omap */
3092         if (cpu_is_omap24xx())
3093                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3094
3095         _dispc_setup_color_conv_coef();
3096
3097         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3098
3099         dispc_read_plane_fifo_sizes();
3100 }
3101
3102 int dispc_init(void)
3103 {
3104         u32 rev;
3105
3106         spin_lock_init(&dispc.irq_lock);
3107
3108 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3109         spin_lock_init(&dispc.irq_stats_lock);
3110         dispc.irq_stats.last_reset = jiffies;
3111 #endif
3112
3113         INIT_WORK(&dispc.error_work, dispc_error_worker);
3114
3115         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3116         if (!dispc.base) {
3117                 DSSERR("can't ioremap DISPC\n");
3118                 return -ENOMEM;
3119         }
3120
3121         enable_clocks(1);
3122
3123         _omap_dispc_initial_config();
3124
3125         _omap_dispc_initialize_irq();
3126
3127         dispc_save_context();
3128
3129         rev = dispc_read_reg(DISPC_REVISION);
3130         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3131                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3132
3133         enable_clocks(0);
3134
3135         return 0;
3136 }
3137
3138 void dispc_exit(void)
3139 {
3140         iounmap(dispc.base);
3141 }
3142
3143 int dispc_enable_plane(enum omap_plane plane, bool enable)
3144 {
3145         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3146
3147         enable_clocks(1);
3148         _dispc_enable_plane(plane, enable);
3149         enable_clocks(0);
3150
3151         return 0;
3152 }
3153
3154 int dispc_setup_plane(enum omap_plane plane,
3155                        u32 paddr, u16 screen_width,
3156                        u16 pos_x, u16 pos_y,
3157                        u16 width, u16 height,
3158                        u16 out_width, u16 out_height,
3159                        enum omap_color_mode color_mode,
3160                        bool ilace,
3161                        enum omap_dss_rotation_type rotation_type,
3162                        u8 rotation, bool mirror, u8 global_alpha)
3163 {
3164         int r = 0;
3165
3166         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3167                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3168                plane, paddr, screen_width, pos_x, pos_y,
3169                width, height,
3170                out_width, out_height,
3171                ilace, color_mode,
3172                rotation, mirror);
3173
3174         enable_clocks(1);
3175
3176         r = _dispc_setup_plane(plane,
3177                            paddr, screen_width,
3178                            pos_x, pos_y,
3179                            width, height,
3180                            out_width, out_height,
3181                            color_mode, ilace,
3182                            rotation_type,
3183                            rotation, mirror,
3184                            global_alpha);
3185
3186         enable_clocks(0);
3187
3188         return r;
3189 }