drivers/video/omap/lcdc.c

   1 /*
   2  * OMAP1 internal LCD controller
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Imre Deak <imre.deak@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  */
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/err.h>
  26 #include <linux/mm.h>
  27 #include <linux/fb.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/clk.h>
  31 #include <linux/gfp.h>
  32
  33 #include <mach/lcdc.h>
  34 #include <plat/dma.h>
  35
  36 #include <asm/mach-types.h>
  37
  38 #include "omapfb.h"
  39
  40 #include "lcdc.h"
  41
  42 #define MODULE_NAME                     "lcdc"
  43
  44 #define MAX_PALETTE_SIZE                PAGE_SIZE
  45
  46 enum lcdc_load_mode {
  47         OMAP_LCDC_LOAD_PALETTE,
  48         OMAP_LCDC_LOAD_FRAME,
  49         OMAP_LCDC_LOAD_PALETTE_AND_FRAME
  50 };
  51
  52 static struct omap_lcd_controller {
  53         enum omapfb_update_mode update_mode;
  54         int                     ext_mode;
  55
  56         unsigned long           frame_offset;
  57         int                     screen_width;
  58         int                     xres;
  59         int                     yres;
  60
  61         enum omapfb_color_format        color_mode;
  62         int                     bpp;
  63         void                    *palette_virt;
  64         dma_addr_t              palette_phys;
  65         int                     palette_code;
  66         int                     palette_size;
  67
  68         unsigned int            irq_mask;
  69         struct completion       last_frame_complete;
  70         struct completion       palette_load_complete;
  71         struct clk              *lcd_ck;
  72         struct omapfb_device    *fbdev;
  73
  74         void                    (*dma_callback)(void *data);
  75         void                    *dma_callback_data;
  76
  77         int                     fbmem_allocated;
  78         dma_addr_t              vram_phys;
  79         void                    *vram_virt;
  80         unsigned long           vram_size;
  81 } lcdc;
  82
  83 static void inline enable_irqs(int mask)
  84 {
  85         lcdc.irq_mask |= mask;
  86 }
  87
  88 static void inline disable_irqs(int mask)
  89 {
  90         lcdc.irq_mask &= ~mask;
  91 }
  92
  93 static void set_load_mode(enum lcdc_load_mode mode)
  94 {
  95         u32 l;
  96
  97         l = omap_readl(OMAP_LCDC_CONTROL);
  98         l &= ~(3 << 20);
  99         switch (mode) {
 100         case OMAP_LCDC_LOAD_PALETTE:
 101                 l |= 1 << 20;
 102                 break;
 103         case OMAP_LCDC_LOAD_FRAME:
 104                 l |= 2 << 20;
 105                 break;
 106         case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
 107                 break;
 108         default:
 109                 BUG();
 110         }
 111         omap_writel(l, OMAP_LCDC_CONTROL);
 112 }
 113
 114 static void enable_controller(void)
 115 {
 116         u32 l;
 117
 118         l = omap_readl(OMAP_LCDC_CONTROL);
 119         l |= OMAP_LCDC_CTRL_LCD_EN;
 120         l &= ~OMAP_LCDC_IRQ_MASK;
 121         l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE;        /* enabled IRQs */
 122         omap_writel(l, OMAP_LCDC_CONTROL);
 123 }
 124
 125 static void disable_controller_async(void)
 126 {
 127         u32 l;
 128         u32 mask;
 129
 130         l = omap_readl(OMAP_LCDC_CONTROL);
 131         mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
 132         /*
 133          * Preserve the DONE mask, since we still want to get the
 134          * final DONE irq. It will be disabled in the IRQ handler.
 135          */
 136         mask &= ~OMAP_LCDC_IRQ_DONE;
 137         l &= ~mask;
 138         omap_writel(l, OMAP_LCDC_CONTROL);
 139 }
 140
 141 static void disable_controller(void)
 142 {
 143         init_completion(&lcdc.last_frame_complete);
 144         disable_controller_async();
 145         if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
 146                                 msecs_to_jiffies(500)))
 147                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 148 }
 149
 150 static void reset_controller(u32 status)
 151 {
 152         static unsigned long reset_count;
 153         static unsigned long last_jiffies;
 154
 155         disable_controller_async();
 156         reset_count++;
 157         if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
 158                 dev_err(lcdc.fbdev->dev,
 159                           "resetting (status %#010x,reset count %lu)\n",
 160                           status, reset_count);
 161                 last_jiffies = jiffies;
 162         }
 163         if (reset_count < 100) {
 164                 enable_controller();
 165         } else {
 166                 reset_count = 0;
 167                 dev_err(lcdc.fbdev->dev,
 168                         "too many reset attempts, giving up.\n");
 169         }
 170 }
 171
 172 /*
 173  * Configure the LCD DMA according to the current mode specified by parameters
 174  * in lcdc.fbdev and fbdev->var.
 175  */
 176 static void setup_lcd_dma(void)
 177 {
 178         static const int dma_elem_type[] = {
 179                 0,
 180                 OMAP_DMA_DATA_TYPE_S8,
 181                 OMAP_DMA_DATA_TYPE_S16,
 182                 0,
 183                 OMAP_DMA_DATA_TYPE_S32,
 184         };
 185         struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
 186         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 187         unsigned long   src;
 188         int             esize, xelem, yelem;
 189
 190         src = lcdc.vram_phys + lcdc.frame_offset;
 191
 192         switch (var->rotate) {
 193         case 0:
 194                 if (plane->info.mirror || (src & 3) ||
 195                     lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
 196                     (lcdc.xres & 1))
 197                         esize = 2;
 198                 else
 199                         esize = 4;
 200                 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
 201                 yelem = lcdc.yres;
 202                 break;
 203         case 90:
 204         case 180:
 205         case 270:
 206                 if (cpu_is_omap15xx()) {
 207                         BUG();
 208                 }
 209                 esize = 2;
 210                 xelem = lcdc.yres * lcdc.bpp / 16;
 211                 yelem = lcdc.xres;
 212                 break;
 213         default:
 214                 BUG();
 215                 return;
 216         }
 217 #ifdef VERBOSE
 218         dev_dbg(lcdc.fbdev->dev,
 219                  "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
 220                  src, esize, xelem, yelem);
 221 #endif
 222         omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
 223         if (!cpu_is_omap15xx()) {
 224                 int bpp = lcdc.bpp;
 225
 226                 /*
 227                  * YUV support is only for external mode when we have the
 228                  * YUV window embedded in a 16bpp frame buffer.
 229                  */
 230                 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
 231                         bpp = 16;
 232                 /* Set virtual xres elem size */
 233                 omap_set_lcd_dma_b1_vxres(
 234                         lcdc.screen_width * bpp / 8 / esize);
 235                 /* Setup transformations */
 236                 omap_set_lcd_dma_b1_rotation(var->rotate);
 237                 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
 238         }
 239         omap_setup_lcd_dma();
 240 }
 241
 242 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
 243 {
 244         u32 status;
 245
 246         status = omap_readl(OMAP_LCDC_STATUS);
 247
 248         if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
 249                 reset_controller(status);
 250         else {
 251                 if (status & OMAP_LCDC_STAT_DONE) {
 252                         u32 l;
 253
 254                         /*
 255                          * Disable IRQ_DONE. The status bit will be cleared
 256                          * only when the controller is reenabled and we don't
 257                          * want to get more interrupts.
 258                          */
 259                         l = omap_readl(OMAP_LCDC_CONTROL);
 260                         l &= ~OMAP_LCDC_IRQ_DONE;
 261                         omap_writel(l, OMAP_LCDC_CONTROL);
 262                         complete(&lcdc.last_frame_complete);
 263                 }
 264                 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
 265                         disable_controller_async();
 266                         complete(&lcdc.palette_load_complete);
 267                 }
 268         }
 269
 270         /*
 271          * Clear these interrupt status bits.
 272          * Sync_lost, FUF bits were cleared by disabling the LCD controller
 273          * LOADED_PALETTE can be cleared this way only in palette only
 274          * load mode. In other load modes it's cleared by disabling the
 275          * controller.
 276          */
 277         status &= ~(OMAP_LCDC_STAT_VSYNC |
 278                     OMAP_LCDC_STAT_LOADED_PALETTE |
 279                     OMAP_LCDC_STAT_ABC |
 280                     OMAP_LCDC_STAT_LINE_INT);
 281         omap_writel(status, OMAP_LCDC_STATUS);
 282         return IRQ_HANDLED;
 283 }
 284
 285 /*
 286  * Change to a new video mode. We defer this to a later time to avoid any
 287  * flicker and not to mess up the current LCD DMA context. For this we disable
 288  * the LCD controller, which will generate a DONE irq after the last frame has
 289  * been transferred. Then it'll be safe to reconfigure both the LCD controller
 290  * as well as the LCD DMA.
 291  */
 292 static int omap_lcdc_setup_plane(int plane, int channel_out,
 293                                  unsigned long offset, int screen_width,
 294                                  int pos_x, int pos_y, int width, int height,
 295                                  int color_mode)
 296 {
 297         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 298         struct lcd_panel *panel = lcdc.fbdev->panel;
 299         int rot_x, rot_y;
 300
 301         if (var->rotate == 0) {
 302                 rot_x = panel->x_res;
 303                 rot_y = panel->y_res;
 304         } else {
 305                 rot_x = panel->y_res;
 306                 rot_y = panel->x_res;
 307         }
 308         if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
 309             width > rot_x || height > rot_y) {
 310 #ifdef VERBOSE
 311                 dev_dbg(lcdc.fbdev->dev,
 312                         "invalid plane params plane %d pos_x %d pos_y %d "
 313                         "w %d h %d\n", plane, pos_x, pos_y, width, height);
 314 #endif
 315                 return -EINVAL;
 316         }
 317
 318         lcdc.frame_offset = offset;
 319         lcdc.xres = width;
 320         lcdc.yres = height;
 321         lcdc.screen_width = screen_width;
 322         lcdc.color_mode = color_mode;
 323
 324         switch (color_mode) {
 325         case OMAPFB_COLOR_CLUT_8BPP:
 326                 lcdc.bpp = 8;
 327                 lcdc.palette_code = 0x3000;
 328                 lcdc.palette_size = 512;
 329                 break;
 330         case OMAPFB_COLOR_RGB565:
 331                 lcdc.bpp = 16;
 332                 lcdc.palette_code = 0x4000;
 333                 lcdc.palette_size = 32;
 334                 break;
 335         case OMAPFB_COLOR_RGB444:
 336                 lcdc.bpp = 16;
 337                 lcdc.palette_code = 0x4000;
 338                 lcdc.palette_size = 32;
 339                 break;
 340         case OMAPFB_COLOR_YUV420:
 341                 if (lcdc.ext_mode) {
 342                         lcdc.bpp = 12;
 343                         break;
 344                 }
 345                 /* fallthrough */
 346         case OMAPFB_COLOR_YUV422:
 347                 if (lcdc.ext_mode) {
 348                         lcdc.bpp = 16;
 349                         break;
 350                 }
 351                 /* fallthrough */
 352         default:
 353                 /* FIXME: other BPPs.
 354                  * bpp1: code  0,     size 256
 355                  * bpp2: code  0x1000 size 256
 356                  * bpp4: code  0x2000 size 256
 357                  * bpp12: code 0x4000 size 32
 358                  */
 359                 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
 360                 BUG();
 361                 return -1;
 362         }
 363
 364         if (lcdc.ext_mode) {
 365                 setup_lcd_dma();
 366                 return 0;
 367         }
 368
 369         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 370                 disable_controller();
 371                 omap_stop_lcd_dma();
 372                 setup_lcd_dma();
 373                 enable_controller();
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int omap_lcdc_enable_plane(int plane, int enable)
 380 {
 381         dev_dbg(lcdc.fbdev->dev,
 382                 "plane %d enable %d update_mode %d ext_mode %d\n",
 383                 plane, enable, lcdc.update_mode, lcdc.ext_mode);
 384         if (plane != OMAPFB_PLANE_GFX)
 385                 return -EINVAL;
 386
 387         return 0;
 388 }
 389
 390 /*
 391  * Configure the LCD DMA for a palette load operation and do the palette
 392  * downloading synchronously. We don't use the frame+palette load mode of
 393  * the controller, since the palette can always be downloaded separately.
 394  */
 395 static void load_palette(void)
 396 {
 397         u16     *palette;
 398
 399         palette = (u16 *)lcdc.palette_virt;
 400
 401         *(u16 *)palette &= 0x0fff;
 402         *(u16 *)palette |= lcdc.palette_code;
 403
 404         omap_set_lcd_dma_b1(lcdc.palette_phys,
 405                 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
 406
 407         omap_set_lcd_dma_single_transfer(1);
 408         omap_setup_lcd_dma();
 409
 410         init_completion(&lcdc.palette_load_complete);
 411         enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 412         set_load_mode(OMAP_LCDC_LOAD_PALETTE);
 413         enable_controller();
 414         if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
 415                                 msecs_to_jiffies(500)))
 416                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 417         /* The controller gets disabled in the irq handler */
 418         disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 419         omap_stop_lcd_dma();
 420
 421         omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
 422 }
 423
 424 /* Used only in internal controller mode */
 425 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
 426                                u16 transp, int update_hw_pal)
 427 {
 428         u16 *palette;
 429
 430         if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
 431                 return -EINVAL;
 432
 433         palette = (u16 *)lcdc.palette_virt;
 434
 435         palette[regno] &= ~0x0fff;
 436         palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
 437                            (blue >> 12);
 438
 439         if (update_hw_pal) {
 440                 disable_controller();
 441                 omap_stop_lcd_dma();
 442                 load_palette();
 443                 setup_lcd_dma();
 444                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 445                 enable_controller();
 446         }
 447
 448         return 0;
 449 }
 450
 451 static void calc_ck_div(int is_tft, int pck, int *pck_div)
 452 {
 453         unsigned long lck;
 454
 455         pck = max(1, pck);
 456         lck = clk_get_rate(lcdc.lcd_ck);
 457         *pck_div = (lck + pck - 1) / pck;
 458         if (is_tft)
 459                 *pck_div = max(2, *pck_div);
 460         else
 461                 *pck_div = max(3, *pck_div);
 462         if (*pck_div > 255) {
 463                 /* FIXME: try to adjust logic clock divider as well */
 464                 *pck_div = 255;
 465                 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
 466                          pck / 1000);
 467         }
 468 }
 469
 470 static void inline setup_regs(void)
 471 {
 472         u32 l;
 473         struct lcd_panel *panel = lcdc.fbdev->panel;
 474         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 475         unsigned long lck;
 476         int pcd;
 477
 478         l = omap_readl(OMAP_LCDC_CONTROL);
 479         l &= ~OMAP_LCDC_CTRL_LCD_TFT;
 480         l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
 481 #ifdef CONFIG_MACH_OMAP_PALMTE
 482 /* FIXME:if (machine_is_omap_palmte()) { */
 483                 /* PalmTE uses alternate TFT setting in 8BPP mode */
 484                 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
 485 /*      } */
 486 #endif
 487         omap_writel(l, OMAP_LCDC_CONTROL);
 488
 489         l = omap_readl(OMAP_LCDC_TIMING2);
 490         l &= ~(((1 << 6) - 1) << 20);
 491         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
 492         omap_writel(l, OMAP_LCDC_TIMING2);
 493
 494         l = panel->x_res - 1;
 495         l |= (panel->hsw - 1) << 10;
 496         l |= (panel->hfp - 1) << 16;
 497         l |= (panel->hbp - 1) << 24;
 498         omap_writel(l, OMAP_LCDC_TIMING0);
 499
 500         l = panel->y_res - 1;
 501         l |= (panel->vsw - 1) << 10;
 502         l |= panel->vfp << 16;
 503         l |= panel->vbp << 24;
 504         omap_writel(l, OMAP_LCDC_TIMING1);
 505
 506         l = omap_readl(OMAP_LCDC_TIMING2);
 507         l &= ~0xff;
 508
 509         lck = clk_get_rate(lcdc.lcd_ck);
 510
 511         if (!panel->pcd)
 512                 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
 513         else {
 514                 dev_warn(lcdc.fbdev->dev,
 515                     "Pixel clock divider value is obsolete.\n"
 516                     "Try to set pixel_clock to %lu and pcd to 0 "
 517                     "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
 518                         lck / panel->pcd / 1000, panel->name);
 519
 520                 pcd = panel->pcd;
 521         }
 522         l |= pcd & 0xff;
 523         l |= panel->acb << 8;
 524         omap_writel(l, OMAP_LCDC_TIMING2);
 525
 526         /* update panel info with the exact clock */
 527         panel->pixel_clock = lck / pcd / 1000;
 528 }
 529
 530 /*
 531  * Configure the LCD controller, download the color palette and start a looped
 532  * DMA transfer of the frame image data. Called only in internal
 533  * controller mode.
 534  */
 535 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
 536 {
 537         int r = 0;
 538
 539         if (mode != lcdc.update_mode) {
 540                 switch (mode) {
 541                 case OMAPFB_AUTO_UPDATE:
 542                         setup_regs();
 543                         load_palette();
 544
 545                         /* Setup and start LCD DMA */
 546                         setup_lcd_dma();
 547
 548                         set_load_mode(OMAP_LCDC_LOAD_FRAME);
 549                         enable_irqs(OMAP_LCDC_IRQ_DONE);
 550                         /* This will start the actual DMA transfer */
 551                         enable_controller();
 552                         lcdc.update_mode = mode;
 553                         break;
 554                 case OMAPFB_UPDATE_DISABLED:
 555                         disable_controller();
 556                         omap_stop_lcd_dma();
 557                         lcdc.update_mode = mode;
 558                         break;
 559                 default:
 560                         r = -EINVAL;
 561                 }
 562         }
 563
 564         return r;
 565 }
 566
 567 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
 568 {
 569         return lcdc.update_mode;
 570 }
 571
 572 /* PM code called only in internal controller mode */
 573 static void omap_lcdc_suspend(void)
 574 {
 575         omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
 576 }
 577
 578 static void omap_lcdc_resume(void)
 579 {
 580         omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
 581 }
 582
 583 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
 584 {
 585         return;
 586 }
 587
 588 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
 589 {
 590         BUG_ON(callback == NULL);
 591
 592         if (lcdc.dma_callback)
 593                 return -EBUSY;
 594         else {
 595                 lcdc.dma_callback = callback;
 596                 lcdc.dma_callback_data = data;
 597         }
 598         return 0;
 599 }
 600 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
 601
 602 void omap_lcdc_free_dma_callback(void)
 603 {
 604         lcdc.dma_callback = NULL;
 605 }
 606 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
 607
 608 static void lcdc_dma_handler(u16 status, void *data)
 609 {
 610         if (lcdc.dma_callback)
 611                 lcdc.dma_callback(lcdc.dma_callback_data);
 612 }
 613
 614 static int mmap_kern(void)
 615 {
 616         struct vm_struct        *kvma;
 617         struct vm_area_struct   vma;
 618         pgprot_t                pgprot;
 619         unsigned long           vaddr;
 620
 621         kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
 622         if (kvma == NULL) {
 623                 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
 624                 return -ENOMEM;
 625         }
 626         vma.vm_mm = &init_mm;
 627
 628         vaddr = (unsigned long)kvma->addr;
 629         vma.vm_start = vaddr;
 630         vma.vm_end = vaddr + lcdc.vram_size;
 631
 632         pgprot = pgprot_writecombine(pgprot_kernel);
 633         if (io_remap_pfn_range(&vma, vaddr,
 634                            lcdc.vram_phys >> PAGE_SHIFT,
 635                            lcdc.vram_size, pgprot) < 0) {
 636                 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
 637                 return -EAGAIN;
 638         }
 639
 640         lcdc.vram_virt = (void *)vaddr;
 641
 642         return 0;
 643 }
 644
 645 static void unmap_kern(void)
 646 {
 647         vunmap(lcdc.vram_virt);
 648 }
 649
 650 static int alloc_palette_ram(void)
 651 {
 652         lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 653                 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
 654         if (lcdc.palette_virt == NULL) {
 655                 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
 656                 return -ENOMEM;
 657         }
 658         memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
 659
 660         return 0;
 661 }
 662
 663 static void free_palette_ram(void)
 664 {
 665         dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
 666                         lcdc.palette_virt, lcdc.palette_phys);
 667 }
 668
 669 static int alloc_fbmem(struct omapfb_mem_region *region)
 670 {
 671         int bpp;
 672         int frame_size;
 673         struct lcd_panel *panel = lcdc.fbdev->panel;
 674
 675         bpp = panel->bpp;
 676         if (bpp == 12)
 677                 bpp = 16;
 678         frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
 679         if (region->size > frame_size)
 680                 frame_size = region->size;
 681         lcdc.vram_size = frame_size;
 682         lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 683                         lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
 684         if (lcdc.vram_virt == NULL) {
 685                 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
 686                 return -ENOMEM;
 687         }
 688         region->size = frame_size;
 689         region->paddr = lcdc.vram_phys;
 690         region->vaddr = lcdc.vram_virt;
 691         region->alloc = 1;
 692
 693         memset(lcdc.vram_virt, 0, lcdc.vram_size);
 694
 695         return 0;
 696 }
 697
 698 static void free_fbmem(void)
 699 {
 700         dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
 701                               lcdc.vram_virt, lcdc.vram_phys);
 702 }
 703
 704 static int setup_fbmem(struct omapfb_mem_desc *req_md)
 705 {
 706         int r;
 707
 708         if (!req_md->region_cnt) {
 709                 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
 710                 return -EINVAL;
 711         }
 712
 713         if (req_md->region_cnt > 1) {
 714                 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
 715                 req_md->region_cnt = 1;
 716         }
 717
 718         if (req_md->region[0].paddr == 0) {
 719                 lcdc.fbmem_allocated = 1;
 720                 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
 721                         return r;
 722                 return 0;
 723         }
 724
 725         lcdc.vram_phys = req_md->region[0].paddr;
 726         lcdc.vram_size = req_md->region[0].size;
 727
 728         if ((r = mmap_kern()) < 0)
 729                 return r;
 730
 731         dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
 732                  lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
 733
 734         return 0;
 735 }
 736
 737 static void cleanup_fbmem(void)
 738 {
 739         if (lcdc.fbmem_allocated)
 740                 free_fbmem();
 741         else
 742                 unmap_kern();
 743 }
 744
 745 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
 746                           struct omapfb_mem_desc *req_vram)
 747 {
 748         int r;
 749         u32 l;
 750         int rate;
 751         struct clk *tc_ck;
 752
 753         lcdc.irq_mask = 0;
 754
 755         lcdc.fbdev = fbdev;
 756         lcdc.ext_mode = ext_mode;
 757
 758         l = 0;
 759         omap_writel(l, OMAP_LCDC_CONTROL);
 760
 761         /* FIXME:
 762          * According to errata some platforms have a clock rate limitiation
 763          */
 764         lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
 765         if (IS_ERR(lcdc.lcd_ck)) {
 766                 dev_err(fbdev->dev, "unable to access LCD clock\n");
 767                 r = PTR_ERR(lcdc.lcd_ck);
 768                 goto fail0;
 769         }
 770
 771         tc_ck = clk_get(fbdev->dev, "tc_ck");
 772         if (IS_ERR(tc_ck)) {
 773                 dev_err(fbdev->dev, "unable to access TC clock\n");
 774                 r = PTR_ERR(tc_ck);
 775                 goto fail1;
 776         }
 777
 778         rate = clk_get_rate(tc_ck);
 779         clk_put(tc_ck);
 780
 781         if (machine_is_ams_delta())
 782                 rate /= 4;
 783         if (machine_is_omap_h3())
 784                 rate /= 3;
 785         r = clk_set_rate(lcdc.lcd_ck, rate);
 786         if (r) {
 787                 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
 788                 goto fail1;
 789         }
 790         clk_enable(lcdc.lcd_ck);
 791
 792         r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
 793         if (r) {
 794                 dev_err(fbdev->dev, "unable to get IRQ\n");
 795                 goto fail2;
 796         }
 797
 798         r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
 799         if (r) {
 800                 dev_err(fbdev->dev, "unable to get LCD DMA\n");
 801                 goto fail3;
 802         }
 803
 804         omap_set_lcd_dma_single_transfer(ext_mode);
 805         omap_set_lcd_dma_ext_controller(ext_mode);
 806
 807         if (!ext_mode)
 808                 if ((r = alloc_palette_ram()) < 0)
 809                         goto fail4;
 810
 811         if ((r = setup_fbmem(req_vram)) < 0)
 812                 goto fail5;
 813
 814         pr_info("omapfb: LCDC initialized\n");
 815
 816         return 0;
 817 fail5:
 818         if (!ext_mode)
 819                 free_palette_ram();
 820 fail4:
 821         omap_free_lcd_dma();
 822 fail3:
 823         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 824 fail2:
 825         clk_disable(lcdc.lcd_ck);
 826 fail1:
 827         clk_put(lcdc.lcd_ck);
 828 fail0:
 829         return r;
 830 }
 831
 832 static void omap_lcdc_cleanup(void)
 833 {
 834         if (!lcdc.ext_mode)
 835                 free_palette_ram();
 836         cleanup_fbmem();
 837         omap_free_lcd_dma();
 838         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 839         clk_disable(lcdc.lcd_ck);
 840         clk_put(lcdc.lcd_ck);
 841 }
 842
 843 const struct lcd_ctrl omap1_int_ctrl = {
 844         .name                   = "internal",
 845         .init                   = omap_lcdc_init,
 846         .cleanup                = omap_lcdc_cleanup,
 847         .get_caps               = omap_lcdc_get_caps,
 848         .set_update_mode        = omap_lcdc_set_update_mode,
 849         .get_update_mode        = omap_lcdc_get_update_mode,
 850         .update_window          = NULL,
 851         .suspend                = omap_lcdc_suspend,
 852         .resume                 = omap_lcdc_resume,
 853         .setup_plane            = omap_lcdc_setup_plane,
 854         .enable_plane           = omap_lcdc_enable_plane,
 855         .setcolreg              = omap_lcdc_setcolreg,
 856 };