intelfb: fixup clock calculation debugging.
[sfrench/cifs-2.6.git] / drivers / video / intelfb / intelfbhw.c
1 /*
2  * intelfb
3  *
4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5  *
6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7  *                   2004 Sylvain Meyer
8  *
9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
10  * the basic fbdev interfaces, is derived in part from the radeonfb and
11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
12  * provides the code to program the hardware.  Most of it is derived from
13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
14  * under a dual license (GPL and MIT/XFree86 license).
15  *
16  * Author: David Dawes
17  *
18  */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/fb.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37
38 #include <asm/io.h>
39
40 #include "intelfb.h"
41 #include "intelfbhw.h"
42
43 struct pll_min_max {
44         int min_m, max_m, min_m1, max_m1;
45         int min_m2, max_m2, min_n, max_n;
46         int min_p, max_p, min_p1, max_p1;
47         int min_vco, max_vco, p_transition_clk, ref_clk;
48         int p_inc_lo, p_inc_hi;
49 };
50
51 #define PLLS_I8xx 0
52 #define PLLS_I9xx 1
53 #define PLLS_MAX 2
54
55 static struct pll_min_max plls[PLLS_MAX] = {
56         { 108, 140, 18, 26,
57           6, 16, 3, 16,
58           4, 128, 0, 31,
59           930000, 1400000, 165000, 48000,
60           4, 2 }, //I8xx
61
62         { 75, 120, 10, 20,
63           5, 9, 4, 7,
64           5, 80, 1, 8,
65           1400000, 2800000, 200000, 96000,
66           10, 5 }  //I9xx
67 };
68
69 int
70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
71 {
72         u32 tmp;
73         if (!pdev || !dinfo)
74                 return 1;
75
76         switch (pdev->device) {
77         case PCI_DEVICE_ID_INTEL_830M:
78                 dinfo->name = "Intel(R) 830M";
79                 dinfo->chipset = INTEL_830M;
80                 dinfo->mobile = 1;
81                 dinfo->pll_index = PLLS_I8xx;
82                 return 0;
83         case PCI_DEVICE_ID_INTEL_845G:
84                 dinfo->name = "Intel(R) 845G";
85                 dinfo->chipset = INTEL_845G;
86                 dinfo->mobile = 0;
87                 dinfo->pll_index = PLLS_I8xx;
88                 return 0;
89         case PCI_DEVICE_ID_INTEL_85XGM:
90                 tmp = 0;
91                 dinfo->mobile = 1;
92                 dinfo->pll_index = PLLS_I8xx;
93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
95                         INTEL_85X_VARIANT_MASK) {
96                 case INTEL_VAR_855GME:
97                         dinfo->name = "Intel(R) 855GME";
98                         dinfo->chipset = INTEL_855GME;
99                         return 0;
100                 case INTEL_VAR_855GM:
101                         dinfo->name = "Intel(R) 855GM";
102                         dinfo->chipset = INTEL_855GM;
103                         return 0;
104                 case INTEL_VAR_852GME:
105                         dinfo->name = "Intel(R) 852GME";
106                         dinfo->chipset = INTEL_852GME;
107                         return 0;
108                 case INTEL_VAR_852GM:
109                         dinfo->name = "Intel(R) 852GM";
110                         dinfo->chipset = INTEL_852GM;
111                         return 0;
112                 default:
113                         dinfo->name = "Intel(R) 852GM/855GM";
114                         dinfo->chipset = INTEL_85XGM;
115                         return 0;
116                 }
117                 break;
118         case PCI_DEVICE_ID_INTEL_865G:
119                 dinfo->name = "Intel(R) 865G";
120                 dinfo->chipset = INTEL_865G;
121                 dinfo->mobile = 0;
122                 dinfo->pll_index = PLLS_I8xx;
123                 return 0;
124         case PCI_DEVICE_ID_INTEL_915G:
125                 dinfo->name = "Intel(R) 915G";
126                 dinfo->chipset = INTEL_915G;
127                 dinfo->mobile = 0;
128                 dinfo->pll_index = PLLS_I9xx;
129                 return 0;
130         case PCI_DEVICE_ID_INTEL_915GM:
131                 dinfo->name = "Intel(R) 915GM";
132                 dinfo->chipset = INTEL_915GM;
133                 dinfo->mobile = 1;
134                 dinfo->pll_index = PLLS_I9xx;
135                 return 0;
136         case PCI_DEVICE_ID_INTEL_945G:
137                 dinfo->name = "Intel(R) 945G";
138                 dinfo->chipset = INTEL_945G;
139                 dinfo->mobile = 0;
140                 dinfo->pll_index = PLLS_I9xx;
141                 return 0;
142         case PCI_DEVICE_ID_INTEL_945GM:
143                 dinfo->name = "Intel(R) 945GM";
144                 dinfo->chipset = INTEL_945GM;
145                 dinfo->mobile = 1;
146                 dinfo->pll_index = PLLS_I9xx;
147                 return 0;
148         default:
149                 return 1;
150         }
151 }
152
153 int
154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
155                      int *stolen_size)
156 {
157         struct pci_dev *bridge_dev;
158         u16 tmp;
159         int stolen_overhead;
160
161         if (!pdev || !aperture_size || !stolen_size)
162                 return 1;
163
164         /* Find the bridge device.  It is always 0:0.0 */
165         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
166                 ERR_MSG("cannot find bridge device\n");
167                 return 1;
168         }
169
170         /* Get the fb aperture size and "stolen" memory amount. */
171         tmp = 0;
172         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
173         switch (pdev->device) {
174         case PCI_DEVICE_ID_INTEL_915G:
175         case PCI_DEVICE_ID_INTEL_915GM:
176         case PCI_DEVICE_ID_INTEL_945G:
177         case PCI_DEVICE_ID_INTEL_945GM:
178                 /* 915 and 945 chipsets support a 256MB aperture.
179                    Aperture size is determined by inspected the
180                    base address of the aperture. */
181                 if (pci_resource_start(pdev, 2) & 0x08000000)
182                         *aperture_size = MB(128);
183                 else
184                         *aperture_size = MB(256);
185                 break;
186         default:
187                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
188                         *aperture_size = MB(64);
189                 else
190                         *aperture_size = MB(128);
191                 break;
192         }
193
194         /* Stolen memory size is reduced by the GTT and the popup.
195            GTT is 1K per MB of aperture size, and popup is 4K. */
196         stolen_overhead = (*aperture_size / MB(1)) + 4;
197         switch(pdev->device) {
198         case PCI_DEVICE_ID_INTEL_830M:
199         case PCI_DEVICE_ID_INTEL_845G:
200                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
201                 case INTEL_830_GMCH_GMS_STOLEN_512:
202                         *stolen_size = KB(512) - KB(stolen_overhead);
203                         return 0;
204                 case INTEL_830_GMCH_GMS_STOLEN_1024:
205                         *stolen_size = MB(1) - KB(stolen_overhead);
206                         return 0;
207                 case INTEL_830_GMCH_GMS_STOLEN_8192:
208                         *stolen_size = MB(8) - KB(stolen_overhead);
209                         return 0;
210                 case INTEL_830_GMCH_GMS_LOCAL:
211                         ERR_MSG("only local memory found\n");
212                         return 1;
213                 case INTEL_830_GMCH_GMS_DISABLED:
214                         ERR_MSG("video memory is disabled\n");
215                         return 1;
216                 default:
217                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
218                                 tmp & INTEL_830_GMCH_GMS_MASK);
219                         return 1;
220                 }
221                 break;
222         default:
223                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
224                 case INTEL_855_GMCH_GMS_STOLEN_1M:
225                         *stolen_size = MB(1) - KB(stolen_overhead);
226                         return 0;
227                 case INTEL_855_GMCH_GMS_STOLEN_4M:
228                         *stolen_size = MB(4) - KB(stolen_overhead);
229                         return 0;
230                 case INTEL_855_GMCH_GMS_STOLEN_8M:
231                         *stolen_size = MB(8) - KB(stolen_overhead);
232                         return 0;
233                 case INTEL_855_GMCH_GMS_STOLEN_16M:
234                         *stolen_size = MB(16) - KB(stolen_overhead);
235                         return 0;
236                 case INTEL_855_GMCH_GMS_STOLEN_32M:
237                         *stolen_size = MB(32) - KB(stolen_overhead);
238                         return 0;
239                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
240                         *stolen_size = MB(48) - KB(stolen_overhead);
241                         return 0;
242                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
243                         *stolen_size = MB(64) - KB(stolen_overhead);
244                         return 0;
245                 case INTEL_855_GMCH_GMS_DISABLED:
246                         ERR_MSG("video memory is disabled\n");
247                         return 0;
248                 default:
249                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
250                                 tmp & INTEL_855_GMCH_GMS_MASK);
251                         return 1;
252                 }
253         }
254 }
255
256 int
257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
258 {
259         int dvo = 0;
260
261         if (INREG(LVDS) & PORT_ENABLE)
262                 dvo |= LVDS_PORT;
263         if (INREG(DVOA) & PORT_ENABLE)
264                 dvo |= DVOA_PORT;
265         if (INREG(DVOB) & PORT_ENABLE)
266                 dvo |= DVOB_PORT;
267         if (INREG(DVOC) & PORT_ENABLE)
268                 dvo |= DVOC_PORT;
269
270         return dvo;
271 }
272
273 const char *
274 intelfbhw_dvo_to_string(int dvo)
275 {
276         if (dvo & DVOA_PORT)
277                 return "DVO port A";
278         else if (dvo & DVOB_PORT)
279                 return "DVO port B";
280         else if (dvo & DVOC_PORT)
281                 return "DVO port C";
282         else if (dvo & LVDS_PORT)
283                 return "LVDS port";
284         else
285                 return NULL;
286 }
287
288
289 int
290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
291                         struct fb_var_screeninfo *var)
292 {
293         int bytes_per_pixel;
294         int tmp;
295
296 #if VERBOSE > 0
297         DBG_MSG("intelfbhw_validate_mode\n");
298 #endif
299
300         bytes_per_pixel = var->bits_per_pixel / 8;
301         if (bytes_per_pixel == 3)
302                 bytes_per_pixel = 4;
303
304         /* Check if enough video memory. */
305         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
306         if (tmp > dinfo->fb.size) {
307                 WRN_MSG("Not enough video ram for mode "
308                         "(%d KByte vs %d KByte).\n",
309                         BtoKB(tmp), BtoKB(dinfo->fb.size));
310                 return 1;
311         }
312
313         /* Check if x/y limits are OK. */
314         if (var->xres - 1 > HACTIVE_MASK) {
315                 WRN_MSG("X resolution too large (%d vs %d).\n",
316                         var->xres, HACTIVE_MASK + 1);
317                 return 1;
318         }
319         if (var->yres - 1 > VACTIVE_MASK) {
320                 WRN_MSG("Y resolution too large (%d vs %d).\n",
321                         var->yres, VACTIVE_MASK + 1);
322                 return 1;
323         }
324
325         /* Check for interlaced/doublescan modes. */
326         if (var->vmode & FB_VMODE_INTERLACED) {
327                 WRN_MSG("Mode is interlaced.\n");
328                 return 1;
329         }
330         if (var->vmode & FB_VMODE_DOUBLE) {
331                 WRN_MSG("Mode is double-scan.\n");
332                 return 1;
333         }
334
335         /* Check if clock is OK. */
336         tmp = 1000000000 / var->pixclock;
337         if (tmp < MIN_CLOCK) {
338                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
339                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
340                 return 1;
341         }
342         if (tmp > MAX_CLOCK) {
343                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
344                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
345                 return 1;
346         }
347
348         return 0;
349 }
350
351 int
352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
353 {
354         struct intelfb_info *dinfo = GET_DINFO(info);
355         u32 offset, xoffset, yoffset;
356
357 #if VERBOSE > 0
358         DBG_MSG("intelfbhw_pan_display\n");
359 #endif
360
361         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
362         yoffset = var->yoffset;
363
364         if ((xoffset + var->xres > var->xres_virtual) ||
365             (yoffset + var->yres > var->yres_virtual))
366                 return -EINVAL;
367
368         offset = (yoffset * dinfo->pitch) +
369                  (xoffset * var->bits_per_pixel) / 8;
370
371         offset += dinfo->fb.offset << 12;
372
373         OUTREG(DSPABASE, offset);
374
375         return 0;
376 }
377
378 /* Blank the screen. */
379 void
380 intelfbhw_do_blank(int blank, struct fb_info *info)
381 {
382         struct intelfb_info *dinfo = GET_DINFO(info);
383         u32 tmp;
384
385 #if VERBOSE > 0
386         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
387 #endif
388
389         /* Turn plane A on or off */
390         tmp = INREG(DSPACNTR);
391         if (blank)
392                 tmp &= ~DISPPLANE_PLANE_ENABLE;
393         else
394                 tmp |= DISPPLANE_PLANE_ENABLE;
395         OUTREG(DSPACNTR, tmp);
396         /* Flush */
397         tmp = INREG(DSPABASE);
398         OUTREG(DSPABASE, tmp);
399
400         /* Turn off/on the HW cursor */
401 #if VERBOSE > 0
402         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
403 #endif
404         if (dinfo->cursor_on) {
405                 if (blank) {
406                         intelfbhw_cursor_hide(dinfo);
407                 } else {
408                         intelfbhw_cursor_show(dinfo);
409                 }
410                 dinfo->cursor_on = 1;
411         }
412         dinfo->cursor_blanked = blank;
413
414         /* Set DPMS level */
415         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
416         switch (blank) {
417         case FB_BLANK_UNBLANK:
418         case FB_BLANK_NORMAL:
419                 tmp |= ADPA_DPMS_D0;
420                 break;
421         case FB_BLANK_VSYNC_SUSPEND:
422                 tmp |= ADPA_DPMS_D1;
423                 break;
424         case FB_BLANK_HSYNC_SUSPEND:
425                 tmp |= ADPA_DPMS_D2;
426                 break;
427         case FB_BLANK_POWERDOWN:
428                 tmp |= ADPA_DPMS_D3;
429                 break;
430         }
431         OUTREG(ADPA, tmp);
432
433         return;
434 }
435
436
437 void
438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
439                     unsigned red, unsigned green, unsigned blue,
440                     unsigned transp)
441 {
442 #if VERBOSE > 0
443         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
444                 regno, red, green, blue);
445 #endif
446
447         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
448                           PALETTE_A : PALETTE_B;
449
450         OUTREG(palette_reg + (regno << 2),
451                (red << PALETTE_8_RED_SHIFT) |
452                (green << PALETTE_8_GREEN_SHIFT) |
453                (blue << PALETTE_8_BLUE_SHIFT));
454 }
455
456
457 int
458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
459                         int flag)
460 {
461         int i;
462
463 #if VERBOSE > 0
464         DBG_MSG("intelfbhw_read_hw_state\n");
465 #endif
466
467         if (!hw || !dinfo)
468                 return -1;
469
470         /* Read in as much of the HW state as possible. */
471         hw->vga0_divisor = INREG(VGA0_DIVISOR);
472         hw->vga1_divisor = INREG(VGA1_DIVISOR);
473         hw->vga_pd = INREG(VGAPD);
474         hw->dpll_a = INREG(DPLL_A);
475         hw->dpll_b = INREG(DPLL_B);
476         hw->fpa0 = INREG(FPA0);
477         hw->fpa1 = INREG(FPA1);
478         hw->fpb0 = INREG(FPB0);
479         hw->fpb1 = INREG(FPB1);
480
481         if (flag == 1)
482                 return flag;
483
484 #if 0
485         /* This seems to be a problem with the 852GM/855GM */
486         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
487                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
488                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
489         }
490 #endif
491
492         if (flag == 2)
493                 return flag;
494
495         hw->htotal_a = INREG(HTOTAL_A);
496         hw->hblank_a = INREG(HBLANK_A);
497         hw->hsync_a = INREG(HSYNC_A);
498         hw->vtotal_a = INREG(VTOTAL_A);
499         hw->vblank_a = INREG(VBLANK_A);
500         hw->vsync_a = INREG(VSYNC_A);
501         hw->src_size_a = INREG(SRC_SIZE_A);
502         hw->bclrpat_a = INREG(BCLRPAT_A);
503         hw->htotal_b = INREG(HTOTAL_B);
504         hw->hblank_b = INREG(HBLANK_B);
505         hw->hsync_b = INREG(HSYNC_B);
506         hw->vtotal_b = INREG(VTOTAL_B);
507         hw->vblank_b = INREG(VBLANK_B);
508         hw->vsync_b = INREG(VSYNC_B);
509         hw->src_size_b = INREG(SRC_SIZE_B);
510         hw->bclrpat_b = INREG(BCLRPAT_B);
511
512         if (flag == 3)
513                 return flag;
514
515         hw->adpa = INREG(ADPA);
516         hw->dvoa = INREG(DVOA);
517         hw->dvob = INREG(DVOB);
518         hw->dvoc = INREG(DVOC);
519         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
520         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
521         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
522         hw->lvds = INREG(LVDS);
523
524         if (flag == 4)
525                 return flag;
526
527         hw->pipe_a_conf = INREG(PIPEACONF);
528         hw->pipe_b_conf = INREG(PIPEBCONF);
529         hw->disp_arb = INREG(DISPARB);
530
531         if (flag == 5)
532                 return flag;
533
534         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
535         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
536         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
537         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
538
539         if (flag == 6)
540                 return flag;
541
542         for (i = 0; i < 4; i++) {
543                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
544                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
545         }
546
547         if (flag == 7)
548                 return flag;
549
550         hw->cursor_size = INREG(CURSOR_SIZE);
551
552         if (flag == 8)
553                 return flag;
554
555         hw->disp_a_ctrl = INREG(DSPACNTR);
556         hw->disp_b_ctrl = INREG(DSPBCNTR);
557         hw->disp_a_base = INREG(DSPABASE);
558         hw->disp_b_base = INREG(DSPBBASE);
559         hw->disp_a_stride = INREG(DSPASTRIDE);
560         hw->disp_b_stride = INREG(DSPBSTRIDE);
561
562         if (flag == 9)
563                 return flag;
564
565         hw->vgacntrl = INREG(VGACNTRL);
566
567         if (flag == 10)
568                 return flag;
569
570         hw->add_id = INREG(ADD_ID);
571
572         if (flag == 11)
573                 return flag;
574
575         for (i = 0; i < 7; i++) {
576                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
577                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
578                 if (i < 3)
579                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
580         }
581
582         for (i = 0; i < 8; i++)
583                 hw->fence[i] = INREG(FENCE + (i << 2));
584
585         hw->instpm = INREG(INSTPM);
586         hw->mem_mode = INREG(MEM_MODE);
587         hw->fw_blc_0 = INREG(FW_BLC_0);
588         hw->fw_blc_1 = INREG(FW_BLC_1);
589
590         return 0;
591 }
592
593
594 static int calc_vclock3(int index, int m, int n, int p)
595 {
596         if (p == 0 || n == 0)
597                 return 0;
598         return plls[index].ref_clk * m / n / p;
599 }
600
601 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
602 {
603         struct pll_min_max *pll = &plls[index];
604         u32 m, vco, p;
605
606         m = (5 * (m1 + 2)) + (m2 + 2);
607         n += 2;
608         vco = pll->ref_clk * m / n;
609
610         if (index == PLLS_I8xx) {
611                 p = ((p1 + 2) * (1 << (p2 + 1)));
612         } else {
613                 p = ((p1) * (p2 ? 5 : 10));
614         }
615         return vco / p;
616 }
617
618 static void
619 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
620 {
621         int p1, p2;
622
623         if (IS_I9XX(dinfo)) {
624                 if (dpll & DPLL_P1_FORCE_DIV2)
625                         p1 = 1;
626                 else
627                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
628                 
629                 p1 = ffs(p1);
630
631                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
632         } else {
633                 if (dpll & DPLL_P1_FORCE_DIV2)
634                         p1 = 0;
635                 else
636                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
637                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
638         }
639
640         *o_p1 = p1;
641         *o_p2 = p2;
642 }
643
644
645 void
646 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
647 {
648 #if REGDUMP
649         int i, m1, m2, n, p1, p2;
650         int index = dinfo->pll_index;
651         DBG_MSG("intelfbhw_print_hw_state\n");
652
653         if (!hw || !dinfo)
654                 return;
655         /* Read in as much of the HW state as possible. */
656         printk("hw state dump start\n");
657         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
658         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
659         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
660         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
661         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
662         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
663
664         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
665
666         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
667                m1, m2, n, p1, p2);
668         printk("        VGA0: clock is %d\n",
669                calc_vclock(index, m1, m2, n, p1, p2, 0));
670
671         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
672         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
673         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
674
675         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
676         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
677                m1, m2, n, p1, p2);
678         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
679
680         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
681         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
682         printk("        FPA0:                   0x%08x\n", hw->fpa0);
683         printk("        FPA1:                   0x%08x\n", hw->fpa1);
684         printk("        FPB0:                   0x%08x\n", hw->fpb0);
685         printk("        FPB1:                   0x%08x\n", hw->fpb1);
686
687         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
688         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
689         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
690
691         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
692
693         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
694                m1, m2, n, p1, p2);
695         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
696
697         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
698         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
699         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
700
701         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
702
703         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
704                m1, m2, n, p1, p2);
705         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
706
707 #if 0
708         printk("        PALETTE_A:\n");
709         for (i = 0; i < PALETTE_8_ENTRIES)
710                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
711         printk("        PALETTE_B:\n");
712         for (i = 0; i < PALETTE_8_ENTRIES)
713                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
714 #endif
715
716         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
717         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
718         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
719         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
720         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
721         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
722         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
723         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
724         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
725         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
726         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
727         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
728         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
729         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
730         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
731         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
732
733         printk("        ADPA:                   0x%08x\n", hw->adpa);
734         printk("        DVOA:                   0x%08x\n", hw->dvoa);
735         printk("        DVOB:                   0x%08x\n", hw->dvob);
736         printk("        DVOC:                   0x%08x\n", hw->dvoc);
737         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
738         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
739         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
740         printk("        LVDS:                   0x%08x\n", hw->lvds);
741
742         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
743         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
744         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
745
746         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
747         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
748         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
749         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
750
751         printk("        CURSOR_A_PALETTE:       ");
752         for (i = 0; i < 4; i++) {
753                 printk("0x%08x", hw->cursor_a_palette[i]);
754                 if (i < 3)
755                         printk(", ");
756         }
757         printk("\n");
758         printk("        CURSOR_B_PALETTE:       ");
759         for (i = 0; i < 4; i++) {
760                 printk("0x%08x", hw->cursor_b_palette[i]);
761                 if (i < 3)
762                         printk(", ");
763         }
764         printk("\n");
765
766         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
767
768         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
769         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
770         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
771         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
772         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
773         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
774
775         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
776         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
777
778         for (i = 0; i < 7; i++) {
779                 printk("        SWF0%d                  0x%08x\n", i,
780                         hw->swf0x[i]);
781         }
782         for (i = 0; i < 7; i++) {
783                 printk("        SWF1%d                  0x%08x\n", i,
784                         hw->swf1x[i]);
785         }
786         for (i = 0; i < 3; i++) {
787                 printk("        SWF3%d                  0x%08x\n", i,
788                        hw->swf3x[i]);
789         }
790         for (i = 0; i < 8; i++)
791                 printk("        FENCE%d                 0x%08x\n", i,
792                        hw->fence[i]);
793
794         printk("        INSTPM                  0x%08x\n", hw->instpm);
795         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
796         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
797         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
798
799         printk("hw state dump end\n");
800 #endif
801 }
802
803
804
805 /* Split the M parameter into M1 and M2. */
806 static int
807 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
808 {
809         int m1, m2;
810         int testm;
811         struct pll_min_max *pll = &plls[index];
812
813         /* no point optimising too much - brute force m */
814         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
815                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
816                         testm = (5 * (m1 + 2)) + (m2 + 2);
817                         if (testm == m) {
818                                 *retm1 = (unsigned int)m1;
819                                 *retm2 = (unsigned int)m2;
820                                 return 0;
821                         }
822                 }
823         }
824         return 1;
825 }
826
827 /* Split the P parameter into P1 and P2. */
828 static int
829 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
830 {
831         int p1, p2;
832         struct pll_min_max *pll = &plls[index];
833
834         if (index == PLLS_I9xx) {
835                 p2 = (p % 10) ? 1 : 0;
836
837                 p1 = p / (p2 ? 5 : 10);
838
839                 *retp1 = (unsigned int)p1;
840                 *retp2 = (unsigned int)p2;
841                 return 0;
842         }
843
844         if (p % 4 == 0)
845                 p2 = 1;
846         else
847                 p2 = 0;
848         p1 = (p / (1 << (p2 + 1))) - 2;
849         if (p % 4 == 0 && p1 < pll->min_p1) {
850                 p2 = 0;
851                 p1 = (p / (1 << (p2 + 1))) - 2;
852         }
853         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
854             (p1 + 2) * (1 << (p2 + 1)) != p) {
855                 return 1;
856         } else {
857                 *retp1 = (unsigned int)p1;
858                 *retp2 = (unsigned int)p2;
859                 return 0;
860         }
861 }
862
863 static int
864 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
865                 u32 *retp2, u32 *retclock)
866 {
867         u32 m1, m2, n, p1, p2, n1, testm;
868         u32 f_vco, p, p_best = 0, m, f_out = 0;
869         u32 err_max, err_target, err_best = 10000000;
870         u32 n_best = 0, m_best = 0, f_best, f_err;
871         u32 p_min, p_max, p_inc, div_max;
872         struct pll_min_max *pll = &plls[index];
873
874         /* Accept 0.5% difference, but aim for 0.1% */
875         err_max = 5 * clock / 1000;
876         err_target = clock / 1000;
877
878         DBG_MSG("Clock is %d\n", clock);
879
880         div_max = pll->max_vco / clock;
881
882         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
883         p_min = p_inc;
884         p_max = ROUND_DOWN_TO(div_max, p_inc);
885         if (p_min < pll->min_p)
886                 p_min = pll->min_p;
887         if (p_max > pll->max_p)
888                 p_max = pll->max_p;
889
890         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
891
892         p = p_min;
893         do {
894                 if (splitp(index, p, &p1, &p2)) {
895                         WRN_MSG("cannot split p = %d\n", p);
896                         p += p_inc;
897                         continue;
898                 }
899                 n = pll->min_n;
900                 f_vco = clock * p;
901
902                 do {
903                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
904                         if (m < pll->min_m)
905                                 m = pll->min_m + 1;
906                         if (m > pll->max_m)
907                                 m = pll->max_m - 1;
908                         for (testm = m - 1; testm <= m; testm++) {
909                                 f_out = calc_vclock3(index, m, n, p);
910                                 if (splitm(index, testm, &m1, &m2)) {
911                                         WRN_MSG("cannot split m = %d\n", m);
912                                         n++;
913                                         continue;
914                                 }
915                                 if (clock > f_out)
916                                         f_err = clock - f_out;
917                                 else/* slightly bias the error for bigger clocks */
918                                         f_err = f_out - clock + 1;
919
920                                 if (f_err < err_best) {
921                                         m_best = testm;
922                                         n_best = n;
923                                         p_best = p;
924                                         f_best = f_out;
925                                         err_best = f_err;
926                                 }
927                         }
928                         n++;
929                 } while ((n <= pll->max_n) && (f_out >= clock));
930                 p += p_inc;
931         } while ((p <= p_max));
932
933         if (!m_best) {
934                 WRN_MSG("cannot find parameters for clock %d\n", clock);
935                 return 1;
936         }
937         m = m_best;
938         n = n_best;
939         p = p_best;
940         splitm(index, m, &m1, &m2);
941         splitp(index, p, &p1, &p2);
942         n1 = n - 2;
943
944         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
945                 "f: %d (%d), VCO: %d\n",
946                 m, m1, m2, n, n1, p, p1, p2,
947                 calc_vclock3(index, m, n, p),
948                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
949                 calc_vclock3(index, m, n, p) * p);
950         *retm1 = m1;
951         *retm2 = m2;
952         *retn = n1;
953         *retp1 = p1;
954         *retp2 = p2;
955         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
956
957         return 0;
958 }
959
960 static __inline__ int
961 check_overflow(u32 value, u32 limit, const char *description)
962 {
963         if (value > limit) {
964                 WRN_MSG("%s value %d exceeds limit %d\n",
965                         description, value, limit);
966                 return 1;
967         }
968         return 0;
969 }
970
971 /* It is assumed that hw is filled in with the initial state information. */
972 int
973 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
974                      struct fb_var_screeninfo *var)
975 {
976         int pipe = PIPE_A;
977         u32 *dpll, *fp0, *fp1;
978         u32 m1, m2, n, p1, p2, clock_target, clock;
979         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
980         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
981         u32 vsync_pol, hsync_pol;
982         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
983         u32 stride_alignment;
984
985         DBG_MSG("intelfbhw_mode_to_hw\n");
986
987         /* Disable VGA */
988         hw->vgacntrl |= VGA_DISABLE;
989
990         /* Check whether pipe A or pipe B is enabled. */
991         if (hw->pipe_a_conf & PIPECONF_ENABLE)
992                 pipe = PIPE_A;
993         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
994                 pipe = PIPE_B;
995
996         /* Set which pipe's registers will be set. */
997         if (pipe == PIPE_B) {
998                 dpll = &hw->dpll_b;
999                 fp0 = &hw->fpb0;
1000                 fp1 = &hw->fpb1;
1001                 hs = &hw->hsync_b;
1002                 hb = &hw->hblank_b;
1003                 ht = &hw->htotal_b;
1004                 vs = &hw->vsync_b;
1005                 vb = &hw->vblank_b;
1006                 vt = &hw->vtotal_b;
1007                 ss = &hw->src_size_b;
1008                 pipe_conf = &hw->pipe_b_conf;
1009         } else {
1010                 dpll = &hw->dpll_a;
1011                 fp0 = &hw->fpa0;
1012                 fp1 = &hw->fpa1;
1013                 hs = &hw->hsync_a;
1014                 hb = &hw->hblank_a;
1015                 ht = &hw->htotal_a;
1016                 vs = &hw->vsync_a;
1017                 vb = &hw->vblank_a;
1018                 vt = &hw->vtotal_a;
1019                 ss = &hw->src_size_a;
1020                 pipe_conf = &hw->pipe_a_conf;
1021         }
1022
1023         /* Use ADPA register for sync control. */
1024         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1025
1026         /* sync polarity */
1027         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1028                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1029         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1030                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1031         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1032                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1033         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1034                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1035
1036         /* Connect correct pipe to the analog port DAC */
1037         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1038         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1039
1040         /* Set DPMS state to D0 (on) */
1041         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1042         hw->adpa |= ADPA_DPMS_D0;
1043
1044         hw->adpa |= ADPA_DAC_ENABLE;
1045
1046         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1047         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1048         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1049
1050         /* Desired clock in kHz */
1051         clock_target = 1000000000 / var->pixclock;
1052
1053         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1054                             &n, &p1, &p2, &clock)) {
1055                 WRN_MSG("calc_pll_params failed\n");
1056                 return 1;
1057         }
1058
1059         /* Check for overflow. */
1060         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1061                 return 1;
1062         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1063                 return 1;
1064         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1065                 return 1;
1066         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1067                 return 1;
1068         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1069                 return 1;
1070
1071         *dpll &= ~DPLL_P1_FORCE_DIV2;
1072         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1073                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1074
1075         if (IS_I9XX(dinfo)) {
1076                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1077                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1078         } else {
1079                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1080         }
1081
1082         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1083                (m1 << FP_M1_DIVISOR_SHIFT) |
1084                (m2 << FP_M2_DIVISOR_SHIFT);
1085         *fp1 = *fp0;
1086
1087         hw->dvob &= ~PORT_ENABLE;
1088         hw->dvoc &= ~PORT_ENABLE;
1089
1090         /* Use display plane A. */
1091         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1092         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1093         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1094         switch (intelfb_var_to_depth(var)) {
1095         case 8:
1096                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1097                 break;
1098         case 15:
1099                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1100                 break;
1101         case 16:
1102                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1103                 break;
1104         case 24:
1105                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1106                 break;
1107         }
1108         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1109         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1110
1111         /* Set CRTC registers. */
1112         hactive = var->xres;
1113         hsync_start = hactive + var->right_margin;
1114         hsync_end = hsync_start + var->hsync_len;
1115         htotal = hsync_end + var->left_margin;
1116         hblank_start = hactive;
1117         hblank_end = htotal;
1118
1119         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1120                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1121                 hblank_end);
1122
1123         vactive = var->yres;
1124         vsync_start = vactive + var->lower_margin;
1125         vsync_end = vsync_start + var->vsync_len;
1126         vtotal = vsync_end + var->upper_margin;
1127         vblank_start = vactive;
1128         vblank_end = vtotal;
1129         vblank_end = vsync_end + 1;
1130
1131         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1132                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1133                 vblank_end);
1134
1135         /* Adjust for register values, and check for overflow. */
1136         hactive--;
1137         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1138                 return 1;
1139         hsync_start--;
1140         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1141                 return 1;
1142         hsync_end--;
1143         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1144                 return 1;
1145         htotal--;
1146         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1147                 return 1;
1148         hblank_start--;
1149         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1150                 return 1;
1151         hblank_end--;
1152         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1153                 return 1;
1154
1155         vactive--;
1156         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1157                 return 1;
1158         vsync_start--;
1159         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1160                 return 1;
1161         vsync_end--;
1162         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1163                 return 1;
1164         vtotal--;
1165         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1166                 return 1;
1167         vblank_start--;
1168         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1169                 return 1;
1170         vblank_end--;
1171         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1172                 return 1;
1173
1174         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1175         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1176               (hblank_end << HSYNCEND_SHIFT);
1177         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1178
1179         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1180         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1181               (vblank_end << VSYNCEND_SHIFT);
1182         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1183         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1184               (vactive << SRC_SIZE_VERT_SHIFT);
1185
1186         hw->disp_a_stride = dinfo->pitch;
1187         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1188
1189         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1190                           var->xoffset * var->bits_per_pixel / 8;
1191
1192         hw->disp_a_base += dinfo->fb.offset << 12;
1193
1194         /* Check stride alignment. */
1195         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1196                                             STRIDE_ALIGNMENT;
1197         if (hw->disp_a_stride % stride_alignment != 0) {
1198                 WRN_MSG("display stride %d has bad alignment %d\n",
1199                         hw->disp_a_stride, stride_alignment);
1200                 return 1;
1201         }
1202
1203         /* Set the palette to 8-bit mode. */
1204         *pipe_conf &= ~PIPECONF_GAMMA;
1205         return 0;
1206 }
1207
1208 /* Program a (non-VGA) video mode. */
1209 int
1210 intelfbhw_program_mode(struct intelfb_info *dinfo,
1211                      const struct intelfb_hwstate *hw, int blank)
1212 {
1213         int pipe = PIPE_A;
1214         u32 tmp;
1215         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1216         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1217         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1218         u32 hsync_reg, htotal_reg, hblank_reg;
1219         u32 vsync_reg, vtotal_reg, vblank_reg;
1220         u32 src_size_reg;
1221         u32 count, tmp_val[3];
1222
1223         /* Assume single pipe, display plane A, analog CRT. */
1224
1225 #if VERBOSE > 0
1226         DBG_MSG("intelfbhw_program_mode\n");
1227 #endif
1228
1229         /* Disable VGA */
1230         tmp = INREG(VGACNTRL);
1231         tmp |= VGA_DISABLE;
1232         OUTREG(VGACNTRL, tmp);
1233
1234         /* Check whether pipe A or pipe B is enabled. */
1235         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1236                 pipe = PIPE_A;
1237         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1238                 pipe = PIPE_B;
1239
1240         dinfo->pipe = pipe;
1241
1242         if (pipe == PIPE_B) {
1243                 dpll = &hw->dpll_b;
1244                 fp0 = &hw->fpb0;
1245                 fp1 = &hw->fpb1;
1246                 pipe_conf = &hw->pipe_b_conf;
1247                 hs = &hw->hsync_b;
1248                 hb = &hw->hblank_b;
1249                 ht = &hw->htotal_b;
1250                 vs = &hw->vsync_b;
1251                 vb = &hw->vblank_b;
1252                 vt = &hw->vtotal_b;
1253                 ss = &hw->src_size_b;
1254                 dpll_reg = DPLL_B;
1255                 fp0_reg = FPB0;
1256                 fp1_reg = FPB1;
1257                 pipe_conf_reg = PIPEBCONF;
1258                 hsync_reg = HSYNC_B;
1259                 htotal_reg = HTOTAL_B;
1260                 hblank_reg = HBLANK_B;
1261                 vsync_reg = VSYNC_B;
1262                 vtotal_reg = VTOTAL_B;
1263                 vblank_reg = VBLANK_B;
1264                 src_size_reg = SRC_SIZE_B;
1265         } else {
1266                 dpll = &hw->dpll_a;
1267                 fp0 = &hw->fpa0;
1268                 fp1 = &hw->fpa1;
1269                 pipe_conf = &hw->pipe_a_conf;
1270                 hs = &hw->hsync_a;
1271                 hb = &hw->hblank_a;
1272                 ht = &hw->htotal_a;
1273                 vs = &hw->vsync_a;
1274                 vb = &hw->vblank_a;
1275                 vt = &hw->vtotal_a;
1276                 ss = &hw->src_size_a;
1277                 dpll_reg = DPLL_A;
1278                 fp0_reg = FPA0;
1279                 fp1_reg = FPA1;
1280                 pipe_conf_reg = PIPEACONF;
1281                 hsync_reg = HSYNC_A;
1282                 htotal_reg = HTOTAL_A;
1283                 hblank_reg = HBLANK_A;
1284                 vsync_reg = VSYNC_A;
1285                 vtotal_reg = VTOTAL_A;
1286                 vblank_reg = VBLANK_A;
1287                 src_size_reg = SRC_SIZE_A;
1288         }
1289
1290         /* turn off pipe */
1291         tmp = INREG(pipe_conf_reg);
1292         tmp &= ~PIPECONF_ENABLE;
1293         OUTREG(pipe_conf_reg, tmp);
1294
1295         count = 0;
1296         do {
1297                 tmp_val[count%3] = INREG(0x70000);
1298                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1299                         break;
1300                 count++;
1301                 udelay(1);
1302                 if (count % 200 == 0) {
1303                         tmp = INREG(pipe_conf_reg);
1304                         tmp &= ~PIPECONF_ENABLE;
1305                         OUTREG(pipe_conf_reg, tmp);
1306                 }
1307         } while(count < 2000);
1308
1309         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1310
1311         /* Disable planes A and B. */
1312         tmp = INREG(DSPACNTR);
1313         tmp &= ~DISPPLANE_PLANE_ENABLE;
1314         OUTREG(DSPACNTR, tmp);
1315         tmp = INREG(DSPBCNTR);
1316         tmp &= ~DISPPLANE_PLANE_ENABLE;
1317         OUTREG(DSPBCNTR, tmp);
1318
1319         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1320         mdelay(20);
1321
1322         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1323         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1324         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1325
1326         /* Disable Sync */
1327         tmp = INREG(ADPA);
1328         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1329         tmp |= ADPA_DPMS_D3;
1330         OUTREG(ADPA, tmp);
1331
1332         /* do some funky magic - xyzzy */
1333         OUTREG(0x61204, 0xabcd0000);
1334
1335         /* turn off PLL */
1336         tmp = INREG(dpll_reg);
1337         dpll_reg &= ~DPLL_VCO_ENABLE;
1338         OUTREG(dpll_reg, tmp);
1339
1340         /* Set PLL parameters */
1341         OUTREG(fp0_reg, *fp0);
1342         OUTREG(fp1_reg, *fp1);
1343
1344         /* Enable PLL */
1345         OUTREG(dpll_reg, *dpll);
1346
1347         /* Set DVOs B/C */
1348         OUTREG(DVOB, hw->dvob);
1349         OUTREG(DVOC, hw->dvoc);
1350
1351         /* undo funky magic */
1352         OUTREG(0x61204, 0x00000000);
1353
1354         /* Set ADPA */
1355         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1356         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1357
1358         /* Set pipe parameters */
1359         OUTREG(hsync_reg, *hs);
1360         OUTREG(hblank_reg, *hb);
1361         OUTREG(htotal_reg, *ht);
1362         OUTREG(vsync_reg, *vs);
1363         OUTREG(vblank_reg, *vb);
1364         OUTREG(vtotal_reg, *vt);
1365         OUTREG(src_size_reg, *ss);
1366
1367         /* Enable pipe */
1368         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1369
1370         /* Enable sync */
1371         tmp = INREG(ADPA);
1372         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1373         tmp |= ADPA_DPMS_D0;
1374         OUTREG(ADPA, tmp);
1375
1376         /* setup display plane */
1377         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1378                 /*
1379                  *      i830M errata: the display plane must be enabled
1380                  *      to allow writes to the other bits in the plane
1381                  *      control register.
1382                  */
1383                 tmp = INREG(DSPACNTR);
1384                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1385                         tmp |= DISPPLANE_PLANE_ENABLE;
1386                         OUTREG(DSPACNTR, tmp);
1387                         OUTREG(DSPACNTR,
1388                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1389                         mdelay(1);
1390                 }
1391         }
1392
1393         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1394         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1395         OUTREG(DSPABASE, hw->disp_a_base);
1396
1397         /* Enable plane */
1398         if (!blank) {
1399                 tmp = INREG(DSPACNTR);
1400                 tmp |= DISPPLANE_PLANE_ENABLE;
1401                 OUTREG(DSPACNTR, tmp);
1402                 OUTREG(DSPABASE, hw->disp_a_base);
1403         }
1404
1405         return 0;
1406 }
1407
1408 /* forward declarations */
1409 static void refresh_ring(struct intelfb_info *dinfo);
1410 static void reset_state(struct intelfb_info *dinfo);
1411 static void do_flush(struct intelfb_info *dinfo);
1412
1413 static int
1414 wait_ring(struct intelfb_info *dinfo, int n)
1415 {
1416         int i = 0;
1417         unsigned long end;
1418         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1419
1420 #if VERBOSE > 0
1421         DBG_MSG("wait_ring: %d\n", n);
1422 #endif
1423
1424         end = jiffies + (HZ * 3);
1425         while (dinfo->ring_space < n) {
1426                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1427                                                    RING_HEAD_MASK);
1428                 if (dinfo->ring_tail + RING_MIN_FREE <
1429                     (u32 __iomem) dinfo->ring_head)
1430                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1431                                 - (dinfo->ring_tail + RING_MIN_FREE);
1432                 else
1433                         dinfo->ring_space = (dinfo->ring.size +
1434                                              (u32 __iomem) dinfo->ring_head)
1435                                 - (dinfo->ring_tail + RING_MIN_FREE);
1436                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1437                         end = jiffies + (HZ * 3);
1438                         last_head = (u32 __iomem) dinfo->ring_head;
1439                 }
1440                 i++;
1441                 if (time_before(end, jiffies)) {
1442                         if (!i) {
1443                                 /* Try again */
1444                                 reset_state(dinfo);
1445                                 refresh_ring(dinfo);
1446                                 do_flush(dinfo);
1447                                 end = jiffies + (HZ * 3);
1448                                 i = 1;
1449                         } else {
1450                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1451                                         dinfo->ring_space, n);
1452                                 WRN_MSG("lockup - turning off hardware "
1453                                         "acceleration\n");
1454                                 dinfo->ring_lockup = 1;
1455                                 break;
1456                         }
1457                 }
1458                 udelay(1);
1459         }
1460         return i;
1461 }
1462
1463 static void
1464 do_flush(struct intelfb_info *dinfo) {
1465         START_RING(2);
1466         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1467         OUT_RING(MI_NOOP);
1468         ADVANCE_RING();
1469 }
1470
1471 void
1472 intelfbhw_do_sync(struct intelfb_info *dinfo)
1473 {
1474 #if VERBOSE > 0
1475         DBG_MSG("intelfbhw_do_sync\n");
1476 #endif
1477
1478         if (!dinfo->accel)
1479                 return;
1480
1481         /*
1482          * Send a flush, then wait until the ring is empty.  This is what
1483          * the XFree86 driver does, and actually it doesn't seem a lot worse
1484          * than the recommended method (both have problems).
1485          */
1486         do_flush(dinfo);
1487         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1488         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1489 }
1490
1491 static void
1492 refresh_ring(struct intelfb_info *dinfo)
1493 {
1494 #if VERBOSE > 0
1495         DBG_MSG("refresh_ring\n");
1496 #endif
1497
1498         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1499                                            RING_HEAD_MASK);
1500         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1501         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1502                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1503                         - (dinfo->ring_tail + RING_MIN_FREE);
1504         else
1505                 dinfo->ring_space = (dinfo->ring.size +
1506                                      (u32 __iomem) dinfo->ring_head)
1507                         - (dinfo->ring_tail + RING_MIN_FREE);
1508 }
1509
1510 static void
1511 reset_state(struct intelfb_info *dinfo)
1512 {
1513         int i;
1514         u32 tmp;
1515
1516 #if VERBOSE > 0
1517         DBG_MSG("reset_state\n");
1518 #endif
1519
1520         for (i = 0; i < FENCE_NUM; i++)
1521                 OUTREG(FENCE + (i << 2), 0);
1522
1523         /* Flush the ring buffer if it's enabled. */
1524         tmp = INREG(PRI_RING_LENGTH);
1525         if (tmp & RING_ENABLE) {
1526 #if VERBOSE > 0
1527                 DBG_MSG("reset_state: ring was enabled\n");
1528 #endif
1529                 refresh_ring(dinfo);
1530                 intelfbhw_do_sync(dinfo);
1531                 DO_RING_IDLE();
1532         }
1533
1534         OUTREG(PRI_RING_LENGTH, 0);
1535         OUTREG(PRI_RING_HEAD, 0);
1536         OUTREG(PRI_RING_TAIL, 0);
1537         OUTREG(PRI_RING_START, 0);
1538 }
1539
1540 /* Stop the 2D engine, and turn off the ring buffer. */
1541 void
1542 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1543 {
1544 #if VERBOSE > 0
1545         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1546                 dinfo->ring_active);
1547 #endif
1548
1549         if (!dinfo->accel)
1550                 return;
1551
1552         dinfo->ring_active = 0;
1553         reset_state(dinfo);
1554 }
1555
1556 /*
1557  * Enable the ring buffer, and initialise the 2D engine.
1558  * It is assumed that the graphics engine has been stopped by previously
1559  * calling intelfb_2d_stop().
1560  */
1561 void
1562 intelfbhw_2d_start(struct intelfb_info *dinfo)
1563 {
1564 #if VERBOSE > 0
1565         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1566                 dinfo->accel, dinfo->ring_active);
1567 #endif
1568
1569         if (!dinfo->accel)
1570                 return;
1571
1572         /* Initialise the primary ring buffer. */
1573         OUTREG(PRI_RING_LENGTH, 0);
1574         OUTREG(PRI_RING_TAIL, 0);
1575         OUTREG(PRI_RING_HEAD, 0);
1576
1577         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1578         OUTREG(PRI_RING_LENGTH,
1579                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1580                 RING_NO_REPORT | RING_ENABLE);
1581         refresh_ring(dinfo);
1582         dinfo->ring_active = 1;
1583 }
1584
1585 /* 2D fillrect (solid fill or invert) */
1586 void
1587 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1588                       u32 color, u32 pitch, u32 bpp, u32 rop)
1589 {
1590         u32 br00, br09, br13, br14, br16;
1591
1592 #if VERBOSE > 0
1593         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1594                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1595 #endif
1596
1597         br00 = COLOR_BLT_CMD;
1598         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1599         br13 = (rop << ROP_SHIFT) | pitch;
1600         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1601         br16 = color;
1602
1603         switch (bpp) {
1604         case 8:
1605                 br13 |= COLOR_DEPTH_8;
1606                 break;
1607         case 16:
1608                 br13 |= COLOR_DEPTH_16;
1609                 break;
1610         case 32:
1611                 br13 |= COLOR_DEPTH_32;
1612                 br00 |= WRITE_ALPHA | WRITE_RGB;
1613                 break;
1614         }
1615
1616         START_RING(6);
1617         OUT_RING(br00);
1618         OUT_RING(br13);
1619         OUT_RING(br14);
1620         OUT_RING(br09);
1621         OUT_RING(br16);
1622         OUT_RING(MI_NOOP);
1623         ADVANCE_RING();
1624
1625 #if VERBOSE > 0
1626         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1627                 dinfo->ring_tail, dinfo->ring_space);
1628 #endif
1629 }
1630
1631 void
1632 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1633                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1634 {
1635         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1636
1637 #if VERBOSE > 0
1638         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1639                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1640 #endif
1641
1642         br00 = XY_SRC_COPY_BLT_CMD;
1643         br09 = dinfo->fb_start;
1644         br11 = (pitch << PITCH_SHIFT);
1645         br12 = dinfo->fb_start;
1646         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1647         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1648         br23 = ((dstx + w) << WIDTH_SHIFT) |
1649                ((dsty + h) << HEIGHT_SHIFT);
1650         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1651
1652         switch (bpp) {
1653         case 8:
1654                 br13 |= COLOR_DEPTH_8;
1655                 break;
1656         case 16:
1657                 br13 |= COLOR_DEPTH_16;
1658                 break;
1659         case 32:
1660                 br13 |= COLOR_DEPTH_32;
1661                 br00 |= WRITE_ALPHA | WRITE_RGB;
1662                 break;
1663         }
1664
1665         START_RING(8);
1666         OUT_RING(br00);
1667         OUT_RING(br13);
1668         OUT_RING(br22);
1669         OUT_RING(br23);
1670         OUT_RING(br09);
1671         OUT_RING(br26);
1672         OUT_RING(br11);
1673         OUT_RING(br12);
1674         ADVANCE_RING();
1675 }
1676
1677 int
1678 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1679                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1680 {
1681         int nbytes, ndwords, pad, tmp;
1682         u32 br00, br09, br13, br18, br19, br22, br23;
1683         int dat, ix, iy, iw;
1684         int i, j;
1685
1686 #if VERBOSE > 0
1687         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1688 #endif
1689
1690         /* size in bytes of a padded scanline */
1691         nbytes = ROUND_UP_TO(w, 16) / 8;
1692
1693         /* Total bytes of padded scanline data to write out. */
1694         nbytes = nbytes * h;
1695
1696         /*
1697          * Check if the glyph data exceeds the immediate mode limit.
1698          * It would take a large font (1K pixels) to hit this limit.
1699          */
1700         if (nbytes > MAX_MONO_IMM_SIZE)
1701                 return 0;
1702
1703         /* Src data is packaged a dword (32-bit) at a time. */
1704         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1705
1706         /*
1707          * Ring has to be padded to a quad word. But because the command starts
1708            with 7 bytes, pad only if there is an even number of ndwords
1709          */
1710         pad = !(ndwords % 2);
1711
1712         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1713         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1714         br09 = dinfo->fb_start;
1715         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1716         br18 = bg;
1717         br19 = fg;
1718         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1719         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1720
1721         switch (bpp) {
1722         case 8:
1723                 br13 |= COLOR_DEPTH_8;
1724                 break;
1725         case 16:
1726                 br13 |= COLOR_DEPTH_16;
1727                 break;
1728         case 32:
1729                 br13 |= COLOR_DEPTH_32;
1730                 br00 |= WRITE_ALPHA | WRITE_RGB;
1731                 break;
1732         }
1733
1734         START_RING(8 + ndwords);
1735         OUT_RING(br00);
1736         OUT_RING(br13);
1737         OUT_RING(br22);
1738         OUT_RING(br23);
1739         OUT_RING(br09);
1740         OUT_RING(br18);
1741         OUT_RING(br19);
1742         ix = iy = 0;
1743         iw = ROUND_UP_TO(w, 8) / 8;
1744         while (ndwords--) {
1745                 dat = 0;
1746                 for (j = 0; j < 2; ++j) {
1747                         for (i = 0; i < 2; ++i) {
1748                                 if (ix != iw || i == 0)
1749                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1750                         }
1751                         if (ix == iw && iy != (h-1)) {
1752                                 ix = 0;
1753                                 ++iy;
1754                         }
1755                 }
1756                 OUT_RING(dat);
1757         }
1758         if (pad)
1759                 OUT_RING(MI_NOOP);
1760         ADVANCE_RING();
1761
1762         return 1;
1763 }
1764
1765 /* HW cursor functions. */
1766 void
1767 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1768 {
1769         u32 tmp;
1770
1771 #if VERBOSE > 0
1772         DBG_MSG("intelfbhw_cursor_init\n");
1773 #endif
1774
1775         if (dinfo->mobile || IS_I9XX(dinfo)) {
1776                 if (!dinfo->cursor.physical)
1777                         return;
1778                 tmp = INREG(CURSOR_A_CONTROL);
1779                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1780                          CURSOR_MEM_TYPE_LOCAL |
1781                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1782                 tmp |= CURSOR_MODE_DISABLE;
1783                 OUTREG(CURSOR_A_CONTROL, tmp);
1784                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1785         } else {
1786                 tmp = INREG(CURSOR_CONTROL);
1787                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1788                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1789                 tmp = CURSOR_FORMAT_3C;
1790                 OUTREG(CURSOR_CONTROL, tmp);
1791                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1792                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1793                       (64 << CURSOR_SIZE_V_SHIFT);
1794                 OUTREG(CURSOR_SIZE, tmp);
1795         }
1796 }
1797
1798 void
1799 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1800 {
1801         u32 tmp;
1802
1803 #if VERBOSE > 0
1804         DBG_MSG("intelfbhw_cursor_hide\n");
1805 #endif
1806
1807         dinfo->cursor_on = 0;
1808         if (dinfo->mobile || IS_I9XX(dinfo)) {
1809                 if (!dinfo->cursor.physical)
1810                         return;
1811                 tmp = INREG(CURSOR_A_CONTROL);
1812                 tmp &= ~CURSOR_MODE_MASK;
1813                 tmp |= CURSOR_MODE_DISABLE;
1814                 OUTREG(CURSOR_A_CONTROL, tmp);
1815                 /* Flush changes */
1816                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1817         } else {
1818                 tmp = INREG(CURSOR_CONTROL);
1819                 tmp &= ~CURSOR_ENABLE;
1820                 OUTREG(CURSOR_CONTROL, tmp);
1821         }
1822 }
1823
1824 void
1825 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1826 {
1827         u32 tmp;
1828
1829 #if VERBOSE > 0
1830         DBG_MSG("intelfbhw_cursor_show\n");
1831 #endif
1832
1833         dinfo->cursor_on = 1;
1834
1835         if (dinfo->cursor_blanked)
1836                 return;
1837
1838         if (dinfo->mobile || IS_I9XX(dinfo)) {
1839                 if (!dinfo->cursor.physical)
1840                         return;
1841                 tmp = INREG(CURSOR_A_CONTROL);
1842                 tmp &= ~CURSOR_MODE_MASK;
1843                 tmp |= CURSOR_MODE_64_4C_AX;
1844                 OUTREG(CURSOR_A_CONTROL, tmp);
1845                 /* Flush changes */
1846                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1847         } else {
1848                 tmp = INREG(CURSOR_CONTROL);
1849                 tmp |= CURSOR_ENABLE;
1850                 OUTREG(CURSOR_CONTROL, tmp);
1851         }
1852 }
1853
1854 void
1855 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1856 {
1857         u32 tmp;
1858
1859 #if VERBOSE > 0
1860         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1861 #endif
1862
1863         /*
1864          * Sets the position. The coordinates are assumed to already
1865          * have any offset adjusted. Assume that the cursor is never
1866          * completely off-screen, and that x, y are always >= 0.
1867          */
1868
1869         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1870               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1871         OUTREG(CURSOR_A_POSITION, tmp);
1872
1873         if (IS_I9XX(dinfo)) {
1874                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1875         }
1876 }
1877
1878 void
1879 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1880 {
1881 #if VERBOSE > 0
1882         DBG_MSG("intelfbhw_cursor_setcolor\n");
1883 #endif
1884
1885         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1886         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1887         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1888         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1889 }
1890
1891 void
1892 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1893                       u8 *data)
1894 {
1895         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1896         int i, j, w = width / 8;
1897         int mod = width % 8, t_mask, d_mask;
1898
1899 #if VERBOSE > 0
1900         DBG_MSG("intelfbhw_cursor_load\n");
1901 #endif
1902
1903         if (!dinfo->cursor.virtual)
1904                 return;
1905
1906         t_mask = 0xff >> mod;
1907         d_mask = ~(0xff >> mod);
1908         for (i = height; i--; ) {
1909                 for (j = 0; j < w; j++) {
1910                         writeb(0x00, addr + j);
1911                         writeb(*(data++), addr + j+8);
1912                 }
1913                 if (mod) {
1914                         writeb(t_mask, addr + j);
1915                         writeb(*(data++) & d_mask, addr + j+8);
1916                 }
1917                 addr += 16;
1918         }
1919 }
1920
1921 void
1922 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1923         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1924         int i, j;
1925
1926 #if VERBOSE > 0
1927         DBG_MSG("intelfbhw_cursor_reset\n");
1928 #endif
1929
1930         if (!dinfo->cursor.virtual)
1931                 return;
1932
1933         for (i = 64; i--; ) {
1934                 for (j = 0; j < 8; j++) {
1935                         writeb(0xff, addr + j+0);
1936                         writeb(0x00, addr + j+8);
1937                 }
1938                 addr += 16;
1939         }
1940 }