16c9c192b4be6ada85205b9f82e16e9de1a800a7
[sfrench/cifs-2.6.git] / drivers / video / intelfb / intelfbhw.c
1 /*
2  * intelfb
3  *
4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5  *
6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7  *                   2004 Sylvain Meyer
8  *
9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
10  * the basic fbdev interfaces, is derived in part from the radeonfb and
11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
12  * provides the code to program the hardware.  Most of it is derived from
13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
14  * under a dual license (GPL and MIT/XFree86 license).
15  *
16  * Author: David Dawes
17  *
18  */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/fb.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37
38 #include <asm/io.h>
39
40 #include "intelfb.h"
41 #include "intelfbhw.h"
42
43 struct pll_min_max {
44         int min_m, max_m, min_m1, max_m1;
45         int min_m2, max_m2, min_n, max_n;
46         int min_p, max_p, min_p1, max_p1;
47         int min_vco, max_vco, p_transition_clk, ref_clk;
48         int p_inc_lo, p_inc_hi;
49 };
50
51 #define PLLS_I8xx 0
52 #define PLLS_I9xx 1
53 #define PLLS_MAX 2
54
55 static struct pll_min_max plls[PLLS_MAX] = {
56         { 108, 140, 18, 26,
57           6, 16, 3, 16,
58           4, 128, 0, 31,
59           930000, 1400000, 165000, 48000,
60           4, 2 }, //I8xx
61
62         { 75, 120, 10, 20,
63           5, 9, 4, 7,
64           5, 80, 1, 8,
65           1400000, 2800000, 200000, 96000,
66           10, 5 }  //I9xx
67 };
68
69 int
70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
71 {
72         u32 tmp;
73         if (!pdev || !dinfo)
74                 return 1;
75
76         switch (pdev->device) {
77         case PCI_DEVICE_ID_INTEL_830M:
78                 dinfo->name = "Intel(R) 830M";
79                 dinfo->chipset = INTEL_830M;
80                 dinfo->mobile = 1;
81                 dinfo->pll_index = PLLS_I8xx;
82                 return 0;
83         case PCI_DEVICE_ID_INTEL_845G:
84                 dinfo->name = "Intel(R) 845G";
85                 dinfo->chipset = INTEL_845G;
86                 dinfo->mobile = 0;
87                 dinfo->pll_index = PLLS_I8xx;
88                 return 0;
89         case PCI_DEVICE_ID_INTEL_85XGM:
90                 tmp = 0;
91                 dinfo->mobile = 1;
92                 dinfo->pll_index = PLLS_I8xx;
93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
95                         INTEL_85X_VARIANT_MASK) {
96                 case INTEL_VAR_855GME:
97                         dinfo->name = "Intel(R) 855GME";
98                         dinfo->chipset = INTEL_855GME;
99                         return 0;
100                 case INTEL_VAR_855GM:
101                         dinfo->name = "Intel(R) 855GM";
102                         dinfo->chipset = INTEL_855GM;
103                         return 0;
104                 case INTEL_VAR_852GME:
105                         dinfo->name = "Intel(R) 852GME";
106                         dinfo->chipset = INTEL_852GME;
107                         return 0;
108                 case INTEL_VAR_852GM:
109                         dinfo->name = "Intel(R) 852GM";
110                         dinfo->chipset = INTEL_852GM;
111                         return 0;
112                 default:
113                         dinfo->name = "Intel(R) 852GM/855GM";
114                         dinfo->chipset = INTEL_85XGM;
115                         return 0;
116                 }
117                 break;
118         case PCI_DEVICE_ID_INTEL_865G:
119                 dinfo->name = "Intel(R) 865G";
120                 dinfo->chipset = INTEL_865G;
121                 dinfo->mobile = 0;
122                 dinfo->pll_index = PLLS_I8xx;
123                 return 0;
124         case PCI_DEVICE_ID_INTEL_915G:
125                 dinfo->name = "Intel(R) 915G";
126                 dinfo->chipset = INTEL_915G;
127                 dinfo->mobile = 0;
128                 dinfo->pll_index = PLLS_I9xx;
129                 return 0;
130         case PCI_DEVICE_ID_INTEL_915GM:
131                 dinfo->name = "Intel(R) 915GM";
132                 dinfo->chipset = INTEL_915GM;
133                 dinfo->mobile = 1;
134                 dinfo->pll_index = PLLS_I9xx;
135                 return 0;
136         case PCI_DEVICE_ID_INTEL_945G:
137                 dinfo->name = "Intel(R) 945G";
138                 dinfo->chipset = INTEL_945G;
139                 dinfo->mobile = 0;
140                 dinfo->pll_index = PLLS_I9xx;
141                 return 0;
142         case PCI_DEVICE_ID_INTEL_945GM:
143                 dinfo->name = "Intel(R) 945GM";
144                 dinfo->chipset = INTEL_945GM;
145                 dinfo->mobile = 1;
146                 dinfo->pll_index = PLLS_I9xx;
147                 return 0;
148         default:
149                 return 1;
150         }
151 }
152
153 int
154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
155                      int *stolen_size)
156 {
157         struct pci_dev *bridge_dev;
158         u16 tmp;
159         int stolen_overhead;
160
161         if (!pdev || !aperture_size || !stolen_size)
162                 return 1;
163
164         /* Find the bridge device.  It is always 0:0.0 */
165         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
166                 ERR_MSG("cannot find bridge device\n");
167                 return 1;
168         }
169
170         /* Get the fb aperture size and "stolen" memory amount. */
171         tmp = 0;
172         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
173         switch (pdev->device) {
174         case PCI_DEVICE_ID_INTEL_915G:
175         case PCI_DEVICE_ID_INTEL_915GM:
176         case PCI_DEVICE_ID_INTEL_945G:
177         case PCI_DEVICE_ID_INTEL_945GM:
178                 /* 915 and 945 chipsets support a 256MB aperture.
179                    Aperture size is determined by inspected the
180                    base address of the aperture. */
181                 if (pci_resource_start(pdev, 2) & 0x08000000)
182                         *aperture_size = MB(128);
183                 else
184                         *aperture_size = MB(256);
185                 break;
186         default:
187                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
188                         *aperture_size = MB(64);
189                 else
190                         *aperture_size = MB(128);
191                 break;
192         }
193
194         /* Stolen memory size is reduced by the GTT and the popup.
195            GTT is 1K per MB of aperture size, and popup is 4K. */
196         stolen_overhead = (*aperture_size / MB(1)) + 4;
197         switch(pdev->device) {
198         case PCI_DEVICE_ID_INTEL_830M:
199         case PCI_DEVICE_ID_INTEL_845G:
200                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
201                 case INTEL_830_GMCH_GMS_STOLEN_512:
202                         *stolen_size = KB(512) - KB(stolen_overhead);
203                         return 0;
204                 case INTEL_830_GMCH_GMS_STOLEN_1024:
205                         *stolen_size = MB(1) - KB(stolen_overhead);
206                         return 0;
207                 case INTEL_830_GMCH_GMS_STOLEN_8192:
208                         *stolen_size = MB(8) - KB(stolen_overhead);
209                         return 0;
210                 case INTEL_830_GMCH_GMS_LOCAL:
211                         ERR_MSG("only local memory found\n");
212                         return 1;
213                 case INTEL_830_GMCH_GMS_DISABLED:
214                         ERR_MSG("video memory is disabled\n");
215                         return 1;
216                 default:
217                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
218                                 tmp & INTEL_830_GMCH_GMS_MASK);
219                         return 1;
220                 }
221                 break;
222         default:
223                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
224                 case INTEL_855_GMCH_GMS_STOLEN_1M:
225                         *stolen_size = MB(1) - KB(stolen_overhead);
226                         return 0;
227                 case INTEL_855_GMCH_GMS_STOLEN_4M:
228                         *stolen_size = MB(4) - KB(stolen_overhead);
229                         return 0;
230                 case INTEL_855_GMCH_GMS_STOLEN_8M:
231                         *stolen_size = MB(8) - KB(stolen_overhead);
232                         return 0;
233                 case INTEL_855_GMCH_GMS_STOLEN_16M:
234                         *stolen_size = MB(16) - KB(stolen_overhead);
235                         return 0;
236                 case INTEL_855_GMCH_GMS_STOLEN_32M:
237                         *stolen_size = MB(32) - KB(stolen_overhead);
238                         return 0;
239                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
240                         *stolen_size = MB(48) - KB(stolen_overhead);
241                         return 0;
242                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
243                         *stolen_size = MB(64) - KB(stolen_overhead);
244                         return 0;
245                 case INTEL_855_GMCH_GMS_DISABLED:
246                         ERR_MSG("video memory is disabled\n");
247                         return 0;
248                 default:
249                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
250                                 tmp & INTEL_855_GMCH_GMS_MASK);
251                         return 1;
252                 }
253         }
254 }
255
256 int
257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
258 {
259         int dvo = 0;
260
261         if (INREG(LVDS) & PORT_ENABLE)
262                 dvo |= LVDS_PORT;
263         if (INREG(DVOA) & PORT_ENABLE)
264                 dvo |= DVOA_PORT;
265         if (INREG(DVOB) & PORT_ENABLE)
266                 dvo |= DVOB_PORT;
267         if (INREG(DVOC) & PORT_ENABLE)
268                 dvo |= DVOC_PORT;
269
270         return dvo;
271 }
272
273 const char *
274 intelfbhw_dvo_to_string(int dvo)
275 {
276         if (dvo & DVOA_PORT)
277                 return "DVO port A";
278         else if (dvo & DVOB_PORT)
279                 return "DVO port B";
280         else if (dvo & DVOC_PORT)
281                 return "DVO port C";
282         else if (dvo & LVDS_PORT)
283                 return "LVDS port";
284         else
285                 return NULL;
286 }
287
288
289 int
290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
291                         struct fb_var_screeninfo *var)
292 {
293         int bytes_per_pixel;
294         int tmp;
295
296 #if VERBOSE > 0
297         DBG_MSG("intelfbhw_validate_mode\n");
298 #endif
299
300         bytes_per_pixel = var->bits_per_pixel / 8;
301         if (bytes_per_pixel == 3)
302                 bytes_per_pixel = 4;
303
304         /* Check if enough video memory. */
305         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
306         if (tmp > dinfo->fb.size) {
307                 WRN_MSG("Not enough video ram for mode "
308                         "(%d KByte vs %d KByte).\n",
309                         BtoKB(tmp), BtoKB(dinfo->fb.size));
310                 return 1;
311         }
312
313         /* Check if x/y limits are OK. */
314         if (var->xres - 1 > HACTIVE_MASK) {
315                 WRN_MSG("X resolution too large (%d vs %d).\n",
316                         var->xres, HACTIVE_MASK + 1);
317                 return 1;
318         }
319         if (var->yres - 1 > VACTIVE_MASK) {
320                 WRN_MSG("Y resolution too large (%d vs %d).\n",
321                         var->yres, VACTIVE_MASK + 1);
322                 return 1;
323         }
324
325         /* Check for interlaced/doublescan modes. */
326         if (var->vmode & FB_VMODE_INTERLACED) {
327                 WRN_MSG("Mode is interlaced.\n");
328                 return 1;
329         }
330         if (var->vmode & FB_VMODE_DOUBLE) {
331                 WRN_MSG("Mode is double-scan.\n");
332                 return 1;
333         }
334
335         /* Check if clock is OK. */
336         tmp = 1000000000 / var->pixclock;
337         if (tmp < MIN_CLOCK) {
338                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
339                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
340                 return 1;
341         }
342         if (tmp > MAX_CLOCK) {
343                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
344                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
345                 return 1;
346         }
347
348         return 0;
349 }
350
351 int
352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
353 {
354         struct intelfb_info *dinfo = GET_DINFO(info);
355         u32 offset, xoffset, yoffset;
356
357 #if VERBOSE > 0
358         DBG_MSG("intelfbhw_pan_display\n");
359 #endif
360
361         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
362         yoffset = var->yoffset;
363
364         if ((xoffset + var->xres > var->xres_virtual) ||
365             (yoffset + var->yres > var->yres_virtual))
366                 return -EINVAL;
367
368         offset = (yoffset * dinfo->pitch) +
369                  (xoffset * var->bits_per_pixel) / 8;
370
371         offset += dinfo->fb.offset << 12;
372
373         OUTREG(DSPABASE, offset);
374
375         return 0;
376 }
377
378 /* Blank the screen. */
379 void
380 intelfbhw_do_blank(int blank, struct fb_info *info)
381 {
382         struct intelfb_info *dinfo = GET_DINFO(info);
383         u32 tmp;
384
385 #if VERBOSE > 0
386         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
387 #endif
388
389         /* Turn plane A on or off */
390         tmp = INREG(DSPACNTR);
391         if (blank)
392                 tmp &= ~DISPPLANE_PLANE_ENABLE;
393         else
394                 tmp |= DISPPLANE_PLANE_ENABLE;
395         OUTREG(DSPACNTR, tmp);
396         /* Flush */
397         tmp = INREG(DSPABASE);
398         OUTREG(DSPABASE, tmp);
399
400         /* Turn off/on the HW cursor */
401 #if VERBOSE > 0
402         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
403 #endif
404         if (dinfo->cursor_on) {
405                 if (blank) {
406                         intelfbhw_cursor_hide(dinfo);
407                 } else {
408                         intelfbhw_cursor_show(dinfo);
409                 }
410                 dinfo->cursor_on = 1;
411         }
412         dinfo->cursor_blanked = blank;
413
414         /* Set DPMS level */
415         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
416         switch (blank) {
417         case FB_BLANK_UNBLANK:
418         case FB_BLANK_NORMAL:
419                 tmp |= ADPA_DPMS_D0;
420                 break;
421         case FB_BLANK_VSYNC_SUSPEND:
422                 tmp |= ADPA_DPMS_D1;
423                 break;
424         case FB_BLANK_HSYNC_SUSPEND:
425                 tmp |= ADPA_DPMS_D2;
426                 break;
427         case FB_BLANK_POWERDOWN:
428                 tmp |= ADPA_DPMS_D3;
429                 break;
430         }
431         OUTREG(ADPA, tmp);
432
433         return;
434 }
435
436
437 void
438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
439                     unsigned red, unsigned green, unsigned blue,
440                     unsigned transp)
441 {
442 #if VERBOSE > 0
443         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
444                 regno, red, green, blue);
445 #endif
446
447         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
448                           PALETTE_A : PALETTE_B;
449
450         OUTREG(palette_reg + (regno << 2),
451                (red << PALETTE_8_RED_SHIFT) |
452                (green << PALETTE_8_GREEN_SHIFT) |
453                (blue << PALETTE_8_BLUE_SHIFT));
454 }
455
456
457 int
458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
459                         int flag)
460 {
461         int i;
462
463 #if VERBOSE > 0
464         DBG_MSG("intelfbhw_read_hw_state\n");
465 #endif
466
467         if (!hw || !dinfo)
468                 return -1;
469
470         /* Read in as much of the HW state as possible. */
471         hw->vga0_divisor = INREG(VGA0_DIVISOR);
472         hw->vga1_divisor = INREG(VGA1_DIVISOR);
473         hw->vga_pd = INREG(VGAPD);
474         hw->dpll_a = INREG(DPLL_A);
475         hw->dpll_b = INREG(DPLL_B);
476         hw->fpa0 = INREG(FPA0);
477         hw->fpa1 = INREG(FPA1);
478         hw->fpb0 = INREG(FPB0);
479         hw->fpb1 = INREG(FPB1);
480
481         if (flag == 1)
482                 return flag;
483
484 #if 0
485         /* This seems to be a problem with the 852GM/855GM */
486         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
487                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
488                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
489         }
490 #endif
491
492         if (flag == 2)
493                 return flag;
494
495         hw->htotal_a = INREG(HTOTAL_A);
496         hw->hblank_a = INREG(HBLANK_A);
497         hw->hsync_a = INREG(HSYNC_A);
498         hw->vtotal_a = INREG(VTOTAL_A);
499         hw->vblank_a = INREG(VBLANK_A);
500         hw->vsync_a = INREG(VSYNC_A);
501         hw->src_size_a = INREG(SRC_SIZE_A);
502         hw->bclrpat_a = INREG(BCLRPAT_A);
503         hw->htotal_b = INREG(HTOTAL_B);
504         hw->hblank_b = INREG(HBLANK_B);
505         hw->hsync_b = INREG(HSYNC_B);
506         hw->vtotal_b = INREG(VTOTAL_B);
507         hw->vblank_b = INREG(VBLANK_B);
508         hw->vsync_b = INREG(VSYNC_B);
509         hw->src_size_b = INREG(SRC_SIZE_B);
510         hw->bclrpat_b = INREG(BCLRPAT_B);
511
512         if (flag == 3)
513                 return flag;
514
515         hw->adpa = INREG(ADPA);
516         hw->dvoa = INREG(DVOA);
517         hw->dvob = INREG(DVOB);
518         hw->dvoc = INREG(DVOC);
519         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
520         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
521         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
522         hw->lvds = INREG(LVDS);
523
524         if (flag == 4)
525                 return flag;
526
527         hw->pipe_a_conf = INREG(PIPEACONF);
528         hw->pipe_b_conf = INREG(PIPEBCONF);
529         hw->disp_arb = INREG(DISPARB);
530
531         if (flag == 5)
532                 return flag;
533
534         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
535         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
536         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
537         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
538
539         if (flag == 6)
540                 return flag;
541
542         for (i = 0; i < 4; i++) {
543                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
544                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
545         }
546
547         if (flag == 7)
548                 return flag;
549
550         hw->cursor_size = INREG(CURSOR_SIZE);
551
552         if (flag == 8)
553                 return flag;
554
555         hw->disp_a_ctrl = INREG(DSPACNTR);
556         hw->disp_b_ctrl = INREG(DSPBCNTR);
557         hw->disp_a_base = INREG(DSPABASE);
558         hw->disp_b_base = INREG(DSPBBASE);
559         hw->disp_a_stride = INREG(DSPASTRIDE);
560         hw->disp_b_stride = INREG(DSPBSTRIDE);
561
562         if (flag == 9)
563                 return flag;
564
565         hw->vgacntrl = INREG(VGACNTRL);
566
567         if (flag == 10)
568                 return flag;
569
570         hw->add_id = INREG(ADD_ID);
571
572         if (flag == 11)
573                 return flag;
574
575         for (i = 0; i < 7; i++) {
576                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
577                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
578                 if (i < 3)
579                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
580         }
581
582         for (i = 0; i < 8; i++)
583                 hw->fence[i] = INREG(FENCE + (i << 2));
584
585         hw->instpm = INREG(INSTPM);
586         hw->mem_mode = INREG(MEM_MODE);
587         hw->fw_blc_0 = INREG(FW_BLC_0);
588         hw->fw_blc_1 = INREG(FW_BLC_1);
589
590         return 0;
591 }
592
593
594 static int calc_vclock3(int index, int m, int n, int p)
595 {
596         if (p == 0 || n == 0)
597                 return 0;
598         return plls[index].ref_clk * m / n / p;
599 }
600
601 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
602 {
603         struct pll_min_max *pll = &plls[index];
604         u32 m, vco, p;
605
606         m = (5 * (m1 + 2)) + (m2 + 2);
607         n += 2;
608         vco = pll->ref_clk * m / n;
609
610         if (index == PLLS_I8xx) {
611                 p = ((p1 + 2) * (1 << (p2 + 1)));
612         } else {
613                 p = ((p1) * (p2 ? 5 : 10));
614         }
615         return vco / p;
616 }
617
618 void
619 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
620 {
621 #if REGDUMP
622         int i, m1, m2, n, p1, p2;
623         int index = dinfo->pll_index;
624         DBG_MSG("intelfbhw_print_hw_state\n");
625
626         if (!hw || !dinfo)
627                 return;
628         /* Read in as much of the HW state as possible. */
629         printk("hw state dump start\n");
630         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
631         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
632         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
633         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
634         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
635         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
636         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
637                 p1 = 0;
638         else
639                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
640
641         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
642
643         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
644                m1, m2, n, p1, p2);
645         printk("        VGA0: clock is %d\n",
646                calc_vclock(index, m1, m2, n, p1, p2, 0));
647
648         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
649         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
650         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
651         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
652                 p1 = 0;
653         else
654                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
655         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
656         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
657                m1, m2, n, p1, p2);
658         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
659
660         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
661         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
662         printk("        FPA0:                   0x%08x\n", hw->fpa0);
663         printk("        FPA1:                   0x%08x\n", hw->fpa1);
664         printk("        FPB0:                   0x%08x\n", hw->fpb0);
665         printk("        FPB1:                   0x%08x\n", hw->fpb1);
666
667         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
668         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
669         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
670
671         if (IS_I9XX(dinfo)) {
672                 int tmpp1;
673
674                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
675                         p1 = 0;
676                 else
677                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
678
679                 tmpp1 = p1;
680
681                 switch (tmpp1)
682                 {
683                 case 0x1: p1 = 1; break;
684                 case 0x2: p1 = 2; break;
685                 case 0x4: p1 = 3; break;
686                 case 0x8: p1 = 4; break;
687                 case 0x10: p1 = 5; break;
688                 case 0x20: p1 = 6; break;
689                 case 0x40: p1 = 7; break;
690                 case 0x80: p1 = 8; break;
691                 default: break;
692                 }
693
694                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
695
696         } else {
697                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
698                         p1 = 0;
699                 else
700                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
701                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
702         }
703
704         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
705                m1, m2, n, p1, p2);
706         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
707
708         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
709         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
710         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
711
712         if (IS_I9XX(dinfo)) {
713                 int tmpp1;
714
715                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
716                         p1 = 0;
717                 else
718                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
719
720                 tmpp1 = p1;
721
722                 switch (tmpp1) {
723                 case 0x1: p1 = 1; break;
724                 case 0x2: p1 = 2; break;
725                 case 0x4: p1 = 3; break;
726                 case 0x8: p1 = 4; break;
727                 case 0x10: p1 = 5; break;
728                 case 0x20: p1 = 6; break;
729                 case 0x40: p1 = 7; break;
730                 case 0x80: p1 = 8; break;
731                 default: break;
732                 }
733                 
734                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
735
736         } else {
737                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
738                         p1 = 0;
739                 else
740                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
741                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
742         }
743         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
744                m1, m2, n, p1, p2);
745         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
746
747 #if 0
748         printk("        PALETTE_A:\n");
749         for (i = 0; i < PALETTE_8_ENTRIES)
750                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
751         printk("        PALETTE_B:\n");
752         for (i = 0; i < PALETTE_8_ENTRIES)
753                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
754 #endif
755
756         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
757         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
758         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
759         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
760         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
761         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
762         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
763         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
764         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
765         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
766         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
767         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
768         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
769         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
770         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
771         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
772
773         printk("        ADPA:                   0x%08x\n", hw->adpa);
774         printk("        DVOA:                   0x%08x\n", hw->dvoa);
775         printk("        DVOB:                   0x%08x\n", hw->dvob);
776         printk("        DVOC:                   0x%08x\n", hw->dvoc);
777         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
778         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
779         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
780         printk("        LVDS:                   0x%08x\n", hw->lvds);
781
782         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
783         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
784         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
785
786         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
787         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
788         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
789         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
790
791         printk("        CURSOR_A_PALETTE:       ");
792         for (i = 0; i < 4; i++) {
793                 printk("0x%08x", hw->cursor_a_palette[i]);
794                 if (i < 3)
795                         printk(", ");
796         }
797         printk("\n");
798         printk("        CURSOR_B_PALETTE:       ");
799         for (i = 0; i < 4; i++) {
800                 printk("0x%08x", hw->cursor_b_palette[i]);
801                 if (i < 3)
802                         printk(", ");
803         }
804         printk("\n");
805
806         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
807
808         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
809         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
810         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
811         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
812         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
813         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
814
815         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
816         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
817
818         for (i = 0; i < 7; i++) {
819                 printk("        SWF0%d                  0x%08x\n", i,
820                         hw->swf0x[i]);
821         }
822         for (i = 0; i < 7; i++) {
823                 printk("        SWF1%d                  0x%08x\n", i,
824                         hw->swf1x[i]);
825         }
826         for (i = 0; i < 3; i++) {
827                 printk("        SWF3%d                  0x%08x\n", i,
828                        hw->swf3x[i]);
829         }
830         for (i = 0; i < 8; i++)
831                 printk("        FENCE%d                 0x%08x\n", i,
832                        hw->fence[i]);
833
834         printk("        INSTPM                  0x%08x\n", hw->instpm);
835         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
836         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
837         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
838
839         printk("hw state dump end\n");
840 #endif
841 }
842
843
844
845 /* Split the M parameter into M1 and M2. */
846 static int
847 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
848 {
849         int m1, m2;
850         int testm;
851         struct pll_min_max *pll = &plls[index];
852
853         /* no point optimising too much - brute force m */
854         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
855                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
856                         testm = (5 * (m1 + 2)) + (m2 + 2);
857                         if (testm == m) {
858                                 *retm1 = (unsigned int)m1;
859                                 *retm2 = (unsigned int)m2;
860                                 return 0;
861                         }
862                 }
863         }
864         return 1;
865 }
866
867 /* Split the P parameter into P1 and P2. */
868 static int
869 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
870 {
871         int p1, p2;
872         struct pll_min_max *pll = &plls[index];
873
874         if (index == PLLS_I9xx) {
875                 p2 = (p % 10) ? 1 : 0;
876
877                 p1 = p / (p2 ? 5 : 10);
878
879                 *retp1 = (unsigned int)p1;
880                 *retp2 = (unsigned int)p2;
881                 return 0;
882         }
883
884         if (p % 4 == 0)
885                 p2 = 1;
886         else
887                 p2 = 0;
888         p1 = (p / (1 << (p2 + 1))) - 2;
889         if (p % 4 == 0 && p1 < pll->min_p1) {
890                 p2 = 0;
891                 p1 = (p / (1 << (p2 + 1))) - 2;
892         }
893         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
894             (p1 + 2) * (1 << (p2 + 1)) != p) {
895                 return 1;
896         } else {
897                 *retp1 = (unsigned int)p1;
898                 *retp2 = (unsigned int)p2;
899                 return 0;
900         }
901 }
902
903 static int
904 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
905                 u32 *retp2, u32 *retclock)
906 {
907         u32 m1, m2, n, p1, p2, n1, testm;
908         u32 f_vco, p, p_best = 0, m, f_out = 0;
909         u32 err_max, err_target, err_best = 10000000;
910         u32 n_best = 0, m_best = 0, f_best, f_err;
911         u32 p_min, p_max, p_inc, div_max;
912         struct pll_min_max *pll = &plls[index];
913
914         /* Accept 0.5% difference, but aim for 0.1% */
915         err_max = 5 * clock / 1000;
916         err_target = clock / 1000;
917
918         DBG_MSG("Clock is %d\n", clock);
919
920         div_max = pll->max_vco / clock;
921
922         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
923         p_min = p_inc;
924         p_max = ROUND_DOWN_TO(div_max, p_inc);
925         if (p_min < pll->min_p)
926                 p_min = pll->min_p;
927         if (p_max > pll->max_p)
928                 p_max = pll->max_p;
929
930         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
931
932         p = p_min;
933         do {
934                 if (splitp(index, p, &p1, &p2)) {
935                         WRN_MSG("cannot split p = %d\n", p);
936                         p += p_inc;
937                         continue;
938                 }
939                 n = pll->min_n;
940                 f_vco = clock * p;
941
942                 do {
943                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
944                         if (m < pll->min_m)
945                                 m = pll->min_m + 1;
946                         if (m > pll->max_m)
947                                 m = pll->max_m - 1;
948                         for (testm = m - 1; testm <= m; testm++) {
949                                 f_out = calc_vclock3(index, m, n, p);
950                                 if (splitm(index, testm, &m1, &m2)) {
951                                         WRN_MSG("cannot split m = %d\n", m);
952                                         n++;
953                                         continue;
954                                 }
955                                 if (clock > f_out)
956                                         f_err = clock - f_out;
957                                 else/* slightly bias the error for bigger clocks */
958                                         f_err = f_out - clock + 1;
959
960                                 if (f_err < err_best) {
961                                         m_best = testm;
962                                         n_best = n;
963                                         p_best = p;
964                                         f_best = f_out;
965                                         err_best = f_err;
966                                 }
967                         }
968                         n++;
969                 } while ((n <= pll->max_n) && (f_out >= clock));
970                 p += p_inc;
971         } while ((p <= p_max));
972
973         if (!m_best) {
974                 WRN_MSG("cannot find parameters for clock %d\n", clock);
975                 return 1;
976         }
977         m = m_best;
978         n = n_best;
979         p = p_best;
980         splitm(index, m, &m1, &m2);
981         splitp(index, p, &p1, &p2);
982         n1 = n - 2;
983
984         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
985                 "f: %d (%d), VCO: %d\n",
986                 m, m1, m2, n, n1, p, p1, p2,
987                 calc_vclock3(index, m, n, p),
988                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
989                 calc_vclock3(index, m, n, p) * p);
990         *retm1 = m1;
991         *retm2 = m2;
992         *retn = n1;
993         *retp1 = p1;
994         *retp2 = p2;
995         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
996
997         return 0;
998 }
999
1000 static __inline__ int
1001 check_overflow(u32 value, u32 limit, const char *description)
1002 {
1003         if (value > limit) {
1004                 WRN_MSG("%s value %d exceeds limit %d\n",
1005                         description, value, limit);
1006                 return 1;
1007         }
1008         return 0;
1009 }
1010
1011 /* It is assumed that hw is filled in with the initial state information. */
1012 int
1013 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
1014                      struct fb_var_screeninfo *var)
1015 {
1016         int pipe = PIPE_A;
1017         u32 *dpll, *fp0, *fp1;
1018         u32 m1, m2, n, p1, p2, clock_target, clock;
1019         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1020         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1021         u32 vsync_pol, hsync_pol;
1022         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1023         u32 stride_alignment;
1024
1025         DBG_MSG("intelfbhw_mode_to_hw\n");
1026
1027         /* Disable VGA */
1028         hw->vgacntrl |= VGA_DISABLE;
1029
1030         /* Check whether pipe A or pipe B is enabled. */
1031         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1032                 pipe = PIPE_A;
1033         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1034                 pipe = PIPE_B;
1035
1036         /* Set which pipe's registers will be set. */
1037         if (pipe == PIPE_B) {
1038                 dpll = &hw->dpll_b;
1039                 fp0 = &hw->fpb0;
1040                 fp1 = &hw->fpb1;
1041                 hs = &hw->hsync_b;
1042                 hb = &hw->hblank_b;
1043                 ht = &hw->htotal_b;
1044                 vs = &hw->vsync_b;
1045                 vb = &hw->vblank_b;
1046                 vt = &hw->vtotal_b;
1047                 ss = &hw->src_size_b;
1048                 pipe_conf = &hw->pipe_b_conf;
1049         } else {
1050                 dpll = &hw->dpll_a;
1051                 fp0 = &hw->fpa0;
1052                 fp1 = &hw->fpa1;
1053                 hs = &hw->hsync_a;
1054                 hb = &hw->hblank_a;
1055                 ht = &hw->htotal_a;
1056                 vs = &hw->vsync_a;
1057                 vb = &hw->vblank_a;
1058                 vt = &hw->vtotal_a;
1059                 ss = &hw->src_size_a;
1060                 pipe_conf = &hw->pipe_a_conf;
1061         }
1062
1063         /* Use ADPA register for sync control. */
1064         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1065
1066         /* sync polarity */
1067         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1068                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1069         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1070                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1071         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1072                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1073         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1074                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1075
1076         /* Connect correct pipe to the analog port DAC */
1077         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1078         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1079
1080         /* Set DPMS state to D0 (on) */
1081         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1082         hw->adpa |= ADPA_DPMS_D0;
1083
1084         hw->adpa |= ADPA_DAC_ENABLE;
1085
1086         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1087         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1088         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1089
1090         /* Desired clock in kHz */
1091         clock_target = 1000000000 / var->pixclock;
1092
1093         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1094                             &n, &p1, &p2, &clock)) {
1095                 WRN_MSG("calc_pll_params failed\n");
1096                 return 1;
1097         }
1098
1099         /* Check for overflow. */
1100         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1101                 return 1;
1102         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1103                 return 1;
1104         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1105                 return 1;
1106         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1107                 return 1;
1108         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1109                 return 1;
1110
1111         *dpll &= ~DPLL_P1_FORCE_DIV2;
1112         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1113                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1114
1115         if (IS_I9XX(dinfo)) {
1116                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1117                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1118         } else {
1119                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1120         }
1121
1122         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1123                (m1 << FP_M1_DIVISOR_SHIFT) |
1124                (m2 << FP_M2_DIVISOR_SHIFT);
1125         *fp1 = *fp0;
1126
1127         hw->dvob &= ~PORT_ENABLE;
1128         hw->dvoc &= ~PORT_ENABLE;
1129
1130         /* Use display plane A. */
1131         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1132         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1133         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1134         switch (intelfb_var_to_depth(var)) {
1135         case 8:
1136                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1137                 break;
1138         case 15:
1139                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1140                 break;
1141         case 16:
1142                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1143                 break;
1144         case 24:
1145                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1146                 break;
1147         }
1148         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1149         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1150
1151         /* Set CRTC registers. */
1152         hactive = var->xres;
1153         hsync_start = hactive + var->right_margin;
1154         hsync_end = hsync_start + var->hsync_len;
1155         htotal = hsync_end + var->left_margin;
1156         hblank_start = hactive;
1157         hblank_end = htotal;
1158
1159         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1160                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1161                 hblank_end);
1162
1163         vactive = var->yres;
1164         vsync_start = vactive + var->lower_margin;
1165         vsync_end = vsync_start + var->vsync_len;
1166         vtotal = vsync_end + var->upper_margin;
1167         vblank_start = vactive;
1168         vblank_end = vtotal;
1169         vblank_end = vsync_end + 1;
1170
1171         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1172                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1173                 vblank_end);
1174
1175         /* Adjust for register values, and check for overflow. */
1176         hactive--;
1177         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1178                 return 1;
1179         hsync_start--;
1180         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1181                 return 1;
1182         hsync_end--;
1183         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1184                 return 1;
1185         htotal--;
1186         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1187                 return 1;
1188         hblank_start--;
1189         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1190                 return 1;
1191         hblank_end--;
1192         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1193                 return 1;
1194
1195         vactive--;
1196         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1197                 return 1;
1198         vsync_start--;
1199         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1200                 return 1;
1201         vsync_end--;
1202         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1203                 return 1;
1204         vtotal--;
1205         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1206                 return 1;
1207         vblank_start--;
1208         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1209                 return 1;
1210         vblank_end--;
1211         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1212                 return 1;
1213
1214         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1215         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1216               (hblank_end << HSYNCEND_SHIFT);
1217         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1218
1219         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1220         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1221               (vblank_end << VSYNCEND_SHIFT);
1222         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1223         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1224               (vactive << SRC_SIZE_VERT_SHIFT);
1225
1226         hw->disp_a_stride = dinfo->pitch;
1227         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1228
1229         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1230                           var->xoffset * var->bits_per_pixel / 8;
1231
1232         hw->disp_a_base += dinfo->fb.offset << 12;
1233
1234         /* Check stride alignment. */
1235         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1236                                             STRIDE_ALIGNMENT;
1237         if (hw->disp_a_stride % stride_alignment != 0) {
1238                 WRN_MSG("display stride %d has bad alignment %d\n",
1239                         hw->disp_a_stride, stride_alignment);
1240                 return 1;
1241         }
1242
1243         /* Set the palette to 8-bit mode. */
1244         *pipe_conf &= ~PIPECONF_GAMMA;
1245         return 0;
1246 }
1247
1248 /* Program a (non-VGA) video mode. */
1249 int
1250 intelfbhw_program_mode(struct intelfb_info *dinfo,
1251                      const struct intelfb_hwstate *hw, int blank)
1252 {
1253         int pipe = PIPE_A;
1254         u32 tmp;
1255         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1256         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1257         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1258         u32 hsync_reg, htotal_reg, hblank_reg;
1259         u32 vsync_reg, vtotal_reg, vblank_reg;
1260         u32 src_size_reg;
1261         u32 count, tmp_val[3];
1262
1263         /* Assume single pipe, display plane A, analog CRT. */
1264
1265 #if VERBOSE > 0
1266         DBG_MSG("intelfbhw_program_mode\n");
1267 #endif
1268
1269         /* Disable VGA */
1270         tmp = INREG(VGACNTRL);
1271         tmp |= VGA_DISABLE;
1272         OUTREG(VGACNTRL, tmp);
1273
1274         /* Check whether pipe A or pipe B is enabled. */
1275         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1276                 pipe = PIPE_A;
1277         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1278                 pipe = PIPE_B;
1279
1280         dinfo->pipe = pipe;
1281
1282         if (pipe == PIPE_B) {
1283                 dpll = &hw->dpll_b;
1284                 fp0 = &hw->fpb0;
1285                 fp1 = &hw->fpb1;
1286                 pipe_conf = &hw->pipe_b_conf;
1287                 hs = &hw->hsync_b;
1288                 hb = &hw->hblank_b;
1289                 ht = &hw->htotal_b;
1290                 vs = &hw->vsync_b;
1291                 vb = &hw->vblank_b;
1292                 vt = &hw->vtotal_b;
1293                 ss = &hw->src_size_b;
1294                 dpll_reg = DPLL_B;
1295                 fp0_reg = FPB0;
1296                 fp1_reg = FPB1;
1297                 pipe_conf_reg = PIPEBCONF;
1298                 hsync_reg = HSYNC_B;
1299                 htotal_reg = HTOTAL_B;
1300                 hblank_reg = HBLANK_B;
1301                 vsync_reg = VSYNC_B;
1302                 vtotal_reg = VTOTAL_B;
1303                 vblank_reg = VBLANK_B;
1304                 src_size_reg = SRC_SIZE_B;
1305         } else {
1306                 dpll = &hw->dpll_a;
1307                 fp0 = &hw->fpa0;
1308                 fp1 = &hw->fpa1;
1309                 pipe_conf = &hw->pipe_a_conf;
1310                 hs = &hw->hsync_a;
1311                 hb = &hw->hblank_a;
1312                 ht = &hw->htotal_a;
1313                 vs = &hw->vsync_a;
1314                 vb = &hw->vblank_a;
1315                 vt = &hw->vtotal_a;
1316                 ss = &hw->src_size_a;
1317                 dpll_reg = DPLL_A;
1318                 fp0_reg = FPA0;
1319                 fp1_reg = FPA1;
1320                 pipe_conf_reg = PIPEACONF;
1321                 hsync_reg = HSYNC_A;
1322                 htotal_reg = HTOTAL_A;
1323                 hblank_reg = HBLANK_A;
1324                 vsync_reg = VSYNC_A;
1325                 vtotal_reg = VTOTAL_A;
1326                 vblank_reg = VBLANK_A;
1327                 src_size_reg = SRC_SIZE_A;
1328         }
1329
1330         /* turn off pipe */
1331         tmp = INREG(pipe_conf_reg);
1332         tmp &= ~PIPECONF_ENABLE;
1333         OUTREG(pipe_conf_reg, tmp);
1334
1335         count = 0;
1336         do {
1337                 tmp_val[count%3] = INREG(0x70000);
1338                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1339                         break;
1340                 count++;
1341                 udelay(1);
1342                 if (count % 200 == 0) {
1343                         tmp = INREG(pipe_conf_reg);
1344                         tmp &= ~PIPECONF_ENABLE;
1345                         OUTREG(pipe_conf_reg, tmp);
1346                 }
1347         } while(count < 2000);
1348
1349         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1350
1351         /* Disable planes A and B. */
1352         tmp = INREG(DSPACNTR);
1353         tmp &= ~DISPPLANE_PLANE_ENABLE;
1354         OUTREG(DSPACNTR, tmp);
1355         tmp = INREG(DSPBCNTR);
1356         tmp &= ~DISPPLANE_PLANE_ENABLE;
1357         OUTREG(DSPBCNTR, tmp);
1358
1359         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1360         mdelay(20);
1361
1362         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1363         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1364         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1365
1366         /* Disable Sync */
1367         tmp = INREG(ADPA);
1368         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1369         tmp |= ADPA_DPMS_D3;
1370         OUTREG(ADPA, tmp);
1371
1372         /* do some funky magic - xyzzy */
1373         OUTREG(0x61204, 0xabcd0000);
1374
1375         /* turn off PLL */
1376         tmp = INREG(dpll_reg);
1377         dpll_reg &= ~DPLL_VCO_ENABLE;
1378         OUTREG(dpll_reg, tmp);
1379
1380         /* Set PLL parameters */
1381         OUTREG(fp0_reg, *fp0);
1382         OUTREG(fp1_reg, *fp1);
1383
1384         /* Enable PLL */
1385         OUTREG(dpll_reg, *dpll);
1386
1387         /* Set DVOs B/C */
1388         OUTREG(DVOB, hw->dvob);
1389         OUTREG(DVOC, hw->dvoc);
1390
1391         /* undo funky magic */
1392         OUTREG(0x61204, 0x00000000);
1393
1394         /* Set ADPA */
1395         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1396         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1397
1398         /* Set pipe parameters */
1399         OUTREG(hsync_reg, *hs);
1400         OUTREG(hblank_reg, *hb);
1401         OUTREG(htotal_reg, *ht);
1402         OUTREG(vsync_reg, *vs);
1403         OUTREG(vblank_reg, *vb);
1404         OUTREG(vtotal_reg, *vt);
1405         OUTREG(src_size_reg, *ss);
1406
1407         /* Enable pipe */
1408         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1409
1410         /* Enable sync */
1411         tmp = INREG(ADPA);
1412         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1413         tmp |= ADPA_DPMS_D0;
1414         OUTREG(ADPA, tmp);
1415
1416         /* setup display plane */
1417         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1418                 /*
1419                  *      i830M errata: the display plane must be enabled
1420                  *      to allow writes to the other bits in the plane
1421                  *      control register.
1422                  */
1423                 tmp = INREG(DSPACNTR);
1424                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1425                         tmp |= DISPPLANE_PLANE_ENABLE;
1426                         OUTREG(DSPACNTR, tmp);
1427                         OUTREG(DSPACNTR,
1428                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1429                         mdelay(1);
1430                 }
1431         }
1432
1433         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1434         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1435         OUTREG(DSPABASE, hw->disp_a_base);
1436
1437         /* Enable plane */
1438         if (!blank) {
1439                 tmp = INREG(DSPACNTR);
1440                 tmp |= DISPPLANE_PLANE_ENABLE;
1441                 OUTREG(DSPACNTR, tmp);
1442                 OUTREG(DSPABASE, hw->disp_a_base);
1443         }
1444
1445         return 0;
1446 }
1447
1448 /* forward declarations */
1449 static void refresh_ring(struct intelfb_info *dinfo);
1450 static void reset_state(struct intelfb_info *dinfo);
1451 static void do_flush(struct intelfb_info *dinfo);
1452
1453 static int
1454 wait_ring(struct intelfb_info *dinfo, int n)
1455 {
1456         int i = 0;
1457         unsigned long end;
1458         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1459
1460 #if VERBOSE > 0
1461         DBG_MSG("wait_ring: %d\n", n);
1462 #endif
1463
1464         end = jiffies + (HZ * 3);
1465         while (dinfo->ring_space < n) {
1466                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1467                                                    RING_HEAD_MASK);
1468                 if (dinfo->ring_tail + RING_MIN_FREE <
1469                     (u32 __iomem) dinfo->ring_head)
1470                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1471                                 - (dinfo->ring_tail + RING_MIN_FREE);
1472                 else
1473                         dinfo->ring_space = (dinfo->ring.size +
1474                                              (u32 __iomem) dinfo->ring_head)
1475                                 - (dinfo->ring_tail + RING_MIN_FREE);
1476                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1477                         end = jiffies + (HZ * 3);
1478                         last_head = (u32 __iomem) dinfo->ring_head;
1479                 }
1480                 i++;
1481                 if (time_before(end, jiffies)) {
1482                         if (!i) {
1483                                 /* Try again */
1484                                 reset_state(dinfo);
1485                                 refresh_ring(dinfo);
1486                                 do_flush(dinfo);
1487                                 end = jiffies + (HZ * 3);
1488                                 i = 1;
1489                         } else {
1490                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1491                                         dinfo->ring_space, n);
1492                                 WRN_MSG("lockup - turning off hardware "
1493                                         "acceleration\n");
1494                                 dinfo->ring_lockup = 1;
1495                                 break;
1496                         }
1497                 }
1498                 udelay(1);
1499         }
1500         return i;
1501 }
1502
1503 static void
1504 do_flush(struct intelfb_info *dinfo) {
1505         START_RING(2);
1506         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1507         OUT_RING(MI_NOOP);
1508         ADVANCE_RING();
1509 }
1510
1511 void
1512 intelfbhw_do_sync(struct intelfb_info *dinfo)
1513 {
1514 #if VERBOSE > 0
1515         DBG_MSG("intelfbhw_do_sync\n");
1516 #endif
1517
1518         if (!dinfo->accel)
1519                 return;
1520
1521         /*
1522          * Send a flush, then wait until the ring is empty.  This is what
1523          * the XFree86 driver does, and actually it doesn't seem a lot worse
1524          * than the recommended method (both have problems).
1525          */
1526         do_flush(dinfo);
1527         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1528         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1529 }
1530
1531 static void
1532 refresh_ring(struct intelfb_info *dinfo)
1533 {
1534 #if VERBOSE > 0
1535         DBG_MSG("refresh_ring\n");
1536 #endif
1537
1538         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1539                                            RING_HEAD_MASK);
1540         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1541         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1542                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1543                         - (dinfo->ring_tail + RING_MIN_FREE);
1544         else
1545                 dinfo->ring_space = (dinfo->ring.size +
1546                                      (u32 __iomem) dinfo->ring_head)
1547                         - (dinfo->ring_tail + RING_MIN_FREE);
1548 }
1549
1550 static void
1551 reset_state(struct intelfb_info *dinfo)
1552 {
1553         int i;
1554         u32 tmp;
1555
1556 #if VERBOSE > 0
1557         DBG_MSG("reset_state\n");
1558 #endif
1559
1560         for (i = 0; i < FENCE_NUM; i++)
1561                 OUTREG(FENCE + (i << 2), 0);
1562
1563         /* Flush the ring buffer if it's enabled. */
1564         tmp = INREG(PRI_RING_LENGTH);
1565         if (tmp & RING_ENABLE) {
1566 #if VERBOSE > 0
1567                 DBG_MSG("reset_state: ring was enabled\n");
1568 #endif
1569                 refresh_ring(dinfo);
1570                 intelfbhw_do_sync(dinfo);
1571                 DO_RING_IDLE();
1572         }
1573
1574         OUTREG(PRI_RING_LENGTH, 0);
1575         OUTREG(PRI_RING_HEAD, 0);
1576         OUTREG(PRI_RING_TAIL, 0);
1577         OUTREG(PRI_RING_START, 0);
1578 }
1579
1580 /* Stop the 2D engine, and turn off the ring buffer. */
1581 void
1582 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1583 {
1584 #if VERBOSE > 0
1585         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1586                 dinfo->ring_active);
1587 #endif
1588
1589         if (!dinfo->accel)
1590                 return;
1591
1592         dinfo->ring_active = 0;
1593         reset_state(dinfo);
1594 }
1595
1596 /*
1597  * Enable the ring buffer, and initialise the 2D engine.
1598  * It is assumed that the graphics engine has been stopped by previously
1599  * calling intelfb_2d_stop().
1600  */
1601 void
1602 intelfbhw_2d_start(struct intelfb_info *dinfo)
1603 {
1604 #if VERBOSE > 0
1605         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1606                 dinfo->accel, dinfo->ring_active);
1607 #endif
1608
1609         if (!dinfo->accel)
1610                 return;
1611
1612         /* Initialise the primary ring buffer. */
1613         OUTREG(PRI_RING_LENGTH, 0);
1614         OUTREG(PRI_RING_TAIL, 0);
1615         OUTREG(PRI_RING_HEAD, 0);
1616
1617         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1618         OUTREG(PRI_RING_LENGTH,
1619                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1620                 RING_NO_REPORT | RING_ENABLE);
1621         refresh_ring(dinfo);
1622         dinfo->ring_active = 1;
1623 }
1624
1625 /* 2D fillrect (solid fill or invert) */
1626 void
1627 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1628                       u32 color, u32 pitch, u32 bpp, u32 rop)
1629 {
1630         u32 br00, br09, br13, br14, br16;
1631
1632 #if VERBOSE > 0
1633         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1634                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1635 #endif
1636
1637         br00 = COLOR_BLT_CMD;
1638         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1639         br13 = (rop << ROP_SHIFT) | pitch;
1640         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1641         br16 = color;
1642
1643         switch (bpp) {
1644         case 8:
1645                 br13 |= COLOR_DEPTH_8;
1646                 break;
1647         case 16:
1648                 br13 |= COLOR_DEPTH_16;
1649                 break;
1650         case 32:
1651                 br13 |= COLOR_DEPTH_32;
1652                 br00 |= WRITE_ALPHA | WRITE_RGB;
1653                 break;
1654         }
1655
1656         START_RING(6);
1657         OUT_RING(br00);
1658         OUT_RING(br13);
1659         OUT_RING(br14);
1660         OUT_RING(br09);
1661         OUT_RING(br16);
1662         OUT_RING(MI_NOOP);
1663         ADVANCE_RING();
1664
1665 #if VERBOSE > 0
1666         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1667                 dinfo->ring_tail, dinfo->ring_space);
1668 #endif
1669 }
1670
1671 void
1672 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1673                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1674 {
1675         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1676
1677 #if VERBOSE > 0
1678         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1679                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1680 #endif
1681
1682         br00 = XY_SRC_COPY_BLT_CMD;
1683         br09 = dinfo->fb_start;
1684         br11 = (pitch << PITCH_SHIFT);
1685         br12 = dinfo->fb_start;
1686         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1687         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1688         br23 = ((dstx + w) << WIDTH_SHIFT) |
1689                ((dsty + h) << HEIGHT_SHIFT);
1690         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1691
1692         switch (bpp) {
1693         case 8:
1694                 br13 |= COLOR_DEPTH_8;
1695                 break;
1696         case 16:
1697                 br13 |= COLOR_DEPTH_16;
1698                 break;
1699         case 32:
1700                 br13 |= COLOR_DEPTH_32;
1701                 br00 |= WRITE_ALPHA | WRITE_RGB;
1702                 break;
1703         }
1704
1705         START_RING(8);
1706         OUT_RING(br00);
1707         OUT_RING(br13);
1708         OUT_RING(br22);
1709         OUT_RING(br23);
1710         OUT_RING(br09);
1711         OUT_RING(br26);
1712         OUT_RING(br11);
1713         OUT_RING(br12);
1714         ADVANCE_RING();
1715 }
1716
1717 int
1718 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1719                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1720 {
1721         int nbytes, ndwords, pad, tmp;
1722         u32 br00, br09, br13, br18, br19, br22, br23;
1723         int dat, ix, iy, iw;
1724         int i, j;
1725
1726 #if VERBOSE > 0
1727         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1728 #endif
1729
1730         /* size in bytes of a padded scanline */
1731         nbytes = ROUND_UP_TO(w, 16) / 8;
1732
1733         /* Total bytes of padded scanline data to write out. */
1734         nbytes = nbytes * h;
1735
1736         /*
1737          * Check if the glyph data exceeds the immediate mode limit.
1738          * It would take a large font (1K pixels) to hit this limit.
1739          */
1740         if (nbytes > MAX_MONO_IMM_SIZE)
1741                 return 0;
1742
1743         /* Src data is packaged a dword (32-bit) at a time. */
1744         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1745
1746         /*
1747          * Ring has to be padded to a quad word. But because the command starts
1748            with 7 bytes, pad only if there is an even number of ndwords
1749          */
1750         pad = !(ndwords % 2);
1751
1752         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1753         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1754         br09 = dinfo->fb_start;
1755         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1756         br18 = bg;
1757         br19 = fg;
1758         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1759         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1760
1761         switch (bpp) {
1762         case 8:
1763                 br13 |= COLOR_DEPTH_8;
1764                 break;
1765         case 16:
1766                 br13 |= COLOR_DEPTH_16;
1767                 break;
1768         case 32:
1769                 br13 |= COLOR_DEPTH_32;
1770                 br00 |= WRITE_ALPHA | WRITE_RGB;
1771                 break;
1772         }
1773
1774         START_RING(8 + ndwords);
1775         OUT_RING(br00);
1776         OUT_RING(br13);
1777         OUT_RING(br22);
1778         OUT_RING(br23);
1779         OUT_RING(br09);
1780         OUT_RING(br18);
1781         OUT_RING(br19);
1782         ix = iy = 0;
1783         iw = ROUND_UP_TO(w, 8) / 8;
1784         while (ndwords--) {
1785                 dat = 0;
1786                 for (j = 0; j < 2; ++j) {
1787                         for (i = 0; i < 2; ++i) {
1788                                 if (ix != iw || i == 0)
1789                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1790                         }
1791                         if (ix == iw && iy != (h-1)) {
1792                                 ix = 0;
1793                                 ++iy;
1794                         }
1795                 }
1796                 OUT_RING(dat);
1797         }
1798         if (pad)
1799                 OUT_RING(MI_NOOP);
1800         ADVANCE_RING();
1801
1802         return 1;
1803 }
1804
1805 /* HW cursor functions. */
1806 void
1807 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1808 {
1809         u32 tmp;
1810
1811 #if VERBOSE > 0
1812         DBG_MSG("intelfbhw_cursor_init\n");
1813 #endif
1814
1815         if (dinfo->mobile || IS_I9XX(dinfo)) {
1816                 if (!dinfo->cursor.physical)
1817                         return;
1818                 tmp = INREG(CURSOR_A_CONTROL);
1819                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1820                          CURSOR_MEM_TYPE_LOCAL |
1821                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1822                 tmp |= CURSOR_MODE_DISABLE;
1823                 OUTREG(CURSOR_A_CONTROL, tmp);
1824                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1825         } else {
1826                 tmp = INREG(CURSOR_CONTROL);
1827                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1828                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1829                 tmp = CURSOR_FORMAT_3C;
1830                 OUTREG(CURSOR_CONTROL, tmp);
1831                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1832                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1833                       (64 << CURSOR_SIZE_V_SHIFT);
1834                 OUTREG(CURSOR_SIZE, tmp);
1835         }
1836 }
1837
1838 void
1839 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1840 {
1841         u32 tmp;
1842
1843 #if VERBOSE > 0
1844         DBG_MSG("intelfbhw_cursor_hide\n");
1845 #endif
1846
1847         dinfo->cursor_on = 0;
1848         if (dinfo->mobile || IS_I9XX(dinfo)) {
1849                 if (!dinfo->cursor.physical)
1850                         return;
1851                 tmp = INREG(CURSOR_A_CONTROL);
1852                 tmp &= ~CURSOR_MODE_MASK;
1853                 tmp |= CURSOR_MODE_DISABLE;
1854                 OUTREG(CURSOR_A_CONTROL, tmp);
1855                 /* Flush changes */
1856                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1857         } else {
1858                 tmp = INREG(CURSOR_CONTROL);
1859                 tmp &= ~CURSOR_ENABLE;
1860                 OUTREG(CURSOR_CONTROL, tmp);
1861         }
1862 }
1863
1864 void
1865 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1866 {
1867         u32 tmp;
1868
1869 #if VERBOSE > 0
1870         DBG_MSG("intelfbhw_cursor_show\n");
1871 #endif
1872
1873         dinfo->cursor_on = 1;
1874
1875         if (dinfo->cursor_blanked)
1876                 return;
1877
1878         if (dinfo->mobile || IS_I9XX(dinfo)) {
1879                 if (!dinfo->cursor.physical)
1880                         return;
1881                 tmp = INREG(CURSOR_A_CONTROL);
1882                 tmp &= ~CURSOR_MODE_MASK;
1883                 tmp |= CURSOR_MODE_64_4C_AX;
1884                 OUTREG(CURSOR_A_CONTROL, tmp);
1885                 /* Flush changes */
1886                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1887         } else {
1888                 tmp = INREG(CURSOR_CONTROL);
1889                 tmp |= CURSOR_ENABLE;
1890                 OUTREG(CURSOR_CONTROL, tmp);
1891         }
1892 }
1893
1894 void
1895 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1896 {
1897         u32 tmp;
1898
1899 #if VERBOSE > 0
1900         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1901 #endif
1902
1903         /*
1904          * Sets the position. The coordinates are assumed to already
1905          * have any offset adjusted. Assume that the cursor is never
1906          * completely off-screen, and that x, y are always >= 0.
1907          */
1908
1909         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1910               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1911         OUTREG(CURSOR_A_POSITION, tmp);
1912
1913         if (IS_I9XX(dinfo)) {
1914                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1915         }
1916 }
1917
1918 void
1919 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1920 {
1921 #if VERBOSE > 0
1922         DBG_MSG("intelfbhw_cursor_setcolor\n");
1923 #endif
1924
1925         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1926         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1927         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1928         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1929 }
1930
1931 void
1932 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1933                       u8 *data)
1934 {
1935         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1936         int i, j, w = width / 8;
1937         int mod = width % 8, t_mask, d_mask;
1938
1939 #if VERBOSE > 0
1940         DBG_MSG("intelfbhw_cursor_load\n");
1941 #endif
1942
1943         if (!dinfo->cursor.virtual)
1944                 return;
1945
1946         t_mask = 0xff >> mod;
1947         d_mask = ~(0xff >> mod);
1948         for (i = height; i--; ) {
1949                 for (j = 0; j < w; j++) {
1950                         writeb(0x00, addr + j);
1951                         writeb(*(data++), addr + j+8);
1952                 }
1953                 if (mod) {
1954                         writeb(t_mask, addr + j);
1955                         writeb(*(data++) & d_mask, addr + j+8);
1956                 }
1957                 addr += 16;
1958         }
1959 }
1960
1961 void
1962 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1963         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1964         int i, j;
1965
1966 #if VERBOSE > 0
1967         DBG_MSG("intelfbhw_cursor_reset\n");
1968 #endif
1969
1970         if (!dinfo->cursor.virtual)
1971                 return;
1972
1973         for (i = 64; i--; ) {
1974                 for (j = 0; j < 8; j++) {
1975                         writeb(0xff, addr + j+0);
1976                         writeb(0x00, addr + j+8);
1977                 }
1978                 addr += 16;
1979         }
1980 }