1fdd1eb38fe0aa67bd317281c521358d50db60ac
[sfrench/cifs-2.6.git] / drivers / video / fbdev / mxsfb.c
1 /*
2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
3  *
4  * This code is based on:
5  * Author: Vitaly Wool <vital@embeddedalley.com>
6  *
7  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  */
19
20 #define DRIVER_NAME "mxsfb"
21
22 /**
23  * @file
24  * @brief LCDIF driver for i.MX23 and i.MX28
25  *
26  * The LCDIF support four modes of operation
27  * - MPU interface (to drive smart displays) -> not supported yet
28  * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
29  * - Dotclock interface (to drive LC displays with RGB data and sync signals)
30  * - DVI (to drive ITU-R BT656)  -> not supported yet
31  *
32  * This driver depends on a correct setup of the pins used for this purpose
33  * (platform specific).
34  *
35  * For the developer: Don't forget to set the data bus width to the display
36  * in the imx_fb_videomode structure. You will else end up with ugly colours.
37  * If you fight against jitter you can vary the clock delay. This is a feature
38  * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
39  * the required value in the imx_fb_videomode structure.
40  */
41
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/of_device.h>
45 #include <linux/platform_device.h>
46 #include <linux/clk.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/io.h>
49 #include <linux/fb.h>
50 #include <linux/regulator/consumer.h>
51 #include <video/of_display_timing.h>
52 #include <video/of_videomode.h>
53 #include <video/videomode.h>
54
55 #define REG_SET 4
56 #define REG_CLR 8
57
58 #define LCDC_CTRL                       0x00
59 #define LCDC_CTRL1                      0x10
60 #define LCDC_V4_CTRL2                   0x20
61 #define LCDC_V3_TRANSFER_COUNT          0x20
62 #define LCDC_V4_TRANSFER_COUNT          0x30
63 #define LCDC_V4_CUR_BUF                 0x40
64 #define LCDC_V4_NEXT_BUF                0x50
65 #define LCDC_V3_CUR_BUF                 0x30
66 #define LCDC_V3_NEXT_BUF                0x40
67 #define LCDC_TIMING                     0x60
68 #define LCDC_VDCTRL0                    0x70
69 #define LCDC_VDCTRL1                    0x80
70 #define LCDC_VDCTRL2                    0x90
71 #define LCDC_VDCTRL3                    0xa0
72 #define LCDC_VDCTRL4                    0xb0
73 #define LCDC_DVICTRL0                   0xc0
74 #define LCDC_DVICTRL1                   0xd0
75 #define LCDC_DVICTRL2                   0xe0
76 #define LCDC_DVICTRL3                   0xf0
77 #define LCDC_DVICTRL4                   0x100
78 #define LCDC_V4_DATA                    0x180
79 #define LCDC_V3_DATA                    0x1b0
80 #define LCDC_V4_DEBUG0                  0x1d0
81 #define LCDC_V3_DEBUG0                  0x1f0
82
83 #define CTRL_SFTRST                     (1 << 31)
84 #define CTRL_CLKGATE                    (1 << 30)
85 #define CTRL_BYPASS_COUNT               (1 << 19)
86 #define CTRL_VSYNC_MODE                 (1 << 18)
87 #define CTRL_DOTCLK_MODE                (1 << 17)
88 #define CTRL_DATA_SELECT                (1 << 16)
89 #define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
90 #define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
91 #define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
92 #define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
93 #define CTRL_MASTER                     (1 << 5)
94 #define CTRL_DF16                       (1 << 3)
95 #define CTRL_DF18                       (1 << 2)
96 #define CTRL_DF24                       (1 << 1)
97 #define CTRL_RUN                        (1 << 0)
98
99 #define CTRL1_FIFO_CLEAR                (1 << 21)
100 #define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
101 #define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
102
103 #define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
104 #define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
105 #define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
106 #define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
107
108
109 #define VDCTRL0_ENABLE_PRESENT          (1 << 28)
110 #define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
111 #define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
112 #define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
113 #define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
114 #define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
115 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
116 #define VDCTRL0_HALF_LINE               (1 << 19)
117 #define VDCTRL0_HALF_LINE_MODE          (1 << 18)
118 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
119 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
120
121 #define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
122 #define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
123
124 #define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
125 #define VDCTRL3_VSYNC_ONLY              (1 << 28)
126 #define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
127 #define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
128 #define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
129 #define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
130
131 #define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
132 #define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
133 #define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
134 #define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
135
136 #define DEBUG0_HSYNC                    (1 < 26)
137 #define DEBUG0_VSYNC                    (1 < 25)
138
139 #define MIN_XRES                        120
140 #define MIN_YRES                        120
141
142 #define RED 0
143 #define GREEN 1
144 #define BLUE 2
145 #define TRANSP 3
146
147 #define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
148 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
149 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
150 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
151
152 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
153 #define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negative edge sampling */
154
155 enum mxsfb_devtype {
156         MXSFB_V3,
157         MXSFB_V4,
158 };
159
160 /* CPU dependent register offsets */
161 struct mxsfb_devdata {
162         unsigned transfer_count;
163         unsigned cur_buf;
164         unsigned next_buf;
165         unsigned debug0;
166         unsigned hs_wdth_mask;
167         unsigned hs_wdth_shift;
168         unsigned ipversion;
169 };
170
171 struct mxsfb_info {
172         struct platform_device *pdev;
173         struct clk *clk;
174         struct clk *clk_axi;
175         struct clk *clk_disp_axi;
176         void __iomem *base;     /* registers */
177         unsigned allocated_size;
178         int enabled;
179         unsigned ld_intf_width;
180         unsigned dotclk_delay;
181         const struct mxsfb_devdata *devdata;
182         u32 sync;
183         struct regulator *reg_lcd;
184         int pre_init;
185 };
186
187 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
188 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
189
190 static const struct mxsfb_devdata mxsfb_devdata[] = {
191         [MXSFB_V3] = {
192                 .transfer_count = LCDC_V3_TRANSFER_COUNT,
193                 .cur_buf = LCDC_V3_CUR_BUF,
194                 .next_buf = LCDC_V3_NEXT_BUF,
195                 .debug0 = LCDC_V3_DEBUG0,
196                 .hs_wdth_mask = 0xff,
197                 .hs_wdth_shift = 24,
198                 .ipversion = 3,
199         },
200         [MXSFB_V4] = {
201                 .transfer_count = LCDC_V4_TRANSFER_COUNT,
202                 .cur_buf = LCDC_V4_CUR_BUF,
203                 .next_buf = LCDC_V4_NEXT_BUF,
204                 .debug0 = LCDC_V4_DEBUG0,
205                 .hs_wdth_mask = 0x3fff,
206                 .hs_wdth_shift = 18,
207                 .ipversion = 4,
208         },
209 };
210
211 /* mask and shift depends on architecture */
212 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
213 {
214         return (val & host->devdata->hs_wdth_mask) <<
215                 host->devdata->hs_wdth_shift;
216 }
217
218 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
219 {
220         return (val >> host->devdata->hs_wdth_shift) &
221                 host->devdata->hs_wdth_mask;
222 }
223
224 static const struct fb_bitfield def_rgb565[] = {
225         [RED] = {
226                 .offset = 11,
227                 .length = 5,
228         },
229         [GREEN] = {
230                 .offset = 5,
231                 .length = 6,
232         },
233         [BLUE] = {
234                 .offset = 0,
235                 .length = 5,
236         },
237         [TRANSP] = {    /* no support for transparency */
238                 .length = 0,
239         }
240 };
241
242 static const struct fb_bitfield def_rgb888[] = {
243         [RED] = {
244                 .offset = 16,
245                 .length = 8,
246         },
247         [GREEN] = {
248                 .offset = 8,
249                 .length = 8,
250         },
251         [BLUE] = {
252                 .offset = 0,
253                 .length = 8,
254         },
255         [TRANSP] = {    /* no support for transparency */
256                 .length = 0,
257         }
258 };
259
260 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
261 {
262         chan &= 0xffff;
263         chan >>= 16 - bf->length;
264         return chan << bf->offset;
265 }
266
267 static int mxsfb_check_var(struct fb_var_screeninfo *var,
268                 struct fb_info *fb_info)
269 {
270         struct mxsfb_info *host = fb_info->par;
271         const struct fb_bitfield *rgb = NULL;
272
273         if (var->xres < MIN_XRES)
274                 var->xres = MIN_XRES;
275         if (var->yres < MIN_YRES)
276                 var->yres = MIN_YRES;
277
278         var->xres_virtual = var->xres;
279
280         var->yres_virtual = var->yres;
281
282         switch (var->bits_per_pixel) {
283         case 16:
284                 /* always expect RGB 565 */
285                 rgb = def_rgb565;
286                 break;
287         case 32:
288                 switch (host->ld_intf_width) {
289                 case STMLCDIF_8BIT:
290                         pr_debug("Unsupported LCD bus width mapping\n");
291                         break;
292                 case STMLCDIF_16BIT:
293                 case STMLCDIF_18BIT:
294                 case STMLCDIF_24BIT:
295                         /* real 24 bit */
296                         rgb = def_rgb888;
297                         break;
298                 }
299                 break;
300         default:
301                 pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel);
302                 return -EINVAL;
303         }
304
305         /*
306          * Copy the RGB parameters for this display
307          * from the machine specific parameters.
308          */
309         var->red    = rgb[RED];
310         var->green  = rgb[GREEN];
311         var->blue   = rgb[BLUE];
312         var->transp = rgb[TRANSP];
313
314         return 0;
315 }
316
317 static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
318 {
319         if (host->clk_axi)
320                 clk_prepare_enable(host->clk_axi);
321 }
322
323 static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
324 {
325         if (host->clk_axi)
326                 clk_disable_unprepare(host->clk_axi);
327 }
328
329 static void mxsfb_enable_controller(struct fb_info *fb_info)
330 {
331         struct mxsfb_info *host = fb_info->par;
332         u32 reg;
333         int ret;
334
335         dev_dbg(&host->pdev->dev, "%s\n", __func__);
336
337         if (host->reg_lcd) {
338                 ret = regulator_enable(host->reg_lcd);
339                 if (ret) {
340                         dev_err(&host->pdev->dev,
341                                 "lcd regulator enable failed:   %d\n", ret);
342                         return;
343                 }
344         }
345
346         if (host->clk_disp_axi)
347                 clk_prepare_enable(host->clk_disp_axi);
348         clk_prepare_enable(host->clk);
349         clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
350
351         mxsfb_enable_axi_clk(host);
352
353         /* if it was disabled, re-enable the mode again */
354         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
355
356         /* enable the SYNC signals first, then the DMA engine */
357         reg = readl(host->base + LCDC_VDCTRL4);
358         reg |= VDCTRL4_SYNC_SIGNALS_ON;
359         writel(reg, host->base + LCDC_VDCTRL4);
360
361         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
362
363         host->enabled = 1;
364 }
365
366 static void mxsfb_disable_controller(struct fb_info *fb_info)
367 {
368         struct mxsfb_info *host = fb_info->par;
369         unsigned loop;
370         u32 reg;
371         int ret;
372
373         dev_dbg(&host->pdev->dev, "%s\n", __func__);
374
375         /*
376          * Even if we disable the controller here, it will still continue
377          * until its FIFOs are running out of data
378          */
379         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
380
381         loop = 1000;
382         while (loop) {
383                 reg = readl(host->base + LCDC_CTRL);
384                 if (!(reg & CTRL_RUN))
385                         break;
386                 loop--;
387         }
388
389         reg = readl(host->base + LCDC_VDCTRL4);
390         writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
391
392         mxsfb_disable_axi_clk(host);
393
394         clk_disable_unprepare(host->clk);
395         if (host->clk_disp_axi)
396                 clk_disable_unprepare(host->clk_disp_axi);
397
398         host->enabled = 0;
399
400         if (host->reg_lcd) {
401                 ret = regulator_disable(host->reg_lcd);
402                 if (ret)
403                         dev_err(&host->pdev->dev,
404                                 "lcd regulator disable failed: %d\n", ret);
405         }
406 }
407
408 static int mxsfb_set_par(struct fb_info *fb_info)
409 {
410         struct mxsfb_info *host = fb_info->par;
411         u32 ctrl, vdctrl0, vdctrl4;
412         int line_size, fb_size;
413         int reenable = 0;
414
415         line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
416         fb_size = fb_info->var.yres_virtual * line_size;
417
418         if (fb_size > fb_info->fix.smem_len)
419                 return -ENOMEM;
420
421         fb_info->fix.line_length = line_size;
422
423         if (host->pre_init) {
424                 mxsfb_enable_controller(fb_info);
425                 host->pre_init = 0;
426                 return 0;
427         }
428
429         /*
430          * It seems, you can't re-program the controller if it is still running.
431          * This may lead into shifted pictures (FIFO issue?).
432          * So, first stop the controller and drain its FIFOs
433          */
434         if (host->enabled) {
435                 reenable = 1;
436                 mxsfb_disable_controller(fb_info);
437         }
438
439         mxsfb_enable_axi_clk(host);
440
441         /* clear the FIFOs */
442         writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
443
444         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
445                 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
446
447         switch (fb_info->var.bits_per_pixel) {
448         case 16:
449                 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
450                 ctrl |= CTRL_SET_WORD_LENGTH(0);
451                 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
452                 break;
453         case 32:
454                 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
455                 ctrl |= CTRL_SET_WORD_LENGTH(3);
456                 switch (host->ld_intf_width) {
457                 case STMLCDIF_8BIT:
458                         mxsfb_disable_axi_clk(host);
459                         dev_err(&host->pdev->dev,
460                                         "Unsupported LCD bus width mapping\n");
461                         return -EINVAL;
462                 case STMLCDIF_16BIT:
463                 case STMLCDIF_18BIT:
464                 case STMLCDIF_24BIT:
465                         /* real 24 bit */
466                         break;
467                 }
468                 /* do not use packed pixels = one pixel per word instead */
469                 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
470                 break;
471         default:
472                 mxsfb_disable_axi_clk(host);
473                 dev_err(&host->pdev->dev, "Unhandled color depth of %u\n",
474                                 fb_info->var.bits_per_pixel);
475                 return -EINVAL;
476         }
477
478         writel(ctrl, host->base + LCDC_CTRL);
479
480         writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
481                         TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
482                         host->base + host->devdata->transfer_count);
483
484         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
485                 VDCTRL0_VSYNC_PERIOD_UNIT |
486                 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
487                 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
488         if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
489                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
490         if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
491                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
492         if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
493                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
494         if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
495                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
496
497         writel(vdctrl0, host->base + LCDC_VDCTRL0);
498
499         /* frame length in lines */
500         writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
501                 fb_info->var.lower_margin + fb_info->var.yres,
502                 host->base + LCDC_VDCTRL1);
503
504         /* line length in units of clocks or pixels */
505         writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
506                 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
507                 fb_info->var.hsync_len + fb_info->var.right_margin +
508                 fb_info->var.xres),
509                 host->base + LCDC_VDCTRL2);
510
511         writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
512                 fb_info->var.hsync_len) |
513                 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
514                         fb_info->var.vsync_len),
515                 host->base + LCDC_VDCTRL3);
516
517         vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
518         if (mxsfb_is_v4(host))
519                 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
520         writel(vdctrl4, host->base + LCDC_VDCTRL4);
521
522         writel(fb_info->fix.smem_start +
523                         fb_info->fix.line_length * fb_info->var.yoffset,
524                         host->base + host->devdata->next_buf);
525
526         mxsfb_disable_axi_clk(host);
527
528         if (reenable)
529                 mxsfb_enable_controller(fb_info);
530
531         return 0;
532 }
533
534 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
535                 u_int transp, struct fb_info *fb_info)
536 {
537         unsigned int val;
538         int ret = -EINVAL;
539
540         /*
541          * If greyscale is true, then we convert the RGB value
542          * to greyscale no matter what visual we are using.
543          */
544         if (fb_info->var.grayscale)
545                 red = green = blue = (19595 * red + 38470 * green +
546                                         7471 * blue) >> 16;
547
548         switch (fb_info->fix.visual) {
549         case FB_VISUAL_TRUECOLOR:
550                 /*
551                  * 12 or 16-bit True Colour.  We encode the RGB value
552                  * according to the RGB bitfield information.
553                  */
554                 if (regno < 16) {
555                         u32 *pal = fb_info->pseudo_palette;
556
557                         val  = chan_to_field(red, &fb_info->var.red);
558                         val |= chan_to_field(green, &fb_info->var.green);
559                         val |= chan_to_field(blue, &fb_info->var.blue);
560
561                         pal[regno] = val;
562                         ret = 0;
563                 }
564                 break;
565
566         case FB_VISUAL_STATIC_PSEUDOCOLOR:
567         case FB_VISUAL_PSEUDOCOLOR:
568                 break;
569         }
570
571         return ret;
572 }
573
574 static int mxsfb_blank(int blank, struct fb_info *fb_info)
575 {
576         struct mxsfb_info *host = fb_info->par;
577
578         switch (blank) {
579         case FB_BLANK_POWERDOWN:
580         case FB_BLANK_VSYNC_SUSPEND:
581         case FB_BLANK_HSYNC_SUSPEND:
582         case FB_BLANK_NORMAL:
583                 if (host->enabled)
584                         mxsfb_disable_controller(fb_info);
585                 break;
586
587         case FB_BLANK_UNBLANK:
588                 if (!host->enabled)
589                         mxsfb_enable_controller(fb_info);
590                 break;
591         }
592         return 0;
593 }
594
595 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
596                 struct fb_info *fb_info)
597 {
598         struct mxsfb_info *host = fb_info->par;
599         unsigned offset;
600
601         if (var->xoffset != 0)
602                 return -EINVAL;
603
604         offset = fb_info->fix.line_length * var->yoffset;
605
606         mxsfb_enable_axi_clk(host);
607
608         /* update on next VSYNC */
609         writel(fb_info->fix.smem_start + offset,
610                         host->base + host->devdata->next_buf);
611
612         mxsfb_disable_axi_clk(host);
613
614         return 0;
615 }
616
617 static struct fb_ops mxsfb_ops = {
618         .owner = THIS_MODULE,
619         .fb_check_var = mxsfb_check_var,
620         .fb_set_par = mxsfb_set_par,
621         .fb_setcolreg = mxsfb_setcolreg,
622         .fb_blank = mxsfb_blank,
623         .fb_pan_display = mxsfb_pan_display,
624         .fb_fillrect = cfb_fillrect,
625         .fb_copyarea = cfb_copyarea,
626         .fb_imageblit = cfb_imageblit,
627 };
628
629 static int mxsfb_restore_mode(struct fb_info *fb_info,
630                         struct fb_videomode *vmode)
631 {
632         struct mxsfb_info *host = fb_info->par;
633         unsigned period;
634         unsigned long pa, fbsize;
635         int bits_per_pixel, ofs, ret = 0;
636         u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
637
638         mxsfb_enable_axi_clk(host);
639
640         /* Only restore the mode when the controller is running */
641         ctrl = readl(host->base + LCDC_CTRL);
642         if (!(ctrl & CTRL_RUN)) {
643                 ret = -EINVAL;
644                 goto err;
645         }
646
647         vdctrl0 = readl(host->base + LCDC_VDCTRL0);
648         vdctrl2 = readl(host->base + LCDC_VDCTRL2);
649         vdctrl3 = readl(host->base + LCDC_VDCTRL3);
650         vdctrl4 = readl(host->base + LCDC_VDCTRL4);
651
652         transfer_count = readl(host->base + host->devdata->transfer_count);
653
654         vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
655         vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
656
657         switch (CTRL_GET_WORD_LENGTH(ctrl)) {
658         case 0:
659                 bits_per_pixel = 16;
660                 break;
661         case 3:
662                 bits_per_pixel = 32;
663                 break;
664         case 1:
665         default:
666                 ret = -EINVAL;
667                 goto err;
668         }
669
670         fb_info->var.bits_per_pixel = bits_per_pixel;
671
672         vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
673         vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2);
674         vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len;
675         vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) -
676                 vmode->hsync_len - vmode->left_margin - vmode->xres;
677         vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
678         period = readl(host->base + LCDC_VDCTRL1);
679         vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len;
680         vmode->lower_margin = period - vmode->vsync_len -
681                 vmode->upper_margin - vmode->yres;
682
683         vmode->vmode = FB_VMODE_NONINTERLACED;
684
685         vmode->sync = 0;
686         if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
687                 vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
688         if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
689                 vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
690
691         pr_debug("Reconstructed video mode:\n");
692         pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
693                 vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin,
694                 vmode->right_margin, vmode->vsync_len, vmode->upper_margin,
695                 vmode->lower_margin);
696         pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock));
697
698         host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
699         host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
700
701         fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3);
702
703         pa = readl(host->base + host->devdata->cur_buf);
704         fbsize = fb_info->fix.line_length * vmode->yres;
705         if (pa < fb_info->fix.smem_start) {
706                 ret = -EINVAL;
707                 goto err;
708         }
709         if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) {
710                 ret = -EINVAL;
711                 goto err;
712         }
713         ofs = pa - fb_info->fix.smem_start;
714         if (ofs) {
715                 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
716                 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
717         }
718
719         fb_info->fix.ypanstep = 1;
720
721         clk_prepare_enable(host->clk);
722         host->enabled = 1;
723
724 err:
725         if (ret)
726                 mxsfb_disable_axi_clk(host);
727
728         return ret;
729 }
730
731 static int mxsfb_init_fbinfo_dt(struct fb_info *fb_info,
732                                 struct fb_videomode *vmode)
733 {
734         struct mxsfb_info *host = fb_info->par;
735         struct fb_var_screeninfo *var = &fb_info->var;
736         struct device *dev = &host->pdev->dev;
737         struct device_node *np = host->pdev->dev.of_node;
738         struct device_node *display_np;
739         struct videomode vm;
740         u32 width;
741         int ret;
742
743         display_np = of_parse_phandle(np, "display", 0);
744         if (!display_np) {
745                 dev_err(dev, "failed to find display phandle\n");
746                 return -ENOENT;
747         }
748
749         ret = of_property_read_u32(display_np, "bus-width", &width);
750         if (ret < 0) {
751                 dev_err(dev, "failed to get property bus-width\n");
752                 goto put_display_node;
753         }
754
755         switch (width) {
756         case 8:
757                 host->ld_intf_width = STMLCDIF_8BIT;
758                 break;
759         case 16:
760                 host->ld_intf_width = STMLCDIF_16BIT;
761                 break;
762         case 18:
763                 host->ld_intf_width = STMLCDIF_18BIT;
764                 break;
765         case 24:
766                 host->ld_intf_width = STMLCDIF_24BIT;
767                 break;
768         default:
769                 dev_err(dev, "invalid bus-width value\n");
770                 ret = -EINVAL;
771                 goto put_display_node;
772         }
773
774         ret = of_property_read_u32(display_np, "bits-per-pixel",
775                                    &var->bits_per_pixel);
776         if (ret < 0) {
777                 dev_err(dev, "failed to get property bits-per-pixel\n");
778                 goto put_display_node;
779         }
780
781         ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
782         if (ret) {
783                 dev_err(dev, "failed to get videomode from DT\n");
784                 goto put_display_node;
785         }
786
787         ret = fb_videomode_from_videomode(&vm, vmode);
788         if (ret < 0)
789                 goto put_display_node;
790
791         if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
792                 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
793
794         /*
795          * The PIXDATA flags of the display_flags enum are controller
796          * centric, e.g. NEGEDGE means drive data on negative edge.
797          * However, the drivers flag is display centric: Sample the
798          * data on negative (falling) edge. Therefore, check for the
799          * POSEDGE flag:
800          * drive on positive edge => sample on negative edge
801          */
802         if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
803                 host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
804
805 put_display_node:
806         of_node_put(display_np);
807         return ret;
808 }
809
810 static int mxsfb_init_fbinfo(struct fb_info *fb_info,
811                         struct fb_videomode *vmode)
812 {
813         int ret;
814         struct mxsfb_info *host = fb_info->par;
815         struct device *dev = &host->pdev->dev;
816         struct fb_var_screeninfo *var = &fb_info->var;
817         dma_addr_t fb_phys;
818         void *fb_virt;
819         unsigned fb_size;
820
821         fb_info->fbops = &mxsfb_ops;
822         fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
823         strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
824         fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
825         fb_info->fix.ypanstep = 1;
826         fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
827         fb_info->fix.accel = FB_ACCEL_NONE;
828
829         ret = mxsfb_init_fbinfo_dt(fb_info, vmode);
830         if (ret)
831                 return ret;
832
833         var->nonstd = 0;
834         var->activate = FB_ACTIVATE_NOW;
835         var->accel_flags = 0;
836         var->vmode = FB_VMODE_NONINTERLACED;
837
838         /* Memory allocation for framebuffer */
839         fb_size = SZ_2M;
840         fb_virt = dma_alloc_wc(dev, PAGE_ALIGN(fb_size), &fb_phys, GFP_KERNEL);
841         if (!fb_virt)
842                 return -ENOMEM;
843
844         fb_info->fix.smem_start = fb_phys;
845         fb_info->screen_base = fb_virt;
846         fb_info->screen_size = fb_info->fix.smem_len = fb_size;
847
848         if (mxsfb_restore_mode(fb_info, vmode))
849                 memset(fb_virt, 0, fb_size);
850
851         return 0;
852 }
853
854 static void mxsfb_free_videomem(struct fb_info *fb_info)
855 {
856         struct mxsfb_info *host = fb_info->par;
857         struct device *dev = &host->pdev->dev;
858
859         dma_free_wc(dev, fb_info->screen_size, fb_info->screen_base,
860                     fb_info->fix.smem_start);
861 }
862
863 static const struct platform_device_id mxsfb_devtype[] = {
864         {
865                 .name = "imx23-fb",
866                 .driver_data = MXSFB_V3,
867         }, {
868                 .name = "imx28-fb",
869                 .driver_data = MXSFB_V4,
870         }, {
871                 /* sentinel */
872         }
873 };
874 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
875
876 static const struct of_device_id mxsfb_dt_ids[] = {
877         { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
878         { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
879         { /* sentinel */ }
880 };
881 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
882
883 static int mxsfb_probe(struct platform_device *pdev)
884 {
885         const struct of_device_id *of_id =
886                         of_match_device(mxsfb_dt_ids, &pdev->dev);
887         struct resource *res;
888         struct mxsfb_info *host;
889         struct fb_info *fb_info;
890         struct fb_videomode *mode;
891         int ret;
892
893         if (of_id)
894                 pdev->id_entry = of_id->data;
895
896         fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
897         if (!fb_info) {
898                 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
899                 return -ENOMEM;
900         }
901
902         mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode),
903                         GFP_KERNEL);
904         if (mode == NULL)
905                 return -ENOMEM;
906
907         host = fb_info->par;
908
909         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910         host->base = devm_ioremap_resource(&pdev->dev, res);
911         if (IS_ERR(host->base)) {
912                 ret = PTR_ERR(host->base);
913                 goto fb_release;
914         }
915
916         host->pdev = pdev;
917         platform_set_drvdata(pdev, host);
918
919         host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
920
921         host->clk = devm_clk_get(&host->pdev->dev, NULL);
922         if (IS_ERR(host->clk)) {
923                 ret = PTR_ERR(host->clk);
924                 goto fb_release;
925         }
926
927         host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
928         if (IS_ERR(host->clk_axi))
929                 host->clk_axi = NULL;
930
931         host->clk_disp_axi = devm_clk_get(&host->pdev->dev, "disp_axi");
932         if (IS_ERR(host->clk_disp_axi))
933                 host->clk_disp_axi = NULL;
934
935         host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
936         if (IS_ERR(host->reg_lcd))
937                 host->reg_lcd = NULL;
938
939 #if defined(CONFIG_FB_PRE_INIT_FB)
940         host->pre_init = 1;
941 #endif
942
943         fb_info->pseudo_palette = devm_kcalloc(&pdev->dev, 16, sizeof(u32),
944                                                GFP_KERNEL);
945         if (!fb_info->pseudo_palette) {
946                 ret = -ENOMEM;
947                 goto fb_release;
948         }
949
950         ret = mxsfb_init_fbinfo(fb_info, mode);
951         if (ret != 0)
952                 goto fb_release;
953
954         fb_videomode_to_var(&fb_info->var, mode);
955
956         /* init the color fields */
957         mxsfb_check_var(&fb_info->var, fb_info);
958
959         platform_set_drvdata(pdev, fb_info);
960
961         ret = register_framebuffer(fb_info);
962         if (ret != 0) {
963                 dev_err(&pdev->dev,"Failed to register framebuffer\n");
964                 goto fb_destroy;
965         }
966
967         if (!host->enabled) {
968                 mxsfb_enable_axi_clk(host);
969                 writel(0, host->base + LCDC_CTRL);
970                 mxsfb_disable_axi_clk(host);
971                 mxsfb_set_par(fb_info);
972                 mxsfb_enable_controller(fb_info);
973         }
974
975         host->pre_init = 0;
976         dev_info(&pdev->dev, "initialized\n");
977
978         return 0;
979
980 fb_destroy:
981         if (host->enabled)
982                 clk_disable_unprepare(host->clk);
983 fb_release:
984         framebuffer_release(fb_info);
985
986         return ret;
987 }
988
989 static int mxsfb_remove(struct platform_device *pdev)
990 {
991         struct fb_info *fb_info = platform_get_drvdata(pdev);
992         struct mxsfb_info *host = fb_info->par;
993
994         if (host->enabled)
995                 mxsfb_disable_controller(fb_info);
996
997         unregister_framebuffer(fb_info);
998         mxsfb_free_videomem(fb_info);
999
1000         framebuffer_release(fb_info);
1001
1002         return 0;
1003 }
1004
1005 static void mxsfb_shutdown(struct platform_device *pdev)
1006 {
1007         struct fb_info *fb_info = platform_get_drvdata(pdev);
1008         struct mxsfb_info *host = fb_info->par;
1009
1010         mxsfb_enable_axi_clk(host);
1011
1012         /*
1013          * Force stop the LCD controller as keeping it running during reboot
1014          * might interfere with the BootROM's boot mode pads sampling.
1015          */
1016         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
1017
1018         mxsfb_disable_axi_clk(host);
1019 }
1020
1021 static struct platform_driver mxsfb_driver = {
1022         .probe = mxsfb_probe,
1023         .remove = mxsfb_remove,
1024         .shutdown = mxsfb_shutdown,
1025         .id_table = mxsfb_devtype,
1026         .driver = {
1027                    .name = DRIVER_NAME,
1028                    .of_match_table = mxsfb_dt_ids,
1029         },
1030 };
1031
1032 module_platform_driver(mxsfb_driver);
1033
1034 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1035 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1036 MODULE_LICENSE("GPL");