drivers/video/fbdev/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/wait.h>
  32 #include <linux/clk.h>
  33 #include <linux/cpufreq.h>
  34 #include <linux/console.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38 #include <linux/lcm.h>
  39 #include <video/da8xx-fb.h>
  40 #include <asm/div64.h>
  41
  42 #define DRIVER_NAME "da8xx_lcdc"
  43
  44 #define LCD_VERSION_1   1
  45 #define LCD_VERSION_2   2
  46
  47 /* LCD Status Register */
  48 #define LCD_END_OF_FRAME1               BIT(9)
  49 #define LCD_END_OF_FRAME0               BIT(8)
  50 #define LCD_PL_LOAD_DONE                BIT(6)
  51 #define LCD_FIFO_UNDERFLOW              BIT(5)
  52 #define LCD_SYNC_LOST                   BIT(2)
  53 #define LCD_FRAME_DONE                  BIT(0)
  54
  55 /* LCD DMA Control Register */
  56 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  57 #define LCD_DMA_BURST_1                 0x0
  58 #define LCD_DMA_BURST_2                 0x1
  59 #define LCD_DMA_BURST_4                 0x2
  60 #define LCD_DMA_BURST_8                 0x3
  61 #define LCD_DMA_BURST_16                0x4
  62 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  63 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  64 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  65 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  66
  67 /* LCD Control Register */
  68 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  69 #define LCD_RASTER_MODE                 0x01
  70
  71 /* LCD Raster Control Register */
  72 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  73 #define PALETTE_AND_DATA                0x00
  74 #define PALETTE_ONLY                    0x01
  75 #define DATA_ONLY                       0x02
  76
  77 #define LCD_MONO_8BIT_MODE              BIT(9)
  78 #define LCD_RASTER_ORDER                BIT(8)
  79 #define LCD_TFT_MODE                    BIT(7)
  80 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  81 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  82 #define LCD_V1_PL_INT_ENA               BIT(4)
  83 #define LCD_V2_PL_INT_ENA               BIT(6)
  84 #define LCD_MONOCHROME_MODE             BIT(1)
  85 #define LCD_RASTER_ENABLE               BIT(0)
  86 #define LCD_TFT_ALT_ENABLE              BIT(23)
  87 #define LCD_STN_565_ENABLE              BIT(24)
  88 #define LCD_V2_DMA_CLK_EN               BIT(2)
  89 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  90 #define LCD_V2_CORE_CLK_EN              BIT(0)
  91 #define LCD_V2_LPP_B10                  26
  92 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
  93 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
  94
  95 /* LCD Raster Timing 2 Register */
  96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  97 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  98 #define LCD_SYNC_CTRL                           BIT(25)
  99 #define LCD_SYNC_EDGE                           BIT(24)
 100 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
 101 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
 102 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
 103
 104 /* LCD Block */
 105 #define  LCD_PID_REG                            0x0
 106 #define  LCD_CTRL_REG                           0x4
 107 #define  LCD_STAT_REG                           0x8
 108 #define  LCD_RASTER_CTRL_REG                    0x28
 109 #define  LCD_RASTER_TIMING_0_REG                0x2C
 110 #define  LCD_RASTER_TIMING_1_REG                0x30
 111 #define  LCD_RASTER_TIMING_2_REG                0x34
 112 #define  LCD_DMA_CTRL_REG                       0x40
 113 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
 114 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
 115 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
 116 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
 117
 118 /* Interrupt Registers available only in Version 2 */
 119 #define  LCD_RAW_STAT_REG                       0x58
 120 #define  LCD_MASKED_STAT_REG                    0x5c
 121 #define  LCD_INT_ENABLE_SET_REG                 0x60
 122 #define  LCD_INT_ENABLE_CLR_REG                 0x64
 123 #define  LCD_END_OF_INT_IND_REG                 0x68
 124
 125 /* Clock registers available only on Version 2 */
 126 #define  LCD_CLK_ENABLE_REG                     0x6c
 127 #define  LCD_CLK_RESET_REG                      0x70
 128 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 129
 130 #define LCD_NUM_BUFFERS 2
 131
 132 #define PALETTE_SIZE    256
 133
 134 #define CLK_MIN_DIV     2
 135 #define CLK_MAX_DIV     255
 136
 137 static void __iomem *da8xx_fb_reg_base;
 138 static unsigned int lcd_revision;
 139 static irq_handler_t lcdc_irq_handler;
 140 static wait_queue_head_t frame_done_wq;
 141 static int frame_done_flag;
 142
 143 static unsigned int lcdc_read(unsigned int addr)
 144 {
 145         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 146 }
 147
 148 static void lcdc_write(unsigned int val, unsigned int addr)
 149 {
 150         __raw_writel(val, da8xx_fb_reg_base + (addr));
 151 }
 152
 153 struct da8xx_fb_par {
 154         struct device           *dev;
 155         dma_addr_t              p_palette_base;
 156         unsigned char *v_palette_base;
 157         dma_addr_t              vram_phys;
 158         unsigned long           vram_size;
 159         void                    *vram_virt;
 160         unsigned int            dma_start;
 161         unsigned int            dma_end;
 162         struct clk *lcdc_clk;
 163         int irq;
 164         unsigned int palette_sz;
 165         int blank;
 166         wait_queue_head_t       vsync_wait;
 167         int                     vsync_flag;
 168         int                     vsync_timeout;
 169         spinlock_t              lock_for_chan_update;
 170
 171         /*
 172          * LCDC has 2 ping pong DMA channels, channel 0
 173          * and channel 1.
 174          */
 175         unsigned int            which_dma_channel_done;
 176 #ifdef CONFIG_CPU_FREQ
 177         struct notifier_block   freq_transition;
 178 #endif
 179         unsigned int            lcdc_clk_rate;
 180         void (*panel_power_ctrl)(int);
 181         u32 pseudo_palette[16];
 182         struct fb_videomode     mode;
 183         struct lcd_ctrl_config  cfg;
 184 };
 185
 186 static struct fb_var_screeninfo da8xx_fb_var;
 187
 188 static struct fb_fix_screeninfo da8xx_fb_fix = {
 189         .id = "DA8xx FB Drv",
 190         .type = FB_TYPE_PACKED_PIXELS,
 191         .type_aux = 0,
 192         .visual = FB_VISUAL_PSEUDOCOLOR,
 193         .xpanstep = 0,
 194         .ypanstep = 1,
 195         .ywrapstep = 0,
 196         .accel = FB_ACCEL_NONE
 197 };
 198
 199 static struct fb_videomode known_lcd_panels[] = {
 200         /* Sharp LCD035Q3DG01 */
 201         [0] = {
 202                 .name           = "Sharp_LCD035Q3DG01",
 203                 .xres           = 320,
 204                 .yres           = 240,
 205                 .pixclock       = KHZ2PICOS(4607),
 206                 .left_margin    = 6,
 207                 .right_margin   = 8,
 208                 .upper_margin   = 2,
 209                 .lower_margin   = 2,
 210                 .hsync_len      = 0,
 211                 .vsync_len      = 0,
 212                 .sync           = FB_SYNC_CLK_INVERT,
 213         },
 214         /* Sharp LK043T1DG01 */
 215         [1] = {
 216                 .name           = "Sharp_LK043T1DG01",
 217                 .xres           = 480,
 218                 .yres           = 272,
 219                 .pixclock       = KHZ2PICOS(7833),
 220                 .left_margin    = 2,
 221                 .right_margin   = 2,
 222                 .upper_margin   = 2,
 223                 .lower_margin   = 2,
 224                 .hsync_len      = 41,
 225                 .vsync_len      = 10,
 226                 .sync           = 0,
 227                 .flag           = 0,
 228         },
 229         [2] = {
 230                 /* Hitachi SP10Q010 */
 231                 .name           = "SP10Q010",
 232                 .xres           = 320,
 233                 .yres           = 240,
 234                 .pixclock       = KHZ2PICOS(7833),
 235                 .left_margin    = 10,
 236                 .right_margin   = 10,
 237                 .upper_margin   = 10,
 238                 .lower_margin   = 10,
 239                 .hsync_len      = 10,
 240                 .vsync_len      = 10,
 241                 .sync           = 0,
 242                 .flag           = 0,
 243         },
 244         [3] = {
 245                 /* Densitron 84-0023-001T */
 246                 .name           = "Densitron_84-0023-001T",
 247                 .xres           = 320,
 248                 .yres           = 240,
 249                 .pixclock       = KHZ2PICOS(6400),
 250                 .left_margin    = 0,
 251                 .right_margin   = 0,
 252                 .upper_margin   = 0,
 253                 .lower_margin   = 0,
 254                 .hsync_len      = 30,
 255                 .vsync_len      = 3,
 256                 .sync           = 0,
 257         },
 258 };
 259
 260 static bool da8xx_fb_is_raster_enabled(void)
 261 {
 262         return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
 263 }
 264
 265 /* Enable the Raster Engine of the LCD Controller */
 266 static void lcd_enable_raster(void)
 267 {
 268         u32 reg;
 269
 270         /* Put LCDC in reset for several cycles */
 271         if (lcd_revision == LCD_VERSION_2)
 272                 /* Write 1 to reset LCDC */
 273                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 274         mdelay(1);
 275
 276         /* Bring LCDC out of reset */
 277         if (lcd_revision == LCD_VERSION_2)
 278                 lcdc_write(0, LCD_CLK_RESET_REG);
 279         mdelay(1);
 280
 281         /* Above reset sequence doesnot reset register context */
 282         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 283         if (!(reg & LCD_RASTER_ENABLE))
 284                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 285 }
 286
 287 /* Disable the Raster Engine of the LCD Controller */
 288 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
 289 {
 290         u32 reg;
 291         int ret;
 292
 293         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 294         if (reg & LCD_RASTER_ENABLE)
 295                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 296         else
 297                 /* return if already disabled */
 298                 return;
 299
 300         if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
 301                         (lcd_revision == LCD_VERSION_2)) {
 302                 frame_done_flag = 0;
 303                 ret = wait_event_interruptible_timeout(frame_done_wq,
 304                                 frame_done_flag != 0,
 305                                 msecs_to_jiffies(50));
 306                 if (ret == 0)
 307                         pr_err("LCD Controller timed out\n");
 308         }
 309 }
 310
 311 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 312 {
 313         u32 start;
 314         u32 end;
 315         u32 reg_ras;
 316         u32 reg_dma;
 317         u32 reg_int;
 318
 319         /* init reg to clear PLM (loading mode) fields */
 320         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 321         reg_ras &= ~(3 << 20);
 322
 323         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 324
 325         if (load_mode == LOAD_DATA) {
 326                 start    = par->dma_start;
 327                 end      = par->dma_end;
 328
 329                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 330                 if (lcd_revision == LCD_VERSION_1) {
 331                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 332                 } else {
 333                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 334                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 335                                 LCD_V2_END_OF_FRAME1_INT_ENA |
 336                                 LCD_FRAME_DONE | LCD_SYNC_LOST;
 337                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 338                 }
 339                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 340
 341                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 342                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 343                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 344                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 345         } else if (load_mode == LOAD_PALETTE) {
 346                 start    = par->p_palette_base;
 347                 end      = start + par->palette_sz - 1;
 348
 349                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 350
 351                 if (lcd_revision == LCD_VERSION_1) {
 352                         reg_ras |= LCD_V1_PL_INT_ENA;
 353                 } else {
 354                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 355                                 LCD_V2_PL_INT_ENA;
 356                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 357                 }
 358
 359                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 360                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 361         }
 362
 363         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 364         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 365
 366         /*
 367          * The Raster enable bit must be set after all other control fields are
 368          * set.
 369          */
 370         lcd_enable_raster();
 371 }
 372
 373 /* Configure the Burst Size and fifo threhold of DMA */
 374 static int lcd_cfg_dma(int burst_size, int fifo_th)
 375 {
 376         u32 reg;
 377
 378         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 379         switch (burst_size) {
 380         case 1:
 381                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 382                 break;
 383         case 2:
 384                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 385                 break;
 386         case 4:
 387                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 388                 break;
 389         case 8:
 390                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 391                 break;
 392         case 16:
 393         default:
 394                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 395                 break;
 396         }
 397
 398         reg |= (fifo_th << 8);
 399
 400         lcdc_write(reg, LCD_DMA_CTRL_REG);
 401
 402         return 0;
 403 }
 404
 405 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 406 {
 407         u32 reg;
 408
 409         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 410         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 411         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 412                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 413         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 414 }
 415
 416 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 417                 int front_porch)
 418 {
 419         u32 reg;
 420
 421         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
 422         reg |= (((back_porch-1) & 0xff) << 24)
 423             | (((front_porch-1) & 0xff) << 16)
 424             | (((pulse_width-1) & 0x3f) << 10);
 425         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 426
 427         /*
 428          * LCDC Version 2 adds some extra bits that increase the allowable
 429          * size of the horizontal timing registers.
 430          * remember that the registers use 0 to represent 1 so all values
 431          * that get set into register need to be decremented by 1
 432          */
 433         if (lcd_revision == LCD_VERSION_2) {
 434                 /* Mask off the bits we want to change */
 435                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
 436                 reg |= ((front_porch-1) & 0x300) >> 8;
 437                 reg |= ((back_porch-1) & 0x300) >> 4;
 438                 reg |= ((pulse_width-1) & 0x3c0) << 21;
 439                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 440         }
 441 }
 442
 443 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 444                 int front_porch)
 445 {
 446         u32 reg;
 447
 448         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 449         reg |= ((back_porch & 0xff) << 24)
 450             | ((front_porch & 0xff) << 16)
 451             | (((pulse_width-1) & 0x3f) << 10);
 452         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 453 }
 454
 455 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
 456                 struct fb_videomode *panel)
 457 {
 458         u32 reg;
 459         u32 reg_int;
 460
 461         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 462                                                 LCD_MONO_8BIT_MODE |
 463                                                 LCD_MONOCHROME_MODE);
 464
 465         switch (cfg->panel_shade) {
 466         case MONOCHROME:
 467                 reg |= LCD_MONOCHROME_MODE;
 468                 if (cfg->mono_8bit_mode)
 469                         reg |= LCD_MONO_8BIT_MODE;
 470                 break;
 471         case COLOR_ACTIVE:
 472                 reg |= LCD_TFT_MODE;
 473                 if (cfg->tft_alt_mode)
 474                         reg |= LCD_TFT_ALT_ENABLE;
 475                 break;
 476
 477         case COLOR_PASSIVE:
 478                 /* AC bias applicable only for Pasive panels */
 479                 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 480                 if (cfg->bpp == 12 && cfg->stn_565_mode)
 481                         reg |= LCD_STN_565_ENABLE;
 482                 break;
 483
 484         default:
 485                 return -EINVAL;
 486         }
 487
 488         /* enable additional interrupts here */
 489         if (lcd_revision == LCD_VERSION_1) {
 490                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 491         } else {
 492                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 493                         LCD_V2_UNDERFLOW_INT_ENA;
 494                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 495         }
 496
 497         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 498
 499         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 500
 501         reg |= LCD_SYNC_CTRL;
 502
 503         if (cfg->sync_edge)
 504                 reg |= LCD_SYNC_EDGE;
 505         else
 506                 reg &= ~LCD_SYNC_EDGE;
 507
 508         if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
 509                 reg |= LCD_INVERT_LINE_CLOCK;
 510         else
 511                 reg &= ~LCD_INVERT_LINE_CLOCK;
 512
 513         if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
 514                 reg |= LCD_INVERT_FRAME_CLOCK;
 515         else
 516                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 517
 518         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 519
 520         return 0;
 521 }
 522
 523 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 524                 u32 bpp, u32 raster_order)
 525 {
 526         u32 reg;
 527
 528         if (bpp > 16 && lcd_revision == LCD_VERSION_1)
 529                 return -EINVAL;
 530
 531         /* Set the Panel Width */
 532         /* Pixels per line = (PPL + 1)*16 */
 533         if (lcd_revision == LCD_VERSION_1) {
 534                 /*
 535                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 536                  * pixels.
 537                  */
 538                 width &= 0x3f0;
 539         } else {
 540                 /*
 541                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 542                  * pixels.
 543                  */
 544                 width &= 0x7f0;
 545         }
 546
 547         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 548         reg &= 0xfffffc00;
 549         if (lcd_revision == LCD_VERSION_1) {
 550                 reg |= ((width >> 4) - 1) << 4;
 551         } else {
 552                 width = (width >> 4) - 1;
 553                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 554         }
 555         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 556
 557         /* Set the Panel Height */
 558         /* Set bits 9:0 of Lines Per Pixel */
 559         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 560         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 561         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 562
 563         /* Set bit 10 of Lines Per Pixel */
 564         if (lcd_revision == LCD_VERSION_2) {
 565                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 566                 reg |= ((height - 1) & 0x400) << 16;
 567                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 568         }
 569
 570         /* Set the Raster Order of the Frame Buffer */
 571         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 572         if (raster_order)
 573                 reg |= LCD_RASTER_ORDER;
 574
 575         par->palette_sz = 16 * 2;
 576
 577         switch (bpp) {
 578         case 1:
 579         case 2:
 580         case 4:
 581         case 16:
 582                 break;
 583         case 24:
 584                 reg |= LCD_V2_TFT_24BPP_MODE;
 585                 break;
 586         case 32:
 587                 reg |= LCD_V2_TFT_24BPP_MODE;
 588                 reg |= LCD_V2_TFT_24BPP_UNPACK;
 589                 break;
 590         case 8:
 591                 par->palette_sz = 256 * 2;
 592                 break;
 593
 594         default:
 595                 return -EINVAL;
 596         }
 597
 598         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 599
 600         return 0;
 601 }
 602
 603 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 604 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 605                               unsigned blue, unsigned transp,
 606                               struct fb_info *info)
 607 {
 608         struct da8xx_fb_par *par = info->par;
 609         unsigned short *palette = (unsigned short *) par->v_palette_base;
 610         u_short pal;
 611         int update_hw = 0;
 612
 613         if (regno > 255)
 614                 return 1;
 615
 616         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 617                 return 1;
 618
 619         if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 620                 return -EINVAL;
 621
 622         switch (info->fix.visual) {
 623         case FB_VISUAL_TRUECOLOR:
 624                 red = CNVT_TOHW(red, info->var.red.length);
 625                 green = CNVT_TOHW(green, info->var.green.length);
 626                 blue = CNVT_TOHW(blue, info->var.blue.length);
 627                 break;
 628         case FB_VISUAL_PSEUDOCOLOR:
 629                 switch (info->var.bits_per_pixel) {
 630                 case 4:
 631                         if (regno > 15)
 632                                 return -EINVAL;
 633
 634                         if (info->var.grayscale) {
 635                                 pal = regno;
 636                         } else {
 637                                 red >>= 4;
 638                                 green >>= 8;
 639                                 blue >>= 12;
 640
 641                                 pal = red & 0x0f00;
 642                                 pal |= green & 0x00f0;
 643                                 pal |= blue & 0x000f;
 644                         }
 645                         if (regno == 0)
 646                                 pal |= 0x2000;
 647                         palette[regno] = pal;
 648                         break;
 649
 650                 case 8:
 651                         red >>= 4;
 652                         green >>= 8;
 653                         blue >>= 12;
 654
 655                         pal = (red & 0x0f00);
 656                         pal |= (green & 0x00f0);
 657                         pal |= (blue & 0x000f);
 658
 659                         if (palette[regno] != pal) {
 660                                 update_hw = 1;
 661                                 palette[regno] = pal;
 662                         }
 663                         break;
 664                 }
 665                 break;
 666         }
 667
 668         /* Truecolor has hardware independent palette */
 669         if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
 670                 u32 v;
 671
 672                 if (regno > 15)
 673                         return -EINVAL;
 674
 675                 v = (red << info->var.red.offset) |
 676                         (green << info->var.green.offset) |
 677                         (blue << info->var.blue.offset);
 678
 679                 ((u32 *) (info->pseudo_palette))[regno] = v;
 680                 if (palette[0] != 0x4000) {
 681                         update_hw = 1;
 682                         palette[0] = 0x4000;
 683                 }
 684         }
 685
 686         /* Update the palette in the h/w as needed. */
 687         if (update_hw)
 688                 lcd_blit(LOAD_PALETTE, par);
 689
 690         return 0;
 691 }
 692 #undef CNVT_TOHW
 693
 694 static void da8xx_fb_lcd_reset(void)
 695 {
 696         /* DMA has to be disabled */
 697         lcdc_write(0, LCD_DMA_CTRL_REG);
 698         lcdc_write(0, LCD_RASTER_CTRL_REG);
 699
 700         if (lcd_revision == LCD_VERSION_2) {
 701                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 702                 /* Write 1 to reset */
 703                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 704                 lcdc_write(0, LCD_CLK_RESET_REG);
 705         }
 706 }
 707
 708 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
 709                                               unsigned lcdc_clk_div,
 710                                               unsigned lcdc_clk_rate)
 711 {
 712         int ret;
 713
 714         if (par->lcdc_clk_rate != lcdc_clk_rate) {
 715                 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
 716                 if (ret) {
 717                         dev_err(par->dev,
 718                                 "unable to set clock rate at %u\n",
 719                                 lcdc_clk_rate);
 720                         return ret;
 721                 }
 722                 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
 723         }
 724
 725         /* Configure the LCD clock divisor. */
 726         lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
 727                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 728
 729         if (lcd_revision == LCD_VERSION_2)
 730                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 731                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 732
 733         return 0;
 734 }
 735
 736 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
 737                                               unsigned pixclock,
 738                                               unsigned *lcdc_clk_rate)
 739 {
 740         unsigned lcdc_clk_div;
 741
 742         pixclock = PICOS2KHZ(pixclock) * 1000;
 743
 744         *lcdc_clk_rate = par->lcdc_clk_rate;
 745
 746         if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
 747                 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
 748                                                 pixclock * CLK_MAX_DIV);
 749                 lcdc_clk_div = CLK_MAX_DIV;
 750         } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
 751                 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
 752                                                 pixclock * CLK_MIN_DIV);
 753                 lcdc_clk_div = CLK_MIN_DIV;
 754         } else {
 755                 lcdc_clk_div = *lcdc_clk_rate / pixclock;
 756         }
 757
 758         return lcdc_clk_div;
 759 }
 760
 761 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
 762                                             struct fb_videomode *mode)
 763 {
 764         unsigned lcdc_clk_rate;
 765         unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
 766                                                           &lcdc_clk_rate);
 767
 768         return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
 769 }
 770
 771 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
 772                                           unsigned pixclock)
 773 {
 774         unsigned lcdc_clk_div, lcdc_clk_rate;
 775
 776         lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
 777         return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
 778 }
 779
 780 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 781                 struct fb_videomode *panel)
 782 {
 783         u32 bpp;
 784         int ret = 0;
 785
 786         ret = da8xx_fb_calc_config_clk_divider(par, panel);
 787         if (ret) {
 788                 dev_err(par->dev, "unable to configure clock\n");
 789                 return ret;
 790         }
 791
 792         if (panel->sync & FB_SYNC_CLK_INVERT)
 793                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 794                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 795         else
 796                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 797                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 798
 799         /* Configure the DMA burst size and fifo threshold. */
 800         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
 801         if (ret < 0)
 802                 return ret;
 803
 804         /* Configure the vertical and horizontal sync properties. */
 805         lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
 806                         panel->lower_margin);
 807         lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
 808                         panel->right_margin);
 809
 810         /* Configure for disply */
 811         ret = lcd_cfg_display(cfg, panel);
 812         if (ret < 0)
 813                 return ret;
 814
 815         bpp = cfg->bpp;
 816
 817         if (bpp == 12)
 818                 bpp = 16;
 819         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
 820                                 (unsigned int)panel->yres, bpp,
 821                                 cfg->raster_order);
 822         if (ret < 0)
 823                 return ret;
 824
 825         /* Configure FDD */
 826         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 827                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 828
 829         return 0;
 830 }
 831
 832 /* IRQ handler for version 2 of LCDC */
 833 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 834 {
 835         struct da8xx_fb_par *par = arg;
 836         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 837
 838         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 839                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 840                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 841                 lcd_enable_raster();
 842         } else if (stat & LCD_PL_LOAD_DONE) {
 843                 /*
 844                  * Must disable raster before changing state of any control bit.
 845                  * And also must be disabled before clearing the PL loading
 846                  * interrupt via the following write to the status register. If
 847                  * this is done after then one gets multiple PL done interrupts.
 848                  */
 849                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 850
 851                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 852
 853                 /* Disable PL completion interrupt */
 854                 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
 855
 856                 /* Setup and start data loading mode */
 857                 lcd_blit(LOAD_DATA, par);
 858         } else {
 859                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 860
 861                 if (stat & LCD_END_OF_FRAME0) {
 862                         par->which_dma_channel_done = 0;
 863                         lcdc_write(par->dma_start,
 864                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 865                         lcdc_write(par->dma_end,
 866                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 867                         par->vsync_flag = 1;
 868                         wake_up_interruptible(&par->vsync_wait);
 869                 }
 870
 871                 if (stat & LCD_END_OF_FRAME1) {
 872                         par->which_dma_channel_done = 1;
 873                         lcdc_write(par->dma_start,
 874                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 875                         lcdc_write(par->dma_end,
 876                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 877                         par->vsync_flag = 1;
 878                         wake_up_interruptible(&par->vsync_wait);
 879                 }
 880
 881                 /* Set only when controller is disabled and at the end of
 882                  * active frame
 883                  */
 884                 if (stat & BIT(0)) {
 885                         frame_done_flag = 1;
 886                         wake_up_interruptible(&frame_done_wq);
 887                 }
 888         }
 889
 890         lcdc_write(0, LCD_END_OF_INT_IND_REG);
 891         return IRQ_HANDLED;
 892 }
 893
 894 /* IRQ handler for version 1 LCDC */
 895 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 896 {
 897         struct da8xx_fb_par *par = arg;
 898         u32 stat = lcdc_read(LCD_STAT_REG);
 899         u32 reg_ras;
 900
 901         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 902                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 903                 lcdc_write(stat, LCD_STAT_REG);
 904                 lcd_enable_raster();
 905         } else if (stat & LCD_PL_LOAD_DONE) {
 906                 /*
 907                  * Must disable raster before changing state of any control bit.
 908                  * And also must be disabled before clearing the PL loading
 909                  * interrupt via the following write to the status register. If
 910                  * this is done after then one gets multiple PL done interrupts.
 911                  */
 912                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 913
 914                 lcdc_write(stat, LCD_STAT_REG);
 915
 916                 /* Disable PL completion inerrupt */
 917                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 918                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 919                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 920
 921                 /* Setup and start data loading mode */
 922                 lcd_blit(LOAD_DATA, par);
 923         } else {
 924                 lcdc_write(stat, LCD_STAT_REG);
 925
 926                 if (stat & LCD_END_OF_FRAME0) {
 927                         par->which_dma_channel_done = 0;
 928                         lcdc_write(par->dma_start,
 929                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 930                         lcdc_write(par->dma_end,
 931                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 932                         par->vsync_flag = 1;
 933                         wake_up_interruptible(&par->vsync_wait);
 934                 }
 935
 936                 if (stat & LCD_END_OF_FRAME1) {
 937                         par->which_dma_channel_done = 1;
 938                         lcdc_write(par->dma_start,
 939                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 940                         lcdc_write(par->dma_end,
 941                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 942                         par->vsync_flag = 1;
 943                         wake_up_interruptible(&par->vsync_wait);
 944                 }
 945         }
 946
 947         return IRQ_HANDLED;
 948 }
 949
 950 static int fb_check_var(struct fb_var_screeninfo *var,
 951                         struct fb_info *info)
 952 {
 953         int err = 0;
 954         struct da8xx_fb_par *par = info->par;
 955         int bpp = var->bits_per_pixel >> 3;
 956         unsigned long line_size = var->xres_virtual * bpp;
 957
 958         if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 959                 return -EINVAL;
 960
 961         switch (var->bits_per_pixel) {
 962         case 1:
 963         case 8:
 964                 var->red.offset = 0;
 965                 var->red.length = 8;
 966                 var->green.offset = 0;
 967                 var->green.length = 8;
 968                 var->blue.offset = 0;
 969                 var->blue.length = 8;
 970                 var->transp.offset = 0;
 971                 var->transp.length = 0;
 972                 var->nonstd = 0;
 973                 break;
 974         case 4:
 975                 var->red.offset = 0;
 976                 var->red.length = 4;
 977                 var->green.offset = 0;
 978                 var->green.length = 4;
 979                 var->blue.offset = 0;
 980                 var->blue.length = 4;
 981                 var->transp.offset = 0;
 982                 var->transp.length = 0;
 983                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
 984                 break;
 985         case 16:                /* RGB 565 */
 986                 var->red.offset = 11;
 987                 var->red.length = 5;
 988                 var->green.offset = 5;
 989                 var->green.length = 6;
 990                 var->blue.offset = 0;
 991                 var->blue.length = 5;
 992                 var->transp.offset = 0;
 993                 var->transp.length = 0;
 994                 var->nonstd = 0;
 995                 break;
 996         case 24:
 997                 var->red.offset = 16;
 998                 var->red.length = 8;
 999                 var->green.offset = 8;
1000                 var->green.length = 8;
1001                 var->blue.offset = 0;
1002                 var->blue.length = 8;
1003                 var->nonstd = 0;
1004                 break;
1005         case 32:
1006                 var->transp.offset = 24;
1007                 var->transp.length = 8;
1008                 var->red.offset = 16;
1009                 var->red.length = 8;
1010                 var->green.offset = 8;
1011                 var->green.length = 8;
1012                 var->blue.offset = 0;
1013                 var->blue.length = 8;
1014                 var->nonstd = 0;
1015                 break;
1016         default:
1017                 err = -EINVAL;
1018         }
1019
1020         var->red.msb_right = 0;
1021         var->green.msb_right = 0;
1022         var->blue.msb_right = 0;
1023         var->transp.msb_right = 0;
1024
1025         if (line_size * var->yres_virtual > par->vram_size)
1026                 var->yres_virtual = par->vram_size / line_size;
1027
1028         if (var->yres > var->yres_virtual)
1029                 var->yres = var->yres_virtual;
1030
1031         if (var->xres > var->xres_virtual)
1032                 var->xres = var->xres_virtual;
1033
1034         if (var->xres + var->xoffset > var->xres_virtual)
1035                 var->xoffset = var->xres_virtual - var->xres;
1036         if (var->yres + var->yoffset > var->yres_virtual)
1037                 var->yoffset = var->yres_virtual - var->yres;
1038
1039         var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1040
1041         return err;
1042 }
1043
1044 #ifdef CONFIG_CPU_FREQ
1045 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1046                                      unsigned long val, void *data)
1047 {
1048         struct da8xx_fb_par *par;
1049
1050         par = container_of(nb, struct da8xx_fb_par, freq_transition);
1051         if (val == CPUFREQ_POSTCHANGE) {
1052                 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1053                         par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1054                         lcd_disable_raster(DA8XX_FRAME_WAIT);
1055                         da8xx_fb_calc_config_clk_divider(par, &par->mode);
1056                         if (par->blank == FB_BLANK_UNBLANK)
1057                                 lcd_enable_raster();
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1065 {
1066         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1067
1068         return cpufreq_register_notifier(&par->freq_transition,
1069                                          CPUFREQ_TRANSITION_NOTIFIER);
1070 }
1071
1072 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1073 {
1074         cpufreq_unregister_notifier(&par->freq_transition,
1075                                     CPUFREQ_TRANSITION_NOTIFIER);
1076 }
1077 #endif
1078
1079 static int fb_remove(struct platform_device *dev)
1080 {
1081         struct fb_info *info = dev_get_drvdata(&dev->dev);
1082
1083         if (info) {
1084                 struct da8xx_fb_par *par = info->par;
1085
1086 #ifdef CONFIG_CPU_FREQ
1087                 lcd_da8xx_cpufreq_deregister(par);
1088 #endif
1089                 if (par->panel_power_ctrl)
1090                         par->panel_power_ctrl(0);
1091
1092                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1093                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1094
1095                 /* disable DMA  */
1096                 lcdc_write(0, LCD_DMA_CTRL_REG);
1097
1098                 unregister_framebuffer(info);
1099                 fb_dealloc_cmap(&info->cmap);
1100                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1101                                   par->p_palette_base);
1102                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1103                                   par->vram_phys);
1104                 pm_runtime_put_sync(&dev->dev);
1105                 pm_runtime_disable(&dev->dev);
1106                 framebuffer_release(info);
1107
1108         }
1109         return 0;
1110 }
1111
1112 /*
1113  * Function to wait for vertical sync which for this LCD peripheral
1114  * translates into waiting for the current raster frame to complete.
1115  */
1116 static int fb_wait_for_vsync(struct fb_info *info)
1117 {
1118         struct da8xx_fb_par *par = info->par;
1119         int ret;
1120
1121         /*
1122          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1123          * race condition here where the ISR could have occurred just before or
1124          * just after this set. But since we are just coarsely waiting for
1125          * a frame to complete then that's OK. i.e. if the frame completed
1126          * just before this code executed then we have to wait another full
1127          * frame time but there is no way to avoid such a situation. On the
1128          * other hand if the frame completed just after then we don't need
1129          * to wait long at all. Either way we are guaranteed to return to the
1130          * user immediately after a frame completion which is all that is
1131          * required.
1132          */
1133         par->vsync_flag = 0;
1134         ret = wait_event_interruptible_timeout(par->vsync_wait,
1135                                                par->vsync_flag != 0,
1136                                                par->vsync_timeout);
1137         if (ret < 0)
1138                 return ret;
1139         if (ret == 0)
1140                 return -ETIMEDOUT;
1141
1142         return 0;
1143 }
1144
1145 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1146                           unsigned long arg)
1147 {
1148         struct lcd_sync_arg sync_arg;
1149
1150         switch (cmd) {
1151         case FBIOGET_CONTRAST:
1152         case FBIOPUT_CONTRAST:
1153         case FBIGET_BRIGHTNESS:
1154         case FBIPUT_BRIGHTNESS:
1155         case FBIGET_COLOR:
1156         case FBIPUT_COLOR:
1157                 return -ENOTTY;
1158         case FBIPUT_HSYNC:
1159                 if (copy_from_user(&sync_arg, (char *)arg,
1160                                 sizeof(struct lcd_sync_arg)))
1161                         return -EFAULT;
1162                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1163                                         sync_arg.pulse_width,
1164                                         sync_arg.front_porch);
1165                 break;
1166         case FBIPUT_VSYNC:
1167                 if (copy_from_user(&sync_arg, (char *)arg,
1168                                 sizeof(struct lcd_sync_arg)))
1169                         return -EFAULT;
1170                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1171                                         sync_arg.pulse_width,
1172                                         sync_arg.front_porch);
1173                 break;
1174         case FBIO_WAITFORVSYNC:
1175                 return fb_wait_for_vsync(info);
1176         default:
1177                 return -EINVAL;
1178         }
1179         return 0;
1180 }
1181
1182 static int cfb_blank(int blank, struct fb_info *info)
1183 {
1184         struct da8xx_fb_par *par = info->par;
1185         int ret = 0;
1186
1187         if (par->blank == blank)
1188                 return 0;
1189
1190         par->blank = blank;
1191         switch (blank) {
1192         case FB_BLANK_UNBLANK:
1193                 lcd_enable_raster();
1194
1195                 if (par->panel_power_ctrl)
1196                         par->panel_power_ctrl(1);
1197                 break;
1198         case FB_BLANK_NORMAL:
1199         case FB_BLANK_VSYNC_SUSPEND:
1200         case FB_BLANK_HSYNC_SUSPEND:
1201         case FB_BLANK_POWERDOWN:
1202                 if (par->panel_power_ctrl)
1203                         par->panel_power_ctrl(0);
1204
1205                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1206                 break;
1207         default:
1208                 ret = -EINVAL;
1209         }
1210
1211         return ret;
1212 }
1213
1214 /*
1215  * Set new x,y offsets in the virtual display for the visible area and switch
1216  * to the new mode.
1217  */
1218 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1219                              struct fb_info *fbi)
1220 {
1221         int ret = 0;
1222         struct fb_var_screeninfo new_var;
1223         struct da8xx_fb_par         *par = fbi->par;
1224         struct fb_fix_screeninfo    *fix = &fbi->fix;
1225         unsigned int end;
1226         unsigned int start;
1227         unsigned long irq_flags;
1228
1229         if (var->xoffset != fbi->var.xoffset ||
1230                         var->yoffset != fbi->var.yoffset) {
1231                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1232                 new_var.xoffset = var->xoffset;
1233                 new_var.yoffset = var->yoffset;
1234                 if (fb_check_var(&new_var, fbi))
1235                         ret = -EINVAL;
1236                 else {
1237                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1238
1239                         start   = fix->smem_start +
1240                                 new_var.yoffset * fix->line_length +
1241                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1242                         end     = start + fbi->var.yres * fix->line_length - 1;
1243                         par->dma_start  = start;
1244                         par->dma_end    = end;
1245                         spin_lock_irqsave(&par->lock_for_chan_update,
1246                                         irq_flags);
1247                         if (par->which_dma_channel_done == 0) {
1248                                 lcdc_write(par->dma_start,
1249                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1250                                 lcdc_write(par->dma_end,
1251                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1252                         } else if (par->which_dma_channel_done == 1) {
1253                                 lcdc_write(par->dma_start,
1254                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1255                                 lcdc_write(par->dma_end,
1256                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1257                         }
1258                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1259                                         irq_flags);
1260                 }
1261         }
1262
1263         return ret;
1264 }
1265
1266 static int da8xxfb_set_par(struct fb_info *info)
1267 {
1268         struct da8xx_fb_par *par = info->par;
1269         int ret;
1270         bool raster = da8xx_fb_is_raster_enabled();
1271
1272         if (raster)
1273                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1274
1275         fb_var_to_videomode(&par->mode, &info->var);
1276
1277         par->cfg.bpp = info->var.bits_per_pixel;
1278
1279         info->fix.visual = (par->cfg.bpp <= 8) ?
1280                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1281         info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1282
1283         ret = lcd_init(par, &par->cfg, &par->mode);
1284         if (ret < 0) {
1285                 dev_err(par->dev, "lcd init failed\n");
1286                 return ret;
1287         }
1288
1289         par->dma_start = info->fix.smem_start +
1290                          info->var.yoffset * info->fix.line_length +
1291                          info->var.xoffset * info->var.bits_per_pixel / 8;
1292         par->dma_end   = par->dma_start +
1293                          info->var.yres * info->fix.line_length - 1;
1294
1295         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1296         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1297         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1298         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1299
1300         if (raster)
1301                 lcd_enable_raster();
1302
1303         return 0;
1304 }
1305
1306 static struct fb_ops da8xx_fb_ops = {
1307         .owner = THIS_MODULE,
1308         .fb_check_var = fb_check_var,
1309         .fb_set_par = da8xxfb_set_par,
1310         .fb_setcolreg = fb_setcolreg,
1311         .fb_pan_display = da8xx_pan_display,
1312         .fb_ioctl = fb_ioctl,
1313         .fb_fillrect = cfb_fillrect,
1314         .fb_copyarea = cfb_copyarea,
1315         .fb_imageblit = cfb_imageblit,
1316         .fb_blank = cfb_blank,
1317 };
1318
1319 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1320 {
1321         struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
1322         struct fb_videomode *lcdc_info;
1323         int i;
1324
1325         for (i = 0, lcdc_info = known_lcd_panels;
1326                 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1327                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1328                         break;
1329         }
1330
1331         if (i == ARRAY_SIZE(known_lcd_panels)) {
1332                 dev_err(&dev->dev, "no panel found\n");
1333                 return NULL;
1334         }
1335         dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1336
1337         return lcdc_info;
1338 }
1339
1340 static int fb_probe(struct platform_device *device)
1341 {
1342         struct da8xx_lcdc_platform_data *fb_pdata =
1343                                                 dev_get_platdata(&device->dev);
1344         struct resource *lcdc_regs;
1345         struct lcd_ctrl_config *lcd_cfg;
1346         struct fb_videomode *lcdc_info;
1347         struct fb_info *da8xx_fb_info;
1348         struct da8xx_fb_par *par;
1349         struct clk *tmp_lcdc_clk;
1350         int ret;
1351         unsigned long ulcm;
1352
1353         if (fb_pdata == NULL) {
1354                 dev_err(&device->dev, "Can not get platform data\n");
1355                 return -ENOENT;
1356         }
1357
1358         lcdc_info = da8xx_fb_get_videomode(device);
1359         if (lcdc_info == NULL)
1360                 return -ENODEV;
1361
1362         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1363         da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs);
1364         if (IS_ERR(da8xx_fb_reg_base))
1365                 return PTR_ERR(da8xx_fb_reg_base);
1366
1367         tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1368         if (IS_ERR(tmp_lcdc_clk)) {
1369                 dev_err(&device->dev, "Can not get device clock\n");
1370                 return PTR_ERR(tmp_lcdc_clk);
1371         }
1372
1373         pm_runtime_enable(&device->dev);
1374         pm_runtime_get_sync(&device->dev);
1375
1376         /* Determine LCD IP Version */
1377         switch (lcdc_read(LCD_PID_REG)) {
1378         case 0x4C100102:
1379                 lcd_revision = LCD_VERSION_1;
1380                 break;
1381         case 0x4F200800:
1382         case 0x4F201000:
1383                 lcd_revision = LCD_VERSION_2;
1384                 break;
1385         default:
1386                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1387                                 "defaulting to LCD revision 1\n",
1388                                 lcdc_read(LCD_PID_REG));
1389                 lcd_revision = LCD_VERSION_1;
1390                 break;
1391         }
1392
1393         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1394
1395         if (!lcd_cfg) {
1396                 ret = -EINVAL;
1397                 goto err_pm_runtime_disable;
1398         }
1399
1400         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1401                                         &device->dev);
1402         if (!da8xx_fb_info) {
1403                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1404                 ret = -ENOMEM;
1405                 goto err_pm_runtime_disable;
1406         }
1407
1408         par = da8xx_fb_info->par;
1409         par->dev = &device->dev;
1410         par->lcdc_clk = tmp_lcdc_clk;
1411         par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1412         if (fb_pdata->panel_power_ctrl) {
1413                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1414                 par->panel_power_ctrl(1);
1415         }
1416
1417         fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1418         par->cfg = *lcd_cfg;
1419
1420         da8xx_fb_lcd_reset();
1421
1422         /* allocate frame buffer */
1423         par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1424         ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1425         par->vram_size = roundup(par->vram_size/8, ulcm);
1426         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1427
1428         par->vram_virt = dma_alloc_coherent(NULL,
1429                                             par->vram_size,
1430                                             &par->vram_phys,
1431                                             GFP_KERNEL | GFP_DMA);
1432         if (!par->vram_virt) {
1433                 dev_err(&device->dev,
1434                         "GLCD: kmalloc for frame buffer failed\n");
1435                 ret = -EINVAL;
1436                 goto err_release_fb;
1437         }
1438
1439         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1440         da8xx_fb_fix.smem_start    = par->vram_phys;
1441         da8xx_fb_fix.smem_len      = par->vram_size;
1442         da8xx_fb_fix.line_length   = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1443
1444         par->dma_start = par->vram_phys;
1445         par->dma_end   = par->dma_start + lcdc_info->yres *
1446                 da8xx_fb_fix.line_length - 1;
1447
1448         /* allocate palette buffer */
1449         par->v_palette_base = dma_alloc_coherent(NULL, PALETTE_SIZE,
1450                                                  &par->p_palette_base,
1451                                                  GFP_KERNEL | GFP_DMA);
1452         if (!par->v_palette_base) {
1453                 dev_err(&device->dev,
1454                         "GLCD: kmalloc for palette buffer failed\n");
1455                 ret = -EINVAL;
1456                 goto err_release_fb_mem;
1457         }
1458
1459         par->irq = platform_get_irq(device, 0);
1460         if (par->irq < 0) {
1461                 ret = -ENOENT;
1462                 goto err_release_pl_mem;
1463         }
1464
1465         da8xx_fb_var.grayscale =
1466             lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1467         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1468
1469         /* Initialize fbinfo */
1470         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1471         da8xx_fb_info->fix = da8xx_fb_fix;
1472         da8xx_fb_info->var = da8xx_fb_var;
1473         da8xx_fb_info->fbops = &da8xx_fb_ops;
1474         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1475         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1476                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1477
1478         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1479         if (ret)
1480                 goto err_release_pl_mem;
1481         da8xx_fb_info->cmap.len = par->palette_sz;
1482
1483         /* initialize var_screeninfo */
1484         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1485         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1486
1487         dev_set_drvdata(&device->dev, da8xx_fb_info);
1488
1489         /* initialize the vsync wait queue */
1490         init_waitqueue_head(&par->vsync_wait);
1491         par->vsync_timeout = HZ / 5;
1492         par->which_dma_channel_done = -1;
1493         spin_lock_init(&par->lock_for_chan_update);
1494
1495         /* Register the Frame Buffer  */
1496         if (register_framebuffer(da8xx_fb_info) < 0) {
1497                 dev_err(&device->dev,
1498                         "GLCD: Frame Buffer Registration Failed!\n");
1499                 ret = -EINVAL;
1500                 goto err_dealloc_cmap;
1501         }
1502
1503 #ifdef CONFIG_CPU_FREQ
1504         ret = lcd_da8xx_cpufreq_register(par);
1505         if (ret) {
1506                 dev_err(&device->dev, "failed to register cpufreq\n");
1507                 goto err_cpu_freq;
1508         }
1509 #endif
1510
1511         if (lcd_revision == LCD_VERSION_1)
1512                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1513         else {
1514                 init_waitqueue_head(&frame_done_wq);
1515                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1516         }
1517
1518         ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1519                                DRIVER_NAME, par);
1520         if (ret)
1521                 goto irq_freq;
1522         return 0;
1523
1524 irq_freq:
1525 #ifdef CONFIG_CPU_FREQ
1526         lcd_da8xx_cpufreq_deregister(par);
1527 err_cpu_freq:
1528 #endif
1529         unregister_framebuffer(da8xx_fb_info);
1530
1531 err_dealloc_cmap:
1532         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1533
1534 err_release_pl_mem:
1535         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1536                           par->p_palette_base);
1537
1538 err_release_fb_mem:
1539         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1540
1541 err_release_fb:
1542         framebuffer_release(da8xx_fb_info);
1543
1544 err_pm_runtime_disable:
1545         pm_runtime_put_sync(&device->dev);
1546         pm_runtime_disable(&device->dev);
1547
1548         return ret;
1549 }
1550
1551 #ifdef CONFIG_PM_SLEEP
1552 static struct lcdc_context {
1553         u32 clk_enable;
1554         u32 ctrl;
1555         u32 dma_ctrl;
1556         u32 raster_timing_0;
1557         u32 raster_timing_1;
1558         u32 raster_timing_2;
1559         u32 int_enable_set;
1560         u32 dma_frm_buf_base_addr_0;
1561         u32 dma_frm_buf_ceiling_addr_0;
1562         u32 dma_frm_buf_base_addr_1;
1563         u32 dma_frm_buf_ceiling_addr_1;
1564         u32 raster_ctrl;
1565 } reg_context;
1566
1567 static void lcd_context_save(void)
1568 {
1569         if (lcd_revision == LCD_VERSION_2) {
1570                 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1571                 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1572         }
1573
1574         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1575         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1576         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1577         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1578         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1579         reg_context.dma_frm_buf_base_addr_0 =
1580                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1581         reg_context.dma_frm_buf_ceiling_addr_0 =
1582                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1583         reg_context.dma_frm_buf_base_addr_1 =
1584                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1585         reg_context.dma_frm_buf_ceiling_addr_1 =
1586                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1587         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1588         return;
1589 }
1590
1591 static void lcd_context_restore(void)
1592 {
1593         if (lcd_revision == LCD_VERSION_2) {
1594                 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1595                 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1596         }
1597
1598         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1599         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1600         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1601         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1602         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1603         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1604                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1605         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1606                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1607         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1608                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1609         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1610                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1611         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1612         return;
1613 }
1614
1615 static int fb_suspend(struct device *dev)
1616 {
1617         struct fb_info *info = dev_get_drvdata(dev);
1618         struct da8xx_fb_par *par = info->par;
1619
1620         console_lock();
1621         if (par->panel_power_ctrl)
1622                 par->panel_power_ctrl(0);
1623
1624         fb_set_suspend(info, 1);
1625         lcd_disable_raster(DA8XX_FRAME_WAIT);
1626         lcd_context_save();
1627         pm_runtime_put_sync(dev);
1628         console_unlock();
1629
1630         return 0;
1631 }
1632 static int fb_resume(struct device *dev)
1633 {
1634         struct fb_info *info = dev_get_drvdata(dev);
1635         struct da8xx_fb_par *par = info->par;
1636
1637         console_lock();
1638         pm_runtime_get_sync(dev);
1639         lcd_context_restore();
1640         if (par->blank == FB_BLANK_UNBLANK) {
1641                 lcd_enable_raster();
1642
1643                 if (par->panel_power_ctrl)
1644                         par->panel_power_ctrl(1);
1645         }
1646
1647         fb_set_suspend(info, 0);
1648         console_unlock();
1649
1650         return 0;
1651 }
1652 #endif
1653
1654 static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume);
1655
1656 static struct platform_driver da8xx_fb_driver = {
1657         .probe = fb_probe,
1658         .remove = fb_remove,
1659         .driver = {
1660                    .name = DRIVER_NAME,
1661                    .pm  = &fb_pm_ops,
1662                    },
1663 };
1664 module_platform_driver(da8xx_fb_driver);
1665
1666 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1667 MODULE_AUTHOR("Texas Instruments");
1668 MODULE_LICENSE("GPL");