drivers/video/cg3.c

   1 /* cg3.c: CGTHREE frame buffer driver
   2  *
   3  * Copyright (C) 2003 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
   5  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
   6  * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
   7  *
   8  * Driver layout based loosely on tgafb.c, see that file for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/string.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/fb.h>
  19 #include <linux/mm.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/sbus.h>
  23 #include <asm/oplib.h>
  24 #include <asm/fbio.h>
  25
  26 #include "sbuslib.h"
  27
  28 /*
  29  * Local functions.
  30  */
  31
  32 static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
  33                          unsigned, struct fb_info *);
  34 static int cg3_blank(int, struct fb_info *);
  35
  36 static int cg3_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
  37 static int cg3_ioctl(struct inode *, struct file *, unsigned int,
  38                      unsigned long, struct fb_info *);
  39
  40 /*
  41  *  Frame buffer operations
  42  */
  43
  44 static struct fb_ops cg3_ops = {
  45         .owner                  = THIS_MODULE,
  46         .fb_setcolreg           = cg3_setcolreg,
  47         .fb_blank               = cg3_blank,
  48         .fb_fillrect            = cfb_fillrect,
  49         .fb_copyarea            = cfb_copyarea,
  50         .fb_imageblit           = cfb_imageblit,
  51         .fb_mmap                = cg3_mmap,
  52         .fb_ioctl               = cg3_ioctl,
  53 #ifdef CONFIG_COMPAT
  54         .fb_compat_ioctl        = sbusfb_compat_ioctl,
  55 #endif
  56 };
  57
  58
  59 /* Control Register Constants */
  60 #define CG3_CR_ENABLE_INTS      0x80
  61 #define CG3_CR_ENABLE_VIDEO     0x40
  62 #define CG3_CR_ENABLE_TIMING    0x20
  63 #define CG3_CR_ENABLE_CURCMP    0x10
  64 #define CG3_CR_XTAL_MASK        0x0c
  65 #define CG3_CR_DIVISOR_MASK     0x03
  66
  67 /* Status Register Constants */
  68 #define CG3_SR_PENDING_INT      0x80
  69 #define CG3_SR_RES_MASK         0x70
  70 #define CG3_SR_1152_900_76_A    0x40
  71 #define CG3_SR_1152_900_76_B    0x60
  72 #define CG3_SR_ID_MASK          0x0f
  73 #define CG3_SR_ID_COLOR         0x01
  74 #define CG3_SR_ID_MONO          0x02
  75 #define CG3_SR_ID_MONO_ECL      0x03
  76
  77 enum cg3_type {
  78         CG3_AT_66HZ = 0,
  79         CG3_AT_76HZ,
  80         CG3_RDI
  81 };
  82
  83 struct bt_regs {
  84         volatile u32 addr;
  85         volatile u32 color_map;
  86         volatile u32 control;
  87         volatile u32 cursor;
  88 };
  89
  90 struct cg3_regs {
  91         struct bt_regs  cmap;
  92         volatile u8     control;
  93         volatile u8     status;
  94         volatile u8     cursor_start;
  95         volatile u8     cursor_end;
  96         volatile u8     h_blank_start;
  97         volatile u8     h_blank_end;
  98         volatile u8     h_sync_start;
  99         volatile u8     h_sync_end;
 100         volatile u8     comp_sync_end;
 101         volatile u8     v_blank_start_high;
 102         volatile u8     v_blank_start_low;
 103         volatile u8     v_blank_end;
 104         volatile u8     v_sync_start;
 105         volatile u8     v_sync_end;
 106         volatile u8     xfer_holdoff_start;
 107         volatile u8     xfer_holdoff_end;
 108 };
 109
 110 /* Offset of interesting structures in the OBIO space */
 111 #define CG3_REGS_OFFSET      0x400000UL
 112 #define CG3_RAM_OFFSET       0x800000UL
 113
 114 struct cg3_par {
 115         spinlock_t              lock;
 116         struct cg3_regs         __iomem *regs;
 117         u32                     sw_cmap[((256 * 3) + 3) / 4];
 118
 119         u32                     flags;
 120 #define CG3_FLAG_BLANKED        0x00000001
 121 #define CG3_FLAG_RDI            0x00000002
 122
 123         unsigned long           physbase;
 124         unsigned long           fbsize;
 125
 126         struct sbus_dev         *sdev;
 127 };
 128
 129 /**
 130  *      cg3_setcolreg - Optional function. Sets a color register.
 131  *      @regno: boolean, 0 copy local, 1 get_user() function
 132  *      @red: frame buffer colormap structure
 133  *      @green: The green value which can be up to 16 bits wide
 134  *      @blue:  The blue value which can be up to 16 bits wide.
 135  *      @transp: If supported the alpha value which can be up to 16 bits wide.
 136  *      @info: frame buffer info structure
 137  *
 138  * The cg3 palette is loaded with 4 color values at each time
 139  * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
 140  * We keep a sw copy of the hw cmap to assist us in this esoteric
 141  * loading procedure.
 142  */
 143 static int cg3_setcolreg(unsigned regno,
 144                          unsigned red, unsigned green, unsigned blue,
 145                          unsigned transp, struct fb_info *info)
 146 {
 147         struct cg3_par *par = (struct cg3_par *) info->par;
 148         struct bt_regs __iomem *bt = &par->regs->cmap;
 149         unsigned long flags;
 150         u32 *p32;
 151         u8 *p8;
 152         int count;
 153
 154         if (regno >= 256)
 155                 return 1;
 156
 157         red >>= 8;
 158         green >>= 8;
 159         blue >>= 8;
 160
 161         spin_lock_irqsave(&par->lock, flags);
 162
 163         p8 = (u8 *)par->sw_cmap + (regno * 3);
 164         p8[0] = red;
 165         p8[1] = green;
 166         p8[2] = blue;
 167
 168 #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2))      /* (x/4)*3 */
 169 #define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */
 170
 171         count = 3;
 172         p32 = &par->sw_cmap[D4M3(regno)];
 173         sbus_writel(D4M4(regno), &bt->addr);
 174         while (count--)
 175                 sbus_writel(*p32++, &bt->color_map);
 176
 177 #undef D4M3
 178 #undef D4M4
 179
 180         spin_unlock_irqrestore(&par->lock, flags);
 181
 182         return 0;
 183 }
 184
 185 /**
 186  *      cg3_blank - Optional function.  Blanks the display.
 187  *      @blank_mode: the blank mode we want.
 188  *      @info: frame buffer structure that represents a single frame buffer
 189  */
 190 static int
 191 cg3_blank(int blank, struct fb_info *info)
 192 {
 193         struct cg3_par *par = (struct cg3_par *) info->par;
 194         struct cg3_regs __iomem *regs = par->regs;
 195         unsigned long flags;
 196         u8 val;
 197
 198         spin_lock_irqsave(&par->lock, flags);
 199
 200         switch (blank) {
 201         case FB_BLANK_UNBLANK: /* Unblanking */
 202                 val = sbus_readb(&regs->control);
 203                 val |= CG3_CR_ENABLE_VIDEO;
 204                 sbus_writeb(val, &regs->control);
 205                 par->flags &= ~CG3_FLAG_BLANKED;
 206                 break;
 207
 208         case FB_BLANK_NORMAL: /* Normal blanking */
 209         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
 210         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
 211         case FB_BLANK_POWERDOWN: /* Poweroff */
 212                 val = sbus_readb(&regs->control);
 213                 val &= ~CG3_CR_ENABLE_VIDEO;
 214                 sbus_writeb(val, &regs->control);
 215                 par->flags |= CG3_FLAG_BLANKED;
 216                 break;
 217         }
 218
 219         spin_unlock_irqrestore(&par->lock, flags);
 220
 221         return 0;
 222 }
 223
 224 static struct sbus_mmap_map cg3_mmap_map[] = {
 225         {
 226                 .voff   = CG3_MMAP_OFFSET,
 227                 .poff   = CG3_RAM_OFFSET,
 228                 .size   = SBUS_MMAP_FBSIZE(1)
 229         },
 230         { .size = 0 }
 231 };
 232
 233 static int cg3_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
 234 {
 235         struct cg3_par *par = (struct cg3_par *)info->par;
 236
 237         return sbusfb_mmap_helper(cg3_mmap_map,
 238                                   par->physbase, par->fbsize,
 239                                   par->sdev->reg_addrs[0].which_io,
 240                                   vma);
 241 }
 242
 243 static int cg3_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 244                      unsigned long arg, struct fb_info *info)
 245 {
 246         struct cg3_par *par = (struct cg3_par *) info->par;
 247
 248         return sbusfb_ioctl_helper(cmd, arg, info,
 249                                    FBTYPE_SUN3COLOR, 8, par->fbsize);
 250 }
 251
 252 /*
 253  *  Initialisation
 254  */
 255
 256 static void
 257 cg3_init_fix(struct fb_info *info, int linebytes)
 258 {
 259         struct cg3_par *par = (struct cg3_par *)info->par;
 260
 261         strlcpy(info->fix.id, par->sdev->prom_name, sizeof(info->fix.id));
 262
 263         info->fix.type = FB_TYPE_PACKED_PIXELS;
 264         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 265
 266         info->fix.line_length = linebytes;
 267
 268         info->fix.accel = FB_ACCEL_SUN_CGTHREE;
 269 }
 270
 271 static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
 272                                     struct sbus_dev *sdev)
 273 {
 274         char buffer[40];
 275         char *p;
 276         int ww, hh;
 277
 278         *buffer = 0;
 279         prom_getstring(sdev->prom_node, "params", buffer, sizeof(buffer));
 280         if (*buffer) {
 281                 ww = simple_strtoul(buffer, &p, 10);
 282                 if (ww && *p == 'x') {
 283                         hh = simple_strtoul(p + 1, &p, 10);
 284                         if (hh && *p == '-') {
 285                                 if (var->xres != ww ||
 286                                     var->yres != hh) {
 287                                         var->xres = var->xres_virtual = ww;
 288                                         var->yres = var->yres_virtual = hh;
 289                                 }
 290                         }
 291                 }
 292         }
 293 }
 294
 295 static u8 cg3regvals_66hz[] __initdata = {      /* 1152 x 900, 66 Hz */
 296         0x14, 0xbb,     0x15, 0x2b,     0x16, 0x04,     0x17, 0x14,
 297         0x18, 0xae,     0x19, 0x03,     0x1a, 0xa8,     0x1b, 0x24,
 298         0x1c, 0x01,     0x1d, 0x05,     0x1e, 0xff,     0x1f, 0x01,
 299         0x10, 0x20,     0
 300 };
 301
 302 static u8 cg3regvals_76hz[] __initdata = {      /* 1152 x 900, 76 Hz */
 303         0x14, 0xb7,     0x15, 0x27,     0x16, 0x03,     0x17, 0x0f,
 304         0x18, 0xae,     0x19, 0x03,     0x1a, 0xae,     0x1b, 0x2a,
 305         0x1c, 0x01,     0x1d, 0x09,     0x1e, 0xff,     0x1f, 0x01,
 306         0x10, 0x24,     0
 307 };
 308
 309 static u8 cg3regvals_rdi[] __initdata = {       /* 640 x 480, cgRDI */
 310         0x14, 0x70,     0x15, 0x20,     0x16, 0x08,     0x17, 0x10,
 311         0x18, 0x06,     0x19, 0x02,     0x1a, 0x31,     0x1b, 0x51,
 312         0x1c, 0x06,     0x1d, 0x0c,     0x1e, 0xff,     0x1f, 0x01,
 313         0x10, 0x22,     0
 314 };
 315
 316 static u8 *cg3_regvals[] __initdata = {
 317         cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
 318 };
 319
 320 static u_char cg3_dacvals[] __initdata = {
 321         4, 0xff,        5, 0x00,        6, 0x70,        7, 0x00,        0
 322 };
 323
 324 static void cg3_do_default_mode(struct cg3_par *par)
 325 {
 326         enum cg3_type type;
 327         u8 *p;
 328
 329         if (par->flags & CG3_FLAG_RDI)
 330                 type = CG3_RDI;
 331         else {
 332                 u8 status = sbus_readb(&par->regs->status), mon;
 333                 if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
 334                         mon = status & CG3_SR_RES_MASK;
 335                         if (mon == CG3_SR_1152_900_76_A ||
 336                             mon == CG3_SR_1152_900_76_B)
 337                                 type = CG3_AT_76HZ;
 338                         else
 339                                 type = CG3_AT_66HZ;
 340                 } else {
 341                         prom_printf("cgthree: can't handle SR %02x\n",
 342                                     status);
 343                         prom_halt();
 344                         return;
 345                 }
 346         }
 347
 348         for (p = cg3_regvals[type]; *p; p += 2) {
 349                 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
 350                 sbus_writeb(p[1], regp);
 351         }
 352         for (p = cg3_dacvals; *p; p += 2) {
 353                 volatile u8 __iomem *regp;
 354
 355                 regp = (volatile u8 __iomem *)&par->regs->cmap.addr;
 356                 sbus_writeb(p[0], regp);
 357                 regp = (volatile u8 __iomem *)&par->regs->cmap.control;
 358                 sbus_writeb(p[1], regp);
 359         }
 360 }
 361
 362 struct all_info {
 363         struct fb_info info;
 364         struct cg3_par par;
 365         struct list_head list;
 366 };
 367 static LIST_HEAD(cg3_list);
 368
 369 static void cg3_init_one(struct sbus_dev *sdev)
 370 {
 371         struct all_info *all;
 372         int linebytes;
 373
 374         all = kmalloc(sizeof(*all), GFP_KERNEL);
 375         if (!all) {
 376                 printk(KERN_ERR "cg3: Cannot allocate memory.\n");
 377                 return;
 378         }
 379         memset(all, 0, sizeof(*all));
 380
 381         INIT_LIST_HEAD(&all->list);
 382
 383         spin_lock_init(&all->par.lock);
 384         all->par.sdev = sdev;
 385
 386         all->par.physbase = sdev->reg_addrs[0].phys_addr;
 387
 388         sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
 389         all->info.var.red.length = 8;
 390         all->info.var.green.length = 8;
 391         all->info.var.blue.length = 8;
 392         if (!strcmp(sdev->prom_name, "cgRDI"))
 393                 all->par.flags |= CG3_FLAG_RDI;
 394         if (all->par.flags & CG3_FLAG_RDI)
 395                 cg3_rdi_maybe_fixup_var(&all->info.var, sdev);
 396
 397         linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
 398                                        all->info.var.xres);
 399         all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
 400
 401         all->par.regs = sbus_ioremap(&sdev->resource[0], CG3_REGS_OFFSET,
 402                              sizeof(struct cg3_regs), "cg3 regs");
 403
 404         all->info.flags = FBINFO_DEFAULT;
 405         all->info.fbops = &cg3_ops;
 406 #ifdef CONFIG_SPARC32
 407         all->info.screen_base = (char __iomem *)
 408                 prom_getintdefault(sdev->prom_node, "address", 0);
 409 #endif
 410         if (!all->info.screen_base)
 411                 all->info.screen_base =
 412                         sbus_ioremap(&sdev->resource[0], CG3_RAM_OFFSET,
 413                                      all->par.fbsize, "cg3 ram");
 414         all->info.par = &all->par;
 415
 416         cg3_blank(0, &all->info);
 417
 418         if (!prom_getbool(sdev->prom_node, "width"))
 419                 cg3_do_default_mode(&all->par);
 420
 421         if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
 422                 printk(KERN_ERR "cg3: Could not allocate color map.\n");
 423                 kfree(all);
 424                 return;
 425         }
 426         fb_set_cmap(&all->info.cmap, &all->info);
 427
 428         cg3_init_fix(&all->info, linebytes);
 429
 430         if (register_framebuffer(&all->info) < 0) {
 431                 printk(KERN_ERR "cg3: Could not register framebuffer.\n");
 432                 fb_dealloc_cmap(&all->info.cmap);
 433                 kfree(all);
 434                 return;
 435         }
 436
 437         list_add(&all->list, &cg3_list);
 438
 439         printk("cg3: %s at %lx:%lx\n",
 440                sdev->prom_name,
 441                (long) sdev->reg_addrs[0].which_io,
 442                (long) sdev->reg_addrs[0].phys_addr);
 443 }
 444
 445 int __init cg3_init(void)
 446 {
 447         struct sbus_bus *sbus;
 448         struct sbus_dev *sdev;
 449
 450         if (fb_get_options("cg3fb", NULL))
 451                 return -ENODEV;
 452
 453         for_all_sbusdev(sdev, sbus) {
 454                 if (!strcmp(sdev->prom_name, "cgthree") ||
 455                     !strcmp(sdev->prom_name, "cgRDI"))
 456                         cg3_init_one(sdev);
 457         }
 458
 459         return 0;
 460 }
 461
 462 void __exit cg3_exit(void)
 463 {
 464         struct list_head *pos, *tmp;
 465
 466         list_for_each_safe(pos, tmp, &cg3_list) {
 467                 struct all_info *all = list_entry(pos, typeof(*all), list);
 468
 469                 unregister_framebuffer(&all->info);
 470                 fb_dealloc_cmap(&all->info.cmap);
 471                 kfree(all);
 472         }
 473 }
 474
 475 int __init
 476 cg3_setup(char *arg)
 477 {
 478         /* No cmdline options yet... */
 479         return 0;
 480 }
 481
 482 module_init(cg3_init);
 483
 484 #ifdef MODULE
 485 module_exit(cg3_exit);
 486 #endif
 487
 488 MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
 489 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
 490 MODULE_LICENSE("GPL");