drivers/video/aty/radeon_pm.c

   1 /*
   2  *      drivers/video/aty/radeon_pm.c
   3  *
   4  *      Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
   5  *      Copyright 2004 Paul Mackerras <paulus@samba.org>
   6  *
   7  *      This is the power management code for ATI radeon chipsets. It contains
   8  *      some dynamic clock PM enable/disable code similar to what X.org does,
   9  *      some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
  10  *      and the necessary bits to re-initialize from scratch a few chips found
  11  *      on PowerMacs as well. The later could be extended to more platforms
  12  *      provided the memory controller configuration code be made more generic,
  13  *      and you can get the proper mode register commands for your RAMs.
  14  *      Those things may be found in the BIOS image...
  15  */
  16
  17 #include "radeonfb.h"
  18
  19 #include <linux/console.h>
  20 #include <linux/agp_backend.h>
  21
  22 #ifdef CONFIG_PPC_PMAC
  23 #include <asm/machdep.h>
  24 #include <asm/prom.h>
  25 #include <asm/pmac_feature.h>
  26 #endif
  27
  28 #include "ati_ids.h"
  29
  30 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
  31
  32 /*
  33  * Workarounds for bugs in PC laptops:
  34  * - enable D2 sleep in some IBM Thinkpads
  35  * - special case for Samsung P35
  36  *
  37  * Whitelist by subsystem vendor/device because
  38  * its the subsystem vendor's fault!
  39  */
  40
  41 #if defined(CONFIG_PM) && defined(CONFIG_X86)
  42 struct radeon_device_id {
  43         const char *ident;                     /* (arbitrary) Name */
  44         const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
  45         const unsigned short subsystem_device; /* Subsystem Device ID */
  46         const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
  47         const reinit_function_ptr new_reinit_func;   /* changed reinit_func */
  48 };
  49
  50 #define BUGFIX(model, sv, sd, pm, fn) { \
  51         .ident = model, \
  52         .subsystem_vendor = sv, \
  53         .subsystem_device = sd, \
  54         .pm_mode_modifier = pm, \
  55         .new_reinit_func  = fn  \
  56 }
  57
  58 static struct radeon_device_id radeon_workaround_list[] = {
  59         BUGFIX("IBM Thinkpad R32",
  60                PCI_VENDOR_ID_IBM, 0x1905,
  61                radeon_pm_d2, NULL),
  62         BUGFIX("IBM Thinkpad R40",
  63                PCI_VENDOR_ID_IBM, 0x0526,
  64                radeon_pm_d2, NULL),
  65         BUGFIX("IBM Thinkpad R40",
  66                PCI_VENDOR_ID_IBM, 0x0527,
  67                radeon_pm_d2, NULL),
  68         BUGFIX("IBM Thinkpad R50/R51/T40/T41",
  69                PCI_VENDOR_ID_IBM, 0x0531,
  70                radeon_pm_d2, NULL),
  71         BUGFIX("IBM Thinkpad R51/T40/T41/T42",
  72                PCI_VENDOR_ID_IBM, 0x0530,
  73                radeon_pm_d2, NULL),
  74         BUGFIX("IBM Thinkpad T30",
  75                PCI_VENDOR_ID_IBM, 0x0517,
  76                radeon_pm_d2, NULL),
  77         BUGFIX("IBM Thinkpad T40p",
  78                PCI_VENDOR_ID_IBM, 0x054d,
  79                radeon_pm_d2, NULL),
  80         BUGFIX("IBM Thinkpad T42",
  81                PCI_VENDOR_ID_IBM, 0x0550,
  82                radeon_pm_d2, NULL),
  83         BUGFIX("IBM Thinkpad X31/X32",
  84                PCI_VENDOR_ID_IBM, 0x052f,
  85                radeon_pm_d2, NULL),
  86         BUGFIX("Samsung P35",
  87                PCI_VENDOR_ID_SAMSUNG, 0xc00c,
  88                radeon_pm_off, radeon_reinitialize_M10),
  89         { .ident = NULL }
  90 };
  91
  92 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
  93 {
  94         struct radeon_device_id *id;
  95
  96         for (id = radeon_workaround_list; id->ident != NULL; id++ )
  97                 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
  98                     (id->subsystem_device == rinfo->pdev->subsystem_device )) {
  99
 100                         /* we found a device that requires workaround */
 101                         printk(KERN_DEBUG "radeonfb: %s detected"
 102                                ", enabling workaround\n", id->ident);
 103
 104                         rinfo->pm_mode |= id->pm_mode_modifier;
 105
 106                         if (id->new_reinit_func != NULL)
 107                                 rinfo->reinit_func = id->new_reinit_func;
 108
 109                         return 1;
 110                 }
 111         return 0;  /* not found */
 112 }
 113
 114 #else  /* defined(CONFIG_PM) && defined(CONFIG_X86) */
 115 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
 116 {
 117         return 0;
 118 }
 119 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
 120
 121
 122
 123 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
 124 {
 125         u32 tmp;
 126
 127         /* RV100 */
 128         if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
 129                 if (rinfo->has_CRTC2) {
 130                         tmp = INPLL(pllSCLK_CNTL);
 131                         tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
 132                         tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
 133                         OUTPLL(pllSCLK_CNTL, tmp);
 134                 }
 135                 tmp = INPLL(pllMCLK_CNTL);
 136                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 137                         MCLK_CNTL__FORCE_MCLKB |
 138                         MCLK_CNTL__FORCE_YCLKA |
 139                         MCLK_CNTL__FORCE_YCLKB |
 140                         MCLK_CNTL__FORCE_AIC |
 141                         MCLK_CNTL__FORCE_MC);
 142                 OUTPLL(pllMCLK_CNTL, tmp);
 143                 return;
 144         }
 145         /* R100 */
 146         if (!rinfo->has_CRTC2) {
 147                 tmp = INPLL(pllSCLK_CNTL);
 148                 tmp |= (SCLK_CNTL__FORCE_CP     | SCLK_CNTL__FORCE_HDP  |
 149                         SCLK_CNTL__FORCE_DISP1  | SCLK_CNTL__FORCE_TOP  |
 150                         SCLK_CNTL__FORCE_E2     | SCLK_CNTL__FORCE_SE   |
 151                         SCLK_CNTL__FORCE_IDCT   | SCLK_CNTL__FORCE_VIP  |
 152                         SCLK_CNTL__FORCE_RE     | SCLK_CNTL__FORCE_PB   |
 153                         SCLK_CNTL__FORCE_TAM    | SCLK_CNTL__FORCE_TDM  |
 154                         SCLK_CNTL__FORCE_RB);
 155                 OUTPLL(pllSCLK_CNTL, tmp);
 156                 return;
 157         }
 158         /* RV350 (M10/M11) */
 159         if (rinfo->family == CHIP_FAMILY_RV350) {
 160                 /* for RV350/M10/M11, no delays are required. */
 161                 tmp = INPLL(pllSCLK_CNTL2);
 162                 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
 163                         SCLK_CNTL2__R300_FORCE_GA  |
 164                         SCLK_CNTL2__R300_FORCE_CBA);
 165                 OUTPLL(pllSCLK_CNTL2, tmp);
 166
 167                 tmp = INPLL(pllSCLK_CNTL);
 168                 tmp |= (SCLK_CNTL__FORCE_DISP2          | SCLK_CNTL__FORCE_CP           |
 169                         SCLK_CNTL__FORCE_HDP            | SCLK_CNTL__FORCE_DISP1        |
 170                         SCLK_CNTL__FORCE_TOP            | SCLK_CNTL__FORCE_E2           |
 171                         SCLK_CNTL__R300_FORCE_VAP       | SCLK_CNTL__FORCE_IDCT         |
 172                         SCLK_CNTL__FORCE_VIP            | SCLK_CNTL__R300_FORCE_SR      |
 173                         SCLK_CNTL__R300_FORCE_PX        | SCLK_CNTL__R300_FORCE_TX      |
 174                         SCLK_CNTL__R300_FORCE_US        | SCLK_CNTL__FORCE_TV_SCLK      |
 175                         SCLK_CNTL__R300_FORCE_SU        | SCLK_CNTL__FORCE_OV0);
 176                 OUTPLL(pllSCLK_CNTL, tmp);
 177
 178                 tmp = INPLL(pllSCLK_MORE_CNTL);
 179                 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS  | SCLK_MORE_CNTL__FORCE_MC_GUI  |
 180                         SCLK_MORE_CNTL__FORCE_MC_HOST);
 181                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 182
 183                 tmp = INPLL(pllMCLK_CNTL);
 184                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 185                         MCLK_CNTL__FORCE_MCLKB |
 186                         MCLK_CNTL__FORCE_YCLKA |
 187                         MCLK_CNTL__FORCE_YCLKB |
 188                         MCLK_CNTL__FORCE_MC);
 189                 OUTPLL(pllMCLK_CNTL, tmp);
 190
 191                 tmp = INPLL(pllVCLK_ECP_CNTL);
 192                 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb  |
 193                          VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
 194                          VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
 195                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 196
 197                 tmp = INPLL(pllPIXCLKS_CNTL);
 198                 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb               |
 199                          PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb           |
 200                          PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb  |
 201                          PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb           |
 202                          PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb          |
 203                          PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb             |
 204                          PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb       |
 205                          PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb           |
 206                          PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb           |
 207                          PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb     |
 208                          PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb       |
 209                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 210                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 211                          PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
 212                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 213
 214                 return;
 215         }
 216
 217         /* Default */
 218
 219         /* Force Core Clocks */
 220         tmp = INPLL(pllSCLK_CNTL);
 221         tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
 222
 223         /* XFree doesn't do that case, but we had this code from Apple and it
 224          * seem necessary for proper suspend/resume operations
 225          */
 226         if (rinfo->is_mobility) {
 227                 tmp |=  SCLK_CNTL__FORCE_HDP|
 228                         SCLK_CNTL__FORCE_DISP1|
 229                         SCLK_CNTL__FORCE_DISP2|
 230                         SCLK_CNTL__FORCE_TOP|
 231                         SCLK_CNTL__FORCE_SE|
 232                         SCLK_CNTL__FORCE_IDCT|
 233                         SCLK_CNTL__FORCE_VIP|
 234                         SCLK_CNTL__FORCE_PB|
 235                         SCLK_CNTL__FORCE_RE|
 236                         SCLK_CNTL__FORCE_TAM|
 237                         SCLK_CNTL__FORCE_TDM|
 238                         SCLK_CNTL__FORCE_RB|
 239                         SCLK_CNTL__FORCE_TV_SCLK|
 240                         SCLK_CNTL__FORCE_SUBPIC|
 241                         SCLK_CNTL__FORCE_OV0;
 242         }
 243         else if (rinfo->family == CHIP_FAMILY_R300 ||
 244                    rinfo->family == CHIP_FAMILY_R350) {
 245                 tmp |=  SCLK_CNTL__FORCE_HDP   |
 246                         SCLK_CNTL__FORCE_DISP1 |
 247                         SCLK_CNTL__FORCE_DISP2 |
 248                         SCLK_CNTL__FORCE_TOP   |
 249                         SCLK_CNTL__FORCE_IDCT  |
 250                         SCLK_CNTL__FORCE_VIP;
 251         }
 252         OUTPLL(pllSCLK_CNTL, tmp);
 253         radeon_msleep(16);
 254
 255         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 256                 tmp = INPLL(pllSCLK_CNTL2);
 257                 tmp |=  SCLK_CNTL2__R300_FORCE_TCL |
 258                         SCLK_CNTL2__R300_FORCE_GA  |
 259                         SCLK_CNTL2__R300_FORCE_CBA;
 260                 OUTPLL(pllSCLK_CNTL2, tmp);
 261                 radeon_msleep(16);
 262         }
 263
 264         tmp = INPLL(pllCLK_PIN_CNTL);
 265         tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 266         OUTPLL(pllCLK_PIN_CNTL, tmp);
 267         radeon_msleep(15);
 268
 269         if (rinfo->is_IGP) {
 270                 /* Weird  ... X is _un_ forcing clocks here, I think it's
 271                  * doing backward. Imitate it for now...
 272                  */
 273                 tmp = INPLL(pllMCLK_CNTL);
 274                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 275                          MCLK_CNTL__FORCE_YCLKA);
 276                 OUTPLL(pllMCLK_CNTL, tmp);
 277                 radeon_msleep(16);
 278         }
 279         /* Hrm... same shit, X doesn't do that but I have to */
 280         else if (rinfo->is_mobility) {
 281                 tmp = INPLL(pllMCLK_CNTL);
 282                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 283                         MCLK_CNTL__FORCE_MCLKB |
 284                         MCLK_CNTL__FORCE_YCLKA |
 285                         MCLK_CNTL__FORCE_YCLKB);
 286                 OUTPLL(pllMCLK_CNTL, tmp);
 287                 radeon_msleep(16);
 288
 289                 tmp = INPLL(pllMCLK_MISC);
 290                 tmp &=  ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 291                           MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 292                           MCLK_MISC__MC_MCLK_DYN_ENABLE|
 293                           MCLK_MISC__IO_MCLK_DYN_ENABLE);
 294                 OUTPLL(pllMCLK_MISC, tmp);
 295                 radeon_msleep(15);
 296         }
 297
 298         if (rinfo->is_mobility) {
 299                 tmp = INPLL(pllSCLK_MORE_CNTL);
 300                 tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS|
 301                         SCLK_MORE_CNTL__FORCE_MC_GUI|
 302                         SCLK_MORE_CNTL__FORCE_MC_HOST;
 303                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 304                 radeon_msleep(16);
 305         }
 306
 307         tmp = INPLL(pllPIXCLKS_CNTL);
 308         tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 309                  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 310                  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 311                  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 312                  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 313                  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 314                  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 315         OUTPLL(pllPIXCLKS_CNTL, tmp);
 316         radeon_msleep(16);
 317
 318         tmp = INPLL( pllVCLK_ECP_CNTL);
 319         tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 320                  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 321         OUTPLL( pllVCLK_ECP_CNTL, tmp);
 322         radeon_msleep(16);
 323 }
 324
 325 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
 326 {
 327         u32 tmp;
 328
 329         /* R100 */
 330         if (!rinfo->has_CRTC2) {
 331                 tmp = INPLL(pllSCLK_CNTL);
 332
 333                 if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
 334                     tmp &= ~(SCLK_CNTL__FORCE_CP        | SCLK_CNTL__FORCE_RB);
 335                 tmp &= ~(SCLK_CNTL__FORCE_HDP           | SCLK_CNTL__FORCE_DISP1 |
 336                          SCLK_CNTL__FORCE_TOP           | SCLK_CNTL__FORCE_SE   |
 337                          SCLK_CNTL__FORCE_IDCT          | SCLK_CNTL__FORCE_RE   |
 338                          SCLK_CNTL__FORCE_PB            | SCLK_CNTL__FORCE_TAM  |
 339                          SCLK_CNTL__FORCE_TDM);
 340                 OUTPLL(pllSCLK_CNTL, tmp);
 341                 return;
 342         }
 343
 344         /* M10/M11 */
 345         if (rinfo->family == CHIP_FAMILY_RV350) {
 346                 tmp = INPLL(pllSCLK_CNTL2);
 347                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 348                          SCLK_CNTL2__R300_FORCE_GA  |
 349                          SCLK_CNTL2__R300_FORCE_CBA);
 350                 tmp |=  (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
 351                          SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT  |
 352                          SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
 353                 OUTPLL(pllSCLK_CNTL2, tmp);
 354
 355                 tmp = INPLL(pllSCLK_CNTL);
 356                 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP      |
 357                          SCLK_CNTL__FORCE_HDP   | SCLK_CNTL__FORCE_DISP1   |
 358                          SCLK_CNTL__FORCE_TOP   | SCLK_CNTL__FORCE_E2      |
 359                          SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
 360                          SCLK_CNTL__FORCE_VIP   | SCLK_CNTL__R300_FORCE_SR |
 361                          SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
 362                          SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
 363                          SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
 364                 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
 365                 OUTPLL(pllSCLK_CNTL, tmp);
 366
 367                 tmp = INPLL(pllSCLK_MORE_CNTL);
 368                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 369                 tmp |=  SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
 370                         SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
 371                         SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
 372                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 373
 374                 tmp = INPLL(pllVCLK_ECP_CNTL);
 375                 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 376                         VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 377                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 378
 379                 tmp = INPLL(pllPIXCLKS_CNTL);
 380                 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb         |
 381                         PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb     |
 382                         PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
 383                         PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            |
 384                         PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb    |
 385                         PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb       |
 386                         PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        |
 387                         PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb     |
 388                         PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb     |
 389                         PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      |
 390                         PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        |
 391                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           |
 392                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
 393                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 394
 395                 tmp = INPLL(pllMCLK_MISC);
 396                 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
 397                         MCLK_MISC__IO_MCLK_DYN_ENABLE);
 398                 OUTPLL(pllMCLK_MISC, tmp);
 399
 400                 tmp = INPLL(pllMCLK_CNTL);
 401                 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
 402                 tmp &= ~(MCLK_CNTL__FORCE_YCLKA  |
 403                          MCLK_CNTL__FORCE_YCLKB  |
 404                          MCLK_CNTL__FORCE_MC);
 405
 406                 /* Some releases of vbios have set DISABLE_MC_MCLKA
 407                  * and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
 408                  * bits will cause H/W hang when reading video memory with dynamic
 409                  * clocking enabled.
 410                  */
 411                 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
 412                     (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
 413                         /* If both bits are set, then check the active channels */
 414                         tmp = INPLL(pllMCLK_CNTL);
 415                         if (rinfo->vram_width == 64) {
 416                             if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
 417                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
 418                             else
 419                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
 420                         } else {
 421                             tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
 422                                      MCLK_CNTL__R300_DISABLE_MC_MCLKB);
 423                         }
 424                 }
 425                 OUTPLL(pllMCLK_CNTL, tmp);
 426                 return;
 427         }
 428
 429         /* R300 */
 430         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 431                 tmp = INPLL(pllSCLK_CNTL);
 432                 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
 433                 tmp |= SCLK_CNTL__FORCE_CP;
 434                 OUTPLL(pllSCLK_CNTL, tmp);
 435                 radeon_msleep(15);
 436
 437                 tmp = INPLL(pllSCLK_CNTL2);
 438                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 439                          SCLK_CNTL2__R300_FORCE_GA  |
 440                          SCLK_CNTL2__R300_FORCE_CBA);
 441                 OUTPLL(pllSCLK_CNTL2, tmp);
 442         }
 443
 444         /* Others */
 445
 446         tmp = INPLL( pllCLK_PWRMGT_CNTL);
 447         tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 448                  CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
 449                  CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
 450         tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
 451                (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
 452         OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
 453         radeon_msleep(15);
 454
 455         tmp = INPLL(pllCLK_PIN_CNTL);
 456         tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 457         OUTPLL(pllCLK_PIN_CNTL, tmp);
 458         radeon_msleep(15);
 459
 460         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
 461          * to lockup randomly, leave them as set by BIOS.
 462          */
 463         tmp = INPLL(pllSCLK_CNTL);
 464         tmp &= ~SCLK_CNTL__FORCEON_MASK;
 465
 466         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
 467         if ((rinfo->family == CHIP_FAMILY_RV250 &&
 468              ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
 469             ((rinfo->family == CHIP_FAMILY_RV100) &&
 470              ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
 471                 tmp |= SCLK_CNTL__FORCE_CP;
 472                 tmp |= SCLK_CNTL__FORCE_VIP;
 473         }
 474         OUTPLL(pllSCLK_CNTL, tmp);
 475         radeon_msleep(15);
 476
 477         if ((rinfo->family == CHIP_FAMILY_RV200) ||
 478             (rinfo->family == CHIP_FAMILY_RV250) ||
 479             (rinfo->family == CHIP_FAMILY_RV280)) {
 480                 tmp = INPLL(pllSCLK_MORE_CNTL);
 481                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 482
 483                 /* RV200::A11 A12 RV250::A11 A12 */
 484                 if (((rinfo->family == CHIP_FAMILY_RV200) ||
 485                      (rinfo->family == CHIP_FAMILY_RV250)) &&
 486                     ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
 487                         tmp |= SCLK_MORE_CNTL__FORCEON;
 488
 489                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 490                 radeon_msleep(15);
 491         }
 492
 493
 494         /* RV200::A11 A12, RV250::A11 A12 */
 495         if (((rinfo->family == CHIP_FAMILY_RV200) ||
 496              (rinfo->family == CHIP_FAMILY_RV250)) &&
 497             ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
 498                 tmp = INPLL(pllPLL_PWRMGT_CNTL);
 499                 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
 500                 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
 501                 radeon_msleep(15);
 502         }
 503
 504         tmp = INPLL(pllPIXCLKS_CNTL);
 505         tmp |=  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
 506                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
 507                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 508                 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
 509                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
 510                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 511                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
 512         OUTPLL(pllPIXCLKS_CNTL, tmp);
 513         radeon_msleep(15);
 514
 515         tmp = INPLL(pllVCLK_ECP_CNTL);
 516         tmp |=  VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 517                 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
 518         OUTPLL(pllVCLK_ECP_CNTL, tmp);
 519
 520         /* X doesn't do that ... hrm, we do on mobility && Macs */
 521 #ifdef CONFIG_PPC_OF
 522         if (rinfo->is_mobility) {
 523                 tmp  = INPLL(pllMCLK_CNTL);
 524                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 525                          MCLK_CNTL__FORCE_MCLKB |
 526                          MCLK_CNTL__FORCE_YCLKA |
 527                          MCLK_CNTL__FORCE_YCLKB);
 528                 OUTPLL(pllMCLK_CNTL, tmp);
 529                 radeon_msleep(15);
 530
 531                 tmp = INPLL(pllMCLK_MISC);
 532                 tmp |=  MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 533                         MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 534                         MCLK_MISC__MC_MCLK_DYN_ENABLE|
 535                         MCLK_MISC__IO_MCLK_DYN_ENABLE;
 536                 OUTPLL(pllMCLK_MISC, tmp);
 537                 radeon_msleep(15);
 538         }
 539 #endif /* CONFIG_PPC_OF */
 540 }
 541
 542 #ifdef CONFIG_PM
 543
 544 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
 545 {
 546         OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
 547         OUTREG( MC_IND_DATA, value);
 548 }
 549
 550 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
 551 {
 552         OUTREG( MC_IND_INDEX, indx);
 553         return INREG( MC_IND_DATA);
 554 }
 555
 556 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
 557 {
 558         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
 559         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
 560         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
 561         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
 562         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
 563         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
 564         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
 565         rinfo->save_regs[7] = INPLL(MCLK_MISC);
 566         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
 567
 568         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
 569         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
 570         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
 571         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
 572         rinfo->save_regs[14] = INREG(BUS_CNTL1);
 573         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
 574         rinfo->save_regs[16] = INREG(AGP_CNTL);
 575         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 576         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 577         rinfo->save_regs[19] = INREG(GPIOPAD_A);
 578         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
 579         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
 580         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
 581         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
 582         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
 583         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
 584         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
 585         rinfo->save_regs[27] = INREG(GPIO_MONID);
 586         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
 587
 588         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
 589         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
 590         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
 591         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
 592         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
 593
 594         rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
 595         rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
 596         rinfo->save_regs[36] = INREG(BUS_CNTL);
 597         rinfo->save_regs[39] = INREG(RBBM_CNTL);
 598         rinfo->save_regs[40] = INREG(DAC_CNTL);
 599         rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
 600         rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
 601         rinfo->save_regs[38] = INREG(FCP_CNTL);
 602
 603         if (rinfo->is_mobility) {
 604                 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
 605                 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
 606                 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
 607                 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
 608                 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
 609                 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
 610                 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
 611         }
 612
 613         if (rinfo->family >= CHIP_FAMILY_RV200) {
 614                 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
 615                 rinfo->save_regs[46] = INREG(MC_CNTL);
 616                 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
 617                 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
 618                 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
 619                 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
 620                 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
 621                 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
 622                 rinfo->save_regs[53] = INREG(MC_DEBUG);
 623         }
 624         rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
 625         rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
 626         rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
 627         rinfo->save_regs[57] = INREG(FW_CNTL);
 628
 629         if (rinfo->family >= CHIP_FAMILY_R300) {
 630                 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
 631                 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
 632                 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
 633                 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
 634                 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
 635                 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
 636                 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
 637                 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
 638                 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
 639                 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
 640                 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
 641                 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
 642                 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
 643                 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
 644                 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
 645                 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
 646         } else {
 647                 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
 648                 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
 649                 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
 650                 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
 651                 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
 652                 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
 653         }
 654
 655         rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
 656         rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
 657         rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
 658         rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
 659         rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
 660         rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
 661         rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
 662
 663         rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
 664         rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
 665         rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
 666         rinfo->save_regs[84] = INREG(TMDS_CNTL);
 667         rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
 668         rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
 669         rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
 670         rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
 671         rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
 672         rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
 673         rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
 674         rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
 675         rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
 676         rinfo->save_regs[96] = INREG(HDP_DEBUG);
 677         rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
 678         rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
 679         rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
 680 }
 681
 682 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
 683 {
 684         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
 685
 686         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
 687         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
 688         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
 689         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
 690         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
 691         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
 692         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
 693         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
 694         if (rinfo->family == CHIP_FAMILY_RV350)
 695                 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
 696
 697         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
 698         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
 699         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
 700         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
 701         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
 702         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
 703
 704         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
 705         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
 706         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
 707         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
 708         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
 709         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
 710         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
 711         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
 712         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
 713         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
 714         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
 715
 716         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
 717         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
 718         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
 719         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
 720         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
 721         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
 722         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
 723         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
 724         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
 725         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
 726 }
 727
 728 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
 729 {
 730         OUTREG(GPIOPAD_MASK, 0x0001ffff);
 731         OUTREG(GPIOPAD_EN, 0x00000400);
 732         OUTREG(GPIOPAD_A, 0x00000000);
 733         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
 734         OUTREG(ZV_LCDPAD_EN, 0x00000000);
 735         OUTREG(ZV_LCDPAD_A, 0x00000000);
 736         OUTREG(GPIO_VGA_DDC, 0x00030000);
 737         OUTREG(GPIO_DVI_DDC, 0x00000000);
 738         OUTREG(GPIO_MONID, 0x00030000);
 739         OUTREG(GPIO_CRT2_DDC, 0x00000000);
 740 }
 741
 742 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
 743 {
 744         /* Set v2clk to 65MHz */
 745         if (rinfo->family <= CHIP_FAMILY_RV280) {
 746                 OUTPLL(pllPIXCLKS_CNTL,
 747                          __INPLL(rinfo, pllPIXCLKS_CNTL)
 748                          & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
 749
 750                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 751                 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
 752         } else {
 753                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 754                 INPLL(pllP2PLL_REF_DIV);
 755                 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
 756         }
 757
 758         OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
 759
 760         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
 761         mdelay(1);
 762
 763         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
 764         mdelay( 1);
 765
 766         OUTPLL(pllPIXCLKS_CNTL,
 767                 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
 768                 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
 769         mdelay( 1);
 770 }
 771
 772 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
 773 {
 774         u32 reg;
 775
 776         reg  = INREG(BUS_CNTL1);
 777         if (rinfo->family <= CHIP_FAMILY_RV280) {
 778                 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
 779                 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
 780         } else {
 781                 reg |= 0x4080;
 782         }
 783         OUTREG(BUS_CNTL1, reg);
 784
 785         reg  = INPLL(PLL_PWRMGT_CNTL);
 786         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
 787                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
 788         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
 789         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
 790         OUTPLL(PLL_PWRMGT_CNTL, reg);
 791
 792         reg  = INREG(TV_DAC_CNTL);
 793         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
 794         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
 795                 TV_DAC_CNTL_BDACPD |
 796                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
 797         OUTREG(TV_DAC_CNTL, reg);
 798
 799         reg  = INREG(TMDS_TRANSMITTER_CNTL);
 800         reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
 801         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
 802
 803         reg = INREG(DAC_CNTL);
 804         reg &= ~DAC_CMP_EN;
 805         OUTREG(DAC_CNTL, reg);
 806
 807         reg = INREG(DAC_CNTL2);
 808         reg &= ~DAC2_CMP_EN;
 809         OUTREG(DAC_CNTL2, reg);
 810
 811         reg  = INREG(TV_DAC_CNTL);
 812         reg &= ~TV_DAC_CNTL_DETECT;
 813         OUTREG(TV_DAC_CNTL, reg);
 814 }
 815
 816 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
 817 {
 818
 819         u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
 820
 821         u32 pll_pwrmgt_cntl;
 822         u32 clk_pwrmgt_cntl;
 823         u32 clk_pin_cntl;
 824         u32 vclk_ecp_cntl;
 825         u32 pixclks_cntl;
 826         u32 disp_mis_cntl;
 827         u32 disp_pwr_man;
 828         u32 tmp;
 829
 830         /* Force Core Clocks */
 831         sclk_cntl = INPLL( pllSCLK_CNTL);
 832         sclk_cntl |=    SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
 833                         SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
 834                         SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
 835                         SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
 836                         SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
 837                         SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
 838                         SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
 839
 840                         SCLK_CNTL__FORCE_DISP2|
 841                         SCLK_CNTL__FORCE_CP|
 842                         SCLK_CNTL__FORCE_HDP|
 843                         SCLK_CNTL__FORCE_DISP1|
 844                         SCLK_CNTL__FORCE_TOP|
 845                         SCLK_CNTL__FORCE_E2|
 846                         SCLK_CNTL__FORCE_SE|
 847                         SCLK_CNTL__FORCE_IDCT|
 848                         SCLK_CNTL__FORCE_VIP|
 849
 850                         SCLK_CNTL__FORCE_PB|
 851                         SCLK_CNTL__FORCE_TAM|
 852                         SCLK_CNTL__FORCE_TDM|
 853                         SCLK_CNTL__FORCE_RB|
 854                         SCLK_CNTL__FORCE_TV_SCLK|
 855                         SCLK_CNTL__FORCE_SUBPIC|
 856                         SCLK_CNTL__FORCE_OV0;
 857         if (rinfo->family <= CHIP_FAMILY_RV280)
 858                 sclk_cntl |= SCLK_CNTL__FORCE_RE;
 859         else
 860                 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
 861                         SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
 862                         SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
 863                         SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
 864                         SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
 865
 866         OUTPLL( pllSCLK_CNTL, sclk_cntl);
 867
 868         sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
 869         sclk_more_cntl |=       SCLK_MORE_CNTL__FORCE_DISPREGS |
 870                                 SCLK_MORE_CNTL__FORCE_MC_GUI |
 871                                 SCLK_MORE_CNTL__FORCE_MC_HOST;
 872
 873         OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
 874
 875
 876         mclk_cntl = INPLL( pllMCLK_CNTL);
 877         mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
 878                         MCLK_CNTL__FORCE_MCLKB |
 879                         MCLK_CNTL__FORCE_YCLKA |
 880                         MCLK_CNTL__FORCE_YCLKB |
 881                         MCLK_CNTL__FORCE_MC
 882                       );
 883         OUTPLL( pllMCLK_CNTL, mclk_cntl);
 884
 885         /* Force Display clocks */
 886         vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
 887         vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
 888                            | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 889         vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
 890         OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
 891
 892
 893         pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
 894         pixclks_cntl &= ~(      PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 895                                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 896                                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 897                                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 898                                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 899                                 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 900                                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 901
 902         OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
 903
 904         /* Switch off LVDS interface */
 905         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
 906                ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
 907
 908         /* Enable System power management */
 909         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
 910
 911         pll_pwrmgt_cntl |=      PLL_PWRMGT_CNTL__SPLL_TURNOFF |
 912                                 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
 913                                 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
 914                                 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
 915                                 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
 916
 917         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
 918
 919         clk_pwrmgt_cntl  = INPLL( pllCLK_PWRMGT_CNTL);
 920
 921         clk_pwrmgt_cntl &= ~(   CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
 922                                 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
 923                                 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
 924                                 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
 925                                 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
 926                                 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
 927                                 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
 928                                 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
 929                                 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
 930                                 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
 931                                 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
 932                                 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 933                                 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
 934                         );
 935
 936         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
 937                 | CLK_PWRMGT_CNTL__DISP_PM;
 938
 939         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
 940
 941         clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
 942
 943         clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
 944
 945         /* because both INPLL and OUTPLL take the same lock, that's why. */
 946         tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
 947         OUTPLL( pllMCLK_MISC, tmp);
 948
 949         /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
 950          * and radeon chip dependent. Thus we only enable it on Mac for
 951          * now (until we get more info on how to compute the correct
 952          * value for various X86 bridges).
 953          */
 954 #ifdef CONFIG_PPC_PMAC
 955         if (machine_is(powermac)) {
 956                 /* AGP PLL control */
 957                 if (rinfo->family <= CHIP_FAMILY_RV280) {
 958                         OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) |  BUS_CNTL1__AGPCLK_VALID);
 959                         OUTREG(BUS_CNTL1,
 960                                (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
 961                                | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT));   // 440BX
 962                 } else {
 963                         OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
 964                         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
 965                 }
 966         }
 967 #endif
 968
 969         OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
 970                                   & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
 971
 972         clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
 973         clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
 974         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
 975
 976         /* Solano2M */
 977         OUTREG(AGP_CNTL,
 978                 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
 979                 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
 980
 981         /* ACPI mode */
 982         /* because both INPLL and OUTPLL take the same lock, that's why. */
 983         tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
 984         OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
 985
 986
 987         disp_mis_cntl = INREG(DISP_MISC_CNTL);
 988
 989         disp_mis_cntl &= ~(     DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
 990                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
 991                                 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
 992                                 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
 993                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
 994                                 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
 995                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
 996                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
 997                                 DISP_MISC_CNTL__SOFT_RESET_LVDS|
 998                                 DISP_MISC_CNTL__SOFT_RESET_TMDS|
 999                                 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1000                                 DISP_MISC_CNTL__SOFT_RESET_TV);
1001
1002         OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1003
1004         disp_pwr_man = INREG(DISP_PWR_MAN);
1005
1006         disp_pwr_man &= ~(      DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN   |
1007                                 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1008                                 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1009                                 DISP_PWR_MAN__DISP_D3_RST|
1010                                 DISP_PWR_MAN__DISP_D3_REG_RST
1011                                 );
1012
1013         disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1014                                         DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1015                                         DISP_PWR_MAN__DISP_D3_OV0_RST|
1016                                         DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1017                                         DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1018                                         DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1019                                         DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1020                                         DISP_PWR_MAN__TV_ENABLE_RST|
1021 //                                      DISP_PWR_MAN__AUTO_PWRUP_EN|
1022                                         0;
1023
1024         OUTREG(DISP_PWR_MAN, disp_pwr_man);
1025
1026         clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1027         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1028         clk_pin_cntl    = INPLL( pllCLK_PIN_CNTL);
1029         disp_pwr_man    = INREG(DISP_PWR_MAN);
1030
1031
1032         /* D2 */
1033         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1034         pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1035         clk_pin_cntl    |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1036         disp_pwr_man    &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1037                              | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1038
1039         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1040         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1041         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1042         OUTREG(DISP_PWR_MAN, disp_pwr_man);
1043
1044         /* disable display request & disable display */
1045         OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1046                 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1047         OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1048                 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1049
1050         mdelay(17);
1051
1052 }
1053
1054 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1055 {
1056         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1057
1058         mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1059                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1060         mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1061                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1062
1063         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1064                | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1065         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1066                | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1067
1068         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1069         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1070
1071         mdelay( 1);
1072 }
1073
1074 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1075 {
1076         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1077
1078         mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1079                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1080         mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1081                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1082
1083         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1084                mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1085         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1086                mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1087
1088         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1089         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1090
1091         mdelay( 1);
1092 }
1093
1094 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1095                                        u8 delay_required)
1096 {
1097         u32 mem_sdram_mode;
1098
1099         mem_sdram_mode  = INREG( MEM_SDRAM_MODE_REG);
1100
1101         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1102         mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1103                 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1104         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1105         if (delay_required >= 2)
1106                 mdelay(1);
1107
1108         mem_sdram_mode |=  MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1109         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1110         if (delay_required >= 2)
1111                 mdelay(1);
1112
1113         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1114         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1115         if (delay_required >= 2)
1116                 mdelay(1);
1117
1118         if (delay_required) {
1119                 do {
1120                         if (delay_required >= 2)
1121                                 mdelay(1);
1122                 } while ((INREG(MC_STATUS)
1123                           & (MC_STATUS__MEM_PWRUP_COMPL_A |
1124                              MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1125         }
1126 }
1127
1128 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1129 {
1130         int cnt;
1131
1132         for (cnt = 0; cnt < 100; ++cnt) {
1133                 mdelay(1);
1134                 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1135                                         | MC_STATUS__MEM_PWRUP_COMPL_B))
1136                         break;
1137         }
1138 }
1139
1140
1141 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1142 {
1143 #define DLL_RESET_DELAY         5
1144 #define DLL_SLEEP_DELAY         1
1145
1146         u32 cko = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP
1147                 | MDLL_CKO__MCKOA_RESET;
1148         u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1149                 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1150                 | MDLL_RDCKA__MRDCKA1_RESET;
1151         u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1152                 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1153                 | MDLL_RDCKB__MRDCKB1_RESET;
1154
1155         /* Setting up the DLL range for write */
1156         OUTPLL(pllMDLL_CKO,     cko);
1157         OUTPLL(pllMDLL_RDCKA,   cka);
1158         OUTPLL(pllMDLL_RDCKB,   ckb);
1159
1160         mdelay(DLL_RESET_DELAY*2);
1161
1162         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1163         OUTPLL(pllMDLL_CKO, cko);
1164         mdelay(DLL_SLEEP_DELAY);
1165         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1166         OUTPLL(pllMDLL_CKO, cko);
1167         mdelay(DLL_RESET_DELAY);
1168
1169         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1170         OUTPLL(pllMDLL_RDCKA, cka);
1171         mdelay(DLL_SLEEP_DELAY);
1172         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1173         OUTPLL(pllMDLL_RDCKA, cka);
1174         mdelay(DLL_RESET_DELAY);
1175
1176         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1177         OUTPLL(pllMDLL_RDCKB, ckb);
1178         mdelay(DLL_SLEEP_DELAY);
1179         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1180         OUTPLL(pllMDLL_RDCKB, ckb);
1181         mdelay(DLL_RESET_DELAY);
1182
1183
1184 #undef DLL_RESET_DELAY
1185 #undef DLL_SLEEP_DELAY
1186 }
1187
1188 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1189 {
1190         u32 dll_value;
1191         u32 dll_sleep_mask = 0;
1192         u32 dll_reset_mask = 0;
1193         u32 mc;
1194
1195 #define DLL_RESET_DELAY         5
1196 #define DLL_SLEEP_DELAY         1
1197
1198         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1199         mc = INREG(MC_CNTL);
1200         /* Check which channels are enabled */
1201         switch (mc & 0x3) {
1202         case 1:
1203                 if (mc & 0x4)
1204                         break;
1205         case 2:
1206                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1207                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1208         case 0:
1209                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1210                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1211         }
1212         switch (mc & 0x3) {
1213         case 1:
1214                 if (!(mc & 0x4))
1215                         break;
1216         case 2:
1217                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1218                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1219                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1220                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1221         }
1222
1223         dll_value = INPLL(pllMDLL_RDCKA);
1224
1225         /* Power Up */
1226         dll_value &= ~(dll_sleep_mask);
1227         OUTPLL(pllMDLL_RDCKA, dll_value);
1228         mdelay( DLL_SLEEP_DELAY);
1229
1230         dll_value &= ~(dll_reset_mask);
1231         OUTPLL(pllMDLL_RDCKA, dll_value);
1232         mdelay( DLL_RESET_DELAY);
1233
1234 #undef DLL_RESET_DELAY
1235 #undef DLL_SLEEP_DELAY
1236 }
1237
1238
1239 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1240 {
1241         u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1242                 fp_gen_cntl, fp2_gen_cntl;
1243
1244         crtcGenCntl  = INREG( CRTC_GEN_CNTL);
1245         crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1246
1247         crtc_more_cntl  = INREG( CRTC_MORE_CNTL);
1248         fp_gen_cntl     = INREG( FP_GEN_CNTL);
1249         fp2_gen_cntl    = INREG( FP2_GEN_CNTL);
1250
1251
1252         OUTREG( CRTC_MORE_CNTL, 0);
1253         OUTREG( FP_GEN_CNTL, 0);
1254         OUTREG( FP2_GEN_CNTL,0);
1255
1256         OUTREG( CRTC_GEN_CNTL,  (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1257         OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1258
1259         /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1260         if (rinfo->family == CHIP_FAMILY_RV350) {
1261                 u32 sdram_mode_reg = rinfo->save_regs[35];
1262                 static u32 default_mrtable[] =
1263                         { 0x21320032,
1264                           0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1265                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1266                           0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1267                           0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1268                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1269                           0x31320032 };
1270
1271                 const u32 *mrtable = default_mrtable;
1272                 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1273
1274                 mdelay(30);
1275
1276                 /* Disable refresh */
1277                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1278                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1279                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1280                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1281
1282                 /* Configure and enable M & SPLLs */
1283                 radeon_pm_enable_dll_m10(rinfo);
1284                 radeon_pm_yclk_mclk_sync_m10(rinfo);
1285
1286 #ifdef CONFIG_PPC_OF
1287                 if (rinfo->of_node != NULL) {
1288                         int size;
1289
1290                         mrtable = get_property(rinfo->of_node, "ATY,MRT", &size);
1291                         if (mrtable)
1292                                 mrtable_size = size >> 2;
1293                         else
1294                                 mrtable = default_mrtable;
1295                 }
1296 #endif /* CONFIG_PPC_OF */
1297
1298                 /* Program the SDRAM */
1299                 sdram_mode_reg = mrtable[0];
1300                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1301                 for (i = 0; i < mrtable_size; i++) {
1302                         if (mrtable[i] == 0xffffffffu)
1303                                 radeon_pm_m10_program_mode_wait(rinfo);
1304                         else {
1305                                 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1306                                                     | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1307                                                     | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1308                                 sdram_mode_reg |= mrtable[i];
1309
1310                                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1311                                 mdelay(1);
1312                         }
1313                 }
1314
1315                 /* Restore memory refresh */
1316                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1317                 mdelay(30);
1318
1319         }
1320         /* Here come the desktop RV200 "QW" card */
1321         else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1322                 /* Disable refresh */
1323                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1324                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1325                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1326                        | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1327                 mdelay(30);
1328
1329                 /* Reset memory */
1330                 OUTREG(MEM_SDRAM_MODE_REG,
1331                        INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1332
1333                 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1334                 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1335                 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1336
1337                 OUTREG(MEM_SDRAM_MODE_REG,
1338                        INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1339
1340                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1341
1342         }
1343         /* The M6 */
1344         else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1345                 /* Disable refresh */
1346                 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1347                 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1348
1349                 /* Reset memory */
1350                 OUTREG( MEM_SDRAM_MODE_REG,
1351                         INREG( MEM_SDRAM_MODE_REG)
1352                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1353
1354                 /* DLL */
1355                 radeon_pm_enable_dll(rinfo);
1356
1357                 /* MLCK / YCLK sync */
1358                 radeon_pm_yclk_mclk_sync(rinfo);
1359
1360                 /* Program Mode Register */
1361                 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1362                 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1363                 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1364                 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1365                 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1366
1367                 /* Complete & re-enable refresh */
1368                 OUTREG( MEM_SDRAM_MODE_REG,
1369                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1370
1371                 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1372         }
1373         /* And finally, the M7..M9 models, including M9+ (RV280) */
1374         else if (rinfo->is_mobility) {
1375
1376                 /* Disable refresh */
1377                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1378                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1379                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1380                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1381
1382                 /* Reset memory */
1383                 OUTREG( MEM_SDRAM_MODE_REG,
1384                         INREG( MEM_SDRAM_MODE_REG)
1385                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1386
1387                 /* DLL */
1388                 radeon_pm_enable_dll(rinfo);
1389
1390                 /* MLCK / YCLK sync */
1391                 radeon_pm_yclk_mclk_sync(rinfo);
1392
1393                 /* M6, M7 and M9 so far ... */
1394                 if (rinfo->family <= CHIP_FAMILY_RV250) {
1395                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1396                         radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1397                         radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1398                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1399                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1400                 }
1401                 /* M9+ (iBook G4) */
1402                 else if (rinfo->family == CHIP_FAMILY_RV280) {
1403                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1404                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1405                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1406                 }
1407
1408                 /* Complete & re-enable refresh */
1409                 OUTREG( MEM_SDRAM_MODE_REG,
1410                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1411
1412                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1413         }
1414
1415         OUTREG( CRTC_GEN_CNTL,          crtcGenCntl);
1416         OUTREG( CRTC2_GEN_CNTL,         crtcGenCntl2);
1417         OUTREG( FP_GEN_CNTL,            fp_gen_cntl);
1418         OUTREG( FP2_GEN_CNTL,           fp2_gen_cntl);
1419
1420         OUTREG( CRTC_MORE_CNTL,         crtc_more_cntl);
1421
1422         mdelay( 15);
1423 }
1424
1425 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1426 {
1427         u32 tmp, tmp2;
1428         int i,j;
1429
1430         /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1431         INREG(PAD_CTLR_STRENGTH);
1432         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1433         tmp = INREG(PAD_CTLR_STRENGTH);
1434         for (i = j = 0; i < 65; ++i) {
1435                 mdelay(1);
1436                 tmp2 = INREG(PAD_CTLR_STRENGTH);
1437                 if (tmp != tmp2) {
1438                         tmp = tmp2;
1439                         i = 0;
1440                         j++;
1441                         if (j > 10) {
1442                                 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1443                                        "stabilize !\n");
1444                                 break;
1445                         }
1446                 }
1447         }
1448 }
1449
1450 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1451 {
1452         u32 tmp;
1453
1454         tmp = INPLL(pllPPLL_CNTL);
1455         OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1456         tmp = INPLL(pllP2PLL_CNTL);
1457         OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1458         tmp = INPLL(pllSPLL_CNTL);
1459         OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1460         tmp = INPLL(pllMPLL_CNTL);
1461         OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1462 }
1463
1464 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1465 {
1466         u32 tmp;
1467
1468         /* Switch SPLL to PCI source */
1469         tmp = INPLL(pllSCLK_CNTL);
1470         OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1471
1472         /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1473         tmp = INPLL(pllSPLL_CNTL);
1474         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1475         radeon_pll_errata_after_index(rinfo);
1476         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1477         radeon_pll_errata_after_data(rinfo);
1478
1479         /* Set SPLL feedback divider */
1480         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1481         tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1482         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1483
1484         /* Power up SPLL */
1485         tmp = INPLL(pllSPLL_CNTL);
1486         OUTPLL(pllSPLL_CNTL, tmp & ~1);
1487         (void)INPLL(pllSPLL_CNTL);
1488
1489         mdelay(10);
1490
1491         /* Release SPLL reset */
1492         tmp = INPLL(pllSPLL_CNTL);
1493         OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1494         (void)INPLL(pllSPLL_CNTL);
1495
1496         mdelay(10);
1497
1498         /* Select SCLK source  */
1499         tmp = INPLL(pllSCLK_CNTL);
1500         tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1501         tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1502         OUTPLL(pllSCLK_CNTL, tmp);
1503         (void)INPLL(pllSCLK_CNTL);
1504
1505         mdelay(10);
1506
1507         /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1508         tmp = INPLL(pllMPLL_CNTL);
1509         OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1510         radeon_pll_errata_after_index(rinfo);
1511         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1512         radeon_pll_errata_after_data(rinfo);
1513
1514         /* Set MPLL feedback divider */
1515         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1516         tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1517
1518         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1519         /* Power up MPLL */
1520         tmp = INPLL(pllMPLL_CNTL);
1521         OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1522         (void)INPLL(pllMPLL_CNTL);
1523
1524         mdelay(10);
1525
1526         /* Un-reset MPLL */
1527         tmp = INPLL(pllMPLL_CNTL);
1528         OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1529         (void)INPLL(pllMPLL_CNTL);
1530
1531         mdelay(10);
1532
1533         /* Select source for MCLK */
1534         tmp = INPLL(pllMCLK_CNTL);
1535         tmp |= rinfo->save_regs[2] & 0xffff;
1536         OUTPLL(pllMCLK_CNTL, tmp);
1537         (void)INPLL(pllMCLK_CNTL);
1538
1539         mdelay(10);
1540 }
1541
1542 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1543 {
1544         u32 r2ec;
1545
1546         /* GACK ! I though we didn't have a DDA on Radeon's anymore
1547          * here we rewrite with the same value, ... I suppose we clear
1548          * some bits that are already clear ? Or maybe this 0x2ec
1549          * register is something new ?
1550          */
1551         mdelay(20);
1552         r2ec = INREG(VGA_DDA_ON_OFF);
1553         OUTREG(VGA_DDA_ON_OFF, r2ec);
1554         mdelay(1);
1555
1556         /* Spread spectrum PLLL off */
1557         OUTPLL(pllSSPLL_CNTL, 0xbf03);
1558
1559         /* Spread spectrum disabled */
1560         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1561
1562         /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1563          * value, not sure what for...
1564          */
1565
1566         r2ec |= 0x3f0;
1567         OUTREG(VGA_DDA_ON_OFF, r2ec);
1568         mdelay(1);
1569 }
1570
1571 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1572 {
1573         u32 r2ec, tmp;
1574
1575         /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1576          * here we rewrite with the same value, ... I suppose we clear/set
1577          * some bits that are already clear/set ?
1578          */
1579         r2ec = INREG(VGA_DDA_ON_OFF);
1580         OUTREG(VGA_DDA_ON_OFF, r2ec);
1581         mdelay(1);
1582
1583         /* Enable spread spectrum */
1584         OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1585         mdelay(3);
1586
1587         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1588         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1589         tmp = INPLL(pllSSPLL_CNTL);
1590         OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1591         mdelay(6);
1592         tmp = INPLL(pllSSPLL_CNTL);
1593         OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1594         mdelay(5);
1595
1596         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1597
1598         r2ec |= 8;
1599         OUTREG(VGA_DDA_ON_OFF, r2ec);
1600         mdelay(20);
1601
1602         /* Enable LVDS interface */
1603         tmp = INREG(LVDS_GEN_CNTL);
1604         OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1605
1606         /* Enable LVDS_PLL */
1607         tmp = INREG(LVDS_PLL_CNTL);
1608         tmp &= ~0x30000;
1609         tmp |= 0x10000;
1610         OUTREG(LVDS_PLL_CNTL, tmp);
1611
1612         OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1613         OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1614
1615         /* The trace reads that one here, waiting for something to settle down ? */
1616         INREG(RBBM_STATUS);
1617
1618         /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1619          * R300 register spec at least...
1620          */
1621         tmp = INPLL(pllSS_TST_CNTL);
1622         tmp |= 0x00400000;
1623         OUTPLL(pllSS_TST_CNTL, tmp);
1624 }
1625
1626 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1627 {
1628         u32 tmp;
1629
1630         OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1631         radeon_pll_errata_after_index(rinfo);
1632         OUTREG8(CLOCK_CNTL_DATA, 0);
1633         radeon_pll_errata_after_data(rinfo);
1634
1635         tmp = INPLL(pllVCLK_ECP_CNTL);
1636         OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1637         mdelay(5);
1638
1639         tmp = INPLL(pllPPLL_REF_DIV);
1640         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1641         OUTPLL(pllPPLL_REF_DIV, tmp);
1642         INPLL(pllPPLL_REF_DIV);
1643
1644         /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1645          * probably useless since we already did it ...
1646          */
1647         tmp = INPLL(pllPPLL_CNTL);
1648         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1649         radeon_pll_errata_after_index(rinfo);
1650         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1651         radeon_pll_errata_after_data(rinfo);
1652
1653         /* Restore our "reference" PPLL divider set by firmware
1654          * according to proper spread spectrum calculations
1655          */
1656         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1657
1658         tmp = INPLL(pllPPLL_CNTL);
1659         OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1660         mdelay(5);
1661
1662         tmp = INPLL(pllPPLL_CNTL);
1663         OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1664         mdelay(5);
1665
1666         tmp = INPLL(pllVCLK_ECP_CNTL);
1667         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1668         mdelay(5);
1669
1670         tmp = INPLL(pllVCLK_ECP_CNTL);
1671         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1672         mdelay(5);
1673
1674         /* Switch pixel clock to firmware default div 0 */
1675         OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1676         radeon_pll_errata_after_index(rinfo);
1677         radeon_pll_errata_after_data(rinfo);
1678 }
1679
1680 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1681 {
1682         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1683         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1684         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1685         OUTREG(MEM_SDRAM_MODE_REG,
1686                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1687         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1688         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1689         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1690         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1691         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1692         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1693
1694         OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1695         OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1696         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1697         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1698         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1699         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1700         OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1701         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1702         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1703         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1704         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1705         OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1706         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1707         OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1708         OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1709         OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1710         OUTREG(MC_IND_INDEX, 0);
1711 }
1712
1713 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1714 {
1715         u32 tmp, i;
1716
1717         /* Restore a bunch of registers first */
1718         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1719         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1720         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1721         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1722         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1723         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1724         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1725         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1726         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1727         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1728         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1729         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1730         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1731         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1732
1733         /* Hrm... */
1734         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1735
1736         /* Reset the PAD CTLR */
1737         radeon_pm_reset_pad_ctlr_strength(rinfo);
1738
1739         /* Some PLLs are Read & written identically in the trace here...
1740          * I suppose it's actually to switch them all off & reset,
1741          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1742          */
1743         radeon_pm_all_ppls_off(rinfo);
1744
1745         /* Clear tiling, reset swappers */
1746         INREG(SURFACE_CNTL);
1747         OUTREG(SURFACE_CNTL, 0);
1748
1749         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1750          * rather than hard coding...
1751          */
1752         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1753         tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1754         OUTREG(TV_DAC_CNTL, tmp);
1755
1756         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1757         tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1758         OUTREG(TV_DAC_CNTL, tmp);
1759
1760         /* More registers restored */
1761         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1762         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1763         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1764
1765         /* Hrmmm ... What is that ? */
1766         tmp = rinfo->save_regs[1]
1767                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1768                     CLK_PWRMGT_CNTL__MC_BUSY);
1769         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1770
1771         OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1772         OUTREG(FW_CNTL, rinfo->save_regs[57]);
1773         OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1774         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1775         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1776         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1777
1778         /* Restore Memory Controller configuration */
1779         radeon_pm_m10_reconfigure_mc(rinfo);
1780
1781         /* Make sure CRTC's dont touch memory */
1782         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1783                | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1784         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1785                | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1786         mdelay(30);
1787
1788         /* Disable SDRAM refresh */
1789         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1790                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1791
1792         /* Restore XTALIN routing (CLK_PIN_CNTL) */
1793         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1794
1795         /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1796         tmp = rinfo->save_regs[2] & 0xff000000;
1797         tmp |=  MCLK_CNTL__FORCE_MCLKA |
1798                 MCLK_CNTL__FORCE_MCLKB |
1799                 MCLK_CNTL__FORCE_YCLKA |
1800                 MCLK_CNTL__FORCE_YCLKB |
1801                 MCLK_CNTL__FORCE_MC;
1802         OUTPLL(pllMCLK_CNTL, tmp);
1803
1804         /* Force all clocks on in SCLK */
1805         tmp = INPLL(pllSCLK_CNTL);
1806         tmp |=  SCLK_CNTL__FORCE_DISP2|
1807                 SCLK_CNTL__FORCE_CP|
1808                 SCLK_CNTL__FORCE_HDP|
1809                 SCLK_CNTL__FORCE_DISP1|
1810                 SCLK_CNTL__FORCE_TOP|
1811                 SCLK_CNTL__FORCE_E2|
1812                 SCLK_CNTL__FORCE_SE|
1813                 SCLK_CNTL__FORCE_IDCT|
1814                 SCLK_CNTL__FORCE_VIP|
1815                 SCLK_CNTL__FORCE_PB|
1816                 SCLK_CNTL__FORCE_TAM|
1817                 SCLK_CNTL__FORCE_TDM|
1818                 SCLK_CNTL__FORCE_RB|
1819                 SCLK_CNTL__FORCE_TV_SCLK|
1820                 SCLK_CNTL__FORCE_SUBPIC|
1821                 SCLK_CNTL__FORCE_OV0;
1822         tmp |=  SCLK_CNTL__CP_MAX_DYN_STOP_LAT  |
1823                 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1824                 SCLK_CNTL__TV_MAX_DYN_STOP_LAT  |
1825                 SCLK_CNTL__E2_MAX_DYN_STOP_LAT  |
1826                 SCLK_CNTL__SE_MAX_DYN_STOP_LAT  |
1827                 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1828                 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1829                 SCLK_CNTL__RE_MAX_DYN_STOP_LAT  |
1830                 SCLK_CNTL__PB_MAX_DYN_STOP_LAT  |
1831                 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1832                 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1833                 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1834         OUTPLL(pllSCLK_CNTL, tmp);
1835
1836         OUTPLL(pllVCLK_ECP_CNTL, 0);
1837         OUTPLL(pllPIXCLKS_CNTL, 0);
1838         OUTPLL(pllMCLK_MISC,
1839                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1840                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1841
1842         mdelay(5);
1843
1844         /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1845         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1846         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1847         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1848
1849         /* Now restore the major PLLs settings, keeping them off & reset though */
1850         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1851         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1852         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1853         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1854
1855         /* Restore MC DLL state and switch it off/reset too  */
1856         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1857
1858         /* Switch MDLL off & reset */
1859         OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1860         mdelay(5);
1861
1862         /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1863          * 0xa1100007... and MacOS writes 0xa1000007 ..
1864          */
1865         OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1866
1867         /* Restore more stuffs */
1868         OUTPLL(pllHTOTAL_CNTL, 0);
1869         OUTPLL(pllHTOTAL2_CNTL, 0);
1870
1871         /* More PLL initial configuration */
1872         tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1873         OUTPLL(pllSCLK_CNTL2, tmp);
1874
1875         tmp = INPLL(pllSCLK_MORE_CNTL);
1876         tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS |        /* a guess */
1877                 SCLK_MORE_CNTL__FORCE_MC_GUI |
1878                 SCLK_MORE_CNTL__FORCE_MC_HOST;
1879         OUTPLL(pllSCLK_MORE_CNTL, tmp);
1880
1881         /* Now we actually start MCLK and SCLK */
1882         radeon_pm_start_mclk_sclk(rinfo);
1883
1884         /* Full reset sdrams, this also re-inits the MDLL */
1885         radeon_pm_full_reset_sdram(rinfo);
1886
1887         /* Fill palettes */
1888         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1889         for (i=0; i<256; i++)
1890                 OUTREG(PALETTE_30_DATA, 0x15555555);
1891         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1892         udelay(20);
1893         for (i=0; i<256; i++)
1894                 OUTREG(PALETTE_30_DATA, 0x15555555);
1895
1896         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1897         mdelay(3);
1898
1899         /* Restore TMDS */
1900         OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1901         OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1902
1903         /* Set LVDS registers but keep interface & pll down */
1904         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1905                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1906         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1907
1908         OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1909
1910         /* Restore GPIOPAD state */
1911         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1912         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1913         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1914
1915         /* write some stuff to the framebuffer... */
1916         for (i = 0; i < 0x8000; ++i)
1917                 writeb(0, rinfo->fb_base + i);
1918
1919         mdelay(40);
1920         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1921         mdelay(40);
1922
1923         /* Restore a few more things */
1924         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1925         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1926
1927         /* Take care of spread spectrum & PPLLs now */
1928         radeon_pm_m10_disable_spread_spectrum(rinfo);
1929         radeon_pm_restore_pixel_pll(rinfo);
1930
1931         /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1932          * code I have for blank/unblank doesn't quite work on some laptop models
1933          * it seems ... Hrm. What I have here works most of the time ...
1934          */
1935         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1936 }
1937
1938 #ifdef CONFIG_PPC_OF
1939
1940 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1941 {
1942         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1943         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1944         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1945         OUTREG(MEM_SDRAM_MODE_REG,
1946                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1947         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1948         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1949         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1950         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1951         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1952         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1953
1954         OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1955         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1956         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1957         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1958         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1959         OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1960         OUTREG(MC_IND_INDEX, 0);
1961         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1962
1963         mdelay(20);
1964 }
1965
1966 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1967 {
1968         u32 tmp, i;
1969
1970         /* Restore a bunch of registers first */
1971         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1972         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1973         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1974         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1975         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1976         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1977         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1978         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1979         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1980         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1981         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1982
1983         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1984         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1985
1986         /* Reset the PAD CTLR */
1987         radeon_pm_reset_pad_ctlr_strength(rinfo);
1988
1989         /* Some PLLs are Read & written identically in the trace here...
1990          * I suppose it's actually to switch them all off & reset,
1991          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1992          */
1993         radeon_pm_all_ppls_off(rinfo);
1994
1995         /* Clear tiling, reset swappers */
1996         INREG(SURFACE_CNTL);
1997         OUTREG(SURFACE_CNTL, 0);
1998
1999         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
2000          * rather than hard coding...
2001          */
2002         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2003         tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2004         OUTREG(TV_DAC_CNTL, tmp);
2005
2006         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2007         tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2008         OUTREG(TV_DAC_CNTL, tmp);
2009
2010         OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2011
2012         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2013         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2014         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2015
2016         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2017         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2018         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2019
2020         tmp  = rinfo->save_regs[1]
2021                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2022                     CLK_PWRMGT_CNTL__MC_BUSY);
2023         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2024
2025         OUTREG(FW_CNTL, rinfo->save_regs[57]);
2026
2027         /* Disable SDRAM refresh */
2028         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2029                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2030
2031         /* Restore XTALIN routing (CLK_PIN_CNTL) */
2032         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2033
2034         /* Force MCLK to be PCI sourced and forced ON */
2035         tmp = rinfo->save_regs[2] & 0xff000000;
2036         tmp |=  MCLK_CNTL__FORCE_MCLKA |
2037                 MCLK_CNTL__FORCE_MCLKB |
2038                 MCLK_CNTL__FORCE_YCLKA |
2039                 MCLK_CNTL__FORCE_YCLKB |
2040                 MCLK_CNTL__FORCE_MC    |
2041                 MCLK_CNTL__FORCE_AIC;
2042         OUTPLL(pllMCLK_CNTL, tmp);
2043
2044         /* Force SCLK to be PCI sourced with a bunch forced */
2045         tmp =   0 |
2046                 SCLK_CNTL__FORCE_DISP2|
2047                 SCLK_CNTL__FORCE_CP|
2048                 SCLK_CNTL__FORCE_HDP|
2049                 SCLK_CNTL__FORCE_DISP1|
2050                 SCLK_CNTL__FORCE_TOP|
2051                 SCLK_CNTL__FORCE_E2|
2052                 SCLK_CNTL__FORCE_SE|
2053                 SCLK_CNTL__FORCE_IDCT|
2054                 SCLK_CNTL__FORCE_VIP|
2055                 SCLK_CNTL__FORCE_RE|
2056                 SCLK_CNTL__FORCE_PB|
2057                 SCLK_CNTL__FORCE_TAM|
2058                 SCLK_CNTL__FORCE_TDM|
2059                 SCLK_CNTL__FORCE_RB;
2060         OUTPLL(pllSCLK_CNTL, tmp);
2061
2062         /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL  */
2063         OUTPLL(pllVCLK_ECP_CNTL, 0);
2064         OUTPLL(pllPIXCLKS_CNTL, 0);
2065
2066         /* Setup MCLK_MISC, non dynamic mode */
2067         OUTPLL(pllMCLK_MISC,
2068                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2069                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2070
2071         mdelay(5);
2072
2073         /* Set back the default clock dividers */
2074         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2075         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2076         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2077
2078         /* PPLL and P2PLL default values & off */
2079         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2080         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2081
2082         /* S and M PLLs are reset & off, configure them */
2083         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2084         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2085
2086         /* Default values for MDLL ... fixme */
2087         OUTPLL(pllMDLL_CKO, 0x9c009c);
2088         OUTPLL(pllMDLL_RDCKA, 0x08830883);
2089         OUTPLL(pllMDLL_RDCKB, 0x08830883);
2090         mdelay(5);
2091
2092         /* Restore PLL_PWRMGT_CNTL */ // XXXX
2093         tmp = rinfo->save_regs[0];
2094         tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2095         tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2096         OUTPLL(PLL_PWRMGT_CNTL,  tmp);
2097
2098         /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2099         OUTPLL(pllHTOTAL_CNTL, 0);
2100         OUTPLL(pllHTOTAL2_CNTL, 0);
2101
2102         /* All outputs off */
2103         OUTREG(CRTC_GEN_CNTL, 0x04000000);
2104         OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2105         OUTREG(FP_GEN_CNTL, 0x00004008);
2106         OUTREG(FP2_GEN_CNTL, 0x00000008);
2107         OUTREG(LVDS_GEN_CNTL, 0x08000008);
2108
2109         /* Restore Memory Controller configuration */
2110         radeon_pm_m9p_reconfigure_mc(rinfo);
2111
2112         /* Now we actually start MCLK and SCLK */
2113         radeon_pm_start_mclk_sclk(rinfo);
2114
2115         /* Full reset sdrams, this also re-inits the MDLL */
2116         radeon_pm_full_reset_sdram(rinfo);
2117
2118         /* Fill palettes */
2119         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2120         for (i=0; i<256; i++)
2121                 OUTREG(PALETTE_30_DATA, 0x15555555);
2122         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2123         udelay(20);
2124         for (i=0; i<256; i++)
2125                 OUTREG(PALETTE_30_DATA, 0x15555555);
2126
2127         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2128         mdelay(3);
2129
2130         /* Restore TV stuff, make sure TV DAC is down */
2131         OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2132         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2133
2134         /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2135          * possibly related to the weird PLL related workarounds and to the
2136          * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2137          * but we keep things the simple way here
2138          */
2139         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2140         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2141         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2142
2143         /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2144          * high bits from backup
2145          */
2146         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2147         tmp |= rinfo->save_regs[34] & 0xffff0000;
2148         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2149         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2150
2151         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2152         tmp |= rinfo->save_regs[34] & 0xffff0000;
2153         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2154         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2155
2156         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2157                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2158         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2159         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2160         mdelay(20);
2161
2162         /* write some stuff to the framebuffer... */
2163         for (i = 0; i < 0x8000; ++i)
2164                 writeb(0, rinfo->fb_base + i);
2165
2166         OUTREG(0x2ec, 0x6332a020);
2167         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2168         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2169         tmp = INPLL(pllSSPLL_CNTL);
2170         tmp &= ~2;
2171         OUTPLL(pllSSPLL_CNTL, tmp);
2172         mdelay(6);
2173         tmp &= ~1;
2174         OUTPLL(pllSSPLL_CNTL, tmp);
2175         mdelay(5);
2176         tmp |= 3;
2177         OUTPLL(pllSSPLL_CNTL, tmp);
2178         mdelay(5);
2179
2180         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2181         OUTREG(0x2ec, 0x6332a3f0);
2182         mdelay(17);
2183
2184         OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2185         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2186
2187         mdelay(40);
2188         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2189         mdelay(40);
2190
2191         /* Restore a few more things */
2192         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2193         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2194
2195         /* Restore PPLL, spread spectrum & LVDS */
2196         radeon_pm_m10_disable_spread_spectrum(rinfo);
2197         radeon_pm_restore_pixel_pll(rinfo);
2198         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2199 }
2200
2201 #if 0 /* Not ready yet */
2202 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2203 {
2204         int i;
2205         u32 tmp, tmp2;
2206         u32 cko, cka, ckb;
2207         u32 cgc, cec, c2gc;
2208
2209         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2210         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2211         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2212         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2213         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2214         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2215
2216         INREG(PAD_CTLR_STRENGTH);
2217         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2218         for (i = 0; i < 65; ++i) {
2219                 mdelay(1);
2220                 INREG(PAD_CTLR_STRENGTH);
2221         }
2222
2223         OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2224         OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2225         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2226         OUTREG(DAC_CNTL, 0xff00410a);
2227         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2228         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2229
2230         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2231         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2232         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2233         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2234
2235         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2236         OUTREG(MC_IND_INDEX, 0);
2237         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2238         OUTREG(MC_IND_INDEX, 0);
2239
2240         OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2241
2242         tmp = INPLL(pllVCLK_ECP_CNTL);
2243         OUTPLL(pllVCLK_ECP_CNTL, tmp);
2244         tmp = INPLL(pllPIXCLKS_CNTL);
2245         OUTPLL(pllPIXCLKS_CNTL, tmp);
2246
2247         OUTPLL(MCLK_CNTL, 0xaa3f0000);
2248         OUTPLL(SCLK_CNTL, 0xffff0000);
2249         OUTPLL(pllMPLL_AUX_CNTL, 6);
2250         OUTPLL(pllSPLL_AUX_CNTL, 1);
2251         OUTPLL(MDLL_CKO, 0x9f009f);
2252         OUTPLL(MDLL_RDCKA, 0x830083);
2253         OUTPLL(pllMDLL_RDCKB, 0x830083);
2254         OUTPLL(PPLL_CNTL, 0xa433);
2255         OUTPLL(P2PLL_CNTL, 0xa433);
2256         OUTPLL(MPLL_CNTL, 0x0400a403);
2257         OUTPLL(SPLL_CNTL, 0x0400a433);
2258
2259         tmp = INPLL(M_SPLL_REF_FB_DIV);
2260         OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2261         tmp = INPLL(M_SPLL_REF_FB_DIV);
2262         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2263         INPLL(M_SPLL_REF_FB_DIV);
2264
2265         tmp = INPLL(MPLL_CNTL);
2266         OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2267         radeon_pll_errata_after_index(rinfo);
2268         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2269         radeon_pll_errata_after_data(rinfo);
2270
2271         tmp = INPLL(M_SPLL_REF_FB_DIV);
2272         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2273
2274         tmp = INPLL(MPLL_CNTL);
2275         OUTPLL(MPLL_CNTL, tmp & ~0x2);
2276         mdelay(1);
2277         tmp = INPLL(MPLL_CNTL);
2278         OUTPLL(MPLL_CNTL, tmp & ~0x1);
2279         mdelay(10);
2280
2281         OUTPLL(MCLK_CNTL, 0xaa3f1212);
2282         mdelay(1);
2283
2284         INPLL(M_SPLL_REF_FB_DIV);
2285         INPLL(MCLK_CNTL);
2286         INPLL(M_SPLL_REF_FB_DIV);
2287
2288         tmp = INPLL(SPLL_CNTL);
2289         OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2290         radeon_pll_errata_after_index(rinfo);
2291         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2292         radeon_pll_errata_after_data(rinfo);
2293
2294         tmp = INPLL(M_SPLL_REF_FB_DIV);
2295         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2296
2297         tmp = INPLL(SPLL_CNTL);
2298         OUTPLL(SPLL_CNTL, tmp & ~0x1);
2299         mdelay(1);
2300         tmp = INPLL(SPLL_CNTL);
2301         OUTPLL(SPLL_CNTL, tmp & ~0x2);
2302         mdelay(10);
2303
2304         tmp = INPLL(SCLK_CNTL);
2305         OUTPLL(SCLK_CNTL, tmp | 2);
2306         mdelay(1);
2307
2308         cko = INPLL(pllMDLL_CKO);
2309         cka = INPLL(pllMDLL_RDCKA);
2310         ckb = INPLL(pllMDLL_RDCKB);
2311
2312         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2313         OUTPLL(pllMDLL_CKO, cko);
2314         mdelay(1);
2315         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2316         OUTPLL(pllMDLL_CKO, cko);
2317         mdelay(5);
2318
2319         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2320         OUTPLL(pllMDLL_RDCKA, cka);
2321         mdelay(1);
2322         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2323         OUTPLL(pllMDLL_RDCKA, cka);
2324         mdelay(5);
2325
2326         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2327         OUTPLL(pllMDLL_RDCKB, ckb);
2328         mdelay(1);
2329         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2330         OUTPLL(pllMDLL_RDCKB, ckb);
2331         mdelay(5);
2332
2333         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2334         OUTREG(MC_IND_INDEX, 0);
2335         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2336         OUTREG(MC_IND_INDEX, 0);
2337         mdelay(1);
2338         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2339         OUTREG(MC_IND_INDEX, 0);
2340         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2341         OUTREG(MC_IND_INDEX, 0);
2342         mdelay(1);
2343
2344         OUTPLL(pllHTOTAL_CNTL, 0);
2345         OUTPLL(pllHTOTAL2_CNTL, 0);
2346
2347         OUTREG(MEM_CNTL, 0x29002901);
2348         OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2349         OUTREG(EXT_MEM_CNTL, 0x1a394333);
2350         OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2351         OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2352         OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218);   /* XXX or save_regs[42]? */
2353         OUTREG(MC_DEBUG, 0);
2354         OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2355
2356         OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2357         OUTREG(MC_IND_INDEX, 0);
2358         OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2359         OUTREG(MC_IND_INDEX, 0);
2360
2361         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2362
2363         radeon_pm_full_reset_sdram(rinfo);
2364
2365         INREG(FP_GEN_CNTL);
2366         OUTREG(TMDS_CNTL, 0x01000000);  /* XXX ? */
2367         tmp = INREG(FP_GEN_CNTL);
2368         tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2369         OUTREG(FP_GEN_CNTL, tmp);
2370
2371         tmp = INREG(DISP_OUTPUT_CNTL);
2372         tmp &= ~0x400;
2373         OUTREG(DISP_OUTPUT_CNTL, tmp);
2374
2375         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2376         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2377         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2378
2379         tmp = INPLL(MCLK_MISC);
2380         tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2381         OUTPLL(MCLK_MISC, tmp);
2382
2383         tmp = INPLL(SCLK_CNTL);
2384         OUTPLL(SCLK_CNTL, tmp);
2385
2386         OUTREG(CRTC_MORE_CNTL, 0);
2387         OUTREG8(CRTC_GEN_CNTL+1, 6);
2388         OUTREG8(CRTC_GEN_CNTL+3, 1);
2389         OUTREG(CRTC_PITCH, 32);
2390
2391         tmp = INPLL(VCLK_ECP_CNTL);
2392         OUTPLL(VCLK_ECP_CNTL, tmp);
2393
2394         tmp = INPLL(PPLL_CNTL);
2395         OUTPLL(PPLL_CNTL, tmp);
2396
2397         /* palette stuff and BIOS_1_SCRATCH... */
2398
2399         tmp = INREG(FP_GEN_CNTL);
2400         tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2401         tmp |= 2;
2402         OUTREG(FP_GEN_CNTL, tmp);
2403         mdelay(5);
2404         OUTREG(FP_GEN_CNTL, tmp);
2405         mdelay(5);
2406         OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2407         OUTREG(CRTC_MORE_CNTL, 0);
2408         mdelay(20);
2409
2410         tmp = INREG(CRTC_MORE_CNTL);
2411         OUTREG(CRTC_MORE_CNTL, tmp);
2412
2413         cgc = INREG(CRTC_GEN_CNTL);
2414         cec = INREG(CRTC_EXT_CNTL);
2415         c2gc = INREG(CRTC2_GEN_CNTL);
2416
2417         OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2418         OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2419         OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2420         radeon_pll_errata_after_index(rinfo);
2421         OUTREG8(CLOCK_CNTL_DATA, 0);
2422         radeon_pll_errata_after_data(rinfo);
2423         OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2424         OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2425         OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2426         OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2427         OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2428         OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2429         OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2430         OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2431         OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2432         OUTREG(FP_HORZ_STRETCH, 0);
2433         OUTREG(FP_VERT_STRETCH, 0);
2434         OUTREG(OVR_CLR, 0);
2435         OUTREG(OVR_WID_LEFT_RIGHT, 0);
2436         OUTREG(OVR_WID_TOP_BOTTOM, 0);
2437
2438         tmp = INPLL(PPLL_REF_DIV);
2439         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2440         OUTPLL(PPLL_REF_DIV, tmp);
2441         INPLL(PPLL_REF_DIV);
2442
2443         OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2444         radeon_pll_errata_after_index(rinfo);
2445         OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2446         radeon_pll_errata_after_data(rinfo);
2447
2448         tmp = INREG(CLOCK_CNTL_INDEX);
2449         radeon_pll_errata_after_index(rinfo);
2450         OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2451         radeon_pll_errata_after_index(rinfo);
2452         radeon_pll_errata_after_data(rinfo);
2453
2454         OUTPLL(PPLL_DIV_0, 0x48090);
2455
2456         tmp = INPLL(PPLL_CNTL);
2457         OUTPLL(PPLL_CNTL, tmp & ~0x2);
2458         mdelay(1);
2459         tmp = INPLL(PPLL_CNTL);
2460         OUTPLL(PPLL_CNTL, tmp & ~0x1);
2461         mdelay(10);
2462
2463         tmp = INPLL(VCLK_ECP_CNTL);
2464         OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2465         mdelay(1);
2466
2467         tmp = INPLL(VCLK_ECP_CNTL);
2468         OUTPLL(VCLK_ECP_CNTL, tmp);
2469
2470         c2gc |= CRTC2_DISP_REQ_EN_B;
2471         OUTREG(CRTC2_GEN_CNTL, c2gc);
2472         cgc |= CRTC_EN;
2473         OUTREG(CRTC_GEN_CNTL, cgc);
2474         OUTREG(CRTC_EXT_CNTL, cec);
2475         OUTREG(CRTC_PITCH, 0xa0);
2476         OUTREG(CRTC_OFFSET, 0);
2477         OUTREG(CRTC_OFFSET_CNTL, 0);
2478
2479         OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2480         OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2481
2482         tmp2 = INREG(FP_GEN_CNTL);
2483         tmp = INREG(TMDS_TRANSMITTER_CNTL);
2484         OUTREG(0x2a8, 0x0000061b);
2485         tmp |= TMDS_PLL_EN;
2486         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2487         mdelay(1);
2488         tmp &= ~TMDS_PLLRST;
2489         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2490         tmp2 &= ~2;
2491         tmp2 |= FP_TMDS_EN;
2492         OUTREG(FP_GEN_CNTL, tmp2);
2493         mdelay(5);
2494         tmp2 |= FP_FPON;
2495         OUTREG(FP_GEN_CNTL, tmp2);
2496
2497         OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2498         cgc = INREG(CRTC_GEN_CNTL);
2499         OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2500         cgc |= 0x10000;
2501         OUTREG(CUR_OFFSET, 0);
2502 }
2503 #endif /* 0 */
2504
2505 #endif /* CONFIG_PPC_OF */
2506
2507 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2508 {
2509         u16 pwr_cmd;
2510         u32 tmp;
2511         int i;
2512
2513         if (!rinfo->pm_reg)
2514                 return;
2515
2516         /* Set the chip into appropriate suspend mode (we use D2,
2517          * D3 would require a compete re-initialization of the chip,
2518          * including PCI config registers, clocks, AGP conf, ...)
2519          */
2520         if (suspend) {
2521                 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2522                        pci_name(rinfo->pdev));
2523
2524                 /* Disable dynamic power management of clocks for the
2525                  * duration of the suspend/resume process
2526                  */
2527                 radeon_pm_disable_dynamic_mode(rinfo);
2528
2529                 /* Save some registers */
2530                 radeon_pm_save_regs(rinfo, 0);
2531
2532                 /* Prepare mobility chips for suspend.
2533                  */
2534                 if (rinfo->is_mobility) {
2535                         /* Program V2CLK */
2536                         radeon_pm_program_v2clk(rinfo);
2537
2538                         /* Disable IO PADs */
2539                         radeon_pm_disable_iopad(rinfo);
2540
2541                         /* Set low current */
2542                         radeon_pm_low_current(rinfo);
2543
2544                         /* Prepare chip for power management */
2545                         radeon_pm_setup_for_suspend(rinfo);
2546
2547                         if (rinfo->family <= CHIP_FAMILY_RV280) {
2548                                 /* Reset the MDLL */
2549                                 /* because both INPLL and OUTPLL take the same
2550                                  * lock, that's why. */
2551                                 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2552                                         | MDLL_CKO__MCKOB_RESET;
2553                                 OUTPLL( pllMDLL_CKO, tmp );
2554                         }
2555                 }
2556
2557                 for (i = 0; i < 64; ++i)
2558                         pci_read_config_dword(rinfo->pdev, i * 4,
2559                                               &rinfo->cfg_save[i]);
2560
2561                 /* Switch PCI power managment to D2. */
2562                 pci_disable_device(rinfo->pdev);
2563                 for (;;) {
2564                         pci_read_config_word(
2565                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2566                                 &pwr_cmd);
2567                         if (pwr_cmd & 2)
2568                                 break;
2569                         pci_write_config_word(
2570                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2571                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2572                         mdelay(500);
2573                 }
2574         } else {
2575                 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2576                        pci_name(rinfo->pdev));
2577
2578                 /* Switch back PCI powermanagment to D0 */
2579                 mdelay(200);
2580                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2581                 mdelay(500);
2582
2583                 if (rinfo->family <= CHIP_FAMILY_RV250) {
2584                         /* Reset the SDRAM controller  */
2585                         radeon_pm_full_reset_sdram(rinfo);
2586
2587                         /* Restore some registers */
2588                         radeon_pm_restore_regs(rinfo);
2589                 } else {
2590                         /* Restore registers first */
2591                         radeon_pm_restore_regs(rinfo);
2592                         /* init sdram controller */
2593                         radeon_pm_full_reset_sdram(rinfo);
2594                 }
2595         }
2596 }
2597
2598 static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo)
2599 {
2600         int i;
2601         static u32 radeon_cfg_after_resume[64];
2602
2603         for (i = 0; i < 64; ++i)
2604                 pci_read_config_dword(rinfo->pdev, i * 4,
2605                                       &radeon_cfg_after_resume[i]);
2606
2607         if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4]
2608             == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4])
2609                 return 0;       /* assume everything is ok */
2610
2611         for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) {
2612                 if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i])
2613                         pci_write_config_dword(rinfo->pdev, i * 4,
2614                                                rinfo->cfg_save[i]);
2615         }
2616         pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE,
2617                               rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]);
2618         pci_write_config_word(rinfo->pdev, PCI_COMMAND,
2619                               rinfo->cfg_save[PCI_COMMAND/4]);
2620         return 1;
2621 }
2622
2623
2624 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2625 {
2626         struct fb_info *info = pci_get_drvdata(pdev);
2627         struct radeonfb_info *rinfo = info->par;
2628         int i;
2629
2630         if (state.event == pdev->dev.power.power_state.event)
2631                 return 0;
2632
2633         printk(KERN_DEBUG "radeonfb (%s): suspending to state: %d...\n",
2634                pci_name(pdev), state.event);
2635
2636         /* For suspend-to-disk, we cheat here. We don't suspend anything and
2637          * let fbcon continue drawing until we are all set. That shouldn't
2638          * really cause any problem at this point, provided that the wakeup
2639          * code knows that any state in memory may not match the HW
2640          */
2641         if (state.event == PM_EVENT_FREEZE)
2642                 goto done;
2643
2644         acquire_console_sem();
2645
2646         fb_set_suspend(info, 1);
2647
2648         if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2649                 /* Make sure engine is reset */
2650                 radeon_engine_idle();
2651                 radeonfb_engine_reset(rinfo);
2652                 radeon_engine_idle();
2653         }
2654
2655         /* Blank display and LCD */
2656         radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2657
2658         /* Sleep */
2659         rinfo->asleep = 1;
2660         rinfo->lock_blank = 1;
2661         del_timer_sync(&rinfo->lvds_timer);
2662
2663 #ifdef CONFIG_PPC_PMAC
2664         /* On powermac, we have hooks to properly suspend/resume AGP now,
2665          * use them here. We'll ultimately need some generic support here,
2666          * but the generic code isn't quite ready for that yet
2667          */
2668         pmac_suspend_agp_for_card(pdev);
2669 #endif /* CONFIG_PPC_PMAC */
2670
2671         /* If we support wakeup from poweroff, we save all regs we can including cfg
2672          * space
2673          */
2674         if (rinfo->pm_mode & radeon_pm_off) {
2675                 /* Always disable dynamic clocks or weird things are happening when
2676                  * the chip goes off (basically the panel doesn't shut down properly
2677                  * and we crash on wakeup),
2678                  * also, we want the saved regs context to have no dynamic clocks in
2679                  * it, we'll restore the dynamic clocks state on wakeup
2680                  */
2681                 radeon_pm_disable_dynamic_mode(rinfo);
2682                 mdelay(50);
2683                 radeon_pm_save_regs(rinfo, 1);
2684
2685                 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2686                         /* Switch off LVDS interface */
2687                         mdelay(1);
2688                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2689                         mdelay(1);
2690                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2691                         OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2692                         mdelay(20);
2693                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2694                 }
2695                 // FIXME: Use PCI layer
2696                 for (i = 0; i < 64; ++i)
2697                         pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]);
2698                 pci_disable_device(pdev);
2699         }
2700         /* If we support D2, we go to it (should be fixed later with a flag forcing
2701          * D3 only for some laptops)
2702          */
2703         if (rinfo->pm_mode & radeon_pm_d2)
2704                 radeon_set_suspend(rinfo, 1);
2705
2706         release_console_sem();
2707
2708  done:
2709         pdev->dev.power.power_state = state;
2710
2711         return 0;
2712 }
2713
2714 int radeonfb_pci_resume(struct pci_dev *pdev)
2715 {
2716         struct fb_info *info = pci_get_drvdata(pdev);
2717         struct radeonfb_info *rinfo = info->par;
2718         int rc = 0;
2719
2720         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2721                 return 0;
2722
2723         if (rinfo->no_schedule) {
2724                 if (try_acquire_console_sem())
2725                         return 0;
2726         } else
2727                 acquire_console_sem();
2728
2729         printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2730                pci_name(pdev), pdev->dev.power.power_state.event);
2731
2732
2733         if (pci_enable_device(pdev)) {
2734                 rc = -ENODEV;
2735                 printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n",
2736                        pci_name(pdev));
2737                 goto bail;
2738         }
2739         pci_set_master(pdev);
2740
2741         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2742                 /* Wakeup chip. Check from config space if we were powered off
2743                  * (todo: additionally, check CLK_PIN_CNTL too)
2744                  */
2745                 if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) {
2746                         if (rinfo->reinit_func != NULL)
2747                                 rinfo->reinit_func(rinfo);
2748                         else {
2749                                 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2750                                        " D3 cold, need softboot !", pci_name(pdev));
2751                                 rc = -EIO;
2752                                 goto bail;
2753                         }
2754                 }
2755                 /* If we support D2, try to resume... we should check what was our
2756                  * state though... (were we really in D2 state ?). Right now, this code
2757                  * is only enable on Macs so it's fine.
2758                  */
2759                 else if (rinfo->pm_mode & radeon_pm_d2)
2760                         radeon_set_suspend(rinfo, 0);
2761
2762                 rinfo->asleep = 0;
2763         } else
2764                 radeon_engine_idle();
2765
2766         /* Restore display & engine */
2767         radeon_write_mode (rinfo, &rinfo->state, 1);
2768         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2769                 radeonfb_engine_init (rinfo);
2770
2771         fb_pan_display(info, &info->var);
2772         fb_set_cmap(&info->cmap, info);
2773
2774         /* Refresh */
2775         fb_set_suspend(info, 0);
2776
2777         /* Unblank */
2778         rinfo->lock_blank = 0;
2779         radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2780
2781 #ifdef CONFIG_PPC_PMAC
2782         /* On powermac, we have hooks to properly suspend/resume AGP now,
2783          * use them here. We'll ultimately need some generic support here,
2784          * but the generic code isn't quite ready for that yet
2785          */
2786         pmac_resume_agp_for_card(pdev);
2787 #endif /* CONFIG_PPC_PMAC */
2788
2789
2790         /* Check status of dynclk */
2791         if (rinfo->dynclk == 1)
2792                 radeon_pm_enable_dynamic_mode(rinfo);
2793         else if (rinfo->dynclk == 0)
2794                 radeon_pm_disable_dynamic_mode(rinfo);
2795
2796         pdev->dev.power.power_state = PMSG_ON;
2797
2798  bail:
2799         release_console_sem();
2800
2801         return rc;
2802 }
2803
2804 #ifdef CONFIG_PPC_OF
2805 static void radeonfb_early_resume(void *data)
2806 {
2807         struct radeonfb_info *rinfo = data;
2808
2809         rinfo->no_schedule = 1;
2810         radeonfb_pci_resume(rinfo->pdev);
2811         rinfo->no_schedule = 0;
2812 }
2813 #endif /* CONFIG_PPC_OF */
2814
2815 #endif /* CONFIG_PM */
2816
2817 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2818 {
2819         /* Find PM registers in config space if any*/
2820         rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2821
2822         /* Enable/Disable dynamic clocks: TODO add sysfs access */
2823         rinfo->dynclk = dynclk;
2824         if (dynclk == 1) {
2825                 radeon_pm_enable_dynamic_mode(rinfo);
2826                 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2827         } else if (dynclk == 0) {
2828                 radeon_pm_disable_dynamic_mode(rinfo);
2829                 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2830         }
2831
2832 #if defined(CONFIG_PM)
2833 #if defined(CONFIG_PPC_PMAC)
2834         /* Check if we can power manage on suspend/resume. We can do
2835          * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2836          * "Mac" cards, but that's all. We need more infos about what the
2837          * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2838          * reason. --BenH
2839          */
2840         if (machine_is(powermac) && rinfo->of_node) {
2841                 if (rinfo->is_mobility && rinfo->pm_reg &&
2842                     rinfo->family <= CHIP_FAMILY_RV250)
2843                         rinfo->pm_mode |= radeon_pm_d2;
2844
2845                 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2846                  * in some desktop G4s), Via (M9+ chip on iBook G4) and
2847                  * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2848                  */
2849                 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2850                     !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2851                         rinfo->reinit_func = radeon_reinitialize_M10;
2852                         rinfo->pm_mode |= radeon_pm_off;
2853                 }
2854 #if 0 /* Not ready yet */
2855                 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2856                         rinfo->reinit_func = radeon_reinitialize_QW;
2857                         rinfo->pm_mode |= radeon_pm_off;
2858                 }
2859 #endif
2860                 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2861                         rinfo->reinit_func = radeon_reinitialize_M9P;
2862                         rinfo->pm_mode |= radeon_pm_off;
2863                 }
2864
2865                 /* If any of the above is set, we assume the machine can sleep/resume.
2866                  * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2867                  * from the platform about what happens to the chip...
2868                  * Now we tell the platform about our capability
2869                  */
2870                 if (rinfo->pm_mode != radeon_pm_none) {
2871                         pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2872                         pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2873                 }
2874
2875 #if 0
2876                 /* Power down TV DAC, taht saves a significant amount of power,
2877                  * we'll have something better once we actually have some TVOut
2878                  * support
2879                  */
2880                 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2881 #endif
2882         }
2883 #endif /* defined(CONFIG_PPC_PMAC) */
2884 #endif /* defined(CONFIG_PM) */
2885
2886         if (ignore_devlist)
2887                 printk(KERN_DEBUG
2888                        "radeonfb: skipping test for device workarounds\n");
2889         else
2890                 radeon_apply_workarounds(rinfo);
2891
2892         if (force_sleep) {
2893                 printk(KERN_DEBUG
2894                        "radeonfb: forcefully enabling D2 sleep mode\n");
2895                 rinfo->pm_mode |= radeon_pm_d2;
2896         }
2897 }
2898
2899 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2900 {
2901 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2902         if (rinfo->pm_mode != radeon_pm_none)
2903                 pmac_set_early_video_resume(NULL, NULL);
2904 #endif
2905 }