drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/pbm.h>
  84 #include <asm/fbio.h>
  85 #endif
  86
  87 #ifdef CONFIG_ADB_PMU
  88 #include <linux/adb.h>
  89 #include <linux/pmu.h>
  90 #endif
  91 #ifdef CONFIG_BOOTX_TEXT
  92 #include <asm/btext.h>
  93 #endif
  94 #ifdef CONFIG_PMAC_BACKLIGHT
  95 #include <asm/backlight.h>
  96 #endif
  97 #ifdef CONFIG_MTRR
  98 #include <asm/mtrr.h>
  99 #endif
 100
 101 /*
 102  * Debug flags.
 103  */
 104 #undef DEBUG
 105 /*#define DEBUG*/
 106
 107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 108 /*  - must be large enough to catch all GUI-Regs   */
 109 /*  - must be aligned to a PAGE boundary           */
 110 #define GUI_RESERVE     (1 * PAGE_SIZE)
 111
 112 /* FIXME: remove the FAIL definition */
 113 #define FAIL(msg) do { \
 114         if (!(var->activate & FB_ACTIVATE_TEST)) \
 115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 116         return -EINVAL; \
 117 } while (0)
 118 #define FAIL_MAX(msg, x, _max_) do { \
 119         if (x > _max_) { \
 120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 122                 return -EINVAL; \
 123         } \
 124 } while (0)
 125 #ifdef DEBUG
 126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 127 #else
 128 #define DPRINTK(fmt, args...)
 129 #endif
 130
 131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 133
 134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 135 static const u32 lt_lcd_regs[] = {
 136         CONFIG_PANEL_LG,
 137         LCD_GEN_CNTL_LG,
 138         DSTN_CONTROL_LG,
 139         HFB_PITCH_ADDR_LG,
 140         HORZ_STRETCHING_LG,
 141         VERT_STRETCHING_LG,
 142         0, /* EXT_VERT_STRETCH */
 143         LT_GIO_LG,
 144         POWER_MANAGEMENT_LG
 145 };
 146
 147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 148 {
 149         if (M64_HAS(LT_LCD_REGS)) {
 150                 aty_st_le32(lt_lcd_regs[index], val, par);
 151         } else {
 152                 unsigned long temp;
 153
 154                 /* write addr byte */
 155                 temp = aty_ld_le32(LCD_INDEX, par);
 156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 157                 /* write the register value */
 158                 aty_st_le32(LCD_DATA, val, par);
 159         }
 160 }
 161
 162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 163 {
 164         if (M64_HAS(LT_LCD_REGS)) {
 165                 return aty_ld_le32(lt_lcd_regs[index], par);
 166         } else {
 167                 unsigned long temp;
 168
 169                 /* write addr byte */
 170                 temp = aty_ld_le32(LCD_INDEX, par);
 171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 172                 /* read the register value */
 173                 return aty_ld_le32(LCD_DATA, par);
 174         }
 175 }
 176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 177
 178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 179 /*
 180  * ATIReduceRatio --
 181  *
 182  * Reduce a fraction by factoring out the largest common divider of the
 183  * fraction's numerator and denominator.
 184  */
 185 static void ATIReduceRatio(int *Numerator, int *Denominator)
 186 {
 187     int Multiplier, Divider, Remainder;
 188
 189     Multiplier = *Numerator;
 190     Divider = *Denominator;
 191
 192     while ((Remainder = Multiplier % Divider))
 193     {
 194         Multiplier = Divider;
 195         Divider = Remainder;
 196     }
 197
 198     *Numerator /= Divider;
 199     *Denominator /= Divider;
 200 }
 201 #endif
 202     /*
 203      *  The Hardware parameters for each card
 204      */
 205
 206 struct pci_mmap_map {
 207         unsigned long voff;
 208         unsigned long poff;
 209         unsigned long size;
 210         unsigned long prot_flag;
 211         unsigned long prot_mask;
 212 };
 213
 214 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 215         .id             = "ATY Mach64",
 216         .type           = FB_TYPE_PACKED_PIXELS,
 217         .visual         = FB_VISUAL_PSEUDOCOLOR,
 218         .xpanstep       = 8,
 219         .ypanstep       = 1,
 220 };
 221
 222     /*
 223      *  Frame buffer device API
 224      */
 225
 226 static int atyfb_open(struct fb_info *info, int user);
 227 static int atyfb_release(struct fb_info *info, int user);
 228 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 229 static int atyfb_set_par(struct fb_info *info);
 230 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 231         u_int transp, struct fb_info *info);
 232 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 233 static int atyfb_blank(int blank, struct fb_info *info);
 234 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 235 #ifdef __sparc__
 236 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 237 #endif
 238 static int atyfb_sync(struct fb_info *info);
 239
 240     /*
 241      *  Internal routines
 242      */
 243
 244 static int aty_init(struct fb_info *info);
 245 static void aty_resume_chip(struct fb_info *info);
 246 #ifdef CONFIG_ATARI
 247 static int store_video_par(char *videopar, unsigned char m64_num);
 248 #endif
 249
 250 static struct crtc saved_crtc;
 251 static union aty_pll saved_pll;
 252 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 253
 254 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 255 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 256 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 258 #ifdef CONFIG_PPC
 259 static int read_aty_sense(const struct atyfb_par *par);
 260 #endif
 261
 262
 263     /*
 264      *  Interface used by the world
 265      */
 266
 267 static struct fb_var_screeninfo default_var = {
 268         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 269         640, 480, 640, 480, 0, 0, 8, 0,
 270         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 271         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 272         0, FB_VMODE_NONINTERLACED
 273 };
 274
 275 static struct fb_videomode defmode = {
 276         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 277         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 278         0, FB_VMODE_NONINTERLACED
 279 };
 280
 281 static struct fb_ops atyfb_ops = {
 282         .owner          = THIS_MODULE,
 283         .fb_open        = atyfb_open,
 284         .fb_release     = atyfb_release,
 285         .fb_check_var   = atyfb_check_var,
 286         .fb_set_par     = atyfb_set_par,
 287         .fb_setcolreg   = atyfb_setcolreg,
 288         .fb_pan_display = atyfb_pan_display,
 289         .fb_blank       = atyfb_blank,
 290         .fb_ioctl       = atyfb_ioctl,
 291         .fb_fillrect    = atyfb_fillrect,
 292         .fb_copyarea    = atyfb_copyarea,
 293         .fb_imageblit   = atyfb_imageblit,
 294 #ifdef __sparc__
 295         .fb_mmap        = atyfb_mmap,
 296 #endif
 297         .fb_sync        = atyfb_sync,
 298 };
 299
 300 static int noaccel;
 301 #ifdef CONFIG_MTRR
 302 static int nomtrr;
 303 #endif
 304 static int vram;
 305 static int pll;
 306 static int mclk;
 307 static int xclk;
 308 static int comp_sync __devinitdata = -1;
 309 static char *mode;
 310
 311 #ifdef CONFIG_PPC
 312 static int default_vmode __devinitdata = VMODE_CHOOSE;
 313 static int default_cmode __devinitdata = CMODE_CHOOSE;
 314
 315 module_param_named(vmode, default_vmode, int, 0);
 316 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 317 module_param_named(cmode, default_cmode, int, 0);
 318 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 319 #endif
 320
 321 #ifdef CONFIG_ATARI
 322 static unsigned int mach64_count __devinitdata = 0;
 323 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 324 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 325 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 326 #endif
 327
 328 /* top -> down is an evolution of mach64 chipset, any corrections? */
 329 #define ATI_CHIP_88800GX   (M64F_GX)
 330 #define ATI_CHIP_88800CX   (M64F_GX)
 331
 332 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 333 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 334
 335 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 336 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 337
 338 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 339 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 340 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 341
 342 /* FIXME what is this chip? */
 343 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 344
 345 /* make sets shorter */
 346 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 349 /*#define ATI_CHIP_264GTDVD  ?*/
 350 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 351
 352 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 353 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 354 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 355
 356 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 357 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 358
 359 static struct {
 360         u16 pci_id;
 361         const char *name;
 362         int pll, mclk, xclk, ecp_max;
 363         u32 features;
 364 } aty_chips[] __devinitdata = {
 365 #ifdef CONFIG_FB_ATY_GX
 366         /* Mach64 GX */
 367         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 368         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 369 #endif /* CONFIG_FB_ATY_GX */
 370
 371 #ifdef CONFIG_FB_ATY_CT
 372         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 373         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 374
 375         /* FIXME what is this chip? */
 376         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 377
 378         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 379         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 380
 381         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 382         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 383
 384         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 385
 386         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 387
 388         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 389         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 390         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 391         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 392
 393         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 394         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 395         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 396         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 397         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 398
 399         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 400         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 401         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 402         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
 403         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 404
 405         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 406         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 407         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 408         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 409         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 410         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 411
 412         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 413         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 414         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 415         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 416 #endif /* CONFIG_FB_ATY_CT */
 417 };
 418
 419 /* can not fail */
 420 static int __devinit correct_chipset(struct atyfb_par *par)
 421 {
 422         u8 rev;
 423         u16 type;
 424         u32 chip_id;
 425         const char *name;
 426         int i;
 427
 428         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 429                 if (par->pci_id == aty_chips[i].pci_id)
 430                         break;
 431
 432         name = aty_chips[i].name;
 433         par->pll_limits.pll_max = aty_chips[i].pll;
 434         par->pll_limits.mclk = aty_chips[i].mclk;
 435         par->pll_limits.xclk = aty_chips[i].xclk;
 436         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 437         par->features = aty_chips[i].features;
 438
 439         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 440         type = chip_id & CFG_CHIP_TYPE;
 441         rev = (chip_id & CFG_CHIP_REV) >> 24;
 442
 443         switch(par->pci_id) {
 444 #ifdef CONFIG_FB_ATY_GX
 445         case PCI_CHIP_MACH64GX:
 446                 if(type != 0x00d7)
 447                         return -ENODEV;
 448                 break;
 449         case PCI_CHIP_MACH64CX:
 450                 if(type != 0x0057)
 451                         return -ENODEV;
 452                 break;
 453 #endif
 454 #ifdef CONFIG_FB_ATY_CT
 455         case PCI_CHIP_MACH64VT:
 456                 switch (rev & 0x07) {
 457                 case 0x00:
 458                         switch (rev & 0xc0) {
 459                         case 0x00:
 460                                 name = "ATI264VT (A3) (Mach64 VT)";
 461                                 par->pll_limits.pll_max = 170;
 462                                 par->pll_limits.mclk = 67;
 463                                 par->pll_limits.xclk = 67;
 464                                 par->pll_limits.ecp_max = 80;
 465                                 par->features = ATI_CHIP_264VT;
 466                                 break;
 467                         case 0x40:
 468                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 469                                 par->pll_limits.pll_max = 200;
 470                                 par->pll_limits.mclk = 67;
 471                                 par->pll_limits.xclk = 67;
 472                                 par->pll_limits.ecp_max = 80;
 473                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 474                                 break;
 475                         }
 476                         break;
 477                 case 0x01:
 478                         name = "ATI264VT3 (B1) (Mach64 VT)";
 479                         par->pll_limits.pll_max = 200;
 480                         par->pll_limits.mclk = 67;
 481                         par->pll_limits.xclk = 67;
 482                         par->pll_limits.ecp_max = 80;
 483                         par->features = ATI_CHIP_264VTB;
 484                         break;
 485                 case 0x02:
 486                         name = "ATI264VT3 (B2) (Mach64 VT)";
 487                         par->pll_limits.pll_max = 200;
 488                         par->pll_limits.mclk = 67;
 489                         par->pll_limits.xclk = 67;
 490                         par->pll_limits.ecp_max = 80;
 491                         par->features = ATI_CHIP_264VT3;
 492                         break;
 493                 }
 494                 break;
 495         case PCI_CHIP_MACH64GT:
 496                 switch (rev & 0x07) {
 497                 case 0x01:
 498                         name = "3D RAGE II (Mach64 GT)";
 499                         par->pll_limits.pll_max = 170;
 500                         par->pll_limits.mclk = 67;
 501                         par->pll_limits.xclk = 67;
 502                         par->pll_limits.ecp_max = 80;
 503                         par->features = ATI_CHIP_264GTB;
 504                         break;
 505                 case 0x02:
 506                         name = "3D RAGE II+ (Mach64 GT)";
 507                         par->pll_limits.pll_max = 200;
 508                         par->pll_limits.mclk = 67;
 509                         par->pll_limits.xclk = 67;
 510                         par->pll_limits.ecp_max = 100;
 511                         par->features = ATI_CHIP_264GTB;
 512                         break;
 513                 }
 514                 break;
 515 #endif
 516         }
 517
 518         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 519         return 0;
 520 }
 521
 522 static char ram_dram[] __devinitdata = "DRAM";
 523 static char ram_resv[] __devinitdata = "RESV";
 524 #ifdef CONFIG_FB_ATY_GX
 525 static char ram_vram[] __devinitdata = "VRAM";
 526 #endif /* CONFIG_FB_ATY_GX */
 527 #ifdef CONFIG_FB_ATY_CT
 528 static char ram_edo[] __devinitdata = "EDO";
 529 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 530 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 531 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 532 static char ram_off[] __devinitdata = "OFF";
 533 #endif /* CONFIG_FB_ATY_CT */
 534
 535
 536 static u32 pseudo_palette[17];
 537
 538 #ifdef CONFIG_FB_ATY_GX
 539 static char *aty_gx_ram[8] __devinitdata = {
 540         ram_dram, ram_vram, ram_vram, ram_dram,
 541         ram_dram, ram_vram, ram_vram, ram_resv
 542 };
 543 #endif /* CONFIG_FB_ATY_GX */
 544
 545 #ifdef CONFIG_FB_ATY_CT
 546 static char *aty_ct_ram[8] __devinitdata = {
 547         ram_off, ram_dram, ram_edo, ram_edo,
 548         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 549 };
 550 #endif /* CONFIG_FB_ATY_CT */
 551
 552 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 553 {
 554         u32 pixclock = var->pixclock;
 555 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 556         u32 lcd_on_off;
 557         par->pll.ct.xres = 0;
 558         if (par->lcd_table != 0) {
 559                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 560                 if(lcd_on_off & LCD_ON) {
 561                         par->pll.ct.xres = var->xres;
 562                         pixclock = par->lcd_pixclock;
 563                 }
 564         }
 565 #endif
 566         return pixclock;
 567 }
 568
 569 #if defined(CONFIG_PPC)
 570
 571 /*
 572  *  Apple monitor sense
 573  */
 574
 575 static int __devinit read_aty_sense(const struct atyfb_par *par)
 576 {
 577         int sense, i;
 578
 579         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 580         __delay(200);
 581         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 582         __delay(2000);
 583         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 584         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 585
 586         /* drive each sense line low in turn and collect the other 2 */
 587         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 588         __delay(2000);
 589         i = aty_ld_le32(GP_IO, par);
 590         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 591         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 592         __delay(200);
 593
 594         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 595         __delay(2000);
 596         i = aty_ld_le32(GP_IO, par);
 597         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 598         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 599         __delay(200);
 600
 601         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 602         __delay(2000);
 603         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 604         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 605         return sense;
 606 }
 607
 608 #endif /* defined(CONFIG_PPC) */
 609
 610 /* ------------------------------------------------------------------------- */
 611
 612 /*
 613  *  CRTC programming
 614  */
 615
 616 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 617 {
 618 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 619         if (par->lcd_table != 0) {
 620                 if(!M64_HAS(LT_LCD_REGS)) {
 621                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 622                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 623                 }
 624                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 625                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 626
 627
 628                 /* switch to non shadow registers */
 629                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 630                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 631
 632                 /* save stretching */
 633                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 634                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 635                 if (!M64_HAS(LT_LCD_REGS))
 636                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 637         }
 638 #endif
 639         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 640         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 641         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 642         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 643         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 644         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 645         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 646
 647 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 648         if (par->lcd_table != 0) {
 649                 /* switch to shadow registers */
 650                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 651                         SHADOW_EN | SHADOW_RW_EN, par);
 652
 653                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 654                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 655                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 656                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 657
 658                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 659         }
 660 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 661 }
 662
 663 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 664 {
 665 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 666         if (par->lcd_table != 0) {
 667                 /* stop CRTC */
 668                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 669
 670                 /* update non-shadow registers first */
 671                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 672                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 673                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 674
 675                 /* temporarily disable stretching */
 676                 aty_st_lcd(HORZ_STRETCHING,
 677                         crtc->horz_stretching &
 678                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 679                 aty_st_lcd(VERT_STRETCHING,
 680                         crtc->vert_stretching &
 681                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 682                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 683         }
 684 #endif
 685         /* turn off CRT */
 686         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 687
 688         DPRINTK("setting up CRTC\n");
 689         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 690             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 691             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 692             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 693
 694         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 695         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 696         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 697         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 698         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 699         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 700         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 701
 702         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 703         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 704         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 705         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 706         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 707         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 708
 709         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 710 #if 0
 711         FIXME
 712         if (par->accel_flags & FB_ACCELF_TEXT)
 713                 aty_init_engine(par, info);
 714 #endif
 715 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 716         /* after setting the CRTC registers we should set the LCD registers. */
 717         if (par->lcd_table != 0) {
 718                 /* switch to shadow registers */
 719                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 720                         (SHADOW_EN | SHADOW_RW_EN), par);
 721
 722                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 723                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 724                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 725
 726                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 727                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 728                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 729                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 730
 731                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 732                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 733                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 734                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 735
 736                 /* restore CRTC selection & shadow state and enable stretching */
 737                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 738                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 739                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 740                 if(!M64_HAS(LT_LCD_REGS))
 741                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 742
 743                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 744                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 745                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 746                 if(!M64_HAS(LT_LCD_REGS)) {
 747                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 748                     aty_ld_le32(LCD_INDEX, par);
 749                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 750                 }
 751         }
 752 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 753 }
 754
 755 static int aty_var_to_crtc(const struct fb_info *info,
 756         const struct fb_var_screeninfo *var, struct crtc *crtc)
 757 {
 758         struct atyfb_par *par = (struct atyfb_par *) info->par;
 759         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 760         u32 sync, vmode, vdisplay;
 761         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 762         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 763         u32 pix_width, dp_pix_width, dp_chain_mask;
 764
 765         /* input */
 766         xres = var->xres;
 767         yres = var->yres;
 768         vxres = var->xres_virtual;
 769         vyres = var->yres_virtual;
 770         xoffset = var->xoffset;
 771         yoffset = var->yoffset;
 772         bpp = var->bits_per_pixel;
 773         if (bpp == 16)
 774                 bpp = (var->green.length == 5) ? 15 : 16;
 775         sync = var->sync;
 776         vmode = var->vmode;
 777
 778         /* convert (and round up) and validate */
 779         if (vxres < xres + xoffset)
 780                 vxres = xres + xoffset;
 781         h_disp = xres;
 782
 783         if (vyres < yres + yoffset)
 784                 vyres = yres + yoffset;
 785         v_disp = yres;
 786
 787         if (bpp <= 8) {
 788                 bpp = 8;
 789                 pix_width = CRTC_PIX_WIDTH_8BPP;
 790                 dp_pix_width =
 791                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 792                     BYTE_ORDER_LSB_TO_MSB;
 793                 dp_chain_mask = DP_CHAIN_8BPP;
 794         } else if (bpp <= 15) {
 795                 bpp = 16;
 796                 pix_width = CRTC_PIX_WIDTH_15BPP;
 797                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 798                     BYTE_ORDER_LSB_TO_MSB;
 799                 dp_chain_mask = DP_CHAIN_15BPP;
 800         } else if (bpp <= 16) {
 801                 bpp = 16;
 802                 pix_width = CRTC_PIX_WIDTH_16BPP;
 803                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 804                     BYTE_ORDER_LSB_TO_MSB;
 805                 dp_chain_mask = DP_CHAIN_16BPP;
 806         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 807                 bpp = 24;
 808                 pix_width = CRTC_PIX_WIDTH_24BPP;
 809                 dp_pix_width =
 810                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 811                     BYTE_ORDER_LSB_TO_MSB;
 812                 dp_chain_mask = DP_CHAIN_24BPP;
 813         } else if (bpp <= 32) {
 814                 bpp = 32;
 815                 pix_width = CRTC_PIX_WIDTH_32BPP;
 816                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 817                     BYTE_ORDER_LSB_TO_MSB;
 818                 dp_chain_mask = DP_CHAIN_32BPP;
 819         } else
 820                 FAIL("invalid bpp");
 821
 822         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 823                 FAIL("not enough video RAM");
 824
 825         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 826         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 827
 828         if((xres > 1600) || (yres > 1200)) {
 829                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 830                 "select anoter resolution.");
 831         }
 832         h_sync_strt = h_disp + var->right_margin;
 833         h_sync_end = h_sync_strt + var->hsync_len;
 834         h_sync_dly  = var->right_margin & 7;
 835         h_total = h_sync_end + h_sync_dly + var->left_margin;
 836
 837         v_sync_strt = v_disp + var->lower_margin;
 838         v_sync_end = v_sync_strt + var->vsync_len;
 839         v_total = v_sync_end + var->upper_margin;
 840
 841 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 842         if (par->lcd_table != 0) {
 843                 if(!M64_HAS(LT_LCD_REGS)) {
 844                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 845                     crtc->lcd_index = lcd_index &
 846                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 847                     aty_st_le32(LCD_INDEX, lcd_index, par);
 848                 }
 849
 850                 if (!M64_HAS(MOBIL_BUS))
 851                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 852
 853                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 854                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 855
 856                 crtc->lcd_gen_cntl &=
 857                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 858                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 859                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 860                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 861
 862                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 863                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 864                         /* We cannot display the mode on the LCD. If the CRT is enabled
 865                            we can turn off the LCD.
 866                            If the CRT is off, it isn't a good idea to switch it on; we don't
 867                            know if one is connected. So it's better to fail then.
 868                          */
 869                         if (crtc->lcd_gen_cntl & CRT_ON) {
 870                                 if (!(var->activate & FB_ACTIVATE_TEST))
 871                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 872                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 873                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 874                         } else {
 875                                 if (!(var->activate & FB_ACTIVATE_TEST))
 876                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 877                                 return -EINVAL;
 878                         }
 879                 }
 880         }
 881
 882         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 883                 int VScan = 1;
 884                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 885                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 886                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 887
 888                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 889
 890                 /* This is horror! When we simulate, say 640x480 on an 800x600
 891                    LCD monitor, the CRTC should be programmed 800x600 values for
 892                    the non visible part, but 640x480 for the visible part.
 893                    This code has been tested on a laptop with it's 1400x1050 LCD
 894                    monitor and a conventional monitor both switched on.
 895                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 896                     works with little glitches also with DOUBLESCAN modes
 897                  */
 898                 if (yres < par->lcd_height) {
 899                         VScan = par->lcd_height / yres;
 900                         if(VScan > 1) {
 901                                 VScan = 2;
 902                                 vmode |= FB_VMODE_DOUBLE;
 903                         }
 904                 }
 905
 906                 h_sync_strt = h_disp + par->lcd_right_margin;
 907                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 908                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 909                 h_total = h_disp + par->lcd_hblank_len;
 910
 911                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 912                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 913                 v_total = v_disp + par->lcd_vblank_len / VScan;
 914         }
 915 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 916
 917         h_disp = (h_disp >> 3) - 1;
 918         h_sync_strt = (h_sync_strt >> 3) - 1;
 919         h_sync_end = (h_sync_end >> 3) - 1;
 920         h_total = (h_total >> 3) - 1;
 921         h_sync_wid = h_sync_end - h_sync_strt;
 922
 923         FAIL_MAX("h_disp too large", h_disp, 0xff);
 924         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 925         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 926         if(h_sync_wid > 0x1f)
 927                 h_sync_wid = 0x1f;
 928         FAIL_MAX("h_total too large", h_total, 0x1ff);
 929
 930         if (vmode & FB_VMODE_DOUBLE) {
 931                 v_disp <<= 1;
 932                 v_sync_strt <<= 1;
 933                 v_sync_end <<= 1;
 934                 v_total <<= 1;
 935         }
 936
 937         vdisplay = yres;
 938 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 939         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 940                 vdisplay  = par->lcd_height;
 941 #endif
 942
 943         v_disp--;
 944         v_sync_strt--;
 945         v_sync_end--;
 946         v_total--;
 947         v_sync_wid = v_sync_end - v_sync_strt;
 948
 949         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 950         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 951         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 952         if(v_sync_wid > 0x1f)
 953                 v_sync_wid = 0x1f;
 954         FAIL_MAX("v_total too large", v_total, 0x7ff);
 955
 956         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 957
 958         /* output */
 959         crtc->vxres = vxres;
 960         crtc->vyres = vyres;
 961         crtc->xoffset = xoffset;
 962         crtc->yoffset = yoffset;
 963         crtc->bpp = bpp;
 964         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 965         crtc->vline_crnt_vline = 0;
 966
 967         crtc->h_tot_disp = h_total | (h_disp<<16);
 968         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 969                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 970         crtc->v_tot_disp = v_total | (v_disp<<16);
 971         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 972
 973         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 974         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 975         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 976
 977         /* Enable doublescan mode if requested */
 978         if (vmode & FB_VMODE_DOUBLE)
 979                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 980         /* Enable interlaced mode if requested */
 981         if (vmode & FB_VMODE_INTERLACED)
 982                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 983 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 984         if (par->lcd_table != 0) {
 985                 vdisplay = yres;
 986                 if(vmode & FB_VMODE_DOUBLE)
 987                         vdisplay <<= 1;
 988                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 989                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 990                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 991                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 992                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 993
 994                 /* MOBILITY M1 tested, FIXME: LT */
 995                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 996                 if (!M64_HAS(LT_LCD_REGS))
 997                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
 998                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
 999
1000                 crtc->horz_stretching &=
1001                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1002                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1003                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1004                         do {
1005                                 /*
1006                                 * The horizontal blender misbehaves when HDisplay is less than a
1007                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1008                                 * stretch such modes enough.  Use pixel replication instead of
1009                                 * blending to stretch modes that can be made to exactly fit the
1010                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1011                                 * pixel-replicated mode to be slightly wider or narrower than the
1012                                 * panel width.  It also causes a mode that is exactly half as wide
1013                                 * as the panel to be pixel-replicated, rather than blended.
1014                                 */
1015                                 int HDisplay  = xres & ~7;
1016                                 int nStretch  = par->lcd_width / HDisplay;
1017                                 int Remainder = par->lcd_width % HDisplay;
1018
1019                                 if ((!Remainder && ((nStretch > 2))) ||
1020                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1021                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1022                                         int horz_stretch_loop = -1, BestRemainder;
1023                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1024                                         int Index = 5;
1025                                         ATIReduceRatio(&Numerator, &Denominator);
1026
1027                                         BestRemainder = (Numerator * 16) / Denominator;
1028                                         while (--Index >= 0) {
1029                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1030                                                         Denominator;
1031                                                 if (Remainder < BestRemainder) {
1032                                                         horz_stretch_loop = Index;
1033                                                         if (!(BestRemainder = Remainder))
1034                                                                 break;
1035                                                 }
1036                                         }
1037
1038                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1039                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1040                                                 int reuse_previous = 1;
1041
1042                                                 Index = StretchLoops[horz_stretch_loop];
1043
1044                                                 while (--Index >= 0) {
1045                                                         if (Accumulator > 0)
1046                                                                 horz_stretch_ratio |= reuse_previous;
1047                                                         else
1048                                                                 Accumulator += Denominator;
1049                                                         Accumulator -= Numerator;
1050                                                         reuse_previous <<= 1;
1051                                                 }
1052
1053                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1054                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1055                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1056                                                 break;      /* Out of the do { ... } while (0) */
1057                                         }
1058                                 }
1059
1060                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1061                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1062                         } while (0);
1063                 }
1064
1065                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1066                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1067                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1068
1069                         if (!M64_HAS(LT_LCD_REGS) &&
1070                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1071                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1072                 } else {
1073                         /*
1074                          * Don't use vertical blending if the mode is too wide or not
1075                          * vertically stretched.
1076                          */
1077                         crtc->vert_stretching = 0;
1078                 }
1079                 /* copy to shadow crtc */
1080                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1081                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1082                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1083                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1084         }
1085 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1086
1087         if (M64_HAS(MAGIC_FIFO)) {
1088                 /* FIXME: display FIFO low watermark values */
1089                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1090         }
1091         crtc->dp_pix_width = dp_pix_width;
1092         crtc->dp_chain_mask = dp_chain_mask;
1093
1094         return 0;
1095 }
1096
1097 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1098 {
1099         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1100         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1101             h_sync_pol;
1102         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1103         u32 pix_width;
1104         u32 double_scan, interlace;
1105
1106         /* input */
1107         h_total = crtc->h_tot_disp & 0x1ff;
1108         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1109         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1110         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1111         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1112         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1113         v_total = crtc->v_tot_disp & 0x7ff;
1114         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1115         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1116         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1117         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1118         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1119         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1120         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1121         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1122
1123         /* convert */
1124         xres = (h_disp + 1) * 8;
1125         yres = v_disp + 1;
1126         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1127         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1128         hslen = h_sync_wid * 8;
1129         upper = v_total - v_sync_strt - v_sync_wid;
1130         lower = v_sync_strt - v_disp;
1131         vslen = v_sync_wid;
1132         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1133             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1134             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1135
1136         switch (pix_width) {
1137 #if 0
1138         case CRTC_PIX_WIDTH_4BPP:
1139                 bpp = 4;
1140                 var->red.offset = 0;
1141                 var->red.length = 8;
1142                 var->green.offset = 0;
1143                 var->green.length = 8;
1144                 var->blue.offset = 0;
1145                 var->blue.length = 8;
1146                 var->transp.offset = 0;
1147                 var->transp.length = 0;
1148                 break;
1149 #endif
1150         case CRTC_PIX_WIDTH_8BPP:
1151                 bpp = 8;
1152                 var->red.offset = 0;
1153                 var->red.length = 8;
1154                 var->green.offset = 0;
1155                 var->green.length = 8;
1156                 var->blue.offset = 0;
1157                 var->blue.length = 8;
1158                 var->transp.offset = 0;
1159                 var->transp.length = 0;
1160                 break;
1161         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1162                 bpp = 16;
1163                 var->red.offset = 10;
1164                 var->red.length = 5;
1165                 var->green.offset = 5;
1166                 var->green.length = 5;
1167                 var->blue.offset = 0;
1168                 var->blue.length = 5;
1169                 var->transp.offset = 0;
1170                 var->transp.length = 0;
1171                 break;
1172         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1173                 bpp = 16;
1174                 var->red.offset = 11;
1175                 var->red.length = 5;
1176                 var->green.offset = 5;
1177                 var->green.length = 6;
1178                 var->blue.offset = 0;
1179                 var->blue.length = 5;
1180                 var->transp.offset = 0;
1181                 var->transp.length = 0;
1182                 break;
1183         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1184                 bpp = 24;
1185                 var->red.offset = 16;
1186                 var->red.length = 8;
1187                 var->green.offset = 8;
1188                 var->green.length = 8;
1189                 var->blue.offset = 0;
1190                 var->blue.length = 8;
1191                 var->transp.offset = 0;
1192                 var->transp.length = 0;
1193                 break;
1194         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1195                 bpp = 32;
1196                 var->red.offset = 16;
1197                 var->red.length = 8;
1198                 var->green.offset = 8;
1199                 var->green.length = 8;
1200                 var->blue.offset = 0;
1201                 var->blue.length = 8;
1202                 var->transp.offset = 24;
1203                 var->transp.length = 8;
1204                 break;
1205         default:
1206                 PRINTKE("Invalid pixel width\n");
1207                 return -EINVAL;
1208         }
1209
1210         /* output */
1211         var->xres = xres;
1212         var->yres = yres;
1213         var->xres_virtual = crtc->vxres;
1214         var->yres_virtual = crtc->vyres;
1215         var->bits_per_pixel = bpp;
1216         var->left_margin = left;
1217         var->right_margin = right;
1218         var->upper_margin = upper;
1219         var->lower_margin = lower;
1220         var->hsync_len = hslen;
1221         var->vsync_len = vslen;
1222         var->sync = sync;
1223         var->vmode = FB_VMODE_NONINTERLACED;
1224         /* In double scan mode, the vertical parameters are doubled, so we need to
1225            half them to get the right values.
1226            In interlaced mode the values are already correct, so no correction is
1227            necessary.
1228          */
1229         if (interlace)
1230                 var->vmode = FB_VMODE_INTERLACED;
1231
1232         if (double_scan) {
1233                 var->vmode = FB_VMODE_DOUBLE;
1234                 var->yres>>=1;
1235                 var->upper_margin>>=1;
1236                 var->lower_margin>>=1;
1237                 var->vsync_len>>=1;
1238         }
1239
1240         return 0;
1241 }
1242
1243 /* ------------------------------------------------------------------------- */
1244
1245 static int atyfb_set_par(struct fb_info *info)
1246 {
1247         struct atyfb_par *par = (struct atyfb_par *) info->par;
1248         struct fb_var_screeninfo *var = &info->var;
1249         u32 tmp, pixclock;
1250         int err;
1251 #ifdef DEBUG
1252         struct fb_var_screeninfo debug;
1253         u32 pixclock_in_ps;
1254 #endif
1255         if (par->asleep)
1256                 return 0;
1257
1258         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1259                 return err;
1260
1261         pixclock = atyfb_get_pixclock(var, par);
1262
1263         if (pixclock == 0) {
1264                 PRINTKE("Invalid pixclock\n");
1265                 return -EINVAL;
1266         } else {
1267                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1268                         return err;
1269         }
1270
1271         par->accel_flags = var->accel_flags; /* hack */
1272
1273         if (var->accel_flags) {
1274                 info->fbops->fb_sync = atyfb_sync;
1275                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1276         } else {
1277                 info->fbops->fb_sync = NULL;
1278                 info->flags |= FBINFO_HWACCEL_DISABLED;
1279         }
1280
1281         if (par->blitter_may_be_busy)
1282                 wait_for_idle(par);
1283
1284         aty_set_crtc(par, &par->crtc);
1285         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1286         par->pll_ops->set_pll(info, &par->pll);
1287
1288 #ifdef DEBUG
1289         if(par->pll_ops && par->pll_ops->pll_to_var)
1290                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1291         else
1292                 pixclock_in_ps = 0;
1293
1294         if(0 == pixclock_in_ps) {
1295                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1296                 pixclock_in_ps = pixclock;
1297         }
1298
1299         memset(&debug, 0, sizeof(debug));
1300         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1301                 u32 hSync, vRefresh;
1302                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1303                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1304
1305                 h_disp = debug.xres;
1306                 h_sync_strt = h_disp + debug.right_margin;
1307                 h_sync_end = h_sync_strt + debug.hsync_len;
1308                 h_total = h_sync_end + debug.left_margin;
1309                 v_disp = debug.yres;
1310                 v_sync_strt = v_disp + debug.lower_margin;
1311                 v_sync_end = v_sync_strt + debug.vsync_len;
1312                 v_total = v_sync_end + debug.upper_margin;
1313
1314                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1315                 vRefresh = (hSync * 1000) / v_total;
1316                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1317                 vRefresh *= 2;
1318                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1319                 vRefresh /= 2;
1320
1321                 DPRINTK("atyfb_set_par\n");
1322                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1323                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1324                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1325                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1326                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1327                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1328                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1329                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1330                         h_disp, h_sync_strt, h_sync_end, h_total,
1331                         v_disp, v_sync_strt, v_sync_end, v_total);
1332                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1333                         pixclock_in_ps,
1334                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1335                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1336         }
1337 #endif /* DEBUG */
1338
1339         if (!M64_HAS(INTEGRATED)) {
1340                 /* Don't forget MEM_CNTL */
1341                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1342                 switch (var->bits_per_pixel) {
1343                 case 8:
1344                         tmp |= 0x02000000;
1345                         break;
1346                 case 16:
1347                         tmp |= 0x03000000;
1348                         break;
1349                 case 32:
1350                         tmp |= 0x06000000;
1351                         break;
1352                 }
1353                 aty_st_le32(MEM_CNTL, tmp, par);
1354         } else {
1355                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1356                 if (!M64_HAS(MAGIC_POSTDIV))
1357                         tmp |= par->mem_refresh_rate << 20;
1358                 switch (var->bits_per_pixel) {
1359                 case 8:
1360                 case 24:
1361                         tmp |= 0x00000000;
1362                         break;
1363                 case 16:
1364                         tmp |= 0x04000000;
1365                         break;
1366                 case 32:
1367                         tmp |= 0x08000000;
1368                         break;
1369                 }
1370                 if (M64_HAS(CT_BUS)) {
1371                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1372                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1373                 } else if (M64_HAS(VT_BUS)) {
1374                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1375                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1376                 } else if (M64_HAS(MOBIL_BUS)) {
1377                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1378                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1379                 } else {
1380                         /* GT */
1381                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1382                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1383                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1384                 }
1385                 aty_st_le32(MEM_CNTL, tmp, par);
1386         }
1387         aty_st_8(DAC_MASK, 0xff, par);
1388
1389         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1390         info->fix.visual = var->bits_per_pixel <= 8 ?
1391                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1392
1393         /* Initialize the graphics engine */
1394         if (par->accel_flags & FB_ACCELF_TEXT)
1395                 aty_init_engine(par, info);
1396
1397 #ifdef CONFIG_BOOTX_TEXT
1398         btext_update_display(info->fix.smem_start,
1399                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1400                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1401                 var->bits_per_pixel,
1402                 par->crtc.vxres * var->bits_per_pixel / 8);
1403 #endif /* CONFIG_BOOTX_TEXT */
1404 #if 0
1405         /* switch to accelerator mode */
1406         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1407                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1408 #endif
1409 #ifdef DEBUG
1410 {
1411         /* dump non shadow CRTC, pll, LCD registers */
1412         int i; u32 base;
1413
1414         /* CRTC registers */
1415         base = 0x2000;
1416         printk("debug atyfb: Mach64 non-shadow register values:");
1417         for (i = 0; i < 256; i = i+4) {
1418                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1419                 printk(" %08X", aty_ld_le32(i, par));
1420         }
1421         printk("\n\n");
1422
1423 #ifdef CONFIG_FB_ATY_CT
1424         /* PLL registers */
1425         base = 0x00;
1426         printk("debug atyfb: Mach64 PLL register values:");
1427         for (i = 0; i < 64; i++) {
1428                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1429                 if(i%4 == 0)  printk(" ");
1430                 printk("%02X", aty_ld_pll_ct(i, par));
1431         }
1432         printk("\n\n");
1433 #endif  /* CONFIG_FB_ATY_CT */
1434
1435 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1436         if (par->lcd_table != 0) {
1437                 /* LCD registers */
1438                 base = 0x00;
1439                 printk("debug atyfb: LCD register values:");
1440                 if(M64_HAS(LT_LCD_REGS)) {
1441                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1442                         if(i == EXT_VERT_STRETCH)
1443                             continue;
1444                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1445                         printk(" %08X", aty_ld_lcd(i, par));
1446                     }
1447
1448                 } else {
1449                     for (i = 0; i < 64; i++) {
1450                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1451                         printk(" %08X", aty_ld_lcd(i, par));
1452                     }
1453                 }
1454                 printk("\n\n");
1455         }
1456 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1457 }
1458 #endif /* DEBUG */
1459         return 0;
1460 }
1461
1462 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1463 {
1464         struct atyfb_par *par = (struct atyfb_par *) info->par;
1465         int err;
1466         struct crtc crtc;
1467         union aty_pll pll;
1468         u32 pixclock;
1469
1470         memcpy(&pll, &(par->pll), sizeof(pll));
1471
1472         if((err = aty_var_to_crtc(info, var, &crtc)))
1473                 return err;
1474
1475         pixclock = atyfb_get_pixclock(var, par);
1476
1477         if (pixclock == 0) {
1478                 if (!(var->activate & FB_ACTIVATE_TEST))
1479                         PRINTKE("Invalid pixclock\n");
1480                 return -EINVAL;
1481         } else {
1482                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1483                         return err;
1484         }
1485
1486         if (var->accel_flags & FB_ACCELF_TEXT)
1487                 info->var.accel_flags = FB_ACCELF_TEXT;
1488         else
1489                 info->var.accel_flags = 0;
1490
1491         aty_crtc_to_var(&crtc, var);
1492         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1493         return 0;
1494 }
1495
1496 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1497 {
1498         u32 xoffset = info->var.xoffset;
1499         u32 yoffset = info->var.yoffset;
1500         u32 vxres = par->crtc.vxres;
1501         u32 bpp = info->var.bits_per_pixel;
1502
1503         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1504 }
1505
1506
1507     /*
1508      *  Open/Release the frame buffer device
1509      */
1510
1511 static int atyfb_open(struct fb_info *info, int user)
1512 {
1513         struct atyfb_par *par = (struct atyfb_par *) info->par;
1514
1515         if (user) {
1516                 par->open++;
1517 #ifdef __sparc__
1518                 par->mmaped = 0;
1519 #endif
1520         }
1521         return (0);
1522 }
1523
1524 static irqreturn_t aty_irq(int irq, void *dev_id)
1525 {
1526         struct atyfb_par *par = dev_id;
1527         int handled = 0;
1528         u32 int_cntl;
1529
1530         spin_lock(&par->int_lock);
1531
1532         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1533
1534         if (int_cntl & CRTC_VBLANK_INT) {
1535                 /* clear interrupt */
1536                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1537                 par->vblank.count++;
1538                 if (par->vblank.pan_display) {
1539                         par->vblank.pan_display = 0;
1540                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1541                 }
1542                 wake_up_interruptible(&par->vblank.wait);
1543                 handled = 1;
1544         }
1545
1546         spin_unlock(&par->int_lock);
1547
1548         return IRQ_RETVAL(handled);
1549 }
1550
1551 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1552 {
1553         u32 int_cntl;
1554
1555         if (!test_and_set_bit(0, &par->irq_flags)) {
1556                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1557                         clear_bit(0, &par->irq_flags);
1558                         return -EINVAL;
1559                 }
1560                 spin_lock_irq(&par->int_lock);
1561                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1562                 /* clear interrupt */
1563                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1564                 /* enable interrupt */
1565                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1566                 spin_unlock_irq(&par->int_lock);
1567         } else if (reenable) {
1568                 spin_lock_irq(&par->int_lock);
1569                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1570                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1571                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1572                         /* re-enable interrupt */
1573                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1574                 }
1575                 spin_unlock_irq(&par->int_lock);
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int aty_disable_irq(struct atyfb_par *par)
1582 {
1583         u32 int_cntl;
1584
1585         if (test_and_clear_bit(0, &par->irq_flags)) {
1586                 if (par->vblank.pan_display) {
1587                         par->vblank.pan_display = 0;
1588                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1589                 }
1590                 spin_lock_irq(&par->int_lock);
1591                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1592                 /* disable interrupt */
1593                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1594                 spin_unlock_irq(&par->int_lock);
1595                 free_irq(par->irq, par);
1596         }
1597
1598         return 0;
1599 }
1600
1601 static int atyfb_release(struct fb_info *info, int user)
1602 {
1603         struct atyfb_par *par = (struct atyfb_par *) info->par;
1604         if (user) {
1605                 par->open--;
1606                 mdelay(1);
1607                 wait_for_idle(par);
1608                 if (!par->open) {
1609 #ifdef __sparc__
1610                         int was_mmaped = par->mmaped;
1611
1612                         par->mmaped = 0;
1613
1614                         if (was_mmaped) {
1615                                 struct fb_var_screeninfo var;
1616
1617                                 /* Now reset the default display config, we have no
1618                                  * idea what the program(s) which mmap'd the chip did
1619                                  * to the configuration, nor whether it restored it
1620                                  * correctly.
1621                                  */
1622                                 var = default_var;
1623                                 if (noaccel)
1624                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1625                                 else
1626                                         var.accel_flags |= FB_ACCELF_TEXT;
1627                                 if (var.yres == var.yres_virtual) {
1628                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1629                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1630                                         if (var.yres_virtual < var.yres)
1631                                                 var.yres_virtual = var.yres;
1632                                 }
1633                         }
1634 #endif
1635                         aty_disable_irq(par);
1636                 }
1637         }
1638         return (0);
1639 }
1640
1641     /*
1642      *  Pan or Wrap the Display
1643      *
1644      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1645      */
1646
1647 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1648 {
1649         struct atyfb_par *par = (struct atyfb_par *) info->par;
1650         u32 xres, yres, xoffset, yoffset;
1651
1652         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1653         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1654         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1655                 yres >>= 1;
1656         xoffset = (var->xoffset + 7) & ~7;
1657         yoffset = var->yoffset;
1658         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1659                 return -EINVAL;
1660         info->var.xoffset = xoffset;
1661         info->var.yoffset = yoffset;
1662         if (par->asleep)
1663                 return 0;
1664
1665         set_off_pitch(par, info);
1666         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1667                 par->vblank.pan_display = 1;
1668         } else {
1669                 par->vblank.pan_display = 0;
1670                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1677 {
1678         struct aty_interrupt *vbl;
1679         unsigned int count;
1680         int ret;
1681
1682         switch (crtc) {
1683         case 0:
1684                 vbl = &par->vblank;
1685                 break;
1686         default:
1687                 return -ENODEV;
1688         }
1689
1690         ret = aty_enable_irq(par, 0);
1691         if (ret)
1692                 return ret;
1693
1694         count = vbl->count;
1695         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1696         if (ret < 0) {
1697                 return ret;
1698         }
1699         if (ret == 0) {
1700                 aty_enable_irq(par, 1);
1701                 return -ETIMEDOUT;
1702         }
1703
1704         return 0;
1705 }
1706
1707
1708 #ifdef DEBUG
1709 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1710 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1711
1712 struct atyclk {
1713         u32 ref_clk_per;
1714         u8 pll_ref_div;
1715         u8 mclk_fb_div;
1716         u8 mclk_post_div;       /* 1,2,3,4,8 */
1717         u8 mclk_fb_mult;        /* 2 or 4 */
1718         u8 xclk_post_div;       /* 1,2,3,4,8 */
1719         u8 vclk_fb_div;
1720         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1721         u32 dsp_xclks_per_row;  /* 0-16383 */
1722         u32 dsp_loop_latency;   /* 0-15 */
1723         u32 dsp_precision;      /* 0-7 */
1724         u32 dsp_on;             /* 0-2047 */
1725         u32 dsp_off;            /* 0-2047 */
1726 };
1727
1728 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1729 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1730 #endif
1731
1732 #ifndef FBIO_WAITFORVSYNC
1733 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1734 #endif
1735
1736 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1737 {
1738         struct atyfb_par *par = (struct atyfb_par *) info->par;
1739 #ifdef __sparc__
1740         struct fbtype fbtyp;
1741 #endif
1742
1743         switch (cmd) {
1744 #ifdef __sparc__
1745         case FBIOGTYPE:
1746                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1747                 fbtyp.fb_width = par->crtc.vxres;
1748                 fbtyp.fb_height = par->crtc.vyres;
1749                 fbtyp.fb_depth = info->var.bits_per_pixel;
1750                 fbtyp.fb_cmsize = info->cmap.len;
1751                 fbtyp.fb_size = info->fix.smem_len;
1752                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1753                         return -EFAULT;
1754                 break;
1755 #endif /* __sparc__ */
1756
1757         case FBIO_WAITFORVSYNC:
1758                 {
1759                         u32 crtc;
1760
1761                         if (get_user(crtc, (__u32 __user *) arg))
1762                                 return -EFAULT;
1763
1764                         return aty_waitforvblank(par, crtc);
1765                 }
1766                 break;
1767
1768 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1769         case ATYIO_CLKR:
1770                 if (M64_HAS(INTEGRATED)) {
1771                         struct atyclk clk;
1772                         union aty_pll *pll = &(par->pll);
1773                         u32 dsp_config = pll->ct.dsp_config;
1774                         u32 dsp_on_off = pll->ct.dsp_on_off;
1775                         clk.ref_clk_per = par->ref_clk_per;
1776                         clk.pll_ref_div = pll->ct.pll_ref_div;
1777                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1778                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1779                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1780                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1781                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1782                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1783                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1784                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1785                         clk.dsp_precision = (dsp_config >> 20) & 7;
1786                         clk.dsp_off = dsp_on_off & 0x7ff;
1787                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1788                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1789                                          sizeof(clk)))
1790                                 return -EFAULT;
1791                 } else
1792                         return -EINVAL;
1793                 break;
1794         case ATYIO_CLKW:
1795                 if (M64_HAS(INTEGRATED)) {
1796                         struct atyclk clk;
1797                         union aty_pll *pll = &(par->pll);
1798                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1799                                 return -EFAULT;
1800                         par->ref_clk_per = clk.ref_clk_per;
1801                         pll->ct.pll_ref_div = clk.pll_ref_div;
1802                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1803                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1804                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1805                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1806                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1807                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1808                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1809                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1810                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1811                         /*aty_calc_pll_ct(info, &pll->ct);*/
1812                         aty_set_pll_ct(info, pll);
1813                 } else
1814                         return -EINVAL;
1815                 break;
1816         case ATYIO_FEATR:
1817                 if (get_user(par->features, (u32 __user *) arg))
1818                         return -EFAULT;
1819                 break;
1820         case ATYIO_FEATW:
1821                 if (put_user(par->features, (u32 __user *) arg))
1822                         return -EFAULT;
1823                 break;
1824 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1825         default:
1826                 return -EINVAL;
1827         }
1828         return 0;
1829 }
1830
1831 static int atyfb_sync(struct fb_info *info)
1832 {
1833         struct atyfb_par *par = (struct atyfb_par *) info->par;
1834
1835         if (par->blitter_may_be_busy)
1836                 wait_for_idle(par);
1837         return 0;
1838 }
1839
1840 #ifdef __sparc__
1841 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1842 {
1843         struct atyfb_par *par = (struct atyfb_par *) info->par;
1844         unsigned int size, page, map_size = 0;
1845         unsigned long map_offset = 0;
1846         unsigned long off;
1847         int i;
1848
1849         if (!par->mmap_map)
1850                 return -ENXIO;
1851
1852         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1853                 return -EINVAL;
1854
1855         off = vma->vm_pgoff << PAGE_SHIFT;
1856         size = vma->vm_end - vma->vm_start;
1857
1858         /* To stop the swapper from even considering these pages. */
1859         vma->vm_flags |= (VM_IO | VM_RESERVED);
1860
1861         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1862             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1863                 off += 0x8000000000000000UL;
1864
1865         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1866
1867         /* Each page, see which map applies */
1868         for (page = 0; page < size;) {
1869                 map_size = 0;
1870                 for (i = 0; par->mmap_map[i].size; i++) {
1871                         unsigned long start = par->mmap_map[i].voff;
1872                         unsigned long end = start + par->mmap_map[i].size;
1873                         unsigned long offset = off + page;
1874
1875                         if (start > offset)
1876                                 continue;
1877                         if (offset >= end)
1878                                 continue;
1879
1880                         map_size = par->mmap_map[i].size - (offset - start);
1881                         map_offset =
1882                             par->mmap_map[i].poff + (offset - start);
1883                         break;
1884                 }
1885                 if (!map_size) {
1886                         page += PAGE_SIZE;
1887                         continue;
1888                 }
1889                 if (page + map_size > size)
1890                         map_size = size - page;
1891
1892                 pgprot_val(vma->vm_page_prot) &=
1893                     ~(par->mmap_map[i].prot_mask);
1894                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1895
1896                 if (remap_pfn_range(vma, vma->vm_start + page,
1897                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1898                         return -EAGAIN;
1899
1900                 page += map_size;
1901         }
1902
1903         if (!map_size)
1904                 return -EINVAL;
1905
1906         if (!par->mmaped)
1907                 par->mmaped = 1;
1908         return 0;
1909 }
1910
1911 static struct {
1912         u32 yoffset;
1913         u8 r[2][256];
1914         u8 g[2][256];
1915         u8 b[2][256];
1916 } atyfb_save;
1917
1918 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1919 {
1920         int i, tmp;
1921
1922         for (i = 0; i < 256; i++) {
1923                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1924                 if (M64_HAS(EXTRA_BRIGHT))
1925                         tmp |= 0x2;
1926                 aty_st_8(DAC_CNTL, tmp, par);
1927                 aty_st_8(DAC_MASK, 0xff, par);
1928
1929                 aty_st_8(DAC_R_INDEX, i, par);
1930                 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1931                 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1932                 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1933                 aty_st_8(DAC_W_INDEX, i, par);
1934                 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1935                 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1936                 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1937         }
1938 }
1939
1940 static void atyfb_palette(int enter)
1941 {
1942         struct atyfb_par *par;
1943         struct fb_info *info;
1944         int i;
1945
1946         for (i = 0; i < FB_MAX; i++) {
1947                 info = registered_fb[i];
1948                 if (info && info->fbops == &atyfb_ops) {
1949                         par = (struct atyfb_par *) info->par;
1950
1951                         atyfb_save_palette(par, enter);
1952                         if (enter) {
1953                                 atyfb_save.yoffset = info->var.yoffset;
1954                                 info->var.yoffset = 0;
1955                                 set_off_pitch(par, info);
1956                         } else {
1957                                 info->var.yoffset = atyfb_save.yoffset;
1958                                 set_off_pitch(par, info);
1959                         }
1960                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1961                         break;
1962                 }
1963         }
1964 }
1965 #endif /* __sparc__ */
1966
1967
1968
1969 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1970
1971 #ifdef CONFIG_PPC_PMAC
1972 /* Power management routines. Those are used for PowerBook sleep.
1973  */
1974 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1975 {
1976         u32 pm;
1977         int timeout;
1978
1979         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1980         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1981         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1982         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1983
1984         timeout = 2000;
1985         if (sleep) {
1986                 /* Sleep */
1987                 pm &= ~PWR_MGT_ON;
1988                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990                 udelay(10);
1991                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1992                 pm |= SUSPEND_NOW;
1993                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1994                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1995                 udelay(10);
1996                 pm |= PWR_MGT_ON;
1997                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998                 do {
1999                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000                         mdelay(1);
2001                         if ((--timeout) == 0)
2002                                 break;
2003                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2004         } else {
2005                 /* Wakeup */
2006                 pm &= ~PWR_MGT_ON;
2007                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2008                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2009                 udelay(10);
2010                 pm &= ~SUSPEND_NOW;
2011                 pm |= (PWR_BLON | AUTO_PWR_UP);
2012                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2013                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2014                 udelay(10);
2015                 pm |= PWR_MGT_ON;
2016                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2017                 do {
2018                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2019                         mdelay(1);
2020                         if ((--timeout) == 0)
2021                                 break;
2022                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2023         }
2024         mdelay(500);
2025
2026         return timeout ? 0 : -EIO;
2027 }
2028 #endif
2029
2030 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2031 {
2032         struct fb_info *info = pci_get_drvdata(pdev);
2033         struct atyfb_par *par = (struct atyfb_par *) info->par;
2034
2035         if (state.event == pdev->dev.power.power_state.event)
2036                 return 0;
2037
2038         acquire_console_sem();
2039
2040         fb_set_suspend(info, 1);
2041
2042         /* Idle & reset engine */
2043         wait_for_idle(par);
2044         aty_reset_engine(par);
2045
2046         /* Blank display and LCD */
2047         atyfb_blank(FB_BLANK_POWERDOWN, info);
2048
2049         par->asleep = 1;
2050         par->lock_blank = 1;
2051
2052 #ifdef CONFIG_PPC_PMAC
2053         /* Set chip to "suspend" mode */
2054         if (aty_power_mgmt(1, par)) {
2055                 par->asleep = 0;
2056                 par->lock_blank = 0;
2057                 atyfb_blank(FB_BLANK_UNBLANK, info);
2058                 fb_set_suspend(info, 0);
2059                 release_console_sem();
2060                 return -EIO;
2061         }
2062 #else
2063         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2064 #endif
2065
2066         release_console_sem();
2067
2068         pdev->dev.power.power_state = state;
2069
2070         return 0;
2071 }
2072
2073 static int atyfb_pci_resume(struct pci_dev *pdev)
2074 {
2075         struct fb_info *info = pci_get_drvdata(pdev);
2076         struct atyfb_par *par = (struct atyfb_par *) info->par;
2077
2078         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2079                 return 0;
2080
2081         acquire_console_sem();
2082
2083 #ifdef CONFIG_PPC_PMAC
2084         if (pdev->dev.power.power_state.event == 2)
2085                 aty_power_mgmt(0, par);
2086 #else
2087         pci_set_power_state(pdev, PCI_D0);
2088 #endif
2089
2090         aty_resume_chip(info);
2091
2092         par->asleep = 0;
2093
2094         /* Restore display */
2095         atyfb_set_par(info);
2096
2097         /* Refresh */
2098         fb_set_suspend(info, 0);
2099
2100         /* Unblank */
2101         par->lock_blank = 0;
2102         atyfb_blank(FB_BLANK_UNBLANK, info);
2103
2104         release_console_sem();
2105
2106         pdev->dev.power.power_state = PMSG_ON;
2107
2108         return 0;
2109 }
2110
2111 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2112
2113 /* Backlight */
2114 #ifdef CONFIG_FB_ATY_BACKLIGHT
2115 #define MAX_LEVEL 0xFF
2116
2117 static struct backlight_properties aty_bl_data;
2118
2119 /* Call with fb_info->bl_mutex held */
2120 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2121 {
2122         struct fb_info *info = pci_get_drvdata(par->pdev);
2123         int atylevel;
2124
2125         /* Get and convert the value */
2126         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2127
2128         if (atylevel < 0)
2129                 atylevel = 0;
2130         else if (atylevel > MAX_LEVEL)
2131                 atylevel = MAX_LEVEL;
2132
2133         return atylevel;
2134 }
2135
2136 /* Call with fb_info->bl_mutex held */
2137 static int __aty_bl_update_status(struct backlight_device *bd)
2138 {
2139         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2140         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2141         int level;
2142
2143         if (bd->props->power != FB_BLANK_UNBLANK ||
2144             bd->props->fb_blank != FB_BLANK_UNBLANK)
2145                 level = 0;
2146         else
2147                 level = bd->props->brightness;
2148
2149         reg |= (BLMOD_EN | BIASMOD_EN);
2150         if (level > 0) {
2151                 reg &= ~BIAS_MOD_LEVEL_MASK;
2152                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2153         } else {
2154                 reg &= ~BIAS_MOD_LEVEL_MASK;
2155                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2156         }
2157         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2158
2159         return 0;
2160 }
2161
2162 static int aty_bl_update_status(struct backlight_device *bd)
2163 {
2164         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2165         struct fb_info *info = pci_get_drvdata(par->pdev);
2166         int ret;
2167
2168         mutex_lock(&info->bl_mutex);
2169         ret = __aty_bl_update_status(bd);
2170         mutex_unlock(&info->bl_mutex);
2171
2172         return ret;
2173 }
2174
2175 static int aty_bl_get_brightness(struct backlight_device *bd)
2176 {
2177         return bd->props->brightness;
2178 }
2179
2180 static struct backlight_properties aty_bl_data = {
2181         .owner    = THIS_MODULE,
2182         .get_brightness = aty_bl_get_brightness,
2183         .update_status  = aty_bl_update_status,
2184         .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2185 };
2186
2187 static void aty_bl_set_power(struct fb_info *info, int power)
2188 {
2189         mutex_lock(&info->bl_mutex);
2190
2191         if (info->bl_dev) {
2192                 down(&info->bl_dev->sem);
2193                 info->bl_dev->props->power = power;
2194                 __aty_bl_update_status(info->bl_dev);
2195                 up(&info->bl_dev->sem);
2196         }
2197
2198         mutex_unlock(&info->bl_mutex);
2199 }
2200
2201 static void aty_bl_init(struct atyfb_par *par)
2202 {
2203         struct fb_info *info = pci_get_drvdata(par->pdev);
2204         struct backlight_device *bd;
2205         char name[12];
2206
2207 #ifdef CONFIG_PMAC_BACKLIGHT
2208         if (!pmac_has_backlight_type("ati"))
2209                 return;
2210 #endif
2211
2212         snprintf(name, sizeof(name), "atybl%d", info->node);
2213
2214         bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2215         if (IS_ERR(bd)) {
2216                 info->bl_dev = NULL;
2217                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2218                 goto error;
2219         }
2220
2221         mutex_lock(&info->bl_mutex);
2222         info->bl_dev = bd;
2223         fb_bl_default_curve(info, 0,
2224                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2225                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2226         mutex_unlock(&info->bl_mutex);
2227
2228         down(&bd->sem);
2229         bd->props->brightness = aty_bl_data.max_brightness;
2230         bd->props->power = FB_BLANK_UNBLANK;
2231         bd->props->update_status(bd);
2232         up(&bd->sem);
2233
2234 #ifdef CONFIG_PMAC_BACKLIGHT
2235         mutex_lock(&pmac_backlight_mutex);
2236         if (!pmac_backlight)
2237                 pmac_backlight = bd;
2238         mutex_unlock(&pmac_backlight_mutex);
2239 #endif
2240
2241         printk("aty: Backlight initialized (%s)\n", name);
2242
2243         return;
2244
2245 error:
2246         return;
2247 }
2248
2249 static void aty_bl_exit(struct atyfb_par *par)
2250 {
2251         struct fb_info *info = pci_get_drvdata(par->pdev);
2252
2253 #ifdef CONFIG_PMAC_BACKLIGHT
2254         mutex_lock(&pmac_backlight_mutex);
2255 #endif
2256
2257         mutex_lock(&info->bl_mutex);
2258         if (info->bl_dev) {
2259 #ifdef CONFIG_PMAC_BACKLIGHT
2260                 if (pmac_backlight == info->bl_dev)
2261                         pmac_backlight = NULL;
2262 #endif
2263
2264                 backlight_device_unregister(info->bl_dev);
2265
2266                 printk("aty: Backlight unloaded\n");
2267         }
2268         mutex_unlock(&info->bl_mutex);
2269
2270 #ifdef CONFIG_PMAC_BACKLIGHT
2271         mutex_unlock(&pmac_backlight_mutex);
2272 #endif
2273 }
2274
2275 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2276
2277 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2278 {
2279         const int ragepro_tbl[] = {
2280                 44, 50, 55, 66, 75, 80, 100
2281         };
2282         const int ragexl_tbl[] = {
2283                 50, 66, 75, 83, 90, 95, 100, 105,
2284                 110, 115, 120, 125, 133, 143, 166
2285         };
2286         const int *refresh_tbl;
2287         int i, size;
2288
2289         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2290                 refresh_tbl = ragexl_tbl;
2291                 size = ARRAY_SIZE(ragexl_tbl);
2292         } else {
2293                 refresh_tbl = ragepro_tbl;
2294                 size = ARRAY_SIZE(ragepro_tbl);
2295         }
2296
2297         for (i=0; i < size; i++) {
2298                 if (xclk < refresh_tbl[i])
2299                 break;
2300         }
2301         par->mem_refresh_rate = i;
2302 }
2303
2304     /*
2305      *  Initialisation
2306      */
2307
2308 static struct fb_info *fb_list = NULL;
2309
2310 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2311 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2312                                                 struct fb_var_screeninfo *var)
2313 {
2314         int ret = -EINVAL;
2315
2316         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2317                 *var = default_var;
2318                 var->xres = var->xres_virtual = par->lcd_hdisp;
2319                 var->right_margin = par->lcd_right_margin;
2320                 var->left_margin = par->lcd_hblank_len -
2321                         (par->lcd_right_margin + par->lcd_hsync_dly +
2322                          par->lcd_hsync_len);
2323                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2324                 var->yres = var->yres_virtual = par->lcd_vdisp;
2325                 var->lower_margin = par->lcd_lower_margin;
2326                 var->upper_margin = par->lcd_vblank_len -
2327                         (par->lcd_lower_margin + par->lcd_vsync_len);
2328                 var->vsync_len = par->lcd_vsync_len;
2329                 var->pixclock = par->lcd_pixclock;
2330                 ret = 0;
2331         }
2332
2333         return ret;
2334 }
2335 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2336
2337 static int __devinit aty_init(struct fb_info *info)
2338 {
2339         struct atyfb_par *par = (struct atyfb_par *) info->par;
2340         const char *ramname = NULL, *xtal;
2341         int gtb_memsize, has_var = 0;
2342         struct fb_var_screeninfo var;
2343
2344         init_waitqueue_head(&par->vblank.wait);
2345         spin_lock_init(&par->int_lock);
2346
2347 #ifdef CONFIG_PPC_PMAC
2348         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2349          * and set the frequency manually. */
2350         if (machine_is_compatible("PowerBook2,1")) {
2351                 par->pll_limits.mclk = 70;
2352                 par->pll_limits.xclk = 53;
2353         }
2354 #endif
2355         if (pll)
2356                 par->pll_limits.pll_max = pll;
2357         if (mclk)
2358                 par->pll_limits.mclk = mclk;
2359         if (xclk)
2360                 par->pll_limits.xclk = xclk;
2361
2362         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2363         par->pll_per = 1000000/par->pll_limits.pll_max;
2364         par->mclk_per = 1000000/par->pll_limits.mclk;
2365         par->xclk_per = 1000000/par->pll_limits.xclk;
2366
2367         par->ref_clk_per = 1000000000000ULL / 14318180;
2368         xtal = "14.31818";
2369
2370 #ifdef CONFIG_FB_ATY_GX
2371         if (!M64_HAS(INTEGRATED)) {
2372                 u32 stat0;
2373                 u8 dac_type, dac_subtype, clk_type;
2374                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2375                 par->bus_type = (stat0 >> 0) & 0x07;
2376                 par->ram_type = (stat0 >> 3) & 0x07;
2377                 ramname = aty_gx_ram[par->ram_type];
2378                 /* FIXME: clockchip/RAMDAC probing? */
2379                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2380 #ifdef CONFIG_ATARI
2381                 clk_type = CLK_ATI18818_1;
2382                 dac_type = (stat0 >> 9) & 0x07;
2383                 if (dac_type == 0x07)
2384                         dac_subtype = DAC_ATT20C408;
2385                 else
2386                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2387 #else
2388                 dac_type = DAC_IBMRGB514;
2389                 dac_subtype = DAC_IBMRGB514;
2390                 clk_type = CLK_IBMRGB514;
2391 #endif
2392                 switch (dac_subtype) {
2393                 case DAC_IBMRGB514:
2394                         par->dac_ops = &aty_dac_ibm514;
2395                         break;
2396                 case DAC_ATI68860_B:
2397                 case DAC_ATI68860_C:
2398                         par->dac_ops = &aty_dac_ati68860b;
2399                         break;
2400                 case DAC_ATT20C408:
2401                 case DAC_ATT21C498:
2402                         par->dac_ops = &aty_dac_att21c498;
2403                         break;
2404                 default:
2405                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2406                         par->dac_ops = &aty_dac_unsupported;
2407                         break;
2408                 }
2409                 switch (clk_type) {
2410 #ifdef CONFIG_ATARI
2411                 case CLK_ATI18818_1:
2412                         par->pll_ops = &aty_pll_ati18818_1;
2413                         break;
2414 #else
2415                 case CLK_IBMRGB514:
2416                         par->pll_ops = &aty_pll_ibm514;
2417                         break;
2418 #endif
2419 #if 0 /* dead code */
2420                 case CLK_STG1703:
2421                         par->pll_ops = &aty_pll_stg1703;
2422                         break;
2423                 case CLK_CH8398:
2424                         par->pll_ops = &aty_pll_ch8398;
2425                         break;
2426                 case CLK_ATT20C408:
2427                         par->pll_ops = &aty_pll_att20c408;
2428                         break;
2429 #endif
2430                 default:
2431                         PRINTKI("aty_init: CLK type not implemented yet!");
2432                         par->pll_ops = &aty_pll_unsupported;
2433                         break;
2434                 }
2435         }
2436 #endif /* CONFIG_FB_ATY_GX */
2437 #ifdef CONFIG_FB_ATY_CT
2438         if (M64_HAS(INTEGRATED)) {
2439                 par->dac_ops = &aty_dac_ct;
2440                 par->pll_ops = &aty_pll_ct;
2441                 par->bus_type = PCI;
2442                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2443                 ramname = aty_ct_ram[par->ram_type];
2444                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2445                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2446                         par->pll_limits.mclk = 63;
2447         }
2448
2449         if (M64_HAS(GTB_DSP)) {
2450                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2451
2452                 if (pll_ref_div) {
2453                         int diff1, diff2;
2454                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2455                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2456                         if (diff1 < 0)
2457                                 diff1 = -diff1;
2458                         if (diff2 < 0)
2459                                 diff2 = -diff2;
2460                         if (diff2 < diff1) {
2461                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2462                                 xtal = "29.498928";
2463                         }
2464                 }
2465         }
2466 #endif /* CONFIG_FB_ATY_CT */
2467
2468         /* save previous video mode */
2469         aty_get_crtc(par, &saved_crtc);
2470         if(par->pll_ops->get_pll)
2471                 par->pll_ops->get_pll(info, &saved_pll);
2472
2473         par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2474         gtb_memsize = M64_HAS(GTB_DSP);
2475         if (gtb_memsize)
2476                 switch (par->mem_cntl & 0xF) {  /* 0xF used instead of MEM_SIZE_ALIAS */
2477                 case MEM_SIZE_512K:
2478                         info->fix.smem_len = 0x80000;
2479                         break;
2480                 case MEM_SIZE_1M:
2481                         info->fix.smem_len = 0x100000;
2482                         break;
2483                 case MEM_SIZE_2M_GTB:
2484                         info->fix.smem_len = 0x200000;
2485                         break;
2486                 case MEM_SIZE_4M_GTB:
2487                         info->fix.smem_len = 0x400000;
2488                         break;
2489                 case MEM_SIZE_6M_GTB:
2490                         info->fix.smem_len = 0x600000;
2491                         break;
2492                 case MEM_SIZE_8M_GTB:
2493                         info->fix.smem_len = 0x800000;
2494                         break;
2495                 default:
2496                         info->fix.smem_len = 0x80000;
2497         } else
2498                 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2499                 case MEM_SIZE_512K:
2500                         info->fix.smem_len = 0x80000;
2501                         break;
2502                 case MEM_SIZE_1M:
2503                         info->fix.smem_len = 0x100000;
2504                         break;
2505                 case MEM_SIZE_2M:
2506                         info->fix.smem_len = 0x200000;
2507                         break;
2508                 case MEM_SIZE_4M:
2509                         info->fix.smem_len = 0x400000;
2510                         break;
2511                 case MEM_SIZE_6M:
2512                         info->fix.smem_len = 0x600000;
2513                         break;
2514                 case MEM_SIZE_8M:
2515                         info->fix.smem_len = 0x800000;
2516                         break;
2517                 default:
2518                         info->fix.smem_len = 0x80000;
2519                 }
2520
2521         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2522                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2523                         info->fix.smem_len += 0x400000;
2524         }
2525
2526         if (vram) {
2527                 info->fix.smem_len = vram * 1024;
2528                 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2529                 if (info->fix.smem_len <= 0x80000)
2530                         par->mem_cntl |= MEM_SIZE_512K;
2531                 else if (info->fix.smem_len <= 0x100000)
2532                         par->mem_cntl |= MEM_SIZE_1M;
2533                 else if (info->fix.smem_len <= 0x200000)
2534                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2535                 else if (info->fix.smem_len <= 0x400000)
2536                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2537                 else if (info->fix.smem_len <= 0x600000)
2538                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2539                 else
2540                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2541                 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2542         }
2543
2544         /*
2545          *  Reg Block 0 (CT-compatible block) is at mmio_start
2546          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2547          */
2548         if (M64_HAS(GX)) {
2549                 info->fix.mmio_len = 0x400;
2550                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2551         } else if (M64_HAS(CT)) {
2552                 info->fix.mmio_len = 0x400;
2553                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2554         } else if (M64_HAS(VT)) {
2555                 info->fix.mmio_start -= 0x400;
2556                 info->fix.mmio_len = 0x800;
2557                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2558         } else {/* GT */
2559                 info->fix.mmio_start -= 0x400;
2560                 info->fix.mmio_len = 0x800;
2561                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2562         }
2563
2564         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2565                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2566                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2567                par->pll_limits.mclk, par->pll_limits.xclk);
2568
2569 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2570         if (M64_HAS(INTEGRATED)) {
2571                 int i;
2572                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2573                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2574                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2575                        "debug atyfb: PLL",
2576                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2577                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2578                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2579                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2580                 for (i = 0; i < 40; i++)
2581                         printk(" %02x", aty_ld_pll_ct(i, par));
2582                 printk("\n");
2583         }
2584 #endif
2585         if(par->pll_ops->init_pll)
2586                 par->pll_ops->init_pll(info, &par->pll);
2587         if (par->pll_ops->resume_pll)
2588                 par->pll_ops->resume_pll(info, &par->pll);
2589
2590         /*
2591          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2592          *  unless the auxiliary register aperture is used.
2593          */
2594
2595         if (!par->aux_start &&
2596                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2597                 info->fix.smem_len -= GUI_RESERVE;
2598
2599         /*
2600          *  Disable register access through the linear aperture
2601          *  if the auxiliary aperture is used so we can access
2602          *  the full 8 MB of video RAM on 8 MB boards.
2603          */
2604         if (par->aux_start)
2605                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2606
2607 #ifdef CONFIG_MTRR
2608         par->mtrr_aper = -1;
2609         par->mtrr_reg = -1;
2610         if (!nomtrr) {
2611                 /* Cover the whole resource. */
2612                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2613                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2614                         /* Make a hole for mmio. */
2615                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2616                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2617                         if (par->mtrr_reg < 0) {
2618                                 mtrr_del(par->mtrr_aper, 0, 0);
2619                                 par->mtrr_aper = -1;
2620                         }
2621                  }
2622         }
2623 #endif
2624
2625         info->fbops = &atyfb_ops;
2626         info->pseudo_palette = pseudo_palette;
2627         info->flags = FBINFO_DEFAULT           |
2628                       FBINFO_HWACCEL_IMAGEBLIT |
2629                       FBINFO_HWACCEL_FILLRECT  |
2630                       FBINFO_HWACCEL_COPYAREA  |
2631                       FBINFO_HWACCEL_YPAN;
2632
2633 #ifdef CONFIG_PMAC_BACKLIGHT
2634         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2635                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2636                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2637                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2638         } else
2639 #endif
2640         if (M64_HAS(MOBIL_BUS)) {
2641 #ifdef CONFIG_FB_ATY_BACKLIGHT
2642                 aty_bl_init (par);
2643 #endif
2644         }
2645
2646         memset(&var, 0, sizeof(var));
2647 #ifdef CONFIG_PPC
2648         if (machine_is(powermac)) {
2649                 /*
2650                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2651                  *         applies to all Mac video cards
2652                  */
2653                 if (mode) {
2654                         if (mac_find_mode(&var, info, mode, 8))
2655                                 has_var = 1;
2656                 } else {
2657                         if (default_vmode == VMODE_CHOOSE) {
2658                                 int sense;
2659                                 if (M64_HAS(G3_PB_1024x768))
2660                                         /* G3 PowerBook with 1024x768 LCD */
2661                                         default_vmode = VMODE_1024_768_60;
2662                                 else if (machine_is_compatible("iMac"))
2663                                         default_vmode = VMODE_1024_768_75;
2664                                 else if (machine_is_compatible
2665                                          ("PowerBook2,1"))
2666                                         /* iBook with 800x600 LCD */
2667                                         default_vmode = VMODE_800_600_60;
2668                                 else
2669                                         default_vmode = VMODE_640_480_67;
2670                                 sense = read_aty_sense(par);
2671                                 PRINTKI("monitor sense=%x, mode %d\n",
2672                                         sense,  mac_map_monitor_sense(sense));
2673                         }
2674                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2675                                 default_vmode = VMODE_640_480_60;
2676                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2677                                 default_cmode = CMODE_8;
2678                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2679                                                &var))
2680                                 has_var = 1;
2681                 }
2682         }
2683
2684 #endif /* !CONFIG_PPC */
2685
2686 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2687         if (!atyfb_get_timings_from_lcd(par, &var))
2688                 has_var = 1;
2689 #endif
2690
2691         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2692                 has_var = 1;
2693
2694         if (!has_var)
2695                 var = default_var;
2696
2697         if (noaccel)
2698                 var.accel_flags &= ~FB_ACCELF_TEXT;
2699         else
2700                 var.accel_flags |= FB_ACCELF_TEXT;
2701
2702         if (comp_sync != -1) {
2703                 if (!comp_sync)
2704                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2705                 else
2706                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2707         }
2708
2709         if (var.yres == var.yres_virtual) {
2710                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2711                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2712                 if (var.yres_virtual < var.yres)
2713                         var.yres_virtual = var.yres;
2714         }
2715
2716         if (atyfb_check_var(&var, info)) {
2717                 PRINTKE("can't set default video mode\n");
2718                 goto aty_init_exit;
2719         }
2720
2721 #ifdef __sparc__
2722         atyfb_save_palette(par, 0);
2723 #endif
2724
2725 #ifdef CONFIG_FB_ATY_CT
2726         if (!noaccel && M64_HAS(INTEGRATED))
2727                 aty_init_cursor(info);
2728 #endif /* CONFIG_FB_ATY_CT */
2729         info->var = var;
2730
2731         fb_alloc_cmap(&info->cmap, 256, 0);
2732
2733         if (register_framebuffer(info) < 0)
2734                 goto aty_init_exit;
2735
2736         fb_list = info;
2737
2738         PRINTKI("fb%d: %s frame buffer device on %s\n",
2739                 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2740         return 0;
2741
2742 aty_init_exit:
2743         /* restore video mode */
2744         aty_set_crtc(par, &saved_crtc);
2745         par->pll_ops->set_pll(info, &saved_pll);
2746
2747 #ifdef CONFIG_MTRR
2748         if (par->mtrr_reg >= 0) {
2749             mtrr_del(par->mtrr_reg, 0, 0);
2750             par->mtrr_reg = -1;
2751         }
2752         if (par->mtrr_aper >= 0) {
2753             mtrr_del(par->mtrr_aper, 0, 0);
2754             par->mtrr_aper = -1;
2755         }
2756 #endif
2757         return -1;
2758 }
2759
2760 static void aty_resume_chip(struct fb_info *info)
2761 {
2762         struct atyfb_par *par = info->par;
2763
2764         aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2765
2766         if (par->pll_ops->resume_pll)
2767                 par->pll_ops->resume_pll(info, &par->pll);
2768
2769         if (par->aux_start)
2770                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2771 }
2772
2773 #ifdef CONFIG_ATARI
2774 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2775 {
2776         char *p;
2777         unsigned long vmembase, size, guiregbase;
2778
2779         PRINTKI("store_video_par() '%s' \n", video_str);
2780
2781         if (!(p = strsep(&video_str, ";")) || !*p)
2782                 goto mach64_invalid;
2783         vmembase = simple_strtoul(p, NULL, 0);
2784         if (!(p = strsep(&video_str, ";")) || !*p)
2785                 goto mach64_invalid;
2786         size = simple_strtoul(p, NULL, 0);
2787         if (!(p = strsep(&video_str, ";")) || !*p)
2788                 goto mach64_invalid;
2789         guiregbase = simple_strtoul(p, NULL, 0);
2790
2791         phys_vmembase[m64_num] = vmembase;
2792         phys_size[m64_num] = size;
2793         phys_guiregbase[m64_num] = guiregbase;
2794         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2795                guiregbase);
2796         return 0;
2797
2798       mach64_invalid:
2799         phys_vmembase[m64_num] = 0;
2800         return -1;
2801 }
2802 #endif /* CONFIG_ATARI */
2803
2804     /*
2805      *  Blank the display.
2806      */
2807
2808 static int atyfb_blank(int blank, struct fb_info *info)
2809 {
2810         struct atyfb_par *par = (struct atyfb_par *) info->par;
2811         u32 gen_cntl;
2812
2813         if (par->lock_blank || par->asleep)
2814                 return 0;
2815
2816 #ifdef CONFIG_FB_ATY_BACKLIGHT
2817         if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2818                 aty_bl_set_power(info, FB_BLANK_POWERDOWN);
2819 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2820         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2821             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2822                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2823                 pm &= ~PWR_BLON;
2824                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2825         }
2826 #endif
2827
2828         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2829         gen_cntl &= ~0x400004c;
2830         switch (blank) {
2831                 case FB_BLANK_UNBLANK:
2832                         break;
2833                 case FB_BLANK_NORMAL:
2834                         gen_cntl |= 0x4000040;
2835                         break;
2836                 case FB_BLANK_VSYNC_SUSPEND:
2837                         gen_cntl |= 0x4000048;
2838                         break;
2839                 case FB_BLANK_HSYNC_SUSPEND:
2840                         gen_cntl |= 0x4000044;
2841                         break;
2842                 case FB_BLANK_POWERDOWN:
2843                         gen_cntl |= 0x400004c;
2844                         break;
2845         }
2846         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2847
2848 #ifdef CONFIG_FB_ATY_BACKLIGHT
2849         if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2850                 aty_bl_set_power(info, FB_BLANK_UNBLANK);
2851 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2852         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2853             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2854                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2855                 pm |= PWR_BLON;
2856                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2857         }
2858 #endif
2859
2860         return 0;
2861 }
2862
2863 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2864                        const struct atyfb_par *par)
2865 {
2866         aty_st_8(DAC_W_INDEX, regno, par);
2867         aty_st_8(DAC_DATA, red, par);
2868         aty_st_8(DAC_DATA, green, par);
2869         aty_st_8(DAC_DATA, blue, par);
2870 }
2871
2872     /*
2873      *  Set a single color register. The values supplied are already
2874      *  rounded down to the hardware's capabilities (according to the
2875      *  entries in the var structure). Return != 0 for invalid regno.
2876      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2877      */
2878
2879 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2880         u_int transp, struct fb_info *info)
2881 {
2882         struct atyfb_par *par = (struct atyfb_par *) info->par;
2883         int i, depth;
2884         u32 *pal = info->pseudo_palette;
2885
2886         depth = info->var.bits_per_pixel;
2887         if (depth == 16)
2888                 depth = (info->var.green.length == 5) ? 15 : 16;
2889
2890         if (par->asleep)
2891                 return 0;
2892
2893         if (regno > 255 ||
2894             (depth == 16 && regno > 63) ||
2895             (depth == 15 && regno > 31))
2896                 return 1;
2897
2898         red >>= 8;
2899         green >>= 8;
2900         blue >>= 8;
2901
2902         par->palette[regno].red = red;
2903         par->palette[regno].green = green;
2904         par->palette[regno].blue = blue;
2905
2906         if (regno < 16) {
2907                 switch (depth) {
2908                 case 15:
2909                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2910                         break;
2911                 case 16:
2912                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2913                         break;
2914                 case 24:
2915                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2916                         break;
2917                 case 32:
2918                         i = (regno << 8) | regno;
2919                         pal[regno] = (i << 16) | i;
2920                         break;
2921                 }
2922         }
2923
2924         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2925         if (M64_HAS(EXTRA_BRIGHT))
2926                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2927         aty_st_8(DAC_CNTL, i, par);
2928         aty_st_8(DAC_MASK, 0xff, par);
2929
2930         if (M64_HAS(INTEGRATED)) {
2931                 if (depth == 16) {
2932                         if (regno < 32)
2933                                 aty_st_pal(regno << 3, red,
2934                                            par->palette[regno<<1].green,
2935                                            blue, par);
2936                         red = par->palette[regno>>1].red;
2937                         blue = par->palette[regno>>1].blue;
2938                         regno <<= 2;
2939                 } else if (depth == 15) {
2940                         regno <<= 3;
2941                         for(i = 0; i < 8; i++) {
2942                             aty_st_pal(regno + i, red, green, blue, par);
2943                         }
2944                 }
2945         }
2946         aty_st_pal(regno, red, green, blue, par);
2947
2948         return 0;
2949 }
2950
2951 #ifdef CONFIG_PCI
2952
2953 #ifdef __sparc__
2954
2955 extern void (*prom_palette) (int);
2956
2957 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2958                         struct fb_info *info, unsigned long addr)
2959 {
2960         extern int con_is_present(void);
2961
2962         struct atyfb_par *par = info->par;
2963         struct pcidev_cookie *pcp;
2964         char prop[128];
2965         int node, len, i, j, ret;
2966         u32 mem, chip_id;
2967
2968         /* Do not attach when we have a serial console. */
2969         if (!con_is_present())
2970                 return -ENXIO;
2971
2972         /*
2973          * Map memory-mapped registers.
2974          */
2975         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2976         info->fix.mmio_start = addr + 0x7ffc00UL;
2977
2978         /*
2979          * Map in big-endian aperture.
2980          */
2981         info->screen_base = (char *) (addr + 0x800000UL);
2982         info->fix.smem_start = addr + 0x800000UL;
2983
2984         /*
2985          * Figure mmap addresses from PCI config space.
2986          * Split Framebuffer in big- and little-endian halfs.
2987          */
2988         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2989                 /* nothing */ ;
2990         j = i + 4;
2991
2992         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2993         if (!par->mmap_map) {
2994                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2995                 return -ENOMEM;
2996         }
2997         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2998
2999         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
3000                 struct resource *rp = &pdev->resource[i];
3001                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3002                 unsigned long base;
3003                 u32 size, pbase;
3004
3005                 base = rp->start;
3006
3007                 io = (rp->flags & IORESOURCE_IO);
3008
3009                 size = rp->end - base + 1;
3010
3011                 pci_read_config_dword(pdev, breg, &pbase);
3012
3013                 if (io)
3014                         size &= ~1;
3015
3016                 /*
3017                  * Map the framebuffer a second time, this time without
3018                  * the braindead _PAGE_IE setting. This is used by the
3019                  * fixed Xserver, but we need to maintain the old mapping
3020                  * to stay compatible with older ones...
3021                  */
3022                 if (base == addr) {
3023                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3024                         par->mmap_map[j].poff = base & PAGE_MASK;
3025                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3026                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3027                         par->mmap_map[j].prot_flag = _PAGE_E;
3028                         j++;
3029                 }
3030
3031                 /*
3032                  * Here comes the old framebuffer mapping with _PAGE_IE
3033                  * set for the big endian half of the framebuffer...
3034                  */
3035                 if (base == addr) {
3036                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3037                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3038                         par->mmap_map[j].size = 0x800000;
3039                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3040                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3041                         size -= 0x800000;
3042                         j++;
3043                 }
3044
3045                 par->mmap_map[j].voff = pbase & PAGE_MASK;
3046                 par->mmap_map[j].poff = base & PAGE_MASK;
3047                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3048                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3049                 par->mmap_map[j].prot_flag = _PAGE_E;
3050                 j++;
3051         }
3052
3053         if((ret = correct_chipset(par)))
3054                 return ret;
3055
3056         if (IS_XL(pdev->device)) {
3057                 /*
3058                  * Fix PROMs idea of MEM_CNTL settings...
3059                  */
3060                 mem = aty_ld_le32(MEM_CNTL, par);
3061                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3062                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3063                         switch (mem & 0x0f) {
3064                         case 3:
3065                                 mem = (mem & ~(0x0f)) | 2;
3066                                 break;
3067                         case 7:
3068                                 mem = (mem & ~(0x0f)) | 3;
3069                                 break;
3070                         case 9:
3071                                 mem = (mem & ~(0x0f)) | 4;
3072                                 break;
3073                         case 11:
3074                                 mem = (mem & ~(0x0f)) | 5;
3075                                 break;
3076                         default:
3077                                 break;
3078                         }
3079                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3080                                 mem &= ~(0x00700000);
3081                 }
3082                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3083                 aty_st_le32(MEM_CNTL, mem, par);
3084         }
3085
3086         /*
3087          * If this is the console device, we will set default video
3088          * settings to what the PROM left us with.
3089          */
3090         node = prom_getchild(prom_root_node);
3091         node = prom_searchsiblings(node, "aliases");
3092         if (node) {
3093                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3094                 if (len > 0) {
3095                         prop[len] = '\0';
3096                         node = prom_finddevice(prop);
3097                 } else
3098                         node = 0;
3099         }
3100
3101         pcp = pdev->sysdata;
3102         if (node == pcp->prom_node->node) {
3103                 struct fb_var_screeninfo *var = &default_var;
3104                 unsigned int N, P, Q, M, T, R;
3105                 u32 v_total, h_total;
3106                 struct crtc crtc;
3107                 u8 pll_regs[16];
3108                 u8 clock_cntl;
3109
3110                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3111                 crtc.vyres = prom_getintdefault(node, "height", 768);
3112                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3113                 var->xoffset = var->yoffset = 0;
3114                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3115                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3116                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3117                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3118                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3119                 aty_crtc_to_var(&crtc, var);
3120
3121                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3122                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3123
3124                 /*
3125                  * Read the PLL to figure actual Refresh Rate.
3126                  */
3127                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3128                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3129                 for (i = 0; i < 16; i++)
3130                         pll_regs[i] = aty_ld_pll_ct(i, par);
3131
3132                 /*
3133                  * PLL Reference Divider M:
3134                  */
3135                 M = pll_regs[2];
3136
3137                 /*
3138                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3139                  */
3140                 N = pll_regs[7 + (clock_cntl & 3)];
3141
3142                 /*
3143                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3144                  */
3145                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3146
3147                 /*
3148                  * PLL Divider Q:
3149                  */
3150                 Q = N / P;
3151
3152                 /*
3153                  * Target Frequency:
3154                  *
3155                  *      T * M
3156                  * Q = -------
3157                  *      2 * R
3158                  *
3159                  * where R is XTALIN (= 14318 or 29498 kHz).
3160                  */
3161                 if (IS_XL(pdev->device))
3162                         R = 29498;
3163                 else
3164                         R = 14318;
3165
3166                 T = 2 * Q * R / M;
3167
3168                 default_var.pixclock = 1000000000 / T;
3169         }
3170
3171         return 0;
3172 }
3173
3174 #else /* __sparc__ */
3175
3176 #ifdef __i386__
3177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3178 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3179 {
3180         u32 driv_inf_tab, sig;
3181         u16 lcd_ofs;
3182
3183         /* To support an LCD panel, we should know it's dimensions and
3184          *  it's desired pixel clock.
3185          * There are two ways to do it:
3186          *  - Check the startup video mode and calculate the panel
3187          *    size from it. This is unreliable.
3188          *  - Read it from the driver information table in the video BIOS.
3189         */
3190         /* Address of driver information table is at offset 0x78. */
3191         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3192
3193         /* Check for the driver information table signature. */
3194         sig = (*(u32 *)driv_inf_tab);
3195         if ((sig == 0x54504c24) || /* Rage LT pro */
3196                 (sig == 0x544d5224) || /* Rage mobility */
3197                 (sig == 0x54435824) || /* Rage XC */
3198                 (sig == 0x544c5824)) { /* Rage XL */
3199                 PRINTKI("BIOS contains driver information table.\n");
3200                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3201                 par->lcd_table = 0;
3202                 if (lcd_ofs != 0) {
3203                         par->lcd_table = bios_base + lcd_ofs;
3204                 }
3205         }
3206
3207         if (par->lcd_table != 0) {
3208                 char model[24];
3209                 char strbuf[16];
3210                 char refresh_rates_buf[100];
3211                 int id, tech, f, i, m, default_refresh_rate;
3212                 char *txtcolour;
3213                 char *txtmonitor;
3214                 char *txtdual;
3215                 char *txtformat;
3216                 u16 width, height, panel_type, refresh_rates;
3217                 u16 *lcdmodeptr;
3218                 u32 format;
3219                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3220                 /* The most important information is the panel size at
3221                  * offset 25 and 27, but there's some other nice information
3222                  * which we print to the screen.
3223                  */
3224                 id = *(u8 *)par->lcd_table;
3225                 strncpy(model,(char *)par->lcd_table+1,24);
3226                 model[23]=0;
3227
3228                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3229                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3230                 panel_type = *(u16 *)(par->lcd_table+29);
3231                 if (panel_type & 1)
3232                         txtcolour = "colour";
3233                 else
3234                         txtcolour = "monochrome";
3235                 if (panel_type & 2)
3236                         txtdual = "dual (split) ";
3237                 else
3238                         txtdual = "";
3239                 tech = (panel_type>>2) & 63;
3240                 switch (tech) {
3241                 case 0:
3242                         txtmonitor = "passive matrix";
3243                         break;
3244                 case 1:
3245                         txtmonitor = "active matrix";
3246                         break;
3247                 case 2:
3248                         txtmonitor = "active addressed STN";
3249                         break;
3250                 case 3:
3251                         txtmonitor = "EL";
3252                         break;
3253                 case 4:
3254                         txtmonitor = "plasma";
3255                         break;
3256                 default:
3257                         txtmonitor = "unknown";
3258                 }
3259                 format = *(u32 *)(par->lcd_table+57);
3260                 if (tech == 0 || tech == 2) {
3261                         switch (format & 7) {
3262                         case 0:
3263                                 txtformat = "12 bit interface";
3264                                 break;
3265                         case 1:
3266                                 txtformat = "16 bit interface";
3267                                 break;
3268                         case 2:
3269                                 txtformat = "24 bit interface";
3270                                 break;
3271                         default:
3272                                 txtformat = "unkown format";
3273                         }
3274                 } else {
3275                         switch (format & 7) {
3276                         case 0:
3277                                 txtformat = "8 colours";
3278                                 break;
3279                         case 1:
3280                                 txtformat = "512 colours";
3281                                 break;
3282                         case 2:
3283                                 txtformat = "4096 colours";
3284                                 break;
3285                         case 4:
3286                                 txtformat = "262144 colours (LT mode)";
3287                                 break;
3288                         case 5:
3289                                 txtformat = "16777216 colours";
3290                                 break;
3291                         case 6:
3292                                 txtformat = "262144 colours (FDPI-2 mode)";
3293                                 break;
3294                         default:
3295                                 txtformat = "unkown format";
3296                         }
3297                 }
3298                 PRINTKI("%s%s %s monitor detected: %s\n",
3299                         txtdual ,txtcolour, txtmonitor, model);
3300                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3301                         id, width, height, txtformat);
3302                 refresh_rates_buf[0] = 0;
3303                 refresh_rates = *(u16 *)(par->lcd_table+62);
3304                 m = 1;
3305                 f = 0;
3306                 for (i=0;i<16;i++) {
3307                         if (refresh_rates & m) {
3308                                 if (f == 0) {
3309                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3310                                         f++;
3311                                 } else {
3312                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3313                                 }
3314                                 strcat(refresh_rates_buf,strbuf);
3315                         }
3316                         m = m << 1;
3317                 }
3318                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3319                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3320                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3321                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3322                 /* We now need to determine the crtc parameters for the
3323                  * LCD monitor. This is tricky, because they are not stored
3324                  * individually in the BIOS. Instead, the BIOS contains a
3325                  * table of display modes that work for this monitor.
3326                  *
3327                  * The idea is that we search for a mode of the same dimensions
3328                  * as the dimensions of the LCD monitor. Say our LCD monitor
3329                  * is 800x600 pixels, we search for a 800x600 monitor.
3330                  * The CRTC parameters we find here are the ones that we need
3331                  * to use to simulate other resolutions on the LCD screen.
3332                  */
3333                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3334                 while (*lcdmodeptr != 0) {
3335                         u32 modeptr;
3336                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3337                         modeptr = bios_base + *lcdmodeptr;
3338
3339                         mwidth = *((u16 *)(modeptr+0));
3340                         mheight = *((u16 *)(modeptr+2));
3341
3342                         if (mwidth == width && mheight == height) {
3343                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3344                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3345                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3346                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3347                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3348                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3349
3350                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3351                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3352                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3353                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3354
3355                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3356                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3357                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3358                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3359
3360                                 par->lcd_vtotal++;
3361                                 par->lcd_vdisp++;
3362                                 lcd_vsync_start++;
3363
3364                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3365                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3366                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3367                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3368                                 break;
3369                         }
3370
3371                         lcdmodeptr++;
3372                 }
3373                 if (*lcdmodeptr == 0) {
3374                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3375                         /* To do: Switch to CRT if possible. */
3376                 } else {
3377                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3378                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3379                                 par->lcd_hdisp,
3380                                 par->lcd_hdisp + par->lcd_right_margin,
3381                                 par->lcd_hdisp + par->lcd_right_margin
3382                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3383                                 par->lcd_htotal,
3384                                 par->lcd_vdisp,
3385                                 par->lcd_vdisp + par->lcd_lower_margin,
3386                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3387                                 par->lcd_vtotal);
3388                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3389                                 par->lcd_pixclock,
3390                                 par->lcd_hblank_len - (par->lcd_right_margin +
3391                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3392                                 par->lcd_hdisp,
3393                                 par->lcd_right_margin,
3394                                 par->lcd_hsync_len,
3395                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3396                                 par->lcd_vdisp,
3397                                 par->lcd_lower_margin,
3398                                 par->lcd_vsync_len);
3399                 }
3400         }
3401 }
3402 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3403
3404 static int __devinit init_from_bios(struct atyfb_par *par)
3405 {
3406         u32 bios_base, rom_addr;
3407         int ret;
3408
3409         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3410         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3411
3412         /* The BIOS starts with 0xaa55. */
3413         if (*((u16 *)bios_base) == 0xaa55) {
3414
3415                 u8 *bios_ptr;
3416                 u16 rom_table_offset, freq_table_offset;
3417                 PLL_BLOCK_MACH64 pll_block;
3418
3419                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3420
3421                 /* check for frequncy table */
3422                 bios_ptr = (u8*)bios_base;
3423                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3424                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3425                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3426
3427                 PRINTKI("BIOS frequency table:\n");
3428                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3429                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3430                         pll_block.ref_freq, pll_block.ref_divider);
3431                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3432                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3433                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3434
3435                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3436                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3437                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3438                 par->pll_limits.ref_div = pll_block.ref_divider;
3439                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3440                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3441                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3442                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3443 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3444                 aty_init_lcd(par, bios_base);
3445 #endif
3446                 ret = 0;
3447         } else {
3448                 PRINTKE("no BIOS frequency table found, use parameters\n");
3449                 ret = -ENXIO;
3450         }
3451         iounmap((void* __iomem )bios_base);
3452
3453         return ret;
3454 }
3455 #endif /* __i386__ */
3456
3457 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3458 {
3459         struct atyfb_par *par = info->par;
3460         u16 tmp;
3461         unsigned long raddr;
3462         struct resource *rrp;
3463         int ret = 0;
3464
3465         raddr = addr + 0x7ff000UL;
3466         rrp = &pdev->resource[2];
3467         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3468                 par->aux_start = rrp->start;
3469                 par->aux_size = rrp->end - rrp->start + 1;
3470                 raddr = rrp->start;
3471                 PRINTKI("using auxiliary register aperture\n");
3472         }
3473
3474         info->fix.mmio_start = raddr;
3475         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3476         if (par->ati_regbase == 0)
3477                 return -ENOMEM;
3478
3479         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3480         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3481
3482         /*
3483          * Enable memory-space accesses using config-space
3484          * command register.
3485          */
3486         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3487         if (!(tmp & PCI_COMMAND_MEMORY)) {
3488                 tmp |= PCI_COMMAND_MEMORY;
3489                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3490         }
3491 #ifdef __BIG_ENDIAN
3492         /* Use the big-endian aperture */
3493         addr += 0x800000;
3494 #endif
3495
3496         /* Map in frame buffer */
3497         info->fix.smem_start = addr;
3498         info->screen_base = ioremap(addr, 0x800000);
3499         if (info->screen_base == NULL) {
3500                 ret = -ENOMEM;
3501                 goto atyfb_setup_generic_fail;
3502         }
3503
3504         if((ret = correct_chipset(par)))
3505                 goto atyfb_setup_generic_fail;
3506 #ifdef __i386__
3507         if((ret = init_from_bios(par)))
3508                 goto atyfb_setup_generic_fail;
3509 #endif
3510         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3511                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3512         else
3513                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3514
3515         /* according to ATI, we should use clock 3 for acelerated mode */
3516         par->clk_wr_offset = 3;
3517
3518         return 0;
3519
3520 atyfb_setup_generic_fail:
3521         iounmap(par->ati_regbase);
3522         par->ati_regbase = NULL;
3523         if (info->screen_base) {
3524                 iounmap(info->screen_base);
3525                 info->screen_base = NULL;
3526         }
3527         return ret;
3528 }
3529
3530 #endif /* !__sparc__ */
3531
3532 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3533 {
3534         unsigned long addr, res_start, res_size;
3535         struct fb_info *info;
3536         struct resource *rp;
3537         struct atyfb_par *par;
3538         int i, rc = -ENOMEM;
3539
3540         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3541                 if (pdev->device == aty_chips[i].pci_id)
3542                         break;
3543
3544         if (i < 0)
3545                 return -ENODEV;
3546
3547         /* Enable device in PCI config */
3548         if (pci_enable_device(pdev)) {
3549                 PRINTKE("Cannot enable PCI device\n");
3550                 return -ENXIO;
3551         }
3552
3553         /* Find which resource to use */
3554         rp = &pdev->resource[0];
3555         if (rp->flags & IORESOURCE_IO)
3556                 rp = &pdev->resource[1];
3557         addr = rp->start;
3558         if (!addr)
3559                 return -ENXIO;
3560
3561         /* Reserve space */
3562         res_start = rp->start;
3563         res_size = rp->end - rp->start + 1;
3564         if (!request_mem_region (res_start, res_size, "atyfb"))
3565                 return -EBUSY;
3566
3567         /* Allocate framebuffer */
3568         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3569         if (!info) {
3570                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3571                 return -ENOMEM;
3572         }
3573         par = info->par;
3574         info->fix = atyfb_fix;
3575         info->device = &pdev->dev;
3576         par->pci_id = aty_chips[i].pci_id;
3577         par->res_start = res_start;
3578         par->res_size = res_size;
3579         par->irq = pdev->irq;
3580         par->pdev = pdev;
3581
3582         /* Setup "info" structure */
3583 #ifdef __sparc__
3584         rc = atyfb_setup_sparc(pdev, info, addr);
3585 #else
3586         rc = atyfb_setup_generic(pdev, info, addr);
3587 #endif
3588         if (rc)
3589                 goto err_release_mem;
3590
3591         pci_set_drvdata(pdev, info);
3592
3593         /* Init chip & register framebuffer */
3594         if (aty_init(info))
3595                 goto err_release_io;
3596
3597 #ifdef __sparc__
3598         if (!prom_palette)
3599                 prom_palette = atyfb_palette;
3600
3601         /*
3602          * Add /dev/fb mmap values.
3603          */
3604         par->mmap_map[0].voff = 0x8000000000000000UL;
3605         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3606         par->mmap_map[0].size = info->fix.smem_len;
3607         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3608         par->mmap_map[0].prot_flag = _PAGE_E;
3609         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3610         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3611         par->mmap_map[1].size = PAGE_SIZE;
3612         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3613         par->mmap_map[1].prot_flag = _PAGE_E;
3614 #endif /* __sparc__ */
3615
3616         return 0;
3617
3618 err_release_io:
3619 #ifdef __sparc__
3620         kfree(par->mmap_map);
3621 #else
3622         if (par->ati_regbase)
3623                 iounmap(par->ati_regbase);
3624         if (info->screen_base)
3625                 iounmap(info->screen_base);
3626 #endif
3627 err_release_mem:
3628         if (par->aux_start)
3629                 release_mem_region(par->aux_start, par->aux_size);
3630
3631         release_mem_region(par->res_start, par->res_size);
3632         framebuffer_release(info);
3633
3634         return rc;
3635 }
3636
3637 #endif /* CONFIG_PCI */
3638
3639 #ifdef CONFIG_ATARI
3640
3641 static int __init atyfb_atari_probe(void)
3642 {
3643         struct atyfb_par *par;
3644         struct fb_info *info;
3645         int m64_num;
3646         u32 clock_r;
3647         int num_found = 0;
3648
3649         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3650                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3651                     !phys_guiregbase[m64_num]) {
3652                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3653                         continue;
3654                 }
3655
3656                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3657                 if (!info) {
3658                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3659                         return -ENOMEM;
3660                 }
3661                 par = info->par;
3662
3663                 info->fix = atyfb_fix;
3664
3665                 par->irq = (unsigned int) -1; /* something invalid */
3666
3667                 /*
3668                  *  Map the video memory (physical address given) to somewhere in the
3669                  *  kernel address space.
3670                  */
3671                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3672                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3673                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3674                                                 0xFC00ul;
3675                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3676
3677                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3678                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3679
3680                 switch (clock_r & 0x003F) {
3681                 case 0x12:
3682                         par->clk_wr_offset = 3; /*  */
3683                         break;
3684                 case 0x34:
3685                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3686                         break;
3687                 case 0x16:
3688                         par->clk_wr_offset = 1; /*  */
3689                         break;
3690                 case 0x38:
3691                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3692                         break;
3693                 }
3694
3695                 /* Fake pci_id for correct_chipset() */
3696                 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3697                 case 0x00d7:
3698                         par->pci_id = PCI_CHIP_MACH64GX;
3699                         break;
3700                 case 0x0057:
3701                         par->pci_id = PCI_CHIP_MACH64CX;
3702                         break;
3703                 default:
3704                         break;
3705                 }
3706
3707                 if (correct_chipset(par) || aty_init(info)) {
3708                         iounmap(info->screen_base);
3709                         iounmap(par->ati_regbase);
3710                         framebuffer_release(info);
3711                 } else {
3712                         num_found++;
3713                 }
3714         }
3715
3716         return num_found ? 0 : -ENXIO;
3717 }
3718
3719 #endif /* CONFIG_ATARI */
3720
3721 #ifdef CONFIG_PCI
3722
3723 static void __devexit atyfb_remove(struct fb_info *info)
3724 {
3725         struct atyfb_par *par = (struct atyfb_par *) info->par;
3726
3727         /* restore video mode */
3728         aty_set_crtc(par, &saved_crtc);
3729         par->pll_ops->set_pll(info, &saved_pll);
3730
3731 #ifdef CONFIG_FB_ATY_BACKLIGHT
3732         if (M64_HAS(MOBIL_BUS))
3733                 aty_bl_exit(par);
3734 #endif
3735
3736         unregister_framebuffer(info);
3737
3738 #ifdef CONFIG_MTRR
3739         if (par->mtrr_reg >= 0) {
3740             mtrr_del(par->mtrr_reg, 0, 0);
3741             par->mtrr_reg = -1;
3742         }
3743         if (par->mtrr_aper >= 0) {
3744             mtrr_del(par->mtrr_aper, 0, 0);
3745             par->mtrr_aper = -1;
3746         }
3747 #endif
3748 #ifndef __sparc__
3749         if (par->ati_regbase)
3750                 iounmap(par->ati_regbase);
3751         if (info->screen_base)
3752                 iounmap(info->screen_base);
3753 #ifdef __BIG_ENDIAN
3754         if (info->sprite.addr)
3755                 iounmap(info->sprite.addr);
3756 #endif
3757 #endif
3758 #ifdef __sparc__
3759         kfree(par->mmap_map);
3760 #endif
3761         if (par->aux_start)
3762                 release_mem_region(par->aux_start, par->aux_size);
3763
3764         if (par->res_start)
3765                 release_mem_region(par->res_start, par->res_size);
3766
3767         framebuffer_release(info);
3768 }
3769
3770
3771 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3772 {
3773         struct fb_info *info = pci_get_drvdata(pdev);
3774
3775         atyfb_remove(info);
3776 }
3777
3778 /*
3779  * This driver uses its own matching table. That will be more difficult
3780  * to fix, so for now, we just match against any ATI ID and let the
3781  * probe() function find out what's up. That also mean we don't have
3782  * a module ID table though.
3783  */
3784 static struct pci_device_id atyfb_pci_tbl[] = {
3785         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3786           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3787         { 0, }
3788 };
3789
3790 static struct pci_driver atyfb_driver = {
3791         .name           = "atyfb",
3792         .id_table       = atyfb_pci_tbl,
3793         .probe          = atyfb_pci_probe,
3794         .remove         = __devexit_p(atyfb_pci_remove),
3795 #ifdef CONFIG_PM
3796         .suspend        = atyfb_pci_suspend,
3797         .resume         = atyfb_pci_resume,
3798 #endif /* CONFIG_PM */
3799 };
3800
3801 #endif /* CONFIG_PCI */
3802
3803 #ifndef MODULE
3804 static int __init atyfb_setup(char *options)
3805 {
3806         char *this_opt;
3807
3808         if (!options || !*options)
3809                 return 0;
3810
3811         while ((this_opt = strsep(&options, ",")) != NULL) {
3812                 if (!strncmp(this_opt, "noaccel", 7)) {
3813                         noaccel = 1;
3814 #ifdef CONFIG_MTRR
3815                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3816                         nomtrr = 1;
3817 #endif
3818                 } else if (!strncmp(this_opt, "vram:", 5))
3819                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3820                 else if (!strncmp(this_opt, "pll:", 4))
3821                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3822                 else if (!strncmp(this_opt, "mclk:", 5))
3823                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3824                 else if (!strncmp(this_opt, "xclk:", 5))
3825                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3826                 else if (!strncmp(this_opt, "comp_sync:", 10))
3827                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3828 #ifdef CONFIG_PPC
3829                 else if (!strncmp(this_opt, "vmode:", 6)) {
3830                         unsigned int vmode =
3831                             simple_strtoul(this_opt + 6, NULL, 0);
3832                         if (vmode > 0 && vmode <= VMODE_MAX)
3833                                 default_vmode = vmode;
3834                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3835                         unsigned int cmode =
3836                             simple_strtoul(this_opt + 6, NULL, 0);
3837                         switch (cmode) {
3838                         case 0:
3839                         case 8:
3840                                 default_cmode = CMODE_8;
3841                                 break;
3842                         case 15:
3843                         case 16:
3844                                 default_cmode = CMODE_16;
3845                                 break;
3846                         case 24:
3847                         case 32:
3848                                 default_cmode = CMODE_32;
3849                                 break;
3850                         }
3851                 }
3852 #endif
3853 #ifdef CONFIG_ATARI
3854                 /*
3855                  * Why do we need this silly Mach64 argument?
3856                  * We are already here because of mach64= so its redundant.
3857                  */
3858                 else if (MACH_IS_ATARI
3859                          && (!strncmp(this_opt, "Mach64:", 7))) {
3860                         static unsigned char m64_num;
3861                         static char mach64_str[80];
3862                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3863                         if (!store_video_par(mach64_str, m64_num)) {
3864                                 m64_num++;
3865                                 mach64_count = m64_num;
3866                         }
3867                 }
3868 #endif
3869                 else
3870                         mode = this_opt;
3871         }
3872         return 0;
3873 }
3874 #endif  /*  MODULE  */
3875
3876 static int __init atyfb_init(void)
3877 {
3878     int err1 = 1, err2 = 1;
3879 #ifndef MODULE
3880     char *option = NULL;
3881
3882     if (fb_get_options("atyfb", &option))
3883         return -ENODEV;
3884     atyfb_setup(option);
3885 #endif
3886
3887 #ifdef CONFIG_PCI
3888     err1 = pci_register_driver(&atyfb_driver);
3889 #endif
3890 #ifdef CONFIG_ATARI
3891     err2 = atyfb_atari_probe();
3892 #endif
3893
3894     return (err1 && err2) ? -ENODEV : 0;
3895 }
3896
3897 static void __exit atyfb_exit(void)
3898 {
3899 #ifdef CONFIG_PCI
3900         pci_unregister_driver(&atyfb_driver);
3901 #endif
3902 }
3903
3904 module_init(atyfb_init);
3905 module_exit(atyfb_exit);
3906
3907 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3908 MODULE_LICENSE("GPL");
3909 module_param(noaccel, bool, 0);
3910 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3911 module_param(vram, int, 0);
3912 MODULE_PARM_DESC(vram, "int: override size of video ram");
3913 module_param(pll, int, 0);
3914 MODULE_PARM_DESC(pll, "int: override video clock");
3915 module_param(mclk, int, 0);
3916 MODULE_PARM_DESC(mclk, "int: override memory clock");
3917 module_param(xclk, int, 0);
3918 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3919 module_param(comp_sync, int, 0);
3920 MODULE_PARM_DESC(comp_sync,
3921                  "Set composite sync signal to low (0) or high (1)");
3922 module_param(mode, charp, 0);
3923 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3924 #ifdef CONFIG_MTRR
3925 module_param(nomtrr, bool, 0);
3926 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3927 #endif