drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/extcon.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/io.h>
  30 #include <linux/ioport.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/reboot.h>
  38 #include <linux/reset.h>
  39 #include <linux/types.h>
  40 #include <linux/usb/otg.h>
  41
  42 #include <linux/usb.h>
  43 #include <linux/usb/otg.h>
  44 #include <linux/usb/of.h>
  45 #include <linux/usb/ulpi.h>
  46 #include <linux/usb/gadget.h>
  47 #include <linux/usb/hcd.h>
  48 #include <linux/usb/msm_hsusb_hw.h>
  49 #include <linux/regulator/consumer.h>
  50
  51 /**
  52  * OTG control
  53  *
  54  * OTG_NO_CONTROL       Id/VBUS notifications not required. Useful in host
  55  *                      only configuration.
  56  * OTG_PHY_CONTROL      Id/VBUS notifications comes form USB PHY.
  57  * OTG_PMIC_CONTROL     Id/VBUS notifications comes from PMIC hardware.
  58  * OTG_USER_CONTROL     Id/VBUS notifcations comes from User via sysfs.
  59  *
  60  */
  61 enum otg_control_type {
  62         OTG_NO_CONTROL = 0,
  63         OTG_PHY_CONTROL,
  64         OTG_PMIC_CONTROL,
  65         OTG_USER_CONTROL,
  66 };
  67
  68 /**
  69  * PHY used in
  70  *
  71  * INVALID_PHY                  Unsupported PHY
  72  * CI_45NM_INTEGRATED_PHY       Chipidea 45nm integrated PHY
  73  * SNPS_28NM_INTEGRATED_PHY     Synopsis 28nm integrated PHY
  74  *
  75  */
  76 enum msm_usb_phy_type {
  77         INVALID_PHY = 0,
  78         CI_45NM_INTEGRATED_PHY,
  79         SNPS_28NM_INTEGRATED_PHY,
  80 };
  81
  82 #define IDEV_CHG_MAX    1500
  83 #define IUNIT           100
  84
  85 /**
  86  * Different states involved in USB charger detection.
  87  *
  88  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  89  *                              process is not yet started.
  90  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  91  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  92  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  93  *                              between SDP and DCP/CDP).
  94  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  95  *                              between DCP and CDP).
  96  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  97  *
  98  */
  99 enum usb_chg_state {
 100         USB_CHG_STATE_UNDEFINED = 0,
 101         USB_CHG_STATE_WAIT_FOR_DCD,
 102         USB_CHG_STATE_DCD_DONE,
 103         USB_CHG_STATE_PRIMARY_DONE,
 104         USB_CHG_STATE_SECONDARY_DONE,
 105         USB_CHG_STATE_DETECTED,
 106 };
 107
 108 /**
 109  * USB charger types
 110  *
 111  * USB_INVALID_CHARGER  Invalid USB charger.
 112  * USB_SDP_CHARGER      Standard downstream port. Refers to a downstream port
 113  *                      on USB2.0 compliant host/hub.
 114  * USB_DCP_CHARGER      Dedicated charger port (AC charger/ Wall charger).
 115  * USB_CDP_CHARGER      Charging downstream port. Enumeration can happen and
 116  *                      IDEV_CHG_MAX can be drawn irrespective of USB state.
 117  *
 118  */
 119 enum usb_chg_type {
 120         USB_INVALID_CHARGER = 0,
 121         USB_SDP_CHARGER,
 122         USB_DCP_CHARGER,
 123         USB_CDP_CHARGER,
 124 };
 125
 126 /**
 127  * struct msm_otg_platform_data - platform device data
 128  *              for msm_otg driver.
 129  * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
 130  *              "do not overwrite default vaule at this address".
 131  * @phy_init_sz: PHY configuration sequence size.
 132  * @vbus_power: VBUS power on/off routine.
 133  * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
 134  * @mode: Supported mode (OTG/peripheral/host).
 135  * @otg_control: OTG switch controlled by user/Id pin
 136  */
 137 struct msm_otg_platform_data {
 138         int *phy_init_seq;
 139         int phy_init_sz;
 140         void (*vbus_power)(bool on);
 141         unsigned power_budget;
 142         enum usb_dr_mode mode;
 143         enum otg_control_type otg_control;
 144         enum msm_usb_phy_type phy_type;
 145         void (*setup_gpio)(enum usb_otg_state state);
 146 };
 147
 148 /**
 149  * struct msm_otg: OTG driver data. Shared by HCD and DCD.
 150  * @otg: USB OTG Transceiver structure.
 151  * @pdata: otg device platform data.
 152  * @irq: IRQ number assigned for HSUSB controller.
 153  * @clk: clock struct of usb_hs_clk.
 154  * @pclk: clock struct of usb_hs_pclk.
 155  * @core_clk: clock struct of usb_hs_core_clk.
 156  * @regs: ioremapped register base address.
 157  * @inputs: OTG state machine inputs(Id, SessValid etc).
 158  * @sm_work: OTG state machine work.
 159  * @in_lpm: indicates low power mode (LPM) state.
 160  * @async_int: Async interrupt arrived.
 161  * @cur_power: The amount of mA available from downstream port.
 162  * @chg_work: Charger detection work.
 163  * @chg_state: The state of charger detection process.
 164  * @chg_type: The type of charger attached.
 165  * @dcd_retires: The retry count used to track Data contact
 166  *               detection process.
 167  * @manual_pullup: true if VBUS is not routed to USB controller/phy
 168  *      and controller driver therefore enables pull-up explicitly before
 169  *      starting controller using usbcmd run/stop bit.
 170  * @vbus: VBUS signal state trakining, using extcon framework
 171  * @id: ID signal state trakining, using extcon framework
 172  * @switch_gpio: Descriptor for GPIO used to control external Dual
 173  *               SPDT USB Switch.
 174  * @reboot: Used to inform the driver to route USB D+/D- line to Device
 175  *          connector
 176  */
 177 struct msm_otg {
 178         struct usb_phy phy;
 179         struct msm_otg_platform_data *pdata;
 180         int irq;
 181         struct clk *clk;
 182         struct clk *pclk;
 183         struct clk *core_clk;
 184         void __iomem *regs;
 185 #define ID              0
 186 #define B_SESS_VLD      1
 187         unsigned long inputs;
 188         struct work_struct sm_work;
 189         atomic_t in_lpm;
 190         int async_int;
 191         unsigned cur_power;
 192         int phy_number;
 193         struct delayed_work chg_work;
 194         enum usb_chg_state chg_state;
 195         enum usb_chg_type chg_type;
 196         u8 dcd_retries;
 197         struct regulator *v3p3;
 198         struct regulator *v1p8;
 199         struct regulator *vddcx;
 200         struct regulator_bulk_data supplies[3];
 201
 202         struct reset_control *phy_rst;
 203         struct reset_control *link_rst;
 204         int vdd_levels[3];
 205
 206         bool manual_pullup;
 207
 208         struct gpio_desc *switch_gpio;
 209         struct notifier_block reboot;
 210 };
 211
 212 #define MSM_USB_BASE    (motg->regs)
 213 #define DRIVER_NAME     "msm_otg"
 214
 215 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
 216 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
 217
 218 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
 219 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
 220 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
 221 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
 222
 223 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
 224 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
 225 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
 226 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
 227
 228 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
 229 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
 230 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
 231
 232 enum vdd_levels {
 233         VDD_LEVEL_NONE = 0,
 234         VDD_LEVEL_MIN,
 235         VDD_LEVEL_MAX,
 236 };
 237
 238 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 239 {
 240         int ret = 0;
 241
 242         if (init) {
 243                 ret = regulator_set_voltage(motg->vddcx,
 244                                 motg->vdd_levels[VDD_LEVEL_MIN],
 245                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 246                 if (ret) {
 247                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 248                         return ret;
 249                 }
 250
 251                 ret = regulator_enable(motg->vddcx);
 252                 if (ret)
 253                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
 254         } else {
 255                 ret = regulator_set_voltage(motg->vddcx, 0,
 256                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 257                 if (ret)
 258                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 259                 ret = regulator_disable(motg->vddcx);
 260                 if (ret)
 261                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
 262         }
 263
 264         return ret;
 265 }
 266
 267 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 268 {
 269         int rc = 0;
 270
 271         if (init) {
 272                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
 273                                 USB_PHY_3P3_VOL_MAX);
 274                 if (rc) {
 275                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
 276                         goto exit;
 277                 }
 278                 rc = regulator_enable(motg->v3p3);
 279                 if (rc) {
 280                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 281                         goto exit;
 282                 }
 283                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 284                                 USB_PHY_1P8_VOL_MAX);
 285                 if (rc) {
 286                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 287                         goto disable_3p3;
 288                 }
 289                 rc = regulator_enable(motg->v1p8);
 290                 if (rc) {
 291                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 292                         goto disable_3p3;
 293                 }
 294
 295                 return 0;
 296         }
 297
 298         regulator_disable(motg->v1p8);
 299 disable_3p3:
 300         regulator_disable(motg->v3p3);
 301 exit:
 302         return rc;
 303 }
 304
 305 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 306 {
 307         int ret = 0;
 308
 309         if (on) {
 310                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
 311                 if (ret < 0) {
 312                         pr_err("Could not set HPM for v1p8\n");
 313                         return ret;
 314                 }
 315                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
 316                 if (ret < 0) {
 317                         pr_err("Could not set HPM for v3p3\n");
 318                         regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 319                         return ret;
 320                 }
 321         } else {
 322                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 323                 if (ret < 0)
 324                         pr_err("Could not set LPM for v1p8\n");
 325                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
 326                 if (ret < 0)
 327                         pr_err("Could not set LPM for v3p3\n");
 328         }
 329
 330         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 331         return ret < 0 ? ret : 0;
 332 }
 333
 334 static int ulpi_read(struct usb_phy *phy, u32 reg)
 335 {
 336         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 337         int cnt = 0;
 338
 339         /* initiate read operation */
 340         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 341                USB_ULPI_VIEWPORT);
 342
 343         /* wait for completion */
 344         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 345                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 346                         break;
 347                 udelay(1);
 348                 cnt++;
 349         }
 350
 351         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 352                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 353                         readl(USB_ULPI_VIEWPORT));
 354                 return -ETIMEDOUT;
 355         }
 356         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 357 }
 358
 359 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 360 {
 361         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 362         int cnt = 0;
 363
 364         /* initiate write operation */
 365         writel(ULPI_RUN | ULPI_WRITE |
 366                ULPI_ADDR(reg) | ULPI_DATA(val),
 367                USB_ULPI_VIEWPORT);
 368
 369         /* wait for completion */
 370         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 371                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 372                         break;
 373                 udelay(1);
 374                 cnt++;
 375         }
 376
 377         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 378                 dev_err(phy->dev, "ulpi_write: timeout\n");
 379                 return -ETIMEDOUT;
 380         }
 381         return 0;
 382 }
 383
 384 static struct usb_phy_io_ops msm_otg_io_ops = {
 385         .read = ulpi_read,
 386         .write = ulpi_write,
 387 };
 388
 389 static void ulpi_init(struct msm_otg *motg)
 390 {
 391         struct msm_otg_platform_data *pdata = motg->pdata;
 392         int *seq = pdata->phy_init_seq, idx;
 393         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
 394
 395         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
 396                 if (seq[idx] == -1)
 397                         continue;
 398
 399                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 400                                 seq[idx], addr + idx);
 401                 ulpi_write(&motg->phy, seq[idx], addr + idx);
 402         }
 403 }
 404
 405 static int msm_phy_notify_disconnect(struct usb_phy *phy,
 406                                    enum usb_device_speed speed)
 407 {
 408         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 409         int val;
 410
 411         if (motg->manual_pullup) {
 412                 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
 413                 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
 414         }
 415
 416         /*
 417          * Put the transceiver in non-driving mode. Otherwise host
 418          * may not detect soft-disconnection.
 419          */
 420         val = ulpi_read(phy, ULPI_FUNC_CTRL);
 421         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 422         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 423         ulpi_write(phy, val, ULPI_FUNC_CTRL);
 424
 425         return 0;
 426 }
 427
 428 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 429 {
 430         int ret;
 431
 432         if (assert)
 433                 ret = reset_control_assert(motg->link_rst);
 434         else
 435                 ret = reset_control_deassert(motg->link_rst);
 436
 437         if (ret)
 438                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 439                         assert ? "assert" : "deassert");
 440
 441         return ret;
 442 }
 443
 444 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 445 {
 446         int ret = 0;
 447
 448         if (motg->phy_rst)
 449                 ret = reset_control_reset(motg->phy_rst);
 450
 451         if (ret)
 452                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 453
 454         return ret;
 455 }
 456
 457 static int msm_link_reset(struct msm_otg *motg)
 458 {
 459         u32 val;
 460         int ret;
 461
 462         ret = msm_otg_link_clk_reset(motg, 1);
 463         if (ret)
 464                 return ret;
 465
 466         /* wait for 1ms delay as suggested in HPG. */
 467         usleep_range(1000, 1200);
 468
 469         ret = msm_otg_link_clk_reset(motg, 0);
 470         if (ret)
 471                 return ret;
 472
 473         if (motg->phy_number)
 474                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 475
 476         /* put transceiver in serial mode as part of reset */
 477         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 478         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
 479
 480         return 0;
 481 }
 482
 483 static int msm_otg_reset(struct usb_phy *phy)
 484 {
 485         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 486         int cnt = 0;
 487
 488         writel(USBCMD_RESET, USB_USBCMD);
 489         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 490                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 491                         break;
 492                 udelay(1);
 493                 cnt++;
 494         }
 495         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 496                 return -ETIMEDOUT;
 497
 498         /* select ULPI phy and clear other status/control bits in PORTSC */
 499         writel(PORTSC_PTS_ULPI, USB_PORTSC);
 500
 501         writel(0x0, USB_AHBBURST);
 502         writel(0x08, USB_AHBMODE);
 503
 504         if (motg->phy_number)
 505                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 506         return 0;
 507 }
 508
 509 static void msm_phy_reset(struct msm_otg *motg)
 510 {
 511         void __iomem *addr;
 512
 513         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
 514                 msm_otg_phy_clk_reset(motg);
 515                 return;
 516         }
 517
 518         addr = USB_PHY_CTRL;
 519         if (motg->phy_number)
 520                 addr = USB_PHY_CTRL2;
 521
 522         /* Assert USB PHY_POR */
 523         writel(readl(addr) | PHY_POR_ASSERT, addr);
 524
 525         /*
 526          * wait for minimum 10 microseconds as suggested in HPG.
 527          * Use a slightly larger value since the exact value didn't
 528          * work 100% of the time.
 529          */
 530         udelay(12);
 531
 532         /* Deassert USB PHY_POR */
 533         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
 534 }
 535
 536 static int msm_usb_reset(struct usb_phy *phy)
 537 {
 538         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 539         int ret;
 540
 541         if (!IS_ERR(motg->core_clk))
 542                 clk_prepare_enable(motg->core_clk);
 543
 544         ret = msm_link_reset(motg);
 545         if (ret) {
 546                 dev_err(phy->dev, "phy_reset failed\n");
 547                 return ret;
 548         }
 549
 550         ret = msm_otg_reset(&motg->phy);
 551         if (ret) {
 552                 dev_err(phy->dev, "link reset failed\n");
 553                 return ret;
 554         }
 555
 556         msleep(100);
 557
 558         /* Reset USB PHY after performing USB Link RESET */
 559         msm_phy_reset(motg);
 560
 561         if (!IS_ERR(motg->core_clk))
 562                 clk_disable_unprepare(motg->core_clk);
 563
 564         return 0;
 565 }
 566
 567 static int msm_phy_init(struct usb_phy *phy)
 568 {
 569         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 570         struct msm_otg_platform_data *pdata = motg->pdata;
 571         u32 val, ulpi_val = 0;
 572
 573         /* Program USB PHY Override registers. */
 574         ulpi_init(motg);
 575
 576         /*
 577          * It is recommended in HPG to reset USB PHY after programming
 578          * USB PHY Override registers.
 579          */
 580         msm_phy_reset(motg);
 581
 582         if (pdata->otg_control == OTG_PHY_CONTROL) {
 583                 val = readl(USB_OTGSC);
 584                 if (pdata->mode == USB_DR_MODE_OTG) {
 585                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 586                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 587                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 588                         ulpi_val = ULPI_INT_SESS_VALID;
 589                         val |= OTGSC_BSVIE;
 590                 }
 591                 writel(val, USB_OTGSC);
 592                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 593                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 594         }
 595
 596         if (motg->manual_pullup) {
 597                 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
 598                 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
 599
 600                 val = readl(USB_GENCONFIG_2);
 601                 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
 602                 writel(val, USB_GENCONFIG_2);
 603
 604                 val = readl(USB_USBCMD);
 605                 val |= USBCMD_SESS_VLD_CTRL;
 606                 writel(val, USB_USBCMD);
 607
 608                 val = ulpi_read(phy, ULPI_FUNC_CTRL);
 609                 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 610                 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 611                 ulpi_write(phy, val, ULPI_FUNC_CTRL);
 612         }
 613
 614         if (motg->phy_number)
 615                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 616
 617         return 0;
 618 }
 619
 620 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 621 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 622
 623 #ifdef CONFIG_PM
 624
 625 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 626 {
 627         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 628         int min_vol;
 629         int ret;
 630
 631         if (high)
 632                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 633         else
 634                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 635
 636         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 637         if (ret) {
 638                 pr_err("Cannot set vddcx voltage\n");
 639                 return ret;
 640         }
 641
 642         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 643
 644         return ret;
 645 }
 646
 647 static int msm_otg_suspend(struct msm_otg *motg)
 648 {
 649         struct usb_phy *phy = &motg->phy;
 650         struct usb_bus *bus = phy->otg->host;
 651         struct msm_otg_platform_data *pdata = motg->pdata;
 652         void __iomem *addr;
 653         int cnt = 0;
 654
 655         if (atomic_read(&motg->in_lpm))
 656                 return 0;
 657
 658         disable_irq(motg->irq);
 659         /*
 660          * Chipidea 45-nm PHY suspend sequence:
 661          *
 662          * Interrupt Latch Register auto-clear feature is not present
 663          * in all PHY versions. Latch register is clear on read type.
 664          * Clear latch register to avoid spurious wakeup from
 665          * low power mode (LPM).
 666          *
 667          * PHY comparators are disabled when PHY enters into low power
 668          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 669          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 670          * PHY comparators. This save significant amount of power.
 671          *
 672          * PLL is not turned off when PHY enters into low power mode (LPM).
 673          * Disable PLL for maximum power savings.
 674          */
 675
 676         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 677                 ulpi_read(phy, 0x14);
 678                 if (pdata->otg_control == OTG_PHY_CONTROL)
 679                         ulpi_write(phy, 0x01, 0x30);
 680                 ulpi_write(phy, 0x08, 0x09);
 681         }
 682
 683         /*
 684          * PHY may take some time or even fail to enter into low power
 685          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 686          * in failure case.
 687          */
 688         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 689         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 690                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 691                         break;
 692                 udelay(1);
 693                 cnt++;
 694         }
 695
 696         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 697                 dev_err(phy->dev, "Unable to suspend PHY\n");
 698                 msm_otg_reset(phy);
 699                 enable_irq(motg->irq);
 700                 return -ETIMEDOUT;
 701         }
 702
 703         /*
 704          * PHY has capability to generate interrupt asynchronously in low
 705          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 706          * line must be disabled till async interrupt enable bit is cleared
 707          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 708          * block data communication from PHY.
 709          */
 710         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 711
 712         addr = USB_PHY_CTRL;
 713         if (motg->phy_number)
 714                 addr = USB_PHY_CTRL2;
 715
 716         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 717                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 718                 writel(readl(addr) | PHY_RETEN, addr);
 719
 720         clk_disable_unprepare(motg->pclk);
 721         clk_disable_unprepare(motg->clk);
 722         if (!IS_ERR(motg->core_clk))
 723                 clk_disable_unprepare(motg->core_clk);
 724
 725         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 726                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 727                 msm_hsusb_ldo_set_mode(motg, 0);
 728                 msm_hsusb_config_vddcx(motg, 0);
 729         }
 730
 731         if (device_may_wakeup(phy->dev))
 732                 enable_irq_wake(motg->irq);
 733         if (bus)
 734                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 735
 736         atomic_set(&motg->in_lpm, 1);
 737         enable_irq(motg->irq);
 738
 739         dev_info(phy->dev, "USB in low power mode\n");
 740
 741         return 0;
 742 }
 743
 744 static int msm_otg_resume(struct msm_otg *motg)
 745 {
 746         struct usb_phy *phy = &motg->phy;
 747         struct usb_bus *bus = phy->otg->host;
 748         void __iomem *addr;
 749         int cnt = 0;
 750         unsigned temp;
 751
 752         if (!atomic_read(&motg->in_lpm))
 753                 return 0;
 754
 755         clk_prepare_enable(motg->pclk);
 756         clk_prepare_enable(motg->clk);
 757         if (!IS_ERR(motg->core_clk))
 758                 clk_prepare_enable(motg->core_clk);
 759
 760         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 761                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 762
 763                 addr = USB_PHY_CTRL;
 764                 if (motg->phy_number)
 765                         addr = USB_PHY_CTRL2;
 766
 767                 msm_hsusb_ldo_set_mode(motg, 1);
 768                 msm_hsusb_config_vddcx(motg, 1);
 769                 writel(readl(addr) & ~PHY_RETEN, addr);
 770         }
 771
 772         temp = readl(USB_USBCMD);
 773         temp &= ~ASYNC_INTR_CTRL;
 774         temp &= ~ULPI_STP_CTRL;
 775         writel(temp, USB_USBCMD);
 776
 777         /*
 778          * PHY comes out of low power mode (LPM) in case of wakeup
 779          * from asynchronous interrupt.
 780          */
 781         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 782                 goto skip_phy_resume;
 783
 784         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 785         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 786                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 787                         break;
 788                 udelay(1);
 789                 cnt++;
 790         }
 791
 792         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 793                 /*
 794                  * This is a fatal error. Reset the link and
 795                  * PHY. USB state can not be restored. Re-insertion
 796                  * of USB cable is the only way to get USB working.
 797                  */
 798                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 799                 msm_otg_reset(phy);
 800         }
 801
 802 skip_phy_resume:
 803         if (device_may_wakeup(phy->dev))
 804                 disable_irq_wake(motg->irq);
 805         if (bus)
 806                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 807
 808         atomic_set(&motg->in_lpm, 0);
 809
 810         if (motg->async_int) {
 811                 motg->async_int = 0;
 812                 pm_runtime_put(phy->dev);
 813                 enable_irq(motg->irq);
 814         }
 815
 816         dev_info(phy->dev, "USB exited from low power mode\n");
 817
 818         return 0;
 819 }
 820 #endif
 821
 822 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 823 {
 824         if (motg->cur_power == mA)
 825                 return;
 826
 827         /* TODO: Notify PMIC about available current */
 828         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 829         motg->cur_power = mA;
 830 }
 831
 832 static void msm_otg_start_host(struct usb_phy *phy, int on)
 833 {
 834         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 835         struct msm_otg_platform_data *pdata = motg->pdata;
 836         struct usb_hcd *hcd;
 837
 838         if (!phy->otg->host)
 839                 return;
 840
 841         hcd = bus_to_hcd(phy->otg->host);
 842
 843         if (on) {
 844                 dev_dbg(phy->dev, "host on\n");
 845
 846                 if (pdata->vbus_power)
 847                         pdata->vbus_power(1);
 848                 /*
 849                  * Some boards have a switch cotrolled by gpio
 850                  * to enable/disable internal HUB. Enable internal
 851                  * HUB before kicking the host.
 852                  */
 853                 if (pdata->setup_gpio)
 854                         pdata->setup_gpio(OTG_STATE_A_HOST);
 855 #ifdef CONFIG_USB
 856                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 857                 device_wakeup_enable(hcd->self.controller);
 858 #endif
 859         } else {
 860                 dev_dbg(phy->dev, "host off\n");
 861
 862 #ifdef CONFIG_USB
 863                 usb_remove_hcd(hcd);
 864 #endif
 865                 if (pdata->setup_gpio)
 866                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 867                 if (pdata->vbus_power)
 868                         pdata->vbus_power(0);
 869         }
 870 }
 871
 872 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 873 {
 874         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 875         struct usb_hcd *hcd;
 876
 877         /*
 878          * Fail host registration if this board can support
 879          * only peripheral configuration.
 880          */
 881         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 882                 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
 883                 return -ENODEV;
 884         }
 885
 886         if (!host) {
 887                 if (otg->state == OTG_STATE_A_HOST) {
 888                         pm_runtime_get_sync(otg->usb_phy->dev);
 889                         msm_otg_start_host(otg->usb_phy, 0);
 890                         otg->host = NULL;
 891                         otg->state = OTG_STATE_UNDEFINED;
 892                         schedule_work(&motg->sm_work);
 893                 } else {
 894                         otg->host = NULL;
 895                 }
 896
 897                 return 0;
 898         }
 899
 900         hcd = bus_to_hcd(host);
 901         hcd->power_budget = motg->pdata->power_budget;
 902
 903         otg->host = host;
 904         dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
 905
 906         pm_runtime_get_sync(otg->usb_phy->dev);
 907         schedule_work(&motg->sm_work);
 908
 909         return 0;
 910 }
 911
 912 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 913 {
 914         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 915         struct msm_otg_platform_data *pdata = motg->pdata;
 916
 917         if (!phy->otg->gadget)
 918                 return;
 919
 920         if (on) {
 921                 dev_dbg(phy->dev, "gadget on\n");
 922                 /*
 923                  * Some boards have a switch cotrolled by gpio
 924                  * to enable/disable internal HUB. Disable internal
 925                  * HUB before kicking the gadget.
 926                  */
 927                 if (pdata->setup_gpio)
 928                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 929                 usb_gadget_vbus_connect(phy->otg->gadget);
 930         } else {
 931                 dev_dbg(phy->dev, "gadget off\n");
 932                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 933                 if (pdata->setup_gpio)
 934                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 935         }
 936
 937 }
 938
 939 static int msm_otg_set_peripheral(struct usb_otg *otg,
 940                                         struct usb_gadget *gadget)
 941 {
 942         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 943
 944         /*
 945          * Fail peripheral registration if this board can support
 946          * only host configuration.
 947          */
 948         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 949                 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
 950                 return -ENODEV;
 951         }
 952
 953         if (!gadget) {
 954                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 955                         pm_runtime_get_sync(otg->usb_phy->dev);
 956                         msm_otg_start_peripheral(otg->usb_phy, 0);
 957                         otg->gadget = NULL;
 958                         otg->state = OTG_STATE_UNDEFINED;
 959                         schedule_work(&motg->sm_work);
 960                 } else {
 961                         otg->gadget = NULL;
 962                 }
 963
 964                 return 0;
 965         }
 966         otg->gadget = gadget;
 967         dev_dbg(otg->usb_phy->dev,
 968                 "peripheral driver registered w/ tranceiver\n");
 969
 970         pm_runtime_get_sync(otg->usb_phy->dev);
 971         schedule_work(&motg->sm_work);
 972
 973         return 0;
 974 }
 975
 976 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 977 {
 978         struct usb_phy *phy = &motg->phy;
 979         u32 chg_det;
 980         bool ret = false;
 981
 982         switch (motg->pdata->phy_type) {
 983         case CI_45NM_INTEGRATED_PHY:
 984                 chg_det = ulpi_read(phy, 0x34);
 985                 ret = chg_det & (1 << 4);
 986                 break;
 987         case SNPS_28NM_INTEGRATED_PHY:
 988                 chg_det = ulpi_read(phy, 0x87);
 989                 ret = chg_det & 1;
 990                 break;
 991         default:
 992                 break;
 993         }
 994         return ret;
 995 }
 996
 997 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 998 {
 999         struct usb_phy *phy = &motg->phy;
1000         u32 chg_det;
1001
1002         switch (motg->pdata->phy_type) {
1003         case CI_45NM_INTEGRATED_PHY:
1004                 chg_det = ulpi_read(phy, 0x34);
1005                 /* Turn off charger block */
1006                 chg_det |= ~(1 << 1);
1007                 ulpi_write(phy, chg_det, 0x34);
1008                 udelay(20);
1009                 /* control chg block via ULPI */
1010                 chg_det &= ~(1 << 3);
1011                 ulpi_write(phy, chg_det, 0x34);
1012                 /* put it in host mode for enabling D- source */
1013                 chg_det &= ~(1 << 2);
1014                 ulpi_write(phy, chg_det, 0x34);
1015                 /* Turn on chg detect block */
1016                 chg_det &= ~(1 << 1);
1017                 ulpi_write(phy, chg_det, 0x34);
1018                 udelay(20);
1019                 /* enable chg detection */
1020                 chg_det &= ~(1 << 0);
1021                 ulpi_write(phy, chg_det, 0x34);
1022                 break;
1023         case SNPS_28NM_INTEGRATED_PHY:
1024                 /*
1025                  * Configure DM as current source, DP as current sink
1026                  * and enable battery charging comparators.
1027                  */
1028                 ulpi_write(phy, 0x8, 0x85);
1029                 ulpi_write(phy, 0x2, 0x85);
1030                 ulpi_write(phy, 0x1, 0x85);
1031                 break;
1032         default:
1033                 break;
1034         }
1035 }
1036
1037 static bool msm_chg_check_primary_det(struct msm_otg *motg)
1038 {
1039         struct usb_phy *phy = &motg->phy;
1040         u32 chg_det;
1041         bool ret = false;
1042
1043         switch (motg->pdata->phy_type) {
1044         case CI_45NM_INTEGRATED_PHY:
1045                 chg_det = ulpi_read(phy, 0x34);
1046                 ret = chg_det & (1 << 4);
1047                 break;
1048         case SNPS_28NM_INTEGRATED_PHY:
1049                 chg_det = ulpi_read(phy, 0x87);
1050                 ret = chg_det & 1;
1051                 break;
1052         default:
1053                 break;
1054         }
1055         return ret;
1056 }
1057
1058 static void msm_chg_enable_primary_det(struct msm_otg *motg)
1059 {
1060         struct usb_phy *phy = &motg->phy;
1061         u32 chg_det;
1062
1063         switch (motg->pdata->phy_type) {
1064         case CI_45NM_INTEGRATED_PHY:
1065                 chg_det = ulpi_read(phy, 0x34);
1066                 /* enable chg detection */
1067                 chg_det &= ~(1 << 0);
1068                 ulpi_write(phy, chg_det, 0x34);
1069                 break;
1070         case SNPS_28NM_INTEGRATED_PHY:
1071                 /*
1072                  * Configure DP as current source, DM as current sink
1073                  * and enable battery charging comparators.
1074                  */
1075                 ulpi_write(phy, 0x2, 0x85);
1076                 ulpi_write(phy, 0x1, 0x85);
1077                 break;
1078         default:
1079                 break;
1080         }
1081 }
1082
1083 static bool msm_chg_check_dcd(struct msm_otg *motg)
1084 {
1085         struct usb_phy *phy = &motg->phy;
1086         u32 line_state;
1087         bool ret = false;
1088
1089         switch (motg->pdata->phy_type) {
1090         case CI_45NM_INTEGRATED_PHY:
1091                 line_state = ulpi_read(phy, 0x15);
1092                 ret = !(line_state & 1);
1093                 break;
1094         case SNPS_28NM_INTEGRATED_PHY:
1095                 line_state = ulpi_read(phy, 0x87);
1096                 ret = line_state & 2;
1097                 break;
1098         default:
1099                 break;
1100         }
1101         return ret;
1102 }
1103
1104 static void msm_chg_disable_dcd(struct msm_otg *motg)
1105 {
1106         struct usb_phy *phy = &motg->phy;
1107         u32 chg_det;
1108
1109         switch (motg->pdata->phy_type) {
1110         case CI_45NM_INTEGRATED_PHY:
1111                 chg_det = ulpi_read(phy, 0x34);
1112                 chg_det &= ~(1 << 5);
1113                 ulpi_write(phy, chg_det, 0x34);
1114                 break;
1115         case SNPS_28NM_INTEGRATED_PHY:
1116                 ulpi_write(phy, 0x10, 0x86);
1117                 break;
1118         default:
1119                 break;
1120         }
1121 }
1122
1123 static void msm_chg_enable_dcd(struct msm_otg *motg)
1124 {
1125         struct usb_phy *phy = &motg->phy;
1126         u32 chg_det;
1127
1128         switch (motg->pdata->phy_type) {
1129         case CI_45NM_INTEGRATED_PHY:
1130                 chg_det = ulpi_read(phy, 0x34);
1131                 /* Turn on D+ current source */
1132                 chg_det |= (1 << 5);
1133                 ulpi_write(phy, chg_det, 0x34);
1134                 break;
1135         case SNPS_28NM_INTEGRATED_PHY:
1136                 /* Data contact detection enable */
1137                 ulpi_write(phy, 0x10, 0x85);
1138                 break;
1139         default:
1140                 break;
1141         }
1142 }
1143
1144 static void msm_chg_block_on(struct msm_otg *motg)
1145 {
1146         struct usb_phy *phy = &motg->phy;
1147         u32 func_ctrl, chg_det;
1148
1149         /* put the controller in non-driving mode */
1150         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1151         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1152         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1153         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1154
1155         switch (motg->pdata->phy_type) {
1156         case CI_45NM_INTEGRATED_PHY:
1157                 chg_det = ulpi_read(phy, 0x34);
1158                 /* control chg block via ULPI */
1159                 chg_det &= ~(1 << 3);
1160                 ulpi_write(phy, chg_det, 0x34);
1161                 /* Turn on chg detect block */
1162                 chg_det &= ~(1 << 1);
1163                 ulpi_write(phy, chg_det, 0x34);
1164                 udelay(20);
1165                 break;
1166         case SNPS_28NM_INTEGRATED_PHY:
1167                 /* Clear charger detecting control bits */
1168                 ulpi_write(phy, 0x3F, 0x86);
1169                 /* Clear alt interrupt latch and enable bits */
1170                 ulpi_write(phy, 0x1F, 0x92);
1171                 ulpi_write(phy, 0x1F, 0x95);
1172                 udelay(100);
1173                 break;
1174         default:
1175                 break;
1176         }
1177 }
1178
1179 static void msm_chg_block_off(struct msm_otg *motg)
1180 {
1181         struct usb_phy *phy = &motg->phy;
1182         u32 func_ctrl, chg_det;
1183
1184         switch (motg->pdata->phy_type) {
1185         case CI_45NM_INTEGRATED_PHY:
1186                 chg_det = ulpi_read(phy, 0x34);
1187                 /* Turn off charger block */
1188                 chg_det |= ~(1 << 1);
1189                 ulpi_write(phy, chg_det, 0x34);
1190                 break;
1191         case SNPS_28NM_INTEGRATED_PHY:
1192                 /* Clear charger detecting control bits */
1193                 ulpi_write(phy, 0x3F, 0x86);
1194                 /* Clear alt interrupt latch and enable bits */
1195                 ulpi_write(phy, 0x1F, 0x92);
1196                 ulpi_write(phy, 0x1F, 0x95);
1197                 break;
1198         default:
1199                 break;
1200         }
1201
1202         /* put the controller in normal mode */
1203         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1204         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1205         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1206         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1207 }
1208
1209 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1210 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1211 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1212 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1213 static void msm_chg_detect_work(struct work_struct *w)
1214 {
1215         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1216         struct usb_phy *phy = &motg->phy;
1217         bool is_dcd, tmout, vout;
1218         unsigned long delay;
1219
1220         dev_dbg(phy->dev, "chg detection work\n");
1221         switch (motg->chg_state) {
1222         case USB_CHG_STATE_UNDEFINED:
1223                 pm_runtime_get_sync(phy->dev);
1224                 msm_chg_block_on(motg);
1225                 msm_chg_enable_dcd(motg);
1226                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1227                 motg->dcd_retries = 0;
1228                 delay = MSM_CHG_DCD_POLL_TIME;
1229                 break;
1230         case USB_CHG_STATE_WAIT_FOR_DCD:
1231                 is_dcd = msm_chg_check_dcd(motg);
1232                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1233                 if (is_dcd || tmout) {
1234                         msm_chg_disable_dcd(motg);
1235                         msm_chg_enable_primary_det(motg);
1236                         delay = MSM_CHG_PRIMARY_DET_TIME;
1237                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1238                 } else {
1239                         delay = MSM_CHG_DCD_POLL_TIME;
1240                 }
1241                 break;
1242         case USB_CHG_STATE_DCD_DONE:
1243                 vout = msm_chg_check_primary_det(motg);
1244                 if (vout) {
1245                         msm_chg_enable_secondary_det(motg);
1246                         delay = MSM_CHG_SECONDARY_DET_TIME;
1247                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1248                 } else {
1249                         motg->chg_type = USB_SDP_CHARGER;
1250                         motg->chg_state = USB_CHG_STATE_DETECTED;
1251                         delay = 0;
1252                 }
1253                 break;
1254         case USB_CHG_STATE_PRIMARY_DONE:
1255                 vout = msm_chg_check_secondary_det(motg);
1256                 if (vout)
1257                         motg->chg_type = USB_DCP_CHARGER;
1258                 else
1259                         motg->chg_type = USB_CDP_CHARGER;
1260                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1261                 /* fall through */
1262         case USB_CHG_STATE_SECONDARY_DONE:
1263                 motg->chg_state = USB_CHG_STATE_DETECTED;
1264         case USB_CHG_STATE_DETECTED:
1265                 msm_chg_block_off(motg);
1266                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1267                 schedule_work(&motg->sm_work);
1268                 return;
1269         default:
1270                 return;
1271         }
1272
1273         schedule_delayed_work(&motg->chg_work, delay);
1274 }
1275
1276 /*
1277  * We support OTG, Peripheral only and Host only configurations. In case
1278  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1279  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1280  * enabled when switch is controlled by user and default mode is supplied
1281  * by board file, which can be changed by userspace later.
1282  */
1283 static void msm_otg_init_sm(struct msm_otg *motg)
1284 {
1285         struct msm_otg_platform_data *pdata = motg->pdata;
1286         u32 otgsc = readl(USB_OTGSC);
1287
1288         switch (pdata->mode) {
1289         case USB_DR_MODE_OTG:
1290                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1291                         if (otgsc & OTGSC_ID)
1292                                 set_bit(ID, &motg->inputs);
1293                         else
1294                                 clear_bit(ID, &motg->inputs);
1295
1296                         if (otgsc & OTGSC_BSV)
1297                                 set_bit(B_SESS_VLD, &motg->inputs);
1298                         else
1299                                 clear_bit(B_SESS_VLD, &motg->inputs);
1300                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1301                                 set_bit(ID, &motg->inputs);
1302                                 clear_bit(B_SESS_VLD, &motg->inputs);
1303                 }
1304                 break;
1305         case USB_DR_MODE_HOST:
1306                 clear_bit(ID, &motg->inputs);
1307                 break;
1308         case USB_DR_MODE_PERIPHERAL:
1309                 set_bit(ID, &motg->inputs);
1310                 if (otgsc & OTGSC_BSV)
1311                         set_bit(B_SESS_VLD, &motg->inputs);
1312                 else
1313                         clear_bit(B_SESS_VLD, &motg->inputs);
1314                 break;
1315         default:
1316                 break;
1317         }
1318 }
1319
1320 static void msm_otg_sm_work(struct work_struct *w)
1321 {
1322         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1323         struct usb_otg *otg = motg->phy.otg;
1324
1325         switch (otg->state) {
1326         case OTG_STATE_UNDEFINED:
1327                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1328                 msm_otg_reset(otg->usb_phy);
1329                 msm_otg_init_sm(motg);
1330                 otg->state = OTG_STATE_B_IDLE;
1331                 /* FALL THROUGH */
1332         case OTG_STATE_B_IDLE:
1333                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1334                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1335                         /* disable BSV bit */
1336                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1337                         msm_otg_start_host(otg->usb_phy, 1);
1338                         otg->state = OTG_STATE_A_HOST;
1339                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1340                         switch (motg->chg_state) {
1341                         case USB_CHG_STATE_UNDEFINED:
1342                                 msm_chg_detect_work(&motg->chg_work.work);
1343                                 break;
1344                         case USB_CHG_STATE_DETECTED:
1345                                 switch (motg->chg_type) {
1346                                 case USB_DCP_CHARGER:
1347                                         msm_otg_notify_charger(motg,
1348                                                         IDEV_CHG_MAX);
1349                                         break;
1350                                 case USB_CDP_CHARGER:
1351                                         msm_otg_notify_charger(motg,
1352                                                         IDEV_CHG_MAX);
1353                                         msm_otg_start_peripheral(otg->usb_phy,
1354                                                                  1);
1355                                         otg->state
1356                                                 = OTG_STATE_B_PERIPHERAL;
1357                                         break;
1358                                 case USB_SDP_CHARGER:
1359                                         msm_otg_notify_charger(motg, IUNIT);
1360                                         msm_otg_start_peripheral(otg->usb_phy,
1361                                                                  1);
1362                                         otg->state
1363                                                 = OTG_STATE_B_PERIPHERAL;
1364                                         break;
1365                                 default:
1366                                         break;
1367                                 }
1368                                 break;
1369                         default:
1370                                 break;
1371                         }
1372                 } else {
1373                         /*
1374                          * If charger detection work is pending, decrement
1375                          * the pm usage counter to balance with the one that
1376                          * is incremented in charger detection work.
1377                          */
1378                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1379                                 pm_runtime_put_sync(otg->usb_phy->dev);
1380                                 msm_otg_reset(otg->usb_phy);
1381                         }
1382                         msm_otg_notify_charger(motg, 0);
1383                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1384                         motg->chg_type = USB_INVALID_CHARGER;
1385                 }
1386
1387                 if (otg->state == OTG_STATE_B_IDLE)
1388                         pm_runtime_put_sync(otg->usb_phy->dev);
1389                 break;
1390         case OTG_STATE_B_PERIPHERAL:
1391                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1392                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1393                                 !test_bit(ID, &motg->inputs)) {
1394                         msm_otg_notify_charger(motg, 0);
1395                         msm_otg_start_peripheral(otg->usb_phy, 0);
1396                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1397                         motg->chg_type = USB_INVALID_CHARGER;
1398                         otg->state = OTG_STATE_B_IDLE;
1399                         msm_otg_reset(otg->usb_phy);
1400                         schedule_work(w);
1401                 }
1402                 break;
1403         case OTG_STATE_A_HOST:
1404                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1405                 if (test_bit(ID, &motg->inputs)) {
1406                         msm_otg_start_host(otg->usb_phy, 0);
1407                         otg->state = OTG_STATE_B_IDLE;
1408                         msm_otg_reset(otg->usb_phy);
1409                         schedule_work(w);
1410                 }
1411                 break;
1412         default:
1413                 break;
1414         }
1415 }
1416
1417 static irqreturn_t msm_otg_irq(int irq, void *data)
1418 {
1419         struct msm_otg *motg = data;
1420         struct usb_phy *phy = &motg->phy;
1421         u32 otgsc = 0;
1422
1423         if (atomic_read(&motg->in_lpm)) {
1424                 disable_irq_nosync(irq);
1425                 motg->async_int = 1;
1426                 pm_runtime_get(phy->dev);
1427                 return IRQ_HANDLED;
1428         }
1429
1430         otgsc = readl(USB_OTGSC);
1431         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1432                 return IRQ_NONE;
1433
1434         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1435                 if (otgsc & OTGSC_ID)
1436                         set_bit(ID, &motg->inputs);
1437                 else
1438                         clear_bit(ID, &motg->inputs);
1439                 dev_dbg(phy->dev, "ID set/clear\n");
1440                 pm_runtime_get_noresume(phy->dev);
1441         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1442                 if (otgsc & OTGSC_BSV)
1443                         set_bit(B_SESS_VLD, &motg->inputs);
1444                 else
1445                         clear_bit(B_SESS_VLD, &motg->inputs);
1446                 dev_dbg(phy->dev, "BSV set/clear\n");
1447                 pm_runtime_get_noresume(phy->dev);
1448         }
1449
1450         writel(otgsc, USB_OTGSC);
1451         schedule_work(&motg->sm_work);
1452         return IRQ_HANDLED;
1453 }
1454
1455 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1456 {
1457         struct msm_otg *motg = s->private;
1458         struct usb_otg *otg = motg->phy.otg;
1459
1460         switch (otg->state) {
1461         case OTG_STATE_A_HOST:
1462                 seq_puts(s, "host\n");
1463                 break;
1464         case OTG_STATE_B_PERIPHERAL:
1465                 seq_puts(s, "peripheral\n");
1466                 break;
1467         default:
1468                 seq_puts(s, "none\n");
1469                 break;
1470         }
1471
1472         return 0;
1473 }
1474
1475 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1476 {
1477         return single_open(file, msm_otg_mode_show, inode->i_private);
1478 }
1479
1480 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1481                                 size_t count, loff_t *ppos)
1482 {
1483         struct seq_file *s = file->private_data;
1484         struct msm_otg *motg = s->private;
1485         char buf[16];
1486         struct usb_otg *otg = motg->phy.otg;
1487         int status = count;
1488         enum usb_dr_mode req_mode;
1489
1490         memset(buf, 0x00, sizeof(buf));
1491
1492         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1493                 status = -EFAULT;
1494                 goto out;
1495         }
1496
1497         if (!strncmp(buf, "host", 4)) {
1498                 req_mode = USB_DR_MODE_HOST;
1499         } else if (!strncmp(buf, "peripheral", 10)) {
1500                 req_mode = USB_DR_MODE_PERIPHERAL;
1501         } else if (!strncmp(buf, "none", 4)) {
1502                 req_mode = USB_DR_MODE_UNKNOWN;
1503         } else {
1504                 status = -EINVAL;
1505                 goto out;
1506         }
1507
1508         switch (req_mode) {
1509         case USB_DR_MODE_UNKNOWN:
1510                 switch (otg->state) {
1511                 case OTG_STATE_A_HOST:
1512                 case OTG_STATE_B_PERIPHERAL:
1513                         set_bit(ID, &motg->inputs);
1514                         clear_bit(B_SESS_VLD, &motg->inputs);
1515                         break;
1516                 default:
1517                         goto out;
1518                 }
1519                 break;
1520         case USB_DR_MODE_PERIPHERAL:
1521                 switch (otg->state) {
1522                 case OTG_STATE_B_IDLE:
1523                 case OTG_STATE_A_HOST:
1524                         set_bit(ID, &motg->inputs);
1525                         set_bit(B_SESS_VLD, &motg->inputs);
1526                         break;
1527                 default:
1528                         goto out;
1529                 }
1530                 break;
1531         case USB_DR_MODE_HOST:
1532                 switch (otg->state) {
1533                 case OTG_STATE_B_IDLE:
1534                 case OTG_STATE_B_PERIPHERAL:
1535                         clear_bit(ID, &motg->inputs);
1536                         break;
1537                 default:
1538                         goto out;
1539                 }
1540                 break;
1541         default:
1542                 goto out;
1543         }
1544
1545         pm_runtime_get_sync(otg->usb_phy->dev);
1546         schedule_work(&motg->sm_work);
1547 out:
1548         return status;
1549 }
1550
1551 static const struct file_operations msm_otg_mode_fops = {
1552         .open = msm_otg_mode_open,
1553         .read = seq_read,
1554         .write = msm_otg_mode_write,
1555         .llseek = seq_lseek,
1556         .release = single_release,
1557 };
1558
1559 static struct dentry *msm_otg_dbg_root;
1560 static struct dentry *msm_otg_dbg_mode;
1561
1562 static int msm_otg_debugfs_init(struct msm_otg *motg)
1563 {
1564         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1565
1566         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1567                 return -ENODEV;
1568
1569         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1570                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1571         if (!msm_otg_dbg_mode) {
1572                 debugfs_remove(msm_otg_dbg_root);
1573                 msm_otg_dbg_root = NULL;
1574                 return -ENODEV;
1575         }
1576
1577         return 0;
1578 }
1579
1580 static void msm_otg_debugfs_cleanup(void)
1581 {
1582         debugfs_remove(msm_otg_dbg_mode);
1583         debugfs_remove(msm_otg_dbg_root);
1584 }
1585
1586 static const struct of_device_id msm_otg_dt_match[] = {
1587         {
1588                 .compatible = "qcom,usb-otg-ci",
1589                 .data = (void *) CI_45NM_INTEGRATED_PHY
1590         },
1591         {
1592                 .compatible = "qcom,usb-otg-snps",
1593                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1594         },
1595         { }
1596 };
1597 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1598
1599 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1600                                 void *ptr)
1601 {
1602         struct usb_phy *usb_phy = container_of(nb, struct usb_phy, vbus_nb);
1603         struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1604
1605         if (event)
1606                 set_bit(B_SESS_VLD, &motg->inputs);
1607         else
1608                 clear_bit(B_SESS_VLD, &motg->inputs);
1609
1610         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1611                 /* Switch D+/D- lines to Device connector */
1612                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1613         } else {
1614                 /* Switch D+/D- lines to Hub */
1615                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1616         }
1617
1618         schedule_work(&motg->sm_work);
1619
1620         return NOTIFY_DONE;
1621 }
1622
1623 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1624                                 void *ptr)
1625 {
1626         struct usb_phy *usb_phy = container_of(nb, struct usb_phy, id_nb);
1627         struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1628
1629         if (event)
1630                 clear_bit(ID, &motg->inputs);
1631         else
1632                 set_bit(ID, &motg->inputs);
1633
1634         schedule_work(&motg->sm_work);
1635
1636         return NOTIFY_DONE;
1637 }
1638
1639 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1640 {
1641         struct msm_otg_platform_data *pdata;
1642         struct device_node *node = pdev->dev.of_node;
1643         struct property *prop;
1644         int len, ret, words;
1645         u32 val, tmp[3];
1646
1647         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1648         if (!pdata)
1649                 return -ENOMEM;
1650
1651         motg->pdata = pdata;
1652
1653         pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1654         if (!pdata->phy_type)
1655                 return 1;
1656
1657         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1658         if (IS_ERR(motg->link_rst))
1659                 return PTR_ERR(motg->link_rst);
1660
1661         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1662         if (IS_ERR(motg->phy_rst))
1663                 motg->phy_rst = NULL;
1664
1665         pdata->mode = usb_get_dr_mode(&pdev->dev);
1666         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1667                 pdata->mode = USB_DR_MODE_OTG;
1668
1669         pdata->otg_control = OTG_PHY_CONTROL;
1670         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1671                 if (val == OTG_PMIC_CONTROL)
1672                         pdata->otg_control = val;
1673
1674         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1675                 motg->phy_number = val;
1676
1677         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1678         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1679         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1680
1681         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1682             len == sizeof(tmp)) {
1683                 of_property_read_u32_array(node, "qcom,vdd-levels",
1684                                            tmp, len / sizeof(*tmp));
1685                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1686                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1687                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1688         }
1689
1690         motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1691
1692         motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1693                                                     GPIOD_OUT_LOW);
1694         if (IS_ERR(motg->switch_gpio))
1695                 return PTR_ERR(motg->switch_gpio);
1696
1697         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1698         if (!prop || !len)
1699                 return 0;
1700
1701         words = len / sizeof(u32);
1702
1703         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1704                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1705                 return 0;
1706         }
1707
1708         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1709         if (!pdata->phy_init_seq)
1710                 return 0;
1711
1712         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1713                                          pdata->phy_init_seq, words);
1714         if (!ret)
1715                 pdata->phy_init_sz = words;
1716
1717         return 0;
1718 }
1719
1720 static int msm_otg_reboot_notify(struct notifier_block *this,
1721                                  unsigned long code, void *unused)
1722 {
1723         struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1724
1725         /*
1726          * Ensure that D+/D- lines are routed to uB connector, so
1727          * we could load bootloader/kernel at next reboot
1728          */
1729         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1730         return NOTIFY_DONE;
1731 }
1732
1733 static int msm_otg_probe(struct platform_device *pdev)
1734 {
1735         int ret = 0;
1736         struct device_node *np = pdev->dev.of_node;
1737         struct msm_otg_platform_data *pdata;
1738         struct resource *res;
1739         struct msm_otg *motg;
1740         struct usb_phy *phy;
1741         void __iomem *phy_select;
1742
1743         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1744         if (!motg)
1745                 return -ENOMEM;
1746
1747         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1748                                      GFP_KERNEL);
1749         if (!motg->phy.otg)
1750                 return -ENOMEM;
1751
1752         phy = &motg->phy;
1753         phy->dev = &pdev->dev;
1754
1755         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1756         if (IS_ERR(motg->clk)) {
1757                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1758                 return PTR_ERR(motg->clk);
1759         }
1760
1761         /*
1762          * If USB Core is running its protocol engine based on CORE CLK,
1763          * CORE CLK  must be running at >55Mhz for correct HSUSB
1764          * operation and USB core cannot tolerate frequency changes on
1765          * CORE CLK.
1766          */
1767         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1768         if (IS_ERR(motg->pclk)) {
1769                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1770                 return PTR_ERR(motg->pclk);
1771         }
1772
1773         /*
1774          * USB core clock is not present on all MSM chips. This
1775          * clock is introduced to remove the dependency on AXI
1776          * bus frequency.
1777          */
1778         motg->core_clk = devm_clk_get(&pdev->dev,
1779                                       np ? "alt_core" : "usb_hs_core_clk");
1780
1781         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782         if (!res)
1783                 return -EINVAL;
1784         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1785         if (!motg->regs)
1786                 return -ENOMEM;
1787
1788         pdata = dev_get_platdata(&pdev->dev);
1789         if (!pdata) {
1790                 if (!np)
1791                         return -ENXIO;
1792                 ret = msm_otg_read_dt(pdev, motg);
1793                 if (ret)
1794                         return ret;
1795         }
1796
1797         /*
1798          * NOTE: The PHYs can be multiplexed between the chipidea controller
1799          * and the dwc3 controller, using a single bit. It is important that
1800          * the dwc3 driver does not set this bit in an incompatible way.
1801          */
1802         if (motg->phy_number) {
1803                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1804                 if (!phy_select)
1805                         return -ENOMEM;
1806
1807                 /* Enable second PHY with the OTG port */
1808                 writel(0x1, phy_select);
1809         }
1810
1811         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1812
1813         motg->irq = platform_get_irq(pdev, 0);
1814         if (motg->irq < 0) {
1815                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1816                 ret = motg->irq;
1817                 return motg->irq;
1818         }
1819
1820         motg->supplies[0].supply = "vddcx";
1821         motg->supplies[1].supply = "v3p3";
1822         motg->supplies[2].supply = "v1p8";
1823
1824         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(motg->supplies),
1825                                       motg->supplies);
1826         if (ret)
1827                 return ret;
1828
1829         motg->vddcx = motg->supplies[0].consumer;
1830         motg->v3p3  = motg->supplies[1].consumer;
1831         motg->v1p8  = motg->supplies[2].consumer;
1832
1833         clk_set_rate(motg->clk, 60000000);
1834
1835         clk_prepare_enable(motg->clk);
1836         clk_prepare_enable(motg->pclk);
1837
1838         if (!IS_ERR(motg->core_clk))
1839                 clk_prepare_enable(motg->core_clk);
1840
1841         ret = msm_hsusb_init_vddcx(motg, 1);
1842         if (ret) {
1843                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1844                 goto disable_clks;
1845         }
1846
1847         ret = msm_hsusb_ldo_init(motg, 1);
1848         if (ret) {
1849                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1850                 goto disable_vddcx;
1851         }
1852         ret = msm_hsusb_ldo_set_mode(motg, 1);
1853         if (ret) {
1854                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1855                 goto disable_ldo;
1856         }
1857
1858         writel(0, USB_USBINTR);
1859         writel(0, USB_OTGSC);
1860
1861         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1862         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1863         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1864                                         "msm_otg", motg);
1865         if (ret) {
1866                 dev_err(&pdev->dev, "request irq failed\n");
1867                 goto disable_ldo;
1868         }
1869
1870         phy->init = msm_phy_init;
1871         phy->notify_disconnect = msm_phy_notify_disconnect;
1872         phy->type = USB_PHY_TYPE_USB2;
1873         phy->vbus_nb.notifier_call = msm_otg_vbus_notifier;
1874         phy->id_nb.notifier_call = msm_otg_id_notifier;
1875
1876         phy->io_ops = &msm_otg_io_ops;
1877
1878         phy->otg->usb_phy = &motg->phy;
1879         phy->otg->set_host = msm_otg_set_host;
1880         phy->otg->set_peripheral = msm_otg_set_peripheral;
1881
1882         msm_usb_reset(phy);
1883
1884         ret = usb_add_phy_dev(&motg->phy);
1885         if (ret) {
1886                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1887                 goto disable_ldo;
1888         }
1889
1890         ret = extcon_get_state(phy->edev, EXTCON_USB);
1891         if (ret)
1892                 set_bit(B_SESS_VLD, &motg->inputs);
1893         else
1894                 clear_bit(B_SESS_VLD, &motg->inputs);
1895
1896         ret = extcon_get_state(phy->id_edev, EXTCON_USB_HOST);
1897         if (ret)
1898                 clear_bit(ID, &motg->inputs);
1899         else
1900                 set_bit(ID, &motg->inputs);
1901
1902         platform_set_drvdata(pdev, motg);
1903         device_init_wakeup(&pdev->dev, 1);
1904
1905         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1906                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1907                 ret = msm_otg_debugfs_init(motg);
1908                 if (ret)
1909                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1910         }
1911
1912         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1913                 /* Switch D+/D- lines to Device connector */
1914                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1915         } else {
1916                 /* Switch D+/D- lines to Hub */
1917                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1918         }
1919
1920         motg->reboot.notifier_call = msm_otg_reboot_notify;
1921         register_reboot_notifier(&motg->reboot);
1922
1923         pm_runtime_set_active(&pdev->dev);
1924         pm_runtime_enable(&pdev->dev);
1925
1926         return 0;
1927
1928 disable_ldo:
1929         msm_hsusb_ldo_init(motg, 0);
1930 disable_vddcx:
1931         msm_hsusb_init_vddcx(motg, 0);
1932 disable_clks:
1933         clk_disable_unprepare(motg->pclk);
1934         clk_disable_unprepare(motg->clk);
1935         if (!IS_ERR(motg->core_clk))
1936                 clk_disable_unprepare(motg->core_clk);
1937
1938         return ret;
1939 }
1940
1941 static int msm_otg_remove(struct platform_device *pdev)
1942 {
1943         struct msm_otg *motg = platform_get_drvdata(pdev);
1944         struct usb_phy *phy = &motg->phy;
1945         int cnt = 0;
1946
1947         if (phy->otg->host || phy->otg->gadget)
1948                 return -EBUSY;
1949
1950         unregister_reboot_notifier(&motg->reboot);
1951
1952         /*
1953          * Ensure that D+/D- lines are routed to uB connector, so
1954          * we could load bootloader/kernel at next reboot
1955          */
1956         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1957
1958         msm_otg_debugfs_cleanup();
1959         cancel_delayed_work_sync(&motg->chg_work);
1960         cancel_work_sync(&motg->sm_work);
1961
1962         pm_runtime_resume(&pdev->dev);
1963
1964         device_init_wakeup(&pdev->dev, 0);
1965         pm_runtime_disable(&pdev->dev);
1966
1967         usb_remove_phy(phy);
1968         disable_irq(motg->irq);
1969
1970         /*
1971          * Put PHY in low power mode.
1972          */
1973         ulpi_read(phy, 0x14);
1974         ulpi_write(phy, 0x08, 0x09);
1975
1976         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1977         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1978                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1979                         break;
1980                 udelay(1);
1981                 cnt++;
1982         }
1983         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1984                 dev_err(phy->dev, "Unable to suspend PHY\n");
1985
1986         clk_disable_unprepare(motg->pclk);
1987         clk_disable_unprepare(motg->clk);
1988         if (!IS_ERR(motg->core_clk))
1989                 clk_disable_unprepare(motg->core_clk);
1990         msm_hsusb_ldo_init(motg, 0);
1991
1992         pm_runtime_set_suspended(&pdev->dev);
1993
1994         return 0;
1995 }
1996
1997 #ifdef CONFIG_PM
1998 static int msm_otg_runtime_idle(struct device *dev)
1999 {
2000         struct msm_otg *motg = dev_get_drvdata(dev);
2001         struct usb_otg *otg = motg->phy.otg;
2002
2003         dev_dbg(dev, "OTG runtime idle\n");
2004
2005         /*
2006          * It is observed some times that a spurious interrupt
2007          * comes when PHY is put into LPM immediately after PHY reset.
2008          * This 1 sec delay also prevents entering into LPM immediately
2009          * after asynchronous interrupt.
2010          */
2011         if (otg->state != OTG_STATE_UNDEFINED)
2012                 pm_schedule_suspend(dev, 1000);
2013
2014         return -EAGAIN;
2015 }
2016
2017 static int msm_otg_runtime_suspend(struct device *dev)
2018 {
2019         struct msm_otg *motg = dev_get_drvdata(dev);
2020
2021         dev_dbg(dev, "OTG runtime suspend\n");
2022         return msm_otg_suspend(motg);
2023 }
2024
2025 static int msm_otg_runtime_resume(struct device *dev)
2026 {
2027         struct msm_otg *motg = dev_get_drvdata(dev);
2028
2029         dev_dbg(dev, "OTG runtime resume\n");
2030         return msm_otg_resume(motg);
2031 }
2032 #endif
2033
2034 #ifdef CONFIG_PM_SLEEP
2035 static int msm_otg_pm_suspend(struct device *dev)
2036 {
2037         struct msm_otg *motg = dev_get_drvdata(dev);
2038
2039         dev_dbg(dev, "OTG PM suspend\n");
2040         return msm_otg_suspend(motg);
2041 }
2042
2043 static int msm_otg_pm_resume(struct device *dev)
2044 {
2045         struct msm_otg *motg = dev_get_drvdata(dev);
2046         int ret;
2047
2048         dev_dbg(dev, "OTG PM resume\n");
2049
2050         ret = msm_otg_resume(motg);
2051         if (ret)
2052                 return ret;
2053
2054         /*
2055          * Runtime PM Documentation recommends bringing the
2056          * device to full powered state upon resume.
2057          */
2058         pm_runtime_disable(dev);
2059         pm_runtime_set_active(dev);
2060         pm_runtime_enable(dev);
2061
2062         return 0;
2063 }
2064 #endif
2065
2066 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
2067         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
2068         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
2069                                 msm_otg_runtime_idle)
2070 };
2071
2072 static struct platform_driver msm_otg_driver = {
2073         .probe = msm_otg_probe,
2074         .remove = msm_otg_remove,
2075         .driver = {
2076                 .name = DRIVER_NAME,
2077                 .pm = &msm_otg_dev_pm_ops,
2078                 .of_match_table = msm_otg_dt_match,
2079         },
2080 };
2081
2082 module_platform_driver(msm_otg_driver);
2083
2084 MODULE_LICENSE("GPL v2");
2085 MODULE_DESCRIPTION("MSM USB transceiver driver");