drivers/usb/musb/musbhsdma.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MUSB OTG driver - support for Mentor's DMA controller
   4  *
   5  * Copyright 2005 Mentor Graphics Corporation
   6  * Copyright (C) 2005-2007 by Texas Instruments
   7  */
   8 #include <linux/device.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12 #include "musb_core.h"
  13
  14 #define MUSB_HSDMA_BASE         0x200
  15 #define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
  16 #define MUSB_HSDMA_CONTROL              0x4
  17 #define MUSB_HSDMA_ADDRESS              0x8
  18 #define MUSB_HSDMA_COUNT                0xc
  19
  20 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
  21                 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
  22
  23 #define musb_read_hsdma_addr(mbase, bchannel)   \
  24         musb_readl(mbase,       \
  25                    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
  26
  27 #define musb_write_hsdma_addr(mbase, bchannel, addr) \
  28         musb_writel(mbase, \
  29                     MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
  30                     addr)
  31
  32 #define musb_read_hsdma_count(mbase, bchannel)  \
  33         musb_readl(mbase,       \
  34                    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
  35
  36 #define musb_write_hsdma_count(mbase, bchannel, len) \
  37         musb_writel(mbase, \
  38                     MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
  39                     len)
  40 /* control register (16-bit): */
  41 #define MUSB_HSDMA_ENABLE_SHIFT         0
  42 #define MUSB_HSDMA_TRANSMIT_SHIFT       1
  43 #define MUSB_HSDMA_MODE1_SHIFT          2
  44 #define MUSB_HSDMA_IRQENABLE_SHIFT      3
  45 #define MUSB_HSDMA_ENDPOINT_SHIFT       4
  46 #define MUSB_HSDMA_BUSERROR_SHIFT       8
  47 #define MUSB_HSDMA_BURSTMODE_SHIFT      9
  48 #define MUSB_HSDMA_BURSTMODE            (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
  49 #define MUSB_HSDMA_BURSTMODE_UNSPEC     0
  50 #define MUSB_HSDMA_BURSTMODE_INCR4      1
  51 #define MUSB_HSDMA_BURSTMODE_INCR8      2
  52 #define MUSB_HSDMA_BURSTMODE_INCR16     3
  53
  54 #define MUSB_HSDMA_CHANNELS             8
  55
  56 struct musb_dma_controller;
  57
  58 struct musb_dma_channel {
  59         struct dma_channel              channel;
  60         struct musb_dma_controller      *controller;
  61         u32                             start_addr;
  62         u32                             len;
  63         u16                             max_packet_sz;
  64         u8                              idx;
  65         u8                              epnum;
  66         u8                              transmit;
  67 };
  68
  69 struct musb_dma_controller {
  70         struct dma_controller           controller;
  71         struct musb_dma_channel         channel[MUSB_HSDMA_CHANNELS];
  72         void                            *private_data;
  73         void __iomem                    *base;
  74         u8                              channel_count;
  75         u8                              used_channels;
  76         int                             irq;
  77 };
  78
  79 static void dma_channel_release(struct dma_channel *channel);
  80
  81 static void dma_controller_stop(struct musb_dma_controller *controller)
  82 {
  83         struct musb *musb = controller->private_data;
  84         struct dma_channel *channel;
  85         u8 bit;
  86
  87         if (controller->used_channels != 0) {
  88                 dev_err(musb->controller,
  89                         "Stopping DMA controller while channel active\n");
  90
  91                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  92                         if (controller->used_channels & (1 << bit)) {
  93                                 channel = &controller->channel[bit].channel;
  94                                 dma_channel_release(channel);
  95
  96                                 if (!controller->used_channels)
  97                                         break;
  98                         }
  99                 }
 100         }
 101 }
 102
 103 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
 104                                 struct musb_hw_ep *hw_ep, u8 transmit)
 105 {
 106         struct musb_dma_controller *controller = container_of(c,
 107                         struct musb_dma_controller, controller);
 108         struct musb_dma_channel *musb_channel = NULL;
 109         struct dma_channel *channel = NULL;
 110         u8 bit;
 111
 112         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
 113                 if (!(controller->used_channels & (1 << bit))) {
 114                         controller->used_channels |= (1 << bit);
 115                         musb_channel = &(controller->channel[bit]);
 116                         musb_channel->controller = controller;
 117                         musb_channel->idx = bit;
 118                         musb_channel->epnum = hw_ep->epnum;
 119                         musb_channel->transmit = transmit;
 120                         channel = &(musb_channel->channel);
 121                         channel->private_data = musb_channel;
 122                         channel->status = MUSB_DMA_STATUS_FREE;
 123                         channel->max_len = 0x100000;
 124                         /* Tx => mode 1; Rx => mode 0 */
 125                         channel->desired_mode = transmit;
 126                         channel->actual_len = 0;
 127                         break;
 128                 }
 129         }
 130
 131         return channel;
 132 }
 133
 134 static void dma_channel_release(struct dma_channel *channel)
 135 {
 136         struct musb_dma_channel *musb_channel = channel->private_data;
 137
 138         channel->actual_len = 0;
 139         musb_channel->start_addr = 0;
 140         musb_channel->len = 0;
 141
 142         musb_channel->controller->used_channels &=
 143                 ~(1 << musb_channel->idx);
 144
 145         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 146 }
 147
 148 static void configure_channel(struct dma_channel *channel,
 149                                 u16 packet_sz, u8 mode,
 150                                 dma_addr_t dma_addr, u32 len)
 151 {
 152         struct musb_dma_channel *musb_channel = channel->private_data;
 153         struct musb_dma_controller *controller = musb_channel->controller;
 154         struct musb *musb = controller->private_data;
 155         void __iomem *mbase = controller->base;
 156         u8 bchannel = musb_channel->idx;
 157         u16 csr = 0;
 158
 159         musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
 160                         channel, packet_sz, &dma_addr, len, mode);
 161
 162         if (mode) {
 163                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 164                 BUG_ON(len < packet_sz);
 165         }
 166         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 167                                 << MUSB_HSDMA_BURSTMODE_SHIFT;
 168
 169         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 170                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 171                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 172                 | (musb_channel->transmit
 173                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 174                                 : 0);
 175
 176         /* address/count */
 177         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 178         musb_write_hsdma_count(mbase, bchannel, len);
 179
 180         /* control (this should start things) */
 181         musb_writew(mbase,
 182                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 183                 csr);
 184 }
 185
 186 static int dma_channel_program(struct dma_channel *channel,
 187                                 u16 packet_sz, u8 mode,
 188                                 dma_addr_t dma_addr, u32 len)
 189 {
 190         struct musb_dma_channel *musb_channel = channel->private_data;
 191         struct musb_dma_controller *controller = musb_channel->controller;
 192         struct musb *musb = controller->private_data;
 193
 194         musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
 195                 musb_channel->epnum,
 196                 musb_channel->transmit ? "Tx" : "Rx",
 197                 packet_sz, &dma_addr, len, mode);
 198
 199         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 200                 channel->status == MUSB_DMA_STATUS_BUSY);
 201
 202         /*
 203          * The DMA engine in RTL1.8 and above cannot handle
 204          * DMA addresses that are not aligned to a 4 byte boundary.
 205          * It ends up masking the last two bits of the address
 206          * programmed in DMA_ADDR.
 207          *
 208          * Fail such DMA transfers, so that the backup PIO mode
 209          * can carry out the transfer
 210          */
 211         if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
 212                 return false;
 213
 214         channel->actual_len = 0;
 215         musb_channel->start_addr = dma_addr;
 216         musb_channel->len = len;
 217         musb_channel->max_packet_sz = packet_sz;
 218         channel->status = MUSB_DMA_STATUS_BUSY;
 219
 220         configure_channel(channel, packet_sz, mode, dma_addr, len);
 221
 222         return true;
 223 }
 224
 225 static int dma_channel_abort(struct dma_channel *channel)
 226 {
 227         struct musb_dma_channel *musb_channel = channel->private_data;
 228         void __iomem *mbase = musb_channel->controller->base;
 229         struct musb *musb = musb_channel->controller->private_data;
 230
 231         u8 bchannel = musb_channel->idx;
 232         int offset;
 233         u16 csr;
 234
 235         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 236                 if (musb_channel->transmit) {
 237                         offset = musb->io.ep_offset(musb_channel->epnum,
 238                                                 MUSB_TXCSR);
 239
 240                         /*
 241                          * The programming guide says that we must clear
 242                          * the DMAENAB bit before the DMAMODE bit...
 243                          */
 244                         csr = musb_readw(mbase, offset);
 245                         csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
 246                         musb_writew(mbase, offset, csr);
 247                         csr &= ~MUSB_TXCSR_DMAMODE;
 248                         musb_writew(mbase, offset, csr);
 249                 } else {
 250                         offset = musb->io.ep_offset(musb_channel->epnum,
 251                                                 MUSB_RXCSR);
 252
 253                         csr = musb_readw(mbase, offset);
 254                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 255                                  MUSB_RXCSR_DMAENAB |
 256                                  MUSB_RXCSR_DMAMODE);
 257                         musb_writew(mbase, offset, csr);
 258                 }
 259
 260                 musb_writew(mbase,
 261                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 262                         0);
 263                 musb_write_hsdma_addr(mbase, bchannel, 0);
 264                 musb_write_hsdma_count(mbase, bchannel, 0);
 265                 channel->status = MUSB_DMA_STATUS_FREE;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 272 {
 273         struct musb_dma_controller *controller = private_data;
 274         struct musb *musb = controller->private_data;
 275         struct musb_dma_channel *musb_channel;
 276         struct dma_channel *channel;
 277
 278         void __iomem *mbase = controller->base;
 279
 280         irqreturn_t retval = IRQ_NONE;
 281
 282         unsigned long flags;
 283
 284         u8 bchannel;
 285         u8 int_hsdma;
 286
 287         u32 addr, count;
 288         u16 csr;
 289
 290         spin_lock_irqsave(&musb->lock, flags);
 291
 292         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 293
 294         if (!int_hsdma) {
 295                 musb_dbg(musb, "spurious DMA irq");
 296
 297                 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 298                         musb_channel = (struct musb_dma_channel *)
 299                                         &(controller->channel[bchannel]);
 300                         channel = &musb_channel->channel;
 301                         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 302                                 count = musb_read_hsdma_count(mbase, bchannel);
 303
 304                                 if (count == 0)
 305                                         int_hsdma |= (1 << bchannel);
 306                         }
 307                 }
 308
 309                 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
 310
 311                 if (!int_hsdma)
 312                         goto done;
 313         }
 314
 315         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 316                 if (int_hsdma & (1 << bchannel)) {
 317                         musb_channel = (struct musb_dma_channel *)
 318                                         &(controller->channel[bchannel]);
 319                         channel = &musb_channel->channel;
 320
 321                         csr = musb_readw(mbase,
 322                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 323                                                         MUSB_HSDMA_CONTROL));
 324
 325                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 326                                 musb_channel->channel.status =
 327                                         MUSB_DMA_STATUS_BUS_ABORT;
 328                         } else {
 329                                 u8 devctl;
 330
 331                                 addr = musb_read_hsdma_addr(mbase,
 332                                                 bchannel);
 333                                 channel->actual_len = addr
 334                                         - musb_channel->start_addr;
 335
 336                                 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
 337                                         channel, musb_channel->start_addr,
 338                                         addr, channel->actual_len,
 339                                         musb_channel->len,
 340                                         (channel->actual_len
 341                                                 < musb_channel->len) ?
 342                                         "=> reconfig 0" : "=> complete");
 343
 344                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 345
 346                                 channel->status = MUSB_DMA_STATUS_FREE;
 347
 348                                 /* completed */
 349                                 if (musb_channel->transmit &&
 350                                         (!channel->desired_mode ||
 351                                         (channel->actual_len %
 352                                             musb_channel->max_packet_sz))) {
 353                                         u8  epnum  = musb_channel->epnum;
 354                                         int offset = musb->io.ep_offset(epnum,
 355                                                                     MUSB_TXCSR);
 356                                         u16 txcsr;
 357
 358                                         /*
 359                                          * The programming guide says that we
 360                                          * must clear DMAENAB before DMAMODE.
 361                                          */
 362                                         musb_ep_select(mbase, epnum);
 363                                         txcsr = musb_readw(mbase, offset);
 364                                         if (channel->desired_mode == 1) {
 365                                                 txcsr &= ~(MUSB_TXCSR_DMAENAB
 366                                                         | MUSB_TXCSR_AUTOSET);
 367                                                 musb_writew(mbase, offset, txcsr);
 368                                                 /* Send out the packet */
 369                                                 txcsr &= ~MUSB_TXCSR_DMAMODE;
 370                                                 txcsr |= MUSB_TXCSR_DMAENAB;
 371                                         }
 372                                         txcsr |=  MUSB_TXCSR_TXPKTRDY;
 373                                         musb_writew(mbase, offset, txcsr);
 374                                 }
 375                                 musb_dma_completion(musb, musb_channel->epnum,
 376                                                     musb_channel->transmit);
 377                         }
 378                 }
 379         }
 380
 381         retval = IRQ_HANDLED;
 382 done:
 383         spin_unlock_irqrestore(&musb->lock, flags);
 384         return retval;
 385 }
 386
 387 void musbhs_dma_controller_destroy(struct dma_controller *c)
 388 {
 389         struct musb_dma_controller *controller = container_of(c,
 390                         struct musb_dma_controller, controller);
 391
 392         dma_controller_stop(controller);
 393
 394         if (controller->irq)
 395                 free_irq(controller->irq, c);
 396
 397         kfree(controller);
 398 }
 399 EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
 400
 401 struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
 402                                                     void __iomem *base)
 403 {
 404         struct musb_dma_controller *controller;
 405         struct device *dev = musb->controller;
 406         struct platform_device *pdev = to_platform_device(dev);
 407         int irq = platform_get_irq_byname(pdev, "dma");
 408
 409         if (irq <= 0) {
 410                 dev_err(dev, "No DMA interrupt line!\n");
 411                 return NULL;
 412         }
 413
 414         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 415         if (!controller)
 416                 return NULL;
 417
 418         controller->channel_count = MUSB_HSDMA_CHANNELS;
 419         controller->private_data = musb;
 420         controller->base = base;
 421
 422         controller->controller.channel_alloc = dma_channel_allocate;
 423         controller->controller.channel_release = dma_channel_release;
 424         controller->controller.channel_program = dma_channel_program;
 425         controller->controller.channel_abort = dma_channel_abort;
 426
 427         if (request_irq(irq, dma_controller_irq, 0,
 428                         dev_name(musb->controller), &controller->controller)) {
 429                 dev_err(dev, "request_irq %d failed!\n", irq);
 430                 musb_dma_controller_destroy(&controller->controller);
 431
 432                 return NULL;
 433         }
 434
 435         controller->irq = irq;
 436
 437         return &controller->controller;
 438 }
 439 EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);