2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk;
43 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks;
47 module_param(quirks, uint, S_IRUGO);
48 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70 if (result == ~(u32)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd *xhci)
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 cmd = readl(&xhci->op_regs->command);
97 writel(cmd, &xhci->op_regs->command);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd *xhci)
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
117 xhci_warn(xhci, "Host halt failed, %d\n", ret);
120 xhci->xhc_state |= XHCI_STATE_HALTED;
121 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126 * Set the run bit and wait for the host to be running.
128 int xhci_start(struct xhci_hcd *xhci)
133 temp = readl(&xhci->op_regs->command);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
137 writel(temp, &xhci->op_regs->command);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
171 if (state == ~(u32)0) {
172 xhci_warn(xhci, "Host not accessible, reset failed.\n");
176 if ((state & STS_HALT) == 0) {
177 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
182 command = readl(&xhci->op_regs->command);
183 command |= CMD_RESET;
184 writel(command, &xhci->op_regs->command);
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
193 if (xhci->quirks & XHCI_INTEL_HOST)
196 ret = xhci_handshake(&xhci->op_regs->command,
197 CMD_RESET, 0, 10 * 1000 * 1000);
201 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
202 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
204 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
205 "Wait for controller to be ready for doorbell rings");
207 * xHCI cannot write to any doorbells or operational registers other
208 * than status until the "Controller Not Ready" flag is cleared.
210 ret = xhci_handshake(&xhci->op_regs->status,
211 STS_CNR, 0, 10 * 1000 * 1000);
213 for (i = 0; i < 2; i++) {
214 xhci->bus_state[i].port_c_suspend = 0;
215 xhci->bus_state[i].suspended_ports = 0;
216 xhci->bus_state[i].resuming_ports = 0;
223 #ifdef CONFIG_USB_PCI
227 static int xhci_setup_msi(struct xhci_hcd *xhci)
231 * TODO:Check with MSI Soc for sysdev
233 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
235 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
237 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
238 "failed to allocate MSI entry");
242 ret = request_irq(pdev->irq, xhci_msi_irq,
243 0, "xhci_hcd", xhci_to_hcd(xhci));
245 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
246 "disable MSI interrupt");
247 pci_free_irq_vectors(pdev);
256 static int xhci_setup_msix(struct xhci_hcd *xhci)
259 struct usb_hcd *hcd = xhci_to_hcd(xhci);
260 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
263 * calculate number of msi-x vectors supported.
264 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
265 * with max number of interrupters based on the xhci HCSPARAMS1.
266 * - num_online_cpus: maximum msi-x vectors per CPUs core.
267 * Add additional 1 vector to ensure always available interrupt.
269 xhci->msix_count = min(num_online_cpus() + 1,
270 HCS_MAX_INTRS(xhci->hcs_params1));
272 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
275 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
276 "Failed to enable MSI-X");
280 for (i = 0; i < xhci->msix_count; i++) {
281 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
282 "xhci_hcd", xhci_to_hcd(xhci));
287 hcd->msix_enabled = 1;
291 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
293 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
294 pci_free_irq_vectors(pdev);
298 /* Free any IRQs and disable MSI-X */
299 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
301 struct usb_hcd *hcd = xhci_to_hcd(xhci);
302 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
304 if (xhci->quirks & XHCI_PLAT)
307 /* return if using legacy interrupt */
311 if (hcd->msix_enabled) {
314 for (i = 0; i < xhci->msix_count; i++)
315 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
317 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
320 pci_free_irq_vectors(pdev);
321 hcd->msix_enabled = 0;
324 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
326 struct usb_hcd *hcd = xhci_to_hcd(xhci);
328 if (hcd->msix_enabled) {
329 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
332 for (i = 0; i < xhci->msix_count; i++)
333 synchronize_irq(pci_irq_vector(pdev, i));
337 static int xhci_try_enable_msi(struct usb_hcd *hcd)
339 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
340 struct pci_dev *pdev;
343 /* The xhci platform device has set up IRQs through usb_add_hcd. */
344 if (xhci->quirks & XHCI_PLAT)
347 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
349 * Some Fresco Logic host controllers advertise MSI, but fail to
350 * generate interrupts. Don't even try to enable MSI.
352 if (xhci->quirks & XHCI_BROKEN_MSI)
355 /* unregister the legacy interrupt */
357 free_irq(hcd->irq, hcd);
360 ret = xhci_setup_msix(xhci);
362 /* fall back to msi*/
363 ret = xhci_setup_msi(xhci);
366 hcd->msi_enabled = 1;
371 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
376 if (!strlen(hcd->irq_descr))
377 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
378 hcd->driver->description, hcd->self.busnum);
380 /* fall back to legacy interrupt*/
381 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
382 hcd->irq_descr, hcd);
384 xhci_err(xhci, "request interrupt %d failed\n",
388 hcd->irq = pdev->irq;
394 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
399 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
403 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
409 static void compliance_mode_recovery(unsigned long arg)
411 struct xhci_hcd *xhci;
416 xhci = (struct xhci_hcd *)arg;
418 for (i = 0; i < xhci->num_usb3_ports; i++) {
419 temp = readl(xhci->usb3_ports[i]);
420 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
422 * Compliance Mode Detected. Letting USB Core
423 * handle the Warm Reset
425 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
426 "Compliance mode detected->port %d",
428 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
429 "Attempting compliance mode recovery");
430 hcd = xhci->shared_hcd;
432 if (hcd->state == HC_STATE_SUSPENDED)
433 usb_hcd_resume_root_hub(hcd);
435 usb_hcd_poll_rh_status(hcd);
439 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
440 mod_timer(&xhci->comp_mode_recovery_timer,
441 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
445 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
446 * that causes ports behind that hardware to enter compliance mode sometimes.
447 * The quirk creates a timer that polls every 2 seconds the link state of
448 * each host controller's port and recovers it by issuing a Warm reset
449 * if Compliance mode is detected, otherwise the port will become "dead" (no
450 * device connections or disconnections will be detected anymore). Becasue no
451 * status event is generated when entering compliance mode (per xhci spec),
452 * this quirk is needed on systems that have the failing hardware installed.
454 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
456 xhci->port_status_u0 = 0;
457 setup_timer(&xhci->comp_mode_recovery_timer,
458 compliance_mode_recovery, (unsigned long)xhci);
459 xhci->comp_mode_recovery_timer.expires = jiffies +
460 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
462 add_timer(&xhci->comp_mode_recovery_timer);
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Compliance mode recovery timer initialized");
468 * This function identifies the systems that have installed the SN65LVPE502CP
469 * USB3.0 re-driver and that need the Compliance Mode Quirk.
471 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
473 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
475 const char *dmi_product_name, *dmi_sys_vendor;
477 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
478 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
479 if (!dmi_product_name || !dmi_sys_vendor)
482 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
485 if (strstr(dmi_product_name, "Z420") ||
486 strstr(dmi_product_name, "Z620") ||
487 strstr(dmi_product_name, "Z820") ||
488 strstr(dmi_product_name, "Z1 Workstation"))
494 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
496 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
501 * Initialize memory for HCD and xHC (one-time init).
503 * Program the PAGESIZE register, initialize the device context array, create
504 * device contexts (?), set up a command ring segment (or two?), create event
505 * ring (one for now).
507 static int xhci_init(struct usb_hcd *hcd)
509 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
512 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
513 spin_lock_init(&xhci->lock);
514 if (xhci->hci_version == 0x95 && link_quirk) {
515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
516 "QUIRK: Not clearing Link TRB chain bits.");
517 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
519 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
520 "xHCI doesn't need link TRB QUIRK");
522 retval = xhci_mem_init(xhci, GFP_KERNEL);
523 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
525 /* Initializing Compliance Mode Recovery Data If Needed */
526 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
527 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
528 compliance_mode_recovery_timer_init(xhci);
534 /*-------------------------------------------------------------------------*/
537 static int xhci_run_finished(struct xhci_hcd *xhci)
539 if (xhci_start(xhci)) {
543 xhci->shared_hcd->state = HC_STATE_RUNNING;
544 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
546 if (xhci->quirks & XHCI_NEC_HOST)
547 xhci_ring_cmd_db(xhci);
549 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
550 "Finished xhci_run for USB3 roothub");
555 * Start the HC after it was halted.
557 * This function is called by the USB core when the HC driver is added.
558 * Its opposite is xhci_stop().
560 * xhci_init() must be called once before this function can be called.
561 * Reset the HC, enable device slot contexts, program DCBAAP, and
562 * set command ring pointer and event ring pointer.
564 * Setup MSI-X vectors and enable interrupts.
566 int xhci_run(struct usb_hcd *hcd)
571 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
573 /* Start the xHCI host controller running only after the USB 2.0 roothub
577 hcd->uses_new_polling = 1;
578 if (!usb_hcd_is_primary_hcd(hcd))
579 return xhci_run_finished(xhci);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
583 ret = xhci_try_enable_msi(hcd);
587 xhci_dbg_cmd_ptrs(xhci);
589 xhci_dbg(xhci, "ERST memory map follows:\n");
590 xhci_dbg_erst(xhci, &xhci->erst);
591 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
592 temp_64 &= ~ERST_PTR_MASK;
593 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
594 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
596 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
597 "// Set the interrupt modulation register");
598 temp = readl(&xhci->ir_set->irq_control);
599 temp &= ~ER_IRQ_INTERVAL_MASK;
601 * the increment interval is 8 times as much as that defined
602 * in xHCI spec on MTK's controller
604 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
605 writel(temp, &xhci->ir_set->irq_control);
607 /* Set the HCD state before we enable the irqs */
608 temp = readl(&xhci->op_regs->command);
610 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
611 "// Enable interrupts, cmd = 0x%x.", temp);
612 writel(temp, &xhci->op_regs->command);
614 temp = readl(&xhci->ir_set->irq_pending);
615 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
616 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
617 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
618 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
619 xhci_print_ir_set(xhci, 0);
621 if (xhci->quirks & XHCI_NEC_HOST) {
622 struct xhci_command *command;
624 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
628 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
629 TRB_TYPE(TRB_NEC_GET_FW));
631 xhci_free_command(xhci, command);
633 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
634 "Finished xhci_run for USB2 roothub");
637 EXPORT_SYMBOL_GPL(xhci_run);
642 * This function is called by the USB core when the HC driver is removed.
643 * Its opposite is xhci_run().
645 * Disable device contexts, disable IRQs, and quiesce the HC.
646 * Reset the HC, finish any completed transactions, and cleanup memory.
648 static void xhci_stop(struct usb_hcd *hcd)
651 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
653 mutex_lock(&xhci->mutex);
655 /* Only halt host and free memory after both hcds are removed */
656 if (!usb_hcd_is_primary_hcd(hcd)) {
657 /* usb core will free this hcd shortly, unset pointer */
658 xhci->shared_hcd = NULL;
659 mutex_unlock(&xhci->mutex);
663 spin_lock_irq(&xhci->lock);
664 xhci->xhc_state |= XHCI_STATE_HALTED;
665 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
668 spin_unlock_irq(&xhci->lock);
670 xhci_cleanup_msix(xhci);
672 /* Deleting Compliance Mode Recovery Timer */
673 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
674 (!(xhci_all_ports_seen_u0(xhci)))) {
675 del_timer_sync(&xhci->comp_mode_recovery_timer);
676 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
677 "%s: compliance mode recovery timer deleted",
681 if (xhci->quirks & XHCI_AMD_PLL_FIX)
684 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
685 "// Disabling event ring interrupts");
686 temp = readl(&xhci->op_regs->status);
687 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
688 temp = readl(&xhci->ir_set->irq_pending);
689 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
690 xhci_print_ir_set(xhci, 0);
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
693 xhci_mem_cleanup(xhci);
694 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
695 "xhci_stop completed - status = %x",
696 readl(&xhci->op_regs->status));
697 mutex_unlock(&xhci->mutex);
701 * Shutdown HC (not bus-specific)
703 * This is called when the machine is rebooting or halting. We assume that the
704 * machine will be powered off, and the HC's internal state will be reset.
705 * Don't bother to free memory.
707 * This will only ever be called with the main usb_hcd (the USB3 roothub).
709 static void xhci_shutdown(struct usb_hcd *hcd)
711 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
713 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
714 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
716 spin_lock_irq(&xhci->lock);
718 /* Workaround for spurious wakeups at shutdown with HSW */
719 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
721 spin_unlock_irq(&xhci->lock);
723 xhci_cleanup_msix(xhci);
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
726 "xhci_shutdown completed - status = %x",
727 readl(&xhci->op_regs->status));
729 /* Yet another workaround for spurious wakeups at shutdown with HSW */
730 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
731 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
735 static void xhci_save_registers(struct xhci_hcd *xhci)
737 xhci->s3.command = readl(&xhci->op_regs->command);
738 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
739 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
740 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
741 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
742 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
743 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
744 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
745 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
748 static void xhci_restore_registers(struct xhci_hcd *xhci)
750 writel(xhci->s3.command, &xhci->op_regs->command);
751 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
752 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
753 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
754 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
755 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
756 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
757 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
758 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
761 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
765 /* step 2: initialize command ring buffer */
766 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
767 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
768 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
769 xhci->cmd_ring->dequeue) &
770 (u64) ~CMD_RING_RSVD_BITS) |
771 xhci->cmd_ring->cycle_state;
772 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
773 "// Setting command ring address to 0x%llx",
774 (long unsigned long) val_64);
775 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
779 * The whole command ring must be cleared to zero when we suspend the host.
781 * The host doesn't save the command ring pointer in the suspend well, so we
782 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
783 * aligned, because of the reserved bits in the command ring dequeue pointer
784 * register. Therefore, we can't just set the dequeue pointer back in the
785 * middle of the ring (TRBs are 16-byte aligned).
787 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
789 struct xhci_ring *ring;
790 struct xhci_segment *seg;
792 ring = xhci->cmd_ring;
796 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
797 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
798 cpu_to_le32(~TRB_CYCLE);
800 } while (seg != ring->deq_seg);
802 /* Reset the software enqueue and dequeue pointers */
803 ring->deq_seg = ring->first_seg;
804 ring->dequeue = ring->first_seg->trbs;
805 ring->enq_seg = ring->deq_seg;
806 ring->enqueue = ring->dequeue;
808 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
810 * Ring is now zeroed, so the HW should look for change of ownership
811 * when the cycle bit is set to 1.
813 ring->cycle_state = 1;
816 * Reset the hardware dequeue pointer.
817 * Yes, this will need to be re-written after resume, but we're paranoid
818 * and want to make sure the hardware doesn't access bogus memory
819 * because, say, the BIOS or an SMI started the host without changing
820 * the command ring pointers.
822 xhci_set_cmd_ring_deq(xhci);
825 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
828 __le32 __iomem **port_array;
832 spin_lock_irqsave(&xhci->lock, flags);
834 /* disable usb3 ports Wake bits */
835 port_index = xhci->num_usb3_ports;
836 port_array = xhci->usb3_ports;
837 while (port_index--) {
838 t1 = readl(port_array[port_index]);
839 t1 = xhci_port_state_to_neutral(t1);
840 t2 = t1 & ~PORT_WAKE_BITS;
842 writel(t2, port_array[port_index]);
845 /* disable usb2 ports Wake bits */
846 port_index = xhci->num_usb2_ports;
847 port_array = xhci->usb2_ports;
848 while (port_index--) {
849 t1 = readl(port_array[port_index]);
850 t1 = xhci_port_state_to_neutral(t1);
851 t2 = t1 & ~PORT_WAKE_BITS;
853 writel(t2, port_array[port_index]);
856 spin_unlock_irqrestore(&xhci->lock, flags);
860 * Stop HC (not bus-specific)
862 * This is called when the machine transition into S3/S4 mode.
865 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
868 unsigned int delay = XHCI_MAX_HALT_USEC;
869 struct usb_hcd *hcd = xhci_to_hcd(xhci);
875 if (hcd->state != HC_STATE_SUSPENDED ||
876 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
879 /* Clear root port wake on bits if wakeup not allowed. */
881 xhci_disable_port_wake_on_bits(xhci);
883 /* Don't poll the roothubs on bus suspend. */
884 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
885 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
886 del_timer_sync(&hcd->rh_timer);
887 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
888 del_timer_sync(&xhci->shared_hcd->rh_timer);
890 spin_lock_irq(&xhci->lock);
891 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
892 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
893 /* step 1: stop endpoint */
894 /* skipped assuming that port suspend has done */
896 /* step 2: clear Run/Stop bit */
897 command = readl(&xhci->op_regs->command);
899 writel(command, &xhci->op_regs->command);
901 /* Some chips from Fresco Logic need an extraordinary delay */
902 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
904 if (xhci_handshake(&xhci->op_regs->status,
905 STS_HALT, STS_HALT, delay)) {
906 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
907 spin_unlock_irq(&xhci->lock);
910 xhci_clear_command_ring(xhci);
912 /* step 3: save registers */
913 xhci_save_registers(xhci);
915 /* step 4: set CSS flag */
916 command = readl(&xhci->op_regs->command);
918 writel(command, &xhci->op_regs->command);
919 if (xhci_handshake(&xhci->op_regs->status,
920 STS_SAVE, 0, 10 * 1000)) {
921 xhci_warn(xhci, "WARN: xHC save state timeout\n");
922 spin_unlock_irq(&xhci->lock);
925 spin_unlock_irq(&xhci->lock);
928 * Deleting Compliance Mode Recovery Timer because the xHCI Host
929 * is about to be suspended.
931 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
932 (!(xhci_all_ports_seen_u0(xhci)))) {
933 del_timer_sync(&xhci->comp_mode_recovery_timer);
934 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
935 "%s: compliance mode recovery timer deleted",
939 /* step 5: remove core well power */
940 /* synchronize irq when using MSI-X */
941 xhci_msix_sync_irqs(xhci);
945 EXPORT_SYMBOL_GPL(xhci_suspend);
948 * start xHC (not bus-specific)
950 * This is called when the machine transition from S3/S4 mode.
953 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
955 u32 command, temp = 0, status;
956 struct usb_hcd *hcd = xhci_to_hcd(xhci);
957 struct usb_hcd *secondary_hcd;
959 bool comp_timer_running = false;
964 /* Wait a bit if either of the roothubs need to settle from the
965 * transition into bus suspend.
967 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
969 xhci->bus_state[1].next_statechange))
972 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
973 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
975 spin_lock_irq(&xhci->lock);
976 if (xhci->quirks & XHCI_RESET_ON_RESUME)
980 /* step 1: restore register */
981 xhci_restore_registers(xhci);
982 /* step 2: initialize command ring buffer */
983 xhci_set_cmd_ring_deq(xhci);
984 /* step 3: restore state and start state*/
985 /* step 3: set CRS flag */
986 command = readl(&xhci->op_regs->command);
988 writel(command, &xhci->op_regs->command);
989 if (xhci_handshake(&xhci->op_regs->status,
990 STS_RESTORE, 0, 10 * 1000)) {
991 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
992 spin_unlock_irq(&xhci->lock);
995 temp = readl(&xhci->op_regs->status);
998 /* If restore operation fails, re-initialize the HC during resume */
999 if ((temp & STS_SRE) || hibernated) {
1001 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1002 !(xhci_all_ports_seen_u0(xhci))) {
1003 del_timer_sync(&xhci->comp_mode_recovery_timer);
1004 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1005 "Compliance Mode Recovery Timer deleted!");
1008 /* Let the USB core know _both_ roothubs lost power. */
1009 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1010 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1012 xhci_dbg(xhci, "Stop HCD\n");
1015 spin_unlock_irq(&xhci->lock);
1016 xhci_cleanup_msix(xhci);
1018 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1019 temp = readl(&xhci->op_regs->status);
1020 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1021 temp = readl(&xhci->ir_set->irq_pending);
1022 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1023 xhci_print_ir_set(xhci, 0);
1025 xhci_dbg(xhci, "cleaning up memory\n");
1026 xhci_mem_cleanup(xhci);
1027 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1028 readl(&xhci->op_regs->status));
1030 /* USB core calls the PCI reinit and start functions twice:
1031 * first with the primary HCD, and then with the secondary HCD.
1032 * If we don't do the same, the host will never be started.
1034 if (!usb_hcd_is_primary_hcd(hcd))
1035 secondary_hcd = hcd;
1037 secondary_hcd = xhci->shared_hcd;
1039 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1040 retval = xhci_init(hcd->primary_hcd);
1043 comp_timer_running = true;
1045 xhci_dbg(xhci, "Start the primary HCD\n");
1046 retval = xhci_run(hcd->primary_hcd);
1048 xhci_dbg(xhci, "Start the secondary HCD\n");
1049 retval = xhci_run(secondary_hcd);
1051 hcd->state = HC_STATE_SUSPENDED;
1052 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1056 /* step 4: set Run/Stop bit */
1057 command = readl(&xhci->op_regs->command);
1059 writel(command, &xhci->op_regs->command);
1060 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1063 /* step 5: walk topology and initialize portsc,
1064 * portpmsc and portli
1066 /* this is done in bus_resume */
1068 /* step 6: restart each of the previously
1069 * Running endpoints by ringing their doorbells
1072 spin_unlock_irq(&xhci->lock);
1076 /* Resume root hubs only when have pending events. */
1077 status = readl(&xhci->op_regs->status);
1078 if (status & STS_EINT) {
1079 usb_hcd_resume_root_hub(xhci->shared_hcd);
1080 usb_hcd_resume_root_hub(hcd);
1085 * If system is subject to the Quirk, Compliance Mode Timer needs to
1086 * be re-initialized Always after a system resume. Ports are subject
1087 * to suffer the Compliance Mode issue again. It doesn't matter if
1088 * ports have entered previously to U0 before system's suspension.
1090 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1091 compliance_mode_recovery_timer_init(xhci);
1093 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1094 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1096 /* Re-enable port polling. */
1097 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1098 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1099 usb_hcd_poll_rh_status(xhci->shared_hcd);
1100 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1101 usb_hcd_poll_rh_status(hcd);
1105 EXPORT_SYMBOL_GPL(xhci_resume);
1106 #endif /* CONFIG_PM */
1108 /*-------------------------------------------------------------------------*/
1111 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1112 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1113 * value to right shift 1 for the bitmask.
1115 * Index = (epnum * 2) + direction - 1,
1116 * where direction = 0 for OUT, 1 for IN.
1117 * For control endpoints, the IN index is used (OUT index is unused), so
1118 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1120 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1123 if (usb_endpoint_xfer_control(desc))
1124 index = (unsigned int) (usb_endpoint_num(desc)*2);
1126 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1127 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1131 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1132 * address from the XHCI endpoint index.
1134 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1136 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1137 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1138 return direction | number;
1141 /* Find the flag for this endpoint (for use in the control context). Use the
1142 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1145 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1147 return 1 << (xhci_get_endpoint_index(desc) + 1);
1150 /* Find the flag for this endpoint (for use in the control context). Use the
1151 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1154 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1156 return 1 << (ep_index + 1);
1159 /* Compute the last valid endpoint context index. Basically, this is the
1160 * endpoint index plus one. For slot contexts with more than valid endpoint,
1161 * we find the most significant bit set in the added contexts flags.
1162 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1163 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1165 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1167 return fls(added_ctxs) - 1;
1170 /* Returns 1 if the arguments are OK;
1171 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1173 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1174 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1176 struct xhci_hcd *xhci;
1177 struct xhci_virt_device *virt_dev;
1179 if (!hcd || (check_ep && !ep) || !udev) {
1180 pr_debug("xHCI %s called with invalid args\n", func);
1183 if (!udev->parent) {
1184 pr_debug("xHCI %s called for root hub\n", func);
1188 xhci = hcd_to_xhci(hcd);
1189 if (check_virt_dev) {
1190 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1191 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1196 virt_dev = xhci->devs[udev->slot_id];
1197 if (virt_dev->udev != udev) {
1198 xhci_dbg(xhci, "xHCI %s called with udev and "
1199 "virt_dev does not match\n", func);
1204 if (xhci->xhc_state & XHCI_STATE_HALTED)
1210 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1211 struct usb_device *udev, struct xhci_command *command,
1212 bool ctx_change, bool must_succeed);
1215 * Full speed devices may have a max packet size greater than 8 bytes, but the
1216 * USB core doesn't know that until it reads the first 8 bytes of the
1217 * descriptor. If the usb_device's max packet size changes after that point,
1218 * we need to issue an evaluate context command and wait on it.
1220 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1221 unsigned int ep_index, struct urb *urb)
1223 struct xhci_container_ctx *out_ctx;
1224 struct xhci_input_control_ctx *ctrl_ctx;
1225 struct xhci_ep_ctx *ep_ctx;
1226 struct xhci_command *command;
1227 int max_packet_size;
1228 int hw_max_packet_size;
1231 out_ctx = xhci->devs[slot_id]->out_ctx;
1232 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1233 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1234 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1235 if (hw_max_packet_size != max_packet_size) {
1236 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1237 "Max Packet Size for ep 0 changed.");
1238 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1239 "Max packet size in usb_device = %d",
1241 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1242 "Max packet size in xHCI HW = %d",
1243 hw_max_packet_size);
1244 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1245 "Issuing evaluate context command.");
1247 /* Set up the input context flags for the command */
1248 /* FIXME: This won't work if a non-default control endpoint
1249 * changes max packet sizes.
1252 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1256 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1257 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1259 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1262 goto command_cleanup;
1264 /* Set up the modified control endpoint 0 */
1265 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1266 xhci->devs[slot_id]->out_ctx, ep_index);
1268 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1269 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1270 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1272 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1273 ctrl_ctx->drop_flags = 0;
1275 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1278 /* Clean up the input context for later use by bandwidth
1281 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1283 kfree(command->completion);
1290 * non-error returns are a promise to giveback() the urb later
1291 * we drop ownership so next owner (or urb unlink) can get it
1293 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1295 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1296 unsigned long flags;
1298 unsigned int slot_id, ep_index, ep_state;
1299 struct urb_priv *urb_priv;
1302 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1303 true, true, __func__) <= 0)
1306 slot_id = urb->dev->slot_id;
1307 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1309 if (!HCD_HW_ACCESSIBLE(hcd)) {
1310 if (!in_interrupt())
1311 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1315 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1316 num_tds = urb->number_of_packets;
1317 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1318 urb->transfer_buffer_length > 0 &&
1319 urb->transfer_flags & URB_ZERO_PACKET &&
1320 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1325 urb_priv = kzalloc(sizeof(struct urb_priv) +
1326 num_tds * sizeof(struct xhci_td), mem_flags);
1330 urb_priv->num_tds = num_tds;
1331 urb_priv->num_tds_done = 0;
1332 urb->hcpriv = urb_priv;
1334 trace_xhci_urb_enqueue(urb);
1336 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1337 /* Check to see if the max packet size for the default control
1338 * endpoint changed during FS device enumeration
1340 if (urb->dev->speed == USB_SPEED_FULL) {
1341 ret = xhci_check_maxpacket(xhci, slot_id,
1344 xhci_urb_free_priv(urb_priv);
1351 spin_lock_irqsave(&xhci->lock, flags);
1353 if (xhci->xhc_state & XHCI_STATE_DYING) {
1354 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1355 urb->ep->desc.bEndpointAddress, urb);
1360 switch (usb_endpoint_type(&urb->ep->desc)) {
1362 case USB_ENDPOINT_XFER_CONTROL:
1363 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1366 case USB_ENDPOINT_XFER_BULK:
1367 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1368 if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1369 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1374 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1379 case USB_ENDPOINT_XFER_INT:
1380 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1384 case USB_ENDPOINT_XFER_ISOC:
1385 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1391 xhci_urb_free_priv(urb_priv);
1394 spin_unlock_irqrestore(&xhci->lock, flags);
1399 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1400 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1401 * should pick up where it left off in the TD, unless a Set Transfer Ring
1402 * Dequeue Pointer is issued.
1404 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1405 * the ring. Since the ring is a contiguous structure, they can't be physically
1406 * removed. Instead, there are two options:
1408 * 1) If the HC is in the middle of processing the URB to be canceled, we
1409 * simply move the ring's dequeue pointer past those TRBs using the Set
1410 * Transfer Ring Dequeue Pointer command. This will be the common case,
1411 * when drivers timeout on the last submitted URB and attempt to cancel.
1413 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1414 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1415 * HC will need to invalidate the any TRBs it has cached after the stop
1416 * endpoint command, as noted in the xHCI 0.95 errata.
1418 * 3) The TD may have completed by the time the Stop Endpoint Command
1419 * completes, so software needs to handle that case too.
1421 * This function should protect against the TD enqueueing code ringing the
1422 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1423 * It also needs to account for multiple cancellations on happening at the same
1424 * time for the same endpoint.
1426 * Note that this function can be called in any context, or so says
1427 * usb_hcd_unlink_urb()
1429 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1431 unsigned long flags;
1434 struct xhci_hcd *xhci;
1435 struct urb_priv *urb_priv;
1437 unsigned int ep_index;
1438 struct xhci_ring *ep_ring;
1439 struct xhci_virt_ep *ep;
1440 struct xhci_command *command;
1441 struct xhci_virt_device *vdev;
1443 xhci = hcd_to_xhci(hcd);
1444 spin_lock_irqsave(&xhci->lock, flags);
1446 trace_xhci_urb_dequeue(urb);
1448 /* Make sure the URB hasn't completed or been unlinked already */
1449 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1453 /* give back URB now if we can't queue it for cancel */
1454 vdev = xhci->devs[urb->dev->slot_id];
1455 urb_priv = urb->hcpriv;
1456 if (!vdev || !urb_priv)
1459 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1460 ep = &vdev->eps[ep_index];
1461 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1462 if (!ep || !ep_ring)
1465 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1466 temp = readl(&xhci->op_regs->status);
1467 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1472 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1473 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1474 "HC halted, freeing TD manually.");
1475 for (i = urb_priv->num_tds_done;
1476 i < urb_priv->num_tds;
1478 td = &urb_priv->td[i];
1479 if (!list_empty(&td->td_list))
1480 list_del_init(&td->td_list);
1481 if (!list_empty(&td->cancelled_td_list))
1482 list_del_init(&td->cancelled_td_list);
1487 i = urb_priv->num_tds_done;
1488 if (i < urb_priv->num_tds)
1489 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1490 "Cancel URB %p, dev %s, ep 0x%x, "
1491 "starting at offset 0x%llx",
1492 urb, urb->dev->devpath,
1493 urb->ep->desc.bEndpointAddress,
1494 (unsigned long long) xhci_trb_virt_to_dma(
1495 urb_priv->td[i].start_seg,
1496 urb_priv->td[i].first_trb));
1498 for (; i < urb_priv->num_tds; i++) {
1499 td = &urb_priv->td[i];
1500 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1503 /* Queue a stop endpoint command, but only if this is
1504 * the first cancellation to be handled.
1506 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1507 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1512 ep->ep_state |= EP_STOP_CMD_PENDING;
1513 ep->stop_cmd_timer.expires = jiffies +
1514 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1515 add_timer(&ep->stop_cmd_timer);
1516 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1518 xhci_ring_cmd_db(xhci);
1521 spin_unlock_irqrestore(&xhci->lock, flags);
1526 xhci_urb_free_priv(urb_priv);
1527 usb_hcd_unlink_urb_from_ep(hcd, urb);
1528 spin_unlock_irqrestore(&xhci->lock, flags);
1529 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1533 /* Drop an endpoint from a new bandwidth configuration for this device.
1534 * Only one call to this function is allowed per endpoint before
1535 * check_bandwidth() or reset_bandwidth() must be called.
1536 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1537 * add the endpoint to the schedule with possibly new parameters denoted by a
1538 * different endpoint descriptor in usb_host_endpoint.
1539 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1542 * The USB core will not allow URBs to be queued to an endpoint that is being
1543 * disabled, so there's no need for mutual exclusion to protect
1544 * the xhci->devs[slot_id] structure.
1546 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1547 struct usb_host_endpoint *ep)
1549 struct xhci_hcd *xhci;
1550 struct xhci_container_ctx *in_ctx, *out_ctx;
1551 struct xhci_input_control_ctx *ctrl_ctx;
1552 unsigned int ep_index;
1553 struct xhci_ep_ctx *ep_ctx;
1555 u32 new_add_flags, new_drop_flags;
1558 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1561 xhci = hcd_to_xhci(hcd);
1562 if (xhci->xhc_state & XHCI_STATE_DYING)
1565 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1566 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1567 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1568 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1569 __func__, drop_flag);
1573 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1574 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1575 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1577 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1582 ep_index = xhci_get_endpoint_index(&ep->desc);
1583 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1584 /* If the HC already knows the endpoint is disabled,
1585 * or the HCD has noted it is disabled, ignore this request
1587 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1588 le32_to_cpu(ctrl_ctx->drop_flags) &
1589 xhci_get_endpoint_flag(&ep->desc)) {
1590 /* Do not warn when called after a usb_device_reset */
1591 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1592 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1597 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1598 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1600 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1601 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1603 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1605 if (xhci->quirks & XHCI_MTK_HOST)
1606 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1608 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1609 (unsigned int) ep->desc.bEndpointAddress,
1611 (unsigned int) new_drop_flags,
1612 (unsigned int) new_add_flags);
1616 /* Add an endpoint to a new possible bandwidth configuration for this device.
1617 * Only one call to this function is allowed per endpoint before
1618 * check_bandwidth() or reset_bandwidth() must be called.
1619 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1620 * add the endpoint to the schedule with possibly new parameters denoted by a
1621 * different endpoint descriptor in usb_host_endpoint.
1622 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1625 * The USB core will not allow URBs to be queued to an endpoint until the
1626 * configuration or alt setting is installed in the device, so there's no need
1627 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1629 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1630 struct usb_host_endpoint *ep)
1632 struct xhci_hcd *xhci;
1633 struct xhci_container_ctx *in_ctx;
1634 unsigned int ep_index;
1635 struct xhci_input_control_ctx *ctrl_ctx;
1637 u32 new_add_flags, new_drop_flags;
1638 struct xhci_virt_device *virt_dev;
1641 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1643 /* So we won't queue a reset ep command for a root hub */
1647 xhci = hcd_to_xhci(hcd);
1648 if (xhci->xhc_state & XHCI_STATE_DYING)
1651 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1652 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1653 /* FIXME when we have to issue an evaluate endpoint command to
1654 * deal with ep0 max packet size changing once we get the
1657 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1658 __func__, added_ctxs);
1662 virt_dev = xhci->devs[udev->slot_id];
1663 in_ctx = virt_dev->in_ctx;
1664 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1666 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1671 ep_index = xhci_get_endpoint_index(&ep->desc);
1672 /* If this endpoint is already in use, and the upper layers are trying
1673 * to add it again without dropping it, reject the addition.
1675 if (virt_dev->eps[ep_index].ring &&
1676 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1677 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1678 "without dropping it.\n",
1679 (unsigned int) ep->desc.bEndpointAddress);
1683 /* If the HCD has already noted the endpoint is enabled,
1684 * ignore this request.
1686 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1687 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1693 * Configuration and alternate setting changes must be done in
1694 * process context, not interrupt context (or so documenation
1695 * for usb_set_interface() and usb_set_configuration() claim).
1697 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1698 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1699 __func__, ep->desc.bEndpointAddress);
1703 if (xhci->quirks & XHCI_MTK_HOST) {
1704 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1706 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1707 virt_dev->eps[ep_index].new_ring = NULL;
1712 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1713 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1715 /* If xhci_endpoint_disable() was called for this endpoint, but the
1716 * xHC hasn't been notified yet through the check_bandwidth() call,
1717 * this re-adds a new state for the endpoint from the new endpoint
1718 * descriptors. We must drop and re-add this endpoint, so we leave the
1721 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1723 /* Store the usb_device pointer for later use */
1726 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1727 (unsigned int) ep->desc.bEndpointAddress,
1729 (unsigned int) new_drop_flags,
1730 (unsigned int) new_add_flags);
1734 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1736 struct xhci_input_control_ctx *ctrl_ctx;
1737 struct xhci_ep_ctx *ep_ctx;
1738 struct xhci_slot_ctx *slot_ctx;
1741 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1743 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1748 /* When a device's add flag and drop flag are zero, any subsequent
1749 * configure endpoint command will leave that endpoint's state
1750 * untouched. Make sure we don't leave any old state in the input
1751 * endpoint contexts.
1753 ctrl_ctx->drop_flags = 0;
1754 ctrl_ctx->add_flags = 0;
1755 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1756 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1757 /* Endpoint 0 is always valid */
1758 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1759 for (i = 1; i < 31; i++) {
1760 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1761 ep_ctx->ep_info = 0;
1762 ep_ctx->ep_info2 = 0;
1764 ep_ctx->tx_info = 0;
1768 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1769 struct usb_device *udev, u32 *cmd_status)
1773 switch (*cmd_status) {
1774 case COMP_COMMAND_ABORTED:
1775 case COMP_COMMAND_RING_STOPPED:
1776 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1779 case COMP_RESOURCE_ERROR:
1780 dev_warn(&udev->dev,
1781 "Not enough host controller resources for new device state.\n");
1783 /* FIXME: can we allocate more resources for the HC? */
1785 case COMP_BANDWIDTH_ERROR:
1786 case COMP_SECONDARY_BANDWIDTH_ERROR:
1787 dev_warn(&udev->dev,
1788 "Not enough bandwidth for new device state.\n");
1790 /* FIXME: can we go back to the old state? */
1792 case COMP_TRB_ERROR:
1793 /* the HCD set up something wrong */
1794 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1796 "and endpoint is not disabled.\n");
1799 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1800 dev_warn(&udev->dev,
1801 "ERROR: Incompatible device for endpoint configure command.\n");
1805 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1806 "Successful Endpoint Configure command");
1810 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1818 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1819 struct usb_device *udev, u32 *cmd_status)
1823 switch (*cmd_status) {
1824 case COMP_COMMAND_ABORTED:
1825 case COMP_COMMAND_RING_STOPPED:
1826 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1829 case COMP_PARAMETER_ERROR:
1830 dev_warn(&udev->dev,
1831 "WARN: xHCI driver setup invalid evaluate context command.\n");
1834 case COMP_SLOT_NOT_ENABLED_ERROR:
1835 dev_warn(&udev->dev,
1836 "WARN: slot not enabled for evaluate context command.\n");
1839 case COMP_CONTEXT_STATE_ERROR:
1840 dev_warn(&udev->dev,
1841 "WARN: invalid context state for evaluate context command.\n");
1844 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1845 dev_warn(&udev->dev,
1846 "ERROR: Incompatible device for evaluate context command.\n");
1849 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1850 /* Max Exit Latency too large error */
1851 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1855 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1856 "Successful evaluate context command");
1860 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1868 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1869 struct xhci_input_control_ctx *ctrl_ctx)
1871 u32 valid_add_flags;
1872 u32 valid_drop_flags;
1874 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1875 * (bit 1). The default control endpoint is added during the Address
1876 * Device command and is never removed until the slot is disabled.
1878 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1879 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1881 /* Use hweight32 to count the number of ones in the add flags, or
1882 * number of endpoints added. Don't count endpoints that are changed
1883 * (both added and dropped).
1885 return hweight32(valid_add_flags) -
1886 hweight32(valid_add_flags & valid_drop_flags);
1889 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1890 struct xhci_input_control_ctx *ctrl_ctx)
1892 u32 valid_add_flags;
1893 u32 valid_drop_flags;
1895 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1896 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1898 return hweight32(valid_drop_flags) -
1899 hweight32(valid_add_flags & valid_drop_flags);
1903 * We need to reserve the new number of endpoints before the configure endpoint
1904 * command completes. We can't subtract the dropped endpoints from the number
1905 * of active endpoints until the command completes because we can oversubscribe
1906 * the host in this case:
1908 * - the first configure endpoint command drops more endpoints than it adds
1909 * - a second configure endpoint command that adds more endpoints is queued
1910 * - the first configure endpoint command fails, so the config is unchanged
1911 * - the second command may succeed, even though there isn't enough resources
1913 * Must be called with xhci->lock held.
1915 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1916 struct xhci_input_control_ctx *ctrl_ctx)
1920 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1921 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1922 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1923 "Not enough ep ctxs: "
1924 "%u active, need to add %u, limit is %u.",
1925 xhci->num_active_eps, added_eps,
1926 xhci->limit_active_eps);
1929 xhci->num_active_eps += added_eps;
1930 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1931 "Adding %u ep ctxs, %u now active.", added_eps,
1932 xhci->num_active_eps);
1937 * The configure endpoint was failed by the xHC for some other reason, so we
1938 * need to revert the resources that failed configuration would have used.
1940 * Must be called with xhci->lock held.
1942 static void xhci_free_host_resources(struct xhci_hcd *xhci,
1943 struct xhci_input_control_ctx *ctrl_ctx)
1947 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1948 xhci->num_active_eps -= num_failed_eps;
1949 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1950 "Removing %u failed ep ctxs, %u now active.",
1952 xhci->num_active_eps);
1956 * Now that the command has completed, clean up the active endpoint count by
1957 * subtracting out the endpoints that were dropped (but not changed).
1959 * Must be called with xhci->lock held.
1961 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1962 struct xhci_input_control_ctx *ctrl_ctx)
1964 u32 num_dropped_eps;
1966 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
1967 xhci->num_active_eps -= num_dropped_eps;
1968 if (num_dropped_eps)
1969 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1970 "Removing %u dropped ep ctxs, %u now active.",
1972 xhci->num_active_eps);
1975 static unsigned int xhci_get_block_size(struct usb_device *udev)
1977 switch (udev->speed) {
1979 case USB_SPEED_FULL:
1981 case USB_SPEED_HIGH:
1983 case USB_SPEED_SUPER:
1984 case USB_SPEED_SUPER_PLUS:
1986 case USB_SPEED_UNKNOWN:
1987 case USB_SPEED_WIRELESS:
1989 /* Should never happen */
1995 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
1997 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
1999 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2004 /* If we are changing a LS/FS device under a HS hub,
2005 * make sure (if we are activating a new TT) that the HS bus has enough
2006 * bandwidth for this new TT.
2008 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2009 struct xhci_virt_device *virt_dev,
2012 struct xhci_interval_bw_table *bw_table;
2013 struct xhci_tt_bw_info *tt_info;
2015 /* Find the bandwidth table for the root port this TT is attached to. */
2016 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2017 tt_info = virt_dev->tt_info;
2018 /* If this TT already had active endpoints, the bandwidth for this TT
2019 * has already been added. Removing all periodic endpoints (and thus
2020 * making the TT enactive) will only decrease the bandwidth used.
2024 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2025 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2029 /* Not sure why we would have no new active endpoints...
2031 * Maybe because of an Evaluate Context change for a hub update or a
2032 * control endpoint 0 max packet size change?
2033 * FIXME: skip the bandwidth calculation in that case.
2038 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2039 struct xhci_virt_device *virt_dev)
2041 unsigned int bw_reserved;
2043 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2044 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2047 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2048 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2055 * This algorithm is a very conservative estimate of the worst-case scheduling
2056 * scenario for any one interval. The hardware dynamically schedules the
2057 * packets, so we can't tell which microframe could be the limiting factor in
2058 * the bandwidth scheduling. This only takes into account periodic endpoints.
2060 * Obviously, we can't solve an NP complete problem to find the minimum worst
2061 * case scenario. Instead, we come up with an estimate that is no less than
2062 * the worst case bandwidth used for any one microframe, but may be an
2065 * We walk the requirements for each endpoint by interval, starting with the
2066 * smallest interval, and place packets in the schedule where there is only one
2067 * possible way to schedule packets for that interval. In order to simplify
2068 * this algorithm, we record the largest max packet size for each interval, and
2069 * assume all packets will be that size.
2071 * For interval 0, we obviously must schedule all packets for each interval.
2072 * The bandwidth for interval 0 is just the amount of data to be transmitted
2073 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2074 * the number of packets).
2076 * For interval 1, we have two possible microframes to schedule those packets
2077 * in. For this algorithm, if we can schedule the same number of packets for
2078 * each possible scheduling opportunity (each microframe), we will do so. The
2079 * remaining number of packets will be saved to be transmitted in the gaps in
2080 * the next interval's scheduling sequence.
2082 * As we move those remaining packets to be scheduled with interval 2 packets,
2083 * we have to double the number of remaining packets to transmit. This is
2084 * because the intervals are actually powers of 2, and we would be transmitting
2085 * the previous interval's packets twice in this interval. We also have to be
2086 * sure that when we look at the largest max packet size for this interval, we
2087 * also look at the largest max packet size for the remaining packets and take
2088 * the greater of the two.
2090 * The algorithm continues to evenly distribute packets in each scheduling
2091 * opportunity, and push the remaining packets out, until we get to the last
2092 * interval. Then those packets and their associated overhead are just added
2093 * to the bandwidth used.
2095 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2096 struct xhci_virt_device *virt_dev,
2099 unsigned int bw_reserved;
2100 unsigned int max_bandwidth;
2101 unsigned int bw_used;
2102 unsigned int block_size;
2103 struct xhci_interval_bw_table *bw_table;
2104 unsigned int packet_size = 0;
2105 unsigned int overhead = 0;
2106 unsigned int packets_transmitted = 0;
2107 unsigned int packets_remaining = 0;
2110 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2111 return xhci_check_ss_bw(xhci, virt_dev);
2113 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2114 max_bandwidth = HS_BW_LIMIT;
2115 /* Convert percent of bus BW reserved to blocks reserved */
2116 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2118 max_bandwidth = FS_BW_LIMIT;
2119 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2122 bw_table = virt_dev->bw_table;
2123 /* We need to translate the max packet size and max ESIT payloads into
2124 * the units the hardware uses.
2126 block_size = xhci_get_block_size(virt_dev->udev);
2128 /* If we are manipulating a LS/FS device under a HS hub, double check
2129 * that the HS bus has enough bandwidth if we are activing a new TT.
2131 if (virt_dev->tt_info) {
2132 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2133 "Recalculating BW for rootport %u",
2134 virt_dev->real_port);
2135 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2136 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2137 "newly activated TT.\n");
2140 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2141 "Recalculating BW for TT slot %u port %u",
2142 virt_dev->tt_info->slot_id,
2143 virt_dev->tt_info->ttport);
2145 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2146 "Recalculating BW for rootport %u",
2147 virt_dev->real_port);
2150 /* Add in how much bandwidth will be used for interval zero, or the
2151 * rounded max ESIT payload + number of packets * largest overhead.
2153 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2154 bw_table->interval_bw[0].num_packets *
2155 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2157 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2158 unsigned int bw_added;
2159 unsigned int largest_mps;
2160 unsigned int interval_overhead;
2163 * How many packets could we transmit in this interval?
2164 * If packets didn't fit in the previous interval, we will need
2165 * to transmit that many packets twice within this interval.
2167 packets_remaining = 2 * packets_remaining +
2168 bw_table->interval_bw[i].num_packets;
2170 /* Find the largest max packet size of this or the previous
2173 if (list_empty(&bw_table->interval_bw[i].endpoints))
2176 struct xhci_virt_ep *virt_ep;
2177 struct list_head *ep_entry;
2179 ep_entry = bw_table->interval_bw[i].endpoints.next;
2180 virt_ep = list_entry(ep_entry,
2181 struct xhci_virt_ep, bw_endpoint_list);
2182 /* Convert to blocks, rounding up */
2183 largest_mps = DIV_ROUND_UP(
2184 virt_ep->bw_info.max_packet_size,
2187 if (largest_mps > packet_size)
2188 packet_size = largest_mps;
2190 /* Use the larger overhead of this or the previous interval. */
2191 interval_overhead = xhci_get_largest_overhead(
2192 &bw_table->interval_bw[i]);
2193 if (interval_overhead > overhead)
2194 overhead = interval_overhead;
2196 /* How many packets can we evenly distribute across
2197 * (1 << (i + 1)) possible scheduling opportunities?
2199 packets_transmitted = packets_remaining >> (i + 1);
2201 /* Add in the bandwidth used for those scheduled packets */
2202 bw_added = packets_transmitted * (overhead + packet_size);
2204 /* How many packets do we have remaining to transmit? */
2205 packets_remaining = packets_remaining % (1 << (i + 1));
2207 /* What largest max packet size should those packets have? */
2208 /* If we've transmitted all packets, don't carry over the
2209 * largest packet size.
2211 if (packets_remaining == 0) {
2214 } else if (packets_transmitted > 0) {
2215 /* Otherwise if we do have remaining packets, and we've
2216 * scheduled some packets in this interval, take the
2217 * largest max packet size from endpoints with this
2220 packet_size = largest_mps;
2221 overhead = interval_overhead;
2223 /* Otherwise carry over packet_size and overhead from the last
2224 * time we had a remainder.
2226 bw_used += bw_added;
2227 if (bw_used > max_bandwidth) {
2228 xhci_warn(xhci, "Not enough bandwidth. "
2229 "Proposed: %u, Max: %u\n",
2230 bw_used, max_bandwidth);
2235 * Ok, we know we have some packets left over after even-handedly
2236 * scheduling interval 15. We don't know which microframes they will
2237 * fit into, so we over-schedule and say they will be scheduled every
2240 if (packets_remaining > 0)
2241 bw_used += overhead + packet_size;
2243 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2244 unsigned int port_index = virt_dev->real_port - 1;
2246 /* OK, we're manipulating a HS device attached to a
2247 * root port bandwidth domain. Include the number of active TTs
2248 * in the bandwidth used.
2250 bw_used += TT_HS_OVERHEAD *
2251 xhci->rh_bw[port_index].num_active_tts;
2254 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2255 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2256 "Available: %u " "percent",
2257 bw_used, max_bandwidth, bw_reserved,
2258 (max_bandwidth - bw_used - bw_reserved) * 100 /
2261 bw_used += bw_reserved;
2262 if (bw_used > max_bandwidth) {
2263 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2264 bw_used, max_bandwidth);
2268 bw_table->bw_used = bw_used;
2272 static bool xhci_is_async_ep(unsigned int ep_type)
2274 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2275 ep_type != ISOC_IN_EP &&
2276 ep_type != INT_IN_EP);
2279 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2281 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2284 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2286 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2288 if (ep_bw->ep_interval == 0)
2289 return SS_OVERHEAD_BURST +
2290 (ep_bw->mult * ep_bw->num_packets *
2291 (SS_OVERHEAD + mps));
2292 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2293 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2294 1 << ep_bw->ep_interval);
2298 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2299 struct xhci_bw_info *ep_bw,
2300 struct xhci_interval_bw_table *bw_table,
2301 struct usb_device *udev,
2302 struct xhci_virt_ep *virt_ep,
2303 struct xhci_tt_bw_info *tt_info)
2305 struct xhci_interval_bw *interval_bw;
2306 int normalized_interval;
2308 if (xhci_is_async_ep(ep_bw->type))
2311 if (udev->speed >= USB_SPEED_SUPER) {
2312 if (xhci_is_sync_in_ep(ep_bw->type))
2313 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2314 xhci_get_ss_bw_consumed(ep_bw);
2316 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2317 xhci_get_ss_bw_consumed(ep_bw);
2321 /* SuperSpeed endpoints never get added to intervals in the table, so
2322 * this check is only valid for HS/FS/LS devices.
2324 if (list_empty(&virt_ep->bw_endpoint_list))
2326 /* For LS/FS devices, we need to translate the interval expressed in
2327 * microframes to frames.
2329 if (udev->speed == USB_SPEED_HIGH)
2330 normalized_interval = ep_bw->ep_interval;
2332 normalized_interval = ep_bw->ep_interval - 3;
2334 if (normalized_interval == 0)
2335 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2336 interval_bw = &bw_table->interval_bw[normalized_interval];
2337 interval_bw->num_packets -= ep_bw->num_packets;
2338 switch (udev->speed) {
2340 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2342 case USB_SPEED_FULL:
2343 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2345 case USB_SPEED_HIGH:
2346 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2348 case USB_SPEED_SUPER:
2349 case USB_SPEED_SUPER_PLUS:
2350 case USB_SPEED_UNKNOWN:
2351 case USB_SPEED_WIRELESS:
2352 /* Should never happen because only LS/FS/HS endpoints will get
2353 * added to the endpoint list.
2358 tt_info->active_eps -= 1;
2359 list_del_init(&virt_ep->bw_endpoint_list);
2362 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2363 struct xhci_bw_info *ep_bw,
2364 struct xhci_interval_bw_table *bw_table,
2365 struct usb_device *udev,
2366 struct xhci_virt_ep *virt_ep,
2367 struct xhci_tt_bw_info *tt_info)
2369 struct xhci_interval_bw *interval_bw;
2370 struct xhci_virt_ep *smaller_ep;
2371 int normalized_interval;
2373 if (xhci_is_async_ep(ep_bw->type))
2376 if (udev->speed == USB_SPEED_SUPER) {
2377 if (xhci_is_sync_in_ep(ep_bw->type))
2378 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2379 xhci_get_ss_bw_consumed(ep_bw);
2381 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2382 xhci_get_ss_bw_consumed(ep_bw);
2386 /* For LS/FS devices, we need to translate the interval expressed in
2387 * microframes to frames.
2389 if (udev->speed == USB_SPEED_HIGH)
2390 normalized_interval = ep_bw->ep_interval;
2392 normalized_interval = ep_bw->ep_interval - 3;
2394 if (normalized_interval == 0)
2395 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2396 interval_bw = &bw_table->interval_bw[normalized_interval];
2397 interval_bw->num_packets += ep_bw->num_packets;
2398 switch (udev->speed) {
2400 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2402 case USB_SPEED_FULL:
2403 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2405 case USB_SPEED_HIGH:
2406 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2408 case USB_SPEED_SUPER:
2409 case USB_SPEED_SUPER_PLUS:
2410 case USB_SPEED_UNKNOWN:
2411 case USB_SPEED_WIRELESS:
2412 /* Should never happen because only LS/FS/HS endpoints will get
2413 * added to the endpoint list.
2419 tt_info->active_eps += 1;
2420 /* Insert the endpoint into the list, largest max packet size first. */
2421 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2423 if (ep_bw->max_packet_size >=
2424 smaller_ep->bw_info.max_packet_size) {
2425 /* Add the new ep before the smaller endpoint */
2426 list_add_tail(&virt_ep->bw_endpoint_list,
2427 &smaller_ep->bw_endpoint_list);
2431 /* Add the new endpoint at the end of the list. */
2432 list_add_tail(&virt_ep->bw_endpoint_list,
2433 &interval_bw->endpoints);
2436 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2437 struct xhci_virt_device *virt_dev,
2440 struct xhci_root_port_bw_info *rh_bw_info;
2441 if (!virt_dev->tt_info)
2444 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2445 if (old_active_eps == 0 &&
2446 virt_dev->tt_info->active_eps != 0) {
2447 rh_bw_info->num_active_tts += 1;
2448 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2449 } else if (old_active_eps != 0 &&
2450 virt_dev->tt_info->active_eps == 0) {
2451 rh_bw_info->num_active_tts -= 1;
2452 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2456 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2457 struct xhci_virt_device *virt_dev,
2458 struct xhci_container_ctx *in_ctx)
2460 struct xhci_bw_info ep_bw_info[31];
2462 struct xhci_input_control_ctx *ctrl_ctx;
2463 int old_active_eps = 0;
2465 if (virt_dev->tt_info)
2466 old_active_eps = virt_dev->tt_info->active_eps;
2468 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2470 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2475 for (i = 0; i < 31; i++) {
2476 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2479 /* Make a copy of the BW info in case we need to revert this */
2480 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2481 sizeof(ep_bw_info[i]));
2482 /* Drop the endpoint from the interval table if the endpoint is
2483 * being dropped or changed.
2485 if (EP_IS_DROPPED(ctrl_ctx, i))
2486 xhci_drop_ep_from_interval_table(xhci,
2487 &virt_dev->eps[i].bw_info,
2493 /* Overwrite the information stored in the endpoints' bw_info */
2494 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2495 for (i = 0; i < 31; i++) {
2496 /* Add any changed or added endpoints to the interval table */
2497 if (EP_IS_ADDED(ctrl_ctx, i))
2498 xhci_add_ep_to_interval_table(xhci,
2499 &virt_dev->eps[i].bw_info,
2506 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2507 /* Ok, this fits in the bandwidth we have.
2508 * Update the number of active TTs.
2510 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2514 /* We don't have enough bandwidth for this, revert the stored info. */
2515 for (i = 0; i < 31; i++) {
2516 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2519 /* Drop the new copies of any added or changed endpoints from
2520 * the interval table.
2522 if (EP_IS_ADDED(ctrl_ctx, i)) {
2523 xhci_drop_ep_from_interval_table(xhci,
2524 &virt_dev->eps[i].bw_info,
2530 /* Revert the endpoint back to its old information */
2531 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2532 sizeof(ep_bw_info[i]));
2533 /* Add any changed or dropped endpoints back into the table */
2534 if (EP_IS_DROPPED(ctrl_ctx, i))
2535 xhci_add_ep_to_interval_table(xhci,
2536 &virt_dev->eps[i].bw_info,
2546 /* Issue a configure endpoint command or evaluate context command
2547 * and wait for it to finish.
2549 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2550 struct usb_device *udev,
2551 struct xhci_command *command,
2552 bool ctx_change, bool must_succeed)
2555 unsigned long flags;
2556 struct xhci_input_control_ctx *ctrl_ctx;
2557 struct xhci_virt_device *virt_dev;
2562 spin_lock_irqsave(&xhci->lock, flags);
2564 if (xhci->xhc_state & XHCI_STATE_DYING) {
2565 spin_unlock_irqrestore(&xhci->lock, flags);
2569 virt_dev = xhci->devs[udev->slot_id];
2571 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2573 spin_unlock_irqrestore(&xhci->lock, flags);
2574 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2579 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2580 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2581 spin_unlock_irqrestore(&xhci->lock, flags);
2582 xhci_warn(xhci, "Not enough host resources, "
2583 "active endpoint contexts = %u\n",
2584 xhci->num_active_eps);
2587 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2588 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2589 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2590 xhci_free_host_resources(xhci, ctrl_ctx);
2591 spin_unlock_irqrestore(&xhci->lock, flags);
2592 xhci_warn(xhci, "Not enough bandwidth\n");
2597 ret = xhci_queue_configure_endpoint(xhci, command,
2598 command->in_ctx->dma,
2599 udev->slot_id, must_succeed);
2601 ret = xhci_queue_evaluate_context(xhci, command,
2602 command->in_ctx->dma,
2603 udev->slot_id, must_succeed);
2605 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2606 xhci_free_host_resources(xhci, ctrl_ctx);
2607 spin_unlock_irqrestore(&xhci->lock, flags);
2608 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2609 "FIXME allocate a new ring segment");
2612 xhci_ring_cmd_db(xhci);
2613 spin_unlock_irqrestore(&xhci->lock, flags);
2615 /* Wait for the configure endpoint command to complete */
2616 wait_for_completion(command->completion);
2619 ret = xhci_configure_endpoint_result(xhci, udev,
2622 ret = xhci_evaluate_context_result(xhci, udev,
2625 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2626 spin_lock_irqsave(&xhci->lock, flags);
2627 /* If the command failed, remove the reserved resources.
2628 * Otherwise, clean up the estimate to include dropped eps.
2631 xhci_free_host_resources(xhci, ctrl_ctx);
2633 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2634 spin_unlock_irqrestore(&xhci->lock, flags);
2639 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2640 struct xhci_virt_device *vdev, int i)
2642 struct xhci_virt_ep *ep = &vdev->eps[i];
2644 if (ep->ep_state & EP_HAS_STREAMS) {
2645 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2646 xhci_get_endpoint_address(i));
2647 xhci_free_stream_info(xhci, ep->stream_info);
2648 ep->stream_info = NULL;
2649 ep->ep_state &= ~EP_HAS_STREAMS;
2653 /* Called after one or more calls to xhci_add_endpoint() or
2654 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2655 * to call xhci_reset_bandwidth().
2657 * Since we are in the middle of changing either configuration or
2658 * installing a new alt setting, the USB core won't allow URBs to be
2659 * enqueued for any endpoint on the old config or interface. Nothing
2660 * else should be touching the xhci->devs[slot_id] structure, so we
2661 * don't need to take the xhci->lock for manipulating that.
2663 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2667 struct xhci_hcd *xhci;
2668 struct xhci_virt_device *virt_dev;
2669 struct xhci_input_control_ctx *ctrl_ctx;
2670 struct xhci_slot_ctx *slot_ctx;
2671 struct xhci_command *command;
2673 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2676 xhci = hcd_to_xhci(hcd);
2677 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2678 (xhci->xhc_state & XHCI_STATE_REMOVING))
2681 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2682 virt_dev = xhci->devs[udev->slot_id];
2684 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2688 command->in_ctx = virt_dev->in_ctx;
2690 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2691 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2693 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2696 goto command_cleanup;
2698 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2699 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2700 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2702 /* Don't issue the command if there's no endpoints to update. */
2703 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2704 ctrl_ctx->drop_flags == 0) {
2706 goto command_cleanup;
2708 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2709 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2710 for (i = 31; i >= 1; i--) {
2711 __le32 le32 = cpu_to_le32(BIT(i));
2713 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2714 || (ctrl_ctx->add_flags & le32) || i == 1) {
2715 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2716 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2721 ret = xhci_configure_endpoint(xhci, udev, command,
2724 /* Callee should call reset_bandwidth() */
2725 goto command_cleanup;
2727 /* Free any rings that were dropped, but not changed. */
2728 for (i = 1; i < 31; i++) {
2729 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2730 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2731 xhci_free_endpoint_ring(xhci, virt_dev, i);
2732 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2735 xhci_zero_in_ctx(xhci, virt_dev);
2737 * Install any rings for completely new endpoints or changed endpoints,
2738 * and free any old rings from changed endpoints.
2740 for (i = 1; i < 31; i++) {
2741 if (!virt_dev->eps[i].new_ring)
2743 /* Only free the old ring if it exists.
2744 * It may not if this is the first add of an endpoint.
2746 if (virt_dev->eps[i].ring) {
2747 xhci_free_endpoint_ring(xhci, virt_dev, i);
2749 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2750 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2751 virt_dev->eps[i].new_ring = NULL;
2754 kfree(command->completion);
2760 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2762 struct xhci_hcd *xhci;
2763 struct xhci_virt_device *virt_dev;
2766 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2769 xhci = hcd_to_xhci(hcd);
2771 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2772 virt_dev = xhci->devs[udev->slot_id];
2773 /* Free any rings allocated for added endpoints */
2774 for (i = 0; i < 31; i++) {
2775 if (virt_dev->eps[i].new_ring) {
2776 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2777 virt_dev->eps[i].new_ring = NULL;
2780 xhci_zero_in_ctx(xhci, virt_dev);
2783 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2784 struct xhci_container_ctx *in_ctx,
2785 struct xhci_container_ctx *out_ctx,
2786 struct xhci_input_control_ctx *ctrl_ctx,
2787 u32 add_flags, u32 drop_flags)
2789 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2790 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2791 xhci_slot_copy(xhci, in_ctx, out_ctx);
2792 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2795 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2796 unsigned int slot_id, unsigned int ep_index,
2797 struct xhci_dequeue_state *deq_state)
2799 struct xhci_input_control_ctx *ctrl_ctx;
2800 struct xhci_container_ctx *in_ctx;
2801 struct xhci_ep_ctx *ep_ctx;
2805 in_ctx = xhci->devs[slot_id]->in_ctx;
2806 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2808 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2813 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2814 xhci->devs[slot_id]->out_ctx, ep_index);
2815 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2816 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2817 deq_state->new_deq_ptr);
2819 xhci_warn(xhci, "WARN Cannot submit config ep after "
2820 "reset ep command\n");
2821 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2822 deq_state->new_deq_seg,
2823 deq_state->new_deq_ptr);
2826 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2828 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2829 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2830 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2831 added_ctxs, added_ctxs);
2834 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2835 unsigned int stream_id, struct xhci_td *td)
2837 struct xhci_dequeue_state deq_state;
2838 struct xhci_virt_ep *ep;
2839 struct usb_device *udev = td->urb->dev;
2841 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2842 "Cleaning up stalled endpoint ring");
2843 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2844 /* We need to move the HW's dequeue pointer past this TD,
2845 * or it will attempt to resend it on the next doorbell ring.
2847 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2848 ep_index, stream_id, td, &deq_state);
2850 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2853 /* HW with the reset endpoint quirk will use the saved dequeue state to
2854 * issue a configure endpoint command later.
2856 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2857 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2858 "Queueing new dequeue state");
2859 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2860 ep_index, &deq_state);
2862 /* Better hope no one uses the input context between now and the
2863 * reset endpoint completion!
2864 * XXX: No idea how this hardware will react when stream rings
2867 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2868 "Setting up input context for "
2869 "configure endpoint command");
2870 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2871 ep_index, &deq_state);
2875 /* Called when clearing halted device. The core should have sent the control
2876 * message to clear the device halt condition. The host side of the halt should
2877 * already be cleared with a reset endpoint command issued when the STALL tx
2878 * event was received.
2880 * Context: in_interrupt
2883 static void xhci_endpoint_reset(struct usb_hcd *hcd,
2884 struct usb_host_endpoint *ep)
2886 struct xhci_hcd *xhci;
2888 xhci = hcd_to_xhci(hcd);
2891 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2892 * The Reset Endpoint Command may only be issued to endpoints in the
2893 * Halted state. If software wishes reset the Data Toggle or Sequence
2894 * Number of an endpoint that isn't in the Halted state, then software
2895 * may issue a Configure Endpoint Command with the Drop and Add bits set
2896 * for the target endpoint. that is in the Stopped state.
2899 /* For now just print debug to follow the situation */
2900 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2901 ep->desc.bEndpointAddress);
2904 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2905 struct usb_device *udev, struct usb_host_endpoint *ep,
2906 unsigned int slot_id)
2909 unsigned int ep_index;
2910 unsigned int ep_state;
2914 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2917 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2918 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2919 " descriptor for ep 0x%x does not support streams\n",
2920 ep->desc.bEndpointAddress);
2924 ep_index = xhci_get_endpoint_index(&ep->desc);
2925 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2926 if (ep_state & EP_HAS_STREAMS ||
2927 ep_state & EP_GETTING_STREAMS) {
2928 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2929 "already has streams set up.\n",
2930 ep->desc.bEndpointAddress);
2931 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2932 "dynamic stream context array reallocation.\n");
2935 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2936 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2937 "endpoint 0x%x; URBs are pending.\n",
2938 ep->desc.bEndpointAddress);
2944 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2945 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2947 unsigned int max_streams;
2949 /* The stream context array size must be a power of two */
2950 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2952 * Find out how many primary stream array entries the host controller
2953 * supports. Later we may use secondary stream arrays (similar to 2nd
2954 * level page entries), but that's an optional feature for xHCI host
2955 * controllers. xHCs must support at least 4 stream IDs.
2957 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2958 if (*num_stream_ctxs > max_streams) {
2959 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2961 *num_stream_ctxs = max_streams;
2962 *num_streams = max_streams;
2966 /* Returns an error code if one of the endpoint already has streams.
2967 * This does not change any data structures, it only checks and gathers
2970 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2971 struct usb_device *udev,
2972 struct usb_host_endpoint **eps, unsigned int num_eps,
2973 unsigned int *num_streams, u32 *changed_ep_bitmask)
2975 unsigned int max_streams;
2976 unsigned int endpoint_flag;
2980 for (i = 0; i < num_eps; i++) {
2981 ret = xhci_check_streams_endpoint(xhci, udev,
2982 eps[i], udev->slot_id);
2986 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
2987 if (max_streams < (*num_streams - 1)) {
2988 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2989 eps[i]->desc.bEndpointAddress,
2991 *num_streams = max_streams+1;
2994 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2995 if (*changed_ep_bitmask & endpoint_flag)
2997 *changed_ep_bitmask |= endpoint_flag;
3002 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3003 struct usb_device *udev,
3004 struct usb_host_endpoint **eps, unsigned int num_eps)
3006 u32 changed_ep_bitmask = 0;
3007 unsigned int slot_id;
3008 unsigned int ep_index;
3009 unsigned int ep_state;
3012 slot_id = udev->slot_id;
3013 if (!xhci->devs[slot_id])
3016 for (i = 0; i < num_eps; i++) {
3017 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3018 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3019 /* Are streams already being freed for the endpoint? */
3020 if (ep_state & EP_GETTING_NO_STREAMS) {
3021 xhci_warn(xhci, "WARN Can't disable streams for "
3023 "streams are being disabled already\n",
3024 eps[i]->desc.bEndpointAddress);
3027 /* Are there actually any streams to free? */
3028 if (!(ep_state & EP_HAS_STREAMS) &&
3029 !(ep_state & EP_GETTING_STREAMS)) {
3030 xhci_warn(xhci, "WARN Can't disable streams for "
3032 "streams are already disabled!\n",
3033 eps[i]->desc.bEndpointAddress);
3034 xhci_warn(xhci, "WARN xhci_free_streams() called "
3035 "with non-streams endpoint\n");
3038 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3040 return changed_ep_bitmask;
3044 * The USB device drivers use this function (through the HCD interface in USB
3045 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3046 * coordinate mass storage command queueing across multiple endpoints (basically
3047 * a stream ID == a task ID).
3049 * Setting up streams involves allocating the same size stream context array
3050 * for each endpoint and issuing a configure endpoint command for all endpoints.
3052 * Don't allow the call to succeed if one endpoint only supports one stream
3053 * (which means it doesn't support streams at all).
3055 * Drivers may get less stream IDs than they asked for, if the host controller
3056 * hardware or endpoints claim they can't support the number of requested
3059 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3060 struct usb_host_endpoint **eps, unsigned int num_eps,
3061 unsigned int num_streams, gfp_t mem_flags)
3064 struct xhci_hcd *xhci;
3065 struct xhci_virt_device *vdev;
3066 struct xhci_command *config_cmd;
3067 struct xhci_input_control_ctx *ctrl_ctx;
3068 unsigned int ep_index;
3069 unsigned int num_stream_ctxs;
3070 unsigned int max_packet;
3071 unsigned long flags;
3072 u32 changed_ep_bitmask = 0;
3077 /* Add one to the number of streams requested to account for
3078 * stream 0 that is reserved for xHCI usage.
3081 xhci = hcd_to_xhci(hcd);
3082 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3085 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3086 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3087 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3088 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3092 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3096 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3098 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3100 xhci_free_command(xhci, config_cmd);
3104 /* Check to make sure all endpoints are not already configured for
3105 * streams. While we're at it, find the maximum number of streams that
3106 * all the endpoints will support and check for duplicate endpoints.
3108 spin_lock_irqsave(&xhci->lock, flags);
3109 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3110 num_eps, &num_streams, &changed_ep_bitmask);
3112 xhci_free_command(xhci, config_cmd);
3113 spin_unlock_irqrestore(&xhci->lock, flags);
3116 if (num_streams <= 1) {
3117 xhci_warn(xhci, "WARN: endpoints can't handle "
3118 "more than one stream.\n");
3119 xhci_free_command(xhci, config_cmd);
3120 spin_unlock_irqrestore(&xhci->lock, flags);
3123 vdev = xhci->devs[udev->slot_id];
3124 /* Mark each endpoint as being in transition, so
3125 * xhci_urb_enqueue() will reject all URBs.
3127 for (i = 0; i < num_eps; i++) {
3128 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3129 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3131 spin_unlock_irqrestore(&xhci->lock, flags);
3133 /* Setup internal data structures and allocate HW data structures for
3134 * streams (but don't install the HW structures in the input context
3135 * until we're sure all memory allocation succeeded).
3137 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3138 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3139 num_stream_ctxs, num_streams);
3141 for (i = 0; i < num_eps; i++) {
3142 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3143 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3144 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3147 max_packet, mem_flags);
3148 if (!vdev->eps[ep_index].stream_info)
3150 /* Set maxPstreams in endpoint context and update deq ptr to
3151 * point to stream context array. FIXME
3155 /* Set up the input context for a configure endpoint command. */
3156 for (i = 0; i < num_eps; i++) {
3157 struct xhci_ep_ctx *ep_ctx;
3159 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3160 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3162 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3163 vdev->out_ctx, ep_index);
3164 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3165 vdev->eps[ep_index].stream_info);
3167 /* Tell the HW to drop its old copy of the endpoint context info
3168 * and add the updated copy from the input context.
3170 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3171 vdev->out_ctx, ctrl_ctx,
3172 changed_ep_bitmask, changed_ep_bitmask);
3174 /* Issue and wait for the configure endpoint command */
3175 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3178 /* xHC rejected the configure endpoint command for some reason, so we
3179 * leave the old ring intact and free our internal streams data
3185 spin_lock_irqsave(&xhci->lock, flags);
3186 for (i = 0; i < num_eps; i++) {
3187 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3188 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3189 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3190 udev->slot_id, ep_index);
3191 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3193 xhci_free_command(xhci, config_cmd);
3194 spin_unlock_irqrestore(&xhci->lock, flags);
3196 /* Subtract 1 for stream 0, which drivers can't use */
3197 return num_streams - 1;
3200 /* If it didn't work, free the streams! */
3201 for (i = 0; i < num_eps; i++) {
3202 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3203 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3204 vdev->eps[ep_index].stream_info = NULL;
3205 /* FIXME Unset maxPstreams in endpoint context and
3206 * update deq ptr to point to normal string ring.
3208 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3209 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3210 xhci_endpoint_zero(xhci, vdev, eps[i]);
3212 xhci_free_command(xhci, config_cmd);
3216 /* Transition the endpoint from using streams to being a "normal" endpoint
3219 * Modify the endpoint context state, submit a configure endpoint command,
3220 * and free all endpoint rings for streams if that completes successfully.
3222 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3223 struct usb_host_endpoint **eps, unsigned int num_eps,
3227 struct xhci_hcd *xhci;
3228 struct xhci_virt_device *vdev;
3229 struct xhci_command *command;
3230 struct xhci_input_control_ctx *ctrl_ctx;
3231 unsigned int ep_index;
3232 unsigned long flags;
3233 u32 changed_ep_bitmask;
3235 xhci = hcd_to_xhci(hcd);
3236 vdev = xhci->devs[udev->slot_id];
3238 /* Set up a configure endpoint command to remove the streams rings */
3239 spin_lock_irqsave(&xhci->lock, flags);
3240 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3241 udev, eps, num_eps);
3242 if (changed_ep_bitmask == 0) {
3243 spin_unlock_irqrestore(&xhci->lock, flags);
3247 /* Use the xhci_command structure from the first endpoint. We may have
3248 * allocated too many, but the driver may call xhci_free_streams() for
3249 * each endpoint it grouped into one call to xhci_alloc_streams().
3251 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3252 command = vdev->eps[ep_index].stream_info->free_streams_command;
3253 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3255 spin_unlock_irqrestore(&xhci->lock, flags);
3256 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3261 for (i = 0; i < num_eps; i++) {
3262 struct xhci_ep_ctx *ep_ctx;
3264 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3265 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3266 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3267 EP_GETTING_NO_STREAMS;
3269 xhci_endpoint_copy(xhci, command->in_ctx,
3270 vdev->out_ctx, ep_index);
3271 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3272 &vdev->eps[ep_index]);
3274 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3275 vdev->out_ctx, ctrl_ctx,
3276 changed_ep_bitmask, changed_ep_bitmask);
3277 spin_unlock_irqrestore(&xhci->lock, flags);
3279 /* Issue and wait for the configure endpoint command,
3280 * which must succeed.
3282 ret = xhci_configure_endpoint(xhci, udev, command,
3285 /* xHC rejected the configure endpoint command for some reason, so we
3286 * leave the streams rings intact.
3291 spin_lock_irqsave(&xhci->lock, flags);
3292 for (i = 0; i < num_eps; i++) {
3293 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3294 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3295 vdev->eps[ep_index].stream_info = NULL;
3296 /* FIXME Unset maxPstreams in endpoint context and
3297 * update deq ptr to point to normal string ring.
3299 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3300 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3302 spin_unlock_irqrestore(&xhci->lock, flags);
3308 * Deletes endpoint resources for endpoints that were active before a Reset
3309 * Device command, or a Disable Slot command. The Reset Device command leaves
3310 * the control endpoint intact, whereas the Disable Slot command deletes it.
3312 * Must be called with xhci->lock held.
3314 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3315 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3318 unsigned int num_dropped_eps = 0;
3319 unsigned int drop_flags = 0;
3321 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3322 if (virt_dev->eps[i].ring) {
3323 drop_flags |= 1 << i;
3327 xhci->num_active_eps -= num_dropped_eps;
3328 if (num_dropped_eps)
3329 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3330 "Dropped %u ep ctxs, flags = 0x%x, "
3332 num_dropped_eps, drop_flags,
3333 xhci->num_active_eps);
3337 * This submits a Reset Device Command, which will set the device state to 0,
3338 * set the device address to 0, and disable all the endpoints except the default
3339 * control endpoint. The USB core should come back and call
3340 * xhci_address_device(), and then re-set up the configuration. If this is
3341 * called because of a usb_reset_and_verify_device(), then the old alternate
3342 * settings will be re-installed through the normal bandwidth allocation
3345 * Wait for the Reset Device command to finish. Remove all structures
3346 * associated with the endpoints that were disabled. Clear the input device
3347 * structure? Reset the control endpoint 0 max packet size?
3349 * If the virt_dev to be reset does not exist or does not match the udev,
3350 * it means the device is lost, possibly due to the xHC restore error and
3351 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3352 * re-allocate the device.
3354 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3355 struct usb_device *udev)
3358 unsigned long flags;
3359 struct xhci_hcd *xhci;
3360 unsigned int slot_id;
3361 struct xhci_virt_device *virt_dev;
3362 struct xhci_command *reset_device_cmd;
3363 int last_freed_endpoint;
3364 struct xhci_slot_ctx *slot_ctx;
3365 int old_active_eps = 0;
3367 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3370 xhci = hcd_to_xhci(hcd);
3371 slot_id = udev->slot_id;
3372 virt_dev = xhci->devs[slot_id];
3374 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3375 "not exist. Re-allocate the device\n", slot_id);
3376 ret = xhci_alloc_dev(hcd, udev);
3383 if (virt_dev->tt_info)
3384 old_active_eps = virt_dev->tt_info->active_eps;
3386 if (virt_dev->udev != udev) {
3387 /* If the virt_dev and the udev does not match, this virt_dev
3388 * may belong to another udev.
3389 * Re-allocate the device.
3391 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3392 "not match the udev. Re-allocate the device\n",
3394 ret = xhci_alloc_dev(hcd, udev);
3401 /* If device is not setup, there is no point in resetting it */
3402 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3403 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3404 SLOT_STATE_DISABLED)
3407 trace_xhci_discover_or_reset_device(slot_ctx);
3409 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3410 /* Allocate the command structure that holds the struct completion.
3411 * Assume we're in process context, since the normal device reset
3412 * process has to wait for the device anyway. Storage devices are
3413 * reset as part of error handling, so use GFP_NOIO instead of
3416 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3417 if (!reset_device_cmd) {
3418 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3422 /* Attempt to submit the Reset Device command to the command ring */
3423 spin_lock_irqsave(&xhci->lock, flags);
3425 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3427 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3428 spin_unlock_irqrestore(&xhci->lock, flags);
3429 goto command_cleanup;
3431 xhci_ring_cmd_db(xhci);
3432 spin_unlock_irqrestore(&xhci->lock, flags);
3434 /* Wait for the Reset Device command to finish */
3435 wait_for_completion(reset_device_cmd->completion);
3437 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3438 * unless we tried to reset a slot ID that wasn't enabled,
3439 * or the device wasn't in the addressed or configured state.
3441 ret = reset_device_cmd->status;
3443 case COMP_COMMAND_ABORTED:
3444 case COMP_COMMAND_RING_STOPPED:
3445 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3447 goto command_cleanup;
3448 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3449 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3450 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3452 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3453 xhci_dbg(xhci, "Not freeing device rings.\n");
3454 /* Don't treat this as an error. May change my mind later. */
3456 goto command_cleanup;
3458 xhci_dbg(xhci, "Successful reset device command.\n");
3461 if (xhci_is_vendor_info_code(xhci, ret))
3463 xhci_warn(xhci, "Unknown completion code %u for "
3464 "reset device command.\n", ret);
3466 goto command_cleanup;
3469 /* Free up host controller endpoint resources */
3470 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3471 spin_lock_irqsave(&xhci->lock, flags);
3472 /* Don't delete the default control endpoint resources */
3473 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3474 spin_unlock_irqrestore(&xhci->lock, flags);
3477 /* Everything but endpoint 0 is disabled, so free the rings. */
3478 last_freed_endpoint = 1;
3479 for (i = 1; i < 31; i++) {
3480 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3482 if (ep->ep_state & EP_HAS_STREAMS) {
3483 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3484 xhci_get_endpoint_address(i));
3485 xhci_free_stream_info(xhci, ep->stream_info);
3486 ep->stream_info = NULL;
3487 ep->ep_state &= ~EP_HAS_STREAMS;
3491 xhci_free_endpoint_ring(xhci, virt_dev, i);
3492 last_freed_endpoint = i;
3494 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3495 xhci_drop_ep_from_interval_table(xhci,
3496 &virt_dev->eps[i].bw_info,
3501 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3503 /* If necessary, update the number of active TTs on this root port */
3504 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3508 xhci_free_command(xhci, reset_device_cmd);
3513 * At this point, the struct usb_device is about to go away, the device has
3514 * disconnected, and all traffic has been stopped and the endpoints have been
3515 * disabled. Free any HC data structures associated with that device.
3517 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3519 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3520 struct xhci_virt_device *virt_dev;
3521 struct xhci_slot_ctx *slot_ctx;
3523 struct xhci_command *command;
3525 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3529 #ifndef CONFIG_USB_DEFAULT_PERSIST
3531 * We called pm_runtime_get_noresume when the device was attached.
3532 * Decrement the counter here to allow controller to runtime suspend
3533 * if no devices remain.
3535 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3536 pm_runtime_put_noidle(hcd->self.controller);
3539 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3540 /* If the host is halted due to driver unload, we still need to free the
3543 if (ret <= 0 && ret != -ENODEV) {
3548 virt_dev = xhci->devs[udev->slot_id];
3549 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3550 trace_xhci_free_dev(slot_ctx);
3552 /* Stop any wayward timer functions (which may grab the lock) */
3553 for (i = 0; i < 31; i++) {
3554 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3555 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3558 xhci_disable_slot(xhci, command, udev->slot_id);
3560 * Event command completion handler will free any data structures
3561 * associated with the slot. XXX Can free sleep?
3565 int xhci_disable_slot(struct xhci_hcd *xhci, struct xhci_command *command,
3568 unsigned long flags;
3571 struct xhci_virt_device *virt_dev;
3573 virt_dev = xhci->devs[slot_id];
3577 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3581 spin_lock_irqsave(&xhci->lock, flags);
3582 /* Don't disable the slot if the host controller is dead. */
3583 state = readl(&xhci->op_regs->status);
3584 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3585 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3586 xhci_free_virt_device(xhci, slot_id);
3587 spin_unlock_irqrestore(&xhci->lock, flags);
3592 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3595 spin_unlock_irqrestore(&xhci->lock, flags);
3596 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3599 xhci_ring_cmd_db(xhci);
3600 spin_unlock_irqrestore(&xhci->lock, flags);
3605 * Checks if we have enough host controller resources for the default control
3608 * Must be called with xhci->lock held.
3610 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3612 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3613 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3614 "Not enough ep ctxs: "
3615 "%u active, need to add 1, limit is %u.",
3616 xhci->num_active_eps, xhci->limit_active_eps);
3619 xhci->num_active_eps += 1;
3620 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3621 "Adding 1 ep ctx, %u now active.",
3622 xhci->num_active_eps);
3628 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3629 * timed out, or allocating memory failed. Returns 1 on success.
3631 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3633 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3634 struct xhci_virt_device *vdev;
3635 struct xhci_slot_ctx *slot_ctx;
3636 unsigned long flags;
3638 struct xhci_command *command;
3640 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3644 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3645 mutex_lock(&xhci->mutex);
3646 spin_lock_irqsave(&xhci->lock, flags);
3647 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3649 spin_unlock_irqrestore(&xhci->lock, flags);
3650 mutex_unlock(&xhci->mutex);
3651 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3652 xhci_free_command(xhci, command);
3655 xhci_ring_cmd_db(xhci);
3656 spin_unlock_irqrestore(&xhci->lock, flags);
3658 wait_for_completion(command->completion);
3659 slot_id = command->slot_id;
3660 mutex_unlock(&xhci->mutex);
3662 if (!slot_id || command->status != COMP_SUCCESS) {
3663 xhci_err(xhci, "Error while assigning device slot ID\n");
3664 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3666 readl(&xhci->cap_regs->hcs_params1)));
3667 xhci_free_command(xhci, command);
3671 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3672 spin_lock_irqsave(&xhci->lock, flags);
3673 ret = xhci_reserve_host_control_ep_resources(xhci);
3675 spin_unlock_irqrestore(&xhci->lock, flags);
3676 xhci_warn(xhci, "Not enough host resources, "
3677 "active endpoint contexts = %u\n",
3678 xhci->num_active_eps);
3681 spin_unlock_irqrestore(&xhci->lock, flags);
3683 /* Use GFP_NOIO, since this function can be called from
3684 * xhci_discover_or_reset_device(), which may be called as part of
3685 * mass storage driver error handling.
3687 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3688 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3691 vdev = xhci->devs[slot_id];
3692 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3693 trace_xhci_alloc_dev(slot_ctx);
3695 udev->slot_id = slot_id;
3697 #ifndef CONFIG_USB_DEFAULT_PERSIST
3699 * If resetting upon resume, we can't put the controller into runtime
3700 * suspend if there is a device attached.
3702 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3703 pm_runtime_get_noresume(hcd->self.controller);
3707 xhci_free_command(xhci, command);
3708 /* Is this a LS or FS device under a HS hub? */
3709 /* Hub or peripherial? */
3713 /* Disable slot, if we can do it without mem alloc */
3714 kfree(command->completion);
3715 command->completion = NULL;
3716 command->status = 0;
3717 return xhci_disable_slot(xhci, command, udev->slot_id);
3721 * Issue an Address Device command and optionally send a corresponding
3722 * SetAddress request to the device.
3724 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3725 enum xhci_setup_dev setup)
3727 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3728 unsigned long flags;
3729 struct xhci_virt_device *virt_dev;
3731 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3732 struct xhci_slot_ctx *slot_ctx;
3733 struct xhci_input_control_ctx *ctrl_ctx;
3735 struct xhci_command *command = NULL;
3737 mutex_lock(&xhci->mutex);
3739 if (xhci->xhc_state) { /* dying, removing or halted */
3744 if (!udev->slot_id) {
3745 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3746 "Bad Slot ID %d", udev->slot_id);
3751 virt_dev = xhci->devs[udev->slot_id];
3753 if (WARN_ON(!virt_dev)) {
3755 * In plug/unplug torture test with an NEC controller,
3756 * a zero-dereference was observed once due to virt_dev = 0.
3757 * Print useful debug rather than crash if it is observed again!
3759 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3764 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3765 trace_xhci_setup_device_slot(slot_ctx);
3767 if (setup == SETUP_CONTEXT_ONLY) {
3768 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3769 SLOT_STATE_DEFAULT) {
3770 xhci_dbg(xhci, "Slot already in default state\n");
3775 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3781 command->in_ctx = virt_dev->in_ctx;
3783 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3784 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3786 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3792 * If this is the first Set Address since device plug-in or
3793 * virt_device realloaction after a resume with an xHCI power loss,
3794 * then set up the slot context.
3796 if (!slot_ctx->dev_info)
3797 xhci_setup_addressable_virt_dev(xhci, udev);
3798 /* Otherwise, update the control endpoint ring enqueue pointer. */
3800 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3801 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3802 ctrl_ctx->drop_flags = 0;
3804 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3805 le32_to_cpu(slot_ctx->dev_info) >> 27);
3807 spin_lock_irqsave(&xhci->lock, flags);
3808 trace_xhci_setup_device(virt_dev);
3809 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3810 udev->slot_id, setup);
3812 spin_unlock_irqrestore(&xhci->lock, flags);
3813 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3814 "FIXME: allocate a command ring segment");
3817 xhci_ring_cmd_db(xhci);
3818 spin_unlock_irqrestore(&xhci->lock, flags);
3820 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3821 wait_for_completion(command->completion);
3823 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3824 * the SetAddress() "recovery interval" required by USB and aborting the
3825 * command on a timeout.
3827 switch (command->status) {
3828 case COMP_COMMAND_ABORTED:
3829 case COMP_COMMAND_RING_STOPPED:
3830 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3833 case COMP_CONTEXT_STATE_ERROR:
3834 case COMP_SLOT_NOT_ENABLED_ERROR:
3835 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3836 act, udev->slot_id);
3839 case COMP_USB_TRANSACTION_ERROR:
3840 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3843 case COMP_INCOMPATIBLE_DEVICE_ERROR:
3844 dev_warn(&udev->dev,
3845 "ERROR: Incompatible device for setup %s command\n", act);
3849 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3850 "Successful setup %s command", act);
3854 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3855 act, command->status);
3856 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3862 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3863 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3864 "Op regs DCBAA ptr = %#016llx", temp_64);
3865 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3866 "Slot ID %d dcbaa entry @%p = %#016llx",
3868 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3869 (unsigned long long)
3870 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3871 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3872 "Output Context DMA address = %#08llx",
3873 (unsigned long long)virt_dev->out_ctx->dma);
3874 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3875 le32_to_cpu(slot_ctx->dev_info) >> 27);
3877 * USB core uses address 1 for the roothubs, so we add one to the
3878 * address given back to us by the HC.
3880 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3881 le32_to_cpu(slot_ctx->dev_info) >> 27);
3882 /* Zero the input context control for later use */
3883 ctrl_ctx->add_flags = 0;
3884 ctrl_ctx->drop_flags = 0;
3886 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3887 "Internal device address = %d",
3888 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3890 mutex_unlock(&xhci->mutex);
3892 kfree(command->completion);
3898 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3900 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3903 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3905 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3909 * Transfer the port index into real index in the HW port status
3910 * registers. Caculate offset between the port's PORTSC register
3911 * and port status base. Divide the number of per port register
3912 * to get the real index. The raw port number bases 1.
3914 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3916 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3917 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3918 __le32 __iomem *addr;
3921 if (hcd->speed < HCD_USB3)
3922 addr = xhci->usb2_ports[port1 - 1];
3924 addr = xhci->usb3_ports[port1 - 1];
3926 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3931 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3932 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3934 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3935 struct usb_device *udev, u16 max_exit_latency)
3937 struct xhci_virt_device *virt_dev;
3938 struct xhci_command *command;
3939 struct xhci_input_control_ctx *ctrl_ctx;
3940 struct xhci_slot_ctx *slot_ctx;
3941 unsigned long flags;
3944 spin_lock_irqsave(&xhci->lock, flags);
3946 virt_dev = xhci->devs[udev->slot_id];
3949 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3950 * xHC was re-initialized. Exit latency will be set later after
3951 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3954 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
3955 spin_unlock_irqrestore(&xhci->lock, flags);
3959 /* Attempt to issue an Evaluate Context command to change the MEL. */
3960 command = xhci->lpm_command;
3961 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3963 spin_unlock_irqrestore(&xhci->lock, flags);
3964 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3969 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
3970 spin_unlock_irqrestore(&xhci->lock, flags);
3972 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3973 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3974 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
3975 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
3976 slot_ctx->dev_state = 0;
3978 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
3979 "Set up evaluate context for LPM MEL change.");
3981 /* Issue and wait for the evaluate context command. */
3982 ret = xhci_configure_endpoint(xhci, udev, command,
3986 spin_lock_irqsave(&xhci->lock, flags);
3987 virt_dev->current_mel = max_exit_latency;
3988 spin_unlock_irqrestore(&xhci->lock, flags);
3995 /* BESL to HIRD Encoding array for USB2 LPM */
3996 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3997 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3999 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4000 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4001 struct usb_device *udev)
4003 int u2del, besl, besl_host;
4004 int besl_device = 0;
4007 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4008 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4010 if (field & USB_BESL_SUPPORT) {
4011 for (besl_host = 0; besl_host < 16; besl_host++) {
4012 if (xhci_besl_encoding[besl_host] >= u2del)
4015 /* Use baseline BESL value as default */
4016 if (field & USB_BESL_BASELINE_VALID)
4017 besl_device = USB_GET_BESL_BASELINE(field);
4018 else if (field & USB_BESL_DEEP_VALID)
4019 besl_device = USB_GET_BESL_DEEP(field);
4024 besl_host = (u2del - 51) / 75 + 1;
4027 besl = besl_host + besl_device;
4034 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4035 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4042 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4044 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4045 l1 = udev->l1_params.timeout / 256;
4047 /* device has preferred BESLD */
4048 if (field & USB_BESL_DEEP_VALID) {
4049 besld = USB_GET_BESL_DEEP(field);
4053 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4056 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4057 struct usb_device *udev, int enable)
4059 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4060 __le32 __iomem **port_array;
4061 __le32 __iomem *pm_addr, *hlpm_addr;
4062 u32 pm_val, hlpm_val, field;
4063 unsigned int port_num;
4064 unsigned long flags;
4065 int hird, exit_latency;
4068 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4072 if (!udev->parent || udev->parent->parent ||
4073 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4076 if (udev->usb2_hw_lpm_capable != 1)
4079 spin_lock_irqsave(&xhci->lock, flags);
4081 port_array = xhci->usb2_ports;
4082 port_num = udev->portnum - 1;
4083 pm_addr = port_array[port_num] + PORTPMSC;
4084 pm_val = readl(pm_addr);
4085 hlpm_addr = port_array[port_num] + PORTHLPMC;
4086 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4088 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4089 enable ? "enable" : "disable", port_num + 1);
4092 /* Host supports BESL timeout instead of HIRD */
4093 if (udev->usb2_hw_lpm_besl_capable) {
4094 /* if device doesn't have a preferred BESL value use a
4095 * default one which works with mixed HIRD and BESL
4096 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4098 if ((field & USB_BESL_SUPPORT) &&
4099 (field & USB_BESL_BASELINE_VALID))
4100 hird = USB_GET_BESL_BASELINE(field);
4102 hird = udev->l1_params.besl;
4104 exit_latency = xhci_besl_encoding[hird];
4105 spin_unlock_irqrestore(&xhci->lock, flags);
4107 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4108 * input context for link powermanagement evaluate
4109 * context commands. It is protected by hcd->bandwidth
4110 * mutex and is shared by all devices. We need to set
4111 * the max ext latency in USB 2 BESL LPM as well, so
4112 * use the same mutex and xhci_change_max_exit_latency()
4114 mutex_lock(hcd->bandwidth_mutex);
4115 ret = xhci_change_max_exit_latency(xhci, udev,
4117 mutex_unlock(hcd->bandwidth_mutex);
4121 spin_lock_irqsave(&xhci->lock, flags);
4123 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4124 writel(hlpm_val, hlpm_addr);
4128 hird = xhci_calculate_hird_besl(xhci, udev);
4131 pm_val &= ~PORT_HIRD_MASK;
4132 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4133 writel(pm_val, pm_addr);
4134 pm_val = readl(pm_addr);
4136 writel(pm_val, pm_addr);
4140 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4141 writel(pm_val, pm_addr);
4144 if (udev->usb2_hw_lpm_besl_capable) {
4145 spin_unlock_irqrestore(&xhci->lock, flags);
4146 mutex_lock(hcd->bandwidth_mutex);
4147 xhci_change_max_exit_latency(xhci, udev, 0);
4148 mutex_unlock(hcd->bandwidth_mutex);
4153 spin_unlock_irqrestore(&xhci->lock, flags);
4157 /* check if a usb2 port supports a given extened capability protocol
4158 * only USB2 ports extended protocol capability values are cached.
4159 * Return 1 if capability is supported
4161 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4162 unsigned capability)
4164 u32 port_offset, port_count;
4167 for (i = 0; i < xhci->num_ext_caps; i++) {
4168 if (xhci->ext_caps[i] & capability) {
4169 /* port offsets starts at 1 */
4170 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4171 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4172 if (port >= port_offset &&
4173 port < port_offset + port_count)
4180 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4182 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4183 int portnum = udev->portnum - 1;
4185 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4189 /* we only support lpm for non-hub device connected to root hub yet */
4190 if (!udev->parent || udev->parent->parent ||
4191 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4194 if (xhci->hw_lpm_support == 1 &&
4195 xhci_check_usb2_port_capability(
4196 xhci, portnum, XHCI_HLC)) {
4197 udev->usb2_hw_lpm_capable = 1;
4198 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4199 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4200 if (xhci_check_usb2_port_capability(xhci, portnum,
4202 udev->usb2_hw_lpm_besl_capable = 1;
4208 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4210 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4211 static unsigned long long xhci_service_interval_to_ns(
4212 struct usb_endpoint_descriptor *desc)
4214 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4217 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4218 enum usb3_link_state state)
4220 unsigned long long sel;
4221 unsigned long long pel;
4222 unsigned int max_sel_pel;
4227 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4228 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4229 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4230 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4234 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4235 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4236 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4240 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4242 return USB3_LPM_DISABLED;
4245 if (sel <= max_sel_pel && pel <= max_sel_pel)
4246 return USB3_LPM_DEVICE_INITIATED;
4248 if (sel > max_sel_pel)
4249 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4250 "due to long SEL %llu ms\n",
4253 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4254 "due to long PEL %llu ms\n",
4256 return USB3_LPM_DISABLED;
4259 /* The U1 timeout should be the maximum of the following values:
4260 * - For control endpoints, U1 system exit latency (SEL) * 3
4261 * - For bulk endpoints, U1 SEL * 5
4262 * - For interrupt endpoints:
4263 * - Notification EPs, U1 SEL * 3
4264 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4265 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4267 static unsigned long long xhci_calculate_intel_u1_timeout(
4268 struct usb_device *udev,
4269 struct usb_endpoint_descriptor *desc)
4271 unsigned long long timeout_ns;
4275 ep_type = usb_endpoint_type(desc);
4277 case USB_ENDPOINT_XFER_CONTROL:
4278 timeout_ns = udev->u1_params.sel * 3;
4280 case USB_ENDPOINT_XFER_BULK:
4281 timeout_ns = udev->u1_params.sel * 5;
4283 case USB_ENDPOINT_XFER_INT:
4284 intr_type = usb_endpoint_interrupt_type(desc);
4285 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4286 timeout_ns = udev->u1_params.sel * 3;
4289 /* Otherwise the calculation is the same as isoc eps */
4290 case USB_ENDPOINT_XFER_ISOC:
4291 timeout_ns = xhci_service_interval_to_ns(desc);
4292 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4293 if (timeout_ns < udev->u1_params.sel * 2)
4294 timeout_ns = udev->u1_params.sel * 2;
4303 /* Returns the hub-encoded U1 timeout value. */
4304 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4305 struct usb_device *udev,
4306 struct usb_endpoint_descriptor *desc)
4308 unsigned long long timeout_ns;
4310 if (xhci->quirks & XHCI_INTEL_HOST)
4311 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4313 timeout_ns = udev->u1_params.sel;
4315 /* The U1 timeout is encoded in 1us intervals.
4316 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4318 if (timeout_ns == USB3_LPM_DISABLED)
4321 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4323 /* If the necessary timeout value is bigger than what we can set in the
4324 * USB 3.0 hub, we have to disable hub-initiated U1.
4326 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4328 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4329 "due to long timeout %llu ms\n", timeout_ns);
4330 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4333 /* The U2 timeout should be the maximum of:
4334 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4335 * - largest bInterval of any active periodic endpoint (to avoid going
4336 * into lower power link states between intervals).
4337 * - the U2 Exit Latency of the device
4339 static unsigned long long xhci_calculate_intel_u2_timeout(
4340 struct usb_device *udev,
4341 struct usb_endpoint_descriptor *desc)
4343 unsigned long long timeout_ns;
4344 unsigned long long u2_del_ns;
4346 timeout_ns = 10 * 1000 * 1000;
4348 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4349 (xhci_service_interval_to_ns(desc) > timeout_ns))
4350 timeout_ns = xhci_service_interval_to_ns(desc);
4352 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4353 if (u2_del_ns > timeout_ns)
4354 timeout_ns = u2_del_ns;
4359 /* Returns the hub-encoded U2 timeout value. */
4360 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4361 struct usb_device *udev,
4362 struct usb_endpoint_descriptor *desc)
4364 unsigned long long timeout_ns;
4366 if (xhci->quirks & XHCI_INTEL_HOST)
4367 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4369 timeout_ns = udev->u2_params.sel;
4371 /* The U2 timeout is encoded in 256us intervals */
4372 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4373 /* If the necessary timeout value is bigger than what we can set in the
4374 * USB 3.0 hub, we have to disable hub-initiated U2.
4376 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4378 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4379 "due to long timeout %llu ms\n", timeout_ns);
4380 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4383 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4384 struct usb_device *udev,
4385 struct usb_endpoint_descriptor *desc,
4386 enum usb3_link_state state,
4389 if (state == USB3_LPM_U1)
4390 return xhci_calculate_u1_timeout(xhci, udev, desc);
4391 else if (state == USB3_LPM_U2)
4392 return xhci_calculate_u2_timeout(xhci, udev, desc);
4394 return USB3_LPM_DISABLED;
4397 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4398 struct usb_device *udev,
4399 struct usb_endpoint_descriptor *desc,
4400 enum usb3_link_state state,
4405 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4406 desc, state, timeout);
4408 /* If we found we can't enable hub-initiated LPM, or
4409 * the U1 or U2 exit latency was too high to allow
4410 * device-initiated LPM as well, just stop searching.
4412 if (alt_timeout == USB3_LPM_DISABLED ||
4413 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4414 *timeout = alt_timeout;
4417 if (alt_timeout > *timeout)
4418 *timeout = alt_timeout;
4422 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4423 struct usb_device *udev,
4424 struct usb_host_interface *alt,
4425 enum usb3_link_state state,
4430 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4431 if (xhci_update_timeout_for_endpoint(xhci, udev,
4432 &alt->endpoint[j].desc, state, timeout))
4439 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4440 enum usb3_link_state state)
4442 struct usb_device *parent;
4443 unsigned int num_hubs;
4445 if (state == USB3_LPM_U2)
4448 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4449 for (parent = udev->parent, num_hubs = 0; parent->parent;
4450 parent = parent->parent)
4456 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4457 " below second-tier hub.\n");
4458 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4459 "to decrease power consumption.\n");
4463 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4464 struct usb_device *udev,
4465 enum usb3_link_state state)
4467 if (xhci->quirks & XHCI_INTEL_HOST)
4468 return xhci_check_intel_tier_policy(udev, state);
4473 /* Returns the U1 or U2 timeout that should be enabled.
4474 * If the tier check or timeout setting functions return with a non-zero exit
4475 * code, that means the timeout value has been finalized and we shouldn't look
4476 * at any more endpoints.
4478 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4479 struct usb_device *udev, enum usb3_link_state state)
4481 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4482 struct usb_host_config *config;
4485 u16 timeout = USB3_LPM_DISABLED;
4487 if (state == USB3_LPM_U1)
4489 else if (state == USB3_LPM_U2)
4492 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4497 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4500 /* Gather some information about the currently installed configuration
4501 * and alternate interface settings.
4503 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4507 config = udev->actconfig;
4511 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4512 struct usb_driver *driver;
4513 struct usb_interface *intf = config->interface[i];
4518 /* Check if any currently bound drivers want hub-initiated LPM
4521 if (intf->dev.driver) {
4522 driver = to_usb_driver(intf->dev.driver);
4523 if (driver && driver->disable_hub_initiated_lpm) {
4524 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4525 "at request of driver %s\n",
4526 state_name, driver->name);
4527 return xhci_get_timeout_no_hub_lpm(udev, state);
4531 /* Not sure how this could happen... */
4532 if (!intf->cur_altsetting)
4535 if (xhci_update_timeout_for_interface(xhci, udev,
4536 intf->cur_altsetting,
4543 static int calculate_max_exit_latency(struct usb_device *udev,
4544 enum usb3_link_state state_changed,
4545 u16 hub_encoded_timeout)
4547 unsigned long long u1_mel_us = 0;
4548 unsigned long long u2_mel_us = 0;
4549 unsigned long long mel_us = 0;
4555 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4556 hub_encoded_timeout == USB3_LPM_DISABLED);
4557 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4558 hub_encoded_timeout == USB3_LPM_DISABLED);
4560 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4561 hub_encoded_timeout != USB3_LPM_DISABLED);
4562 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4563 hub_encoded_timeout != USB3_LPM_DISABLED);
4565 /* If U1 was already enabled and we're not disabling it,
4566 * or we're going to enable U1, account for the U1 max exit latency.
4568 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4570 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4571 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4573 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4575 if (u1_mel_us > u2_mel_us)
4579 /* xHCI host controller max exit latency field is only 16 bits wide. */
4580 if (mel_us > MAX_EXIT) {
4581 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4582 "is too big.\n", mel_us);
4588 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4589 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4590 struct usb_device *udev, enum usb3_link_state state)
4592 struct xhci_hcd *xhci;
4593 u16 hub_encoded_timeout;
4597 xhci = hcd_to_xhci(hcd);
4598 /* The LPM timeout values are pretty host-controller specific, so don't
4599 * enable hub-initiated timeouts unless the vendor has provided
4600 * information about their timeout algorithm.
4602 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4603 !xhci->devs[udev->slot_id])
4604 return USB3_LPM_DISABLED;
4606 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4607 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4609 /* Max Exit Latency is too big, disable LPM. */
4610 hub_encoded_timeout = USB3_LPM_DISABLED;
4614 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4617 return hub_encoded_timeout;
4620 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4621 struct usb_device *udev, enum usb3_link_state state)
4623 struct xhci_hcd *xhci;
4626 xhci = hcd_to_xhci(hcd);
4627 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4628 !xhci->devs[udev->slot_id])
4631 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4632 return xhci_change_max_exit_latency(xhci, udev, mel);
4634 #else /* CONFIG_PM */
4636 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4637 struct usb_device *udev, int enable)
4642 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4647 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4648 struct usb_device *udev, enum usb3_link_state state)
4650 return USB3_LPM_DISABLED;
4653 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4654 struct usb_device *udev, enum usb3_link_state state)
4658 #endif /* CONFIG_PM */
4660 /*-------------------------------------------------------------------------*/
4662 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4663 * internal data structures for the device.
4665 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4666 struct usb_tt *tt, gfp_t mem_flags)
4668 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4669 struct xhci_virt_device *vdev;
4670 struct xhci_command *config_cmd;
4671 struct xhci_input_control_ctx *ctrl_ctx;
4672 struct xhci_slot_ctx *slot_ctx;
4673 unsigned long flags;
4674 unsigned think_time;
4677 /* Ignore root hubs */
4681 vdev = xhci->devs[hdev->slot_id];
4683 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4687 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4691 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4693 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4695 xhci_free_command(xhci, config_cmd);
4699 spin_lock_irqsave(&xhci->lock, flags);
4700 if (hdev->speed == USB_SPEED_HIGH &&
4701 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4702 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4703 xhci_free_command(xhci, config_cmd);
4704 spin_unlock_irqrestore(&xhci->lock, flags);
4708 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4709 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4710 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4711 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4713 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4714 * but it may be already set to 1 when setup an xHCI virtual
4715 * device, so clear it anyway.
4718 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4719 else if (hdev->speed == USB_SPEED_FULL)
4720 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4722 if (xhci->hci_version > 0x95) {
4723 xhci_dbg(xhci, "xHCI version %x needs hub "
4724 "TT think time and number of ports\n",
4725 (unsigned int) xhci->hci_version);
4726 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4727 /* Set TT think time - convert from ns to FS bit times.
4728 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4729 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4731 * xHCI 1.0: this field shall be 0 if the device is not a
4734 think_time = tt->think_time;
4735 if (think_time != 0)
4736 think_time = (think_time / 666) - 1;
4737 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4738 slot_ctx->tt_info |=
4739 cpu_to_le32(TT_THINK_TIME(think_time));
4741 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4742 "TT think time or number of ports\n",
4743 (unsigned int) xhci->hci_version);
4745 slot_ctx->dev_state = 0;
4746 spin_unlock_irqrestore(&xhci->lock, flags);
4748 xhci_dbg(xhci, "Set up %s for hub device.\n",
4749 (xhci->hci_version > 0x95) ?
4750 "configure endpoint" : "evaluate context");
4752 /* Issue and wait for the configure endpoint or
4753 * evaluate context command.
4755 if (xhci->hci_version > 0x95)
4756 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4759 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4762 xhci_free_command(xhci, config_cmd);
4766 static int xhci_get_frame(struct usb_hcd *hcd)
4768 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4769 /* EHCI mods by the periodic size. Why? */
4770 return readl(&xhci->run_regs->microframe_index) >> 3;
4773 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4775 struct xhci_hcd *xhci;
4777 * TODO: Check with DWC3 clients for sysdev according to
4780 struct device *dev = hcd->self.sysdev;
4783 /* Accept arbitrarily long scatter-gather lists */
4784 hcd->self.sg_tablesize = ~0;
4786 /* support to build packet from discontinuous buffers */
4787 hcd->self.no_sg_constraint = 1;
4789 /* XHCI controllers don't stop the ep queue on short packets :| */
4790 hcd->self.no_stop_on_short = 1;
4792 xhci = hcd_to_xhci(hcd);
4794 if (usb_hcd_is_primary_hcd(hcd)) {
4795 xhci->main_hcd = hcd;
4796 /* Mark the first roothub as being USB 2.0.
4797 * The xHCI driver will register the USB 3.0 roothub.
4799 hcd->speed = HCD_USB2;
4800 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4802 * USB 2.0 roothub under xHCI has an integrated TT,
4803 * (rate matching hub) as opposed to having an OHCI/UHCI
4804 * companion controller.
4808 if (xhci->sbrn == 0x31) {
4809 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4810 hcd->speed = HCD_USB31;
4811 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4813 /* xHCI private pointer was set in xhci_pci_probe for the second
4814 * registered roothub.
4819 mutex_init(&xhci->mutex);
4820 xhci->cap_regs = hcd->regs;
4821 xhci->op_regs = hcd->regs +
4822 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4823 xhci->run_regs = hcd->regs +
4824 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4825 /* Cache read-only capability registers */
4826 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4827 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4828 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4829 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4830 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4831 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4832 if (xhci->hci_version > 0x100)
4833 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4834 xhci_print_registers(xhci);
4836 xhci->quirks |= quirks;
4838 get_quirks(dev, xhci);
4840 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4841 * success event after a short transfer. This quirk will ignore such
4844 if (xhci->hci_version > 0x96)
4845 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4847 /* Make sure the HC is halted. */
4848 retval = xhci_halt(xhci);
4852 xhci_dbg(xhci, "Resetting HCD\n");
4853 /* Reset the internal HC memory state and registers. */
4854 retval = xhci_reset(xhci);
4857 xhci_dbg(xhci, "Reset complete\n");
4860 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4861 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4862 * address memory pointers actually. So, this driver clears the AC64
4863 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4864 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4866 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4867 xhci->hcc_params &= ~BIT(0);
4869 /* Set dma_mask and coherent_dma_mask to 64-bits,
4870 * if xHC supports 64-bit addressing */
4871 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4872 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4873 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4874 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4877 * This is to avoid error in cases where a 32-bit USB
4878 * controller is used on a 64-bit capable system.
4880 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4883 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4884 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4887 xhci_dbg(xhci, "Calling HCD init\n");
4888 /* Initialize HCD and host controller data structures. */
4889 retval = xhci_init(hcd);
4892 xhci_dbg(xhci, "Called HCD init\n");
4894 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4895 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4899 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4901 static const struct hc_driver xhci_hc_driver = {
4902 .description = "xhci-hcd",
4903 .product_desc = "xHCI Host Controller",
4904 .hcd_priv_size = sizeof(struct xhci_hcd),
4907 * generic hardware linkage
4910 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4913 * basic lifecycle operations
4915 .reset = NULL, /* set in xhci_init_driver() */
4918 .shutdown = xhci_shutdown,
4921 * managing i/o requests and associated device resources
4923 .urb_enqueue = xhci_urb_enqueue,
4924 .urb_dequeue = xhci_urb_dequeue,
4925 .alloc_dev = xhci_alloc_dev,
4926 .free_dev = xhci_free_dev,
4927 .alloc_streams = xhci_alloc_streams,
4928 .free_streams = xhci_free_streams,
4929 .add_endpoint = xhci_add_endpoint,
4930 .drop_endpoint = xhci_drop_endpoint,
4931 .endpoint_reset = xhci_endpoint_reset,
4932 .check_bandwidth = xhci_check_bandwidth,
4933 .reset_bandwidth = xhci_reset_bandwidth,
4934 .address_device = xhci_address_device,
4935 .enable_device = xhci_enable_device,
4936 .update_hub_device = xhci_update_hub_device,
4937 .reset_device = xhci_discover_or_reset_device,
4940 * scheduling support
4942 .get_frame_number = xhci_get_frame,
4947 .hub_control = xhci_hub_control,
4948 .hub_status_data = xhci_hub_status_data,
4949 .bus_suspend = xhci_bus_suspend,
4950 .bus_resume = xhci_bus_resume,
4953 * call back when device connected and addressed
4955 .update_device = xhci_update_device,
4956 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
4957 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
4958 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
4959 .find_raw_port_number = xhci_find_raw_port_number,
4962 void xhci_init_driver(struct hc_driver *drv,
4963 const struct xhci_driver_overrides *over)
4967 /* Copy the generic table to drv then apply the overrides */
4968 *drv = xhci_hc_driver;
4971 drv->hcd_priv_size += over->extra_priv_size;
4973 drv->reset = over->reset;
4975 drv->start = over->start;
4978 EXPORT_SYMBOL_GPL(xhci_init_driver);
4980 MODULE_DESCRIPTION(DRIVER_DESC);
4981 MODULE_AUTHOR(DRIVER_AUTHOR);
4982 MODULE_LICENSE("GPL");
4984 static int __init xhci_hcd_init(void)
4987 * Check the compiler generated sizes of structures that must be laid
4988 * out in specific ways for hardware access.
4990 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4991 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4992 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4993 /* xhci_device_control has eight fields, and also
4994 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4996 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4997 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4998 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4999 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5000 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5001 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5002 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5011 * If an init function is provided, an exit function must also be provided
5012 * to allow module unload.
5014 static void __exit xhci_hcd_fini(void) { }
5016 module_init(xhci_hcd_init);
5017 module_exit(xhci_hcd_fini);