drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  46
  47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  48         if (!seg->trbs) {
  49                 kfree(seg);
  50                 return NULL;
  51         }
  52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  53                         seg->trbs, (unsigned long long)dma);
  54
  55         memset(seg->trbs, 0, SEGMENT_SIZE);
  56         seg->dma = dma;
  57         seg->next = NULL;
  58
  59         return seg;
  60 }
  61
  62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  63 {
  64         if (!seg)
  65                 return;
  66         if (seg->trbs) {
  67                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  68                                 seg->trbs, (unsigned long long)seg->dma);
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  73         kfree(seg);
  74 }
  75
  76 /*
  77  * Make the prev segment point to the next segment.
  78  *
  79  * Change the last TRB in the prev segment to be a Link TRB which points to the
  80  * DMA address of the next segment.  The caller needs to set any Link TRB
  81  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  82  */
  83 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  84                 struct xhci_segment *next, bool link_trbs)
  85 {
  86         u32 val;
  87
  88         if (!prev || !next)
  89                 return;
  90         prev->next = next;
  91         if (link_trbs) {
  92                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
  93
  94                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  95                 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
  96                 val &= ~TRB_TYPE_BITMASK;
  97                 val |= TRB_TYPE(TRB_LINK);
  98                 /* Always set the chain bit with 0.95 hardware */
  99                 if (xhci_link_trb_quirk(xhci))
 100                         val |= TRB_CHAIN;
 101                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
 102         }
 103         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
 104                         (unsigned long long)prev->dma,
 105                         (unsigned long long)next->dma);
 106 }
 107
 108 /* XXX: Do we need the hcd structure in all these functions? */
 109 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 110 {
 111         struct xhci_segment *seg;
 112         struct xhci_segment *first_seg;
 113
 114         if (!ring || !ring->first_seg)
 115                 return;
 116         first_seg = ring->first_seg;
 117         seg = first_seg->next;
 118         xhci_dbg(xhci, "Freeing ring at %p\n", ring);
 119         while (seg != first_seg) {
 120                 struct xhci_segment *next = seg->next;
 121                 xhci_segment_free(xhci, seg);
 122                 seg = next;
 123         }
 124         xhci_segment_free(xhci, first_seg);
 125         ring->first_seg = NULL;
 126         kfree(ring);
 127 }
 128
 129 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 130 {
 131         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 132         ring->enqueue = ring->first_seg->trbs;
 133         ring->enq_seg = ring->first_seg;
 134         ring->dequeue = ring->enqueue;
 135         ring->deq_seg = ring->first_seg;
 136         /* The ring is initialized to 0. The producer must write 1 to the cycle
 137          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 138          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 139          */
 140         ring->cycle_state = 1;
 141         /* Not necessary for new rings, but needed for re-initialized rings */
 142         ring->enq_updates = 0;
 143         ring->deq_updates = 0;
 144 }
 145
 146 /**
 147  * Create a new ring with zero or more segments.
 148  *
 149  * Link each segment together into a ring.
 150  * Set the end flag and the cycle toggle bit on the last segment.
 151  * See section 4.9.1 and figures 15 and 16.
 152  */
 153 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 154                 unsigned int num_segs, bool link_trbs, gfp_t flags)
 155 {
 156         struct xhci_ring        *ring;
 157         struct xhci_segment     *prev;
 158
 159         ring = kzalloc(sizeof *(ring), flags);
 160         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
 161         if (!ring)
 162                 return NULL;
 163
 164         INIT_LIST_HEAD(&ring->td_list);
 165         if (num_segs == 0)
 166                 return ring;
 167
 168         ring->first_seg = xhci_segment_alloc(xhci, flags);
 169         if (!ring->first_seg)
 170                 goto fail;
 171         num_segs--;
 172
 173         prev = ring->first_seg;
 174         while (num_segs > 0) {
 175                 struct xhci_segment     *next;
 176
 177                 next = xhci_segment_alloc(xhci, flags);
 178                 if (!next)
 179                         goto fail;
 180                 xhci_link_segments(xhci, prev, next, link_trbs);
 181
 182                 prev = next;
 183                 num_segs--;
 184         }
 185         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
 186
 187         if (link_trbs) {
 188                 /* See section 4.9.2.1 and 6.4.4.1 */
 189                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
 190                 xhci_dbg(xhci, "Wrote link toggle flag to"
 191                                 " segment %p (virtual), 0x%llx (DMA)\n",
 192                                 prev, (unsigned long long)prev->dma);
 193         }
 194         xhci_initialize_ring_info(ring);
 195         return ring;
 196
 197 fail:
 198         xhci_ring_free(xhci, ring);
 199         return NULL;
 200 }
 201
 202 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 203                 struct xhci_virt_device *virt_dev,
 204                 unsigned int ep_index)
 205 {
 206         int rings_cached;
 207
 208         rings_cached = virt_dev->num_rings_cached;
 209         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 210                 virt_dev->num_rings_cached++;
 211                 rings_cached = virt_dev->num_rings_cached;
 212                 virt_dev->ring_cache[rings_cached] =
 213                         virt_dev->eps[ep_index].ring;
 214                 xhci_dbg(xhci, "Cached old ring, "
 215                                 "%d ring%s cached\n",
 216                                 rings_cached,
 217                                 (rings_cached > 1) ? "s" : "");
 218         } else {
 219                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 220                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 221                                 "freeing ring\n",
 222                                 virt_dev->num_rings_cached);
 223         }
 224         virt_dev->eps[ep_index].ring = NULL;
 225 }
 226
 227 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 228  * pointers to the beginning of the ring.
 229  */
 230 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 231                 struct xhci_ring *ring)
 232 {
 233         struct xhci_segment     *seg = ring->first_seg;
 234         do {
 235                 memset(seg->trbs, 0,
 236                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 237                 /* All endpoint rings have link TRBs */
 238                 xhci_link_segments(xhci, seg, seg->next, 1);
 239                 seg = seg->next;
 240         } while (seg != ring->first_seg);
 241         xhci_initialize_ring_info(ring);
 242         /* td list should be empty since all URBs have been cancelled,
 243          * but just in case...
 244          */
 245         INIT_LIST_HEAD(&ring->td_list);
 246 }
 247
 248 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 249
 250 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 251                                                     int type, gfp_t flags)
 252 {
 253         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 254         if (!ctx)
 255                 return NULL;
 256
 257         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 258         ctx->type = type;
 259         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 260         if (type == XHCI_CTX_TYPE_INPUT)
 261                 ctx->size += CTX_SIZE(xhci->hcc_params);
 262
 263         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 264         memset(ctx->bytes, 0, ctx->size);
 265         return ctx;
 266 }
 267
 268 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 269                              struct xhci_container_ctx *ctx)
 270 {
 271         if (!ctx)
 272                 return;
 273         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 274         kfree(ctx);
 275 }
 276
 277 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 278                                               struct xhci_container_ctx *ctx)
 279 {
 280         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 281         return (struct xhci_input_control_ctx *)ctx->bytes;
 282 }
 283
 284 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 285                                         struct xhci_container_ctx *ctx)
 286 {
 287         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 288                 return (struct xhci_slot_ctx *)ctx->bytes;
 289
 290         return (struct xhci_slot_ctx *)
 291                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 292 }
 293
 294 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 295                                     struct xhci_container_ctx *ctx,
 296                                     unsigned int ep_index)
 297 {
 298         /* increment ep index by offset of start of ep ctx array */
 299         ep_index++;
 300         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 301                 ep_index++;
 302
 303         return (struct xhci_ep_ctx *)
 304                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 305 }
 306
 307
 308 /***************** Streams structures manipulation *************************/
 309
 310 void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 311                 unsigned int num_stream_ctxs,
 312                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 313 {
 314         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 315
 316         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 317                 pci_free_consistent(pdev,
 318                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 319                                 stream_ctx, dma);
 320         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 321                 return dma_pool_free(xhci->small_streams_pool,
 322                                 stream_ctx, dma);
 323         else
 324                 return dma_pool_free(xhci->medium_streams_pool,
 325                                 stream_ctx, dma);
 326 }
 327
 328 /*
 329  * The stream context array for each endpoint with bulk streams enabled can
 330  * vary in size, based on:
 331  *  - how many streams the endpoint supports,
 332  *  - the maximum primary stream array size the host controller supports,
 333  *  - and how many streams the device driver asks for.
 334  *
 335  * The stream context array must be a power of 2, and can be as small as
 336  * 64 bytes or as large as 1MB.
 337  */
 338 struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 339                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 340                 gfp_t mem_flags)
 341 {
 342         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 343
 344         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 345                 return pci_alloc_consistent(pdev,
 346                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 347                                 dma);
 348         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 349                 return dma_pool_alloc(xhci->small_streams_pool,
 350                                 mem_flags, dma);
 351         else
 352                 return dma_pool_alloc(xhci->medium_streams_pool,
 353                                 mem_flags, dma);
 354 }
 355
 356 struct xhci_ring *xhci_dma_to_transfer_ring(
 357                 struct xhci_virt_ep *ep,
 358                 u64 address)
 359 {
 360         if (ep->ep_state & EP_HAS_STREAMS)
 361                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 362                                 address >> SEGMENT_SHIFT);
 363         return ep->ring;
 364 }
 365
 366 /* Only use this when you know stream_info is valid */
 367 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 368 static struct xhci_ring *dma_to_stream_ring(
 369                 struct xhci_stream_info *stream_info,
 370                 u64 address)
 371 {
 372         return radix_tree_lookup(&stream_info->trb_address_map,
 373                         address >> SEGMENT_SHIFT);
 374 }
 375 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 376
 377 struct xhci_ring *xhci_stream_id_to_ring(
 378                 struct xhci_virt_device *dev,
 379                 unsigned int ep_index,
 380                 unsigned int stream_id)
 381 {
 382         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 383
 384         if (stream_id == 0)
 385                 return ep->ring;
 386         if (!ep->stream_info)
 387                 return NULL;
 388
 389         if (stream_id > ep->stream_info->num_streams)
 390                 return NULL;
 391         return ep->stream_info->stream_rings[stream_id];
 392 }
 393
 394 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 395 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 396                 unsigned int num_streams,
 397                 struct xhci_stream_info *stream_info)
 398 {
 399         u32 cur_stream;
 400         struct xhci_ring *cur_ring;
 401         u64 addr;
 402
 403         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 404                 struct xhci_ring *mapped_ring;
 405                 int trb_size = sizeof(union xhci_trb);
 406
 407                 cur_ring = stream_info->stream_rings[cur_stream];
 408                 for (addr = cur_ring->first_seg->dma;
 409                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 410                                 addr += trb_size) {
 411                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 412                         if (cur_ring != mapped_ring) {
 413                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 414                                                 "didn't map to stream ID %u; "
 415                                                 "mapped to ring %p\n",
 416                                                 (unsigned long long) addr,
 417                                                 cur_stream,
 418                                                 mapped_ring);
 419                                 return -EINVAL;
 420                         }
 421                 }
 422                 /* One TRB after the end of the ring segment shouldn't return a
 423                  * pointer to the current ring (although it may be a part of a
 424                  * different ring).
 425                  */
 426                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 427                 if (mapped_ring != cur_ring) {
 428                         /* One TRB before should also fail */
 429                         addr = cur_ring->first_seg->dma - trb_size;
 430                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 431                 }
 432                 if (mapped_ring == cur_ring) {
 433                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 434                                         "mapped to valid stream ID %u; "
 435                                         "mapped ring = %p\n",
 436                                         (unsigned long long) addr,
 437                                         cur_stream,
 438                                         mapped_ring);
 439                         return -EINVAL;
 440                 }
 441         }
 442         return 0;
 443 }
 444 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 445
 446 /*
 447  * Change an endpoint's internal structure so it supports stream IDs.  The
 448  * number of requested streams includes stream 0, which cannot be used by device
 449  * drivers.
 450  *
 451  * The number of stream contexts in the stream context array may be bigger than
 452  * the number of streams the driver wants to use.  This is because the number of
 453  * stream context array entries must be a power of two.
 454  *
 455  * We need a radix tree for mapping physical addresses of TRBs to which stream
 456  * ID they belong to.  We need to do this because the host controller won't tell
 457  * us which stream ring the TRB came from.  We could store the stream ID in an
 458  * event data TRB, but that doesn't help us for the cancellation case, since the
 459  * endpoint may stop before it reaches that event data TRB.
 460  *
 461  * The radix tree maps the upper portion of the TRB DMA address to a ring
 462  * segment that has the same upper portion of DMA addresses.  For example, say I
 463  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 464  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 465  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 466  * pass the radix tree a key to get the right stream ID:
 467  *
 468  *      0x10c90fff >> 10 = 0x43243
 469  *      0x10c912c0 >> 10 = 0x43244
 470  *      0x10c91400 >> 10 = 0x43245
 471  *
 472  * Obviously, only those TRBs with DMA addresses that are within the segment
 473  * will make the radix tree return the stream ID for that ring.
 474  *
 475  * Caveats for the radix tree:
 476  *
 477  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 478  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 479  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 480  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 481  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 482  * extended systems (where the DMA address can be bigger than 32-bits),
 483  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 484  */
 485 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 486                 unsigned int num_stream_ctxs,
 487                 unsigned int num_streams, gfp_t mem_flags)
 488 {
 489         struct xhci_stream_info *stream_info;
 490         u32 cur_stream;
 491         struct xhci_ring *cur_ring;
 492         unsigned long key;
 493         u64 addr;
 494         int ret;
 495
 496         xhci_dbg(xhci, "Allocating %u streams and %u "
 497                         "stream context array entries.\n",
 498                         num_streams, num_stream_ctxs);
 499         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 500                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 501                 return NULL;
 502         }
 503         xhci->cmd_ring_reserved_trbs++;
 504
 505         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 506         if (!stream_info)
 507                 goto cleanup_trbs;
 508
 509         stream_info->num_streams = num_streams;
 510         stream_info->num_stream_ctxs = num_stream_ctxs;
 511
 512         /* Initialize the array of virtual pointers to stream rings. */
 513         stream_info->stream_rings = kzalloc(
 514                         sizeof(struct xhci_ring *)*num_streams,
 515                         mem_flags);
 516         if (!stream_info->stream_rings)
 517                 goto cleanup_info;
 518
 519         /* Initialize the array of DMA addresses for stream rings for the HW. */
 520         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 521                         num_stream_ctxs, &stream_info->ctx_array_dma,
 522                         mem_flags);
 523         if (!stream_info->stream_ctx_array)
 524                 goto cleanup_ctx;
 525         memset(stream_info->stream_ctx_array, 0,
 526                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 527
 528         /* Allocate everything needed to free the stream rings later */
 529         stream_info->free_streams_command =
 530                 xhci_alloc_command(xhci, true, true, mem_flags);
 531         if (!stream_info->free_streams_command)
 532                 goto cleanup_ctx;
 533
 534         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 535
 536         /* Allocate rings for all the streams that the driver will use,
 537          * and add their segment DMA addresses to the radix tree.
 538          * Stream 0 is reserved.
 539          */
 540         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 541                 stream_info->stream_rings[cur_stream] =
 542                         xhci_ring_alloc(xhci, 1, true, mem_flags);
 543                 cur_ring = stream_info->stream_rings[cur_stream];
 544                 if (!cur_ring)
 545                         goto cleanup_rings;
 546                 cur_ring->stream_id = cur_stream;
 547                 /* Set deq ptr, cycle bit, and stream context type */
 548                 addr = cur_ring->first_seg->dma |
 549                         SCT_FOR_CTX(SCT_PRI_TR) |
 550                         cur_ring->cycle_state;
 551                 stream_info->stream_ctx_array[cur_stream].stream_ring = addr;
 552                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 553                                 cur_stream, (unsigned long long) addr);
 554
 555                 key = (unsigned long)
 556                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 557                 ret = radix_tree_insert(&stream_info->trb_address_map,
 558                                 key, cur_ring);
 559                 if (ret) {
 560                         xhci_ring_free(xhci, cur_ring);
 561                         stream_info->stream_rings[cur_stream] = NULL;
 562                         goto cleanup_rings;
 563                 }
 564         }
 565         /* Leave the other unused stream ring pointers in the stream context
 566          * array initialized to zero.  This will cause the xHC to give us an
 567          * error if the device asks for a stream ID we don't have setup (if it
 568          * was any other way, the host controller would assume the ring is
 569          * "empty" and wait forever for data to be queued to that stream ID).
 570          */
 571 #if XHCI_DEBUG
 572         /* Do a little test on the radix tree to make sure it returns the
 573          * correct values.
 574          */
 575         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 576                 goto cleanup_rings;
 577 #endif
 578
 579         return stream_info;
 580
 581 cleanup_rings:
 582         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 583                 cur_ring = stream_info->stream_rings[cur_stream];
 584                 if (cur_ring) {
 585                         addr = cur_ring->first_seg->dma;
 586                         radix_tree_delete(&stream_info->trb_address_map,
 587                                         addr >> SEGMENT_SHIFT);
 588                         xhci_ring_free(xhci, cur_ring);
 589                         stream_info->stream_rings[cur_stream] = NULL;
 590                 }
 591         }
 592         xhci_free_command(xhci, stream_info->free_streams_command);
 593 cleanup_ctx:
 594         kfree(stream_info->stream_rings);
 595 cleanup_info:
 596         kfree(stream_info);
 597 cleanup_trbs:
 598         xhci->cmd_ring_reserved_trbs--;
 599         return NULL;
 600 }
 601 /*
 602  * Sets the MaxPStreams field and the Linear Stream Array field.
 603  * Sets the dequeue pointer to the stream context array.
 604  */
 605 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 606                 struct xhci_ep_ctx *ep_ctx,
 607                 struct xhci_stream_info *stream_info)
 608 {
 609         u32 max_primary_streams;
 610         /* MaxPStreams is the number of stream context array entries, not the
 611          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 612          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 613          */
 614         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 615         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 616                         1 << (max_primary_streams + 1));
 617         ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK;
 618         ep_ctx->ep_info |= EP_MAXPSTREAMS(max_primary_streams);
 619         ep_ctx->ep_info |= EP_HAS_LSA;
 620         ep_ctx->deq  = stream_info->ctx_array_dma;
 621 }
 622
 623 /*
 624  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 625  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 626  * not at the beginning of the ring).
 627  */
 628 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 629                 struct xhci_ep_ctx *ep_ctx,
 630                 struct xhci_virt_ep *ep)
 631 {
 632         dma_addr_t addr;
 633         ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK;
 634         ep_ctx->ep_info &= ~EP_HAS_LSA;
 635         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 636         ep_ctx->deq  = addr | ep->ring->cycle_state;
 637 }
 638
 639 /* Frees all stream contexts associated with the endpoint,
 640  *
 641  * Caller should fix the endpoint context streams fields.
 642  */
 643 void xhci_free_stream_info(struct xhci_hcd *xhci,
 644                 struct xhci_stream_info *stream_info)
 645 {
 646         int cur_stream;
 647         struct xhci_ring *cur_ring;
 648         dma_addr_t addr;
 649
 650         if (!stream_info)
 651                 return;
 652
 653         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 654                         cur_stream++) {
 655                 cur_ring = stream_info->stream_rings[cur_stream];
 656                 if (cur_ring) {
 657                         addr = cur_ring->first_seg->dma;
 658                         radix_tree_delete(&stream_info->trb_address_map,
 659                                         addr >> SEGMENT_SHIFT);
 660                         xhci_ring_free(xhci, cur_ring);
 661                         stream_info->stream_rings[cur_stream] = NULL;
 662                 }
 663         }
 664         xhci_free_command(xhci, stream_info->free_streams_command);
 665         xhci->cmd_ring_reserved_trbs--;
 666         if (stream_info->stream_ctx_array)
 667                 xhci_free_stream_ctx(xhci,
 668                                 stream_info->num_stream_ctxs,
 669                                 stream_info->stream_ctx_array,
 670                                 stream_info->ctx_array_dma);
 671
 672         if (stream_info)
 673                 kfree(stream_info->stream_rings);
 674         kfree(stream_info);
 675 }
 676
 677
 678 /***************** Device context manipulation *************************/
 679
 680 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 681                 struct xhci_virt_ep *ep)
 682 {
 683         init_timer(&ep->stop_cmd_timer);
 684         ep->stop_cmd_timer.data = (unsigned long) ep;
 685         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 686         ep->xhci = xhci;
 687 }
 688
 689 /* All the xhci_tds in the ring's TD list should be freed at this point */
 690 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 691 {
 692         struct xhci_virt_device *dev;
 693         int i;
 694
 695         /* Slot ID 0 is reserved */
 696         if (slot_id == 0 || !xhci->devs[slot_id])
 697                 return;
 698
 699         dev = xhci->devs[slot_id];
 700         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 701         if (!dev)
 702                 return;
 703
 704         for (i = 0; i < 31; ++i) {
 705                 if (dev->eps[i].ring)
 706                         xhci_ring_free(xhci, dev->eps[i].ring);
 707                 if (dev->eps[i].stream_info)
 708                         xhci_free_stream_info(xhci,
 709                                         dev->eps[i].stream_info);
 710         }
 711
 712         if (dev->ring_cache) {
 713                 for (i = 0; i < dev->num_rings_cached; i++)
 714                         xhci_ring_free(xhci, dev->ring_cache[i]);
 715                 kfree(dev->ring_cache);
 716         }
 717
 718         if (dev->in_ctx)
 719                 xhci_free_container_ctx(xhci, dev->in_ctx);
 720         if (dev->out_ctx)
 721                 xhci_free_container_ctx(xhci, dev->out_ctx);
 722
 723         kfree(xhci->devs[slot_id]);
 724         xhci->devs[slot_id] = NULL;
 725 }
 726
 727 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 728                 struct usb_device *udev, gfp_t flags)
 729 {
 730         struct xhci_virt_device *dev;
 731         int i;
 732
 733         /* Slot ID 0 is reserved */
 734         if (slot_id == 0 || xhci->devs[slot_id]) {
 735                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 736                 return 0;
 737         }
 738
 739         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 740         if (!xhci->devs[slot_id])
 741                 return 0;
 742         dev = xhci->devs[slot_id];
 743
 744         /* Allocate the (output) device context that will be used in the HC. */
 745         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 746         if (!dev->out_ctx)
 747                 goto fail;
 748
 749         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 750                         (unsigned long long)dev->out_ctx->dma);
 751
 752         /* Allocate the (input) device context for address device command */
 753         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 754         if (!dev->in_ctx)
 755                 goto fail;
 756
 757         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 758                         (unsigned long long)dev->in_ctx->dma);
 759
 760         /* Initialize the cancellation list and watchdog timers for each ep */
 761         for (i = 0; i < 31; i++) {
 762                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 763                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 764         }
 765
 766         /* Allocate endpoint 0 ring */
 767         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
 768         if (!dev->eps[0].ring)
 769                 goto fail;
 770
 771         /* Allocate pointers to the ring cache */
 772         dev->ring_cache = kzalloc(
 773                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 774                         flags);
 775         if (!dev->ring_cache)
 776                 goto fail;
 777         dev->num_rings_cached = 0;
 778
 779         init_completion(&dev->cmd_completion);
 780         INIT_LIST_HEAD(&dev->cmd_list);
 781
 782         /* Point to output device context in dcbaa. */
 783         xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
 784         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 785                         slot_id,
 786                         &xhci->dcbaa->dev_context_ptrs[slot_id],
 787                         (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
 788
 789         return 1;
 790 fail:
 791         xhci_free_virt_device(xhci, slot_id);
 792         return 0;
 793 }
 794
 795 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 796                 struct usb_device *udev)
 797 {
 798         struct xhci_virt_device *virt_dev;
 799         struct xhci_ep_ctx      *ep0_ctx;
 800         struct xhci_ring        *ep_ring;
 801
 802         virt_dev = xhci->devs[udev->slot_id];
 803         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 804         ep_ring = virt_dev->eps[0].ring;
 805         /*
 806          * FIXME we don't keep track of the dequeue pointer very well after a
 807          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 808          * host to our enqueue pointer.  This should only be called after a
 809          * configured device has reset, so all control transfers should have
 810          * been completed or cancelled before the reset.
 811          */
 812         ep0_ctx->deq = xhci_trb_virt_to_dma(ep_ring->enq_seg, ep_ring->enqueue);
 813         ep0_ctx->deq |= ep_ring->cycle_state;
 814 }
 815
 816 /* Setup an xHCI virtual device for a Set Address command */
 817 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 818 {
 819         struct xhci_virt_device *dev;
 820         struct xhci_ep_ctx      *ep0_ctx;
 821         struct usb_device       *top_dev;
 822         struct xhci_slot_ctx    *slot_ctx;
 823         struct xhci_input_control_ctx *ctrl_ctx;
 824
 825         dev = xhci->devs[udev->slot_id];
 826         /* Slot ID 0 is reserved */
 827         if (udev->slot_id == 0 || !dev) {
 828                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 829                                 udev->slot_id);
 830                 return -EINVAL;
 831         }
 832         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 833         ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
 834         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 835
 836         /* 2) New slot context and endpoint 0 context are valid*/
 837         ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
 838
 839         /* 3) Only the control endpoint is valid - one endpoint context */
 840         slot_ctx->dev_info |= LAST_CTX(1);
 841
 842         slot_ctx->dev_info |= (u32) udev->route;
 843         switch (udev->speed) {
 844         case USB_SPEED_SUPER:
 845                 slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
 846                 break;
 847         case USB_SPEED_HIGH:
 848                 slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
 849                 break;
 850         case USB_SPEED_FULL:
 851                 slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
 852                 break;
 853         case USB_SPEED_LOW:
 854                 slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
 855                 break;
 856         case USB_SPEED_WIRELESS:
 857                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 858                 return -EINVAL;
 859                 break;
 860         default:
 861                 /* Speed was set earlier, this shouldn't happen. */
 862                 BUG();
 863         }
 864         /* Find the root hub port this device is under */
 865         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 866                         top_dev = top_dev->parent)
 867                 /* Found device below root hub */;
 868         slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
 869         xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
 870
 871         /* Is this a LS/FS device under a HS hub? */
 872         if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
 873                         udev->tt) {
 874                 slot_ctx->tt_info = udev->tt->hub->slot_id;
 875                 slot_ctx->tt_info |= udev->ttport << 8;
 876                 if (udev->tt->multi)
 877                         slot_ctx->dev_info |= DEV_MTT;
 878         }
 879         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
 880         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
 881
 882         /* Step 4 - ring already allocated */
 883         /* Step 5 */
 884         ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
 885         /*
 886          * XXX: Not sure about wireless USB devices.
 887          */
 888         switch (udev->speed) {
 889         case USB_SPEED_SUPER:
 890                 ep0_ctx->ep_info2 |= MAX_PACKET(512);
 891                 break;
 892         case USB_SPEED_HIGH:
 893         /* USB core guesses at a 64-byte max packet first for FS devices */
 894         case USB_SPEED_FULL:
 895                 ep0_ctx->ep_info2 |= MAX_PACKET(64);
 896                 break;
 897         case USB_SPEED_LOW:
 898                 ep0_ctx->ep_info2 |= MAX_PACKET(8);
 899                 break;
 900         case USB_SPEED_WIRELESS:
 901                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 902                 return -EINVAL;
 903                 break;
 904         default:
 905                 /* New speed? */
 906                 BUG();
 907         }
 908         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
 909         ep0_ctx->ep_info2 |= MAX_BURST(0);
 910         ep0_ctx->ep_info2 |= ERROR_COUNT(3);
 911
 912         ep0_ctx->deq =
 913                 dev->eps[0].ring->first_seg->dma;
 914         ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
 915
 916         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
 917
 918         return 0;
 919 }
 920
 921 /* Return the polling or NAK interval.
 922  *
 923  * The polling interval is expressed in "microframes".  If xHCI's Interval field
 924  * is set to N, it will service the endpoint every 2^(Interval)*125us.
 925  *
 926  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
 927  * is set to 0.
 928  */
 929 static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
 930                 struct usb_host_endpoint *ep)
 931 {
 932         unsigned int interval = 0;
 933
 934         switch (udev->speed) {
 935         case USB_SPEED_HIGH:
 936                 /* Max NAK rate */
 937                 if (usb_endpoint_xfer_control(&ep->desc) ||
 938                                 usb_endpoint_xfer_bulk(&ep->desc))
 939                         interval = ep->desc.bInterval;
 940                 /* Fall through - SS and HS isoc/int have same decoding */
 941         case USB_SPEED_SUPER:
 942                 if (usb_endpoint_xfer_int(&ep->desc) ||
 943                                 usb_endpoint_xfer_isoc(&ep->desc)) {
 944                         if (ep->desc.bInterval == 0)
 945                                 interval = 0;
 946                         else
 947                                 interval = ep->desc.bInterval - 1;
 948                         if (interval > 15)
 949                                 interval = 15;
 950                         if (interval != ep->desc.bInterval + 1)
 951                                 dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
 952                                                 ep->desc.bEndpointAddress, 1 << interval);
 953                 }
 954                 break;
 955         /* Convert bInterval (in 1-255 frames) to microframes and round down to
 956          * nearest power of 2.
 957          */
 958         case USB_SPEED_FULL:
 959         case USB_SPEED_LOW:
 960                 if (usb_endpoint_xfer_int(&ep->desc) ||
 961                                 usb_endpoint_xfer_isoc(&ep->desc)) {
 962                         interval = fls(8*ep->desc.bInterval) - 1;
 963                         if (interval > 10)
 964                                 interval = 10;
 965                         if (interval < 3)
 966                                 interval = 3;
 967                         if ((1 << interval) != 8*ep->desc.bInterval)
 968                                 dev_warn(&udev->dev,
 969                                                 "ep %#x - rounding interval"
 970                                                 " to %d microframes, "
 971                                                 "ep desc says %d microframes\n",
 972                                                 ep->desc.bEndpointAddress,
 973                                                 1 << interval,
 974                                                 8*ep->desc.bInterval);
 975                 }
 976                 break;
 977         default:
 978                 BUG();
 979         }
 980         return EP_INTERVAL(interval);
 981 }
 982
 983 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
 984  * High speed endpoint descriptors can define "the number of additional
 985  * transaction opportunities per microframe", but that goes in the Max Burst
 986  * endpoint context field.
 987  */
 988 static inline u32 xhci_get_endpoint_mult(struct usb_device *udev,
 989                 struct usb_host_endpoint *ep)
 990 {
 991         if (udev->speed != USB_SPEED_SUPER ||
 992                         !usb_endpoint_xfer_isoc(&ep->desc))
 993                 return 0;
 994         return ep->ss_ep_comp.bmAttributes;
 995 }
 996
 997 static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
 998                 struct usb_host_endpoint *ep)
 999 {
1000         int in;
1001         u32 type;
1002
1003         in = usb_endpoint_dir_in(&ep->desc);
1004         if (usb_endpoint_xfer_control(&ep->desc)) {
1005                 type = EP_TYPE(CTRL_EP);
1006         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1007                 if (in)
1008                         type = EP_TYPE(BULK_IN_EP);
1009                 else
1010                         type = EP_TYPE(BULK_OUT_EP);
1011         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1012                 if (in)
1013                         type = EP_TYPE(ISOC_IN_EP);
1014                 else
1015                         type = EP_TYPE(ISOC_OUT_EP);
1016         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1017                 if (in)
1018                         type = EP_TYPE(INT_IN_EP);
1019                 else
1020                         type = EP_TYPE(INT_OUT_EP);
1021         } else {
1022                 BUG();
1023         }
1024         return type;
1025 }
1026
1027 /* Return the maximum endpoint service interval time (ESIT) payload.
1028  * Basically, this is the maxpacket size, multiplied by the burst size
1029  * and mult size.
1030  */
1031 static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1032                 struct usb_device *udev,
1033                 struct usb_host_endpoint *ep)
1034 {
1035         int max_burst;
1036         int max_packet;
1037
1038         /* Only applies for interrupt or isochronous endpoints */
1039         if (usb_endpoint_xfer_control(&ep->desc) ||
1040                         usb_endpoint_xfer_bulk(&ep->desc))
1041                 return 0;
1042
1043         if (udev->speed == USB_SPEED_SUPER)
1044                 return ep->ss_ep_comp.wBytesPerInterval;
1045
1046         max_packet = ep->desc.wMaxPacketSize & 0x3ff;
1047         max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
1048         /* A 0 in max burst means 1 transfer per ESIT */
1049         return max_packet * (max_burst + 1);
1050 }
1051
1052 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1053  * Drivers will have to call usb_alloc_streams() to do that.
1054  */
1055 int xhci_endpoint_init(struct xhci_hcd *xhci,
1056                 struct xhci_virt_device *virt_dev,
1057                 struct usb_device *udev,
1058                 struct usb_host_endpoint *ep,
1059                 gfp_t mem_flags)
1060 {
1061         unsigned int ep_index;
1062         struct xhci_ep_ctx *ep_ctx;
1063         struct xhci_ring *ep_ring;
1064         unsigned int max_packet;
1065         unsigned int max_burst;
1066         u32 max_esit_payload;
1067
1068         ep_index = xhci_get_endpoint_index(&ep->desc);
1069         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1070
1071         /* Set up the endpoint ring */
1072         /*
1073          * Isochronous endpoint ring needs bigger size because one isoc URB
1074          * carries multiple packets and it will insert multiple tds to the
1075          * ring.
1076          * This should be replaced with dynamic ring resizing in the future.
1077          */
1078         if (usb_endpoint_xfer_isoc(&ep->desc))
1079                 virt_dev->eps[ep_index].new_ring =
1080                         xhci_ring_alloc(xhci, 8, true, mem_flags);
1081         else
1082                 virt_dev->eps[ep_index].new_ring =
1083                         xhci_ring_alloc(xhci, 1, true, mem_flags);
1084         if (!virt_dev->eps[ep_index].new_ring) {
1085                 /* Attempt to use the ring cache */
1086                 if (virt_dev->num_rings_cached == 0)
1087                         return -ENOMEM;
1088                 virt_dev->eps[ep_index].new_ring =
1089                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1090                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1091                 virt_dev->num_rings_cached--;
1092                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
1093         }
1094         virt_dev->eps[ep_index].skip = false;
1095         ep_ring = virt_dev->eps[ep_index].new_ring;
1096         ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
1097
1098         ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
1099         ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep));
1100
1101         /* FIXME dig Mult and streams info out of ep companion desc */
1102
1103         /* Allow 3 retries for everything but isoc;
1104          * error count = 0 means infinite retries.
1105          */
1106         if (!usb_endpoint_xfer_isoc(&ep->desc))
1107                 ep_ctx->ep_info2 = ERROR_COUNT(3);
1108         else
1109                 ep_ctx->ep_info2 = ERROR_COUNT(1);
1110
1111         ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
1112
1113         /* Set the max packet size and max burst */
1114         switch (udev->speed) {
1115         case USB_SPEED_SUPER:
1116                 max_packet = ep->desc.wMaxPacketSize;
1117                 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
1118                 /* dig out max burst from ep companion desc */
1119                 max_packet = ep->ss_ep_comp.bMaxBurst;
1120                 if (!max_packet)
1121                         xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n");
1122                 ep_ctx->ep_info2 |= MAX_BURST(max_packet);
1123                 break;
1124         case USB_SPEED_HIGH:
1125                 /* bits 11:12 specify the number of additional transaction
1126                  * opportunities per microframe (USB 2.0, section 9.6.6)
1127                  */
1128                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1129                                 usb_endpoint_xfer_int(&ep->desc)) {
1130                         max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
1131                         ep_ctx->ep_info2 |= MAX_BURST(max_burst);
1132                 }
1133                 /* Fall through */
1134         case USB_SPEED_FULL:
1135         case USB_SPEED_LOW:
1136                 max_packet = ep->desc.wMaxPacketSize & 0x3ff;
1137                 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
1138                 break;
1139         default:
1140                 BUG();
1141         }
1142         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1143         ep_ctx->tx_info = MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload);
1144
1145         /*
1146          * XXX no idea how to calculate the average TRB buffer length for bulk
1147          * endpoints, as the driver gives us no clue how big each scatter gather
1148          * list entry (or buffer) is going to be.
1149          *
1150          * For isochronous and interrupt endpoints, we set it to the max
1151          * available, until we have new API in the USB core to allow drivers to
1152          * declare how much bandwidth they actually need.
1153          *
1154          * Normally, it would be calculated by taking the total of the buffer
1155          * lengths in the TD and then dividing by the number of TRBs in a TD,
1156          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1157          * use Event Data TRBs, and we don't chain in a link TRB on short
1158          * transfers, we're basically dividing by 1.
1159          */
1160         ep_ctx->tx_info |= AVG_TRB_LENGTH_FOR_EP(max_esit_payload);
1161
1162         /* FIXME Debug endpoint context */
1163         return 0;
1164 }
1165
1166 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1167                 struct xhci_virt_device *virt_dev,
1168                 struct usb_host_endpoint *ep)
1169 {
1170         unsigned int ep_index;
1171         struct xhci_ep_ctx *ep_ctx;
1172
1173         ep_index = xhci_get_endpoint_index(&ep->desc);
1174         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1175
1176         ep_ctx->ep_info = 0;
1177         ep_ctx->ep_info2 = 0;
1178         ep_ctx->deq = 0;
1179         ep_ctx->tx_info = 0;
1180         /* Don't free the endpoint ring until the set interface or configuration
1181          * request succeeds.
1182          */
1183 }
1184
1185 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1186  * Useful when you want to change one particular aspect of the endpoint and then
1187  * issue a configure endpoint command.
1188  */
1189 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1190                 struct xhci_container_ctx *in_ctx,
1191                 struct xhci_container_ctx *out_ctx,
1192                 unsigned int ep_index)
1193 {
1194         struct xhci_ep_ctx *out_ep_ctx;
1195         struct xhci_ep_ctx *in_ep_ctx;
1196
1197         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1198         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1199
1200         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1201         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1202         in_ep_ctx->deq = out_ep_ctx->deq;
1203         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1204 }
1205
1206 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1207  * Useful when you want to change one particular aspect of the endpoint and then
1208  * issue a configure endpoint command.  Only the context entries field matters,
1209  * but we'll copy the whole thing anyway.
1210  */
1211 void xhci_slot_copy(struct xhci_hcd *xhci,
1212                 struct xhci_container_ctx *in_ctx,
1213                 struct xhci_container_ctx *out_ctx)
1214 {
1215         struct xhci_slot_ctx *in_slot_ctx;
1216         struct xhci_slot_ctx *out_slot_ctx;
1217
1218         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1219         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1220
1221         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1222         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1223         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1224         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1225 }
1226
1227 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1228 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1229 {
1230         int i;
1231         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1232         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1233
1234         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1235
1236         if (!num_sp)
1237                 return 0;
1238
1239         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1240         if (!xhci->scratchpad)
1241                 goto fail_sp;
1242
1243         xhci->scratchpad->sp_array =
1244                 pci_alloc_consistent(to_pci_dev(dev),
1245                                      num_sp * sizeof(u64),
1246                                      &xhci->scratchpad->sp_dma);
1247         if (!xhci->scratchpad->sp_array)
1248                 goto fail_sp2;
1249
1250         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1251         if (!xhci->scratchpad->sp_buffers)
1252                 goto fail_sp3;
1253
1254         xhci->scratchpad->sp_dma_buffers =
1255                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1256
1257         if (!xhci->scratchpad->sp_dma_buffers)
1258                 goto fail_sp4;
1259
1260         xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
1261         for (i = 0; i < num_sp; i++) {
1262                 dma_addr_t dma;
1263                 void *buf = pci_alloc_consistent(to_pci_dev(dev),
1264                                                  xhci->page_size, &dma);
1265                 if (!buf)
1266                         goto fail_sp5;
1267
1268                 xhci->scratchpad->sp_array[i] = dma;
1269                 xhci->scratchpad->sp_buffers[i] = buf;
1270                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1271         }
1272
1273         return 0;
1274
1275  fail_sp5:
1276         for (i = i - 1; i >= 0; i--) {
1277                 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
1278                                     xhci->scratchpad->sp_buffers[i],
1279                                     xhci->scratchpad->sp_dma_buffers[i]);
1280         }
1281         kfree(xhci->scratchpad->sp_dma_buffers);
1282
1283  fail_sp4:
1284         kfree(xhci->scratchpad->sp_buffers);
1285
1286  fail_sp3:
1287         pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
1288                             xhci->scratchpad->sp_array,
1289                             xhci->scratchpad->sp_dma);
1290
1291  fail_sp2:
1292         kfree(xhci->scratchpad);
1293         xhci->scratchpad = NULL;
1294
1295  fail_sp:
1296         return -ENOMEM;
1297 }
1298
1299 static void scratchpad_free(struct xhci_hcd *xhci)
1300 {
1301         int num_sp;
1302         int i;
1303         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1304
1305         if (!xhci->scratchpad)
1306                 return;
1307
1308         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1309
1310         for (i = 0; i < num_sp; i++) {
1311                 pci_free_consistent(pdev, xhci->page_size,
1312                                     xhci->scratchpad->sp_buffers[i],
1313                                     xhci->scratchpad->sp_dma_buffers[i]);
1314         }
1315         kfree(xhci->scratchpad->sp_dma_buffers);
1316         kfree(xhci->scratchpad->sp_buffers);
1317         pci_free_consistent(pdev, num_sp * sizeof(u64),
1318                             xhci->scratchpad->sp_array,
1319                             xhci->scratchpad->sp_dma);
1320         kfree(xhci->scratchpad);
1321         xhci->scratchpad = NULL;
1322 }
1323
1324 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1325                 bool allocate_in_ctx, bool allocate_completion,
1326                 gfp_t mem_flags)
1327 {
1328         struct xhci_command *command;
1329
1330         command = kzalloc(sizeof(*command), mem_flags);
1331         if (!command)
1332                 return NULL;
1333
1334         if (allocate_in_ctx) {
1335                 command->in_ctx =
1336                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1337                                         mem_flags);
1338                 if (!command->in_ctx) {
1339                         kfree(command);
1340                         return NULL;
1341                 }
1342         }
1343
1344         if (allocate_completion) {
1345                 command->completion =
1346                         kzalloc(sizeof(struct completion), mem_flags);
1347                 if (!command->completion) {
1348                         xhci_free_container_ctx(xhci, command->in_ctx);
1349                         kfree(command);
1350                         return NULL;
1351                 }
1352                 init_completion(command->completion);
1353         }
1354
1355         command->status = 0;
1356         INIT_LIST_HEAD(&command->cmd_list);
1357         return command;
1358 }
1359
1360 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1361 {
1362         int last;
1363
1364         if (!urb_priv)
1365                 return;
1366
1367         last = urb_priv->length - 1;
1368         if (last >= 0) {
1369                 int     i;
1370                 for (i = 0; i <= last; i++)
1371                         kfree(urb_priv->td[i]);
1372         }
1373         kfree(urb_priv);
1374 }
1375
1376 void xhci_free_command(struct xhci_hcd *xhci,
1377                 struct xhci_command *command)
1378 {
1379         xhci_free_container_ctx(xhci,
1380                         command->in_ctx);
1381         kfree(command->completion);
1382         kfree(command);
1383 }
1384
1385 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1386 {
1387         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1388         int size;
1389         int i;
1390
1391         /* Free the Event Ring Segment Table and the actual Event Ring */
1392         if (xhci->ir_set) {
1393                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1394                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1395                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1396         }
1397         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1398         if (xhci->erst.entries)
1399                 pci_free_consistent(pdev, size,
1400                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1401         xhci->erst.entries = NULL;
1402         xhci_dbg(xhci, "Freed ERST\n");
1403         if (xhci->event_ring)
1404                 xhci_ring_free(xhci, xhci->event_ring);
1405         xhci->event_ring = NULL;
1406         xhci_dbg(xhci, "Freed event ring\n");
1407
1408         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1409         if (xhci->cmd_ring)
1410                 xhci_ring_free(xhci, xhci->cmd_ring);
1411         xhci->cmd_ring = NULL;
1412         xhci_dbg(xhci, "Freed command ring\n");
1413
1414         for (i = 1; i < MAX_HC_SLOTS; ++i)
1415                 xhci_free_virt_device(xhci, i);
1416
1417         if (xhci->segment_pool)
1418                 dma_pool_destroy(xhci->segment_pool);
1419         xhci->segment_pool = NULL;
1420         xhci_dbg(xhci, "Freed segment pool\n");
1421
1422         if (xhci->device_pool)
1423                 dma_pool_destroy(xhci->device_pool);
1424         xhci->device_pool = NULL;
1425         xhci_dbg(xhci, "Freed device context pool\n");
1426
1427         if (xhci->small_streams_pool)
1428                 dma_pool_destroy(xhci->small_streams_pool);
1429         xhci->small_streams_pool = NULL;
1430         xhci_dbg(xhci, "Freed small stream array pool\n");
1431
1432         if (xhci->medium_streams_pool)
1433                 dma_pool_destroy(xhci->medium_streams_pool);
1434         xhci->medium_streams_pool = NULL;
1435         xhci_dbg(xhci, "Freed medium stream array pool\n");
1436
1437         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1438         if (xhci->dcbaa)
1439                 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
1440                                 xhci->dcbaa, xhci->dcbaa->dma);
1441         xhci->dcbaa = NULL;
1442
1443         scratchpad_free(xhci);
1444         xhci->page_size = 0;
1445         xhci->page_shift = 0;
1446 }
1447
1448 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1449                 struct xhci_segment *input_seg,
1450                 union xhci_trb *start_trb,
1451                 union xhci_trb *end_trb,
1452                 dma_addr_t input_dma,
1453                 struct xhci_segment *result_seg,
1454                 char *test_name, int test_number)
1455 {
1456         unsigned long long start_dma;
1457         unsigned long long end_dma;
1458         struct xhci_segment *seg;
1459
1460         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1461         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1462
1463         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1464         if (seg != result_seg) {
1465                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1466                                 test_name, test_number);
1467                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1468                                 "input DMA 0x%llx\n",
1469                                 input_seg,
1470                                 (unsigned long long) input_dma);
1471                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1472                                 "ending TRB %p (0x%llx DMA)\n",
1473                                 start_trb, start_dma,
1474                                 end_trb, end_dma);
1475                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1476                                 result_seg, seg);
1477                 return -1;
1478         }
1479         return 0;
1480 }
1481
1482 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1483 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1484 {
1485         struct {
1486                 dma_addr_t              input_dma;
1487                 struct xhci_segment     *result_seg;
1488         } simple_test_vector [] = {
1489                 /* A zeroed DMA field should fail */
1490                 { 0, NULL },
1491                 /* One TRB before the ring start should fail */
1492                 { xhci->event_ring->first_seg->dma - 16, NULL },
1493                 /* One byte before the ring start should fail */
1494                 { xhci->event_ring->first_seg->dma - 1, NULL },
1495                 /* Starting TRB should succeed */
1496                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1497                 /* Ending TRB should succeed */
1498                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1499                         xhci->event_ring->first_seg },
1500                 /* One byte after the ring end should fail */
1501                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1502                 /* One TRB after the ring end should fail */
1503                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1504                 /* An address of all ones should fail */
1505                 { (dma_addr_t) (~0), NULL },
1506         };
1507         struct {
1508                 struct xhci_segment     *input_seg;
1509                 union xhci_trb          *start_trb;
1510                 union xhci_trb          *end_trb;
1511                 dma_addr_t              input_dma;
1512                 struct xhci_segment     *result_seg;
1513         } complex_test_vector [] = {
1514                 /* Test feeding a valid DMA address from a different ring */
1515                 {       .input_seg = xhci->event_ring->first_seg,
1516                         .start_trb = xhci->event_ring->first_seg->trbs,
1517                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1518                         .input_dma = xhci->cmd_ring->first_seg->dma,
1519                         .result_seg = NULL,
1520                 },
1521                 /* Test feeding a valid end TRB from a different ring */
1522                 {       .input_seg = xhci->event_ring->first_seg,
1523                         .start_trb = xhci->event_ring->first_seg->trbs,
1524                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1525                         .input_dma = xhci->cmd_ring->first_seg->dma,
1526                         .result_seg = NULL,
1527                 },
1528                 /* Test feeding a valid start and end TRB from a different ring */
1529                 {       .input_seg = xhci->event_ring->first_seg,
1530                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1531                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1532                         .input_dma = xhci->cmd_ring->first_seg->dma,
1533                         .result_seg = NULL,
1534                 },
1535                 /* TRB in this ring, but after this TD */
1536                 {       .input_seg = xhci->event_ring->first_seg,
1537                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1538                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1539                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1540                         .result_seg = NULL,
1541                 },
1542                 /* TRB in this ring, but before this TD */
1543                 {       .input_seg = xhci->event_ring->first_seg,
1544                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1545                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1546                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1547                         .result_seg = NULL,
1548                 },
1549                 /* TRB in this ring, but after this wrapped TD */
1550                 {       .input_seg = xhci->event_ring->first_seg,
1551                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1552                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1553                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1554                         .result_seg = NULL,
1555                 },
1556                 /* TRB in this ring, but before this wrapped TD */
1557                 {       .input_seg = xhci->event_ring->first_seg,
1558                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1559                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1560                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1561                         .result_seg = NULL,
1562                 },
1563                 /* TRB not in this ring, and we have a wrapped TD */
1564                 {       .input_seg = xhci->event_ring->first_seg,
1565                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1566                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1567                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1568                         .result_seg = NULL,
1569                 },
1570         };
1571
1572         unsigned int num_tests;
1573         int i, ret;
1574
1575         num_tests = ARRAY_SIZE(simple_test_vector);
1576         for (i = 0; i < num_tests; i++) {
1577                 ret = xhci_test_trb_in_td(xhci,
1578                                 xhci->event_ring->first_seg,
1579                                 xhci->event_ring->first_seg->trbs,
1580                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1581                                 simple_test_vector[i].input_dma,
1582                                 simple_test_vector[i].result_seg,
1583                                 "Simple", i);
1584                 if (ret < 0)
1585                         return ret;
1586         }
1587
1588         num_tests = ARRAY_SIZE(complex_test_vector);
1589         for (i = 0; i < num_tests; i++) {
1590                 ret = xhci_test_trb_in_td(xhci,
1591                                 complex_test_vector[i].input_seg,
1592                                 complex_test_vector[i].start_trb,
1593                                 complex_test_vector[i].end_trb,
1594                                 complex_test_vector[i].input_dma,
1595                                 complex_test_vector[i].result_seg,
1596                                 "Complex", i);
1597                 if (ret < 0)
1598                         return ret;
1599         }
1600         xhci_dbg(xhci, "TRB math tests passed.\n");
1601         return 0;
1602 }
1603
1604 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1605 {
1606         u64 temp;
1607         dma_addr_t deq;
1608
1609         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1610                         xhci->event_ring->dequeue);
1611         if (deq == 0 && !in_interrupt())
1612                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1613                                 "dequeue ptr.\n");
1614         /* Update HC event ring dequeue pointer */
1615         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1616         temp &= ERST_PTR_MASK;
1617         /* Don't clear the EHB bit (which is RW1C) because
1618          * there might be more events to service.
1619          */
1620         temp &= ~ERST_EHB;
1621         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1622                         "preserving EHB bit\n");
1623         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1624                         &xhci->ir_set->erst_dequeue);
1625 }
1626
1627
1628 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
1629 {
1630         dma_addr_t      dma;
1631         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
1632         unsigned int    val, val2;
1633         u64             val_64;
1634         struct xhci_segment     *seg;
1635         u32 page_size;
1636         int i;
1637
1638         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
1639         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
1640         for (i = 0; i < 16; i++) {
1641                 if ((0x1 & page_size) != 0)
1642                         break;
1643                 page_size = page_size >> 1;
1644         }
1645         if (i < 16)
1646                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
1647         else
1648                 xhci_warn(xhci, "WARN: no supported page size\n");
1649         /* Use 4K pages, since that's common and the minimum the HC supports */
1650         xhci->page_shift = 12;
1651         xhci->page_size = 1 << xhci->page_shift;
1652         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
1653
1654         /*
1655          * Program the Number of Device Slots Enabled field in the CONFIG
1656          * register with the max value of slots the HC can handle.
1657          */
1658         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
1659         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
1660                         (unsigned int) val);
1661         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
1662         val |= (val2 & ~HCS_SLOTS_MASK);
1663         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
1664                         (unsigned int) val);
1665         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
1666
1667         /*
1668          * Section 5.4.8 - doorbell array must be
1669          * "physically contiguous and 64-byte (cache line) aligned".
1670          */
1671         xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
1672                         sizeof(*xhci->dcbaa), &dma);
1673         if (!xhci->dcbaa)
1674                 goto fail;
1675         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
1676         xhci->dcbaa->dma = dma;
1677         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
1678                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
1679         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
1680
1681         /*
1682          * Initialize the ring segment pool.  The ring must be a contiguous
1683          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
1684          * however, the command ring segment needs 64-byte aligned segments,
1685          * so we pick the greater alignment need.
1686          */
1687         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
1688                         SEGMENT_SIZE, 64, xhci->page_size);
1689
1690         /* See Table 46 and Note on Figure 55 */
1691         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
1692                         2112, 64, xhci->page_size);
1693         if (!xhci->segment_pool || !xhci->device_pool)
1694                 goto fail;
1695
1696         /* Linear stream context arrays don't have any boundary restrictions,
1697          * and only need to be 16-byte aligned.
1698          */
1699         xhci->small_streams_pool =
1700                 dma_pool_create("xHCI 256 byte stream ctx arrays",
1701                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
1702         xhci->medium_streams_pool =
1703                 dma_pool_create("xHCI 1KB stream ctx arrays",
1704                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
1705         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
1706          * will be allocated with pci_alloc_consistent()
1707          */
1708
1709         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
1710                 goto fail;
1711
1712         /* Set up the command ring to have one segments for now. */
1713         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
1714         if (!xhci->cmd_ring)
1715                 goto fail;
1716         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
1717         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
1718                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
1719
1720         /* Set the address in the Command Ring Control register */
1721         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1722         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
1723                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
1724                 xhci->cmd_ring->cycle_state;
1725         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
1726         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
1727         xhci_dbg_cmd_ptrs(xhci);
1728
1729         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
1730         val &= DBOFF_MASK;
1731         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
1732                         " from cap regs base addr\n", val);
1733         xhci->dba = (void *) xhci->cap_regs + val;
1734         xhci_dbg_regs(xhci);
1735         xhci_print_run_regs(xhci);
1736         /* Set ir_set to interrupt register set 0 */
1737         xhci->ir_set = (void *) xhci->run_regs->ir_set;
1738
1739         /*
1740          * Event ring setup: Allocate a normal ring, but also setup
1741          * the event ring segment table (ERST).  Section 4.9.3.
1742          */
1743         xhci_dbg(xhci, "// Allocating event ring\n");
1744         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
1745         if (!xhci->event_ring)
1746                 goto fail;
1747         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
1748                 goto fail;
1749
1750         xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
1751                         sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
1752         if (!xhci->erst.entries)
1753                 goto fail;
1754         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
1755                         (unsigned long long)dma);
1756
1757         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
1758         xhci->erst.num_entries = ERST_NUM_SEGS;
1759         xhci->erst.erst_dma_addr = dma;
1760         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
1761                         xhci->erst.num_entries,
1762                         xhci->erst.entries,
1763                         (unsigned long long)xhci->erst.erst_dma_addr);
1764
1765         /* set ring base address and size for each segment table entry */
1766         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
1767                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
1768                 entry->seg_addr = seg->dma;
1769                 entry->seg_size = TRBS_PER_SEGMENT;
1770                 entry->rsvd = 0;
1771                 seg = seg->next;
1772         }
1773
1774         /* set ERST count with the number of entries in the segment table */
1775         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
1776         val &= ERST_SIZE_MASK;
1777         val |= ERST_NUM_SEGS;
1778         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
1779                         val);
1780         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
1781
1782         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
1783         /* set the segment table base address */
1784         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
1785                         (unsigned long long)xhci->erst.erst_dma_addr);
1786         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
1787         val_64 &= ERST_PTR_MASK;
1788         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
1789         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
1790
1791         /* Set the event ring dequeue address */
1792         xhci_set_hc_event_deq(xhci);
1793         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
1794         xhci_print_ir_set(xhci, xhci->ir_set, 0);
1795
1796         /*
1797          * XXX: Might need to set the Interrupter Moderation Register to
1798          * something other than the default (~1ms minimum between interrupts).
1799          * See section 5.5.1.2.
1800          */
1801         init_completion(&xhci->addr_dev);
1802         for (i = 0; i < MAX_HC_SLOTS; ++i)
1803                 xhci->devs[i] = NULL;
1804
1805         if (scratchpad_alloc(xhci, flags))
1806                 goto fail;
1807
1808         return 0;
1809
1810 fail:
1811         xhci_warn(xhci, "Couldn't initialize memory\n");
1812         xhci_mem_cleanup(xhci);
1813         return -ENOMEM;
1814 }